rt2x00: Removed unused descriptor read in txdone
[deliverable/linux.git] / drivers / net / wireless / rt2x00 / rt2x00reg.h
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95ea3627 1/*
811aa9ca 2 Copyright (C) 2004 - 2008 rt2x00 SourceForge Project
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3 <http://rt2x00.serialmonkey.com>
4
5 This program is free software; you can redistribute it and/or modify
6 it under the terms of the GNU General Public License as published by
7 the Free Software Foundation; either version 2 of the License, or
8 (at your option) any later version.
9
10 This program is distributed in the hope that it will be useful,
11 but WITHOUT ANY WARRANTY; without even the implied warranty of
12 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 GNU General Public License for more details.
14
15 You should have received a copy of the GNU General Public License
16 along with this program; if not, write to the
17 Free Software Foundation, Inc.,
18 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
19 */
20
21/*
22 Module: rt2x00
23 Abstract: rt2x00 generic register information.
24 */
25
26#ifndef RT2X00REG_H
27#define RT2X00REG_H
28
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29/*
30 * Antenna values
31 */
32enum antenna {
33 ANTENNA_SW_DIVERSITY = 0,
34 ANTENNA_A = 1,
35 ANTENNA_B = 2,
36 ANTENNA_HW_DIVERSITY = 3,
37};
38
39/*
40 * Led mode values.
41 */
42enum led_mode {
43 LED_MODE_DEFAULT = 0,
44 LED_MODE_TXRX_ACTIVITY = 1,
45 LED_MODE_SIGNAL_STRENGTH = 2,
46 LED_MODE_ASUS = 3,
47 LED_MODE_ALPHA = 4,
48};
49
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50/*
51 * TSF sync values
52 */
53enum tsf_sync {
54 TSF_SYNC_NONE = 0,
55 TSF_SYNC_INFRA = 1,
56 TSF_SYNC_BEACON = 2,
57};
58
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59/*
60 * Device states
61 */
62enum dev_state {
63 STATE_DEEP_SLEEP = 0,
64 STATE_SLEEP = 1,
65 STATE_STANDBY = 2,
66 STATE_AWAKE = 3,
67
68/*
69 * Additional device states, these values are
70 * not strict since they are not directly passed
71 * into the device.
72 */
73 STATE_RADIO_ON,
74 STATE_RADIO_OFF,
75 STATE_RADIO_RX_ON,
76 STATE_RADIO_RX_OFF,
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77 STATE_RADIO_RX_ON_LINK,
78 STATE_RADIO_RX_OFF_LINK,
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79 STATE_RADIO_IRQ_ON,
80 STATE_RADIO_IRQ_OFF,
81};
82
83/*
84 * IFS backoff values
85 */
86enum ifs {
87 IFS_BACKOFF = 0,
88 IFS_SIFS = 1,
89 IFS_NEW_BACKOFF = 2,
90 IFS_NONE = 3,
91};
92
93/*
94 * Cipher types for hardware encryption
95 */
96enum cipher {
97 CIPHER_NONE = 0,
98 CIPHER_WEP64 = 1,
99 CIPHER_WEP128 = 2,
100 CIPHER_TKIP = 3,
101 CIPHER_AES = 4,
102/*
103 * The following fields were added by rt61pci and rt73usb.
104 */
105 CIPHER_CKIP64 = 5,
106 CIPHER_CKIP128 = 6,
107 CIPHER_TKIP_NO_MIC = 7,
108};
109
110/*
111 * Register handlers.
112 * We store the position of a register field inside a field structure,
113 * This will simplify the process of setting and reading a certain field
114 * inside the register while making sure the process remains byte order safe.
115 */
116struct rt2x00_field8 {
117 u8 bit_offset;
118 u8 bit_mask;
119};
120
121struct rt2x00_field16 {
122 u16 bit_offset;
123 u16 bit_mask;
124};
125
126struct rt2x00_field32 {
127 u32 bit_offset;
128 u32 bit_mask;
129};
130
131/*
132 * Power of two check, this will check
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133 * if the mask that has been given contains and contiguous set of bits.
134 * Note that we cannot use the is_power_of_2() function since this
135 * check must be done at compile-time.
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136 */
137#define is_power_of_two(x) ( !((x) & ((x)-1)) )
138#define low_bit_mask(x) ( ((x)-1) & ~(x) )
139#define is_valid_mask(x) is_power_of_two(1 + (x) + low_bit_mask(x))
140
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141/*
142 * Macro's to find first set bit in a variable.
143 * These macro's behaves the same as the __ffs() function with
144 * the most important difference that this is done during
145 * compile-time rather then run-time.
146 */
147#define compile_ffs2(__x) \
148 ( ((__x) & 0x1) ? 0 : 1 )
149
150#define compile_ffs4(__x) \
151 ( ((__x) & 0x3) ? \
152 compile_ffs2(__x) : (compile_ffs2((__x) >> 2) + 2) )
153
154#define compile_ffs8(__x) \
155 ( ((__x) & 0xf) ? \
156 compile_ffs4(__x) : (compile_ffs4((__x) >> 4) + 4) )
157
158#define compile_ffs16(__x) \
159 ( ((__x) & 0xff) ? \
160 compile_ffs8(__x) : (compile_ffs8((__x) >> 8) + 8) )
161
162#define compile_ffs32(__x) \
163 ( ((__x) & 0xffff) ? \
164 compile_ffs16(__x) : (compile_ffs16((__x) >> 16) + 16) )
165
166/*
167 * This macro will check the requirements for the FIELD{8,16,32} macros
168 * The mask should be a constant non-zero contiguous set of bits which
169 * does not exceed the given typelimit.
170 */
171#define FIELD_CHECK(__mask, __type) \
172 BUILD_BUG_ON(!__builtin_constant_p(__mask) || \
173 !(__mask) || \
174 !is_valid_mask(__mask) || \
175 (__mask) != (__type)(__mask)) \
176
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177#define FIELD8(__mask) \
178({ \
9dad92b9 179 FIELD_CHECK(__mask, u8); \
95ea3627 180 (struct rt2x00_field8) { \
9dad92b9 181 compile_ffs8(__mask), (__mask) \
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182 }; \
183})
184
185#define FIELD16(__mask) \
186({ \
9dad92b9 187 FIELD_CHECK(__mask, u16); \
95ea3627 188 (struct rt2x00_field16) { \
9dad92b9 189 compile_ffs16(__mask), (__mask) \
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190 }; \
191})
192
193#define FIELD32(__mask) \
194({ \
9dad92b9 195 FIELD_CHECK(__mask, u32); \
95ea3627 196 (struct rt2x00_field32) { \
9dad92b9 197 compile_ffs32(__mask), (__mask) \
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198 }; \
199})
200
201static inline void rt2x00_set_field32(u32 *reg,
202 const struct rt2x00_field32 field,
203 const u32 value)
204{
205 *reg &= ~(field.bit_mask);
206 *reg |= (value << field.bit_offset) & field.bit_mask;
207}
208
209static inline u32 rt2x00_get_field32(const u32 reg,
210 const struct rt2x00_field32 field)
211{
212 return (reg & field.bit_mask) >> field.bit_offset;
213}
214
215static inline void rt2x00_set_field16(u16 *reg,
216 const struct rt2x00_field16 field,
217 const u16 value)
218{
219 *reg &= ~(field.bit_mask);
220 *reg |= (value << field.bit_offset) & field.bit_mask;
221}
222
223static inline u16 rt2x00_get_field16(const u16 reg,
224 const struct rt2x00_field16 field)
225{
226 return (reg & field.bit_mask) >> field.bit_offset;
227}
228
229static inline void rt2x00_set_field8(u8 *reg,
230 const struct rt2x00_field8 field,
231 const u8 value)
232{
233 *reg &= ~(field.bit_mask);
234 *reg |= (value << field.bit_offset) & field.bit_mask;
235}
236
237static inline u8 rt2x00_get_field8(const u8 reg,
238 const struct rt2x00_field8 field)
239{
240 return (reg & field.bit_mask) >> field.bit_offset;
241}
242
95ea3627 243#endif /* RT2X00REG_H */
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