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Merge branch 'for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/dtor/input
[deliverable/linux.git] / drivers / net / wireless / rt2x00 / rt61pci.c
CommitLineData
95ea3627 1/*
9c9a0d14 2 Copyright (C) 2004 - 2009 Ivo van Doorn <IvDoorn@gmail.com>
95ea3627
ID		 3 <http://rt2x00.serialmonkey.com>
4
5 This program is free software; you can redistribute it and/or modify
6 it under the terms of the GNU General Public License as published by
7 the Free Software Foundation; either version 2 of the License, or
8 (at your option) any later version.
9
10 This program is distributed in the hope that it will be useful,
11 but WITHOUT ANY WARRANTY; without even the implied warranty of
12 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 GNU General Public License for more details.
14
15 You should have received a copy of the GNU General Public License
16 along with this program; if not, write to the
17 Free Software Foundation, Inc.,
18 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
19 */
20
21/*
22 Module: rt61pci
23 Abstract: rt61pci device specific routines.
24 Supported chipsets: RT2561, RT2561s, RT2661.
25 */
26
a7f3a06c 27#include <linux/crc-itu-t.h>
95ea3627
ID		 28#include <linux/delay.h>
29#include <linux/etherdevice.h>
30#include <linux/init.h>
31#include <linux/kernel.h>
32#include <linux/module.h>
5a0e3ad6 33#include <linux/slab.h>
95ea3627
ID		 34#include <linux/pci.h>
35#include <linux/eeprom_93cx6.h>
36
37#include "rt2x00.h"
69a2bac8 38#include "rt2x00mmio.h"
95ea3627
ID		 39#include "rt2x00pci.h"
40#include "rt61pci.h"
41
008c4482
ID		 42/*
43 * Allow hardware encryption to be disabled.
44 */
eb939922 45static bool modparam_nohwcrypt = false;
008c4482
ID		 46module_param_named(nohwcrypt, modparam_nohwcrypt, bool, S_IRUGO);
47MODULE_PARM_DESC(nohwcrypt, "Disable hardware encryption.");
48
95ea3627
ID		 49/*
50 * Register access.
51 * BBP and RF register require indirect register access,
52 * and use the CSR registers PHY_CSR3 and PHY_CSR4 to achieve this.
53 * These indirect registers work with busy bits,
54 * and we will try maximal REGISTER_BUSY_COUNT times to access
55 * the register while taking a REGISTER_BUSY_DELAY us delay
b34e620f 56 * between each attempt. When the busy bit is still set at that time,
95ea3627
ID		 57 * the access attempt is considered to have failed,
58 * and we will print an error.
59 */
c9c3b1a5 60#define WAIT_FOR_BBP(__dev, __reg) \
1d6205d0 61 rt2x00mmio_regbusy_read((__dev), PHY_CSR3, PHY_CSR3_BUSY, (__reg))
c9c3b1a5 62#define WAIT_FOR_RF(__dev, __reg) \
1d6205d0 63 rt2x00mmio_regbusy_read((__dev), PHY_CSR4, PHY_CSR4_BUSY, (__reg))
c9c3b1a5 64#define WAIT_FOR_MCU(__dev, __reg) \
1d6205d0
GJ		 65 rt2x00mmio_regbusy_read((__dev), H2M_MAILBOX_CSR, \
66 H2M_MAILBOX_CSR_OWNER, (__reg))
95ea3627 67
0e14f6d3 68static void rt61pci_bbp_write(struct rt2x00_dev *rt2x00dev,
95ea3627
ID		 69 const unsigned int word, const u8 value)
70{
71 u32 reg;
72
8ff48a8b
ID		 73 mutex_lock(&rt2x00dev->csr_mutex);
74
95ea3627 75 /*
c9c3b1a5
ID		 76 * Wait until the BBP becomes available, afterwards we
77 * can safely write the new data into the register.
95ea3627 78 */
c9c3b1a5
ID		 79 if (WAIT_FOR_BBP(rt2x00dev, &reg)) {
80 reg = 0;
81 rt2x00_set_field32(&reg, PHY_CSR3_VALUE, value);
82 rt2x00_set_field32(&reg, PHY_CSR3_REGNUM, word);
83 rt2x00_set_field32(&reg, PHY_CSR3_BUSY, 1);
84 rt2x00_set_field32(&reg, PHY_CSR3_READ_CONTROL, 0);
85
1d6205d0 86 rt2x00mmio_register_write(rt2x00dev, PHY_CSR3, reg);
c9c3b1a5 87 }
8ff48a8b 88
8ff48a8b 89 mutex_unlock(&rt2x00dev->csr_mutex);
95ea3627
ID		 90}
91
0e14f6d3 92static void rt61pci_bbp_read(struct rt2x00_dev *rt2x00dev,
95ea3627
ID		 93 const unsigned int word, u8 *value)
94{
95 u32 reg;
96
8ff48a8b
ID		 97 mutex_lock(&rt2x00dev->csr_mutex);
98
95ea3627 99 /*
c9c3b1a5
ID		 100 * Wait until the BBP becomes available, afterwards we
101 * can safely write the read request into the register.
102 * After the data has been written, we wait until hardware
103 * returns the correct value, if at any time the register
104 * doesn't become available in time, reg will be 0xffffffff
105 * which means we return 0xff to the caller.
95ea3627 106 */
c9c3b1a5
ID		 107 if (WAIT_FOR_BBP(rt2x00dev, &reg)) {
108 reg = 0;
109 rt2x00_set_field32(&reg, PHY_CSR3_REGNUM, word);
110 rt2x00_set_field32(&reg, PHY_CSR3_BUSY, 1);
111 rt2x00_set_field32(&reg, PHY_CSR3_READ_CONTROL, 1);
95ea3627 112
1d6205d0 113 rt2x00mmio_register_write(rt2x00dev, PHY_CSR3, reg);
95ea3627 114
c9c3b1a5
ID		 115 WAIT_FOR_BBP(rt2x00dev, &reg);
116 }
95ea3627
ID		 117
118 *value = rt2x00_get_field32(reg, PHY_CSR3_VALUE);
8ff48a8b 119
8ff48a8b 120 mutex_unlock(&rt2x00dev->csr_mutex);
95ea3627
ID		 121}
122
0e14f6d3 123static void rt61pci_rf_write(struct rt2x00_dev *rt2x00dev,
95ea3627
ID		 124 const unsigned int word, const u32 value)
125{
126 u32 reg;
95ea3627 127
8ff48a8b
ID		 128 mutex_lock(&rt2x00dev->csr_mutex);
129
c9c3b1a5
ID		 130 /*
131 * Wait until the RF becomes available, afterwards we
132 * can safely write the new data into the register.
133 */
134 if (WAIT_FOR_RF(rt2x00dev, &reg)) {
135 reg = 0;
136 rt2x00_set_field32(&reg, PHY_CSR4_VALUE, value);
137 rt2x00_set_field32(&reg, PHY_CSR4_NUMBER_OF_BITS, 21);
138 rt2x00_set_field32(&reg, PHY_CSR4_IF_SELECT, 0);
139 rt2x00_set_field32(&reg, PHY_CSR4_BUSY, 1);
140
1d6205d0 141 rt2x00mmio_register_write(rt2x00dev, PHY_CSR4, reg);
c9c3b1a5 142 rt2x00_rf_write(rt2x00dev, word, value);
95ea3627
ID		 143 }
144
8ff48a8b 145 mutex_unlock(&rt2x00dev->csr_mutex);
95ea3627
ID		 146}
147
0e14f6d3 148static void rt61pci_mcu_request(struct rt2x00_dev *rt2x00dev,
95ea3627
ID		 149 const u8 command, const u8 token,
150 const u8 arg0, const u8 arg1)
151{
152 u32 reg;
153
8ff48a8b
ID		 154 mutex_lock(&rt2x00dev->csr_mutex);
155
c9c3b1a5
ID		 156 /*
157 * Wait until the MCU becomes available, afterwards we
158 * can safely write the new data into the register.
159 */
160 if (WAIT_FOR_MCU(rt2x00dev, &reg)) {
161 rt2x00_set_field32(&reg, H2M_MAILBOX_CSR_OWNER, 1);
162 rt2x00_set_field32(&reg, H2M_MAILBOX_CSR_CMD_TOKEN, token);
163 rt2x00_set_field32(&reg, H2M_MAILBOX_CSR_ARG0, arg0);
164 rt2x00_set_field32(&reg, H2M_MAILBOX_CSR_ARG1, arg1);
1d6205d0 165 rt2x00mmio_register_write(rt2x00dev, H2M_MAILBOX_CSR, reg);
c9c3b1a5 166
1d6205d0 167 rt2x00mmio_register_read(rt2x00dev, HOST_CMD_CSR, &reg);
c9c3b1a5
ID		 168 rt2x00_set_field32(&reg, HOST_CMD_CSR_HOST_COMMAND, command);
169 rt2x00_set_field32(&reg, HOST_CMD_CSR_INTERRUPT_MCU, 1);
1d6205d0 170 rt2x00mmio_register_write(rt2x00dev, HOST_CMD_CSR, reg);
c9c3b1a5 171 }
8ff48a8b 172
8ff48a8b
ID		 173 mutex_unlock(&rt2x00dev->csr_mutex);
174
95ea3627
ID		 175}
176
177static void rt61pci_eepromregister_read(struct eeprom_93cx6 *eeprom)
178{
179 struct rt2x00_dev *rt2x00dev = eeprom->data;
180 u32 reg;
181
1d6205d0 182 rt2x00mmio_register_read(rt2x00dev, E2PROM_CSR, &reg);
95ea3627
ID		 183
184 eeprom->reg_data_in = !!rt2x00_get_field32(reg, E2PROM_CSR_DATA_IN);
185 eeprom->reg_data_out = !!rt2x00_get_field32(reg, E2PROM_CSR_DATA_OUT);
186 eeprom->reg_data_clock =
187 !!rt2x00_get_field32(reg, E2PROM_CSR_DATA_CLOCK);
188 eeprom->reg_chip_select =
189 !!rt2x00_get_field32(reg, E2PROM_CSR_CHIP_SELECT);
190}
191
192static void rt61pci_eepromregister_write(struct eeprom_93cx6 *eeprom)
193{
194 struct rt2x00_dev *rt2x00dev = eeprom->data;
195 u32 reg = 0;
196
197 rt2x00_set_field32(&reg, E2PROM_CSR_DATA_IN, !!eeprom->reg_data_in);
198 rt2x00_set_field32(&reg, E2PROM_CSR_DATA_OUT, !!eeprom->reg_data_out);
199 rt2x00_set_field32(&reg, E2PROM_CSR_DATA_CLOCK,
200 !!eeprom->reg_data_clock);
201 rt2x00_set_field32(&reg, E2PROM_CSR_CHIP_SELECT,
202 !!eeprom->reg_chip_select);
203
1d6205d0 204 rt2x00mmio_register_write(rt2x00dev, E2PROM_CSR, reg);
95ea3627
ID		 205}
206
207#ifdef CONFIG_RT2X00_LIB_DEBUGFS
95ea3627
ID		 208static const struct rt2x00debug rt61pci_rt2x00debug = {
209 .owner = THIS_MODULE,
210 .csr = {
1d6205d0
GJ		 211 .read = rt2x00mmio_register_read,
212 .write = rt2x00mmio_register_write,
743b97ca
ID		 213 .flags = RT2X00DEBUGFS_OFFSET,
214 .word_base = CSR_REG_BASE,
95ea3627
ID		 215 .word_size = sizeof(u32),
216 .word_count = CSR_REG_SIZE / sizeof(u32),
217 },
218 .eeprom = {
219 .read = rt2x00_eeprom_read,
220 .write = rt2x00_eeprom_write,
743b97ca 221 .word_base = EEPROM_BASE,
95ea3627
ID		 222 .word_size = sizeof(u16),
223 .word_count = EEPROM_SIZE / sizeof(u16),
224 },
225 .bbp = {
226 .read = rt61pci_bbp_read,
227 .write = rt61pci_bbp_write,
743b97ca 228 .word_base = BBP_BASE,
95ea3627
ID		 229 .word_size = sizeof(u8),
230 .word_count = BBP_SIZE / sizeof(u8),
231 },
232 .rf = {
233 .read = rt2x00_rf_read,
234 .write = rt61pci_rf_write,
743b97ca 235 .word_base = RF_BASE,
95ea3627
ID		 236 .word_size = sizeof(u32),
237 .word_count = RF_SIZE / sizeof(u32),
238 },
239};
240#endif /* CONFIG_RT2X00_LIB_DEBUGFS */
241
95ea3627
ID		 242static int rt61pci_rfkill_poll(struct rt2x00_dev *rt2x00dev)
243{
244 u32 reg;
245
1d6205d0 246 rt2x00mmio_register_read(rt2x00dev, MAC_CSR13, &reg);
99bdf51a 247 return rt2x00_get_field32(reg, MAC_CSR13_VAL5);
95ea3627 248}
95ea3627 249
771fd565 250#ifdef CONFIG_RT2X00_LIB_LEDS
a2e1d52a 251static void rt61pci_brightness_set(struct led_classdev *led_cdev,
a9450b70
ID		 252 enum led_brightness brightness)
253{
254 struct rt2x00_led *led =
255 container_of(led_cdev, struct rt2x00_led, led_dev);
256 unsigned int enabled = brightness != LED_OFF;
257 unsigned int a_mode =
258 (enabled && led->rt2x00dev->curr_band == IEEE80211_BAND_5GHZ);
259 unsigned int bg_mode =
260 (enabled && led->rt2x00dev->curr_band == IEEE80211_BAND_2GHZ);
261
262 if (led->type == LED_TYPE_RADIO) {
263 rt2x00_set_field16(&led->rt2x00dev->led_mcu_reg,
264 MCU_LEDCS_RADIO_STATUS, enabled);
265
266 rt61pci_mcu_request(led->rt2x00dev, MCU_LED, 0xff,
267 (led->rt2x00dev->led_mcu_reg & 0xff),
268 ((led->rt2x00dev->led_mcu_reg >> 8)));
269 } else if (led->type == LED_TYPE_ASSOC) {
270 rt2x00_set_field16(&led->rt2x00dev->led_mcu_reg,
271 MCU_LEDCS_LINK_BG_STATUS, bg_mode);
272 rt2x00_set_field16(&led->rt2x00dev->led_mcu_reg,
273 MCU_LEDCS_LINK_A_STATUS, a_mode);
274
275 rt61pci_mcu_request(led->rt2x00dev, MCU_LED, 0xff,
276 (led->rt2x00dev->led_mcu_reg & 0xff),
277 ((led->rt2x00dev->led_mcu_reg >> 8)));
278 } else if (led->type == LED_TYPE_QUALITY) {
279 /*
280 * The brightness is divided into 6 levels (0 - 5),
281 * this means we need to convert the brightness
282 * argument into the matching level within that range.
283 */
284 rt61pci_mcu_request(led->rt2x00dev, MCU_LED_STRENGTH, 0xff,
285 brightness / (LED_FULL / 6), 0);
286 }
287}
a2e1d52a
ID		 288
289static int rt61pci_blink_set(struct led_classdev *led_cdev,
290 unsigned long *delay_on,
291 unsigned long *delay_off)
292{
293 struct rt2x00_led *led =
294 container_of(led_cdev, struct rt2x00_led, led_dev);
295 u32 reg;
296
1d6205d0 297 rt2x00mmio_register_read(led->rt2x00dev, MAC_CSR14, &reg);
a2e1d52a
ID		 298 rt2x00_set_field32(&reg, MAC_CSR14_ON_PERIOD, *delay_on);
299 rt2x00_set_field32(&reg, MAC_CSR14_OFF_PERIOD, *delay_off);
1d6205d0 300 rt2x00mmio_register_write(led->rt2x00dev, MAC_CSR14, reg);
a2e1d52a
ID		 301
302 return 0;
303}
475433be
ID		 304
305static void rt61pci_init_led(struct rt2x00_dev *rt2x00dev,
306 struct rt2x00_led *led,
307 enum led_type type)
308{
309 led->rt2x00dev = rt2x00dev;
310 led->type = type;
311 led->led_dev.brightness_set = rt61pci_brightness_set;
312 led->led_dev.blink_set = rt61pci_blink_set;
313 led->flags = LED_INITIALIZED;
314}
771fd565 315#endif /* CONFIG_RT2X00_LIB_LEDS */
a9450b70 316
95ea3627
ID		 317/*
318 * Configuration handlers.
319 */
61e754f4
ID		 320static int rt61pci_config_shared_key(struct rt2x00_dev *rt2x00dev,
321 struct rt2x00lib_crypto *crypto,
322 struct ieee80211_key_conf *key)
323{
324 struct hw_key_entry key_entry;
325 struct rt2x00_field32 field;
326 u32 mask;
327 u32 reg;
328
329 if (crypto->cmd == SET_KEY) {
330 /*
331 * rt2x00lib can't determine the correct free
332 * key_idx for shared keys. We have 1 register
333 * with key valid bits. The goal is simple, read
334 * the register, if that is full we have no slots
335 * left.
336 * Note that each BSS is allowed to have up to 4
337 * shared keys, so put a mask over the allowed
338 * entries.
339 */
340 mask = (0xf << crypto->bssidx);
341
1d6205d0 342 rt2x00mmio_register_read(rt2x00dev, SEC_CSR0, &reg);
61e754f4
ID		 343 reg &= mask;
344
345 if (reg && reg == mask)
346 return -ENOSPC;
347
acaf908d 348 key->hw_key_idx += reg ? ffz(reg) : 0;
61e754f4
ID		 349
350 /*
351 * Upload key to hardware
352 */
353 memcpy(key_entry.key, crypto->key,
354 sizeof(key_entry.key));
355 memcpy(key_entry.tx_mic, crypto->tx_mic,
356 sizeof(key_entry.tx_mic));
357 memcpy(key_entry.rx_mic, crypto->rx_mic,
358 sizeof(key_entry.rx_mic));
359
360 reg = SHARED_KEY_ENTRY(key->hw_key_idx);
1d6205d0
GJ		 361 rt2x00mmio_register_multiwrite(rt2x00dev, reg,
362 &key_entry, sizeof(key_entry));
61e754f4
ID		 363
364 /*
365 * The cipher types are stored over 2 registers.
366 * bssidx 0 and 1 keys are stored in SEC_CSR1 and
367 * bssidx 1 and 2 keys are stored in SEC_CSR5.
368 * Using the correct defines correctly will cause overhead,
369 * so just calculate the correct offset.
370 */
371 if (key->hw_key_idx < 8) {
372 field.bit_offset = (3 * key->hw_key_idx);
373 field.bit_mask = 0x7 << field.bit_offset;
374
1d6205d0 375 rt2x00mmio_register_read(rt2x00dev, SEC_CSR1, &reg);
61e754f4 376 rt2x00_set_field32(&reg, field, crypto->cipher);
1d6205d0 377 rt2x00mmio_register_write(rt2x00dev, SEC_CSR1, reg);
61e754f4
ID		 378 } else {
379 field.bit_offset = (3 * (key->hw_key_idx - 8));
380 field.bit_mask = 0x7 << field.bit_offset;
381
1d6205d0 382 rt2x00mmio_register_read(rt2x00dev, SEC_CSR5, &reg);
61e754f4 383 rt2x00_set_field32(&reg, field, crypto->cipher);
1d6205d0 384 rt2x00mmio_register_write(rt2x00dev, SEC_CSR5, reg);
61e754f4
ID		 385 }
386
387 /*
388 * The driver does not support the IV/EIV generation
389 * in hardware. However it doesn't support the IV/EIV
390 * inside the ieee80211 frame either, but requires it
b34e620f 391 * to be provided separately for the descriptor.
61e754f4
ID		 392 * rt2x00lib will cut the IV/EIV data out of all frames
393 * given to us by mac80211, but we must tell mac80211
394 * to generate the IV/EIV data.
395 */
396 key->flags |= IEEE80211_KEY_FLAG_GENERATE_IV;
397 }
398
399 /*
400 * SEC_CSR0 contains only single-bit fields to indicate
401 * a particular key is valid. Because using the FIELD32()
b34e620f 402 * defines directly will cause a lot of overhead, we use
61e754f4
ID		 403 * a calculation to determine the correct bit directly.
404 */
405 mask = 1 << key->hw_key_idx;
406
1d6205d0 407 rt2x00mmio_register_read(rt2x00dev, SEC_CSR0, &reg);
61e754f4
ID		 408 if (crypto->cmd == SET_KEY)
409 reg |= mask;
410 else if (crypto->cmd == DISABLE_KEY)
411 reg &= ~mask;
1d6205d0 412 rt2x00mmio_register_write(rt2x00dev, SEC_CSR0, reg);
61e754f4
ID		 413
414 return 0;
415}
416
417static int rt61pci_config_pairwise_key(struct rt2x00_dev *rt2x00dev,
418 struct rt2x00lib_crypto *crypto,
419 struct ieee80211_key_conf *key)
420{
421 struct hw_pairwise_ta_entry addr_entry;
422 struct hw_key_entry key_entry;
423 u32 mask;
424 u32 reg;
425
426 if (crypto->cmd == SET_KEY) {
427 /*
428 * rt2x00lib can't determine the correct free
429 * key_idx for pairwise keys. We have 2 registers
b34e620f
TLSC		 430 * with key valid bits. The goal is simple: read
431 * the first register. If that is full, move to
61e754f4 432 * the next register.
b34e620f
TLSC		 433 * When both registers are full, we drop the key.
434 * Otherwise, we use the first invalid entry.
61e754f4 435 */
1d6205d0 436 rt2x00mmio_register_read(rt2x00dev, SEC_CSR2, &reg);
61e754f4
ID		 437 if (reg && reg == ~0) {
438 key->hw_key_idx = 32;
1d6205d0 439 rt2x00mmio_register_read(rt2x00dev, SEC_CSR3, &reg);
61e754f4
ID		 440 if (reg && reg == ~0)
441 return -ENOSPC;
442 }
443
acaf908d 444 key->hw_key_idx += reg ? ffz(reg) : 0;
61e754f4
ID		 445
446 /*
447 * Upload key to hardware
448 */
449 memcpy(key_entry.key, crypto->key,
450 sizeof(key_entry.key));
451 memcpy(key_entry.tx_mic, crypto->tx_mic,
452 sizeof(key_entry.tx_mic));
453 memcpy(key_entry.rx_mic, crypto->rx_mic,
454 sizeof(key_entry.rx_mic));
455
456 memset(&addr_entry, 0, sizeof(addr_entry));
457 memcpy(&addr_entry, crypto->address, ETH_ALEN);
458 addr_entry.cipher = crypto->cipher;
459
460 reg = PAIRWISE_KEY_ENTRY(key->hw_key_idx);
1d6205d0
GJ		 461 rt2x00mmio_register_multiwrite(rt2x00dev, reg,
462 &key_entry, sizeof(key_entry));
61e754f4
ID		 463
464 reg = PAIRWISE_TA_ENTRY(key->hw_key_idx);
1d6205d0
GJ		 465 rt2x00mmio_register_multiwrite(rt2x00dev, reg,
466 &addr_entry, sizeof(addr_entry));
61e754f4
ID		 467
468 /*
b34e620f
TLSC		 469 * Enable pairwise lookup table for given BSS idx.
470 * Without this, received frames will not be decrypted
61e754f4
ID		 471 * by the hardware.
472 */
1d6205d0 473 rt2x00mmio_register_read(rt2x00dev, SEC_CSR4, &reg);
61e754f4 474 reg |= (1 << crypto->bssidx);
1d6205d0 475 rt2x00mmio_register_write(rt2x00dev, SEC_CSR4, reg);
61e754f4
ID		 476
477 /*
478 * The driver does not support the IV/EIV generation
479 * in hardware. However it doesn't support the IV/EIV
480 * inside the ieee80211 frame either, but requires it
3ad2f3fb 481 * to be provided separately for the descriptor.
61e754f4
ID		 482 * rt2x00lib will cut the IV/EIV data out of all frames
483 * given to us by mac80211, but we must tell mac80211
484 * to generate the IV/EIV data.
485 */
486 key->flags |= IEEE80211_KEY_FLAG_GENERATE_IV;
487 }
488
489 /*
490 * SEC_CSR2 and SEC_CSR3 contain only single-bit fields to indicate
491 * a particular key is valid. Because using the FIELD32()
b34e620f 492 * defines directly will cause a lot of overhead, we use
61e754f4
ID		 493 * a calculation to determine the correct bit directly.
494 */
495 if (key->hw_key_idx < 32) {
496 mask = 1 << key->hw_key_idx;
497
1d6205d0 498 rt2x00mmio_register_read(rt2x00dev, SEC_CSR2, &reg);
61e754f4
ID		 499 if (crypto->cmd == SET_KEY)
500 reg |= mask;
501 else if (crypto->cmd == DISABLE_KEY)
502 reg &= ~mask;
1d6205d0 503 rt2x00mmio_register_write(rt2x00dev, SEC_CSR2, reg);
61e754f4
ID		 504 } else {
505 mask = 1 << (key->hw_key_idx - 32);
506
1d6205d0 507 rt2x00mmio_register_read(rt2x00dev, SEC_CSR3, &reg);
61e754f4
ID		 508 if (crypto->cmd == SET_KEY)
509 reg |= mask;
510 else if (crypto->cmd == DISABLE_KEY)
511 reg &= ~mask;
1d6205d0 512 rt2x00mmio_register_write(rt2x00dev, SEC_CSR3, reg);
61e754f4
ID		 513 }
514
515 return 0;
516}
517
3a643d24
ID		 518static void rt61pci_config_filter(struct rt2x00_dev *rt2x00dev,
519 const unsigned int filter_flags)
520{
521 u32 reg;
522
523 /*
524 * Start configuration steps.
525 * Note that the version error will always be dropped
526 * and broadcast frames will always be accepted since
527 * there is no filter for it at this time.
528 */
1d6205d0 529 rt2x00mmio_register_read(rt2x00dev, TXRX_CSR0, &reg);
3a643d24
ID		 530 rt2x00_set_field32(&reg, TXRX_CSR0_DROP_CRC,
531 !(filter_flags & FIF_FCSFAIL));
532 rt2x00_set_field32(&reg, TXRX_CSR0_DROP_PHYSICAL,
533 !(filter_flags & FIF_PLCPFAIL));
534 rt2x00_set_field32(&reg, TXRX_CSR0_DROP_CONTROL,
1afcfd54 535 !(filter_flags & (FIF_CONTROL | FIF_PSPOLL)));
3a643d24
ID		 536 rt2x00_set_field32(&reg, TXRX_CSR0_DROP_NOT_TO_ME,
537 !(filter_flags & FIF_PROMISC_IN_BSS));
538 rt2x00_set_field32(&reg, TXRX_CSR0_DROP_TO_DS,
e0b005fa
ID		 539 !(filter_flags & FIF_PROMISC_IN_BSS) &&
540 !rt2x00dev->intf_ap_count);
3a643d24
ID		 541 rt2x00_set_field32(&reg, TXRX_CSR0_DROP_VERSION_ERROR, 1);
542 rt2x00_set_field32(&reg, TXRX_CSR0_DROP_MULTICAST,
543 !(filter_flags & FIF_ALLMULTI));
544 rt2x00_set_field32(&reg, TXRX_CSR0_DROP_BROADCAST, 0);
545 rt2x00_set_field32(&reg, TXRX_CSR0_DROP_ACK_CTS,
546 !(filter_flags & FIF_CONTROL));
1d6205d0 547 rt2x00mmio_register_write(rt2x00dev, TXRX_CSR0, reg);
3a643d24
ID		 548}
549
6bb40dd1
ID		 550static void rt61pci_config_intf(struct rt2x00_dev *rt2x00dev,
551 struct rt2x00_intf *intf,
552 struct rt2x00intf_conf *conf,
553 const unsigned int flags)
95ea3627 554{
6bb40dd1 555 u32 reg;
95ea3627 556
6bb40dd1 557 if (flags & CONFIG_UPDATE_TYPE) {
6bb40dd1
ID		 558 /*
559 * Enable synchronisation.
560 */
1d6205d0 561 rt2x00mmio_register_read(rt2x00dev, TXRX_CSR9, &reg);
6bb40dd1 562 rt2x00_set_field32(&reg, TXRX_CSR9_TSF_SYNC, conf->sync);
1d6205d0 563 rt2x00mmio_register_write(rt2x00dev, TXRX_CSR9, reg);
6bb40dd1 564 }
95ea3627 565
6bb40dd1
ID		 566 if (flags & CONFIG_UPDATE_MAC) {
567 reg = le32_to_cpu(conf->mac[1]);
568 rt2x00_set_field32(&reg, MAC_CSR3_UNICAST_TO_ME_MASK, 0xff);
569 conf->mac[1] = cpu_to_le32(reg);
95ea3627 570
1d6205d0
GJ		 571 rt2x00mmio_register_multiwrite(rt2x00dev, MAC_CSR2,
572 conf->mac, sizeof(conf->mac));
6bb40dd1 573 }
95ea3627 574
6bb40dd1
ID		 575 if (flags & CONFIG_UPDATE_BSSID) {
576 reg = le32_to_cpu(conf->bssid[1]);
577 rt2x00_set_field32(&reg, MAC_CSR5_BSS_ID_MASK, 3);
578 conf->bssid[1] = cpu_to_le32(reg);
95ea3627 579
1d6205d0
GJ		 580 rt2x00mmio_register_multiwrite(rt2x00dev, MAC_CSR4,
581 conf->bssid,
582 sizeof(conf->bssid));
6bb40dd1 583 }
95ea3627
ID		 584}
585
3a643d24 586static void rt61pci_config_erp(struct rt2x00_dev *rt2x00dev,
02044643
HS		 587 struct rt2x00lib_erp *erp,
588 u32 changed)
95ea3627 589{
95ea3627 590 u32 reg;
95ea3627 591
1d6205d0 592 rt2x00mmio_register_read(rt2x00dev, TXRX_CSR0, &reg);
4789666e 593 rt2x00_set_field32(&reg, TXRX_CSR0_RX_ACK_TIMEOUT, 0x32);
8a566afe 594 rt2x00_set_field32(&reg, TXRX_CSR0_TSF_OFFSET, IEEE80211_HEADER);
1d6205d0 595 rt2x00mmio_register_write(rt2x00dev, TXRX_CSR0, reg);
95ea3627 596
02044643 597 if (changed & BSS_CHANGED_ERP_PREAMBLE) {
1d6205d0 598 rt2x00mmio_register_read(rt2x00dev, TXRX_CSR4, &reg);
02044643
HS		 599 rt2x00_set_field32(&reg, TXRX_CSR4_AUTORESPOND_ENABLE, 1);
600 rt2x00_set_field32(&reg, TXRX_CSR4_AUTORESPOND_PREAMBLE,
601 !!erp->short_preamble);
1d6205d0 602 rt2x00mmio_register_write(rt2x00dev, TXRX_CSR4, reg);
02044643 603 }
95ea3627 604
02044643 605 if (changed & BSS_CHANGED_BASIC_RATES)
1d6205d0
GJ		 606 rt2x00mmio_register_write(rt2x00dev, TXRX_CSR5,
607 erp->basic_rates);
95ea3627 608
02044643 609 if (changed & BSS_CHANGED_BEACON_INT) {
1d6205d0 610 rt2x00mmio_register_read(rt2x00dev, TXRX_CSR9, &reg);
02044643
HS		 611 rt2x00_set_field32(&reg, TXRX_CSR9_BEACON_INTERVAL,
612 erp->beacon_int * 16);
1d6205d0 613 rt2x00mmio_register_write(rt2x00dev, TXRX_CSR9, reg);
02044643 614 }
8a566afe 615
02044643 616 if (changed & BSS_CHANGED_ERP_SLOT) {
1d6205d0 617 rt2x00mmio_register_read(rt2x00dev, MAC_CSR9, &reg);
02044643 618 rt2x00_set_field32(&reg, MAC_CSR9_SLOT_TIME, erp->slot_time);
1d6205d0 619 rt2x00mmio_register_write(rt2x00dev, MAC_CSR9, reg);
95ea3627 620
1d6205d0 621 rt2x00mmio_register_read(rt2x00dev, MAC_CSR8, &reg);
02044643
HS		 622 rt2x00_set_field32(&reg, MAC_CSR8_SIFS, erp->sifs);
623 rt2x00_set_field32(&reg, MAC_CSR8_SIFS_AFTER_RX_OFDM, 3);
624 rt2x00_set_field32(&reg, MAC_CSR8_EIFS, erp->eifs);
1d6205d0 625 rt2x00mmio_register_write(rt2x00dev, MAC_CSR8, reg);
02044643 626 }
95ea3627
ID		 627}
628
629static void rt61pci_config_antenna_5x(struct rt2x00_dev *rt2x00dev,
addc81bd 630 struct antenna_setup *ant)
95ea3627
ID		 631{
632 u8 r3;
633 u8 r4;
634 u8 r77;
635
636 rt61pci_bbp_read(rt2x00dev, 3, &r3);
637 rt61pci_bbp_read(rt2x00dev, 4, &r4);
638 rt61pci_bbp_read(rt2x00dev, 77, &r77);
639
5122d898 640 rt2x00_set_field8(&r3, BBP_R3_SMART_MODE, rt2x00_rf(rt2x00dev, RF5325));
e4cd2ff8
ID		 641
642 /*
643 * Configure the RX antenna.
644 */
addc81bd 645 switch (ant->rx) {
95ea3627 646 case ANTENNA_HW_DIVERSITY:
acaa410d 647 rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA_CONTROL, 2);
95ea3627 648 rt2x00_set_field8(&r4, BBP_R4_RX_FRAME_END,
8318d78a 649 (rt2x00dev->curr_band != IEEE80211_BAND_5GHZ));
95ea3627
ID		 650 break;
651 case ANTENNA_A:
acaa410d 652 rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA_CONTROL, 1);
95ea3627 653 rt2x00_set_field8(&r4, BBP_R4_RX_FRAME_END, 0);
8318d78a 654 if (rt2x00dev->curr_band == IEEE80211_BAND_5GHZ)
acaa410d
MN		 655 rt2x00_set_field8(&r77, BBP_R77_RX_ANTENNA, 0);
656 else
657 rt2x00_set_field8(&r77, BBP_R77_RX_ANTENNA, 3);
95ea3627
ID		 658 break;
659 case ANTENNA_B:
a4fe07d9 660 default:
acaa410d 661 rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA_CONTROL, 1);
95ea3627 662 rt2x00_set_field8(&r4, BBP_R4_RX_FRAME_END, 0);
8318d78a 663 if (rt2x00dev->curr_band == IEEE80211_BAND_5GHZ)
acaa410d
MN		 664 rt2x00_set_field8(&r77, BBP_R77_RX_ANTENNA, 3);
665 else
666 rt2x00_set_field8(&r77, BBP_R77_RX_ANTENNA, 0);
95ea3627
ID		 667 break;
668 }
669
670 rt61pci_bbp_write(rt2x00dev, 77, r77);
671 rt61pci_bbp_write(rt2x00dev, 3, r3);
672 rt61pci_bbp_write(rt2x00dev, 4, r4);
673}
674
675static void rt61pci_config_antenna_2x(struct rt2x00_dev *rt2x00dev,
addc81bd 676 struct antenna_setup *ant)
95ea3627
ID		 677{
678 u8 r3;
679 u8 r4;
680 u8 r77;
681
682 rt61pci_bbp_read(rt2x00dev, 3, &r3);
683 rt61pci_bbp_read(rt2x00dev, 4, &r4);
684 rt61pci_bbp_read(rt2x00dev, 77, &r77);
685
5122d898 686 rt2x00_set_field8(&r3, BBP_R3_SMART_MODE, rt2x00_rf(rt2x00dev, RF2529));
95ea3627 687 rt2x00_set_field8(&r4, BBP_R4_RX_FRAME_END,
7dab73b3 688 !test_bit(CAPABILITY_FRAME_TYPE, &rt2x00dev->cap_flags));
95ea3627 689
e4cd2ff8
ID		 690 /*
691 * Configure the RX antenna.
692 */
addc81bd 693 switch (ant->rx) {
95ea3627 694 case ANTENNA_HW_DIVERSITY:
acaa410d 695 rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA_CONTROL, 2);
95ea3627
ID		 696 break;
697 case ANTENNA_A:
acaa410d
MN		 698 rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA_CONTROL, 1);
699 rt2x00_set_field8(&r77, BBP_R77_RX_ANTENNA, 3);
95ea3627
ID		 700 break;
701 case ANTENNA_B:
a4fe07d9 702 default:
acaa410d
MN		 703 rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA_CONTROL, 1);
704 rt2x00_set_field8(&r77, BBP_R77_RX_ANTENNA, 0);
95ea3627
ID		 705 break;
706 }
707
708 rt61pci_bbp_write(rt2x00dev, 77, r77);
709 rt61pci_bbp_write(rt2x00dev, 3, r3);
710 rt61pci_bbp_write(rt2x00dev, 4, r4);
711}
712
713static void rt61pci_config_antenna_2529_rx(struct rt2x00_dev *rt2x00dev,
714 const int p1, const int p2)
715{
716 u32 reg;
717
1d6205d0 718 rt2x00mmio_register_read(rt2x00dev, MAC_CSR13, &reg);
95ea3627 719
99bdf51a
GW		 720 rt2x00_set_field32(&reg, MAC_CSR13_DIR4, 0);
721 rt2x00_set_field32(&reg, MAC_CSR13_VAL4, p1);
acaa410d 722
99bdf51a
GW		 723 rt2x00_set_field32(&reg, MAC_CSR13_DIR3, 0);
724 rt2x00_set_field32(&reg, MAC_CSR13_VAL3, !p2);
acaa410d 725
1d6205d0 726 rt2x00mmio_register_write(rt2x00dev, MAC_CSR13, reg);
95ea3627
ID		 727}
728
729static void rt61pci_config_antenna_2529(struct rt2x00_dev *rt2x00dev,
addc81bd 730 struct antenna_setup *ant)
95ea3627 731{
95ea3627
ID		 732 u8 r3;
733 u8 r4;
734 u8 r77;
735
736 rt61pci_bbp_read(rt2x00dev, 3, &r3);
737 rt61pci_bbp_read(rt2x00dev, 4, &r4);
738 rt61pci_bbp_read(rt2x00dev, 77, &r77);
e4cd2ff8 739
e4cd2ff8
ID		 740 /*
741 * Configure the RX antenna.
742 */
743 switch (ant->rx) {
744 case ANTENNA_A:
acaa410d
MN		 745 rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA_CONTROL, 1);
746 rt2x00_set_field8(&r77, BBP_R77_RX_ANTENNA, 0);
747 rt61pci_config_antenna_2529_rx(rt2x00dev, 0, 0);
e4cd2ff8 748 break;
e4cd2ff8
ID		 749 case ANTENNA_HW_DIVERSITY:
750 /*
a4fe07d9
ID		 751 * FIXME: Antenna selection for the rf 2529 is very confusing
752 * in the legacy driver. Just default to antenna B until the
753 * legacy code can be properly translated into rt2x00 code.
e4cd2ff8
ID		 754 */
755 case ANTENNA_B:
a4fe07d9 756 default:
acaa410d
MN		 757 rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA_CONTROL, 1);
758 rt2x00_set_field8(&r77, BBP_R77_RX_ANTENNA, 3);
759 rt61pci_config_antenna_2529_rx(rt2x00dev, 1, 1);
e4cd2ff8
ID		 760 break;
761 }
762
e4cd2ff8 763 rt61pci_bbp_write(rt2x00dev, 77, r77);
95ea3627
ID		 764 rt61pci_bbp_write(rt2x00dev, 3, r3);
765 rt61pci_bbp_write(rt2x00dev, 4, r4);
766}
767
768struct antenna_sel {
769 u8 word;
770 /*
771 * value[0] -> non-LNA
772 * value[1] -> LNA
773 */
774 u8 value[2];
775};
776
777static const struct antenna_sel antenna_sel_a[] = {
778 { 96, { 0x58, 0x78 } },
779 { 104, { 0x38, 0x48 } },
780 { 75, { 0xfe, 0x80 } },
781 { 86, { 0xfe, 0x80 } },
782 { 88, { 0xfe, 0x80 } },
783 { 35, { 0x60, 0x60 } },
784 { 97, { 0x58, 0x58 } },
785 { 98, { 0x58, 0x58 } },
786};
787
788static const struct antenna_sel antenna_sel_bg[] = {
789 { 96, { 0x48, 0x68 } },
790 { 104, { 0x2c, 0x3c } },
791 { 75, { 0xfe, 0x80 } },
792 { 86, { 0xfe, 0x80 } },
793 { 88, { 0xfe, 0x80 } },
794 { 35, { 0x50, 0x50 } },
795 { 97, { 0x48, 0x48 } },
796 { 98, { 0x48, 0x48 } },
797};
798
e4ea1c40
ID		 799static void rt61pci_config_ant(struct rt2x00_dev *rt2x00dev,
800 struct antenna_setup *ant)
95ea3627
ID		 801{
802 const struct antenna_sel *sel;
803 unsigned int lna;
804 unsigned int i;
805 u32 reg;
806
a4fe07d9
ID		 807 /*
808 * We should never come here because rt2x00lib is supposed
809 * to catch this and send us the correct antenna explicitely.
810 */
811 BUG_ON(ant->rx == ANTENNA_SW_DIVERSITY ||
812 ant->tx == ANTENNA_SW_DIVERSITY);
813
8318d78a 814 if (rt2x00dev->curr_band == IEEE80211_BAND_5GHZ) {
95ea3627 815 sel = antenna_sel_a;
7dab73b3 816 lna = test_bit(CAPABILITY_EXTERNAL_LNA_A, &rt2x00dev->cap_flags);
95ea3627
ID		 817 } else {
818 sel = antenna_sel_bg;
7dab73b3 819 lna = test_bit(CAPABILITY_EXTERNAL_LNA_BG, &rt2x00dev->cap_flags);
95ea3627
ID		 820 }
821
acaa410d
MN		 822 for (i = 0; i < ARRAY_SIZE(antenna_sel_a); i++)
823 rt61pci_bbp_write(rt2x00dev, sel[i].word, sel[i].value[lna]);
824
1d6205d0 825 rt2x00mmio_register_read(rt2x00dev, PHY_CSR0, &reg);
acaa410d 826
ddc827f9 827 rt2x00_set_field32(&reg, PHY_CSR0_PA_PE_BG,
8318d78a 828 rt2x00dev->curr_band == IEEE80211_BAND_2GHZ);
ddc827f9 829 rt2x00_set_field32(&reg, PHY_CSR0_PA_PE_A,
8318d78a 830 rt2x00dev->curr_band == IEEE80211_BAND_5GHZ);
ddc827f9 831
1d6205d0 832 rt2x00mmio_register_write(rt2x00dev, PHY_CSR0, reg);
95ea3627 833
5122d898 834 if (rt2x00_rf(rt2x00dev, RF5225) || rt2x00_rf(rt2x00dev, RF5325))
addc81bd 835 rt61pci_config_antenna_5x(rt2x00dev, ant);
5122d898 836 else if (rt2x00_rf(rt2x00dev, RF2527))
addc81bd 837 rt61pci_config_antenna_2x(rt2x00dev, ant);
5122d898 838 else if (rt2x00_rf(rt2x00dev, RF2529)) {
7dab73b3 839 if (test_bit(CAPABILITY_DOUBLE_ANTENNA, &rt2x00dev->cap_flags))
addc81bd 840 rt61pci_config_antenna_2x(rt2x00dev, ant);
95ea3627 841 else
addc81bd 842 rt61pci_config_antenna_2529(rt2x00dev, ant);
95ea3627
ID		 843 }
844}
845
e4ea1c40
ID		 846static void rt61pci_config_lna_gain(struct rt2x00_dev *rt2x00dev,
847 struct rt2x00lib_conf *libconf)
848{
849 u16 eeprom;
850 short lna_gain = 0;
851
675a0b04 852 if (libconf->conf->chandef.chan->band == IEEE80211_BAND_2GHZ) {
7dab73b3 853 if (test_bit(CAPABILITY_EXTERNAL_LNA_BG, &rt2x00dev->cap_flags))
e4ea1c40
ID		 854 lna_gain += 14;
855
856 rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_OFFSET_BG, &eeprom);
857 lna_gain -= rt2x00_get_field16(eeprom, EEPROM_RSSI_OFFSET_BG_1);
858 } else {
7dab73b3 859 if (test_bit(CAPABILITY_EXTERNAL_LNA_A, &rt2x00dev->cap_flags))
e4ea1c40
ID		 860 lna_gain += 14;
861
862 rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_OFFSET_A, &eeprom);
863 lna_gain -= rt2x00_get_field16(eeprom, EEPROM_RSSI_OFFSET_A_1);
864 }
865
866 rt2x00dev->lna_gain = lna_gain;
867}
868
869static void rt61pci_config_channel(struct rt2x00_dev *rt2x00dev,
870 struct rf_channel *rf, const int txpower)
871{
872 u8 r3;
873 u8 r94;
874 u8 smart;
875
876 rt2x00_set_field32(&rf->rf3, RF3_TXPOWER, TXPOWER_TO_DEV(txpower));
877 rt2x00_set_field32(&rf->rf4, RF4_FREQ_OFFSET, rt2x00dev->freq_offset);
878
5122d898 879 smart = !(rt2x00_rf(rt2x00dev, RF5225) || rt2x00_rf(rt2x00dev, RF2527));
e4ea1c40
ID		 880
881 rt61pci_bbp_read(rt2x00dev, 3, &r3);
882 rt2x00_set_field8(&r3, BBP_R3_SMART_MODE, smart);
883 rt61pci_bbp_write(rt2x00dev, 3, r3);
884
885 r94 = 6;
886 if (txpower > MAX_TXPOWER && txpower <= (MAX_TXPOWER + r94))
887 r94 += txpower - MAX_TXPOWER;
888 else if (txpower < MIN_TXPOWER && txpower >= (MIN_TXPOWER - r94))
889 r94 += txpower;
890 rt61pci_bbp_write(rt2x00dev, 94, r94);
891
892 rt61pci_rf_write(rt2x00dev, 1, rf->rf1);
893 rt61pci_rf_write(rt2x00dev, 2, rf->rf2);
894 rt61pci_rf_write(rt2x00dev, 3, rf->rf3 & ~0x00000004);
895 rt61pci_rf_write(rt2x00dev, 4, rf->rf4);
896
897 udelay(200);
898
899 rt61pci_rf_write(rt2x00dev, 1, rf->rf1);
900 rt61pci_rf_write(rt2x00dev, 2, rf->rf2);
901 rt61pci_rf_write(rt2x00dev, 3, rf->rf3 | 0x00000004);
902 rt61pci_rf_write(rt2x00dev, 4, rf->rf4);
903
904 udelay(200);
905
906 rt61pci_rf_write(rt2x00dev, 1, rf->rf1);
907 rt61pci_rf_write(rt2x00dev, 2, rf->rf2);
908 rt61pci_rf_write(rt2x00dev, 3, rf->rf3 & ~0x00000004);
909 rt61pci_rf_write(rt2x00dev, 4, rf->rf4);
910
911 msleep(1);
912}
913
914static void rt61pci_config_txpower(struct rt2x00_dev *rt2x00dev,
915 const int txpower)
916{
917 struct rf_channel rf;
918
919 rt2x00_rf_read(rt2x00dev, 1, &rf.rf1);
920 rt2x00_rf_read(rt2x00dev, 2, &rf.rf2);
921 rt2x00_rf_read(rt2x00dev, 3, &rf.rf3);
922 rt2x00_rf_read(rt2x00dev, 4, &rf.rf4);
923
924 rt61pci_config_channel(rt2x00dev, &rf, txpower);
925}
926
927static void rt61pci_config_retry_limit(struct rt2x00_dev *rt2x00dev,
5c58ee51 928 struct rt2x00lib_conf *libconf)
95ea3627
ID		 929{
930 u32 reg;
931
1d6205d0 932 rt2x00mmio_register_read(rt2x00dev, TXRX_CSR4, &reg);
e1b4d7b7
ID		 933 rt2x00_set_field32(&reg, TXRX_CSR4_OFDM_TX_RATE_DOWN, 1);
934 rt2x00_set_field32(&reg, TXRX_CSR4_OFDM_TX_RATE_STEP, 0);
935 rt2x00_set_field32(&reg, TXRX_CSR4_OFDM_TX_FALLBACK_CCK, 0);
e4ea1c40
ID		 936 rt2x00_set_field32(&reg, TXRX_CSR4_LONG_RETRY_LIMIT,
937 libconf->conf->long_frame_max_tx_count);
938 rt2x00_set_field32(&reg, TXRX_CSR4_SHORT_RETRY_LIMIT,
939 libconf->conf->short_frame_max_tx_count);
1d6205d0 940 rt2x00mmio_register_write(rt2x00dev, TXRX_CSR4, reg);
e4ea1c40 941}
95ea3627 942
7d7f19cc
ID		 943static void rt61pci_config_ps(struct rt2x00_dev *rt2x00dev,
944 struct rt2x00lib_conf *libconf)
945{
946 enum dev_state state =
947 (libconf->conf->flags & IEEE80211_CONF_PS) ?
948 STATE_SLEEP : STATE_AWAKE;
949 u32 reg;
950
951 if (state == STATE_SLEEP) {
1d6205d0 952 rt2x00mmio_register_read(rt2x00dev, MAC_CSR11, &reg);
7d7f19cc 953 rt2x00_set_field32(&reg, MAC_CSR11_DELAY_AFTER_TBCN,
6b347bff 954 rt2x00dev->beacon_int - 10);
7d7f19cc
ID		 955 rt2x00_set_field32(&reg, MAC_CSR11_TBCN_BEFORE_WAKEUP,
956 libconf->conf->listen_interval - 1);
957 rt2x00_set_field32(&reg, MAC_CSR11_WAKEUP_LATENCY, 5);
958
959 /* We must first disable autowake before it can be enabled */
960 rt2x00_set_field32(&reg, MAC_CSR11_AUTOWAKE, 0);
1d6205d0 961 rt2x00mmio_register_write(rt2x00dev, MAC_CSR11, reg);
7d7f19cc
ID		 962
963 rt2x00_set_field32(&reg, MAC_CSR11_AUTOWAKE, 1);
1d6205d0 964 rt2x00mmio_register_write(rt2x00dev, MAC_CSR11, reg);
7d7f19cc 965
1d6205d0
GJ		 966 rt2x00mmio_register_write(rt2x00dev, SOFT_RESET_CSR,
967 0x00000005);
968 rt2x00mmio_register_write(rt2x00dev, IO_CNTL_CSR, 0x0000001c);
969 rt2x00mmio_register_write(rt2x00dev, PCI_USEC_CSR, 0x00000060);
7d7f19cc
ID		 970
971 rt61pci_mcu_request(rt2x00dev, MCU_SLEEP, 0xff, 0, 0);
972 } else {
1d6205d0 973 rt2x00mmio_register_read(rt2x00dev, MAC_CSR11, &reg);
7d7f19cc
ID		 974 rt2x00_set_field32(&reg, MAC_CSR11_DELAY_AFTER_TBCN, 0);
975 rt2x00_set_field32(&reg, MAC_CSR11_TBCN_BEFORE_WAKEUP, 0);
976 rt2x00_set_field32(&reg, MAC_CSR11_AUTOWAKE, 0);
977 rt2x00_set_field32(&reg, MAC_CSR11_WAKEUP_LATENCY, 0);
1d6205d0 978 rt2x00mmio_register_write(rt2x00dev, MAC_CSR11, reg);
7d7f19cc 979
1d6205d0
GJ		 980 rt2x00mmio_register_write(rt2x00dev, SOFT_RESET_CSR,
981 0x00000007);
982 rt2x00mmio_register_write(rt2x00dev, IO_CNTL_CSR, 0x00000018);
983 rt2x00mmio_register_write(rt2x00dev, PCI_USEC_CSR, 0x00000020);
7d7f19cc
ID		 984
985 rt61pci_mcu_request(rt2x00dev, MCU_WAKEUP, 0xff, 0, 0);
986 }
987}
988
95ea3627 989static void rt61pci_config(struct rt2x00_dev *rt2x00dev,
6bb40dd1
ID		 990 struct rt2x00lib_conf *libconf,
991 const unsigned int flags)
95ea3627 992{
ba2ab471
ID		 993 /* Always recalculate LNA gain before changing configuration */
994 rt61pci_config_lna_gain(rt2x00dev, libconf);
995
e4ea1c40 996 if (flags & IEEE80211_CONF_CHANGE_CHANNEL)
5c58ee51
ID		 997 rt61pci_config_channel(rt2x00dev, &libconf->rf,
998 libconf->conf->power_level);
e4ea1c40
ID		 999 if ((flags & IEEE80211_CONF_CHANGE_POWER) &&
1000 !(flags & IEEE80211_CONF_CHANGE_CHANNEL))
5c58ee51 1001 rt61pci_config_txpower(rt2x00dev, libconf->conf->power_level);
e4ea1c40
ID		 1002 if (flags & IEEE80211_CONF_CHANGE_RETRY_LIMITS)
1003 rt61pci_config_retry_limit(rt2x00dev, libconf);
7d7f19cc
ID		 1004 if (flags & IEEE80211_CONF_CHANGE_PS)
1005 rt61pci_config_ps(rt2x00dev, libconf);
95ea3627
ID		 1006}
1007
95ea3627
ID		 1008/*
1009 * Link tuning
1010 */
ebcf26da
ID		 1011static void rt61pci_link_stats(struct rt2x00_dev *rt2x00dev,
1012 struct link_qual *qual)
95ea3627
ID		 1013{
1014 u32 reg;
1015
1016 /*
1017 * Update FCS error count from register.
1018 */
1d6205d0 1019 rt2x00mmio_register_read(rt2x00dev, STA_CSR0, &reg);
ebcf26da 1020 qual->rx_failed = rt2x00_get_field32(reg, STA_CSR0_FCS_ERROR);
95ea3627
ID		 1021
1022 /*
1023 * Update False CCA count from register.
1024 */
1d6205d0 1025 rt2x00mmio_register_read(rt2x00dev, STA_CSR1, &reg);
ebcf26da 1026 qual->false_cca = rt2x00_get_field32(reg, STA_CSR1_FALSE_CCA_ERROR);
95ea3627
ID		 1027}
1028
5352ff65
ID		 1029static inline void rt61pci_set_vgc(struct rt2x00_dev *rt2x00dev,
1030 struct link_qual *qual, u8 vgc_level)
eb20b4e8 1031{
5352ff65 1032 if (qual->vgc_level != vgc_level) {
eb20b4e8 1033 rt61pci_bbp_write(rt2x00dev, 17, vgc_level);
5352ff65
ID		 1034 qual->vgc_level = vgc_level;
1035 qual->vgc_level_reg = vgc_level;
eb20b4e8
ID		 1036 }
1037}
1038
5352ff65
ID		 1039static void rt61pci_reset_tuner(struct rt2x00_dev *rt2x00dev,
1040 struct link_qual *qual)
95ea3627 1041{
5352ff65 1042 rt61pci_set_vgc(rt2x00dev, qual, 0x20);
95ea3627
ID		 1043}
1044
5352ff65
ID		 1045static void rt61pci_link_tuner(struct rt2x00_dev *rt2x00dev,
1046 struct link_qual *qual, const u32 count)
95ea3627 1047{
95ea3627
ID		 1048 u8 up_bound;
1049 u8 low_bound;
1050
95ea3627
ID		 1051 /*
1052 * Determine r17 bounds.
1053 */
e5ef5bad 1054 if (rt2x00dev->curr_band == IEEE80211_BAND_5GHZ) {
95ea3627
ID		 1055 low_bound = 0x28;
1056 up_bound = 0x48;
7dab73b3 1057 if (test_bit(CAPABILITY_EXTERNAL_LNA_A, &rt2x00dev->cap_flags)) {
95ea3627
ID		 1058 low_bound += 0x10;
1059 up_bound += 0x10;
1060 }
1061 } else {
1062 low_bound = 0x20;
1063 up_bound = 0x40;
7dab73b3 1064 if (test_bit(CAPABILITY_EXTERNAL_LNA_BG, &rt2x00dev->cap_flags)) {
95ea3627
ID		 1065 low_bound += 0x10;
1066 up_bound += 0x10;
1067 }
1068 }
1069
6bb40dd1
ID		 1070 /*
1071 * If we are not associated, we should go straight to the
1072 * dynamic CCA tuning.
1073 */
1074 if (!rt2x00dev->intf_associated)
1075 goto dynamic_cca_tune;
1076
95ea3627
ID		 1077 /*
1078 * Special big-R17 for very short distance
1079 */
5352ff65
ID		 1080 if (qual->rssi >= -35) {
1081 rt61pci_set_vgc(rt2x00dev, qual, 0x60);
95ea3627
ID		 1082 return;
1083 }
1084
1085 /*
1086 * Special big-R17 for short distance
1087 */
5352ff65
ID		 1088 if (qual->rssi >= -58) {
1089 rt61pci_set_vgc(rt2x00dev, qual, up_bound);
95ea3627
ID		 1090 return;
1091 }
1092
1093 /*
1094 * Special big-R17 for middle-short distance
1095 */
5352ff65
ID		 1096 if (qual->rssi >= -66) {
1097 rt61pci_set_vgc(rt2x00dev, qual, low_bound + 0x10);
95ea3627
ID		 1098 return;
1099 }
1100
1101 /*
1102 * Special mid-R17 for middle distance
1103 */
5352ff65
ID		 1104 if (qual->rssi >= -74) {
1105 rt61pci_set_vgc(rt2x00dev, qual, low_bound + 0x08);
95ea3627
ID		 1106 return;
1107 }
1108
1109 /*
1110 * Special case: Change up_bound based on the rssi.
1111 * Lower up_bound when rssi is weaker then -74 dBm.
1112 */
5352ff65 1113 up_bound -= 2 * (-74 - qual->rssi);
95ea3627
ID		 1114 if (low_bound > up_bound)
1115 up_bound = low_bound;
1116
5352ff65
ID		 1117 if (qual->vgc_level > up_bound) {
1118 rt61pci_set_vgc(rt2x00dev, qual, up_bound);
95ea3627
ID		 1119 return;
1120 }
1121
6bb40dd1
ID		 1122dynamic_cca_tune:
1123
95ea3627
ID		 1124 /*
1125 * r17 does not yet exceed upper limit, continue and base
1126 * the r17 tuning on the false CCA count.
1127 */
5352ff65
ID		 1128 if ((qual->false_cca > 512) && (qual->vgc_level < up_bound))
1129 rt61pci_set_vgc(rt2x00dev, qual, ++qual->vgc_level);
1130 else if ((qual->false_cca < 100) && (qual->vgc_level > low_bound))
1131 rt61pci_set_vgc(rt2x00dev, qual, --qual->vgc_level);
95ea3627
ID		 1132}
1133
5450b7e2
ID		 1134/*
1135 * Queue handlers.
1136 */
1137static void rt61pci_start_queue(struct data_queue *queue)
1138{
1139 struct rt2x00_dev *rt2x00dev = queue->rt2x00dev;
1140 u32 reg;
1141
1142 switch (queue->qid) {
1143 case QID_RX:
1d6205d0 1144 rt2x00mmio_register_read(rt2x00dev, TXRX_CSR0, &reg);
5450b7e2 1145 rt2x00_set_field32(&reg, TXRX_CSR0_DISABLE_RX, 0);
1d6205d0 1146 rt2x00mmio_register_write(rt2x00dev, TXRX_CSR0, reg);
5450b7e2
ID		 1147 break;
1148 case QID_BEACON:
1d6205d0 1149 rt2x00mmio_register_read(rt2x00dev, TXRX_CSR9, &reg);
5450b7e2
ID		 1150 rt2x00_set_field32(&reg, TXRX_CSR9_TSF_TICKING, 1);
1151 rt2x00_set_field32(&reg, TXRX_CSR9_TBTT_ENABLE, 1);
1152 rt2x00_set_field32(&reg, TXRX_CSR9_BEACON_GEN, 1);
1d6205d0 1153 rt2x00mmio_register_write(rt2x00dev, TXRX_CSR9, reg);
5450b7e2
ID		 1154 break;
1155 default:
1156 break;
1157 }
1158}
1159
1160static void rt61pci_kick_queue(struct data_queue *queue)
1161{
1162 struct rt2x00_dev *rt2x00dev = queue->rt2x00dev;
1163 u32 reg;
1164
1165 switch (queue->qid) {
f615e9a3 1166 case QID_AC_VO:
1d6205d0 1167 rt2x00mmio_register_read(rt2x00dev, TX_CNTL_CSR, &reg);
5450b7e2 1168 rt2x00_set_field32(&reg, TX_CNTL_CSR_KICK_TX_AC0, 1);
1d6205d0 1169 rt2x00mmio_register_write(rt2x00dev, TX_CNTL_CSR, reg);
5450b7e2 1170 break;
f615e9a3 1171 case QID_AC_VI:
1d6205d0 1172 rt2x00mmio_register_read(rt2x00dev, TX_CNTL_CSR, &reg);
5450b7e2 1173 rt2x00_set_field32(&reg, TX_CNTL_CSR_KICK_TX_AC1, 1);
1d6205d0 1174 rt2x00mmio_register_write(rt2x00dev, TX_CNTL_CSR, reg);
5450b7e2 1175 break;
f615e9a3 1176 case QID_AC_BE:
1d6205d0 1177 rt2x00mmio_register_read(rt2x00dev, TX_CNTL_CSR, &reg);
5450b7e2 1178 rt2x00_set_field32(&reg, TX_CNTL_CSR_KICK_TX_AC2, 1);
1d6205d0 1179 rt2x00mmio_register_write(rt2x00dev, TX_CNTL_CSR, reg);
5450b7e2 1180 break;
f615e9a3 1181 case QID_AC_BK:
1d6205d0 1182 rt2x00mmio_register_read(rt2x00dev, TX_CNTL_CSR, &reg);
5450b7e2 1183 rt2x00_set_field32(&reg, TX_CNTL_CSR_KICK_TX_AC3, 1);
1d6205d0 1184 rt2x00mmio_register_write(rt2x00dev, TX_CNTL_CSR, reg);
5450b7e2
ID		 1185 break;
1186 default:
1187 break;
1188 }
1189}
1190
1191static void rt61pci_stop_queue(struct data_queue *queue)
1192{
1193 struct rt2x00_dev *rt2x00dev = queue->rt2x00dev;
1194 u32 reg;
1195
1196 switch (queue->qid) {
f615e9a3 1197 case QID_AC_VO:
1d6205d0 1198 rt2x00mmio_register_read(rt2x00dev, TX_CNTL_CSR, &reg);
5450b7e2 1199 rt2x00_set_field32(&reg, TX_CNTL_CSR_ABORT_TX_AC0, 1);
1d6205d0 1200 rt2x00mmio_register_write(rt2x00dev, TX_CNTL_CSR, reg);
5450b7e2 1201 break;
f615e9a3 1202 case QID_AC_VI:
1d6205d0 1203 rt2x00mmio_register_read(rt2x00dev, TX_CNTL_CSR, &reg);
5450b7e2 1204 rt2x00_set_field32(&reg, TX_CNTL_CSR_ABORT_TX_AC1, 1);
1d6205d0 1205 rt2x00mmio_register_write(rt2x00dev, TX_CNTL_CSR, reg);
5450b7e2 1206 break;
f615e9a3 1207 case QID_AC_BE:
1d6205d0 1208 rt2x00mmio_register_read(rt2x00dev, TX_CNTL_CSR, &reg);
5450b7e2 1209 rt2x00_set_field32(&reg, TX_CNTL_CSR_ABORT_TX_AC2, 1);
1d6205d0 1210 rt2x00mmio_register_write(rt2x00dev, TX_CNTL_CSR, reg);
5450b7e2 1211 break;
f615e9a3 1212 case QID_AC_BK:
1d6205d0 1213 rt2x00mmio_register_read(rt2x00dev, TX_CNTL_CSR, &reg);
5450b7e2 1214 rt2x00_set_field32(&reg, TX_CNTL_CSR_ABORT_TX_AC3, 1);
1d6205d0 1215 rt2x00mmio_register_write(rt2x00dev, TX_CNTL_CSR, reg);
5450b7e2
ID		 1216 break;
1217 case QID_RX:
1d6205d0 1218 rt2x00mmio_register_read(rt2x00dev, TXRX_CSR0, &reg);
5450b7e2 1219 rt2x00_set_field32(&reg, TXRX_CSR0_DISABLE_RX, 1);
1d6205d0 1220 rt2x00mmio_register_write(rt2x00dev, TXRX_CSR0, reg);
5450b7e2
ID		 1221 break;
1222 case QID_BEACON:
1d6205d0 1223 rt2x00mmio_register_read(rt2x00dev, TXRX_CSR9, &reg);
5450b7e2
ID		 1224 rt2x00_set_field32(&reg, TXRX_CSR9_TSF_TICKING, 0);
1225 rt2x00_set_field32(&reg, TXRX_CSR9_TBTT_ENABLE, 0);
1226 rt2x00_set_field32(&reg, TXRX_CSR9_BEACON_GEN, 0);
1d6205d0 1227 rt2x00mmio_register_write(rt2x00dev, TXRX_CSR9, reg);
5846a550
HS		 1228
1229 /*
1230 * Wait for possibly running tbtt tasklets.
1231 */
abc11994 1232 tasklet_kill(&rt2x00dev->tbtt_tasklet);
5450b7e2
ID		 1233 break;
1234 default:
1235 break;
1236 }
1237}
1238
95ea3627 1239/*
a7f3a06c 1240 * Firmware functions
95ea3627
ID		 1241 */
1242static char *rt61pci_get_firmware_name(struct rt2x00_dev *rt2x00dev)
1243{
49e721ec 1244 u16 chip;
95ea3627
ID		 1245 char *fw_name;
1246
49e721ec
GW		 1247 pci_read_config_word(to_pci_dev(rt2x00dev->dev), PCI_DEVICE_ID, &chip);
1248 switch (chip) {
1249 case RT2561_PCI_ID:
95ea3627
ID		 1250 fw_name = FIRMWARE_RT2561;
1251 break;
49e721ec 1252 case RT2561s_PCI_ID:
95ea3627
ID		 1253 fw_name = FIRMWARE_RT2561s;
1254 break;
49e721ec 1255 case RT2661_PCI_ID:
95ea3627
ID		 1256 fw_name = FIRMWARE_RT2661;
1257 break;
1258 default:
1259 fw_name = NULL;
1260 break;
1261 }
1262
1263 return fw_name;
1264}
1265
0cbe0064
ID		 1266static int rt61pci_check_firmware(struct rt2x00_dev *rt2x00dev,
1267 const u8 *data, const size_t len)
a7f3a06c 1268{
0cbe0064 1269 u16 fw_crc;
a7f3a06c
ID		 1270 u16 crc;
1271
1272 /*
0cbe0064
ID		 1273 * Only support 8kb firmware files.
1274 */
1275 if (len != 8192)
1276 return FW_BAD_LENGTH;
1277
1278 /*
b34e620f
TLSC		 1279 * The last 2 bytes in the firmware array are the crc checksum itself.
1280 * This means that we should never pass those 2 bytes to the crc
a7f3a06c
ID		 1281 * algorithm.
1282 */
0cbe0064
ID		 1283 fw_crc = (data[len - 2] << 8 | data[len - 1]);
1284
1285 /*
1286 * Use the crc itu-t algorithm.
1287 */
a7f3a06c
ID		 1288 crc = crc_itu_t(0, data, len - 2);
1289 crc = crc_itu_t_byte(crc, 0);
1290 crc = crc_itu_t_byte(crc, 0);
1291
0cbe0064 1292 return (fw_crc == crc) ? FW_OK : FW_BAD_CRC;
a7f3a06c
ID		 1293}
1294
0cbe0064
ID		 1295static int rt61pci_load_firmware(struct rt2x00_dev *rt2x00dev,
1296 const u8 *data, const size_t len)
95ea3627
ID		 1297{
1298 int i;
1299 u32 reg;
1300
1301 /*
1302 * Wait for stable hardware.
1303 */
1304 for (i = 0; i < 100; i++) {
1d6205d0 1305 rt2x00mmio_register_read(rt2x00dev, MAC_CSR0, &reg);
95ea3627
ID		 1306 if (reg)
1307 break;
1308 msleep(1);
1309 }
1310
1311 if (!reg) {
ec9c4989 1312 rt2x00_err(rt2x00dev, "Unstable hardware\n");
95ea3627
ID		 1313 return -EBUSY;
1314 }
1315
1316 /*
1317 * Prepare MCU and mailbox for firmware loading.
1318 */
1319 reg = 0;
1320 rt2x00_set_field32(&reg, MCU_CNTL_CSR_RESET, 1);
1d6205d0
GJ		 1321 rt2x00mmio_register_write(rt2x00dev, MCU_CNTL_CSR, reg);
1322 rt2x00mmio_register_write(rt2x00dev, M2H_CMD_DONE_CSR, 0xffffffff);
1323 rt2x00mmio_register_write(rt2x00dev, H2M_MAILBOX_CSR, 0);
1324 rt2x00mmio_register_write(rt2x00dev, HOST_CMD_CSR, 0);
95ea3627
ID		 1325
1326 /*
1327 * Write firmware to device.
1328 */
1329 reg = 0;
1330 rt2x00_set_field32(&reg, MCU_CNTL_CSR_RESET, 1);
1331 rt2x00_set_field32(&reg, MCU_CNTL_CSR_SELECT_BANK, 1);
1d6205d0 1332 rt2x00mmio_register_write(rt2x00dev, MCU_CNTL_CSR, reg);
95ea3627 1333
1d6205d0
GJ		 1334 rt2x00mmio_register_multiwrite(rt2x00dev, FIRMWARE_IMAGE_BASE,
1335 data, len);
95ea3627
ID		 1336
1337 rt2x00_set_field32(&reg, MCU_CNTL_CSR_SELECT_BANK, 0);
1d6205d0 1338 rt2x00mmio_register_write(rt2x00dev, MCU_CNTL_CSR, reg);
95ea3627
ID		 1339
1340 rt2x00_set_field32(&reg, MCU_CNTL_CSR_RESET, 0);
1d6205d0 1341 rt2x00mmio_register_write(rt2x00dev, MCU_CNTL_CSR, reg);
95ea3627
ID		 1342
1343 for (i = 0; i < 100; i++) {
1d6205d0 1344 rt2x00mmio_register_read(rt2x00dev, MCU_CNTL_CSR, &reg);
95ea3627
ID		 1345 if (rt2x00_get_field32(reg, MCU_CNTL_CSR_READY))
1346 break;
1347 msleep(1);
1348 }
1349
1350 if (i == 100) {
ec9c4989 1351 rt2x00_err(rt2x00dev, "MCU Control register not ready\n");
95ea3627
ID		 1352 return -EBUSY;
1353 }
1354
e6d3e902
ID		 1355 /*
1356 * Hardware needs another millisecond before it is ready.
1357 */
1358 msleep(1);
1359
95ea3627
ID		 1360 /*
1361 * Reset MAC and BBP registers.
1362 */
1363 reg = 0;
1364 rt2x00_set_field32(&reg, MAC_CSR1_SOFT_RESET, 1);
1365 rt2x00_set_field32(&reg, MAC_CSR1_BBP_RESET, 1);
1d6205d0 1366 rt2x00mmio_register_write(rt2x00dev, MAC_CSR1, reg);
95ea3627 1367
1d6205d0 1368 rt2x00mmio_register_read(rt2x00dev, MAC_CSR1, &reg);
95ea3627
ID		 1369 rt2x00_set_field32(&reg, MAC_CSR1_SOFT_RESET, 0);
1370 rt2x00_set_field32(&reg, MAC_CSR1_BBP_RESET, 0);
1d6205d0 1371 rt2x00mmio_register_write(rt2x00dev, MAC_CSR1, reg);
95ea3627 1372
1d6205d0 1373 rt2x00mmio_register_read(rt2x00dev, MAC_CSR1, &reg);
95ea3627 1374 rt2x00_set_field32(&reg, MAC_CSR1_HOST_READY, 1);
1d6205d0 1375 rt2x00mmio_register_write(rt2x00dev, MAC_CSR1, reg);
95ea3627
ID		 1376
1377 return 0;
1378}
1379
a7f3a06c
ID		 1380/*
1381 * Initialization functions.
1382 */
798b7adb 1383static bool rt61pci_get_entry_state(struct queue_entry *entry)
95ea3627 1384{
1d6205d0 1385 struct queue_entry_priv_mmio *entry_priv = entry->priv_data;
95ea3627
ID		 1386 u32 word;
1387
798b7adb
ID		 1388 if (entry->queue->qid == QID_RX) {
1389 rt2x00_desc_read(entry_priv->desc, 0, &word);
95ea3627 1390
798b7adb
ID		 1391 return rt2x00_get_field32(word, RXD_W0_OWNER_NIC);
1392 } else {
1393 rt2x00_desc_read(entry_priv->desc, 0, &word);
1394
1395 return (rt2x00_get_field32(word, TXD_W0_OWNER_NIC) ||
1396 rt2x00_get_field32(word, TXD_W0_VALID));
1397 }
95ea3627
ID		 1398}
1399
798b7adb 1400static void rt61pci_clear_entry(struct queue_entry *entry)
95ea3627 1401{
1d6205d0 1402 struct queue_entry_priv_mmio *entry_priv = entry->priv_data;
798b7adb 1403 struct skb_frame_desc *skbdesc = get_skb_frame_desc(entry->skb);
95ea3627
ID		 1404 u32 word;
1405
798b7adb
ID		 1406 if (entry->queue->qid == QID_RX) {
1407 rt2x00_desc_read(entry_priv->desc, 5, &word);
1408 rt2x00_set_field32(&word, RXD_W5_BUFFER_PHYSICAL_ADDRESS,
1409 skbdesc->skb_dma);
1410 rt2x00_desc_write(entry_priv->desc, 5, word);
1411
1412 rt2x00_desc_read(entry_priv->desc, 0, &word);
1413 rt2x00_set_field32(&word, RXD_W0_OWNER_NIC, 1);
1414 rt2x00_desc_write(entry_priv->desc, 0, word);
1415 } else {
1416 rt2x00_desc_read(entry_priv->desc, 0, &word);
1417 rt2x00_set_field32(&word, TXD_W0_VALID, 0);
1418 rt2x00_set_field32(&word, TXD_W0_OWNER_NIC, 0);
1419 rt2x00_desc_write(entry_priv->desc, 0, word);
1420 }
95ea3627
ID		 1421}
1422
181d6902 1423static int rt61pci_init_queues(struct rt2x00_dev *rt2x00dev)
95ea3627 1424{
1d6205d0 1425 struct queue_entry_priv_mmio *entry_priv;
95ea3627
ID		 1426 u32 reg;
1427
95ea3627
ID		 1428 /*
1429 * Initialize registers.
1430 */
1d6205d0 1431 rt2x00mmio_register_read(rt2x00dev, TX_RING_CSR0, &reg);
95ea3627 1432 rt2x00_set_field32(&reg, TX_RING_CSR0_AC0_RING_SIZE,
181d6902 1433 rt2x00dev->tx[0].limit);
95ea3627 1434 rt2x00_set_field32(&reg, TX_RING_CSR0_AC1_RING_SIZE,
181d6902 1435 rt2x00dev->tx[1].limit);
95ea3627 1436 rt2x00_set_field32(&reg, TX_RING_CSR0_AC2_RING_SIZE,
181d6902 1437 rt2x00dev->tx[2].limit);
95ea3627 1438 rt2x00_set_field32(&reg, TX_RING_CSR0_AC3_RING_SIZE,
181d6902 1439 rt2x00dev->tx[3].limit);
1d6205d0 1440 rt2x00mmio_register_write(rt2x00dev, TX_RING_CSR0, reg);
95ea3627 1441
1d6205d0 1442 rt2x00mmio_register_read(rt2x00dev, TX_RING_CSR1, &reg);
95ea3627 1443 rt2x00_set_field32(&reg, TX_RING_CSR1_TXD_SIZE,
181d6902 1444 rt2x00dev->tx[0].desc_size / 4);
1d6205d0 1445 rt2x00mmio_register_write(rt2x00dev, TX_RING_CSR1, reg);
95ea3627 1446
b8be63ff 1447 entry_priv = rt2x00dev->tx[0].entries[0].priv_data;
1d6205d0 1448 rt2x00mmio_register_read(rt2x00dev, AC0_BASE_CSR, &reg);
30b3a23c 1449 rt2x00_set_field32(&reg, AC0_BASE_CSR_RING_REGISTER,
b8be63ff 1450 entry_priv->desc_dma);
1d6205d0 1451 rt2x00mmio_register_write(rt2x00dev, AC0_BASE_CSR, reg);
95ea3627 1452
b8be63ff 1453 entry_priv = rt2x00dev->tx[1].entries[0].priv_data;
1d6205d0 1454 rt2x00mmio_register_read(rt2x00dev, AC1_BASE_CSR, &reg);
30b3a23c 1455 rt2x00_set_field32(&reg, AC1_BASE_CSR_RING_REGISTER,
b8be63ff 1456 entry_priv->desc_dma);
1d6205d0 1457 rt2x00mmio_register_write(rt2x00dev, AC1_BASE_CSR, reg);
95ea3627 1458
b8be63ff 1459 entry_priv = rt2x00dev->tx[2].entries[0].priv_data;
1d6205d0 1460 rt2x00mmio_register_read(rt2x00dev, AC2_BASE_CSR, &reg);
30b3a23c 1461 rt2x00_set_field32(&reg, AC2_BASE_CSR_RING_REGISTER,
b8be63ff 1462 entry_priv->desc_dma);
1d6205d0 1463 rt2x00mmio_register_write(rt2x00dev, AC2_BASE_CSR, reg);
95ea3627 1464
b8be63ff 1465 entry_priv = rt2x00dev->tx[3].entries[0].priv_data;
1d6205d0 1466 rt2x00mmio_register_read(rt2x00dev, AC3_BASE_CSR, &reg);
30b3a23c 1467 rt2x00_set_field32(&reg, AC3_BASE_CSR_RING_REGISTER,
b8be63ff 1468 entry_priv->desc_dma);
1d6205d0 1469 rt2x00mmio_register_write(rt2x00dev, AC3_BASE_CSR, reg);
95ea3627 1470
1d6205d0 1471 rt2x00mmio_register_read(rt2x00dev, RX_RING_CSR, &reg);
181d6902 1472 rt2x00_set_field32(&reg, RX_RING_CSR_RING_SIZE, rt2x00dev->rx->limit);
95ea3627
ID		 1473 rt2x00_set_field32(&reg, RX_RING_CSR_RXD_SIZE,
1474 rt2x00dev->rx->desc_size / 4);
1475 rt2x00_set_field32(&reg, RX_RING_CSR_RXD_WRITEBACK_SIZE, 4);
1d6205d0 1476 rt2x00mmio_register_write(rt2x00dev, RX_RING_CSR, reg);
95ea3627 1477
b8be63ff 1478 entry_priv = rt2x00dev->rx->entries[0].priv_data;
1d6205d0 1479 rt2x00mmio_register_read(rt2x00dev, RX_BASE_CSR, &reg);
30b3a23c 1480 rt2x00_set_field32(&reg, RX_BASE_CSR_RING_REGISTER,
b8be63ff 1481 entry_priv->desc_dma);
1d6205d0 1482 rt2x00mmio_register_write(rt2x00dev, RX_BASE_CSR, reg);
95ea3627 1483
1d6205d0 1484 rt2x00mmio_register_read(rt2x00dev, TX_DMA_DST_CSR, &reg);
95ea3627
ID		 1485 rt2x00_set_field32(&reg, TX_DMA_DST_CSR_DEST_AC0, 2);
1486 rt2x00_set_field32(&reg, TX_DMA_DST_CSR_DEST_AC1, 2);
1487 rt2x00_set_field32(&reg, TX_DMA_DST_CSR_DEST_AC2, 2);
1488 rt2x00_set_field32(&reg, TX_DMA_DST_CSR_DEST_AC3, 2);
1d6205d0 1489 rt2x00mmio_register_write(rt2x00dev, TX_DMA_DST_CSR, reg);
95ea3627 1490
1d6205d0 1491 rt2x00mmio_register_read(rt2x00dev, LOAD_TX_RING_CSR, &reg);
95ea3627
ID		 1492 rt2x00_set_field32(&reg, LOAD_TX_RING_CSR_LOAD_TXD_AC0, 1);
1493 rt2x00_set_field32(&reg, LOAD_TX_RING_CSR_LOAD_TXD_AC1, 1);
1494 rt2x00_set_field32(&reg, LOAD_TX_RING_CSR_LOAD_TXD_AC2, 1);
1495 rt2x00_set_field32(&reg, LOAD_TX_RING_CSR_LOAD_TXD_AC3, 1);
1d6205d0 1496 rt2x00mmio_register_write(rt2x00dev, LOAD_TX_RING_CSR, reg);
95ea3627 1497
1d6205d0 1498 rt2x00mmio_register_read(rt2x00dev, RX_CNTL_CSR, &reg);
95ea3627 1499 rt2x00_set_field32(&reg, RX_CNTL_CSR_LOAD_RXD, 1);
1d6205d0 1500 rt2x00mmio_register_write(rt2x00dev, RX_CNTL_CSR, reg);
95ea3627
ID		 1501
1502 return 0;
1503}
1504
1505static int rt61pci_init_registers(struct rt2x00_dev *rt2x00dev)
1506{
1507 u32 reg;
1508
1d6205d0 1509 rt2x00mmio_register_read(rt2x00dev, TXRX_CSR0, &reg);
95ea3627
ID		 1510 rt2x00_set_field32(&reg, TXRX_CSR0_AUTO_TX_SEQ, 1);
1511 rt2x00_set_field32(&reg, TXRX_CSR0_DISABLE_RX, 0);
1512 rt2x00_set_field32(&reg, TXRX_CSR0_TX_WITHOUT_WAITING, 0);
1d6205d0 1513 rt2x00mmio_register_write(rt2x00dev, TXRX_CSR0, reg);
95ea3627 1514
1d6205d0 1515 rt2x00mmio_register_read(rt2x00dev, TXRX_CSR1, &reg);
95ea3627
ID		 1516 rt2x00_set_field32(&reg, TXRX_CSR1_BBP_ID0, 47); /* CCK Signal */
1517 rt2x00_set_field32(&reg, TXRX_CSR1_BBP_ID0_VALID, 1);
1518 rt2x00_set_field32(&reg, TXRX_CSR1_BBP_ID1, 30); /* Rssi */
1519 rt2x00_set_field32(&reg, TXRX_CSR1_BBP_ID1_VALID, 1);
1520 rt2x00_set_field32(&reg, TXRX_CSR1_BBP_ID2, 42); /* OFDM Rate */
1521 rt2x00_set_field32(&reg, TXRX_CSR1_BBP_ID2_VALID, 1);
1522 rt2x00_set_field32(&reg, TXRX_CSR1_BBP_ID3, 30); /* Rssi */
1523 rt2x00_set_field32(&reg, TXRX_CSR1_BBP_ID3_VALID, 1);
1d6205d0 1524 rt2x00mmio_register_write(rt2x00dev, TXRX_CSR1, reg);
95ea3627
ID		 1525
1526 /*
1527 * CCK TXD BBP registers
1528 */
1d6205d0 1529 rt2x00mmio_register_read(rt2x00dev, TXRX_CSR2, &reg);
95ea3627
ID		 1530 rt2x00_set_field32(&reg, TXRX_CSR2_BBP_ID0, 13);
1531 rt2x00_set_field32(&reg, TXRX_CSR2_BBP_ID0_VALID, 1);
1532 rt2x00_set_field32(&reg, TXRX_CSR2_BBP_ID1, 12);
1533 rt2x00_set_field32(&reg, TXRX_CSR2_BBP_ID1_VALID, 1);
1534 rt2x00_set_field32(&reg, TXRX_CSR2_BBP_ID2, 11);
1535 rt2x00_set_field32(&reg, TXRX_CSR2_BBP_ID2_VALID, 1);
1536 rt2x00_set_field32(&reg, TXRX_CSR2_BBP_ID3, 10);
1537 rt2x00_set_field32(&reg, TXRX_CSR2_BBP_ID3_VALID, 1);
1d6205d0 1538 rt2x00mmio_register_write(rt2x00dev, TXRX_CSR2, reg);
95ea3627
ID		 1539
1540 /*
1541 * OFDM TXD BBP registers
1542 */
1d6205d0 1543 rt2x00mmio_register_read(rt2x00dev, TXRX_CSR3, &reg);
95ea3627
ID		 1544 rt2x00_set_field32(&reg, TXRX_CSR3_BBP_ID0, 7);
1545 rt2x00_set_field32(&reg, TXRX_CSR3_BBP_ID0_VALID, 1);
1546 rt2x00_set_field32(&reg, TXRX_CSR3_BBP_ID1, 6);
1547 rt2x00_set_field32(&reg, TXRX_CSR3_BBP_ID1_VALID, 1);
1548 rt2x00_set_field32(&reg, TXRX_CSR3_BBP_ID2, 5);
1549 rt2x00_set_field32(&reg, TXRX_CSR3_BBP_ID2_VALID, 1);
1d6205d0 1550 rt2x00mmio_register_write(rt2x00dev, TXRX_CSR3, reg);
95ea3627 1551
1d6205d0 1552 rt2x00mmio_register_read(rt2x00dev, TXRX_CSR7, &reg);
95ea3627
ID		 1553 rt2x00_set_field32(&reg, TXRX_CSR7_ACK_CTS_6MBS, 59);
1554 rt2x00_set_field32(&reg, TXRX_CSR7_ACK_CTS_9MBS, 53);
1555 rt2x00_set_field32(&reg, TXRX_CSR7_ACK_CTS_12MBS, 49);
1556 rt2x00_set_field32(&reg, TXRX_CSR7_ACK_CTS_18MBS, 46);
1d6205d0 1557 rt2x00mmio_register_write(rt2x00dev, TXRX_CSR7, reg);
95ea3627 1558
1d6205d0 1559 rt2x00mmio_register_read(rt2x00dev, TXRX_CSR8, &reg);
95ea3627
ID		 1560 rt2x00_set_field32(&reg, TXRX_CSR8_ACK_CTS_24MBS, 44);
1561 rt2x00_set_field32(&reg, TXRX_CSR8_ACK_CTS_36MBS, 42);
1562 rt2x00_set_field32(&reg, TXRX_CSR8_ACK_CTS_48MBS, 42);
1563 rt2x00_set_field32(&reg, TXRX_CSR8_ACK_CTS_54MBS, 42);
1d6205d0 1564 rt2x00mmio_register_write(rt2x00dev, TXRX_CSR8, reg);
95ea3627 1565
1d6205d0 1566 rt2x00mmio_register_read(rt2x00dev, TXRX_CSR9, &reg);
1f909162
ID		 1567 rt2x00_set_field32(&reg, TXRX_CSR9_BEACON_INTERVAL, 0);
1568 rt2x00_set_field32(&reg, TXRX_CSR9_TSF_TICKING, 0);
1569 rt2x00_set_field32(&reg, TXRX_CSR9_TSF_SYNC, 0);
1570 rt2x00_set_field32(&reg, TXRX_CSR9_TBTT_ENABLE, 0);
1571 rt2x00_set_field32(&reg, TXRX_CSR9_BEACON_GEN, 0);
1572 rt2x00_set_field32(&reg, TXRX_CSR9_TIMESTAMP_COMPENSATE, 0);
1d6205d0 1573 rt2x00mmio_register_write(rt2x00dev, TXRX_CSR9, reg);
1f909162 1574
1d6205d0 1575 rt2x00mmio_register_write(rt2x00dev, TXRX_CSR15, 0x0000000f);
95ea3627 1576
1d6205d0 1577 rt2x00mmio_register_write(rt2x00dev, MAC_CSR6, 0x00000fff);
95ea3627 1578
1d6205d0 1579 rt2x00mmio_register_read(rt2x00dev, MAC_CSR9, &reg);
95ea3627 1580 rt2x00_set_field32(&reg, MAC_CSR9_CW_SELECT, 0);
1d6205d0 1581 rt2x00mmio_register_write(rt2x00dev, MAC_CSR9, reg);
95ea3627 1582
1d6205d0 1583 rt2x00mmio_register_write(rt2x00dev, MAC_CSR10, 0x0000071c);
95ea3627
ID		 1584
1585 if (rt2x00dev->ops->lib->set_device_state(rt2x00dev, STATE_AWAKE))
1586 return -EBUSY;
1587
1d6205d0 1588 rt2x00mmio_register_write(rt2x00dev, MAC_CSR13, 0x0000e000);
95ea3627
ID		 1589
1590 /*
1591 * Invalidate all Shared Keys (SEC_CSR0),
1592 * and clear the Shared key Cipher algorithms (SEC_CSR1 & SEC_CSR5)
1593 */
1d6205d0
GJ		 1594 rt2x00mmio_register_write(rt2x00dev, SEC_CSR0, 0x00000000);
1595 rt2x00mmio_register_write(rt2x00dev, SEC_CSR1, 0x00000000);
1596 rt2x00mmio_register_write(rt2x00dev, SEC_CSR5, 0x00000000);
95ea3627 1597
1d6205d0
GJ		 1598 rt2x00mmio_register_write(rt2x00dev, PHY_CSR1, 0x000023b0);
1599 rt2x00mmio_register_write(rt2x00dev, PHY_CSR5, 0x060a100c);
1600 rt2x00mmio_register_write(rt2x00dev, PHY_CSR6, 0x00080606);
1601 rt2x00mmio_register_write(rt2x00dev, PHY_CSR7, 0x00000a08);
95ea3627 1602
1d6205d0 1603 rt2x00mmio_register_write(rt2x00dev, PCI_CFG_CSR, 0x28ca4404);
95ea3627 1604
1d6205d0 1605 rt2x00mmio_register_write(rt2x00dev, TEST_MODE_CSR, 0x00000200);
95ea3627 1606
1d6205d0 1607 rt2x00mmio_register_write(rt2x00dev, M2H_CMD_DONE_CSR, 0xffffffff);
95ea3627 1608
6bb40dd1
ID		 1609 /*
1610 * Clear all beacons
1611 * For the Beacon base registers we only need to clear
1612 * the first byte since that byte contains the VALID and OWNER
1613 * bits which (when set to 0) will invalidate the entire beacon.
1614 */
1d6205d0
GJ		 1615 rt2x00mmio_register_write(rt2x00dev, HW_BEACON_BASE0, 0);
1616 rt2x00mmio_register_write(rt2x00dev, HW_BEACON_BASE1, 0);
1617 rt2x00mmio_register_write(rt2x00dev, HW_BEACON_BASE2, 0);
1618 rt2x00mmio_register_write(rt2x00dev, HW_BEACON_BASE3, 0);
6bb40dd1 1619
95ea3627
ID		 1620 /*
1621 * We must clear the error counters.
1622 * These registers are cleared on read,
1623 * so we may pass a useless variable to store the value.
1624 */
1d6205d0
GJ		 1625 rt2x00mmio_register_read(rt2x00dev, STA_CSR0, &reg);
1626 rt2x00mmio_register_read(rt2x00dev, STA_CSR1, &reg);
1627 rt2x00mmio_register_read(rt2x00dev, STA_CSR2, &reg);
95ea3627
ID		 1628
1629 /*
1630 * Reset MAC and BBP registers.
1631 */
1d6205d0 1632 rt2x00mmio_register_read(rt2x00dev, MAC_CSR1, &reg);
95ea3627
ID		 1633 rt2x00_set_field32(&reg, MAC_CSR1_SOFT_RESET, 1);
1634 rt2x00_set_field32(&reg, MAC_CSR1_BBP_RESET, 1);
1d6205d0 1635 rt2x00mmio_register_write(rt2x00dev, MAC_CSR1, reg);
95ea3627 1636
1d6205d0 1637 rt2x00mmio_register_read(rt2x00dev, MAC_CSR1, &reg);
95ea3627
ID		 1638 rt2x00_set_field32(&reg, MAC_CSR1_SOFT_RESET, 0);
1639 rt2x00_set_field32(&reg, MAC_CSR1_BBP_RESET, 0);
1d6205d0 1640 rt2x00mmio_register_write(rt2x00dev, MAC_CSR1, reg);
95ea3627 1641
1d6205d0 1642 rt2x00mmio_register_read(rt2x00dev, MAC_CSR1, &reg);
95ea3627 1643 rt2x00_set_field32(&reg, MAC_CSR1_HOST_READY, 1);
1d6205d0 1644 rt2x00mmio_register_write(rt2x00dev, MAC_CSR1, reg);
95ea3627
ID		 1645
1646 return 0;
1647}
1648
2b08da3f 1649static int rt61pci_wait_bbp_ready(struct rt2x00_dev *rt2x00dev)
95ea3627
ID		 1650{
1651 unsigned int i;
95ea3627
ID		 1652 u8 value;
1653
1654 for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
1655 rt61pci_bbp_read(rt2x00dev, 0, &value);
1656 if ((value != 0xff) && (value != 0x00))
2b08da3f 1657 return 0;
95ea3627
ID		 1658 udelay(REGISTER_BUSY_DELAY);
1659 }
1660
ec9c4989 1661 rt2x00_err(rt2x00dev, "BBP register access failed, aborting\n");
95ea3627 1662 return -EACCES;
2b08da3f
ID		 1663}
1664
1665static int rt61pci_init_bbp(struct rt2x00_dev *rt2x00dev)
1666{
1667 unsigned int i;
1668 u16 eeprom;
1669 u8 reg_id;
1670 u8 value;
1671
1672 if (unlikely(rt61pci_wait_bbp_ready(rt2x00dev)))
1673 return -EACCES;
95ea3627 1674
95ea3627
ID		 1675 rt61pci_bbp_write(rt2x00dev, 3, 0x00);
1676 rt61pci_bbp_write(rt2x00dev, 15, 0x30);
1677 rt61pci_bbp_write(rt2x00dev, 21, 0xc8);
1678 rt61pci_bbp_write(rt2x00dev, 22, 0x38);
1679 rt61pci_bbp_write(rt2x00dev, 23, 0x06);
1680 rt61pci_bbp_write(rt2x00dev, 24, 0xfe);
1681 rt61pci_bbp_write(rt2x00dev, 25, 0x0a);
1682 rt61pci_bbp_write(rt2x00dev, 26, 0x0d);
1683 rt61pci_bbp_write(rt2x00dev, 34, 0x12);
1684 rt61pci_bbp_write(rt2x00dev, 37, 0x07);
1685 rt61pci_bbp_write(rt2x00dev, 39, 0xf8);
1686 rt61pci_bbp_write(rt2x00dev, 41, 0x60);
1687 rt61pci_bbp_write(rt2x00dev, 53, 0x10);
1688 rt61pci_bbp_write(rt2x00dev, 54, 0x18);
1689 rt61pci_bbp_write(rt2x00dev, 60, 0x10);
1690 rt61pci_bbp_write(rt2x00dev, 61, 0x04);
1691 rt61pci_bbp_write(rt2x00dev, 62, 0x04);
1692 rt61pci_bbp_write(rt2x00dev, 75, 0xfe);
1693 rt61pci_bbp_write(rt2x00dev, 86, 0xfe);
1694 rt61pci_bbp_write(rt2x00dev, 88, 0xfe);
1695 rt61pci_bbp_write(rt2x00dev, 90, 0x0f);
1696 rt61pci_bbp_write(rt2x00dev, 99, 0x00);
1697 rt61pci_bbp_write(rt2x00dev, 102, 0x16);
1698 rt61pci_bbp_write(rt2x00dev, 107, 0x04);
1699
95ea3627
ID		 1700 for (i = 0; i < EEPROM_BBP_SIZE; i++) {
1701 rt2x00_eeprom_read(rt2x00dev, EEPROM_BBP_START + i, &eeprom);
1702
1703 if (eeprom != 0xffff && eeprom != 0x0000) {
1704 reg_id = rt2x00_get_field16(eeprom, EEPROM_BBP_REG_ID);
1705 value = rt2x00_get_field16(eeprom, EEPROM_BBP_VALUE);
95ea3627
ID		 1706 rt61pci_bbp_write(rt2x00dev, reg_id, value);
1707 }
1708 }
95ea3627
ID		 1709
1710 return 0;
1711}
1712
1713/*
1714 * Device state switch handlers.
1715 */
95ea3627
ID		 1716static void rt61pci_toggle_irq(struct rt2x00_dev *rt2x00dev,
1717 enum dev_state state)
1718{
b550911a 1719 int mask = (state == STATE_RADIO_IRQ_OFF);
95ea3627 1720 u32 reg;
5846a550 1721 unsigned long flags;
95ea3627
ID		 1722
1723 /*
1724 * When interrupts are being enabled, the interrupt registers
1725 * should clear the register to assure a clean state.
1726 */
1727 if (state == STATE_RADIO_IRQ_ON) {
1d6205d0
GJ		 1728 rt2x00mmio_register_read(rt2x00dev, INT_SOURCE_CSR, &reg);
1729 rt2x00mmio_register_write(rt2x00dev, INT_SOURCE_CSR, reg);
95ea3627 1730
1d6205d0
GJ		 1731 rt2x00mmio_register_read(rt2x00dev, MCU_INT_SOURCE_CSR, &reg);
1732 rt2x00mmio_register_write(rt2x00dev, MCU_INT_SOURCE_CSR, reg);
95ea3627
ID		 1733 }
1734
1735 /*
1736 * Only toggle the interrupts bits we are going to use.
1737 * Non-checked interrupt bits are disabled by default.
1738 */
5846a550
HS		 1739 spin_lock_irqsave(&rt2x00dev->irqmask_lock, flags);
1740
1d6205d0 1741 rt2x00mmio_register_read(rt2x00dev, INT_MASK_CSR, &reg);
95ea3627
ID		 1742 rt2x00_set_field32(&reg, INT_MASK_CSR_TXDONE, mask);
1743 rt2x00_set_field32(&reg, INT_MASK_CSR_RXDONE, mask);
6646505d 1744 rt2x00_set_field32(&reg, INT_MASK_CSR_BEACON_DONE, mask);
95ea3627
ID		 1745 rt2x00_set_field32(&reg, INT_MASK_CSR_ENABLE_MITIGATION, mask);
1746 rt2x00_set_field32(&reg, INT_MASK_CSR_MITIGATION_PERIOD, 0xff);
1d6205d0 1747 rt2x00mmio_register_write(rt2x00dev, INT_MASK_CSR, reg);
95ea3627 1748
1d6205d0 1749 rt2x00mmio_register_read(rt2x00dev, MCU_INT_MASK_CSR, &reg);
95ea3627
ID		 1750 rt2x00_set_field32(&reg, MCU_INT_MASK_CSR_0, mask);
1751 rt2x00_set_field32(&reg, MCU_INT_MASK_CSR_1, mask);
1752 rt2x00_set_field32(&reg, MCU_INT_MASK_CSR_2, mask);
1753 rt2x00_set_field32(&reg, MCU_INT_MASK_CSR_3, mask);
1754 rt2x00_set_field32(&reg, MCU_INT_MASK_CSR_4, mask);
1755 rt2x00_set_field32(&reg, MCU_INT_MASK_CSR_5, mask);
1756 rt2x00_set_field32(&reg, MCU_INT_MASK_CSR_6, mask);
1757 rt2x00_set_field32(&reg, MCU_INT_MASK_CSR_7, mask);
6646505d 1758 rt2x00_set_field32(&reg, MCU_INT_MASK_CSR_TWAKEUP, mask);
1d6205d0 1759 rt2x00mmio_register_write(rt2x00dev, MCU_INT_MASK_CSR, reg);
5846a550
HS		 1760
1761 spin_unlock_irqrestore(&rt2x00dev->irqmask_lock, flags);
1762
1763 if (state == STATE_RADIO_IRQ_OFF) {
1764 /*
1765 * Ensure that all tasklets are finished.
1766 */
abc11994
HS		 1767 tasklet_kill(&rt2x00dev->txstatus_tasklet);
1768 tasklet_kill(&rt2x00dev->rxdone_tasklet);
1769 tasklet_kill(&rt2x00dev->autowake_tasklet);
1770 tasklet_kill(&rt2x00dev->tbtt_tasklet);
5846a550 1771 }
95ea3627
ID		 1772}
1773
1774static int rt61pci_enable_radio(struct rt2x00_dev *rt2x00dev)
1775{
1776 u32 reg;
1777
1778 /*
1779 * Initialize all registers.
1780 */
2b08da3f
ID		 1781 if (unlikely(rt61pci_init_queues(rt2x00dev) ||
1782 rt61pci_init_registers(rt2x00dev) ||
1783 rt61pci_init_bbp(rt2x00dev)))
95ea3627 1784 return -EIO;
95ea3627
ID		 1785
1786 /*
1787 * Enable RX.
1788 */
1d6205d0 1789 rt2x00mmio_register_read(rt2x00dev, RX_CNTL_CSR, &reg);
95ea3627 1790 rt2x00_set_field32(&reg, RX_CNTL_CSR_ENABLE_RX_DMA, 1);
1d6205d0 1791 rt2x00mmio_register_write(rt2x00dev, RX_CNTL_CSR, reg);
95ea3627 1792
95ea3627
ID		 1793 return 0;
1794}
1795
1796static void rt61pci_disable_radio(struct rt2x00_dev *rt2x00dev)
1797{
95ea3627 1798 /*
a2c9b652 1799 * Disable power
95ea3627 1800 */
1d6205d0 1801 rt2x00mmio_register_write(rt2x00dev, MAC_CSR10, 0x00001818);
95ea3627
ID		 1802}
1803
1804static int rt61pci_set_state(struct rt2x00_dev *rt2x00dev, enum dev_state state)
1805{
9655a6ec 1806 u32 reg, reg2;
95ea3627
ID		 1807 unsigned int i;
1808 char put_to_sleep;
95ea3627
ID		 1809
1810 put_to_sleep = (state != STATE_AWAKE);
1811
1d6205d0 1812 rt2x00mmio_register_read(rt2x00dev, MAC_CSR12, &reg);
95ea3627
ID		 1813 rt2x00_set_field32(&reg, MAC_CSR12_FORCE_WAKEUP, !put_to_sleep);
1814 rt2x00_set_field32(&reg, MAC_CSR12_PUT_TO_SLEEP, put_to_sleep);
1d6205d0 1815 rt2x00mmio_register_write(rt2x00dev, MAC_CSR12, reg);
95ea3627
ID		 1816
1817 /*
1818 * Device is not guaranteed to be in the requested state yet.
1819 * We must wait until the register indicates that the
1820 * device has entered the correct state.
1821 */
1822 for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
1d6205d0 1823 rt2x00mmio_register_read(rt2x00dev, MAC_CSR12, &reg2);
9655a6ec 1824 state = rt2x00_get_field32(reg2, MAC_CSR12_BBP_CURRENT_STATE);
2b08da3f 1825 if (state == !put_to_sleep)
95ea3627 1826 return 0;
1d6205d0 1827 rt2x00mmio_register_write(rt2x00dev, MAC_CSR12, reg);
95ea3627
ID		 1828 msleep(10);
1829 }
1830
95ea3627
ID		 1831 return -EBUSY;
1832}
1833
1834static int rt61pci_set_device_state(struct rt2x00_dev *rt2x00dev,
1835 enum dev_state state)
1836{
1837 int retval = 0;
1838
1839 switch (state) {
1840 case STATE_RADIO_ON:
1841 retval = rt61pci_enable_radio(rt2x00dev);
1842 break;
1843 case STATE_RADIO_OFF:
1844 rt61pci_disable_radio(rt2x00dev);
1845 break;
2b08da3f
ID		 1846 case STATE_RADIO_IRQ_ON:
1847 case STATE_RADIO_IRQ_OFF:
1848 rt61pci_toggle_irq(rt2x00dev, state);
95ea3627
ID		 1849 break;
1850 case STATE_DEEP_SLEEP:
1851 case STATE_SLEEP:
1852 case STATE_STANDBY:
1853 case STATE_AWAKE:
1854 retval = rt61pci_set_state(rt2x00dev, state);
1855 break;
1856 default:
1857 retval = -ENOTSUPP;
1858 break;
1859 }
1860
2b08da3f 1861 if (unlikely(retval))
ec9c4989
JP		 1862 rt2x00_err(rt2x00dev, "Device failed to enter state %d (%d)\n",
1863 state, retval);
2b08da3f 1864
95ea3627
ID		 1865 return retval;
1866}
1867
1868/*
1869 * TX descriptor initialization
1870 */
93331458 1871static void rt61pci_write_tx_desc(struct queue_entry *entry,
61e754f4 1872 struct txentry_desc *txdesc)
95ea3627 1873{
93331458 1874 struct skb_frame_desc *skbdesc = get_skb_frame_desc(entry->skb);
1d6205d0 1875 struct queue_entry_priv_mmio *entry_priv = entry->priv_data;
85b7a8b3 1876 __le32 *txd = entry_priv->desc;
95ea3627
ID		 1877 u32 word;
1878
1879 /*
1880 * Start writing the descriptor words.
1881 */
1882 rt2x00_desc_read(txd, 1, &word);
2b23cdaa
HS		 1883 rt2x00_set_field32(&word, TXD_W1_HOST_Q_ID, entry->queue->qid);
1884 rt2x00_set_field32(&word, TXD_W1_AIFSN, entry->queue->aifs);
1885 rt2x00_set_field32(&word, TXD_W1_CWMIN, entry->queue->cw_min);
1886 rt2x00_set_field32(&word, TXD_W1_CWMAX, entry->queue->cw_max);
61e754f4 1887 rt2x00_set_field32(&word, TXD_W1_IV_OFFSET, txdesc->iv_offset);
5adf6d63
ID		 1888 rt2x00_set_field32(&word, TXD_W1_HW_SEQUENCE,
1889 test_bit(ENTRY_TXD_GENERATE_SEQ, &txdesc->flags));
4de36fe5 1890 rt2x00_set_field32(&word, TXD_W1_BUFFER_COUNT, 1);
95ea3627
ID		 1891 rt2x00_desc_write(txd, 1, word);
1892
1893 rt2x00_desc_read(txd, 2, &word);
26a1d07f
HS		 1894 rt2x00_set_field32(&word, TXD_W2_PLCP_SIGNAL, txdesc->u.plcp.signal);
1895 rt2x00_set_field32(&word, TXD_W2_PLCP_SERVICE, txdesc->u.plcp.service);
1896 rt2x00_set_field32(&word, TXD_W2_PLCP_LENGTH_LOW,
1897 txdesc->u.plcp.length_low);
1898 rt2x00_set_field32(&word, TXD_W2_PLCP_LENGTH_HIGH,
1899 txdesc->u.plcp.length_high);
95ea3627
ID		 1900 rt2x00_desc_write(txd, 2, word);
1901
61e754f4 1902 if (test_bit(ENTRY_TXD_ENCRYPT, &txdesc->flags)) {
1ce9cdac
ID		 1903 _rt2x00_desc_write(txd, 3, skbdesc->iv[0]);
1904 _rt2x00_desc_write(txd, 4, skbdesc->iv[1]);
61e754f4
ID		 1905 }
1906
95ea3627 1907 rt2x00_desc_read(txd, 5, &word);
93331458 1908 rt2x00_set_field32(&word, TXD_W5_PID_TYPE, entry->queue->qid);
4de36fe5
GW		 1909 rt2x00_set_field32(&word, TXD_W5_PID_SUBTYPE,
1910 skbdesc->entry->entry_idx);
95ea3627 1911 rt2x00_set_field32(&word, TXD_W5_TX_POWER,
93331458 1912 TXPOWER_TO_DEV(entry->queue->rt2x00dev->tx_power));
95ea3627
ID		 1913 rt2x00_set_field32(&word, TXD_W5_WAITING_DMA_DONE_INT, 1);
1914 rt2x00_desc_write(txd, 5, word);
1915
2b23cdaa 1916 if (entry->queue->qid != QID_BEACON) {
6b97cb04
GW		 1917 rt2x00_desc_read(txd, 6, &word);
1918 rt2x00_set_field32(&word, TXD_W6_BUFFER_PHYSICAL_ADDRESS,
1919 skbdesc->skb_dma);
1920 rt2x00_desc_write(txd, 6, word);
4de36fe5 1921
d7bafff3 1922 rt2x00_desc_read(txd, 11, &word);
df624ca5
GW		 1923 rt2x00_set_field32(&word, TXD_W11_BUFFER_LENGTH0,
1924 txdesc->length);
d7bafff3
AB		 1925 rt2x00_desc_write(txd, 11, word);
1926 }
95ea3627 1927
e01f1ec3
GW		 1928 /*
1929 * Writing TXD word 0 must the last to prevent a race condition with
1930 * the device, whereby the device may take hold of the TXD before we
1931 * finished updating it.
1932 */
95ea3627
ID		 1933 rt2x00_desc_read(txd, 0, &word);
1934 rt2x00_set_field32(&word, TXD_W0_OWNER_NIC, 1);
1935 rt2x00_set_field32(&word, TXD_W0_VALID, 1);
1936 rt2x00_set_field32(&word, TXD_W0_MORE_FRAG,
181d6902 1937 test_bit(ENTRY_TXD_MORE_FRAG, &txdesc->flags));
95ea3627 1938 rt2x00_set_field32(&word, TXD_W0_ACK,
181d6902 1939 test_bit(ENTRY_TXD_ACK, &txdesc->flags));
95ea3627 1940 rt2x00_set_field32(&word, TXD_W0_TIMESTAMP,
181d6902 1941 test_bit(ENTRY_TXD_REQ_TIMESTAMP, &txdesc->flags));
95ea3627 1942 rt2x00_set_field32(&word, TXD_W0_OFDM,
076f9582 1943 (txdesc->rate_mode == RATE_MODE_OFDM));
2517794b 1944 rt2x00_set_field32(&word, TXD_W0_IFS, txdesc->u.plcp.ifs);
95ea3627 1945 rt2x00_set_field32(&word, TXD_W0_RETRY_MODE,
61486e0f 1946 test_bit(ENTRY_TXD_RETRY_MODE, &txdesc->flags));
61e754f4
ID		 1947 rt2x00_set_field32(&word, TXD_W0_TKIP_MIC,
1948 test_bit(ENTRY_TXD_ENCRYPT_MMIC, &txdesc->flags));
1949 rt2x00_set_field32(&word, TXD_W0_KEY_TABLE,
1950 test_bit(ENTRY_TXD_ENCRYPT_PAIRWISE, &txdesc->flags));
1951 rt2x00_set_field32(&word, TXD_W0_KEY_INDEX, txdesc->key_idx);
df624ca5 1952 rt2x00_set_field32(&word, TXD_W0_DATABYTE_COUNT, txdesc->length);
95ea3627 1953 rt2x00_set_field32(&word, TXD_W0_BURST,
181d6902 1954 test_bit(ENTRY_TXD_BURST, &txdesc->flags));
61e754f4 1955 rt2x00_set_field32(&word, TXD_W0_CIPHER_ALG, txdesc->cipher);
95ea3627 1956 rt2x00_desc_write(txd, 0, word);
85b7a8b3
GW		 1957
1958 /*
1959 * Register descriptor details in skb frame descriptor.
1960 */
1961 skbdesc->desc = txd;
2b23cdaa
HS		 1962 skbdesc->desc_len = (entry->queue->qid == QID_BEACON) ? TXINFO_SIZE :
1963 TXD_DESC_SIZE;
95ea3627
ID		 1964}
1965
1966/*
1967 * TX data initialization
1968 */
f224f4ef
GW		 1969static void rt61pci_write_beacon(struct queue_entry *entry,
1970 struct txentry_desc *txdesc)
bd88a781
ID		 1971{
1972 struct rt2x00_dev *rt2x00dev = entry->queue->rt2x00dev;
1d6205d0 1973 struct queue_entry_priv_mmio *entry_priv = entry->priv_data;
bd88a781 1974 unsigned int beacon_base;
739fd940 1975 unsigned int padding_len;
d76dfc61 1976 u32 orig_reg, reg;
bd88a781
ID		 1977
1978 /*
1979 * Disable beaconing while we are reloading the beacon data,
1980 * otherwise we might be sending out invalid data.
1981 */
1d6205d0 1982 rt2x00mmio_register_read(rt2x00dev, TXRX_CSR9, &reg);
d76dfc61 1983 orig_reg = reg;
bd88a781 1984 rt2x00_set_field32(&reg, TXRX_CSR9_BEACON_GEN, 0);
1d6205d0 1985 rt2x00mmio_register_write(rt2x00dev, TXRX_CSR9, reg);
bd88a781 1986
5c3b685c
GW		 1987 /*
1988 * Write the TX descriptor for the beacon.
1989 */
93331458 1990 rt61pci_write_tx_desc(entry, txdesc);
5c3b685c
GW		 1991
1992 /*
1993 * Dump beacon to userspace through debugfs.
1994 */
1995 rt2x00debug_dump_frame(rt2x00dev, DUMP_FRAME_BEACON, entry->skb);
1996
bd88a781 1997 /*
739fd940 1998 * Write entire beacon with descriptor and padding to register.
bd88a781 1999 */
739fd940 2000 padding_len = roundup(entry->skb->len, 4) - entry->skb->len;
d76dfc61 2001 if (padding_len && skb_pad(entry->skb, padding_len)) {
ec9c4989 2002 rt2x00_err(rt2x00dev, "Failure padding beacon, aborting\n");
d76dfc61
SF		 2003 /* skb freed by skb_pad() on failure */
2004 entry->skb = NULL;
1d6205d0 2005 rt2x00mmio_register_write(rt2x00dev, TXRX_CSR9, orig_reg);
d76dfc61
SF		 2006 return;
2007 }
2008
bd88a781 2009 beacon_base = HW_BEACON_OFFSET(entry->entry_idx);
1d6205d0
GJ		 2010 rt2x00mmio_register_multiwrite(rt2x00dev, beacon_base,
2011 entry_priv->desc, TXINFO_SIZE);
2012 rt2x00mmio_register_multiwrite(rt2x00dev, beacon_base + TXINFO_SIZE,
2013 entry->skb->data,
2014 entry->skb->len + padding_len);
bd88a781 2015
d61cb266
GW		 2016 /*
2017 * Enable beaconing again.
2018 *
2019 * For Wi-Fi faily generated beacons between participating
2020 * stations. Set TBTT phase adaptive adjustment step to 8us.
2021 */
1d6205d0 2022 rt2x00mmio_register_write(rt2x00dev, TXRX_CSR10, 0x00001008);
d61cb266 2023
d61cb266 2024 rt2x00_set_field32(&reg, TXRX_CSR9_BEACON_GEN, 1);
1d6205d0 2025 rt2x00mmio_register_write(rt2x00dev, TXRX_CSR9, reg);
d61cb266 2026
bd88a781
ID		 2027 /*
2028 * Clean up beacon skb.
2029 */
2030 dev_kfree_skb_any(entry->skb);
2031 entry->skb = NULL;
2032}
2033
69cf36a4
HS		 2034static void rt61pci_clear_beacon(struct queue_entry *entry)
2035{
2036 struct rt2x00_dev *rt2x00dev = entry->queue->rt2x00dev;
2037 u32 reg;
2038
2039 /*
2040 * Disable beaconing while we are reloading the beacon data,
2041 * otherwise we might be sending out invalid data.
2042 */
1d6205d0 2043 rt2x00mmio_register_read(rt2x00dev, TXRX_CSR9, &reg);
69cf36a4 2044 rt2x00_set_field32(&reg, TXRX_CSR9_BEACON_GEN, 0);
1d6205d0 2045 rt2x00mmio_register_write(rt2x00dev, TXRX_CSR9, reg);
69cf36a4
HS		 2046
2047 /*
2048 * Clear beacon.
2049 */
1d6205d0
GJ		 2050 rt2x00mmio_register_write(rt2x00dev,
2051 HW_BEACON_OFFSET(entry->entry_idx), 0);
69cf36a4
HS		 2052
2053 /*
2054 * Enable beaconing again.
2055 */
2056 rt2x00_set_field32(&reg, TXRX_CSR9_BEACON_GEN, 1);
1d6205d0 2057 rt2x00mmio_register_write(rt2x00dev, TXRX_CSR9, reg);
69cf36a4
HS		 2058}
2059
95ea3627
ID		 2060/*
2061 * RX control handlers
2062 */
2063static int rt61pci_agc_to_rssi(struct rt2x00_dev *rt2x00dev, int rxd_w1)
2064{
ba2ab471 2065 u8 offset = rt2x00dev->lna_gain;
95ea3627
ID		 2066 u8 lna;
2067
2068 lna = rt2x00_get_field32(rxd_w1, RXD_W1_RSSI_LNA);
2069 switch (lna) {
2070 case 3:
ba2ab471 2071 offset += 90;
95ea3627
ID		 2072 break;
2073 case 2:
ba2ab471 2074 offset += 74;
95ea3627
ID		 2075 break;
2076 case 1:
ba2ab471 2077 offset += 64;
95ea3627
ID		 2078 break;
2079 default:
2080 return 0;
2081 }
2082
e5ef5bad 2083 if (rt2x00dev->curr_band == IEEE80211_BAND_5GHZ) {
95ea3627
ID		 2084 if (lna == 3 || lna == 2)
2085 offset += 10;
95ea3627
ID		 2086 }
2087
2088 return rt2x00_get_field32(rxd_w1, RXD_W1_RSSI_AGC) * 2 - offset;
2089}
2090
181d6902 2091static void rt61pci_fill_rxdone(struct queue_entry *entry,
55887511 2092 struct rxdone_entry_desc *rxdesc)
95ea3627 2093{
61e754f4 2094 struct rt2x00_dev *rt2x00dev = entry->queue->rt2x00dev;
1d6205d0 2095 struct queue_entry_priv_mmio *entry_priv = entry->priv_data;
95ea3627
ID		 2096 u32 word0;
2097 u32 word1;
2098
b8be63ff
ID		 2099 rt2x00_desc_read(entry_priv->desc, 0, &word0);
2100 rt2x00_desc_read(entry_priv->desc, 1, &word1);
95ea3627 2101
4150c572 2102 if (rt2x00_get_field32(word0, RXD_W0_CRC_ERROR))
181d6902 2103 rxdesc->flags |= RX_FLAG_FAILED_FCS_CRC;
95ea3627 2104
78b8f3b0
GW		 2105 rxdesc->cipher = rt2x00_get_field32(word0, RXD_W0_CIPHER_ALG);
2106 rxdesc->cipher_status = rt2x00_get_field32(word0, RXD_W0_CIPHER_ERROR);
61e754f4
ID		 2107
2108 if (rxdesc->cipher != CIPHER_NONE) {
1ce9cdac
ID		 2109 _rt2x00_desc_read(entry_priv->desc, 2, &rxdesc->iv[0]);
2110 _rt2x00_desc_read(entry_priv->desc, 3, &rxdesc->iv[1]);
74415edb
ID		 2111 rxdesc->dev_flags |= RXDONE_CRYPTO_IV;
2112
61e754f4 2113 _rt2x00_desc_read(entry_priv->desc, 4, &rxdesc->icv);
74415edb 2114 rxdesc->dev_flags |= RXDONE_CRYPTO_ICV;
61e754f4
ID		 2115
2116 /*
2117 * Hardware has stripped IV/EIV data from 802.11 frame during
b34e620f 2118 * decryption. It has provided the data separately but rt2x00lib
61e754f4
ID		 2119 * should decide if it should be reinserted.
2120 */
2121 rxdesc->flags |= RX_FLAG_IV_STRIPPED;
2122
2123 /*
a0aff623
GW		 2124 * The hardware has already checked the Michael Mic and has
2125 * stripped it from the frame. Signal this to mac80211.
61e754f4
ID		 2126 */
2127 rxdesc->flags |= RX_FLAG_MMIC_STRIPPED;
2128
2129 if (rxdesc->cipher_status == RX_CRYPTO_SUCCESS)
2130 rxdesc->flags |= RX_FLAG_DECRYPTED;
2131 else if (rxdesc->cipher_status == RX_CRYPTO_FAIL_MIC)
2132 rxdesc->flags |= RX_FLAG_MMIC_ERROR;
2133 }
2134
95ea3627
ID		 2135 /*
2136 * Obtain the status about this packet.
89993890
ID		 2137 * When frame was received with an OFDM bitrate,
2138 * the signal is the PLCP value. If it was received with
2139 * a CCK bitrate the signal is the rate in 100kbit/s.
95ea3627 2140 */
181d6902 2141 rxdesc->signal = rt2x00_get_field32(word1, RXD_W1_SIGNAL);
61e754f4 2142 rxdesc->rssi = rt61pci_agc_to_rssi(rt2x00dev, word1);
181d6902 2143 rxdesc->size = rt2x00_get_field32(word0, RXD_W0_DATABYTE_COUNT);
19d30e02 2144
19d30e02
ID		 2145 if (rt2x00_get_field32(word0, RXD_W0_OFDM))
2146 rxdesc->dev_flags |= RXDONE_SIGNAL_PLCP;
6c6aa3c0
ID		 2147 else
2148 rxdesc->dev_flags |= RXDONE_SIGNAL_BITRATE;
19d30e02
ID		 2149 if (rt2x00_get_field32(word0, RXD_W0_MY_BSS))
2150 rxdesc->dev_flags |= RXDONE_MY_BSS;
95ea3627
ID		 2151}
2152
2153/*
2154 * Interrupt functions.
2155 */
2156static void rt61pci_txdone(struct rt2x00_dev *rt2x00dev)
2157{
181d6902
ID		 2158 struct data_queue *queue;
2159 struct queue_entry *entry;
2160 struct queue_entry *entry_done;
1d6205d0 2161 struct queue_entry_priv_mmio *entry_priv;
181d6902 2162 struct txdone_entry_desc txdesc;
95ea3627
ID		 2163 u32 word;
2164 u32 reg;
95ea3627
ID		 2165 int type;
2166 int index;
e6474c3c 2167 int i;
95ea3627
ID		 2168
2169 /*
e6474c3c
ID		 2170 * TX_STA_FIFO is a stack of X entries, hence read TX_STA_FIFO
2171 * at most X times and also stop processing once the TX_STA_FIFO_VALID
2172 * flag is not set anymore.
2173 *
2174 * The legacy drivers use X=TX_RING_SIZE but state in a comment
2175 * that the TX_STA_FIFO stack has a size of 16. We stick to our
2176 * tx ring size for now.
95ea3627 2177 */
98cd6c71 2178 for (i = 0; i < rt2x00dev->tx->limit; i++) {
1d6205d0 2179 rt2x00mmio_register_read(rt2x00dev, STA_CSR4, &reg);
95ea3627
ID		 2180 if (!rt2x00_get_field32(reg, STA_CSR4_VALID))
2181 break;
2182
95ea3627
ID		 2183 /*
2184 * Skip this entry when it contains an invalid
181d6902 2185 * queue identication number.
95ea3627
ID		 2186 */
2187 type = rt2x00_get_field32(reg, STA_CSR4_PID_TYPE);
11f818e0 2188 queue = rt2x00queue_get_tx_queue(rt2x00dev, type);
181d6902 2189 if (unlikely(!queue))
95ea3627
ID		 2190 continue;
2191
2192 /*
2193 * Skip this entry when it contains an invalid
2194 * index number.
2195 */
2196 index = rt2x00_get_field32(reg, STA_CSR4_PID_SUBTYPE);
181d6902 2197 if (unlikely(index >= queue->limit))
95ea3627
ID		 2198 continue;
2199
181d6902 2200 entry = &queue->entries[index];
b8be63ff
ID		 2201 entry_priv = entry->priv_data;
2202 rt2x00_desc_read(entry_priv->desc, 0, &word);
95ea3627
ID		 2203
2204 if (rt2x00_get_field32(word, TXD_W0_OWNER_NIC) ||
2205 !rt2x00_get_field32(word, TXD_W0_VALID))
2206 return;
2207
181d6902 2208 entry_done = rt2x00queue_get_entry(queue, Q_INDEX_DONE);
62bc060b 2209 while (entry != entry_done) {
181d6902
ID		 2210 /* Catch up.
2211 * Just report any entries we missed as failed.
2212 */
ec9c4989
JP		 2213 rt2x00_warn(rt2x00dev, "TX status report missed for entry %d\n",
2214 entry_done->entry_idx);
181d6902 2215
65b7fc97 2216 rt2x00lib_txdone_noinfo(entry_done, TXDONE_UNKNOWN);
181d6902 2217 entry_done = rt2x00queue_get_entry(queue, Q_INDEX_DONE);
62bc060b
MN		 2218 }
2219
95ea3627
ID		 2220 /*
2221 * Obtain the status about this packet.
2222 */
fb55f4d1
ID		 2223 txdesc.flags = 0;
2224 switch (rt2x00_get_field32(reg, STA_CSR4_TX_RESULT)) {
2225 case 0: /* Success, maybe with retry */
2226 __set_bit(TXDONE_SUCCESS, &txdesc.flags);
2227 break;
2228 case 6: /* Failure, excessive retries */
2229 __set_bit(TXDONE_EXCESSIVE_RETRY, &txdesc.flags);
2230 /* Don't break, this is a failed frame! */
2231 default: /* Failure */
2232 __set_bit(TXDONE_FAILURE, &txdesc.flags);
2233 }
181d6902 2234 txdesc.retry = rt2x00_get_field32(reg, STA_CSR4_RETRY_COUNT);
95ea3627 2235
e1b4d7b7
ID		 2236 /*
2237 * the frame was retried at least once
2238 * -> hw used fallback rates
2239 */
2240 if (txdesc.retry)
2241 __set_bit(TXDONE_FALLBACK, &txdesc.flags);
2242
e513a0b6 2243 rt2x00lib_txdone(entry, &txdesc);
95ea3627
ID		 2244 }
2245}
2246
9e189446
GW		 2247static void rt61pci_wakeup(struct rt2x00_dev *rt2x00dev)
2248{
deee0214 2249 struct rt2x00lib_conf libconf = { .conf = &rt2x00dev->hw->conf };
9e189446
GW		 2250
2251 rt61pci_config(rt2x00dev, &libconf, IEEE80211_CONF_CHANGE_PS);
2252}
2253
7a5a681a
HS		 2254static inline void rt61pci_enable_interrupt(struct rt2x00_dev *rt2x00dev,
2255 struct rt2x00_field32 irq_field)
95ea3627 2256{
5846a550 2257 u32 reg;
95ea3627
ID		 2258
2259 /*
5846a550
HS		 2260 * Enable a single interrupt. The interrupt mask register
2261 * access needs locking.
95ea3627 2262 */
0aa13b2e 2263 spin_lock_irq(&rt2x00dev->irqmask_lock);
95ea3627 2264
1d6205d0 2265 rt2x00mmio_register_read(rt2x00dev, INT_MASK_CSR, &reg);
5846a550 2266 rt2x00_set_field32(&reg, irq_field, 0);
1d6205d0 2267 rt2x00mmio_register_write(rt2x00dev, INT_MASK_CSR, reg);
95ea3627 2268
0aa13b2e 2269 spin_unlock_irq(&rt2x00dev->irqmask_lock);
5846a550 2270}
95ea3627 2271
5846a550
HS		 2272static void rt61pci_enable_mcu_interrupt(struct rt2x00_dev *rt2x00dev,
2273 struct rt2x00_field32 irq_field)
2274{
5846a550 2275 u32 reg;
95ea3627 2276
9e189446 2277 /*
5846a550
HS		 2278 * Enable a single MCU interrupt. The interrupt mask register
2279 * access needs locking.
9e189446 2280 */
0aa13b2e 2281 spin_lock_irq(&rt2x00dev->irqmask_lock);
9e189446 2282
1d6205d0 2283 rt2x00mmio_register_read(rt2x00dev, MCU_INT_MASK_CSR, &reg);
5846a550 2284 rt2x00_set_field32(&reg, irq_field, 0);
1d6205d0 2285 rt2x00mmio_register_write(rt2x00dev, MCU_INT_MASK_CSR, reg);
fa43750f 2286
0aa13b2e 2287 spin_unlock_irq(&rt2x00dev->irqmask_lock);
95ea3627
ID		 2288}
2289
5846a550
HS		 2290static void rt61pci_txstatus_tasklet(unsigned long data)
2291{
2292 struct rt2x00_dev *rt2x00dev = (struct rt2x00_dev *)data;
2293 rt61pci_txdone(rt2x00dev);
abc11994
HS		 2294 if (test_bit(DEVICE_STATE_ENABLED_RADIO, &rt2x00dev->flags))
2295 rt61pci_enable_interrupt(rt2x00dev, INT_MASK_CSR_TXDONE);
5846a550
HS		 2296}
2297
2298static void rt61pci_tbtt_tasklet(unsigned long data)
2299{
2300 struct rt2x00_dev *rt2x00dev = (struct rt2x00_dev *)data;
2301 rt2x00lib_beacondone(rt2x00dev);
abc11994
HS		 2302 if (test_bit(DEVICE_STATE_ENABLED_RADIO, &rt2x00dev->flags))
2303 rt61pci_enable_interrupt(rt2x00dev, INT_MASK_CSR_BEACON_DONE);
5846a550
HS		 2304}
2305
2306static void rt61pci_rxdone_tasklet(unsigned long data)
2307{
2308 struct rt2x00_dev *rt2x00dev = (struct rt2x00_dev *)data;
1d6205d0 2309 if (rt2x00mmio_rxdone(rt2x00dev))
abc11994
HS		 2310 tasklet_schedule(&rt2x00dev->rxdone_tasklet);
2311 else if (test_bit(DEVICE_STATE_ENABLED_RADIO, &rt2x00dev->flags))
16638937 2312 rt61pci_enable_interrupt(rt2x00dev, INT_MASK_CSR_RXDONE);
5846a550
HS		 2313}
2314
2315static void rt61pci_autowake_tasklet(unsigned long data)
2316{
2317 struct rt2x00_dev *rt2x00dev = (struct rt2x00_dev *)data;
2318 rt61pci_wakeup(rt2x00dev);
1d6205d0
GJ		 2319 rt2x00mmio_register_write(rt2x00dev,
2320 M2H_CMD_DONE_CSR, 0xffffffff);
abc11994
HS		 2321 if (test_bit(DEVICE_STATE_ENABLED_RADIO, &rt2x00dev->flags))
2322 rt61pci_enable_mcu_interrupt(rt2x00dev, MCU_INT_MASK_CSR_TWAKEUP);
5846a550 2323}
78e256c9
HS		 2324
2325static irqreturn_t rt61pci_interrupt(int irq, void *dev_instance)
2326{
2327 struct rt2x00_dev *rt2x00dev = dev_instance;
5846a550
HS		 2328 u32 reg_mcu, mask_mcu;
2329 u32 reg, mask;
78e256c9
HS		 2330
2331 /*
2332 * Get the interrupt sources & saved to local variable.
2333 * Write register value back to clear pending interrupts.
2334 */
1d6205d0
GJ		 2335 rt2x00mmio_register_read(rt2x00dev, MCU_INT_SOURCE_CSR, &reg_mcu);
2336 rt2x00mmio_register_write(rt2x00dev, MCU_INT_SOURCE_CSR, reg_mcu);
78e256c9 2337
1d6205d0
GJ		 2338 rt2x00mmio_register_read(rt2x00dev, INT_SOURCE_CSR, &reg);
2339 rt2x00mmio_register_write(rt2x00dev, INT_SOURCE_CSR, reg);
78e256c9
HS		 2340
2341 if (!reg && !reg_mcu)
2342 return IRQ_NONE;
2343
2344 if (!test_bit(DEVICE_STATE_ENABLED_RADIO, &rt2x00dev->flags))
2345 return IRQ_HANDLED;
2346
5846a550
HS		 2347 /*
2348 * Schedule tasklets for interrupt handling.
2349 */
2350 if (rt2x00_get_field32(reg, INT_SOURCE_CSR_RXDONE))
2351 tasklet_schedule(&rt2x00dev->rxdone_tasklet);
2352
2353 if (rt2x00_get_field32(reg, INT_SOURCE_CSR_TXDONE))
2354 tasklet_schedule(&rt2x00dev->txstatus_tasklet);
2355
2356 if (rt2x00_get_field32(reg, INT_SOURCE_CSR_BEACON_DONE))
2357 tasklet_hi_schedule(&rt2x00dev->tbtt_tasklet);
2358
2359 if (rt2x00_get_field32(reg_mcu, MCU_INT_SOURCE_CSR_TWAKEUP))
2360 tasklet_schedule(&rt2x00dev->autowake_tasklet);
2361
2362 /*
2363 * Since INT_MASK_CSR and INT_SOURCE_CSR use the same bits
2364 * for interrupts and interrupt masks we can just use the value of
2365 * INT_SOURCE_CSR to create the interrupt mask.
2366 */
2367 mask = reg;
2368 mask_mcu = reg_mcu;
2369
2370 /*
2371 * Disable all interrupts for which a tasklet was scheduled right now,
2372 * the tasklet will reenable the appropriate interrupts.
2373 */
0aa13b2e 2374 spin_lock(&rt2x00dev->irqmask_lock);
5846a550 2375
1d6205d0 2376 rt2x00mmio_register_read(rt2x00dev, INT_MASK_CSR, &reg);
5846a550 2377 reg |= mask;
1d6205d0 2378 rt2x00mmio_register_write(rt2x00dev, INT_MASK_CSR, reg);
78e256c9 2379
1d6205d0 2380 rt2x00mmio_register_read(rt2x00dev, MCU_INT_MASK_CSR, &reg);
5846a550 2381 reg |= mask_mcu;
1d6205d0 2382 rt2x00mmio_register_write(rt2x00dev, MCU_INT_MASK_CSR, reg);
5846a550 2383
0aa13b2e 2384 spin_unlock(&rt2x00dev->irqmask_lock);
5846a550
HS		 2385
2386 return IRQ_HANDLED;
78e256c9
HS		 2387}
2388
95ea3627
ID		 2389/*
2390 * Device probe functions.
2391 */
2392static int rt61pci_validate_eeprom(struct rt2x00_dev *rt2x00dev)
2393{
2394 struct eeprom_93cx6 eeprom;
2395 u32 reg;
2396 u16 word;
2397 u8 *mac;
2398 s8 value;
2399
1d6205d0 2400 rt2x00mmio_register_read(rt2x00dev, E2PROM_CSR, &reg);
95ea3627
ID		 2401
2402 eeprom.data = rt2x00dev;
2403 eeprom.register_read = rt61pci_eepromregister_read;
2404 eeprom.register_write = rt61pci_eepromregister_write;
2405 eeprom.width = rt2x00_get_field32(reg, E2PROM_CSR_TYPE_93C46) ?
2406 PCI_EEPROM_WIDTH_93C46 : PCI_EEPROM_WIDTH_93C66;
2407 eeprom.reg_data_in = 0;
2408 eeprom.reg_data_out = 0;
2409 eeprom.reg_data_clock = 0;
2410 eeprom.reg_chip_select = 0;
2411
2412 eeprom_93cx6_multiread(&eeprom, EEPROM_BASE, rt2x00dev->eeprom,
2413 EEPROM_SIZE / sizeof(u16));
2414
2415 /*
2416 * Start validation of the data that has been read.
2417 */
2418 mac = rt2x00_eeprom_addr(rt2x00dev, EEPROM_MAC_ADDR_0);
2419 if (!is_valid_ether_addr(mac)) {
f4f7f414 2420 eth_random_addr(mac);
ec9c4989 2421 rt2x00_eeprom_dbg(rt2x00dev, "MAC: %pM\n", mac);
95ea3627
ID		 2422 }
2423
2424 rt2x00_eeprom_read(rt2x00dev, EEPROM_ANTENNA, &word);
2425 if (word == 0xffff) {
2426 rt2x00_set_field16(&word, EEPROM_ANTENNA_NUM, 2);
362f3b6b
ID		 2427 rt2x00_set_field16(&word, EEPROM_ANTENNA_TX_DEFAULT,
2428 ANTENNA_B);
2429 rt2x00_set_field16(&word, EEPROM_ANTENNA_RX_DEFAULT,
2430 ANTENNA_B);
95ea3627
ID		 2431 rt2x00_set_field16(&word, EEPROM_ANTENNA_FRAME_TYPE, 0);
2432 rt2x00_set_field16(&word, EEPROM_ANTENNA_DYN_TXAGC, 0);
2433 rt2x00_set_field16(&word, EEPROM_ANTENNA_HARDWARE_RADIO, 0);
2434 rt2x00_set_field16(&word, EEPROM_ANTENNA_RF_TYPE, RF5225);
2435 rt2x00_eeprom_write(rt2x00dev, EEPROM_ANTENNA, word);
ec9c4989 2436 rt2x00_eeprom_dbg(rt2x00dev, "Antenna: 0x%04x\n", word);
95ea3627
ID		 2437 }
2438
2439 rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC, &word);
2440 if (word == 0xffff) {
2441 rt2x00_set_field16(&word, EEPROM_NIC_ENABLE_DIVERSITY, 0);
2442 rt2x00_set_field16(&word, EEPROM_NIC_TX_DIVERSITY, 0);
91581b62
ID		 2443 rt2x00_set_field16(&word, EEPROM_NIC_RX_FIXED, 0);
2444 rt2x00_set_field16(&word, EEPROM_NIC_TX_FIXED, 0);
95ea3627
ID		 2445 rt2x00_set_field16(&word, EEPROM_NIC_EXTERNAL_LNA_BG, 0);
2446 rt2x00_set_field16(&word, EEPROM_NIC_CARDBUS_ACCEL, 0);
2447 rt2x00_set_field16(&word, EEPROM_NIC_EXTERNAL_LNA_A, 0);
2448 rt2x00_eeprom_write(rt2x00dev, EEPROM_NIC, word);
ec9c4989 2449 rt2x00_eeprom_dbg(rt2x00dev, "NIC: 0x%04x\n", word);
95ea3627
ID		 2450 }
2451
2452 rt2x00_eeprom_read(rt2x00dev, EEPROM_LED, &word);
2453 if (word == 0xffff) {
2454 rt2x00_set_field16(&word, EEPROM_LED_LED_MODE,
2455 LED_MODE_DEFAULT);
2456 rt2x00_eeprom_write(rt2x00dev, EEPROM_LED, word);
ec9c4989 2457 rt2x00_eeprom_dbg(rt2x00dev, "Led: 0x%04x\n", word);
95ea3627
ID		 2458 }
2459
2460 rt2x00_eeprom_read(rt2x00dev, EEPROM_FREQ, &word);
2461 if (word == 0xffff) {
2462 rt2x00_set_field16(&word, EEPROM_FREQ_OFFSET, 0);
2463 rt2x00_set_field16(&word, EEPROM_FREQ_SEQ, 0);
2464 rt2x00_eeprom_write(rt2x00dev, EEPROM_FREQ, word);
ec9c4989 2465 rt2x00_eeprom_dbg(rt2x00dev, "Freq: 0x%04x\n", word);
95ea3627
ID		 2466 }
2467
2468 rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_OFFSET_BG, &word);
2469 if (word == 0xffff) {
2470 rt2x00_set_field16(&word, EEPROM_RSSI_OFFSET_BG_1, 0);
2471 rt2x00_set_field16(&word, EEPROM_RSSI_OFFSET_BG_2, 0);
2472 rt2x00_eeprom_write(rt2x00dev, EEPROM_RSSI_OFFSET_BG, word);
ec9c4989 2473 rt2x00_eeprom_dbg(rt2x00dev, "RSSI OFFSET BG: 0x%04x\n", word);
95ea3627
ID		 2474 } else {
2475 value = rt2x00_get_field16(word, EEPROM_RSSI_OFFSET_BG_1);
2476 if (value < -10 || value > 10)
2477 rt2x00_set_field16(&word, EEPROM_RSSI_OFFSET_BG_1, 0);
2478 value = rt2x00_get_field16(word, EEPROM_RSSI_OFFSET_BG_2);
2479 if (value < -10 || value > 10)
2480 rt2x00_set_field16(&word, EEPROM_RSSI_OFFSET_BG_2, 0);
2481 rt2x00_eeprom_write(rt2x00dev, EEPROM_RSSI_OFFSET_BG, word);
2482 }
2483
2484 rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_OFFSET_A, &word);
2485 if (word == 0xffff) {
2486 rt2x00_set_field16(&word, EEPROM_RSSI_OFFSET_A_1, 0);
2487 rt2x00_set_field16(&word, EEPROM_RSSI_OFFSET_A_2, 0);
2488 rt2x00_eeprom_write(rt2x00dev, EEPROM_RSSI_OFFSET_A, word);
ec9c4989 2489 rt2x00_eeprom_dbg(rt2x00dev, "RSSI OFFSET A: 0x%04x\n", word);
95ea3627
ID		 2490 } else {
2491 value = rt2x00_get_field16(word, EEPROM_RSSI_OFFSET_A_1);
2492 if (value < -10 || value > 10)
2493 rt2x00_set_field16(&word, EEPROM_RSSI_OFFSET_A_1, 0);
2494 value = rt2x00_get_field16(word, EEPROM_RSSI_OFFSET_A_2);
2495 if (value < -10 || value > 10)
2496 rt2x00_set_field16(&word, EEPROM_RSSI_OFFSET_A_2, 0);
2497 rt2x00_eeprom_write(rt2x00dev, EEPROM_RSSI_OFFSET_A, word);
2498 }
2499
2500 return 0;
2501}
2502
2503static int rt61pci_init_eeprom(struct rt2x00_dev *rt2x00dev)
2504{
2505 u32 reg;
2506 u16 value;
2507 u16 eeprom;
95ea3627
ID		 2508
2509 /*
2510 * Read EEPROM word for configuration.
2511 */
2512 rt2x00_eeprom_read(rt2x00dev, EEPROM_ANTENNA, &eeprom);
2513
2514 /*
2515 * Identify RF chipset.
95ea3627 2516 */
95ea3627 2517 value = rt2x00_get_field16(eeprom, EEPROM_ANTENNA_RF_TYPE);
1d6205d0 2518 rt2x00mmio_register_read(rt2x00dev, MAC_CSR0, &reg);
49e721ec
GW		 2519 rt2x00_set_chip(rt2x00dev, rt2x00_get_field32(reg, MAC_CSR0_CHIPSET),
2520 value, rt2x00_get_field32(reg, MAC_CSR0_REVISION));
95ea3627 2521
5122d898
GW		 2522 if (!rt2x00_rf(rt2x00dev, RF5225) &&
2523 !rt2x00_rf(rt2x00dev, RF5325) &&
2524 !rt2x00_rf(rt2x00dev, RF2527) &&
2525 !rt2x00_rf(rt2x00dev, RF2529)) {
ec9c4989 2526 rt2x00_err(rt2x00dev, "Invalid RF chipset detected\n");
95ea3627
ID		 2527 return -ENODEV;
2528 }
2529
e4cd2ff8 2530 /*
49513481 2531 * Determine number of antennas.
e4cd2ff8
ID		 2532 */
2533 if (rt2x00_get_field16(eeprom, EEPROM_ANTENNA_NUM) == 2)
7dab73b3 2534 __set_bit(CAPABILITY_DOUBLE_ANTENNA, &rt2x00dev->cap_flags);
e4cd2ff8 2535
95ea3627
ID		 2536 /*
2537 * Identify default antenna configuration.
2538 */
addc81bd 2539 rt2x00dev->default_ant.tx =
95ea3627 2540 rt2x00_get_field16(eeprom, EEPROM_ANTENNA_TX_DEFAULT);
addc81bd 2541 rt2x00dev->default_ant.rx =
95ea3627
ID		 2542 rt2x00_get_field16(eeprom, EEPROM_ANTENNA_RX_DEFAULT);
2543
2544 /*
2545 * Read the Frame type.
2546 */
2547 if (rt2x00_get_field16(eeprom, EEPROM_ANTENNA_FRAME_TYPE))
7dab73b3 2548 __set_bit(CAPABILITY_FRAME_TYPE, &rt2x00dev->cap_flags);
95ea3627 2549
95ea3627 2550 /*
b34e620f 2551 * Detect if this device has a hardware controlled radio.
95ea3627
ID		 2552 */
2553 if (rt2x00_get_field16(eeprom, EEPROM_ANTENNA_HARDWARE_RADIO))
7dab73b3 2554 __set_bit(CAPABILITY_HW_BUTTON, &rt2x00dev->cap_flags);
95ea3627
ID		 2555
2556 /*
2557 * Read frequency offset and RF programming sequence.
2558 */
2559 rt2x00_eeprom_read(rt2x00dev, EEPROM_FREQ, &eeprom);
2560 if (rt2x00_get_field16(eeprom, EEPROM_FREQ_SEQ))
7dab73b3 2561 __set_bit(CAPABILITY_RF_SEQUENCE, &rt2x00dev->cap_flags);
95ea3627
ID		 2562
2563 rt2x00dev->freq_offset = rt2x00_get_field16(eeprom, EEPROM_FREQ_OFFSET);
2564
2565 /*
2566 * Read external LNA informations.
2567 */
2568 rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC, &eeprom);
2569
2570 if (rt2x00_get_field16(eeprom, EEPROM_NIC_EXTERNAL_LNA_A))
7dab73b3 2571 __set_bit(CAPABILITY_EXTERNAL_LNA_A, &rt2x00dev->cap_flags);
95ea3627 2572 if (rt2x00_get_field16(eeprom, EEPROM_NIC_EXTERNAL_LNA_BG))
7dab73b3 2573 __set_bit(CAPABILITY_EXTERNAL_LNA_BG, &rt2x00dev->cap_flags);
95ea3627 2574
e4cd2ff8 2575 /*
b34e620f 2576 * When working with a RF2529 chip without double antenna,
e4cd2ff8
ID		 2577 * the antenna settings should be gathered from the NIC
2578 * eeprom word.
2579 */
5122d898 2580 if (rt2x00_rf(rt2x00dev, RF2529) &&
7dab73b3 2581 !test_bit(CAPABILITY_DOUBLE_ANTENNA, &rt2x00dev->cap_flags)) {
91581b62
ID		 2582 rt2x00dev->default_ant.rx =
2583 ANTENNA_A + rt2x00_get_field16(eeprom, EEPROM_NIC_RX_FIXED);
2584 rt2x00dev->default_ant.tx =
2585 ANTENNA_B - rt2x00_get_field16(eeprom, EEPROM_NIC_TX_FIXED);
e4cd2ff8
ID		 2586
2587 if (rt2x00_get_field16(eeprom, EEPROM_NIC_TX_DIVERSITY))
2588 rt2x00dev->default_ant.tx = ANTENNA_SW_DIVERSITY;
2589 if (rt2x00_get_field16(eeprom, EEPROM_NIC_ENABLE_DIVERSITY))
2590 rt2x00dev->default_ant.rx = ANTENNA_SW_DIVERSITY;
2591 }
2592
95ea3627
ID		 2593 /*
2594 * Store led settings, for correct led behaviour.
2595 * If the eeprom value is invalid,
2596 * switch to default led mode.
2597 */
771fd565 2598#ifdef CONFIG_RT2X00_LIB_LEDS
95ea3627 2599 rt2x00_eeprom_read(rt2x00dev, EEPROM_LED, &eeprom);
a9450b70
ID		 2600 value = rt2x00_get_field16(eeprom, EEPROM_LED_LED_MODE);
2601
475433be
ID		 2602 rt61pci_init_led(rt2x00dev, &rt2x00dev->led_radio, LED_TYPE_RADIO);
2603 rt61pci_init_led(rt2x00dev, &rt2x00dev->led_assoc, LED_TYPE_ASSOC);
2604 if (value == LED_MODE_SIGNAL_STRENGTH)
2605 rt61pci_init_led(rt2x00dev, &rt2x00dev->led_qual,
2606 LED_TYPE_QUALITY);
95ea3627 2607
a9450b70
ID		 2608 rt2x00_set_field16(&rt2x00dev->led_mcu_reg, MCU_LEDCS_LED_MODE, value);
2609 rt2x00_set_field16(&rt2x00dev->led_mcu_reg, MCU_LEDCS_POLARITY_GPIO_0,
95ea3627
ID		 2610 rt2x00_get_field16(eeprom,
2611 EEPROM_LED_POLARITY_GPIO_0));
a9450b70 2612 rt2x00_set_field16(&rt2x00dev->led_mcu_reg, MCU_LEDCS_POLARITY_GPIO_1,
95ea3627
ID		 2613 rt2x00_get_field16(eeprom,
2614 EEPROM_LED_POLARITY_GPIO_1));
a9450b70 2615 rt2x00_set_field16(&rt2x00dev->led_mcu_reg, MCU_LEDCS_POLARITY_GPIO_2,
95ea3627
ID		 2616 rt2x00_get_field16(eeprom,
2617 EEPROM_LED_POLARITY_GPIO_2));
a9450b70 2618 rt2x00_set_field16(&rt2x00dev->led_mcu_reg, MCU_LEDCS_POLARITY_GPIO_3,
95ea3627
ID		 2619 rt2x00_get_field16(eeprom,
2620 EEPROM_LED_POLARITY_GPIO_3));
a9450b70 2621 rt2x00_set_field16(&rt2x00dev->led_mcu_reg, MCU_LEDCS_POLARITY_GPIO_4,
95ea3627
ID		 2622 rt2x00_get_field16(eeprom,
2623 EEPROM_LED_POLARITY_GPIO_4));
a9450b70 2624 rt2x00_set_field16(&rt2x00dev->led_mcu_reg, MCU_LEDCS_POLARITY_ACT,
95ea3627 2625 rt2x00_get_field16(eeprom, EEPROM_LED_POLARITY_ACT));
a9450b70 2626 rt2x00_set_field16(&rt2x00dev->led_mcu_reg, MCU_LEDCS_POLARITY_READY_BG,
95ea3627
ID		 2627 rt2x00_get_field16(eeprom,
2628 EEPROM_LED_POLARITY_RDY_G));
a9450b70 2629 rt2x00_set_field16(&rt2x00dev->led_mcu_reg, MCU_LEDCS_POLARITY_READY_A,
95ea3627
ID		 2630 rt2x00_get_field16(eeprom,
2631 EEPROM_LED_POLARITY_RDY_A));
771fd565 2632#endif /* CONFIG_RT2X00_LIB_LEDS */
95ea3627
ID		 2633
2634 return 0;
2635}
2636
2637/*
2638 * RF value list for RF5225 & RF5325
2639 * Supports: 2.4 GHz & 5.2 GHz, rf_sequence disabled
2640 */
2641static const struct rf_channel rf_vals_noseq[] = {
2642 { 1, 0x00002ccc, 0x00004786, 0x00068455, 0x000ffa0b },
2643 { 2, 0x00002ccc, 0x00004786, 0x00068455, 0x000ffa1f },
2644 { 3, 0x00002ccc, 0x0000478a, 0x00068455, 0x000ffa0b },
2645 { 4, 0x00002ccc, 0x0000478a, 0x00068455, 0x000ffa1f },
2646 { 5, 0x00002ccc, 0x0000478e, 0x00068455, 0x000ffa0b },
2647 { 6, 0x00002ccc, 0x0000478e, 0x00068455, 0x000ffa1f },
2648 { 7, 0x00002ccc, 0x00004792, 0x00068455, 0x000ffa0b },
2649 { 8, 0x00002ccc, 0x00004792, 0x00068455, 0x000ffa1f },
2650 { 9, 0x00002ccc, 0x00004796, 0x00068455, 0x000ffa0b },
2651 { 10, 0x00002ccc, 0x00004796, 0x00068455, 0x000ffa1f },
2652 { 11, 0x00002ccc, 0x0000479a, 0x00068455, 0x000ffa0b },
2653 { 12, 0x00002ccc, 0x0000479a, 0x00068455, 0x000ffa1f },
2654 { 13, 0x00002ccc, 0x0000479e, 0x00068455, 0x000ffa0b },
2655 { 14, 0x00002ccc, 0x000047a2, 0x00068455, 0x000ffa13 },
2656
2657 /* 802.11 UNI / HyperLan 2 */
2658 { 36, 0x00002ccc, 0x0000499a, 0x0009be55, 0x000ffa23 },
2659 { 40, 0x00002ccc, 0x000049a2, 0x0009be55, 0x000ffa03 },
2660 { 44, 0x00002ccc, 0x000049a6, 0x0009be55, 0x000ffa0b },
2661 { 48, 0x00002ccc, 0x000049aa, 0x0009be55, 0x000ffa13 },
2662 { 52, 0x00002ccc, 0x000049ae, 0x0009ae55, 0x000ffa1b },
2663 { 56, 0x00002ccc, 0x000049b2, 0x0009ae55, 0x000ffa23 },
2664 { 60, 0x00002ccc, 0x000049ba, 0x0009ae55, 0x000ffa03 },
2665 { 64, 0x00002ccc, 0x000049be, 0x0009ae55, 0x000ffa0b },
2666
2667 /* 802.11 HyperLan 2 */
2668 { 100, 0x00002ccc, 0x00004a2a, 0x000bae55, 0x000ffa03 },
2669 { 104, 0x00002ccc, 0x00004a2e, 0x000bae55, 0x000ffa0b },
2670 { 108, 0x00002ccc, 0x00004a32, 0x000bae55, 0x000ffa13 },
2671 { 112, 0x00002ccc, 0x00004a36, 0x000bae55, 0x000ffa1b },
2672 { 116, 0x00002ccc, 0x00004a3a, 0x000bbe55, 0x000ffa23 },
2673 { 120, 0x00002ccc, 0x00004a82, 0x000bbe55, 0x000ffa03 },
2674 { 124, 0x00002ccc, 0x00004a86, 0x000bbe55, 0x000ffa0b },
2675 { 128, 0x00002ccc, 0x00004a8a, 0x000bbe55, 0x000ffa13 },
2676 { 132, 0x00002ccc, 0x00004a8e, 0x000bbe55, 0x000ffa1b },
2677 { 136, 0x00002ccc, 0x00004a92, 0x000bbe55, 0x000ffa23 },
2678
2679 /* 802.11 UNII */
2680 { 140, 0x00002ccc, 0x00004a9a, 0x000bbe55, 0x000ffa03 },
2681 { 149, 0x00002ccc, 0x00004aa2, 0x000bbe55, 0x000ffa1f },
2682 { 153, 0x00002ccc, 0x00004aa6, 0x000bbe55, 0x000ffa27 },
2683 { 157, 0x00002ccc, 0x00004aae, 0x000bbe55, 0x000ffa07 },
2684 { 161, 0x00002ccc, 0x00004ab2, 0x000bbe55, 0x000ffa0f },
2685 { 165, 0x00002ccc, 0x00004ab6, 0x000bbe55, 0x000ffa17 },
2686
2687 /* MMAC(Japan)J52 ch 34,38,42,46 */
2688 { 34, 0x00002ccc, 0x0000499a, 0x0009be55, 0x000ffa0b },
2689 { 38, 0x00002ccc, 0x0000499e, 0x0009be55, 0x000ffa13 },
2690 { 42, 0x00002ccc, 0x000049a2, 0x0009be55, 0x000ffa1b },
2691 { 46, 0x00002ccc, 0x000049a6, 0x0009be55, 0x000ffa23 },
2692};
2693
2694/*
2695 * RF value list for RF5225 & RF5325
2696 * Supports: 2.4 GHz & 5.2 GHz, rf_sequence enabled
2697 */
2698static const struct rf_channel rf_vals_seq[] = {
2699 { 1, 0x00002ccc, 0x00004786, 0x00068455, 0x000ffa0b },
2700 { 2, 0x00002ccc, 0x00004786, 0x00068455, 0x000ffa1f },
2701 { 3, 0x00002ccc, 0x0000478a, 0x00068455, 0x000ffa0b },
2702 { 4, 0x00002ccc, 0x0000478a, 0x00068455, 0x000ffa1f },
2703 { 5, 0x00002ccc, 0x0000478e, 0x00068455, 0x000ffa0b },
2704 { 6, 0x00002ccc, 0x0000478e, 0x00068455, 0x000ffa1f },
2705 { 7, 0x00002ccc, 0x00004792, 0x00068455, 0x000ffa0b },
2706 { 8, 0x00002ccc, 0x00004792, 0x00068455, 0x000ffa1f },
2707 { 9, 0x00002ccc, 0x00004796, 0x00068455, 0x000ffa0b },
2708 { 10, 0x00002ccc, 0x00004796, 0x00068455, 0x000ffa1f },
2709 { 11, 0x00002ccc, 0x0000479a, 0x00068455, 0x000ffa0b },
2710 { 12, 0x00002ccc, 0x0000479a, 0x00068455, 0x000ffa1f },
2711 { 13, 0x00002ccc, 0x0000479e, 0x00068455, 0x000ffa0b },
2712 { 14, 0x00002ccc, 0x000047a2, 0x00068455, 0x000ffa13 },
2713
2714 /* 802.11 UNI / HyperLan 2 */
2715 { 36, 0x00002cd4, 0x0004481a, 0x00098455, 0x000c0a03 },
2716 { 40, 0x00002cd0, 0x00044682, 0x00098455, 0x000c0a03 },
2717 { 44, 0x00002cd0, 0x00044686, 0x00098455, 0x000c0a1b },
2718 { 48, 0x00002cd0, 0x0004468e, 0x00098655, 0x000c0a0b },
2719 { 52, 0x00002cd0, 0x00044692, 0x00098855, 0x000c0a23 },
2720 { 56, 0x00002cd0, 0x0004469a, 0x00098c55, 0x000c0a13 },
2721 { 60, 0x00002cd0, 0x000446a2, 0x00098e55, 0x000c0a03 },
2722 { 64, 0x00002cd0, 0x000446a6, 0x00099255, 0x000c0a1b },
2723
2724 /* 802.11 HyperLan 2 */
2725 { 100, 0x00002cd4, 0x0004489a, 0x000b9855, 0x000c0a03 },
2726 { 104, 0x00002cd4, 0x000448a2, 0x000b9855, 0x000c0a03 },
2727 { 108, 0x00002cd4, 0x000448aa, 0x000b9855, 0x000c0a03 },
2728 { 112, 0x00002cd4, 0x000448b2, 0x000b9a55, 0x000c0a03 },
2729 { 116, 0x00002cd4, 0x000448ba, 0x000b9a55, 0x000c0a03 },
2730 { 120, 0x00002cd0, 0x00044702, 0x000b9a55, 0x000c0a03 },
2731 { 124, 0x00002cd0, 0x00044706, 0x000b9a55, 0x000c0a1b },
2732 { 128, 0x00002cd0, 0x0004470e, 0x000b9c55, 0x000c0a0b },
2733 { 132, 0x00002cd0, 0x00044712, 0x000b9c55, 0x000c0a23 },
2734 { 136, 0x00002cd0, 0x0004471a, 0x000b9e55, 0x000c0a13 },
2735
2736 /* 802.11 UNII */
2737 { 140, 0x00002cd0, 0x00044722, 0x000b9e55, 0x000c0a03 },
2738 { 149, 0x00002cd0, 0x0004472e, 0x000ba255, 0x000c0a1b },
2739 { 153, 0x00002cd0, 0x00044736, 0x000ba255, 0x000c0a0b },
2740 { 157, 0x00002cd4, 0x0004490a, 0x000ba255, 0x000c0a17 },
2741 { 161, 0x00002cd4, 0x00044912, 0x000ba255, 0x000c0a17 },
2742 { 165, 0x00002cd4, 0x0004491a, 0x000ba255, 0x000c0a17 },
2743
2744 /* MMAC(Japan)J52 ch 34,38,42,46 */
2745 { 34, 0x00002ccc, 0x0000499a, 0x0009be55, 0x000c0a0b },
2746 { 38, 0x00002ccc, 0x0000499e, 0x0009be55, 0x000c0a13 },
2747 { 42, 0x00002ccc, 0x000049a2, 0x0009be55, 0x000c0a1b },
2748 { 46, 0x00002ccc, 0x000049a6, 0x0009be55, 0x000c0a23 },
2749};
2750
8c5e7a5f 2751static int rt61pci_probe_hw_mode(struct rt2x00_dev *rt2x00dev)
95ea3627
ID		 2752{
2753 struct hw_mode_spec *spec = &rt2x00dev->spec;
8c5e7a5f
ID		 2754 struct channel_info *info;
2755 char *tx_power;
95ea3627
ID		 2756 unsigned int i;
2757
93b6bd26
GW		 2758 /*
2759 * Disable powersaving as default.
2760 */
2761 rt2x00dev->hw->wiphy->flags &= ~WIPHY_FLAG_PS_ON_BY_DEFAULT;
2762
95ea3627
ID		 2763 /*
2764 * Initialize all hw fields.
2765 */
2766 rt2x00dev->hw->flags =
566bfe5a 2767 IEEE80211_HW_HOST_BROADCAST_PS_BUFFERING |
4be8c387
JB		 2768 IEEE80211_HW_SIGNAL_DBM |
2769 IEEE80211_HW_SUPPORTS_PS |
2770 IEEE80211_HW_PS_NULLFUNC_STACK;
95ea3627 2771
14a3bf89 2772 SET_IEEE80211_DEV(rt2x00dev->hw, rt2x00dev->dev);
95ea3627
ID		 2773 SET_IEEE80211_PERM_ADDR(rt2x00dev->hw,
2774 rt2x00_eeprom_addr(rt2x00dev,
2775 EEPROM_MAC_ADDR_0));
2776
95ea3627 2777 /*
e1b4d7b7
ID		 2778 * As rt61 has a global fallback table we cannot specify
2779 * more then one tx rate per frame but since the hw will
2780 * try several rates (based on the fallback table) we should
ba3b9e5e 2781 * initialize max_report_rates to the maximum number of rates
e1b4d7b7
ID		 2782 * we are going to try. Otherwise mac80211 will truncate our
2783 * reported tx rates and the rc algortihm will end up with
2784 * incorrect data.
2785 */
ba3b9e5e
HS		 2786 rt2x00dev->hw->max_rates = 1;
2787 rt2x00dev->hw->max_report_rates = 7;
e1b4d7b7
ID		 2788 rt2x00dev->hw->max_rate_tries = 1;
2789
2790 /*
95ea3627
ID		 2791 * Initialize hw_mode information.
2792 */
31562e80
ID		 2793 spec->supported_bands = SUPPORT_BAND_2GHZ;
2794 spec->supported_rates = SUPPORT_RATE_CCK | SUPPORT_RATE_OFDM;
95ea3627 2795
7dab73b3 2796 if (!test_bit(CAPABILITY_RF_SEQUENCE, &rt2x00dev->cap_flags)) {
95ea3627
ID		 2797 spec->num_channels = 14;
2798 spec->channels = rf_vals_noseq;
2799 } else {
2800 spec->num_channels = 14;
2801 spec->channels = rf_vals_seq;
2802 }
2803
5122d898 2804 if (rt2x00_rf(rt2x00dev, RF5225) || rt2x00_rf(rt2x00dev, RF5325)) {
31562e80 2805 spec->supported_bands |= SUPPORT_BAND_5GHZ;
95ea3627 2806 spec->num_channels = ARRAY_SIZE(rf_vals_seq);
8c5e7a5f
ID		 2807 }
2808
2809 /*
2810 * Create channel information array
2811 */
baeb2ffa 2812 info = kcalloc(spec->num_channels, sizeof(*info), GFP_KERNEL);
8c5e7a5f
ID		 2813 if (!info)
2814 return -ENOMEM;
2815
2816 spec->channels_info = info;
95ea3627 2817
8c5e7a5f 2818 tx_power = rt2x00_eeprom_addr(rt2x00dev, EEPROM_TXPOWER_G_START);
8d1331b3
ID		 2819 for (i = 0; i < 14; i++) {
2820 info[i].max_power = MAX_TXPOWER;
2821 info[i].default_power1 = TXPOWER_FROM_DEV(tx_power[i]);
2822 }
95ea3627 2823
8c5e7a5f
ID		 2824 if (spec->num_channels > 14) {
2825 tx_power = rt2x00_eeprom_addr(rt2x00dev, EEPROM_TXPOWER_A_START);
8d1331b3
ID		 2826 for (i = 14; i < spec->num_channels; i++) {
2827 info[i].max_power = MAX_TXPOWER;
0a6f3a8e
GJ		 2828 info[i].default_power1 =
2829 TXPOWER_FROM_DEV(tx_power[i - 14]);
8d1331b3 2830 }
95ea3627 2831 }
8c5e7a5f
ID		 2832
2833 return 0;
95ea3627
ID		 2834}
2835
2836static int rt61pci_probe_hw(struct rt2x00_dev *rt2x00dev)
2837{
2838 int retval;
a396e100 2839 u32 reg;
95ea3627 2840
117839bd
PR		 2841 /*
2842 * Disable power saving.
2843 */
1d6205d0 2844 rt2x00mmio_register_write(rt2x00dev, SOFT_RESET_CSR, 0x00000007);
117839bd 2845
95ea3627
ID		 2846 /*
2847 * Allocate eeprom data.
2848 */
2849 retval = rt61pci_validate_eeprom(rt2x00dev);
2850 if (retval)
2851 return retval;
2852
2853 retval = rt61pci_init_eeprom(rt2x00dev);
2854 if (retval)
2855 return retval;
2856
a396e100
GW		 2857 /*
2858 * Enable rfkill polling by setting GPIO direction of the
2859 * rfkill switch GPIO pin correctly.
2860 */
1d6205d0 2861 rt2x00mmio_register_read(rt2x00dev, MAC_CSR13, &reg);
99bdf51a 2862 rt2x00_set_field32(&reg, MAC_CSR13_DIR5, 1);
1d6205d0 2863 rt2x00mmio_register_write(rt2x00dev, MAC_CSR13, reg);
a396e100 2864
95ea3627
ID		 2865 /*
2866 * Initialize hw specifications.
2867 */
8c5e7a5f
ID		 2868 retval = rt61pci_probe_hw_mode(rt2x00dev);
2869 if (retval)
2870 return retval;
95ea3627 2871
1afcfd54
IP		 2872 /*
2873 * This device has multiple filters for control frames,
2874 * but has no a separate filter for PS Poll frames.
2875 */
7dab73b3 2876 __set_bit(CAPABILITY_CONTROL_FILTERS, &rt2x00dev->cap_flags);
1afcfd54 2877
95ea3627 2878 /*
c4da0048 2879 * This device requires firmware and DMA mapped skbs.
95ea3627 2880 */
7dab73b3
ID		 2881 __set_bit(REQUIRE_FIRMWARE, &rt2x00dev->cap_flags);
2882 __set_bit(REQUIRE_DMA, &rt2x00dev->cap_flags);
008c4482 2883 if (!modparam_nohwcrypt)
7dab73b3
ID		 2884 __set_bit(CAPABILITY_HW_CRYPTO, &rt2x00dev->cap_flags);
2885 __set_bit(CAPABILITY_LINK_TUNING, &rt2x00dev->cap_flags);
95ea3627
ID		 2886
2887 /*
2888 * Set the rssi offset.
2889 */
2890 rt2x00dev->rssi_offset = DEFAULT_RSSI_OFFSET;
2891
2892 return 0;
2893}
2894
2895/*
2896 * IEEE80211 stack callback functions.
2897 */
8a3a3c85
EP		 2898static int rt61pci_conf_tx(struct ieee80211_hw *hw,
2899 struct ieee80211_vif *vif, u16 queue_idx,
2af0a570
ID		 2900 const struct ieee80211_tx_queue_params *params)
2901{
2902 struct rt2x00_dev *rt2x00dev = hw->priv;
2903 struct data_queue *queue;
2904 struct rt2x00_field32 field;
2905 int retval;
2906 u32 reg;
5e790023 2907 u32 offset;
2af0a570
ID		 2908
2909 /*
2910 * First pass the configuration through rt2x00lib, that will
2911 * update the queue settings and validate the input. After that
2912 * we are free to update the registers based on the value
2913 * in the queue parameter.
2914 */
8a3a3c85 2915 retval = rt2x00mac_conf_tx(hw, vif, queue_idx, params);
2af0a570
ID		 2916 if (retval)
2917 return retval;
2918
5e790023
ID		 2919 /*
2920 * We only need to perform additional register initialization
b34e620f 2921 * for WMM queues.
5e790023
ID		 2922 */
2923 if (queue_idx >= 4)
2924 return 0;
2925
11f818e0 2926 queue = rt2x00queue_get_tx_queue(rt2x00dev, queue_idx);
2af0a570
ID		 2927
2928 /* Update WMM TXOP register */
5e790023
ID		 2929 offset = AC_TXOP_CSR0 + (sizeof(u32) * (!!(queue_idx & 2)));
2930 field.bit_offset = (queue_idx & 1) * 16;
2931 field.bit_mask = 0xffff << field.bit_offset;
2932
1d6205d0 2933 rt2x00mmio_register_read(rt2x00dev, offset, &reg);
5e790023 2934 rt2x00_set_field32(&reg, field, queue->txop);
1d6205d0 2935 rt2x00mmio_register_write(rt2x00dev, offset, reg);
2af0a570
ID		 2936
2937 /* Update WMM registers */
2938 field.bit_offset = queue_idx * 4;
2939 field.bit_mask = 0xf << field.bit_offset;
2940
1d6205d0 2941 rt2x00mmio_register_read(rt2x00dev, AIFSN_CSR, &reg);
2af0a570 2942 rt2x00_set_field32(&reg, field, queue->aifs);
1d6205d0 2943 rt2x00mmio_register_write(rt2x00dev, AIFSN_CSR, reg);
2af0a570 2944
1d6205d0 2945 rt2x00mmio_register_read(rt2x00dev, CWMIN_CSR, &reg);
2af0a570 2946 rt2x00_set_field32(&reg, field, queue->cw_min);
1d6205d0 2947 rt2x00mmio_register_write(rt2x00dev, CWMIN_CSR, reg);
2af0a570 2948
1d6205d0 2949 rt2x00mmio_register_read(rt2x00dev, CWMAX_CSR, &reg);
2af0a570 2950 rt2x00_set_field32(&reg, field, queue->cw_max);
1d6205d0 2951 rt2x00mmio_register_write(rt2x00dev, CWMAX_CSR, reg);
2af0a570
ID		 2952
2953 return 0;
2954}
2955
37a41b4a 2956static u64 rt61pci_get_tsf(struct ieee80211_hw *hw, struct ieee80211_vif *vif)
95ea3627
ID		 2957{
2958 struct rt2x00_dev *rt2x00dev = hw->priv;
2959 u64 tsf;
2960 u32 reg;
2961
1d6205d0 2962 rt2x00mmio_register_read(rt2x00dev, TXRX_CSR13, &reg);
95ea3627 2963 tsf = (u64) rt2x00_get_field32(reg, TXRX_CSR13_HIGH_TSFTIMER) << 32;
1d6205d0 2964 rt2x00mmio_register_read(rt2x00dev, TXRX_CSR12, &reg);
95ea3627
ID		 2965 tsf |= rt2x00_get_field32(reg, TXRX_CSR12_LOW_TSFTIMER);
2966
2967 return tsf;
2968}
2969
95ea3627
ID		 2970static const struct ieee80211_ops rt61pci_mac80211_ops = {
2971 .tx = rt2x00mac_tx,
4150c572
JB		 2972 .start = rt2x00mac_start,
2973 .stop = rt2x00mac_stop,
95ea3627
ID		 2974 .add_interface = rt2x00mac_add_interface,
2975 .remove_interface = rt2x00mac_remove_interface,
2976 .config = rt2x00mac_config,
3a643d24 2977 .configure_filter = rt2x00mac_configure_filter,
61e754f4 2978 .set_key = rt2x00mac_set_key,
d8147f9d
ID		 2979 .sw_scan_start = rt2x00mac_sw_scan_start,
2980 .sw_scan_complete = rt2x00mac_sw_scan_complete,
95ea3627 2981 .get_stats = rt2x00mac_get_stats,
471b3efd 2982 .bss_info_changed = rt2x00mac_bss_info_changed,
2af0a570 2983 .conf_tx = rt61pci_conf_tx,
95ea3627 2984 .get_tsf = rt61pci_get_tsf,
e47a5cdd 2985 .rfkill_poll = rt2x00mac_rfkill_poll,
f44df18c 2986 .flush = rt2x00mac_flush,
0ed7b3c0
ID		 2987 .set_antenna = rt2x00mac_set_antenna,
2988 .get_antenna = rt2x00mac_get_antenna,
e7dee444 2989 .get_ringparam = rt2x00mac_get_ringparam,
5f0dd296 2990 .tx_frames_pending = rt2x00mac_tx_frames_pending,
95ea3627
ID		 2991};
2992
2993static const struct rt2x00lib_ops rt61pci_rt2x00_ops = {
2994 .irq_handler = rt61pci_interrupt,
5846a550
HS		 2995 .txstatus_tasklet = rt61pci_txstatus_tasklet,
2996 .tbtt_tasklet = rt61pci_tbtt_tasklet,
2997 .rxdone_tasklet = rt61pci_rxdone_tasklet,
2998 .autowake_tasklet = rt61pci_autowake_tasklet,
95ea3627
ID		 2999 .probe_hw = rt61pci_probe_hw,
3000 .get_firmware_name = rt61pci_get_firmware_name,
0cbe0064 3001 .check_firmware = rt61pci_check_firmware,
95ea3627 3002 .load_firmware = rt61pci_load_firmware,
1d6205d0
GJ		 3003 .initialize = rt2x00mmio_initialize,
3004 .uninitialize = rt2x00mmio_uninitialize,
798b7adb
ID		 3005 .get_entry_state = rt61pci_get_entry_state,
3006 .clear_entry = rt61pci_clear_entry,
95ea3627 3007 .set_device_state = rt61pci_set_device_state,
95ea3627 3008 .rfkill_poll = rt61pci_rfkill_poll,
95ea3627
ID		 3009 .link_stats = rt61pci_link_stats,
3010 .reset_tuner = rt61pci_reset_tuner,
3011 .link_tuner = rt61pci_link_tuner,
dbba306f
ID		 3012 .start_queue = rt61pci_start_queue,
3013 .kick_queue = rt61pci_kick_queue,
3014 .stop_queue = rt61pci_stop_queue,
1d6205d0 3015 .flush_queue = rt2x00mmio_flush_queue,
95ea3627 3016 .write_tx_desc = rt61pci_write_tx_desc,
bd88a781 3017 .write_beacon = rt61pci_write_beacon,
69cf36a4 3018 .clear_beacon = rt61pci_clear_beacon,
95ea3627 3019 .fill_rxdone = rt61pci_fill_rxdone,
61e754f4
ID		 3020 .config_shared_key = rt61pci_config_shared_key,
3021 .config_pairwise_key = rt61pci_config_pairwise_key,
3a643d24 3022 .config_filter = rt61pci_config_filter,
6bb40dd1 3023 .config_intf = rt61pci_config_intf,
72810379 3024 .config_erp = rt61pci_config_erp,
e4ea1c40 3025 .config_ant = rt61pci_config_ant,
95ea3627
ID		 3026 .config = rt61pci_config,
3027};
3028
7106d97b
GJ		 3029static void rt61pci_queue_init(struct data_queue *queue)
3030{
3031 switch (queue->qid) {
3032 case QID_RX:
3033 queue->limit = 32;
3034 queue->data_size = DATA_FRAME_SIZE;
3035 queue->desc_size = RXD_DESC_SIZE;
3036 queue->priv_size = sizeof(struct queue_entry_priv_mmio);
3037 break;
181d6902 3038
7106d97b
GJ		 3039 case QID_AC_VO:
3040 case QID_AC_VI:
3041 case QID_AC_BE:
3042 case QID_AC_BK:
3043 queue->limit = 32;
3044 queue->data_size = DATA_FRAME_SIZE;
3045 queue->desc_size = TXD_DESC_SIZE;
3046 queue->priv_size = sizeof(struct queue_entry_priv_mmio);
3047 break;
181d6902 3048
7106d97b
GJ		 3049 case QID_BEACON:
3050 queue->limit = 4;
3051 queue->data_size = 0; /* No DMA required for beacons */
3052 queue->desc_size = TXINFO_SIZE;
3053 queue->priv_size = sizeof(struct queue_entry_priv_mmio);
3054 break;
3055
3056 case QID_ATIM:
3057 /* fallthrough */
3058 default:
3059 BUG();
3060 break;
3061 }
3062}
181d6902 3063
95ea3627 3064static const struct rt2x00_ops rt61pci_ops = {
04d0362e 3065 .name = KBUILD_MODNAME,
04d0362e
GW		 3066 .max_ap_intf = 4,
3067 .eeprom_size = EEPROM_SIZE,
3068 .rf_size = RF_SIZE,
3069 .tx_queues = NUM_TX_QUEUES,
7106d97b 3070 .queue_init = rt61pci_queue_init,
04d0362e
GW		 3071 .lib = &rt61pci_rt2x00_ops,
3072 .hw = &rt61pci_mac80211_ops,
95ea3627 3073#ifdef CONFIG_RT2X00_LIB_DEBUGFS
04d0362e 3074 .debugfs = &rt61pci_rt2x00debug,
95ea3627
ID		 3075#endif /* CONFIG_RT2X00_LIB_DEBUGFS */
3076};
3077
3078/*
3079 * RT61pci module information.
3080 */
a3aa1884 3081static DEFINE_PCI_DEVICE_TABLE(rt61pci_device_table) = {
95ea3627 3082 /* RT2561s */
e01ae27f 3083 { PCI_DEVICE(0x1814, 0x0301) },
95ea3627 3084 /* RT2561 v2 */
e01ae27f 3085 { PCI_DEVICE(0x1814, 0x0302) },
95ea3627 3086 /* RT2661 */
e01ae27f 3087 { PCI_DEVICE(0x1814, 0x0401) },
95ea3627
ID		 3088 { 0, }
3089};
3090
3091MODULE_AUTHOR(DRV_PROJECT);
3092MODULE_VERSION(DRV_VERSION);
3093MODULE_DESCRIPTION("Ralink RT61 PCI & PCMCIA Wireless LAN driver.");
3094MODULE_SUPPORTED_DEVICE("Ralink RT2561, RT2561s & RT2661 "
3095 "PCI & PCMCIA chipset based cards");
3096MODULE_DEVICE_TABLE(pci, rt61pci_device_table);
3097MODULE_FIRMWARE(FIRMWARE_RT2561);
3098MODULE_FIRMWARE(FIRMWARE_RT2561s);
3099MODULE_FIRMWARE(FIRMWARE_RT2661);
3100MODULE_LICENSE("GPL");
3101
e01ae27f
GW		 3102static int rt61pci_probe(struct pci_dev *pci_dev,
3103 const struct pci_device_id *id)
3104{
3105 return rt2x00pci_probe(pci_dev, &rt61pci_ops);
3106}
3107
95ea3627 3108static struct pci_driver rt61pci_driver = {
2360157c 3109 .name = KBUILD_MODNAME,
95ea3627 3110 .id_table = rt61pci_device_table,
e01ae27f 3111 .probe = rt61pci_probe,
69202359 3112 .remove = rt2x00pci_remove,
95ea3627
ID		 3113 .suspend = rt2x00pci_suspend,
3114 .resume = rt2x00pci_resume,
3115};
3116
5b0a3b7e 3117module_pci_driver(rt61pci_driver);
Linux kernel - Deliverables
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