Commit | Line | Data |
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95ea3627 | 1 | /* |
811aa9ca | 2 | Copyright (C) 2004 - 2008 rt2x00 SourceForge Project |
95ea3627 ID |
3 | <http://rt2x00.serialmonkey.com> |
4 | ||
5 | This program is free software; you can redistribute it and/or modify | |
6 | it under the terms of the GNU General Public License as published by | |
7 | the Free Software Foundation; either version 2 of the License, or | |
8 | (at your option) any later version. | |
9 | ||
10 | This program is distributed in the hope that it will be useful, | |
11 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
12 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
13 | GNU General Public License for more details. | |
14 | ||
15 | You should have received a copy of the GNU General Public License | |
16 | along with this program; if not, write to the | |
17 | Free Software Foundation, Inc., | |
18 | 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. | |
19 | */ | |
20 | ||
21 | /* | |
22 | Module: rt61pci | |
23 | Abstract: rt61pci device specific routines. | |
24 | Supported chipsets: RT2561, RT2561s, RT2661. | |
25 | */ | |
26 | ||
a7f3a06c | 27 | #include <linux/crc-itu-t.h> |
95ea3627 ID |
28 | #include <linux/delay.h> |
29 | #include <linux/etherdevice.h> | |
30 | #include <linux/init.h> | |
31 | #include <linux/kernel.h> | |
32 | #include <linux/module.h> | |
33 | #include <linux/pci.h> | |
34 | #include <linux/eeprom_93cx6.h> | |
35 | ||
36 | #include "rt2x00.h" | |
37 | #include "rt2x00pci.h" | |
38 | #include "rt61pci.h" | |
39 | ||
008c4482 ID |
40 | /* |
41 | * Allow hardware encryption to be disabled. | |
42 | */ | |
43 | static int modparam_nohwcrypt = 0; | |
44 | module_param_named(nohwcrypt, modparam_nohwcrypt, bool, S_IRUGO); | |
45 | MODULE_PARM_DESC(nohwcrypt, "Disable hardware encryption."); | |
46 | ||
95ea3627 ID |
47 | /* |
48 | * Register access. | |
49 | * BBP and RF register require indirect register access, | |
50 | * and use the CSR registers PHY_CSR3 and PHY_CSR4 to achieve this. | |
51 | * These indirect registers work with busy bits, | |
52 | * and we will try maximal REGISTER_BUSY_COUNT times to access | |
53 | * the register while taking a REGISTER_BUSY_DELAY us delay | |
54 | * between each attampt. When the busy bit is still set at that time, | |
55 | * the access attempt is considered to have failed, | |
56 | * and we will print an error. | |
57 | */ | |
0e14f6d3 | 58 | static u32 rt61pci_bbp_check(struct rt2x00_dev *rt2x00dev) |
95ea3627 ID |
59 | { |
60 | u32 reg; | |
61 | unsigned int i; | |
62 | ||
63 | for (i = 0; i < REGISTER_BUSY_COUNT; i++) { | |
64 | rt2x00pci_register_read(rt2x00dev, PHY_CSR3, ®); | |
65 | if (!rt2x00_get_field32(reg, PHY_CSR3_BUSY)) | |
66 | break; | |
67 | udelay(REGISTER_BUSY_DELAY); | |
68 | } | |
69 | ||
70 | return reg; | |
71 | } | |
72 | ||
0e14f6d3 | 73 | static void rt61pci_bbp_write(struct rt2x00_dev *rt2x00dev, |
95ea3627 ID |
74 | const unsigned int word, const u8 value) |
75 | { | |
76 | u32 reg; | |
77 | ||
78 | /* | |
79 | * Wait until the BBP becomes ready. | |
80 | */ | |
81 | reg = rt61pci_bbp_check(rt2x00dev); | |
82 | if (rt2x00_get_field32(reg, PHY_CSR3_BUSY)) { | |
83 | ERROR(rt2x00dev, "PHY_CSR3 register busy. Write failed.\n"); | |
84 | return; | |
85 | } | |
86 | ||
87 | /* | |
88 | * Write the data into the BBP. | |
89 | */ | |
90 | reg = 0; | |
91 | rt2x00_set_field32(®, PHY_CSR3_VALUE, value); | |
92 | rt2x00_set_field32(®, PHY_CSR3_REGNUM, word); | |
93 | rt2x00_set_field32(®, PHY_CSR3_BUSY, 1); | |
94 | rt2x00_set_field32(®, PHY_CSR3_READ_CONTROL, 0); | |
95 | ||
96 | rt2x00pci_register_write(rt2x00dev, PHY_CSR3, reg); | |
97 | } | |
98 | ||
0e14f6d3 | 99 | static void rt61pci_bbp_read(struct rt2x00_dev *rt2x00dev, |
95ea3627 ID |
100 | const unsigned int word, u8 *value) |
101 | { | |
102 | u32 reg; | |
103 | ||
104 | /* | |
105 | * Wait until the BBP becomes ready. | |
106 | */ | |
107 | reg = rt61pci_bbp_check(rt2x00dev); | |
108 | if (rt2x00_get_field32(reg, PHY_CSR3_BUSY)) { | |
109 | ERROR(rt2x00dev, "PHY_CSR3 register busy. Read failed.\n"); | |
110 | return; | |
111 | } | |
112 | ||
113 | /* | |
114 | * Write the request into the BBP. | |
115 | */ | |
116 | reg = 0; | |
117 | rt2x00_set_field32(®, PHY_CSR3_REGNUM, word); | |
118 | rt2x00_set_field32(®, PHY_CSR3_BUSY, 1); | |
119 | rt2x00_set_field32(®, PHY_CSR3_READ_CONTROL, 1); | |
120 | ||
121 | rt2x00pci_register_write(rt2x00dev, PHY_CSR3, reg); | |
122 | ||
123 | /* | |
124 | * Wait until the BBP becomes ready. | |
125 | */ | |
126 | reg = rt61pci_bbp_check(rt2x00dev); | |
127 | if (rt2x00_get_field32(reg, PHY_CSR3_BUSY)) { | |
128 | ERROR(rt2x00dev, "PHY_CSR3 register busy. Read failed.\n"); | |
129 | *value = 0xff; | |
130 | return; | |
131 | } | |
132 | ||
133 | *value = rt2x00_get_field32(reg, PHY_CSR3_VALUE); | |
134 | } | |
135 | ||
0e14f6d3 | 136 | static void rt61pci_rf_write(struct rt2x00_dev *rt2x00dev, |
95ea3627 ID |
137 | const unsigned int word, const u32 value) |
138 | { | |
139 | u32 reg; | |
140 | unsigned int i; | |
141 | ||
142 | if (!word) | |
143 | return; | |
144 | ||
145 | for (i = 0; i < REGISTER_BUSY_COUNT; i++) { | |
146 | rt2x00pci_register_read(rt2x00dev, PHY_CSR4, ®); | |
147 | if (!rt2x00_get_field32(reg, PHY_CSR4_BUSY)) | |
148 | goto rf_write; | |
149 | udelay(REGISTER_BUSY_DELAY); | |
150 | } | |
151 | ||
152 | ERROR(rt2x00dev, "PHY_CSR4 register busy. Write failed.\n"); | |
153 | return; | |
154 | ||
155 | rf_write: | |
156 | reg = 0; | |
157 | rt2x00_set_field32(®, PHY_CSR4_VALUE, value); | |
158 | rt2x00_set_field32(®, PHY_CSR4_NUMBER_OF_BITS, 21); | |
159 | rt2x00_set_field32(®, PHY_CSR4_IF_SELECT, 0); | |
160 | rt2x00_set_field32(®, PHY_CSR4_BUSY, 1); | |
161 | ||
162 | rt2x00pci_register_write(rt2x00dev, PHY_CSR4, reg); | |
163 | rt2x00_rf_write(rt2x00dev, word, value); | |
164 | } | |
165 | ||
771fd565 | 166 | #ifdef CONFIG_RT2X00_LIB_LEDS |
a9450b70 ID |
167 | /* |
168 | * This function is only called from rt61pci_led_brightness() | |
169 | * make gcc happy by placing this function inside the | |
170 | * same ifdef statement as the caller. | |
171 | */ | |
0e14f6d3 | 172 | static void rt61pci_mcu_request(struct rt2x00_dev *rt2x00dev, |
95ea3627 ID |
173 | const u8 command, const u8 token, |
174 | const u8 arg0, const u8 arg1) | |
175 | { | |
176 | u32 reg; | |
177 | ||
178 | rt2x00pci_register_read(rt2x00dev, H2M_MAILBOX_CSR, ®); | |
179 | ||
180 | if (rt2x00_get_field32(reg, H2M_MAILBOX_CSR_OWNER)) { | |
181 | ERROR(rt2x00dev, "mcu request error. " | |
182 | "Request 0x%02x failed for token 0x%02x.\n", | |
183 | command, token); | |
184 | return; | |
185 | } | |
186 | ||
187 | rt2x00_set_field32(®, H2M_MAILBOX_CSR_OWNER, 1); | |
188 | rt2x00_set_field32(®, H2M_MAILBOX_CSR_CMD_TOKEN, token); | |
189 | rt2x00_set_field32(®, H2M_MAILBOX_CSR_ARG0, arg0); | |
190 | rt2x00_set_field32(®, H2M_MAILBOX_CSR_ARG1, arg1); | |
191 | rt2x00pci_register_write(rt2x00dev, H2M_MAILBOX_CSR, reg); | |
192 | ||
193 | rt2x00pci_register_read(rt2x00dev, HOST_CMD_CSR, ®); | |
194 | rt2x00_set_field32(®, HOST_CMD_CSR_HOST_COMMAND, command); | |
195 | rt2x00_set_field32(®, HOST_CMD_CSR_INTERRUPT_MCU, 1); | |
196 | rt2x00pci_register_write(rt2x00dev, HOST_CMD_CSR, reg); | |
197 | } | |
771fd565 | 198 | #endif /* CONFIG_RT2X00_LIB_LEDS */ |
95ea3627 ID |
199 | |
200 | static void rt61pci_eepromregister_read(struct eeprom_93cx6 *eeprom) | |
201 | { | |
202 | struct rt2x00_dev *rt2x00dev = eeprom->data; | |
203 | u32 reg; | |
204 | ||
205 | rt2x00pci_register_read(rt2x00dev, E2PROM_CSR, ®); | |
206 | ||
207 | eeprom->reg_data_in = !!rt2x00_get_field32(reg, E2PROM_CSR_DATA_IN); | |
208 | eeprom->reg_data_out = !!rt2x00_get_field32(reg, E2PROM_CSR_DATA_OUT); | |
209 | eeprom->reg_data_clock = | |
210 | !!rt2x00_get_field32(reg, E2PROM_CSR_DATA_CLOCK); | |
211 | eeprom->reg_chip_select = | |
212 | !!rt2x00_get_field32(reg, E2PROM_CSR_CHIP_SELECT); | |
213 | } | |
214 | ||
215 | static void rt61pci_eepromregister_write(struct eeprom_93cx6 *eeprom) | |
216 | { | |
217 | struct rt2x00_dev *rt2x00dev = eeprom->data; | |
218 | u32 reg = 0; | |
219 | ||
220 | rt2x00_set_field32(®, E2PROM_CSR_DATA_IN, !!eeprom->reg_data_in); | |
221 | rt2x00_set_field32(®, E2PROM_CSR_DATA_OUT, !!eeprom->reg_data_out); | |
222 | rt2x00_set_field32(®, E2PROM_CSR_DATA_CLOCK, | |
223 | !!eeprom->reg_data_clock); | |
224 | rt2x00_set_field32(®, E2PROM_CSR_CHIP_SELECT, | |
225 | !!eeprom->reg_chip_select); | |
226 | ||
227 | rt2x00pci_register_write(rt2x00dev, E2PROM_CSR, reg); | |
228 | } | |
229 | ||
230 | #ifdef CONFIG_RT2X00_LIB_DEBUGFS | |
231 | #define CSR_OFFSET(__word) ( CSR_REG_BASE + ((__word) * sizeof(u32)) ) | |
232 | ||
0e14f6d3 | 233 | static void rt61pci_read_csr(struct rt2x00_dev *rt2x00dev, |
95ea3627 ID |
234 | const unsigned int word, u32 *data) |
235 | { | |
236 | rt2x00pci_register_read(rt2x00dev, CSR_OFFSET(word), data); | |
237 | } | |
238 | ||
0e14f6d3 | 239 | static void rt61pci_write_csr(struct rt2x00_dev *rt2x00dev, |
95ea3627 ID |
240 | const unsigned int word, u32 data) |
241 | { | |
242 | rt2x00pci_register_write(rt2x00dev, CSR_OFFSET(word), data); | |
243 | } | |
244 | ||
245 | static const struct rt2x00debug rt61pci_rt2x00debug = { | |
246 | .owner = THIS_MODULE, | |
247 | .csr = { | |
248 | .read = rt61pci_read_csr, | |
249 | .write = rt61pci_write_csr, | |
250 | .word_size = sizeof(u32), | |
251 | .word_count = CSR_REG_SIZE / sizeof(u32), | |
252 | }, | |
253 | .eeprom = { | |
254 | .read = rt2x00_eeprom_read, | |
255 | .write = rt2x00_eeprom_write, | |
256 | .word_size = sizeof(u16), | |
257 | .word_count = EEPROM_SIZE / sizeof(u16), | |
258 | }, | |
259 | .bbp = { | |
260 | .read = rt61pci_bbp_read, | |
261 | .write = rt61pci_bbp_write, | |
262 | .word_size = sizeof(u8), | |
263 | .word_count = BBP_SIZE / sizeof(u8), | |
264 | }, | |
265 | .rf = { | |
266 | .read = rt2x00_rf_read, | |
267 | .write = rt61pci_rf_write, | |
268 | .word_size = sizeof(u32), | |
269 | .word_count = RF_SIZE / sizeof(u32), | |
270 | }, | |
271 | }; | |
272 | #endif /* CONFIG_RT2X00_LIB_DEBUGFS */ | |
273 | ||
58169529 | 274 | #ifdef CONFIG_RT2X00_LIB_RFKILL |
95ea3627 ID |
275 | static int rt61pci_rfkill_poll(struct rt2x00_dev *rt2x00dev) |
276 | { | |
277 | u32 reg; | |
278 | ||
279 | rt2x00pci_register_read(rt2x00dev, MAC_CSR13, ®); | |
181d6902 | 280 | return rt2x00_get_field32(reg, MAC_CSR13_BIT5); |
95ea3627 | 281 | } |
81873e9c ID |
282 | #else |
283 | #define rt61pci_rfkill_poll NULL | |
58169529 | 284 | #endif /* CONFIG_RT2X00_LIB_RFKILL */ |
95ea3627 | 285 | |
771fd565 | 286 | #ifdef CONFIG_RT2X00_LIB_LEDS |
a2e1d52a | 287 | static void rt61pci_brightness_set(struct led_classdev *led_cdev, |
a9450b70 ID |
288 | enum led_brightness brightness) |
289 | { | |
290 | struct rt2x00_led *led = | |
291 | container_of(led_cdev, struct rt2x00_led, led_dev); | |
292 | unsigned int enabled = brightness != LED_OFF; | |
293 | unsigned int a_mode = | |
294 | (enabled && led->rt2x00dev->curr_band == IEEE80211_BAND_5GHZ); | |
295 | unsigned int bg_mode = | |
296 | (enabled && led->rt2x00dev->curr_band == IEEE80211_BAND_2GHZ); | |
297 | ||
298 | if (led->type == LED_TYPE_RADIO) { | |
299 | rt2x00_set_field16(&led->rt2x00dev->led_mcu_reg, | |
300 | MCU_LEDCS_RADIO_STATUS, enabled); | |
301 | ||
302 | rt61pci_mcu_request(led->rt2x00dev, MCU_LED, 0xff, | |
303 | (led->rt2x00dev->led_mcu_reg & 0xff), | |
304 | ((led->rt2x00dev->led_mcu_reg >> 8))); | |
305 | } else if (led->type == LED_TYPE_ASSOC) { | |
306 | rt2x00_set_field16(&led->rt2x00dev->led_mcu_reg, | |
307 | MCU_LEDCS_LINK_BG_STATUS, bg_mode); | |
308 | rt2x00_set_field16(&led->rt2x00dev->led_mcu_reg, | |
309 | MCU_LEDCS_LINK_A_STATUS, a_mode); | |
310 | ||
311 | rt61pci_mcu_request(led->rt2x00dev, MCU_LED, 0xff, | |
312 | (led->rt2x00dev->led_mcu_reg & 0xff), | |
313 | ((led->rt2x00dev->led_mcu_reg >> 8))); | |
314 | } else if (led->type == LED_TYPE_QUALITY) { | |
315 | /* | |
316 | * The brightness is divided into 6 levels (0 - 5), | |
317 | * this means we need to convert the brightness | |
318 | * argument into the matching level within that range. | |
319 | */ | |
320 | rt61pci_mcu_request(led->rt2x00dev, MCU_LED_STRENGTH, 0xff, | |
321 | brightness / (LED_FULL / 6), 0); | |
322 | } | |
323 | } | |
a2e1d52a ID |
324 | |
325 | static int rt61pci_blink_set(struct led_classdev *led_cdev, | |
326 | unsigned long *delay_on, | |
327 | unsigned long *delay_off) | |
328 | { | |
329 | struct rt2x00_led *led = | |
330 | container_of(led_cdev, struct rt2x00_led, led_dev); | |
331 | u32 reg; | |
332 | ||
333 | rt2x00pci_register_read(led->rt2x00dev, MAC_CSR14, ®); | |
334 | rt2x00_set_field32(®, MAC_CSR14_ON_PERIOD, *delay_on); | |
335 | rt2x00_set_field32(®, MAC_CSR14_OFF_PERIOD, *delay_off); | |
336 | rt2x00pci_register_write(led->rt2x00dev, MAC_CSR14, reg); | |
337 | ||
338 | return 0; | |
339 | } | |
475433be ID |
340 | |
341 | static void rt61pci_init_led(struct rt2x00_dev *rt2x00dev, | |
342 | struct rt2x00_led *led, | |
343 | enum led_type type) | |
344 | { | |
345 | led->rt2x00dev = rt2x00dev; | |
346 | led->type = type; | |
347 | led->led_dev.brightness_set = rt61pci_brightness_set; | |
348 | led->led_dev.blink_set = rt61pci_blink_set; | |
349 | led->flags = LED_INITIALIZED; | |
350 | } | |
771fd565 | 351 | #endif /* CONFIG_RT2X00_LIB_LEDS */ |
a9450b70 | 352 | |
95ea3627 ID |
353 | /* |
354 | * Configuration handlers. | |
355 | */ | |
61e754f4 ID |
356 | static int rt61pci_config_shared_key(struct rt2x00_dev *rt2x00dev, |
357 | struct rt2x00lib_crypto *crypto, | |
358 | struct ieee80211_key_conf *key) | |
359 | { | |
360 | struct hw_key_entry key_entry; | |
361 | struct rt2x00_field32 field; | |
362 | u32 mask; | |
363 | u32 reg; | |
364 | ||
365 | if (crypto->cmd == SET_KEY) { | |
366 | /* | |
367 | * rt2x00lib can't determine the correct free | |
368 | * key_idx for shared keys. We have 1 register | |
369 | * with key valid bits. The goal is simple, read | |
370 | * the register, if that is full we have no slots | |
371 | * left. | |
372 | * Note that each BSS is allowed to have up to 4 | |
373 | * shared keys, so put a mask over the allowed | |
374 | * entries. | |
375 | */ | |
376 | mask = (0xf << crypto->bssidx); | |
377 | ||
378 | rt2x00pci_register_read(rt2x00dev, SEC_CSR0, ®); | |
379 | reg &= mask; | |
380 | ||
381 | if (reg && reg == mask) | |
382 | return -ENOSPC; | |
383 | ||
acaf908d | 384 | key->hw_key_idx += reg ? ffz(reg) : 0; |
61e754f4 ID |
385 | |
386 | /* | |
387 | * Upload key to hardware | |
388 | */ | |
389 | memcpy(key_entry.key, crypto->key, | |
390 | sizeof(key_entry.key)); | |
391 | memcpy(key_entry.tx_mic, crypto->tx_mic, | |
392 | sizeof(key_entry.tx_mic)); | |
393 | memcpy(key_entry.rx_mic, crypto->rx_mic, | |
394 | sizeof(key_entry.rx_mic)); | |
395 | ||
396 | reg = SHARED_KEY_ENTRY(key->hw_key_idx); | |
397 | rt2x00pci_register_multiwrite(rt2x00dev, reg, | |
398 | &key_entry, sizeof(key_entry)); | |
399 | ||
400 | /* | |
401 | * The cipher types are stored over 2 registers. | |
402 | * bssidx 0 and 1 keys are stored in SEC_CSR1 and | |
403 | * bssidx 1 and 2 keys are stored in SEC_CSR5. | |
404 | * Using the correct defines correctly will cause overhead, | |
405 | * so just calculate the correct offset. | |
406 | */ | |
407 | if (key->hw_key_idx < 8) { | |
408 | field.bit_offset = (3 * key->hw_key_idx); | |
409 | field.bit_mask = 0x7 << field.bit_offset; | |
410 | ||
411 | rt2x00pci_register_read(rt2x00dev, SEC_CSR1, ®); | |
412 | rt2x00_set_field32(®, field, crypto->cipher); | |
413 | rt2x00pci_register_write(rt2x00dev, SEC_CSR1, reg); | |
414 | } else { | |
415 | field.bit_offset = (3 * (key->hw_key_idx - 8)); | |
416 | field.bit_mask = 0x7 << field.bit_offset; | |
417 | ||
418 | rt2x00pci_register_read(rt2x00dev, SEC_CSR5, ®); | |
419 | rt2x00_set_field32(®, field, crypto->cipher); | |
420 | rt2x00pci_register_write(rt2x00dev, SEC_CSR5, reg); | |
421 | } | |
422 | ||
423 | /* | |
424 | * The driver does not support the IV/EIV generation | |
425 | * in hardware. However it doesn't support the IV/EIV | |
426 | * inside the ieee80211 frame either, but requires it | |
427 | * to be provided seperately for the descriptor. | |
428 | * rt2x00lib will cut the IV/EIV data out of all frames | |
429 | * given to us by mac80211, but we must tell mac80211 | |
430 | * to generate the IV/EIV data. | |
431 | */ | |
432 | key->flags |= IEEE80211_KEY_FLAG_GENERATE_IV; | |
433 | } | |
434 | ||
435 | /* | |
436 | * SEC_CSR0 contains only single-bit fields to indicate | |
437 | * a particular key is valid. Because using the FIELD32() | |
438 | * defines directly will cause a lot of overhead we use | |
439 | * a calculation to determine the correct bit directly. | |
440 | */ | |
441 | mask = 1 << key->hw_key_idx; | |
442 | ||
443 | rt2x00pci_register_read(rt2x00dev, SEC_CSR0, ®); | |
444 | if (crypto->cmd == SET_KEY) | |
445 | reg |= mask; | |
446 | else if (crypto->cmd == DISABLE_KEY) | |
447 | reg &= ~mask; | |
448 | rt2x00pci_register_write(rt2x00dev, SEC_CSR0, reg); | |
449 | ||
450 | return 0; | |
451 | } | |
452 | ||
453 | static int rt61pci_config_pairwise_key(struct rt2x00_dev *rt2x00dev, | |
454 | struct rt2x00lib_crypto *crypto, | |
455 | struct ieee80211_key_conf *key) | |
456 | { | |
457 | struct hw_pairwise_ta_entry addr_entry; | |
458 | struct hw_key_entry key_entry; | |
459 | u32 mask; | |
460 | u32 reg; | |
461 | ||
462 | if (crypto->cmd == SET_KEY) { | |
463 | /* | |
464 | * rt2x00lib can't determine the correct free | |
465 | * key_idx for pairwise keys. We have 2 registers | |
466 | * with key valid bits. The goal is simple, read | |
467 | * the first register, if that is full move to | |
468 | * the next register. | |
469 | * When both registers are full, we drop the key, | |
470 | * otherwise we use the first invalid entry. | |
471 | */ | |
472 | rt2x00pci_register_read(rt2x00dev, SEC_CSR2, ®); | |
473 | if (reg && reg == ~0) { | |
474 | key->hw_key_idx = 32; | |
475 | rt2x00pci_register_read(rt2x00dev, SEC_CSR3, ®); | |
476 | if (reg && reg == ~0) | |
477 | return -ENOSPC; | |
478 | } | |
479 | ||
acaf908d | 480 | key->hw_key_idx += reg ? ffz(reg) : 0; |
61e754f4 ID |
481 | |
482 | /* | |
483 | * Upload key to hardware | |
484 | */ | |
485 | memcpy(key_entry.key, crypto->key, | |
486 | sizeof(key_entry.key)); | |
487 | memcpy(key_entry.tx_mic, crypto->tx_mic, | |
488 | sizeof(key_entry.tx_mic)); | |
489 | memcpy(key_entry.rx_mic, crypto->rx_mic, | |
490 | sizeof(key_entry.rx_mic)); | |
491 | ||
492 | memset(&addr_entry, 0, sizeof(addr_entry)); | |
493 | memcpy(&addr_entry, crypto->address, ETH_ALEN); | |
494 | addr_entry.cipher = crypto->cipher; | |
495 | ||
496 | reg = PAIRWISE_KEY_ENTRY(key->hw_key_idx); | |
497 | rt2x00pci_register_multiwrite(rt2x00dev, reg, | |
498 | &key_entry, sizeof(key_entry)); | |
499 | ||
500 | reg = PAIRWISE_TA_ENTRY(key->hw_key_idx); | |
501 | rt2x00pci_register_multiwrite(rt2x00dev, reg, | |
502 | &addr_entry, sizeof(addr_entry)); | |
503 | ||
504 | /* | |
505 | * Enable pairwise lookup table for given BSS idx, | |
506 | * without this received frames will not be decrypted | |
507 | * by the hardware. | |
508 | */ | |
509 | rt2x00pci_register_read(rt2x00dev, SEC_CSR4, ®); | |
510 | reg |= (1 << crypto->bssidx); | |
511 | rt2x00pci_register_write(rt2x00dev, SEC_CSR4, reg); | |
512 | ||
513 | /* | |
514 | * The driver does not support the IV/EIV generation | |
515 | * in hardware. However it doesn't support the IV/EIV | |
516 | * inside the ieee80211 frame either, but requires it | |
517 | * to be provided seperately for the descriptor. | |
518 | * rt2x00lib will cut the IV/EIV data out of all frames | |
519 | * given to us by mac80211, but we must tell mac80211 | |
520 | * to generate the IV/EIV data. | |
521 | */ | |
522 | key->flags |= IEEE80211_KEY_FLAG_GENERATE_IV; | |
523 | } | |
524 | ||
525 | /* | |
526 | * SEC_CSR2 and SEC_CSR3 contain only single-bit fields to indicate | |
527 | * a particular key is valid. Because using the FIELD32() | |
528 | * defines directly will cause a lot of overhead we use | |
529 | * a calculation to determine the correct bit directly. | |
530 | */ | |
531 | if (key->hw_key_idx < 32) { | |
532 | mask = 1 << key->hw_key_idx; | |
533 | ||
534 | rt2x00pci_register_read(rt2x00dev, SEC_CSR2, ®); | |
535 | if (crypto->cmd == SET_KEY) | |
536 | reg |= mask; | |
537 | else if (crypto->cmd == DISABLE_KEY) | |
538 | reg &= ~mask; | |
539 | rt2x00pci_register_write(rt2x00dev, SEC_CSR2, reg); | |
540 | } else { | |
541 | mask = 1 << (key->hw_key_idx - 32); | |
542 | ||
543 | rt2x00pci_register_read(rt2x00dev, SEC_CSR3, ®); | |
544 | if (crypto->cmd == SET_KEY) | |
545 | reg |= mask; | |
546 | else if (crypto->cmd == DISABLE_KEY) | |
547 | reg &= ~mask; | |
548 | rt2x00pci_register_write(rt2x00dev, SEC_CSR3, reg); | |
549 | } | |
550 | ||
551 | return 0; | |
552 | } | |
553 | ||
3a643d24 ID |
554 | static void rt61pci_config_filter(struct rt2x00_dev *rt2x00dev, |
555 | const unsigned int filter_flags) | |
556 | { | |
557 | u32 reg; | |
558 | ||
559 | /* | |
560 | * Start configuration steps. | |
561 | * Note that the version error will always be dropped | |
562 | * and broadcast frames will always be accepted since | |
563 | * there is no filter for it at this time. | |
564 | */ | |
565 | rt2x00pci_register_read(rt2x00dev, TXRX_CSR0, ®); | |
566 | rt2x00_set_field32(®, TXRX_CSR0_DROP_CRC, | |
567 | !(filter_flags & FIF_FCSFAIL)); | |
568 | rt2x00_set_field32(®, TXRX_CSR0_DROP_PHYSICAL, | |
569 | !(filter_flags & FIF_PLCPFAIL)); | |
570 | rt2x00_set_field32(®, TXRX_CSR0_DROP_CONTROL, | |
571 | !(filter_flags & FIF_CONTROL)); | |
572 | rt2x00_set_field32(®, TXRX_CSR0_DROP_NOT_TO_ME, | |
573 | !(filter_flags & FIF_PROMISC_IN_BSS)); | |
574 | rt2x00_set_field32(®, TXRX_CSR0_DROP_TO_DS, | |
e0b005fa ID |
575 | !(filter_flags & FIF_PROMISC_IN_BSS) && |
576 | !rt2x00dev->intf_ap_count); | |
3a643d24 ID |
577 | rt2x00_set_field32(®, TXRX_CSR0_DROP_VERSION_ERROR, 1); |
578 | rt2x00_set_field32(®, TXRX_CSR0_DROP_MULTICAST, | |
579 | !(filter_flags & FIF_ALLMULTI)); | |
580 | rt2x00_set_field32(®, TXRX_CSR0_DROP_BROADCAST, 0); | |
581 | rt2x00_set_field32(®, TXRX_CSR0_DROP_ACK_CTS, | |
582 | !(filter_flags & FIF_CONTROL)); | |
583 | rt2x00pci_register_write(rt2x00dev, TXRX_CSR0, reg); | |
584 | } | |
585 | ||
6bb40dd1 ID |
586 | static void rt61pci_config_intf(struct rt2x00_dev *rt2x00dev, |
587 | struct rt2x00_intf *intf, | |
588 | struct rt2x00intf_conf *conf, | |
589 | const unsigned int flags) | |
95ea3627 | 590 | { |
6bb40dd1 ID |
591 | unsigned int beacon_base; |
592 | u32 reg; | |
95ea3627 | 593 | |
6bb40dd1 ID |
594 | if (flags & CONFIG_UPDATE_TYPE) { |
595 | /* | |
596 | * Clear current synchronisation setup. | |
597 | * For the Beacon base registers we only need to clear | |
598 | * the first byte since that byte contains the VALID and OWNER | |
599 | * bits which (when set to 0) will invalidate the entire beacon. | |
600 | */ | |
601 | beacon_base = HW_BEACON_OFFSET(intf->beacon->entry_idx); | |
6bb40dd1 | 602 | rt2x00pci_register_write(rt2x00dev, beacon_base, 0); |
95ea3627 | 603 | |
6bb40dd1 ID |
604 | /* |
605 | * Enable synchronisation. | |
606 | */ | |
607 | rt2x00pci_register_read(rt2x00dev, TXRX_CSR9, ®); | |
fd3c91c5 | 608 | rt2x00_set_field32(®, TXRX_CSR9_TSF_TICKING, 1); |
6bb40dd1 | 609 | rt2x00_set_field32(®, TXRX_CSR9_TSF_SYNC, conf->sync); |
fd3c91c5 | 610 | rt2x00_set_field32(®, TXRX_CSR9_TBTT_ENABLE, 1); |
6bb40dd1 ID |
611 | rt2x00pci_register_write(rt2x00dev, TXRX_CSR9, reg); |
612 | } | |
95ea3627 | 613 | |
6bb40dd1 ID |
614 | if (flags & CONFIG_UPDATE_MAC) { |
615 | reg = le32_to_cpu(conf->mac[1]); | |
616 | rt2x00_set_field32(®, MAC_CSR3_UNICAST_TO_ME_MASK, 0xff); | |
617 | conf->mac[1] = cpu_to_le32(reg); | |
95ea3627 | 618 | |
6bb40dd1 ID |
619 | rt2x00pci_register_multiwrite(rt2x00dev, MAC_CSR2, |
620 | conf->mac, sizeof(conf->mac)); | |
621 | } | |
95ea3627 | 622 | |
6bb40dd1 ID |
623 | if (flags & CONFIG_UPDATE_BSSID) { |
624 | reg = le32_to_cpu(conf->bssid[1]); | |
625 | rt2x00_set_field32(®, MAC_CSR5_BSS_ID_MASK, 3); | |
626 | conf->bssid[1] = cpu_to_le32(reg); | |
95ea3627 | 627 | |
6bb40dd1 ID |
628 | rt2x00pci_register_multiwrite(rt2x00dev, MAC_CSR4, |
629 | conf->bssid, sizeof(conf->bssid)); | |
630 | } | |
95ea3627 ID |
631 | } |
632 | ||
3a643d24 ID |
633 | static void rt61pci_config_erp(struct rt2x00_dev *rt2x00dev, |
634 | struct rt2x00lib_erp *erp) | |
95ea3627 | 635 | { |
95ea3627 | 636 | u32 reg; |
95ea3627 ID |
637 | |
638 | rt2x00pci_register_read(rt2x00dev, TXRX_CSR0, ®); | |
72810379 | 639 | rt2x00_set_field32(®, TXRX_CSR0_RX_ACK_TIMEOUT, erp->ack_timeout); |
95ea3627 ID |
640 | rt2x00pci_register_write(rt2x00dev, TXRX_CSR0, reg); |
641 | ||
642 | rt2x00pci_register_read(rt2x00dev, TXRX_CSR4, ®); | |
4f5af6eb | 643 | rt2x00_set_field32(®, TXRX_CSR4_AUTORESPOND_PREAMBLE, |
72810379 | 644 | !!erp->short_preamble); |
95ea3627 ID |
645 | rt2x00pci_register_write(rt2x00dev, TXRX_CSR4, reg); |
646 | } | |
647 | ||
ba2ab471 ID |
648 | |
649 | static void rt61pci_config_lna_gain(struct rt2x00_dev *rt2x00dev, | |
650 | struct rt2x00lib_conf *libconf) | |
651 | { | |
652 | u16 eeprom; | |
653 | short lna_gain = 0; | |
654 | ||
655 | if (libconf->band == IEEE80211_BAND_2GHZ) { | |
656 | if (test_bit(CONFIG_EXTERNAL_LNA_BG, &rt2x00dev->flags)) | |
657 | lna_gain += 14; | |
658 | ||
659 | rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_OFFSET_BG, &eeprom); | |
660 | lna_gain -= rt2x00_get_field16(eeprom, EEPROM_RSSI_OFFSET_BG_1); | |
661 | } else { | |
662 | if (test_bit(CONFIG_EXTERNAL_LNA_A, &rt2x00dev->flags)) | |
663 | lna_gain += 14; | |
664 | ||
665 | rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_OFFSET_A, &eeprom); | |
666 | lna_gain -= rt2x00_get_field16(eeprom, EEPROM_RSSI_OFFSET_A_1); | |
667 | } | |
668 | ||
669 | rt2x00dev->lna_gain = lna_gain; | |
670 | } | |
671 | ||
95ea3627 | 672 | static void rt61pci_config_phymode(struct rt2x00_dev *rt2x00dev, |
5c58ee51 | 673 | const int basic_rate_mask) |
95ea3627 | 674 | { |
5c58ee51 | 675 | rt2x00pci_register_write(rt2x00dev, TXRX_CSR5, basic_rate_mask); |
95ea3627 ID |
676 | } |
677 | ||
5c58ee51 ID |
678 | static void rt61pci_config_channel(struct rt2x00_dev *rt2x00dev, |
679 | struct rf_channel *rf, const int txpower) | |
95ea3627 ID |
680 | { |
681 | u8 r3; | |
682 | u8 r94; | |
683 | u8 smart; | |
684 | ||
685 | rt2x00_set_field32(&rf->rf3, RF3_TXPOWER, TXPOWER_TO_DEV(txpower)); | |
686 | rt2x00_set_field32(&rf->rf4, RF4_FREQ_OFFSET, rt2x00dev->freq_offset); | |
687 | ||
688 | smart = !(rt2x00_rf(&rt2x00dev->chip, RF5225) || | |
689 | rt2x00_rf(&rt2x00dev->chip, RF2527)); | |
690 | ||
691 | rt61pci_bbp_read(rt2x00dev, 3, &r3); | |
692 | rt2x00_set_field8(&r3, BBP_R3_SMART_MODE, smart); | |
693 | rt61pci_bbp_write(rt2x00dev, 3, r3); | |
694 | ||
695 | r94 = 6; | |
696 | if (txpower > MAX_TXPOWER && txpower <= (MAX_TXPOWER + r94)) | |
697 | r94 += txpower - MAX_TXPOWER; | |
698 | else if (txpower < MIN_TXPOWER && txpower >= (MIN_TXPOWER - r94)) | |
699 | r94 += txpower; | |
700 | rt61pci_bbp_write(rt2x00dev, 94, r94); | |
701 | ||
702 | rt61pci_rf_write(rt2x00dev, 1, rf->rf1); | |
703 | rt61pci_rf_write(rt2x00dev, 2, rf->rf2); | |
704 | rt61pci_rf_write(rt2x00dev, 3, rf->rf3 & ~0x00000004); | |
705 | rt61pci_rf_write(rt2x00dev, 4, rf->rf4); | |
706 | ||
707 | udelay(200); | |
708 | ||
709 | rt61pci_rf_write(rt2x00dev, 1, rf->rf1); | |
710 | rt61pci_rf_write(rt2x00dev, 2, rf->rf2); | |
711 | rt61pci_rf_write(rt2x00dev, 3, rf->rf3 | 0x00000004); | |
712 | rt61pci_rf_write(rt2x00dev, 4, rf->rf4); | |
713 | ||
714 | udelay(200); | |
715 | ||
716 | rt61pci_rf_write(rt2x00dev, 1, rf->rf1); | |
717 | rt61pci_rf_write(rt2x00dev, 2, rf->rf2); | |
718 | rt61pci_rf_write(rt2x00dev, 3, rf->rf3 & ~0x00000004); | |
719 | rt61pci_rf_write(rt2x00dev, 4, rf->rf4); | |
720 | ||
721 | msleep(1); | |
722 | } | |
723 | ||
95ea3627 ID |
724 | static void rt61pci_config_txpower(struct rt2x00_dev *rt2x00dev, |
725 | const int txpower) | |
726 | { | |
727 | struct rf_channel rf; | |
728 | ||
729 | rt2x00_rf_read(rt2x00dev, 1, &rf.rf1); | |
730 | rt2x00_rf_read(rt2x00dev, 2, &rf.rf2); | |
731 | rt2x00_rf_read(rt2x00dev, 3, &rf.rf3); | |
732 | rt2x00_rf_read(rt2x00dev, 4, &rf.rf4); | |
733 | ||
5c58ee51 | 734 | rt61pci_config_channel(rt2x00dev, &rf, txpower); |
95ea3627 ID |
735 | } |
736 | ||
737 | static void rt61pci_config_antenna_5x(struct rt2x00_dev *rt2x00dev, | |
addc81bd | 738 | struct antenna_setup *ant) |
95ea3627 ID |
739 | { |
740 | u8 r3; | |
741 | u8 r4; | |
742 | u8 r77; | |
743 | ||
744 | rt61pci_bbp_read(rt2x00dev, 3, &r3); | |
745 | rt61pci_bbp_read(rt2x00dev, 4, &r4); | |
746 | rt61pci_bbp_read(rt2x00dev, 77, &r77); | |
747 | ||
748 | rt2x00_set_field8(&r3, BBP_R3_SMART_MODE, | |
acaa410d | 749 | rt2x00_rf(&rt2x00dev->chip, RF5325)); |
e4cd2ff8 ID |
750 | |
751 | /* | |
752 | * Configure the RX antenna. | |
753 | */ | |
addc81bd | 754 | switch (ant->rx) { |
95ea3627 | 755 | case ANTENNA_HW_DIVERSITY: |
acaa410d | 756 | rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA_CONTROL, 2); |
95ea3627 | 757 | rt2x00_set_field8(&r4, BBP_R4_RX_FRAME_END, |
8318d78a | 758 | (rt2x00dev->curr_band != IEEE80211_BAND_5GHZ)); |
95ea3627 ID |
759 | break; |
760 | case ANTENNA_A: | |
acaa410d | 761 | rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA_CONTROL, 1); |
95ea3627 | 762 | rt2x00_set_field8(&r4, BBP_R4_RX_FRAME_END, 0); |
8318d78a | 763 | if (rt2x00dev->curr_band == IEEE80211_BAND_5GHZ) |
acaa410d MN |
764 | rt2x00_set_field8(&r77, BBP_R77_RX_ANTENNA, 0); |
765 | else | |
766 | rt2x00_set_field8(&r77, BBP_R77_RX_ANTENNA, 3); | |
95ea3627 ID |
767 | break; |
768 | case ANTENNA_B: | |
a4fe07d9 | 769 | default: |
acaa410d | 770 | rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA_CONTROL, 1); |
95ea3627 | 771 | rt2x00_set_field8(&r4, BBP_R4_RX_FRAME_END, 0); |
8318d78a | 772 | if (rt2x00dev->curr_band == IEEE80211_BAND_5GHZ) |
acaa410d MN |
773 | rt2x00_set_field8(&r77, BBP_R77_RX_ANTENNA, 3); |
774 | else | |
775 | rt2x00_set_field8(&r77, BBP_R77_RX_ANTENNA, 0); | |
95ea3627 ID |
776 | break; |
777 | } | |
778 | ||
779 | rt61pci_bbp_write(rt2x00dev, 77, r77); | |
780 | rt61pci_bbp_write(rt2x00dev, 3, r3); | |
781 | rt61pci_bbp_write(rt2x00dev, 4, r4); | |
782 | } | |
783 | ||
784 | static void rt61pci_config_antenna_2x(struct rt2x00_dev *rt2x00dev, | |
addc81bd | 785 | struct antenna_setup *ant) |
95ea3627 ID |
786 | { |
787 | u8 r3; | |
788 | u8 r4; | |
789 | u8 r77; | |
790 | ||
791 | rt61pci_bbp_read(rt2x00dev, 3, &r3); | |
792 | rt61pci_bbp_read(rt2x00dev, 4, &r4); | |
793 | rt61pci_bbp_read(rt2x00dev, 77, &r77); | |
794 | ||
795 | rt2x00_set_field8(&r3, BBP_R3_SMART_MODE, | |
acaa410d | 796 | rt2x00_rf(&rt2x00dev->chip, RF2529)); |
95ea3627 ID |
797 | rt2x00_set_field8(&r4, BBP_R4_RX_FRAME_END, |
798 | !test_bit(CONFIG_FRAME_TYPE, &rt2x00dev->flags)); | |
799 | ||
e4cd2ff8 ID |
800 | /* |
801 | * Configure the RX antenna. | |
802 | */ | |
addc81bd | 803 | switch (ant->rx) { |
95ea3627 | 804 | case ANTENNA_HW_DIVERSITY: |
acaa410d | 805 | rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA_CONTROL, 2); |
95ea3627 ID |
806 | break; |
807 | case ANTENNA_A: | |
acaa410d MN |
808 | rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA_CONTROL, 1); |
809 | rt2x00_set_field8(&r77, BBP_R77_RX_ANTENNA, 3); | |
95ea3627 ID |
810 | break; |
811 | case ANTENNA_B: | |
a4fe07d9 | 812 | default: |
acaa410d MN |
813 | rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA_CONTROL, 1); |
814 | rt2x00_set_field8(&r77, BBP_R77_RX_ANTENNA, 0); | |
95ea3627 ID |
815 | break; |
816 | } | |
817 | ||
818 | rt61pci_bbp_write(rt2x00dev, 77, r77); | |
819 | rt61pci_bbp_write(rt2x00dev, 3, r3); | |
820 | rt61pci_bbp_write(rt2x00dev, 4, r4); | |
821 | } | |
822 | ||
823 | static void rt61pci_config_antenna_2529_rx(struct rt2x00_dev *rt2x00dev, | |
824 | const int p1, const int p2) | |
825 | { | |
826 | u32 reg; | |
827 | ||
828 | rt2x00pci_register_read(rt2x00dev, MAC_CSR13, ®); | |
829 | ||
acaa410d MN |
830 | rt2x00_set_field32(®, MAC_CSR13_BIT4, p1); |
831 | rt2x00_set_field32(®, MAC_CSR13_BIT12, 0); | |
832 | ||
833 | rt2x00_set_field32(®, MAC_CSR13_BIT3, !p2); | |
834 | rt2x00_set_field32(®, MAC_CSR13_BIT11, 0); | |
835 | ||
836 | rt2x00pci_register_write(rt2x00dev, MAC_CSR13, reg); | |
95ea3627 ID |
837 | } |
838 | ||
839 | static void rt61pci_config_antenna_2529(struct rt2x00_dev *rt2x00dev, | |
addc81bd | 840 | struct antenna_setup *ant) |
95ea3627 | 841 | { |
95ea3627 ID |
842 | u8 r3; |
843 | u8 r4; | |
844 | u8 r77; | |
845 | ||
846 | rt61pci_bbp_read(rt2x00dev, 3, &r3); | |
847 | rt61pci_bbp_read(rt2x00dev, 4, &r4); | |
848 | rt61pci_bbp_read(rt2x00dev, 77, &r77); | |
e4cd2ff8 | 849 | |
e4cd2ff8 ID |
850 | /* |
851 | * Configure the RX antenna. | |
852 | */ | |
853 | switch (ant->rx) { | |
854 | case ANTENNA_A: | |
acaa410d MN |
855 | rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA_CONTROL, 1); |
856 | rt2x00_set_field8(&r77, BBP_R77_RX_ANTENNA, 0); | |
857 | rt61pci_config_antenna_2529_rx(rt2x00dev, 0, 0); | |
e4cd2ff8 | 858 | break; |
e4cd2ff8 ID |
859 | case ANTENNA_HW_DIVERSITY: |
860 | /* | |
a4fe07d9 ID |
861 | * FIXME: Antenna selection for the rf 2529 is very confusing |
862 | * in the legacy driver. Just default to antenna B until the | |
863 | * legacy code can be properly translated into rt2x00 code. | |
e4cd2ff8 ID |
864 | */ |
865 | case ANTENNA_B: | |
a4fe07d9 | 866 | default: |
acaa410d MN |
867 | rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA_CONTROL, 1); |
868 | rt2x00_set_field8(&r77, BBP_R77_RX_ANTENNA, 3); | |
869 | rt61pci_config_antenna_2529_rx(rt2x00dev, 1, 1); | |
e4cd2ff8 ID |
870 | break; |
871 | } | |
872 | ||
e4cd2ff8 | 873 | rt61pci_bbp_write(rt2x00dev, 77, r77); |
95ea3627 ID |
874 | rt61pci_bbp_write(rt2x00dev, 3, r3); |
875 | rt61pci_bbp_write(rt2x00dev, 4, r4); | |
876 | } | |
877 | ||
878 | struct antenna_sel { | |
879 | u8 word; | |
880 | /* | |
881 | * value[0] -> non-LNA | |
882 | * value[1] -> LNA | |
883 | */ | |
884 | u8 value[2]; | |
885 | }; | |
886 | ||
887 | static const struct antenna_sel antenna_sel_a[] = { | |
888 | { 96, { 0x58, 0x78 } }, | |
889 | { 104, { 0x38, 0x48 } }, | |
890 | { 75, { 0xfe, 0x80 } }, | |
891 | { 86, { 0xfe, 0x80 } }, | |
892 | { 88, { 0xfe, 0x80 } }, | |
893 | { 35, { 0x60, 0x60 } }, | |
894 | { 97, { 0x58, 0x58 } }, | |
895 | { 98, { 0x58, 0x58 } }, | |
896 | }; | |
897 | ||
898 | static const struct antenna_sel antenna_sel_bg[] = { | |
899 | { 96, { 0x48, 0x68 } }, | |
900 | { 104, { 0x2c, 0x3c } }, | |
901 | { 75, { 0xfe, 0x80 } }, | |
902 | { 86, { 0xfe, 0x80 } }, | |
903 | { 88, { 0xfe, 0x80 } }, | |
904 | { 35, { 0x50, 0x50 } }, | |
905 | { 97, { 0x48, 0x48 } }, | |
906 | { 98, { 0x48, 0x48 } }, | |
907 | }; | |
908 | ||
909 | static void rt61pci_config_antenna(struct rt2x00_dev *rt2x00dev, | |
addc81bd | 910 | struct antenna_setup *ant) |
95ea3627 ID |
911 | { |
912 | const struct antenna_sel *sel; | |
913 | unsigned int lna; | |
914 | unsigned int i; | |
915 | u32 reg; | |
916 | ||
a4fe07d9 ID |
917 | /* |
918 | * We should never come here because rt2x00lib is supposed | |
919 | * to catch this and send us the correct antenna explicitely. | |
920 | */ | |
921 | BUG_ON(ant->rx == ANTENNA_SW_DIVERSITY || | |
922 | ant->tx == ANTENNA_SW_DIVERSITY); | |
923 | ||
8318d78a | 924 | if (rt2x00dev->curr_band == IEEE80211_BAND_5GHZ) { |
95ea3627 ID |
925 | sel = antenna_sel_a; |
926 | lna = test_bit(CONFIG_EXTERNAL_LNA_A, &rt2x00dev->flags); | |
95ea3627 ID |
927 | } else { |
928 | sel = antenna_sel_bg; | |
929 | lna = test_bit(CONFIG_EXTERNAL_LNA_BG, &rt2x00dev->flags); | |
95ea3627 ID |
930 | } |
931 | ||
acaa410d MN |
932 | for (i = 0; i < ARRAY_SIZE(antenna_sel_a); i++) |
933 | rt61pci_bbp_write(rt2x00dev, sel[i].word, sel[i].value[lna]); | |
934 | ||
935 | rt2x00pci_register_read(rt2x00dev, PHY_CSR0, ®); | |
936 | ||
ddc827f9 | 937 | rt2x00_set_field32(®, PHY_CSR0_PA_PE_BG, |
8318d78a | 938 | rt2x00dev->curr_band == IEEE80211_BAND_2GHZ); |
ddc827f9 | 939 | rt2x00_set_field32(®, PHY_CSR0_PA_PE_A, |
8318d78a | 940 | rt2x00dev->curr_band == IEEE80211_BAND_5GHZ); |
ddc827f9 | 941 | |
95ea3627 ID |
942 | rt2x00pci_register_write(rt2x00dev, PHY_CSR0, reg); |
943 | ||
944 | if (rt2x00_rf(&rt2x00dev->chip, RF5225) || | |
945 | rt2x00_rf(&rt2x00dev->chip, RF5325)) | |
addc81bd | 946 | rt61pci_config_antenna_5x(rt2x00dev, ant); |
95ea3627 | 947 | else if (rt2x00_rf(&rt2x00dev->chip, RF2527)) |
addc81bd | 948 | rt61pci_config_antenna_2x(rt2x00dev, ant); |
95ea3627 ID |
949 | else if (rt2x00_rf(&rt2x00dev->chip, RF2529)) { |
950 | if (test_bit(CONFIG_DOUBLE_ANTENNA, &rt2x00dev->flags)) | |
addc81bd | 951 | rt61pci_config_antenna_2x(rt2x00dev, ant); |
95ea3627 | 952 | else |
addc81bd | 953 | rt61pci_config_antenna_2529(rt2x00dev, ant); |
95ea3627 ID |
954 | } |
955 | } | |
956 | ||
957 | static void rt61pci_config_duration(struct rt2x00_dev *rt2x00dev, | |
5c58ee51 | 958 | struct rt2x00lib_conf *libconf) |
95ea3627 ID |
959 | { |
960 | u32 reg; | |
961 | ||
962 | rt2x00pci_register_read(rt2x00dev, MAC_CSR9, ®); | |
5c58ee51 | 963 | rt2x00_set_field32(®, MAC_CSR9_SLOT_TIME, libconf->slot_time); |
95ea3627 ID |
964 | rt2x00pci_register_write(rt2x00dev, MAC_CSR9, reg); |
965 | ||
966 | rt2x00pci_register_read(rt2x00dev, MAC_CSR8, ®); | |
5c58ee51 | 967 | rt2x00_set_field32(®, MAC_CSR8_SIFS, libconf->sifs); |
95ea3627 | 968 | rt2x00_set_field32(®, MAC_CSR8_SIFS_AFTER_RX_OFDM, 3); |
5c58ee51 | 969 | rt2x00_set_field32(®, MAC_CSR8_EIFS, libconf->eifs); |
95ea3627 ID |
970 | rt2x00pci_register_write(rt2x00dev, MAC_CSR8, reg); |
971 | ||
972 | rt2x00pci_register_read(rt2x00dev, TXRX_CSR0, ®); | |
973 | rt2x00_set_field32(®, TXRX_CSR0_TSF_OFFSET, IEEE80211_HEADER); | |
974 | rt2x00pci_register_write(rt2x00dev, TXRX_CSR0, reg); | |
975 | ||
976 | rt2x00pci_register_read(rt2x00dev, TXRX_CSR4, ®); | |
977 | rt2x00_set_field32(®, TXRX_CSR4_AUTORESPOND_ENABLE, 1); | |
978 | rt2x00pci_register_write(rt2x00dev, TXRX_CSR4, reg); | |
979 | ||
980 | rt2x00pci_register_read(rt2x00dev, TXRX_CSR9, ®); | |
5c58ee51 ID |
981 | rt2x00_set_field32(®, TXRX_CSR9_BEACON_INTERVAL, |
982 | libconf->conf->beacon_int * 16); | |
95ea3627 ID |
983 | rt2x00pci_register_write(rt2x00dev, TXRX_CSR9, reg); |
984 | } | |
985 | ||
986 | static void rt61pci_config(struct rt2x00_dev *rt2x00dev, | |
6bb40dd1 ID |
987 | struct rt2x00lib_conf *libconf, |
988 | const unsigned int flags) | |
95ea3627 | 989 | { |
ba2ab471 ID |
990 | /* Always recalculate LNA gain before changing configuration */ |
991 | rt61pci_config_lna_gain(rt2x00dev, libconf); | |
992 | ||
95ea3627 | 993 | if (flags & CONFIG_UPDATE_PHYMODE) |
5c58ee51 | 994 | rt61pci_config_phymode(rt2x00dev, libconf->basic_rates); |
95ea3627 | 995 | if (flags & CONFIG_UPDATE_CHANNEL) |
5c58ee51 ID |
996 | rt61pci_config_channel(rt2x00dev, &libconf->rf, |
997 | libconf->conf->power_level); | |
95ea3627 | 998 | if ((flags & CONFIG_UPDATE_TXPOWER) && !(flags & CONFIG_UPDATE_CHANNEL)) |
5c58ee51 | 999 | rt61pci_config_txpower(rt2x00dev, libconf->conf->power_level); |
95ea3627 | 1000 | if (flags & CONFIG_UPDATE_ANTENNA) |
addc81bd | 1001 | rt61pci_config_antenna(rt2x00dev, &libconf->ant); |
95ea3627 | 1002 | if (flags & (CONFIG_UPDATE_SLOT_TIME | CONFIG_UPDATE_BEACON_INT)) |
5c58ee51 | 1003 | rt61pci_config_duration(rt2x00dev, libconf); |
95ea3627 ID |
1004 | } |
1005 | ||
95ea3627 ID |
1006 | /* |
1007 | * Link tuning | |
1008 | */ | |
ebcf26da ID |
1009 | static void rt61pci_link_stats(struct rt2x00_dev *rt2x00dev, |
1010 | struct link_qual *qual) | |
95ea3627 ID |
1011 | { |
1012 | u32 reg; | |
1013 | ||
1014 | /* | |
1015 | * Update FCS error count from register. | |
1016 | */ | |
1017 | rt2x00pci_register_read(rt2x00dev, STA_CSR0, ®); | |
ebcf26da | 1018 | qual->rx_failed = rt2x00_get_field32(reg, STA_CSR0_FCS_ERROR); |
95ea3627 ID |
1019 | |
1020 | /* | |
1021 | * Update False CCA count from register. | |
1022 | */ | |
1023 | rt2x00pci_register_read(rt2x00dev, STA_CSR1, ®); | |
ebcf26da | 1024 | qual->false_cca = rt2x00_get_field32(reg, STA_CSR1_FALSE_CCA_ERROR); |
95ea3627 ID |
1025 | } |
1026 | ||
1027 | static void rt61pci_reset_tuner(struct rt2x00_dev *rt2x00dev) | |
1028 | { | |
1029 | rt61pci_bbp_write(rt2x00dev, 17, 0x20); | |
1030 | rt2x00dev->link.vgc_level = 0x20; | |
1031 | } | |
1032 | ||
1033 | static void rt61pci_link_tuner(struct rt2x00_dev *rt2x00dev) | |
1034 | { | |
1035 | int rssi = rt2x00_get_link_rssi(&rt2x00dev->link); | |
1036 | u8 r17; | |
1037 | u8 up_bound; | |
1038 | u8 low_bound; | |
1039 | ||
95ea3627 ID |
1040 | rt61pci_bbp_read(rt2x00dev, 17, &r17); |
1041 | ||
1042 | /* | |
1043 | * Determine r17 bounds. | |
1044 | */ | |
1497074a | 1045 | if (rt2x00dev->rx_status.band == IEEE80211_BAND_5GHZ) { |
95ea3627 ID |
1046 | low_bound = 0x28; |
1047 | up_bound = 0x48; | |
1048 | if (test_bit(CONFIG_EXTERNAL_LNA_A, &rt2x00dev->flags)) { | |
1049 | low_bound += 0x10; | |
1050 | up_bound += 0x10; | |
1051 | } | |
1052 | } else { | |
1053 | low_bound = 0x20; | |
1054 | up_bound = 0x40; | |
1055 | if (test_bit(CONFIG_EXTERNAL_LNA_BG, &rt2x00dev->flags)) { | |
1056 | low_bound += 0x10; | |
1057 | up_bound += 0x10; | |
1058 | } | |
1059 | } | |
1060 | ||
6bb40dd1 ID |
1061 | /* |
1062 | * If we are not associated, we should go straight to the | |
1063 | * dynamic CCA tuning. | |
1064 | */ | |
1065 | if (!rt2x00dev->intf_associated) | |
1066 | goto dynamic_cca_tune; | |
1067 | ||
95ea3627 ID |
1068 | /* |
1069 | * Special big-R17 for very short distance | |
1070 | */ | |
1071 | if (rssi >= -35) { | |
1072 | if (r17 != 0x60) | |
1073 | rt61pci_bbp_write(rt2x00dev, 17, 0x60); | |
1074 | return; | |
1075 | } | |
1076 | ||
1077 | /* | |
1078 | * Special big-R17 for short distance | |
1079 | */ | |
1080 | if (rssi >= -58) { | |
1081 | if (r17 != up_bound) | |
1082 | rt61pci_bbp_write(rt2x00dev, 17, up_bound); | |
1083 | return; | |
1084 | } | |
1085 | ||
1086 | /* | |
1087 | * Special big-R17 for middle-short distance | |
1088 | */ | |
1089 | if (rssi >= -66) { | |
1090 | low_bound += 0x10; | |
1091 | if (r17 != low_bound) | |
1092 | rt61pci_bbp_write(rt2x00dev, 17, low_bound); | |
1093 | return; | |
1094 | } | |
1095 | ||
1096 | /* | |
1097 | * Special mid-R17 for middle distance | |
1098 | */ | |
1099 | if (rssi >= -74) { | |
1100 | low_bound += 0x08; | |
1101 | if (r17 != low_bound) | |
1102 | rt61pci_bbp_write(rt2x00dev, 17, low_bound); | |
1103 | return; | |
1104 | } | |
1105 | ||
1106 | /* | |
1107 | * Special case: Change up_bound based on the rssi. | |
1108 | * Lower up_bound when rssi is weaker then -74 dBm. | |
1109 | */ | |
1110 | up_bound -= 2 * (-74 - rssi); | |
1111 | if (low_bound > up_bound) | |
1112 | up_bound = low_bound; | |
1113 | ||
1114 | if (r17 > up_bound) { | |
1115 | rt61pci_bbp_write(rt2x00dev, 17, up_bound); | |
1116 | return; | |
1117 | } | |
1118 | ||
6bb40dd1 ID |
1119 | dynamic_cca_tune: |
1120 | ||
95ea3627 ID |
1121 | /* |
1122 | * r17 does not yet exceed upper limit, continue and base | |
1123 | * the r17 tuning on the false CCA count. | |
1124 | */ | |
ebcf26da | 1125 | if (rt2x00dev->link.qual.false_cca > 512 && r17 < up_bound) { |
95ea3627 ID |
1126 | if (++r17 > up_bound) |
1127 | r17 = up_bound; | |
1128 | rt61pci_bbp_write(rt2x00dev, 17, r17); | |
ebcf26da | 1129 | } else if (rt2x00dev->link.qual.false_cca < 100 && r17 > low_bound) { |
95ea3627 ID |
1130 | if (--r17 < low_bound) |
1131 | r17 = low_bound; | |
1132 | rt61pci_bbp_write(rt2x00dev, 17, r17); | |
1133 | } | |
1134 | } | |
1135 | ||
1136 | /* | |
a7f3a06c | 1137 | * Firmware functions |
95ea3627 ID |
1138 | */ |
1139 | static char *rt61pci_get_firmware_name(struct rt2x00_dev *rt2x00dev) | |
1140 | { | |
1141 | char *fw_name; | |
1142 | ||
1143 | switch (rt2x00dev->chip.rt) { | |
1144 | case RT2561: | |
1145 | fw_name = FIRMWARE_RT2561; | |
1146 | break; | |
1147 | case RT2561s: | |
1148 | fw_name = FIRMWARE_RT2561s; | |
1149 | break; | |
1150 | case RT2661: | |
1151 | fw_name = FIRMWARE_RT2661; | |
1152 | break; | |
1153 | default: | |
1154 | fw_name = NULL; | |
1155 | break; | |
1156 | } | |
1157 | ||
1158 | return fw_name; | |
1159 | } | |
1160 | ||
f160ebcb | 1161 | static u16 rt61pci_get_firmware_crc(const void *data, const size_t len) |
a7f3a06c ID |
1162 | { |
1163 | u16 crc; | |
1164 | ||
1165 | /* | |
1166 | * Use the crc itu-t algorithm. | |
1167 | * The last 2 bytes in the firmware array are the crc checksum itself, | |
1168 | * this means that we should never pass those 2 bytes to the crc | |
1169 | * algorithm. | |
1170 | */ | |
1171 | crc = crc_itu_t(0, data, len - 2); | |
1172 | crc = crc_itu_t_byte(crc, 0); | |
1173 | crc = crc_itu_t_byte(crc, 0); | |
1174 | ||
1175 | return crc; | |
1176 | } | |
1177 | ||
f160ebcb | 1178 | static int rt61pci_load_firmware(struct rt2x00_dev *rt2x00dev, const void *data, |
95ea3627 ID |
1179 | const size_t len) |
1180 | { | |
1181 | int i; | |
1182 | u32 reg; | |
1183 | ||
1184 | /* | |
1185 | * Wait for stable hardware. | |
1186 | */ | |
1187 | for (i = 0; i < 100; i++) { | |
1188 | rt2x00pci_register_read(rt2x00dev, MAC_CSR0, ®); | |
1189 | if (reg) | |
1190 | break; | |
1191 | msleep(1); | |
1192 | } | |
1193 | ||
1194 | if (!reg) { | |
1195 | ERROR(rt2x00dev, "Unstable hardware.\n"); | |
1196 | return -EBUSY; | |
1197 | } | |
1198 | ||
1199 | /* | |
1200 | * Prepare MCU and mailbox for firmware loading. | |
1201 | */ | |
1202 | reg = 0; | |
1203 | rt2x00_set_field32(®, MCU_CNTL_CSR_RESET, 1); | |
1204 | rt2x00pci_register_write(rt2x00dev, MCU_CNTL_CSR, reg); | |
1205 | rt2x00pci_register_write(rt2x00dev, M2H_CMD_DONE_CSR, 0xffffffff); | |
1206 | rt2x00pci_register_write(rt2x00dev, H2M_MAILBOX_CSR, 0); | |
1207 | rt2x00pci_register_write(rt2x00dev, HOST_CMD_CSR, 0); | |
1208 | ||
1209 | /* | |
1210 | * Write firmware to device. | |
1211 | */ | |
1212 | reg = 0; | |
1213 | rt2x00_set_field32(®, MCU_CNTL_CSR_RESET, 1); | |
1214 | rt2x00_set_field32(®, MCU_CNTL_CSR_SELECT_BANK, 1); | |
1215 | rt2x00pci_register_write(rt2x00dev, MCU_CNTL_CSR, reg); | |
1216 | ||
1217 | rt2x00pci_register_multiwrite(rt2x00dev, FIRMWARE_IMAGE_BASE, | |
1218 | data, len); | |
1219 | ||
1220 | rt2x00_set_field32(®, MCU_CNTL_CSR_SELECT_BANK, 0); | |
1221 | rt2x00pci_register_write(rt2x00dev, MCU_CNTL_CSR, reg); | |
1222 | ||
1223 | rt2x00_set_field32(®, MCU_CNTL_CSR_RESET, 0); | |
1224 | rt2x00pci_register_write(rt2x00dev, MCU_CNTL_CSR, reg); | |
1225 | ||
1226 | for (i = 0; i < 100; i++) { | |
1227 | rt2x00pci_register_read(rt2x00dev, MCU_CNTL_CSR, ®); | |
1228 | if (rt2x00_get_field32(reg, MCU_CNTL_CSR_READY)) | |
1229 | break; | |
1230 | msleep(1); | |
1231 | } | |
1232 | ||
1233 | if (i == 100) { | |
1234 | ERROR(rt2x00dev, "MCU Control register not ready.\n"); | |
1235 | return -EBUSY; | |
1236 | } | |
1237 | ||
e6d3e902 ID |
1238 | /* |
1239 | * Hardware needs another millisecond before it is ready. | |
1240 | */ | |
1241 | msleep(1); | |
1242 | ||
95ea3627 ID |
1243 | /* |
1244 | * Reset MAC and BBP registers. | |
1245 | */ | |
1246 | reg = 0; | |
1247 | rt2x00_set_field32(®, MAC_CSR1_SOFT_RESET, 1); | |
1248 | rt2x00_set_field32(®, MAC_CSR1_BBP_RESET, 1); | |
1249 | rt2x00pci_register_write(rt2x00dev, MAC_CSR1, reg); | |
1250 | ||
1251 | rt2x00pci_register_read(rt2x00dev, MAC_CSR1, ®); | |
1252 | rt2x00_set_field32(®, MAC_CSR1_SOFT_RESET, 0); | |
1253 | rt2x00_set_field32(®, MAC_CSR1_BBP_RESET, 0); | |
1254 | rt2x00pci_register_write(rt2x00dev, MAC_CSR1, reg); | |
1255 | ||
1256 | rt2x00pci_register_read(rt2x00dev, MAC_CSR1, ®); | |
1257 | rt2x00_set_field32(®, MAC_CSR1_HOST_READY, 1); | |
1258 | rt2x00pci_register_write(rt2x00dev, MAC_CSR1, reg); | |
1259 | ||
1260 | return 0; | |
1261 | } | |
1262 | ||
a7f3a06c ID |
1263 | /* |
1264 | * Initialization functions. | |
1265 | */ | |
837e7f24 | 1266 | static void rt61pci_init_rxentry(struct rt2x00_dev *rt2x00dev, |
181d6902 | 1267 | struct queue_entry *entry) |
95ea3627 | 1268 | { |
b8be63ff | 1269 | struct queue_entry_priv_pci *entry_priv = entry->priv_data; |
c4da0048 | 1270 | struct skb_frame_desc *skbdesc = get_skb_frame_desc(entry->skb); |
95ea3627 ID |
1271 | u32 word; |
1272 | ||
b8be63ff | 1273 | rt2x00_desc_read(entry_priv->desc, 5, &word); |
30b3a23c | 1274 | rt2x00_set_field32(&word, RXD_W5_BUFFER_PHYSICAL_ADDRESS, |
c4da0048 | 1275 | skbdesc->skb_dma); |
b8be63ff | 1276 | rt2x00_desc_write(entry_priv->desc, 5, word); |
95ea3627 | 1277 | |
b8be63ff | 1278 | rt2x00_desc_read(entry_priv->desc, 0, &word); |
837e7f24 | 1279 | rt2x00_set_field32(&word, RXD_W0_OWNER_NIC, 1); |
b8be63ff | 1280 | rt2x00_desc_write(entry_priv->desc, 0, word); |
95ea3627 ID |
1281 | } |
1282 | ||
837e7f24 | 1283 | static void rt61pci_init_txentry(struct rt2x00_dev *rt2x00dev, |
181d6902 | 1284 | struct queue_entry *entry) |
95ea3627 | 1285 | { |
b8be63ff | 1286 | struct queue_entry_priv_pci *entry_priv = entry->priv_data; |
95ea3627 ID |
1287 | u32 word; |
1288 | ||
b8be63ff | 1289 | rt2x00_desc_read(entry_priv->desc, 0, &word); |
837e7f24 ID |
1290 | rt2x00_set_field32(&word, TXD_W0_VALID, 0); |
1291 | rt2x00_set_field32(&word, TXD_W0_OWNER_NIC, 0); | |
b8be63ff | 1292 | rt2x00_desc_write(entry_priv->desc, 0, word); |
95ea3627 ID |
1293 | } |
1294 | ||
181d6902 | 1295 | static int rt61pci_init_queues(struct rt2x00_dev *rt2x00dev) |
95ea3627 | 1296 | { |
b8be63ff | 1297 | struct queue_entry_priv_pci *entry_priv; |
95ea3627 ID |
1298 | u32 reg; |
1299 | ||
95ea3627 ID |
1300 | /* |
1301 | * Initialize registers. | |
1302 | */ | |
1303 | rt2x00pci_register_read(rt2x00dev, TX_RING_CSR0, ®); | |
1304 | rt2x00_set_field32(®, TX_RING_CSR0_AC0_RING_SIZE, | |
181d6902 | 1305 | rt2x00dev->tx[0].limit); |
95ea3627 | 1306 | rt2x00_set_field32(®, TX_RING_CSR0_AC1_RING_SIZE, |
181d6902 | 1307 | rt2x00dev->tx[1].limit); |
95ea3627 | 1308 | rt2x00_set_field32(®, TX_RING_CSR0_AC2_RING_SIZE, |
181d6902 | 1309 | rt2x00dev->tx[2].limit); |
95ea3627 | 1310 | rt2x00_set_field32(®, TX_RING_CSR0_AC3_RING_SIZE, |
181d6902 | 1311 | rt2x00dev->tx[3].limit); |
95ea3627 ID |
1312 | rt2x00pci_register_write(rt2x00dev, TX_RING_CSR0, reg); |
1313 | ||
1314 | rt2x00pci_register_read(rt2x00dev, TX_RING_CSR1, ®); | |
95ea3627 | 1315 | rt2x00_set_field32(®, TX_RING_CSR1_TXD_SIZE, |
181d6902 | 1316 | rt2x00dev->tx[0].desc_size / 4); |
95ea3627 ID |
1317 | rt2x00pci_register_write(rt2x00dev, TX_RING_CSR1, reg); |
1318 | ||
b8be63ff | 1319 | entry_priv = rt2x00dev->tx[0].entries[0].priv_data; |
95ea3627 | 1320 | rt2x00pci_register_read(rt2x00dev, AC0_BASE_CSR, ®); |
30b3a23c | 1321 | rt2x00_set_field32(®, AC0_BASE_CSR_RING_REGISTER, |
b8be63ff | 1322 | entry_priv->desc_dma); |
95ea3627 ID |
1323 | rt2x00pci_register_write(rt2x00dev, AC0_BASE_CSR, reg); |
1324 | ||
b8be63ff | 1325 | entry_priv = rt2x00dev->tx[1].entries[0].priv_data; |
95ea3627 | 1326 | rt2x00pci_register_read(rt2x00dev, AC1_BASE_CSR, ®); |
30b3a23c | 1327 | rt2x00_set_field32(®, AC1_BASE_CSR_RING_REGISTER, |
b8be63ff | 1328 | entry_priv->desc_dma); |
95ea3627 ID |
1329 | rt2x00pci_register_write(rt2x00dev, AC1_BASE_CSR, reg); |
1330 | ||
b8be63ff | 1331 | entry_priv = rt2x00dev->tx[2].entries[0].priv_data; |
95ea3627 | 1332 | rt2x00pci_register_read(rt2x00dev, AC2_BASE_CSR, ®); |
30b3a23c | 1333 | rt2x00_set_field32(®, AC2_BASE_CSR_RING_REGISTER, |
b8be63ff | 1334 | entry_priv->desc_dma); |
95ea3627 ID |
1335 | rt2x00pci_register_write(rt2x00dev, AC2_BASE_CSR, reg); |
1336 | ||
b8be63ff | 1337 | entry_priv = rt2x00dev->tx[3].entries[0].priv_data; |
95ea3627 | 1338 | rt2x00pci_register_read(rt2x00dev, AC3_BASE_CSR, ®); |
30b3a23c | 1339 | rt2x00_set_field32(®, AC3_BASE_CSR_RING_REGISTER, |
b8be63ff | 1340 | entry_priv->desc_dma); |
95ea3627 ID |
1341 | rt2x00pci_register_write(rt2x00dev, AC3_BASE_CSR, reg); |
1342 | ||
95ea3627 | 1343 | rt2x00pci_register_read(rt2x00dev, RX_RING_CSR, ®); |
181d6902 | 1344 | rt2x00_set_field32(®, RX_RING_CSR_RING_SIZE, rt2x00dev->rx->limit); |
95ea3627 ID |
1345 | rt2x00_set_field32(®, RX_RING_CSR_RXD_SIZE, |
1346 | rt2x00dev->rx->desc_size / 4); | |
1347 | rt2x00_set_field32(®, RX_RING_CSR_RXD_WRITEBACK_SIZE, 4); | |
1348 | rt2x00pci_register_write(rt2x00dev, RX_RING_CSR, reg); | |
1349 | ||
b8be63ff | 1350 | entry_priv = rt2x00dev->rx->entries[0].priv_data; |
95ea3627 | 1351 | rt2x00pci_register_read(rt2x00dev, RX_BASE_CSR, ®); |
30b3a23c | 1352 | rt2x00_set_field32(®, RX_BASE_CSR_RING_REGISTER, |
b8be63ff | 1353 | entry_priv->desc_dma); |
95ea3627 ID |
1354 | rt2x00pci_register_write(rt2x00dev, RX_BASE_CSR, reg); |
1355 | ||
1356 | rt2x00pci_register_read(rt2x00dev, TX_DMA_DST_CSR, ®); | |
1357 | rt2x00_set_field32(®, TX_DMA_DST_CSR_DEST_AC0, 2); | |
1358 | rt2x00_set_field32(®, TX_DMA_DST_CSR_DEST_AC1, 2); | |
1359 | rt2x00_set_field32(®, TX_DMA_DST_CSR_DEST_AC2, 2); | |
1360 | rt2x00_set_field32(®, TX_DMA_DST_CSR_DEST_AC3, 2); | |
95ea3627 ID |
1361 | rt2x00pci_register_write(rt2x00dev, TX_DMA_DST_CSR, reg); |
1362 | ||
1363 | rt2x00pci_register_read(rt2x00dev, LOAD_TX_RING_CSR, ®); | |
1364 | rt2x00_set_field32(®, LOAD_TX_RING_CSR_LOAD_TXD_AC0, 1); | |
1365 | rt2x00_set_field32(®, LOAD_TX_RING_CSR_LOAD_TXD_AC1, 1); | |
1366 | rt2x00_set_field32(®, LOAD_TX_RING_CSR_LOAD_TXD_AC2, 1); | |
1367 | rt2x00_set_field32(®, LOAD_TX_RING_CSR_LOAD_TXD_AC3, 1); | |
95ea3627 ID |
1368 | rt2x00pci_register_write(rt2x00dev, LOAD_TX_RING_CSR, reg); |
1369 | ||
1370 | rt2x00pci_register_read(rt2x00dev, RX_CNTL_CSR, ®); | |
1371 | rt2x00_set_field32(®, RX_CNTL_CSR_LOAD_RXD, 1); | |
1372 | rt2x00pci_register_write(rt2x00dev, RX_CNTL_CSR, reg); | |
1373 | ||
1374 | return 0; | |
1375 | } | |
1376 | ||
1377 | static int rt61pci_init_registers(struct rt2x00_dev *rt2x00dev) | |
1378 | { | |
1379 | u32 reg; | |
1380 | ||
1381 | rt2x00pci_register_read(rt2x00dev, TXRX_CSR0, ®); | |
1382 | rt2x00_set_field32(®, TXRX_CSR0_AUTO_TX_SEQ, 1); | |
1383 | rt2x00_set_field32(®, TXRX_CSR0_DISABLE_RX, 0); | |
1384 | rt2x00_set_field32(®, TXRX_CSR0_TX_WITHOUT_WAITING, 0); | |
1385 | rt2x00pci_register_write(rt2x00dev, TXRX_CSR0, reg); | |
1386 | ||
1387 | rt2x00pci_register_read(rt2x00dev, TXRX_CSR1, ®); | |
1388 | rt2x00_set_field32(®, TXRX_CSR1_BBP_ID0, 47); /* CCK Signal */ | |
1389 | rt2x00_set_field32(®, TXRX_CSR1_BBP_ID0_VALID, 1); | |
1390 | rt2x00_set_field32(®, TXRX_CSR1_BBP_ID1, 30); /* Rssi */ | |
1391 | rt2x00_set_field32(®, TXRX_CSR1_BBP_ID1_VALID, 1); | |
1392 | rt2x00_set_field32(®, TXRX_CSR1_BBP_ID2, 42); /* OFDM Rate */ | |
1393 | rt2x00_set_field32(®, TXRX_CSR1_BBP_ID2_VALID, 1); | |
1394 | rt2x00_set_field32(®, TXRX_CSR1_BBP_ID3, 30); /* Rssi */ | |
1395 | rt2x00_set_field32(®, TXRX_CSR1_BBP_ID3_VALID, 1); | |
1396 | rt2x00pci_register_write(rt2x00dev, TXRX_CSR1, reg); | |
1397 | ||
1398 | /* | |
1399 | * CCK TXD BBP registers | |
1400 | */ | |
1401 | rt2x00pci_register_read(rt2x00dev, TXRX_CSR2, ®); | |
1402 | rt2x00_set_field32(®, TXRX_CSR2_BBP_ID0, 13); | |
1403 | rt2x00_set_field32(®, TXRX_CSR2_BBP_ID0_VALID, 1); | |
1404 | rt2x00_set_field32(®, TXRX_CSR2_BBP_ID1, 12); | |
1405 | rt2x00_set_field32(®, TXRX_CSR2_BBP_ID1_VALID, 1); | |
1406 | rt2x00_set_field32(®, TXRX_CSR2_BBP_ID2, 11); | |
1407 | rt2x00_set_field32(®, TXRX_CSR2_BBP_ID2_VALID, 1); | |
1408 | rt2x00_set_field32(®, TXRX_CSR2_BBP_ID3, 10); | |
1409 | rt2x00_set_field32(®, TXRX_CSR2_BBP_ID3_VALID, 1); | |
1410 | rt2x00pci_register_write(rt2x00dev, TXRX_CSR2, reg); | |
1411 | ||
1412 | /* | |
1413 | * OFDM TXD BBP registers | |
1414 | */ | |
1415 | rt2x00pci_register_read(rt2x00dev, TXRX_CSR3, ®); | |
1416 | rt2x00_set_field32(®, TXRX_CSR3_BBP_ID0, 7); | |
1417 | rt2x00_set_field32(®, TXRX_CSR3_BBP_ID0_VALID, 1); | |
1418 | rt2x00_set_field32(®, TXRX_CSR3_BBP_ID1, 6); | |
1419 | rt2x00_set_field32(®, TXRX_CSR3_BBP_ID1_VALID, 1); | |
1420 | rt2x00_set_field32(®, TXRX_CSR3_BBP_ID2, 5); | |
1421 | rt2x00_set_field32(®, TXRX_CSR3_BBP_ID2_VALID, 1); | |
1422 | rt2x00pci_register_write(rt2x00dev, TXRX_CSR3, reg); | |
1423 | ||
1424 | rt2x00pci_register_read(rt2x00dev, TXRX_CSR7, ®); | |
1425 | rt2x00_set_field32(®, TXRX_CSR7_ACK_CTS_6MBS, 59); | |
1426 | rt2x00_set_field32(®, TXRX_CSR7_ACK_CTS_9MBS, 53); | |
1427 | rt2x00_set_field32(®, TXRX_CSR7_ACK_CTS_12MBS, 49); | |
1428 | rt2x00_set_field32(®, TXRX_CSR7_ACK_CTS_18MBS, 46); | |
1429 | rt2x00pci_register_write(rt2x00dev, TXRX_CSR7, reg); | |
1430 | ||
1431 | rt2x00pci_register_read(rt2x00dev, TXRX_CSR8, ®); | |
1432 | rt2x00_set_field32(®, TXRX_CSR8_ACK_CTS_24MBS, 44); | |
1433 | rt2x00_set_field32(®, TXRX_CSR8_ACK_CTS_36MBS, 42); | |
1434 | rt2x00_set_field32(®, TXRX_CSR8_ACK_CTS_48MBS, 42); | |
1435 | rt2x00_set_field32(®, TXRX_CSR8_ACK_CTS_54MBS, 42); | |
1436 | rt2x00pci_register_write(rt2x00dev, TXRX_CSR8, reg); | |
1437 | ||
1f909162 ID |
1438 | rt2x00pci_register_read(rt2x00dev, TXRX_CSR9, ®); |
1439 | rt2x00_set_field32(®, TXRX_CSR9_BEACON_INTERVAL, 0); | |
1440 | rt2x00_set_field32(®, TXRX_CSR9_TSF_TICKING, 0); | |
1441 | rt2x00_set_field32(®, TXRX_CSR9_TSF_SYNC, 0); | |
1442 | rt2x00_set_field32(®, TXRX_CSR9_TBTT_ENABLE, 0); | |
1443 | rt2x00_set_field32(®, TXRX_CSR9_BEACON_GEN, 0); | |
1444 | rt2x00_set_field32(®, TXRX_CSR9_TIMESTAMP_COMPENSATE, 0); | |
1445 | rt2x00pci_register_write(rt2x00dev, TXRX_CSR9, reg); | |
1446 | ||
95ea3627 ID |
1447 | rt2x00pci_register_write(rt2x00dev, TXRX_CSR15, 0x0000000f); |
1448 | ||
1449 | rt2x00pci_register_write(rt2x00dev, MAC_CSR6, 0x00000fff); | |
1450 | ||
1451 | rt2x00pci_register_read(rt2x00dev, MAC_CSR9, ®); | |
1452 | rt2x00_set_field32(®, MAC_CSR9_CW_SELECT, 0); | |
1453 | rt2x00pci_register_write(rt2x00dev, MAC_CSR9, reg); | |
1454 | ||
1455 | rt2x00pci_register_write(rt2x00dev, MAC_CSR10, 0x0000071c); | |
1456 | ||
1457 | if (rt2x00dev->ops->lib->set_device_state(rt2x00dev, STATE_AWAKE)) | |
1458 | return -EBUSY; | |
1459 | ||
1460 | rt2x00pci_register_write(rt2x00dev, MAC_CSR13, 0x0000e000); | |
1461 | ||
1462 | /* | |
1463 | * Invalidate all Shared Keys (SEC_CSR0), | |
1464 | * and clear the Shared key Cipher algorithms (SEC_CSR1 & SEC_CSR5) | |
1465 | */ | |
1466 | rt2x00pci_register_write(rt2x00dev, SEC_CSR0, 0x00000000); | |
1467 | rt2x00pci_register_write(rt2x00dev, SEC_CSR1, 0x00000000); | |
1468 | rt2x00pci_register_write(rt2x00dev, SEC_CSR5, 0x00000000); | |
1469 | ||
1470 | rt2x00pci_register_write(rt2x00dev, PHY_CSR1, 0x000023b0); | |
1471 | rt2x00pci_register_write(rt2x00dev, PHY_CSR5, 0x060a100c); | |
1472 | rt2x00pci_register_write(rt2x00dev, PHY_CSR6, 0x00080606); | |
1473 | rt2x00pci_register_write(rt2x00dev, PHY_CSR7, 0x00000a08); | |
1474 | ||
1475 | rt2x00pci_register_write(rt2x00dev, PCI_CFG_CSR, 0x28ca4404); | |
1476 | ||
1477 | rt2x00pci_register_write(rt2x00dev, TEST_MODE_CSR, 0x00000200); | |
1478 | ||
1479 | rt2x00pci_register_write(rt2x00dev, M2H_CMD_DONE_CSR, 0xffffffff); | |
1480 | ||
6bb40dd1 ID |
1481 | /* |
1482 | * Clear all beacons | |
1483 | * For the Beacon base registers we only need to clear | |
1484 | * the first byte since that byte contains the VALID and OWNER | |
1485 | * bits which (when set to 0) will invalidate the entire beacon. | |
1486 | */ | |
1487 | rt2x00pci_register_write(rt2x00dev, HW_BEACON_BASE0, 0); | |
1488 | rt2x00pci_register_write(rt2x00dev, HW_BEACON_BASE1, 0); | |
1489 | rt2x00pci_register_write(rt2x00dev, HW_BEACON_BASE2, 0); | |
1490 | rt2x00pci_register_write(rt2x00dev, HW_BEACON_BASE3, 0); | |
1491 | ||
95ea3627 ID |
1492 | /* |
1493 | * We must clear the error counters. | |
1494 | * These registers are cleared on read, | |
1495 | * so we may pass a useless variable to store the value. | |
1496 | */ | |
1497 | rt2x00pci_register_read(rt2x00dev, STA_CSR0, ®); | |
1498 | rt2x00pci_register_read(rt2x00dev, STA_CSR1, ®); | |
1499 | rt2x00pci_register_read(rt2x00dev, STA_CSR2, ®); | |
1500 | ||
1501 | /* | |
1502 | * Reset MAC and BBP registers. | |
1503 | */ | |
1504 | rt2x00pci_register_read(rt2x00dev, MAC_CSR1, ®); | |
1505 | rt2x00_set_field32(®, MAC_CSR1_SOFT_RESET, 1); | |
1506 | rt2x00_set_field32(®, MAC_CSR1_BBP_RESET, 1); | |
1507 | rt2x00pci_register_write(rt2x00dev, MAC_CSR1, reg); | |
1508 | ||
1509 | rt2x00pci_register_read(rt2x00dev, MAC_CSR1, ®); | |
1510 | rt2x00_set_field32(®, MAC_CSR1_SOFT_RESET, 0); | |
1511 | rt2x00_set_field32(®, MAC_CSR1_BBP_RESET, 0); | |
1512 | rt2x00pci_register_write(rt2x00dev, MAC_CSR1, reg); | |
1513 | ||
1514 | rt2x00pci_register_read(rt2x00dev, MAC_CSR1, ®); | |
1515 | rt2x00_set_field32(®, MAC_CSR1_HOST_READY, 1); | |
1516 | rt2x00pci_register_write(rt2x00dev, MAC_CSR1, reg); | |
1517 | ||
1518 | return 0; | |
1519 | } | |
1520 | ||
2b08da3f | 1521 | static int rt61pci_wait_bbp_ready(struct rt2x00_dev *rt2x00dev) |
95ea3627 ID |
1522 | { |
1523 | unsigned int i; | |
95ea3627 ID |
1524 | u8 value; |
1525 | ||
1526 | for (i = 0; i < REGISTER_BUSY_COUNT; i++) { | |
1527 | rt61pci_bbp_read(rt2x00dev, 0, &value); | |
1528 | if ((value != 0xff) && (value != 0x00)) | |
2b08da3f | 1529 | return 0; |
95ea3627 ID |
1530 | udelay(REGISTER_BUSY_DELAY); |
1531 | } | |
1532 | ||
1533 | ERROR(rt2x00dev, "BBP register access failed, aborting.\n"); | |
1534 | return -EACCES; | |
2b08da3f ID |
1535 | } |
1536 | ||
1537 | static int rt61pci_init_bbp(struct rt2x00_dev *rt2x00dev) | |
1538 | { | |
1539 | unsigned int i; | |
1540 | u16 eeprom; | |
1541 | u8 reg_id; | |
1542 | u8 value; | |
1543 | ||
1544 | if (unlikely(rt61pci_wait_bbp_ready(rt2x00dev))) | |
1545 | return -EACCES; | |
95ea3627 | 1546 | |
95ea3627 ID |
1547 | rt61pci_bbp_write(rt2x00dev, 3, 0x00); |
1548 | rt61pci_bbp_write(rt2x00dev, 15, 0x30); | |
1549 | rt61pci_bbp_write(rt2x00dev, 21, 0xc8); | |
1550 | rt61pci_bbp_write(rt2x00dev, 22, 0x38); | |
1551 | rt61pci_bbp_write(rt2x00dev, 23, 0x06); | |
1552 | rt61pci_bbp_write(rt2x00dev, 24, 0xfe); | |
1553 | rt61pci_bbp_write(rt2x00dev, 25, 0x0a); | |
1554 | rt61pci_bbp_write(rt2x00dev, 26, 0x0d); | |
1555 | rt61pci_bbp_write(rt2x00dev, 34, 0x12); | |
1556 | rt61pci_bbp_write(rt2x00dev, 37, 0x07); | |
1557 | rt61pci_bbp_write(rt2x00dev, 39, 0xf8); | |
1558 | rt61pci_bbp_write(rt2x00dev, 41, 0x60); | |
1559 | rt61pci_bbp_write(rt2x00dev, 53, 0x10); | |
1560 | rt61pci_bbp_write(rt2x00dev, 54, 0x18); | |
1561 | rt61pci_bbp_write(rt2x00dev, 60, 0x10); | |
1562 | rt61pci_bbp_write(rt2x00dev, 61, 0x04); | |
1563 | rt61pci_bbp_write(rt2x00dev, 62, 0x04); | |
1564 | rt61pci_bbp_write(rt2x00dev, 75, 0xfe); | |
1565 | rt61pci_bbp_write(rt2x00dev, 86, 0xfe); | |
1566 | rt61pci_bbp_write(rt2x00dev, 88, 0xfe); | |
1567 | rt61pci_bbp_write(rt2x00dev, 90, 0x0f); | |
1568 | rt61pci_bbp_write(rt2x00dev, 99, 0x00); | |
1569 | rt61pci_bbp_write(rt2x00dev, 102, 0x16); | |
1570 | rt61pci_bbp_write(rt2x00dev, 107, 0x04); | |
1571 | ||
95ea3627 ID |
1572 | for (i = 0; i < EEPROM_BBP_SIZE; i++) { |
1573 | rt2x00_eeprom_read(rt2x00dev, EEPROM_BBP_START + i, &eeprom); | |
1574 | ||
1575 | if (eeprom != 0xffff && eeprom != 0x0000) { | |
1576 | reg_id = rt2x00_get_field16(eeprom, EEPROM_BBP_REG_ID); | |
1577 | value = rt2x00_get_field16(eeprom, EEPROM_BBP_VALUE); | |
95ea3627 ID |
1578 | rt61pci_bbp_write(rt2x00dev, reg_id, value); |
1579 | } | |
1580 | } | |
95ea3627 ID |
1581 | |
1582 | return 0; | |
1583 | } | |
1584 | ||
1585 | /* | |
1586 | * Device state switch handlers. | |
1587 | */ | |
1588 | static void rt61pci_toggle_rx(struct rt2x00_dev *rt2x00dev, | |
1589 | enum dev_state state) | |
1590 | { | |
1591 | u32 reg; | |
1592 | ||
1593 | rt2x00pci_register_read(rt2x00dev, TXRX_CSR0, ®); | |
1594 | rt2x00_set_field32(®, TXRX_CSR0_DISABLE_RX, | |
2b08da3f ID |
1595 | (state == STATE_RADIO_RX_OFF) || |
1596 | (state == STATE_RADIO_RX_OFF_LINK)); | |
95ea3627 ID |
1597 | rt2x00pci_register_write(rt2x00dev, TXRX_CSR0, reg); |
1598 | } | |
1599 | ||
1600 | static void rt61pci_toggle_irq(struct rt2x00_dev *rt2x00dev, | |
1601 | enum dev_state state) | |
1602 | { | |
1603 | int mask = (state == STATE_RADIO_IRQ_OFF); | |
1604 | u32 reg; | |
1605 | ||
1606 | /* | |
1607 | * When interrupts are being enabled, the interrupt registers | |
1608 | * should clear the register to assure a clean state. | |
1609 | */ | |
1610 | if (state == STATE_RADIO_IRQ_ON) { | |
1611 | rt2x00pci_register_read(rt2x00dev, INT_SOURCE_CSR, ®); | |
1612 | rt2x00pci_register_write(rt2x00dev, INT_SOURCE_CSR, reg); | |
1613 | ||
1614 | rt2x00pci_register_read(rt2x00dev, MCU_INT_SOURCE_CSR, ®); | |
1615 | rt2x00pci_register_write(rt2x00dev, MCU_INT_SOURCE_CSR, reg); | |
1616 | } | |
1617 | ||
1618 | /* | |
1619 | * Only toggle the interrupts bits we are going to use. | |
1620 | * Non-checked interrupt bits are disabled by default. | |
1621 | */ | |
1622 | rt2x00pci_register_read(rt2x00dev, INT_MASK_CSR, ®); | |
1623 | rt2x00_set_field32(®, INT_MASK_CSR_TXDONE, mask); | |
1624 | rt2x00_set_field32(®, INT_MASK_CSR_RXDONE, mask); | |
1625 | rt2x00_set_field32(®, INT_MASK_CSR_ENABLE_MITIGATION, mask); | |
1626 | rt2x00_set_field32(®, INT_MASK_CSR_MITIGATION_PERIOD, 0xff); | |
1627 | rt2x00pci_register_write(rt2x00dev, INT_MASK_CSR, reg); | |
1628 | ||
1629 | rt2x00pci_register_read(rt2x00dev, MCU_INT_MASK_CSR, ®); | |
1630 | rt2x00_set_field32(®, MCU_INT_MASK_CSR_0, mask); | |
1631 | rt2x00_set_field32(®, MCU_INT_MASK_CSR_1, mask); | |
1632 | rt2x00_set_field32(®, MCU_INT_MASK_CSR_2, mask); | |
1633 | rt2x00_set_field32(®, MCU_INT_MASK_CSR_3, mask); | |
1634 | rt2x00_set_field32(®, MCU_INT_MASK_CSR_4, mask); | |
1635 | rt2x00_set_field32(®, MCU_INT_MASK_CSR_5, mask); | |
1636 | rt2x00_set_field32(®, MCU_INT_MASK_CSR_6, mask); | |
1637 | rt2x00_set_field32(®, MCU_INT_MASK_CSR_7, mask); | |
1638 | rt2x00pci_register_write(rt2x00dev, MCU_INT_MASK_CSR, reg); | |
1639 | } | |
1640 | ||
1641 | static int rt61pci_enable_radio(struct rt2x00_dev *rt2x00dev) | |
1642 | { | |
1643 | u32 reg; | |
1644 | ||
1645 | /* | |
1646 | * Initialize all registers. | |
1647 | */ | |
2b08da3f ID |
1648 | if (unlikely(rt61pci_init_queues(rt2x00dev) || |
1649 | rt61pci_init_registers(rt2x00dev) || | |
1650 | rt61pci_init_bbp(rt2x00dev))) | |
95ea3627 | 1651 | return -EIO; |
95ea3627 ID |
1652 | |
1653 | /* | |
1654 | * Enable RX. | |
1655 | */ | |
1656 | rt2x00pci_register_read(rt2x00dev, RX_CNTL_CSR, ®); | |
1657 | rt2x00_set_field32(®, RX_CNTL_CSR_ENABLE_RX_DMA, 1); | |
1658 | rt2x00pci_register_write(rt2x00dev, RX_CNTL_CSR, reg); | |
1659 | ||
95ea3627 ID |
1660 | return 0; |
1661 | } | |
1662 | ||
1663 | static void rt61pci_disable_radio(struct rt2x00_dev *rt2x00dev) | |
1664 | { | |
1665 | u32 reg; | |
1666 | ||
95ea3627 ID |
1667 | rt2x00pci_register_write(rt2x00dev, MAC_CSR10, 0x00001818); |
1668 | ||
1669 | /* | |
1670 | * Disable synchronisation. | |
1671 | */ | |
1672 | rt2x00pci_register_write(rt2x00dev, TXRX_CSR9, 0); | |
1673 | ||
1674 | /* | |
1675 | * Cancel RX and TX. | |
1676 | */ | |
1677 | rt2x00pci_register_read(rt2x00dev, TX_CNTL_CSR, ®); | |
1678 | rt2x00_set_field32(®, TX_CNTL_CSR_ABORT_TX_AC0, 1); | |
1679 | rt2x00_set_field32(®, TX_CNTL_CSR_ABORT_TX_AC1, 1); | |
1680 | rt2x00_set_field32(®, TX_CNTL_CSR_ABORT_TX_AC2, 1); | |
1681 | rt2x00_set_field32(®, TX_CNTL_CSR_ABORT_TX_AC3, 1); | |
95ea3627 | 1682 | rt2x00pci_register_write(rt2x00dev, TX_CNTL_CSR, reg); |
95ea3627 ID |
1683 | } |
1684 | ||
1685 | static int rt61pci_set_state(struct rt2x00_dev *rt2x00dev, enum dev_state state) | |
1686 | { | |
1687 | u32 reg; | |
1688 | unsigned int i; | |
1689 | char put_to_sleep; | |
95ea3627 ID |
1690 | |
1691 | put_to_sleep = (state != STATE_AWAKE); | |
1692 | ||
1693 | rt2x00pci_register_read(rt2x00dev, MAC_CSR12, ®); | |
1694 | rt2x00_set_field32(®, MAC_CSR12_FORCE_WAKEUP, !put_to_sleep); | |
1695 | rt2x00_set_field32(®, MAC_CSR12_PUT_TO_SLEEP, put_to_sleep); | |
1696 | rt2x00pci_register_write(rt2x00dev, MAC_CSR12, reg); | |
1697 | ||
1698 | /* | |
1699 | * Device is not guaranteed to be in the requested state yet. | |
1700 | * We must wait until the register indicates that the | |
1701 | * device has entered the correct state. | |
1702 | */ | |
1703 | for (i = 0; i < REGISTER_BUSY_COUNT; i++) { | |
1704 | rt2x00pci_register_read(rt2x00dev, MAC_CSR12, ®); | |
2b08da3f ID |
1705 | state = rt2x00_get_field32(reg, MAC_CSR12_BBP_CURRENT_STATE); |
1706 | if (state == !put_to_sleep) | |
95ea3627 ID |
1707 | return 0; |
1708 | msleep(10); | |
1709 | } | |
1710 | ||
95ea3627 ID |
1711 | return -EBUSY; |
1712 | } | |
1713 | ||
1714 | static int rt61pci_set_device_state(struct rt2x00_dev *rt2x00dev, | |
1715 | enum dev_state state) | |
1716 | { | |
1717 | int retval = 0; | |
1718 | ||
1719 | switch (state) { | |
1720 | case STATE_RADIO_ON: | |
1721 | retval = rt61pci_enable_radio(rt2x00dev); | |
1722 | break; | |
1723 | case STATE_RADIO_OFF: | |
1724 | rt61pci_disable_radio(rt2x00dev); | |
1725 | break; | |
1726 | case STATE_RADIO_RX_ON: | |
61667d8d | 1727 | case STATE_RADIO_RX_ON_LINK: |
95ea3627 | 1728 | case STATE_RADIO_RX_OFF: |
61667d8d | 1729 | case STATE_RADIO_RX_OFF_LINK: |
2b08da3f ID |
1730 | rt61pci_toggle_rx(rt2x00dev, state); |
1731 | break; | |
1732 | case STATE_RADIO_IRQ_ON: | |
1733 | case STATE_RADIO_IRQ_OFF: | |
1734 | rt61pci_toggle_irq(rt2x00dev, state); | |
95ea3627 ID |
1735 | break; |
1736 | case STATE_DEEP_SLEEP: | |
1737 | case STATE_SLEEP: | |
1738 | case STATE_STANDBY: | |
1739 | case STATE_AWAKE: | |
1740 | retval = rt61pci_set_state(rt2x00dev, state); | |
1741 | break; | |
1742 | default: | |
1743 | retval = -ENOTSUPP; | |
1744 | break; | |
1745 | } | |
1746 | ||
2b08da3f ID |
1747 | if (unlikely(retval)) |
1748 | ERROR(rt2x00dev, "Device failed to enter state %d (%d).\n", | |
1749 | state, retval); | |
1750 | ||
95ea3627 ID |
1751 | return retval; |
1752 | } | |
1753 | ||
1754 | /* | |
1755 | * TX descriptor initialization | |
1756 | */ | |
1757 | static void rt61pci_write_tx_desc(struct rt2x00_dev *rt2x00dev, | |
61e754f4 ID |
1758 | struct sk_buff *skb, |
1759 | struct txentry_desc *txdesc) | |
95ea3627 | 1760 | { |
181d6902 | 1761 | struct skb_frame_desc *skbdesc = get_skb_frame_desc(skb); |
dd3193e1 | 1762 | __le32 *txd = skbdesc->desc; |
95ea3627 ID |
1763 | u32 word; |
1764 | ||
1765 | /* | |
1766 | * Start writing the descriptor words. | |
1767 | */ | |
1768 | rt2x00_desc_read(txd, 1, &word); | |
181d6902 ID |
1769 | rt2x00_set_field32(&word, TXD_W1_HOST_Q_ID, txdesc->queue); |
1770 | rt2x00_set_field32(&word, TXD_W1_AIFSN, txdesc->aifs); | |
1771 | rt2x00_set_field32(&word, TXD_W1_CWMIN, txdesc->cw_min); | |
1772 | rt2x00_set_field32(&word, TXD_W1_CWMAX, txdesc->cw_max); | |
61e754f4 | 1773 | rt2x00_set_field32(&word, TXD_W1_IV_OFFSET, txdesc->iv_offset); |
5adf6d63 ID |
1774 | rt2x00_set_field32(&word, TXD_W1_HW_SEQUENCE, |
1775 | test_bit(ENTRY_TXD_GENERATE_SEQ, &txdesc->flags)); | |
4de36fe5 | 1776 | rt2x00_set_field32(&word, TXD_W1_BUFFER_COUNT, 1); |
95ea3627 ID |
1777 | rt2x00_desc_write(txd, 1, word); |
1778 | ||
1779 | rt2x00_desc_read(txd, 2, &word); | |
181d6902 ID |
1780 | rt2x00_set_field32(&word, TXD_W2_PLCP_SIGNAL, txdesc->signal); |
1781 | rt2x00_set_field32(&word, TXD_W2_PLCP_SERVICE, txdesc->service); | |
1782 | rt2x00_set_field32(&word, TXD_W2_PLCP_LENGTH_LOW, txdesc->length_low); | |
1783 | rt2x00_set_field32(&word, TXD_W2_PLCP_LENGTH_HIGH, txdesc->length_high); | |
95ea3627 ID |
1784 | rt2x00_desc_write(txd, 2, word); |
1785 | ||
61e754f4 ID |
1786 | if (test_bit(ENTRY_TXD_ENCRYPT, &txdesc->flags)) { |
1787 | _rt2x00_desc_write(txd, 3, skbdesc->iv); | |
1788 | _rt2x00_desc_write(txd, 4, skbdesc->eiv); | |
1789 | } | |
1790 | ||
95ea3627 | 1791 | rt2x00_desc_read(txd, 5, &word); |
4de36fe5 GW |
1792 | rt2x00_set_field32(&word, TXD_W5_PID_TYPE, skbdesc->entry->queue->qid); |
1793 | rt2x00_set_field32(&word, TXD_W5_PID_SUBTYPE, | |
1794 | skbdesc->entry->entry_idx); | |
95ea3627 | 1795 | rt2x00_set_field32(&word, TXD_W5_TX_POWER, |
ac1aa7e4 | 1796 | TXPOWER_TO_DEV(rt2x00dev->tx_power)); |
95ea3627 ID |
1797 | rt2x00_set_field32(&word, TXD_W5_WAITING_DMA_DONE_INT, 1); |
1798 | rt2x00_desc_write(txd, 5, word); | |
1799 | ||
4de36fe5 GW |
1800 | rt2x00_desc_read(txd, 6, &word); |
1801 | rt2x00_set_field32(&word, TXD_W6_BUFFER_PHYSICAL_ADDRESS, | |
c4da0048 | 1802 | skbdesc->skb_dma); |
4de36fe5 GW |
1803 | rt2x00_desc_write(txd, 6, word); |
1804 | ||
d7bafff3 AB |
1805 | if (skbdesc->desc_len > TXINFO_SIZE) { |
1806 | rt2x00_desc_read(txd, 11, &word); | |
d56d453a | 1807 | rt2x00_set_field32(&word, TXD_W11_BUFFER_LENGTH0, skb->len); |
d7bafff3 AB |
1808 | rt2x00_desc_write(txd, 11, word); |
1809 | } | |
95ea3627 ID |
1810 | |
1811 | rt2x00_desc_read(txd, 0, &word); | |
1812 | rt2x00_set_field32(&word, TXD_W0_OWNER_NIC, 1); | |
1813 | rt2x00_set_field32(&word, TXD_W0_VALID, 1); | |
1814 | rt2x00_set_field32(&word, TXD_W0_MORE_FRAG, | |
181d6902 | 1815 | test_bit(ENTRY_TXD_MORE_FRAG, &txdesc->flags)); |
95ea3627 | 1816 | rt2x00_set_field32(&word, TXD_W0_ACK, |
181d6902 | 1817 | test_bit(ENTRY_TXD_ACK, &txdesc->flags)); |
95ea3627 | 1818 | rt2x00_set_field32(&word, TXD_W0_TIMESTAMP, |
181d6902 | 1819 | test_bit(ENTRY_TXD_REQ_TIMESTAMP, &txdesc->flags)); |
95ea3627 | 1820 | rt2x00_set_field32(&word, TXD_W0_OFDM, |
181d6902 ID |
1821 | test_bit(ENTRY_TXD_OFDM_RATE, &txdesc->flags)); |
1822 | rt2x00_set_field32(&word, TXD_W0_IFS, txdesc->ifs); | |
95ea3627 | 1823 | rt2x00_set_field32(&word, TXD_W0_RETRY_MODE, |
61486e0f | 1824 | test_bit(ENTRY_TXD_RETRY_MODE, &txdesc->flags)); |
61e754f4 ID |
1825 | rt2x00_set_field32(&word, TXD_W0_TKIP_MIC, |
1826 | test_bit(ENTRY_TXD_ENCRYPT_MMIC, &txdesc->flags)); | |
1827 | rt2x00_set_field32(&word, TXD_W0_KEY_TABLE, | |
1828 | test_bit(ENTRY_TXD_ENCRYPT_PAIRWISE, &txdesc->flags)); | |
1829 | rt2x00_set_field32(&word, TXD_W0_KEY_INDEX, txdesc->key_idx); | |
d56d453a | 1830 | rt2x00_set_field32(&word, TXD_W0_DATABYTE_COUNT, skb->len); |
95ea3627 | 1831 | rt2x00_set_field32(&word, TXD_W0_BURST, |
181d6902 | 1832 | test_bit(ENTRY_TXD_BURST, &txdesc->flags)); |
61e754f4 | 1833 | rt2x00_set_field32(&word, TXD_W0_CIPHER_ALG, txdesc->cipher); |
95ea3627 ID |
1834 | rt2x00_desc_write(txd, 0, word); |
1835 | } | |
1836 | ||
1837 | /* | |
1838 | * TX data initialization | |
1839 | */ | |
bd88a781 ID |
1840 | static void rt61pci_write_beacon(struct queue_entry *entry) |
1841 | { | |
1842 | struct rt2x00_dev *rt2x00dev = entry->queue->rt2x00dev; | |
1843 | struct skb_frame_desc *skbdesc = get_skb_frame_desc(entry->skb); | |
1844 | unsigned int beacon_base; | |
1845 | u32 reg; | |
1846 | ||
1847 | /* | |
1848 | * Disable beaconing while we are reloading the beacon data, | |
1849 | * otherwise we might be sending out invalid data. | |
1850 | */ | |
1851 | rt2x00pci_register_read(rt2x00dev, TXRX_CSR9, ®); | |
1852 | rt2x00_set_field32(®, TXRX_CSR9_TSF_TICKING, 0); | |
1853 | rt2x00_set_field32(®, TXRX_CSR9_TBTT_ENABLE, 0); | |
1854 | rt2x00_set_field32(®, TXRX_CSR9_BEACON_GEN, 0); | |
1855 | rt2x00pci_register_write(rt2x00dev, TXRX_CSR9, reg); | |
1856 | ||
1857 | /* | |
1858 | * Write entire beacon with descriptor to register. | |
1859 | */ | |
1860 | beacon_base = HW_BEACON_OFFSET(entry->entry_idx); | |
1861 | rt2x00pci_register_multiwrite(rt2x00dev, | |
1862 | beacon_base, | |
1863 | skbdesc->desc, skbdesc->desc_len); | |
1864 | rt2x00pci_register_multiwrite(rt2x00dev, | |
1865 | beacon_base + skbdesc->desc_len, | |
1866 | entry->skb->data, entry->skb->len); | |
1867 | ||
1868 | /* | |
1869 | * Clean up beacon skb. | |
1870 | */ | |
1871 | dev_kfree_skb_any(entry->skb); | |
1872 | entry->skb = NULL; | |
1873 | } | |
1874 | ||
95ea3627 | 1875 | static void rt61pci_kick_tx_queue(struct rt2x00_dev *rt2x00dev, |
e58c6aca | 1876 | const enum data_queue_qid queue) |
95ea3627 ID |
1877 | { |
1878 | u32 reg; | |
1879 | ||
e58c6aca | 1880 | if (queue == QID_BEACON) { |
95ea3627 ID |
1881 | /* |
1882 | * For Wi-Fi faily generated beacons between participating | |
1883 | * stations. Set TBTT phase adaptive adjustment step to 8us. | |
1884 | */ | |
1885 | rt2x00pci_register_write(rt2x00dev, TXRX_CSR10, 0x00001008); | |
1886 | ||
1887 | rt2x00pci_register_read(rt2x00dev, TXRX_CSR9, ®); | |
1888 | if (!rt2x00_get_field32(reg, TXRX_CSR9_BEACON_GEN)) { | |
8af244cc ID |
1889 | rt2x00_set_field32(®, TXRX_CSR9_TSF_TICKING, 1); |
1890 | rt2x00_set_field32(®, TXRX_CSR9_TBTT_ENABLE, 1); | |
95ea3627 ID |
1891 | rt2x00_set_field32(®, TXRX_CSR9_BEACON_GEN, 1); |
1892 | rt2x00pci_register_write(rt2x00dev, TXRX_CSR9, reg); | |
1893 | } | |
1894 | return; | |
1895 | } | |
1896 | ||
1897 | rt2x00pci_register_read(rt2x00dev, TX_CNTL_CSR, ®); | |
e58c6aca ID |
1898 | rt2x00_set_field32(®, TX_CNTL_CSR_KICK_TX_AC0, (queue == QID_AC_BE)); |
1899 | rt2x00_set_field32(®, TX_CNTL_CSR_KICK_TX_AC1, (queue == QID_AC_BK)); | |
1900 | rt2x00_set_field32(®, TX_CNTL_CSR_KICK_TX_AC2, (queue == QID_AC_VI)); | |
1901 | rt2x00_set_field32(®, TX_CNTL_CSR_KICK_TX_AC3, (queue == QID_AC_VO)); | |
95ea3627 ID |
1902 | rt2x00pci_register_write(rt2x00dev, TX_CNTL_CSR, reg); |
1903 | } | |
1904 | ||
1905 | /* | |
1906 | * RX control handlers | |
1907 | */ | |
1908 | static int rt61pci_agc_to_rssi(struct rt2x00_dev *rt2x00dev, int rxd_w1) | |
1909 | { | |
ba2ab471 | 1910 | u8 offset = rt2x00dev->lna_gain; |
95ea3627 ID |
1911 | u8 lna; |
1912 | ||
1913 | lna = rt2x00_get_field32(rxd_w1, RXD_W1_RSSI_LNA); | |
1914 | switch (lna) { | |
1915 | case 3: | |
ba2ab471 | 1916 | offset += 90; |
95ea3627 ID |
1917 | break; |
1918 | case 2: | |
ba2ab471 | 1919 | offset += 74; |
95ea3627 ID |
1920 | break; |
1921 | case 1: | |
ba2ab471 | 1922 | offset += 64; |
95ea3627 ID |
1923 | break; |
1924 | default: | |
1925 | return 0; | |
1926 | } | |
1927 | ||
8318d78a | 1928 | if (rt2x00dev->rx_status.band == IEEE80211_BAND_5GHZ) { |
95ea3627 ID |
1929 | if (lna == 3 || lna == 2) |
1930 | offset += 10; | |
95ea3627 ID |
1931 | } |
1932 | ||
1933 | return rt2x00_get_field32(rxd_w1, RXD_W1_RSSI_AGC) * 2 - offset; | |
1934 | } | |
1935 | ||
181d6902 ID |
1936 | static void rt61pci_fill_rxdone(struct queue_entry *entry, |
1937 | struct rxdone_entry_desc *rxdesc) | |
95ea3627 | 1938 | { |
61e754f4 | 1939 | struct rt2x00_dev *rt2x00dev = entry->queue->rt2x00dev; |
b8be63ff | 1940 | struct queue_entry_priv_pci *entry_priv = entry->priv_data; |
95ea3627 ID |
1941 | u32 word0; |
1942 | u32 word1; | |
1943 | ||
b8be63ff ID |
1944 | rt2x00_desc_read(entry_priv->desc, 0, &word0); |
1945 | rt2x00_desc_read(entry_priv->desc, 1, &word1); | |
95ea3627 | 1946 | |
4150c572 | 1947 | if (rt2x00_get_field32(word0, RXD_W0_CRC_ERROR)) |
181d6902 | 1948 | rxdesc->flags |= RX_FLAG_FAILED_FCS_CRC; |
95ea3627 | 1949 | |
61e754f4 ID |
1950 | if (test_bit(CONFIG_SUPPORT_HW_CRYPTO, &rt2x00dev->flags)) { |
1951 | rxdesc->cipher = | |
1952 | rt2x00_get_field32(word0, RXD_W0_CIPHER_ALG); | |
1953 | rxdesc->cipher_status = | |
1954 | rt2x00_get_field32(word0, RXD_W0_CIPHER_ERROR); | |
1955 | } | |
1956 | ||
1957 | if (rxdesc->cipher != CIPHER_NONE) { | |
1958 | _rt2x00_desc_read(entry_priv->desc, 2, &rxdesc->iv); | |
1959 | _rt2x00_desc_read(entry_priv->desc, 3, &rxdesc->eiv); | |
1960 | _rt2x00_desc_read(entry_priv->desc, 4, &rxdesc->icv); | |
1961 | ||
1962 | /* | |
1963 | * Hardware has stripped IV/EIV data from 802.11 frame during | |
1964 | * decryption. It has provided the data seperately but rt2x00lib | |
1965 | * should decide if it should be reinserted. | |
1966 | */ | |
1967 | rxdesc->flags |= RX_FLAG_IV_STRIPPED; | |
1968 | ||
1969 | /* | |
1970 | * FIXME: Legacy driver indicates that the frame does | |
1971 | * contain the Michael Mic. Unfortunately, in rt2x00 | |
1972 | * the MIC seems to be missing completely... | |
1973 | */ | |
1974 | rxdesc->flags |= RX_FLAG_MMIC_STRIPPED; | |
1975 | ||
1976 | if (rxdesc->cipher_status == RX_CRYPTO_SUCCESS) | |
1977 | rxdesc->flags |= RX_FLAG_DECRYPTED; | |
1978 | else if (rxdesc->cipher_status == RX_CRYPTO_FAIL_MIC) | |
1979 | rxdesc->flags |= RX_FLAG_MMIC_ERROR; | |
1980 | } | |
1981 | ||
95ea3627 ID |
1982 | /* |
1983 | * Obtain the status about this packet. | |
89993890 ID |
1984 | * When frame was received with an OFDM bitrate, |
1985 | * the signal is the PLCP value. If it was received with | |
1986 | * a CCK bitrate the signal is the rate in 100kbit/s. | |
95ea3627 | 1987 | */ |
181d6902 | 1988 | rxdesc->signal = rt2x00_get_field32(word1, RXD_W1_SIGNAL); |
61e754f4 | 1989 | rxdesc->rssi = rt61pci_agc_to_rssi(rt2x00dev, word1); |
181d6902 | 1990 | rxdesc->size = rt2x00_get_field32(word0, RXD_W0_DATABYTE_COUNT); |
19d30e02 | 1991 | |
19d30e02 ID |
1992 | if (rt2x00_get_field32(word0, RXD_W0_OFDM)) |
1993 | rxdesc->dev_flags |= RXDONE_SIGNAL_PLCP; | |
6c6aa3c0 ID |
1994 | else |
1995 | rxdesc->dev_flags |= RXDONE_SIGNAL_BITRATE; | |
19d30e02 ID |
1996 | if (rt2x00_get_field32(word0, RXD_W0_MY_BSS)) |
1997 | rxdesc->dev_flags |= RXDONE_MY_BSS; | |
95ea3627 ID |
1998 | } |
1999 | ||
2000 | /* | |
2001 | * Interrupt functions. | |
2002 | */ | |
2003 | static void rt61pci_txdone(struct rt2x00_dev *rt2x00dev) | |
2004 | { | |
181d6902 ID |
2005 | struct data_queue *queue; |
2006 | struct queue_entry *entry; | |
2007 | struct queue_entry *entry_done; | |
b8be63ff | 2008 | struct queue_entry_priv_pci *entry_priv; |
181d6902 | 2009 | struct txdone_entry_desc txdesc; |
95ea3627 ID |
2010 | u32 word; |
2011 | u32 reg; | |
2012 | u32 old_reg; | |
2013 | int type; | |
2014 | int index; | |
95ea3627 ID |
2015 | |
2016 | /* | |
2017 | * During each loop we will compare the freshly read | |
2018 | * STA_CSR4 register value with the value read from | |
2019 | * the previous loop. If the 2 values are equal then | |
2020 | * we should stop processing because the chance it | |
2021 | * quite big that the device has been unplugged and | |
2022 | * we risk going into an endless loop. | |
2023 | */ | |
2024 | old_reg = 0; | |
2025 | ||
2026 | while (1) { | |
2027 | rt2x00pci_register_read(rt2x00dev, STA_CSR4, ®); | |
2028 | if (!rt2x00_get_field32(reg, STA_CSR4_VALID)) | |
2029 | break; | |
2030 | ||
2031 | if (old_reg == reg) | |
2032 | break; | |
2033 | old_reg = reg; | |
2034 | ||
2035 | /* | |
2036 | * Skip this entry when it contains an invalid | |
181d6902 | 2037 | * queue identication number. |
95ea3627 ID |
2038 | */ |
2039 | type = rt2x00_get_field32(reg, STA_CSR4_PID_TYPE); | |
181d6902 ID |
2040 | queue = rt2x00queue_get_queue(rt2x00dev, type); |
2041 | if (unlikely(!queue)) | |
95ea3627 ID |
2042 | continue; |
2043 | ||
2044 | /* | |
2045 | * Skip this entry when it contains an invalid | |
2046 | * index number. | |
2047 | */ | |
2048 | index = rt2x00_get_field32(reg, STA_CSR4_PID_SUBTYPE); | |
181d6902 | 2049 | if (unlikely(index >= queue->limit)) |
95ea3627 ID |
2050 | continue; |
2051 | ||
181d6902 | 2052 | entry = &queue->entries[index]; |
b8be63ff ID |
2053 | entry_priv = entry->priv_data; |
2054 | rt2x00_desc_read(entry_priv->desc, 0, &word); | |
95ea3627 ID |
2055 | |
2056 | if (rt2x00_get_field32(word, TXD_W0_OWNER_NIC) || | |
2057 | !rt2x00_get_field32(word, TXD_W0_VALID)) | |
2058 | return; | |
2059 | ||
181d6902 | 2060 | entry_done = rt2x00queue_get_entry(queue, Q_INDEX_DONE); |
62bc060b | 2061 | while (entry != entry_done) { |
181d6902 ID |
2062 | /* Catch up. |
2063 | * Just report any entries we missed as failed. | |
2064 | */ | |
62bc060b | 2065 | WARNING(rt2x00dev, |
181d6902 ID |
2066 | "TX status report missed for entry %d\n", |
2067 | entry_done->entry_idx); | |
2068 | ||
fb55f4d1 ID |
2069 | txdesc.flags = 0; |
2070 | __set_bit(TXDONE_UNKNOWN, &txdesc.flags); | |
181d6902 ID |
2071 | txdesc.retry = 0; |
2072 | ||
d74f5ba4 | 2073 | rt2x00lib_txdone(entry_done, &txdesc); |
181d6902 | 2074 | entry_done = rt2x00queue_get_entry(queue, Q_INDEX_DONE); |
62bc060b MN |
2075 | } |
2076 | ||
95ea3627 ID |
2077 | /* |
2078 | * Obtain the status about this packet. | |
2079 | */ | |
fb55f4d1 ID |
2080 | txdesc.flags = 0; |
2081 | switch (rt2x00_get_field32(reg, STA_CSR4_TX_RESULT)) { | |
2082 | case 0: /* Success, maybe with retry */ | |
2083 | __set_bit(TXDONE_SUCCESS, &txdesc.flags); | |
2084 | break; | |
2085 | case 6: /* Failure, excessive retries */ | |
2086 | __set_bit(TXDONE_EXCESSIVE_RETRY, &txdesc.flags); | |
2087 | /* Don't break, this is a failed frame! */ | |
2088 | default: /* Failure */ | |
2089 | __set_bit(TXDONE_FAILURE, &txdesc.flags); | |
2090 | } | |
181d6902 | 2091 | txdesc.retry = rt2x00_get_field32(reg, STA_CSR4_RETRY_COUNT); |
95ea3627 | 2092 | |
d74f5ba4 | 2093 | rt2x00lib_txdone(entry, &txdesc); |
95ea3627 ID |
2094 | } |
2095 | } | |
2096 | ||
2097 | static irqreturn_t rt61pci_interrupt(int irq, void *dev_instance) | |
2098 | { | |
2099 | struct rt2x00_dev *rt2x00dev = dev_instance; | |
2100 | u32 reg_mcu; | |
2101 | u32 reg; | |
2102 | ||
2103 | /* | |
2104 | * Get the interrupt sources & saved to local variable. | |
2105 | * Write register value back to clear pending interrupts. | |
2106 | */ | |
2107 | rt2x00pci_register_read(rt2x00dev, MCU_INT_SOURCE_CSR, ®_mcu); | |
2108 | rt2x00pci_register_write(rt2x00dev, MCU_INT_SOURCE_CSR, reg_mcu); | |
2109 | ||
2110 | rt2x00pci_register_read(rt2x00dev, INT_SOURCE_CSR, ®); | |
2111 | rt2x00pci_register_write(rt2x00dev, INT_SOURCE_CSR, reg); | |
2112 | ||
2113 | if (!reg && !reg_mcu) | |
2114 | return IRQ_NONE; | |
2115 | ||
0262ab0d | 2116 | if (!test_bit(DEVICE_STATE_ENABLED_RADIO, &rt2x00dev->flags)) |
95ea3627 ID |
2117 | return IRQ_HANDLED; |
2118 | ||
2119 | /* | |
2120 | * Handle interrupts, walk through all bits | |
2121 | * and run the tasks, the bits are checked in order of | |
2122 | * priority. | |
2123 | */ | |
2124 | ||
2125 | /* | |
2126 | * 1 - Rx ring done interrupt. | |
2127 | */ | |
2128 | if (rt2x00_get_field32(reg, INT_SOURCE_CSR_RXDONE)) | |
2129 | rt2x00pci_rxdone(rt2x00dev); | |
2130 | ||
2131 | /* | |
2132 | * 2 - Tx ring done interrupt. | |
2133 | */ | |
2134 | if (rt2x00_get_field32(reg, INT_SOURCE_CSR_TXDONE)) | |
2135 | rt61pci_txdone(rt2x00dev); | |
2136 | ||
2137 | /* | |
2138 | * 3 - Handle MCU command done. | |
2139 | */ | |
2140 | if (reg_mcu) | |
2141 | rt2x00pci_register_write(rt2x00dev, | |
2142 | M2H_CMD_DONE_CSR, 0xffffffff); | |
2143 | ||
2144 | return IRQ_HANDLED; | |
2145 | } | |
2146 | ||
2147 | /* | |
2148 | * Device probe functions. | |
2149 | */ | |
2150 | static int rt61pci_validate_eeprom(struct rt2x00_dev *rt2x00dev) | |
2151 | { | |
2152 | struct eeprom_93cx6 eeprom; | |
2153 | u32 reg; | |
2154 | u16 word; | |
2155 | u8 *mac; | |
2156 | s8 value; | |
2157 | ||
2158 | rt2x00pci_register_read(rt2x00dev, E2PROM_CSR, ®); | |
2159 | ||
2160 | eeprom.data = rt2x00dev; | |
2161 | eeprom.register_read = rt61pci_eepromregister_read; | |
2162 | eeprom.register_write = rt61pci_eepromregister_write; | |
2163 | eeprom.width = rt2x00_get_field32(reg, E2PROM_CSR_TYPE_93C46) ? | |
2164 | PCI_EEPROM_WIDTH_93C46 : PCI_EEPROM_WIDTH_93C66; | |
2165 | eeprom.reg_data_in = 0; | |
2166 | eeprom.reg_data_out = 0; | |
2167 | eeprom.reg_data_clock = 0; | |
2168 | eeprom.reg_chip_select = 0; | |
2169 | ||
2170 | eeprom_93cx6_multiread(&eeprom, EEPROM_BASE, rt2x00dev->eeprom, | |
2171 | EEPROM_SIZE / sizeof(u16)); | |
2172 | ||
2173 | /* | |
2174 | * Start validation of the data that has been read. | |
2175 | */ | |
2176 | mac = rt2x00_eeprom_addr(rt2x00dev, EEPROM_MAC_ADDR_0); | |
2177 | if (!is_valid_ether_addr(mac)) { | |
0795af57 JP |
2178 | DECLARE_MAC_BUF(macbuf); |
2179 | ||
95ea3627 | 2180 | random_ether_addr(mac); |
0795af57 | 2181 | EEPROM(rt2x00dev, "MAC: %s\n", print_mac(macbuf, mac)); |
95ea3627 ID |
2182 | } |
2183 | ||
2184 | rt2x00_eeprom_read(rt2x00dev, EEPROM_ANTENNA, &word); | |
2185 | if (word == 0xffff) { | |
2186 | rt2x00_set_field16(&word, EEPROM_ANTENNA_NUM, 2); | |
362f3b6b ID |
2187 | rt2x00_set_field16(&word, EEPROM_ANTENNA_TX_DEFAULT, |
2188 | ANTENNA_B); | |
2189 | rt2x00_set_field16(&word, EEPROM_ANTENNA_RX_DEFAULT, | |
2190 | ANTENNA_B); | |
95ea3627 ID |
2191 | rt2x00_set_field16(&word, EEPROM_ANTENNA_FRAME_TYPE, 0); |
2192 | rt2x00_set_field16(&word, EEPROM_ANTENNA_DYN_TXAGC, 0); | |
2193 | rt2x00_set_field16(&word, EEPROM_ANTENNA_HARDWARE_RADIO, 0); | |
2194 | rt2x00_set_field16(&word, EEPROM_ANTENNA_RF_TYPE, RF5225); | |
2195 | rt2x00_eeprom_write(rt2x00dev, EEPROM_ANTENNA, word); | |
2196 | EEPROM(rt2x00dev, "Antenna: 0x%04x\n", word); | |
2197 | } | |
2198 | ||
2199 | rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC, &word); | |
2200 | if (word == 0xffff) { | |
2201 | rt2x00_set_field16(&word, EEPROM_NIC_ENABLE_DIVERSITY, 0); | |
2202 | rt2x00_set_field16(&word, EEPROM_NIC_TX_DIVERSITY, 0); | |
2203 | rt2x00_set_field16(&word, EEPROM_NIC_TX_RX_FIXED, 0); | |
2204 | rt2x00_set_field16(&word, EEPROM_NIC_EXTERNAL_LNA_BG, 0); | |
2205 | rt2x00_set_field16(&word, EEPROM_NIC_CARDBUS_ACCEL, 0); | |
2206 | rt2x00_set_field16(&word, EEPROM_NIC_EXTERNAL_LNA_A, 0); | |
2207 | rt2x00_eeprom_write(rt2x00dev, EEPROM_NIC, word); | |
2208 | EEPROM(rt2x00dev, "NIC: 0x%04x\n", word); | |
2209 | } | |
2210 | ||
2211 | rt2x00_eeprom_read(rt2x00dev, EEPROM_LED, &word); | |
2212 | if (word == 0xffff) { | |
2213 | rt2x00_set_field16(&word, EEPROM_LED_LED_MODE, | |
2214 | LED_MODE_DEFAULT); | |
2215 | rt2x00_eeprom_write(rt2x00dev, EEPROM_LED, word); | |
2216 | EEPROM(rt2x00dev, "Led: 0x%04x\n", word); | |
2217 | } | |
2218 | ||
2219 | rt2x00_eeprom_read(rt2x00dev, EEPROM_FREQ, &word); | |
2220 | if (word == 0xffff) { | |
2221 | rt2x00_set_field16(&word, EEPROM_FREQ_OFFSET, 0); | |
2222 | rt2x00_set_field16(&word, EEPROM_FREQ_SEQ, 0); | |
2223 | rt2x00_eeprom_write(rt2x00dev, EEPROM_FREQ, word); | |
2224 | EEPROM(rt2x00dev, "Freq: 0x%04x\n", word); | |
2225 | } | |
2226 | ||
2227 | rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_OFFSET_BG, &word); | |
2228 | if (word == 0xffff) { | |
2229 | rt2x00_set_field16(&word, EEPROM_RSSI_OFFSET_BG_1, 0); | |
2230 | rt2x00_set_field16(&word, EEPROM_RSSI_OFFSET_BG_2, 0); | |
2231 | rt2x00_eeprom_write(rt2x00dev, EEPROM_RSSI_OFFSET_BG, word); | |
2232 | EEPROM(rt2x00dev, "RSSI OFFSET BG: 0x%04x\n", word); | |
2233 | } else { | |
2234 | value = rt2x00_get_field16(word, EEPROM_RSSI_OFFSET_BG_1); | |
2235 | if (value < -10 || value > 10) | |
2236 | rt2x00_set_field16(&word, EEPROM_RSSI_OFFSET_BG_1, 0); | |
2237 | value = rt2x00_get_field16(word, EEPROM_RSSI_OFFSET_BG_2); | |
2238 | if (value < -10 || value > 10) | |
2239 | rt2x00_set_field16(&word, EEPROM_RSSI_OFFSET_BG_2, 0); | |
2240 | rt2x00_eeprom_write(rt2x00dev, EEPROM_RSSI_OFFSET_BG, word); | |
2241 | } | |
2242 | ||
2243 | rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_OFFSET_A, &word); | |
2244 | if (word == 0xffff) { | |
2245 | rt2x00_set_field16(&word, EEPROM_RSSI_OFFSET_A_1, 0); | |
2246 | rt2x00_set_field16(&word, EEPROM_RSSI_OFFSET_A_2, 0); | |
2247 | rt2x00_eeprom_write(rt2x00dev, EEPROM_RSSI_OFFSET_A, word); | |
417f412f | 2248 | EEPROM(rt2x00dev, "RSSI OFFSET A: 0x%04x\n", word); |
95ea3627 ID |
2249 | } else { |
2250 | value = rt2x00_get_field16(word, EEPROM_RSSI_OFFSET_A_1); | |
2251 | if (value < -10 || value > 10) | |
2252 | rt2x00_set_field16(&word, EEPROM_RSSI_OFFSET_A_1, 0); | |
2253 | value = rt2x00_get_field16(word, EEPROM_RSSI_OFFSET_A_2); | |
2254 | if (value < -10 || value > 10) | |
2255 | rt2x00_set_field16(&word, EEPROM_RSSI_OFFSET_A_2, 0); | |
2256 | rt2x00_eeprom_write(rt2x00dev, EEPROM_RSSI_OFFSET_A, word); | |
2257 | } | |
2258 | ||
2259 | return 0; | |
2260 | } | |
2261 | ||
2262 | static int rt61pci_init_eeprom(struct rt2x00_dev *rt2x00dev) | |
2263 | { | |
2264 | u32 reg; | |
2265 | u16 value; | |
2266 | u16 eeprom; | |
2267 | u16 device; | |
2268 | ||
2269 | /* | |
2270 | * Read EEPROM word for configuration. | |
2271 | */ | |
2272 | rt2x00_eeprom_read(rt2x00dev, EEPROM_ANTENNA, &eeprom); | |
2273 | ||
2274 | /* | |
2275 | * Identify RF chipset. | |
2276 | * To determine the RT chip we have to read the | |
2277 | * PCI header of the device. | |
2278 | */ | |
14a3bf89 | 2279 | pci_read_config_word(to_pci_dev(rt2x00dev->dev), |
95ea3627 ID |
2280 | PCI_CONFIG_HEADER_DEVICE, &device); |
2281 | value = rt2x00_get_field16(eeprom, EEPROM_ANTENNA_RF_TYPE); | |
2282 | rt2x00pci_register_read(rt2x00dev, MAC_CSR0, ®); | |
2283 | rt2x00_set_chip(rt2x00dev, device, value, reg); | |
2284 | ||
2285 | if (!rt2x00_rf(&rt2x00dev->chip, RF5225) && | |
2286 | !rt2x00_rf(&rt2x00dev->chip, RF5325) && | |
2287 | !rt2x00_rf(&rt2x00dev->chip, RF2527) && | |
2288 | !rt2x00_rf(&rt2x00dev->chip, RF2529)) { | |
2289 | ERROR(rt2x00dev, "Invalid RF chipset detected.\n"); | |
2290 | return -ENODEV; | |
2291 | } | |
2292 | ||
e4cd2ff8 ID |
2293 | /* |
2294 | * Determine number of antenna's. | |
2295 | */ | |
2296 | if (rt2x00_get_field16(eeprom, EEPROM_ANTENNA_NUM) == 2) | |
2297 | __set_bit(CONFIG_DOUBLE_ANTENNA, &rt2x00dev->flags); | |
2298 | ||
95ea3627 ID |
2299 | /* |
2300 | * Identify default antenna configuration. | |
2301 | */ | |
addc81bd | 2302 | rt2x00dev->default_ant.tx = |
95ea3627 | 2303 | rt2x00_get_field16(eeprom, EEPROM_ANTENNA_TX_DEFAULT); |
addc81bd | 2304 | rt2x00dev->default_ant.rx = |
95ea3627 ID |
2305 | rt2x00_get_field16(eeprom, EEPROM_ANTENNA_RX_DEFAULT); |
2306 | ||
2307 | /* | |
2308 | * Read the Frame type. | |
2309 | */ | |
2310 | if (rt2x00_get_field16(eeprom, EEPROM_ANTENNA_FRAME_TYPE)) | |
2311 | __set_bit(CONFIG_FRAME_TYPE, &rt2x00dev->flags); | |
2312 | ||
95ea3627 ID |
2313 | /* |
2314 | * Detect if this device has an hardware controlled radio. | |
2315 | */ | |
58169529 | 2316 | #ifdef CONFIG_RT2X00_LIB_RFKILL |
95ea3627 | 2317 | if (rt2x00_get_field16(eeprom, EEPROM_ANTENNA_HARDWARE_RADIO)) |
066cb637 | 2318 | __set_bit(CONFIG_SUPPORT_HW_BUTTON, &rt2x00dev->flags); |
58169529 | 2319 | #endif /* CONFIG_RT2X00_LIB_RFKILL */ |
95ea3627 ID |
2320 | |
2321 | /* | |
2322 | * Read frequency offset and RF programming sequence. | |
2323 | */ | |
2324 | rt2x00_eeprom_read(rt2x00dev, EEPROM_FREQ, &eeprom); | |
2325 | if (rt2x00_get_field16(eeprom, EEPROM_FREQ_SEQ)) | |
2326 | __set_bit(CONFIG_RF_SEQUENCE, &rt2x00dev->flags); | |
2327 | ||
2328 | rt2x00dev->freq_offset = rt2x00_get_field16(eeprom, EEPROM_FREQ_OFFSET); | |
2329 | ||
2330 | /* | |
2331 | * Read external LNA informations. | |
2332 | */ | |
2333 | rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC, &eeprom); | |
2334 | ||
2335 | if (rt2x00_get_field16(eeprom, EEPROM_NIC_EXTERNAL_LNA_A)) | |
2336 | __set_bit(CONFIG_EXTERNAL_LNA_A, &rt2x00dev->flags); | |
2337 | if (rt2x00_get_field16(eeprom, EEPROM_NIC_EXTERNAL_LNA_BG)) | |
2338 | __set_bit(CONFIG_EXTERNAL_LNA_BG, &rt2x00dev->flags); | |
2339 | ||
e4cd2ff8 ID |
2340 | /* |
2341 | * When working with a RF2529 chip without double antenna | |
2342 | * the antenna settings should be gathered from the NIC | |
2343 | * eeprom word. | |
2344 | */ | |
2345 | if (rt2x00_rf(&rt2x00dev->chip, RF2529) && | |
2346 | !test_bit(CONFIG_DOUBLE_ANTENNA, &rt2x00dev->flags)) { | |
2347 | switch (rt2x00_get_field16(eeprom, EEPROM_NIC_TX_RX_FIXED)) { | |
2348 | case 0: | |
2349 | rt2x00dev->default_ant.tx = ANTENNA_B; | |
2350 | rt2x00dev->default_ant.rx = ANTENNA_A; | |
2351 | break; | |
2352 | case 1: | |
2353 | rt2x00dev->default_ant.tx = ANTENNA_B; | |
2354 | rt2x00dev->default_ant.rx = ANTENNA_B; | |
2355 | break; | |
2356 | case 2: | |
2357 | rt2x00dev->default_ant.tx = ANTENNA_A; | |
2358 | rt2x00dev->default_ant.rx = ANTENNA_A; | |
2359 | break; | |
2360 | case 3: | |
2361 | rt2x00dev->default_ant.tx = ANTENNA_A; | |
2362 | rt2x00dev->default_ant.rx = ANTENNA_B; | |
2363 | break; | |
2364 | } | |
2365 | ||
2366 | if (rt2x00_get_field16(eeprom, EEPROM_NIC_TX_DIVERSITY)) | |
2367 | rt2x00dev->default_ant.tx = ANTENNA_SW_DIVERSITY; | |
2368 | if (rt2x00_get_field16(eeprom, EEPROM_NIC_ENABLE_DIVERSITY)) | |
2369 | rt2x00dev->default_ant.rx = ANTENNA_SW_DIVERSITY; | |
2370 | } | |
2371 | ||
95ea3627 ID |
2372 | /* |
2373 | * Store led settings, for correct led behaviour. | |
2374 | * If the eeprom value is invalid, | |
2375 | * switch to default led mode. | |
2376 | */ | |
771fd565 | 2377 | #ifdef CONFIG_RT2X00_LIB_LEDS |
95ea3627 | 2378 | rt2x00_eeprom_read(rt2x00dev, EEPROM_LED, &eeprom); |
a9450b70 ID |
2379 | value = rt2x00_get_field16(eeprom, EEPROM_LED_LED_MODE); |
2380 | ||
475433be ID |
2381 | rt61pci_init_led(rt2x00dev, &rt2x00dev->led_radio, LED_TYPE_RADIO); |
2382 | rt61pci_init_led(rt2x00dev, &rt2x00dev->led_assoc, LED_TYPE_ASSOC); | |
2383 | if (value == LED_MODE_SIGNAL_STRENGTH) | |
2384 | rt61pci_init_led(rt2x00dev, &rt2x00dev->led_qual, | |
2385 | LED_TYPE_QUALITY); | |
95ea3627 | 2386 | |
a9450b70 ID |
2387 | rt2x00_set_field16(&rt2x00dev->led_mcu_reg, MCU_LEDCS_LED_MODE, value); |
2388 | rt2x00_set_field16(&rt2x00dev->led_mcu_reg, MCU_LEDCS_POLARITY_GPIO_0, | |
95ea3627 ID |
2389 | rt2x00_get_field16(eeprom, |
2390 | EEPROM_LED_POLARITY_GPIO_0)); | |
a9450b70 | 2391 | rt2x00_set_field16(&rt2x00dev->led_mcu_reg, MCU_LEDCS_POLARITY_GPIO_1, |
95ea3627 ID |
2392 | rt2x00_get_field16(eeprom, |
2393 | EEPROM_LED_POLARITY_GPIO_1)); | |
a9450b70 | 2394 | rt2x00_set_field16(&rt2x00dev->led_mcu_reg, MCU_LEDCS_POLARITY_GPIO_2, |
95ea3627 ID |
2395 | rt2x00_get_field16(eeprom, |
2396 | EEPROM_LED_POLARITY_GPIO_2)); | |
a9450b70 | 2397 | rt2x00_set_field16(&rt2x00dev->led_mcu_reg, MCU_LEDCS_POLARITY_GPIO_3, |
95ea3627 ID |
2398 | rt2x00_get_field16(eeprom, |
2399 | EEPROM_LED_POLARITY_GPIO_3)); | |
a9450b70 | 2400 | rt2x00_set_field16(&rt2x00dev->led_mcu_reg, MCU_LEDCS_POLARITY_GPIO_4, |
95ea3627 ID |
2401 | rt2x00_get_field16(eeprom, |
2402 | EEPROM_LED_POLARITY_GPIO_4)); | |
a9450b70 | 2403 | rt2x00_set_field16(&rt2x00dev->led_mcu_reg, MCU_LEDCS_POLARITY_ACT, |
95ea3627 | 2404 | rt2x00_get_field16(eeprom, EEPROM_LED_POLARITY_ACT)); |
a9450b70 | 2405 | rt2x00_set_field16(&rt2x00dev->led_mcu_reg, MCU_LEDCS_POLARITY_READY_BG, |
95ea3627 ID |
2406 | rt2x00_get_field16(eeprom, |
2407 | EEPROM_LED_POLARITY_RDY_G)); | |
a9450b70 | 2408 | rt2x00_set_field16(&rt2x00dev->led_mcu_reg, MCU_LEDCS_POLARITY_READY_A, |
95ea3627 ID |
2409 | rt2x00_get_field16(eeprom, |
2410 | EEPROM_LED_POLARITY_RDY_A)); | |
771fd565 | 2411 | #endif /* CONFIG_RT2X00_LIB_LEDS */ |
95ea3627 ID |
2412 | |
2413 | return 0; | |
2414 | } | |
2415 | ||
2416 | /* | |
2417 | * RF value list for RF5225 & RF5325 | |
2418 | * Supports: 2.4 GHz & 5.2 GHz, rf_sequence disabled | |
2419 | */ | |
2420 | static const struct rf_channel rf_vals_noseq[] = { | |
2421 | { 1, 0x00002ccc, 0x00004786, 0x00068455, 0x000ffa0b }, | |
2422 | { 2, 0x00002ccc, 0x00004786, 0x00068455, 0x000ffa1f }, | |
2423 | { 3, 0x00002ccc, 0x0000478a, 0x00068455, 0x000ffa0b }, | |
2424 | { 4, 0x00002ccc, 0x0000478a, 0x00068455, 0x000ffa1f }, | |
2425 | { 5, 0x00002ccc, 0x0000478e, 0x00068455, 0x000ffa0b }, | |
2426 | { 6, 0x00002ccc, 0x0000478e, 0x00068455, 0x000ffa1f }, | |
2427 | { 7, 0x00002ccc, 0x00004792, 0x00068455, 0x000ffa0b }, | |
2428 | { 8, 0x00002ccc, 0x00004792, 0x00068455, 0x000ffa1f }, | |
2429 | { 9, 0x00002ccc, 0x00004796, 0x00068455, 0x000ffa0b }, | |
2430 | { 10, 0x00002ccc, 0x00004796, 0x00068455, 0x000ffa1f }, | |
2431 | { 11, 0x00002ccc, 0x0000479a, 0x00068455, 0x000ffa0b }, | |
2432 | { 12, 0x00002ccc, 0x0000479a, 0x00068455, 0x000ffa1f }, | |
2433 | { 13, 0x00002ccc, 0x0000479e, 0x00068455, 0x000ffa0b }, | |
2434 | { 14, 0x00002ccc, 0x000047a2, 0x00068455, 0x000ffa13 }, | |
2435 | ||
2436 | /* 802.11 UNI / HyperLan 2 */ | |
2437 | { 36, 0x00002ccc, 0x0000499a, 0x0009be55, 0x000ffa23 }, | |
2438 | { 40, 0x00002ccc, 0x000049a2, 0x0009be55, 0x000ffa03 }, | |
2439 | { 44, 0x00002ccc, 0x000049a6, 0x0009be55, 0x000ffa0b }, | |
2440 | { 48, 0x00002ccc, 0x000049aa, 0x0009be55, 0x000ffa13 }, | |
2441 | { 52, 0x00002ccc, 0x000049ae, 0x0009ae55, 0x000ffa1b }, | |
2442 | { 56, 0x00002ccc, 0x000049b2, 0x0009ae55, 0x000ffa23 }, | |
2443 | { 60, 0x00002ccc, 0x000049ba, 0x0009ae55, 0x000ffa03 }, | |
2444 | { 64, 0x00002ccc, 0x000049be, 0x0009ae55, 0x000ffa0b }, | |
2445 | ||
2446 | /* 802.11 HyperLan 2 */ | |
2447 | { 100, 0x00002ccc, 0x00004a2a, 0x000bae55, 0x000ffa03 }, | |
2448 | { 104, 0x00002ccc, 0x00004a2e, 0x000bae55, 0x000ffa0b }, | |
2449 | { 108, 0x00002ccc, 0x00004a32, 0x000bae55, 0x000ffa13 }, | |
2450 | { 112, 0x00002ccc, 0x00004a36, 0x000bae55, 0x000ffa1b }, | |
2451 | { 116, 0x00002ccc, 0x00004a3a, 0x000bbe55, 0x000ffa23 }, | |
2452 | { 120, 0x00002ccc, 0x00004a82, 0x000bbe55, 0x000ffa03 }, | |
2453 | { 124, 0x00002ccc, 0x00004a86, 0x000bbe55, 0x000ffa0b }, | |
2454 | { 128, 0x00002ccc, 0x00004a8a, 0x000bbe55, 0x000ffa13 }, | |
2455 | { 132, 0x00002ccc, 0x00004a8e, 0x000bbe55, 0x000ffa1b }, | |
2456 | { 136, 0x00002ccc, 0x00004a92, 0x000bbe55, 0x000ffa23 }, | |
2457 | ||
2458 | /* 802.11 UNII */ | |
2459 | { 140, 0x00002ccc, 0x00004a9a, 0x000bbe55, 0x000ffa03 }, | |
2460 | { 149, 0x00002ccc, 0x00004aa2, 0x000bbe55, 0x000ffa1f }, | |
2461 | { 153, 0x00002ccc, 0x00004aa6, 0x000bbe55, 0x000ffa27 }, | |
2462 | { 157, 0x00002ccc, 0x00004aae, 0x000bbe55, 0x000ffa07 }, | |
2463 | { 161, 0x00002ccc, 0x00004ab2, 0x000bbe55, 0x000ffa0f }, | |
2464 | { 165, 0x00002ccc, 0x00004ab6, 0x000bbe55, 0x000ffa17 }, | |
2465 | ||
2466 | /* MMAC(Japan)J52 ch 34,38,42,46 */ | |
2467 | { 34, 0x00002ccc, 0x0000499a, 0x0009be55, 0x000ffa0b }, | |
2468 | { 38, 0x00002ccc, 0x0000499e, 0x0009be55, 0x000ffa13 }, | |
2469 | { 42, 0x00002ccc, 0x000049a2, 0x0009be55, 0x000ffa1b }, | |
2470 | { 46, 0x00002ccc, 0x000049a6, 0x0009be55, 0x000ffa23 }, | |
2471 | }; | |
2472 | ||
2473 | /* | |
2474 | * RF value list for RF5225 & RF5325 | |
2475 | * Supports: 2.4 GHz & 5.2 GHz, rf_sequence enabled | |
2476 | */ | |
2477 | static const struct rf_channel rf_vals_seq[] = { | |
2478 | { 1, 0x00002ccc, 0x00004786, 0x00068455, 0x000ffa0b }, | |
2479 | { 2, 0x00002ccc, 0x00004786, 0x00068455, 0x000ffa1f }, | |
2480 | { 3, 0x00002ccc, 0x0000478a, 0x00068455, 0x000ffa0b }, | |
2481 | { 4, 0x00002ccc, 0x0000478a, 0x00068455, 0x000ffa1f }, | |
2482 | { 5, 0x00002ccc, 0x0000478e, 0x00068455, 0x000ffa0b }, | |
2483 | { 6, 0x00002ccc, 0x0000478e, 0x00068455, 0x000ffa1f }, | |
2484 | { 7, 0x00002ccc, 0x00004792, 0x00068455, 0x000ffa0b }, | |
2485 | { 8, 0x00002ccc, 0x00004792, 0x00068455, 0x000ffa1f }, | |
2486 | { 9, 0x00002ccc, 0x00004796, 0x00068455, 0x000ffa0b }, | |
2487 | { 10, 0x00002ccc, 0x00004796, 0x00068455, 0x000ffa1f }, | |
2488 | { 11, 0x00002ccc, 0x0000479a, 0x00068455, 0x000ffa0b }, | |
2489 | { 12, 0x00002ccc, 0x0000479a, 0x00068455, 0x000ffa1f }, | |
2490 | { 13, 0x00002ccc, 0x0000479e, 0x00068455, 0x000ffa0b }, | |
2491 | { 14, 0x00002ccc, 0x000047a2, 0x00068455, 0x000ffa13 }, | |
2492 | ||
2493 | /* 802.11 UNI / HyperLan 2 */ | |
2494 | { 36, 0x00002cd4, 0x0004481a, 0x00098455, 0x000c0a03 }, | |
2495 | { 40, 0x00002cd0, 0x00044682, 0x00098455, 0x000c0a03 }, | |
2496 | { 44, 0x00002cd0, 0x00044686, 0x00098455, 0x000c0a1b }, | |
2497 | { 48, 0x00002cd0, 0x0004468e, 0x00098655, 0x000c0a0b }, | |
2498 | { 52, 0x00002cd0, 0x00044692, 0x00098855, 0x000c0a23 }, | |
2499 | { 56, 0x00002cd0, 0x0004469a, 0x00098c55, 0x000c0a13 }, | |
2500 | { 60, 0x00002cd0, 0x000446a2, 0x00098e55, 0x000c0a03 }, | |
2501 | { 64, 0x00002cd0, 0x000446a6, 0x00099255, 0x000c0a1b }, | |
2502 | ||
2503 | /* 802.11 HyperLan 2 */ | |
2504 | { 100, 0x00002cd4, 0x0004489a, 0x000b9855, 0x000c0a03 }, | |
2505 | { 104, 0x00002cd4, 0x000448a2, 0x000b9855, 0x000c0a03 }, | |
2506 | { 108, 0x00002cd4, 0x000448aa, 0x000b9855, 0x000c0a03 }, | |
2507 | { 112, 0x00002cd4, 0x000448b2, 0x000b9a55, 0x000c0a03 }, | |
2508 | { 116, 0x00002cd4, 0x000448ba, 0x000b9a55, 0x000c0a03 }, | |
2509 | { 120, 0x00002cd0, 0x00044702, 0x000b9a55, 0x000c0a03 }, | |
2510 | { 124, 0x00002cd0, 0x00044706, 0x000b9a55, 0x000c0a1b }, | |
2511 | { 128, 0x00002cd0, 0x0004470e, 0x000b9c55, 0x000c0a0b }, | |
2512 | { 132, 0x00002cd0, 0x00044712, 0x000b9c55, 0x000c0a23 }, | |
2513 | { 136, 0x00002cd0, 0x0004471a, 0x000b9e55, 0x000c0a13 }, | |
2514 | ||
2515 | /* 802.11 UNII */ | |
2516 | { 140, 0x00002cd0, 0x00044722, 0x000b9e55, 0x000c0a03 }, | |
2517 | { 149, 0x00002cd0, 0x0004472e, 0x000ba255, 0x000c0a1b }, | |
2518 | { 153, 0x00002cd0, 0x00044736, 0x000ba255, 0x000c0a0b }, | |
2519 | { 157, 0x00002cd4, 0x0004490a, 0x000ba255, 0x000c0a17 }, | |
2520 | { 161, 0x00002cd4, 0x00044912, 0x000ba255, 0x000c0a17 }, | |
2521 | { 165, 0x00002cd4, 0x0004491a, 0x000ba255, 0x000c0a17 }, | |
2522 | ||
2523 | /* MMAC(Japan)J52 ch 34,38,42,46 */ | |
2524 | { 34, 0x00002ccc, 0x0000499a, 0x0009be55, 0x000c0a0b }, | |
2525 | { 38, 0x00002ccc, 0x0000499e, 0x0009be55, 0x000c0a13 }, | |
2526 | { 42, 0x00002ccc, 0x000049a2, 0x0009be55, 0x000c0a1b }, | |
2527 | { 46, 0x00002ccc, 0x000049a6, 0x0009be55, 0x000c0a23 }, | |
2528 | }; | |
2529 | ||
8c5e7a5f | 2530 | static int rt61pci_probe_hw_mode(struct rt2x00_dev *rt2x00dev) |
95ea3627 ID |
2531 | { |
2532 | struct hw_mode_spec *spec = &rt2x00dev->spec; | |
8c5e7a5f ID |
2533 | struct channel_info *info; |
2534 | char *tx_power; | |
95ea3627 ID |
2535 | unsigned int i; |
2536 | ||
2537 | /* | |
2538 | * Initialize all hw fields. | |
2539 | */ | |
2540 | rt2x00dev->hw->flags = | |
566bfe5a BR |
2541 | IEEE80211_HW_HOST_BROADCAST_PS_BUFFERING | |
2542 | IEEE80211_HW_SIGNAL_DBM; | |
95ea3627 | 2543 | rt2x00dev->hw->extra_tx_headroom = 0; |
95ea3627 | 2544 | |
14a3bf89 | 2545 | SET_IEEE80211_DEV(rt2x00dev->hw, rt2x00dev->dev); |
95ea3627 ID |
2546 | SET_IEEE80211_PERM_ADDR(rt2x00dev->hw, |
2547 | rt2x00_eeprom_addr(rt2x00dev, | |
2548 | EEPROM_MAC_ADDR_0)); | |
2549 | ||
95ea3627 ID |
2550 | /* |
2551 | * Initialize hw_mode information. | |
2552 | */ | |
31562e80 ID |
2553 | spec->supported_bands = SUPPORT_BAND_2GHZ; |
2554 | spec->supported_rates = SUPPORT_RATE_CCK | SUPPORT_RATE_OFDM; | |
95ea3627 ID |
2555 | |
2556 | if (!test_bit(CONFIG_RF_SEQUENCE, &rt2x00dev->flags)) { | |
2557 | spec->num_channels = 14; | |
2558 | spec->channels = rf_vals_noseq; | |
2559 | } else { | |
2560 | spec->num_channels = 14; | |
2561 | spec->channels = rf_vals_seq; | |
2562 | } | |
2563 | ||
2564 | if (rt2x00_rf(&rt2x00dev->chip, RF5225) || | |
2565 | rt2x00_rf(&rt2x00dev->chip, RF5325)) { | |
31562e80 | 2566 | spec->supported_bands |= SUPPORT_BAND_5GHZ; |
95ea3627 | 2567 | spec->num_channels = ARRAY_SIZE(rf_vals_seq); |
8c5e7a5f ID |
2568 | } |
2569 | ||
2570 | /* | |
2571 | * Create channel information array | |
2572 | */ | |
2573 | info = kzalloc(spec->num_channels * sizeof(*info), GFP_KERNEL); | |
2574 | if (!info) | |
2575 | return -ENOMEM; | |
2576 | ||
2577 | spec->channels_info = info; | |
95ea3627 | 2578 | |
8c5e7a5f ID |
2579 | tx_power = rt2x00_eeprom_addr(rt2x00dev, EEPROM_TXPOWER_G_START); |
2580 | for (i = 0; i < 14; i++) | |
2581 | info[i].tx_power1 = TXPOWER_FROM_DEV(tx_power[i]); | |
95ea3627 | 2582 | |
8c5e7a5f ID |
2583 | if (spec->num_channels > 14) { |
2584 | tx_power = rt2x00_eeprom_addr(rt2x00dev, EEPROM_TXPOWER_A_START); | |
2585 | for (i = 14; i < spec->num_channels; i++) | |
2586 | info[i].tx_power1 = TXPOWER_FROM_DEV(tx_power[i]); | |
95ea3627 | 2587 | } |
8c5e7a5f ID |
2588 | |
2589 | return 0; | |
95ea3627 ID |
2590 | } |
2591 | ||
2592 | static int rt61pci_probe_hw(struct rt2x00_dev *rt2x00dev) | |
2593 | { | |
2594 | int retval; | |
2595 | ||
2596 | /* | |
2597 | * Allocate eeprom data. | |
2598 | */ | |
2599 | retval = rt61pci_validate_eeprom(rt2x00dev); | |
2600 | if (retval) | |
2601 | return retval; | |
2602 | ||
2603 | retval = rt61pci_init_eeprom(rt2x00dev); | |
2604 | if (retval) | |
2605 | return retval; | |
2606 | ||
2607 | /* | |
2608 | * Initialize hw specifications. | |
2609 | */ | |
8c5e7a5f ID |
2610 | retval = rt61pci_probe_hw_mode(rt2x00dev); |
2611 | if (retval) | |
2612 | return retval; | |
95ea3627 ID |
2613 | |
2614 | /* | |
c4da0048 | 2615 | * This device requires firmware and DMA mapped skbs. |
95ea3627 | 2616 | */ |
066cb637 | 2617 | __set_bit(DRIVER_REQUIRE_FIRMWARE, &rt2x00dev->flags); |
c4da0048 | 2618 | __set_bit(DRIVER_REQUIRE_DMA, &rt2x00dev->flags); |
008c4482 ID |
2619 | if (!modparam_nohwcrypt) |
2620 | __set_bit(CONFIG_SUPPORT_HW_CRYPTO, &rt2x00dev->flags); | |
95ea3627 ID |
2621 | |
2622 | /* | |
2623 | * Set the rssi offset. | |
2624 | */ | |
2625 | rt2x00dev->rssi_offset = DEFAULT_RSSI_OFFSET; | |
2626 | ||
2627 | return 0; | |
2628 | } | |
2629 | ||
2630 | /* | |
2631 | * IEEE80211 stack callback functions. | |
2632 | */ | |
2633 | static int rt61pci_set_retry_limit(struct ieee80211_hw *hw, | |
2634 | u32 short_retry, u32 long_retry) | |
2635 | { | |
2636 | struct rt2x00_dev *rt2x00dev = hw->priv; | |
2637 | u32 reg; | |
2638 | ||
2639 | rt2x00pci_register_read(rt2x00dev, TXRX_CSR4, ®); | |
2640 | rt2x00_set_field32(®, TXRX_CSR4_LONG_RETRY_LIMIT, long_retry); | |
2641 | rt2x00_set_field32(®, TXRX_CSR4_SHORT_RETRY_LIMIT, short_retry); | |
2642 | rt2x00pci_register_write(rt2x00dev, TXRX_CSR4, reg); | |
2643 | ||
2644 | return 0; | |
2645 | } | |
2646 | ||
2af0a570 ID |
2647 | static int rt61pci_conf_tx(struct ieee80211_hw *hw, u16 queue_idx, |
2648 | const struct ieee80211_tx_queue_params *params) | |
2649 | { | |
2650 | struct rt2x00_dev *rt2x00dev = hw->priv; | |
2651 | struct data_queue *queue; | |
2652 | struct rt2x00_field32 field; | |
2653 | int retval; | |
2654 | u32 reg; | |
2655 | ||
2656 | /* | |
2657 | * First pass the configuration through rt2x00lib, that will | |
2658 | * update the queue settings and validate the input. After that | |
2659 | * we are free to update the registers based on the value | |
2660 | * in the queue parameter. | |
2661 | */ | |
2662 | retval = rt2x00mac_conf_tx(hw, queue_idx, params); | |
2663 | if (retval) | |
2664 | return retval; | |
2665 | ||
2666 | queue = rt2x00queue_get_queue(rt2x00dev, queue_idx); | |
2667 | ||
2668 | /* Update WMM TXOP register */ | |
2669 | if (queue_idx < 2) { | |
2670 | field.bit_offset = queue_idx * 16; | |
2671 | field.bit_mask = 0xffff << field.bit_offset; | |
2672 | ||
2673 | rt2x00pci_register_read(rt2x00dev, AC_TXOP_CSR0, ®); | |
2674 | rt2x00_set_field32(®, field, queue->txop); | |
2675 | rt2x00pci_register_write(rt2x00dev, AC_TXOP_CSR0, reg); | |
2676 | } else if (queue_idx < 4) { | |
2677 | field.bit_offset = (queue_idx - 2) * 16; | |
2678 | field.bit_mask = 0xffff << field.bit_offset; | |
2679 | ||
2680 | rt2x00pci_register_read(rt2x00dev, AC_TXOP_CSR1, ®); | |
2681 | rt2x00_set_field32(®, field, queue->txop); | |
2682 | rt2x00pci_register_write(rt2x00dev, AC_TXOP_CSR1, reg); | |
2683 | } | |
2684 | ||
2685 | /* Update WMM registers */ | |
2686 | field.bit_offset = queue_idx * 4; | |
2687 | field.bit_mask = 0xf << field.bit_offset; | |
2688 | ||
2689 | rt2x00pci_register_read(rt2x00dev, AIFSN_CSR, ®); | |
2690 | rt2x00_set_field32(®, field, queue->aifs); | |
2691 | rt2x00pci_register_write(rt2x00dev, AIFSN_CSR, reg); | |
2692 | ||
2693 | rt2x00pci_register_read(rt2x00dev, CWMIN_CSR, ®); | |
2694 | rt2x00_set_field32(®, field, queue->cw_min); | |
2695 | rt2x00pci_register_write(rt2x00dev, CWMIN_CSR, reg); | |
2696 | ||
2697 | rt2x00pci_register_read(rt2x00dev, CWMAX_CSR, ®); | |
2698 | rt2x00_set_field32(®, field, queue->cw_max); | |
2699 | rt2x00pci_register_write(rt2x00dev, CWMAX_CSR, reg); | |
2700 | ||
2701 | return 0; | |
2702 | } | |
2703 | ||
95ea3627 ID |
2704 | static u64 rt61pci_get_tsf(struct ieee80211_hw *hw) |
2705 | { | |
2706 | struct rt2x00_dev *rt2x00dev = hw->priv; | |
2707 | u64 tsf; | |
2708 | u32 reg; | |
2709 | ||
2710 | rt2x00pci_register_read(rt2x00dev, TXRX_CSR13, ®); | |
2711 | tsf = (u64) rt2x00_get_field32(reg, TXRX_CSR13_HIGH_TSFTIMER) << 32; | |
2712 | rt2x00pci_register_read(rt2x00dev, TXRX_CSR12, ®); | |
2713 | tsf |= rt2x00_get_field32(reg, TXRX_CSR12_LOW_TSFTIMER); | |
2714 | ||
2715 | return tsf; | |
2716 | } | |
2717 | ||
95ea3627 ID |
2718 | static const struct ieee80211_ops rt61pci_mac80211_ops = { |
2719 | .tx = rt2x00mac_tx, | |
4150c572 JB |
2720 | .start = rt2x00mac_start, |
2721 | .stop = rt2x00mac_stop, | |
95ea3627 ID |
2722 | .add_interface = rt2x00mac_add_interface, |
2723 | .remove_interface = rt2x00mac_remove_interface, | |
2724 | .config = rt2x00mac_config, | |
2725 | .config_interface = rt2x00mac_config_interface, | |
3a643d24 | 2726 | .configure_filter = rt2x00mac_configure_filter, |
61e754f4 | 2727 | .set_key = rt2x00mac_set_key, |
95ea3627 ID |
2728 | .get_stats = rt2x00mac_get_stats, |
2729 | .set_retry_limit = rt61pci_set_retry_limit, | |
471b3efd | 2730 | .bss_info_changed = rt2x00mac_bss_info_changed, |
2af0a570 | 2731 | .conf_tx = rt61pci_conf_tx, |
95ea3627 ID |
2732 | .get_tx_stats = rt2x00mac_get_tx_stats, |
2733 | .get_tsf = rt61pci_get_tsf, | |
95ea3627 ID |
2734 | }; |
2735 | ||
2736 | static const struct rt2x00lib_ops rt61pci_rt2x00_ops = { | |
2737 | .irq_handler = rt61pci_interrupt, | |
2738 | .probe_hw = rt61pci_probe_hw, | |
2739 | .get_firmware_name = rt61pci_get_firmware_name, | |
a7f3a06c | 2740 | .get_firmware_crc = rt61pci_get_firmware_crc, |
95ea3627 ID |
2741 | .load_firmware = rt61pci_load_firmware, |
2742 | .initialize = rt2x00pci_initialize, | |
2743 | .uninitialize = rt2x00pci_uninitialize, | |
837e7f24 ID |
2744 | .init_rxentry = rt61pci_init_rxentry, |
2745 | .init_txentry = rt61pci_init_txentry, | |
95ea3627 | 2746 | .set_device_state = rt61pci_set_device_state, |
95ea3627 | 2747 | .rfkill_poll = rt61pci_rfkill_poll, |
95ea3627 ID |
2748 | .link_stats = rt61pci_link_stats, |
2749 | .reset_tuner = rt61pci_reset_tuner, | |
2750 | .link_tuner = rt61pci_link_tuner, | |
2751 | .write_tx_desc = rt61pci_write_tx_desc, | |
2752 | .write_tx_data = rt2x00pci_write_tx_data, | |
bd88a781 | 2753 | .write_beacon = rt61pci_write_beacon, |
95ea3627 ID |
2754 | .kick_tx_queue = rt61pci_kick_tx_queue, |
2755 | .fill_rxdone = rt61pci_fill_rxdone, | |
61e754f4 ID |
2756 | .config_shared_key = rt61pci_config_shared_key, |
2757 | .config_pairwise_key = rt61pci_config_pairwise_key, | |
3a643d24 | 2758 | .config_filter = rt61pci_config_filter, |
6bb40dd1 | 2759 | .config_intf = rt61pci_config_intf, |
72810379 | 2760 | .config_erp = rt61pci_config_erp, |
95ea3627 ID |
2761 | .config = rt61pci_config, |
2762 | }; | |
2763 | ||
181d6902 ID |
2764 | static const struct data_queue_desc rt61pci_queue_rx = { |
2765 | .entry_num = RX_ENTRIES, | |
2766 | .data_size = DATA_FRAME_SIZE, | |
2767 | .desc_size = RXD_DESC_SIZE, | |
b8be63ff | 2768 | .priv_size = sizeof(struct queue_entry_priv_pci), |
181d6902 ID |
2769 | }; |
2770 | ||
2771 | static const struct data_queue_desc rt61pci_queue_tx = { | |
2772 | .entry_num = TX_ENTRIES, | |
2773 | .data_size = DATA_FRAME_SIZE, | |
2774 | .desc_size = TXD_DESC_SIZE, | |
b8be63ff | 2775 | .priv_size = sizeof(struct queue_entry_priv_pci), |
181d6902 ID |
2776 | }; |
2777 | ||
2778 | static const struct data_queue_desc rt61pci_queue_bcn = { | |
6bb40dd1 | 2779 | .entry_num = 4 * BEACON_ENTRIES, |
78720897 | 2780 | .data_size = 0, /* No DMA required for beacons */ |
181d6902 | 2781 | .desc_size = TXINFO_SIZE, |
b8be63ff | 2782 | .priv_size = sizeof(struct queue_entry_priv_pci), |
181d6902 ID |
2783 | }; |
2784 | ||
95ea3627 | 2785 | static const struct rt2x00_ops rt61pci_ops = { |
2360157c | 2786 | .name = KBUILD_MODNAME, |
6bb40dd1 ID |
2787 | .max_sta_intf = 1, |
2788 | .max_ap_intf = 4, | |
95ea3627 ID |
2789 | .eeprom_size = EEPROM_SIZE, |
2790 | .rf_size = RF_SIZE, | |
61448f88 | 2791 | .tx_queues = NUM_TX_QUEUES, |
181d6902 ID |
2792 | .rx = &rt61pci_queue_rx, |
2793 | .tx = &rt61pci_queue_tx, | |
2794 | .bcn = &rt61pci_queue_bcn, | |
95ea3627 ID |
2795 | .lib = &rt61pci_rt2x00_ops, |
2796 | .hw = &rt61pci_mac80211_ops, | |
2797 | #ifdef CONFIG_RT2X00_LIB_DEBUGFS | |
2798 | .debugfs = &rt61pci_rt2x00debug, | |
2799 | #endif /* CONFIG_RT2X00_LIB_DEBUGFS */ | |
2800 | }; | |
2801 | ||
2802 | /* | |
2803 | * RT61pci module information. | |
2804 | */ | |
2805 | static struct pci_device_id rt61pci_device_table[] = { | |
2806 | /* RT2561s */ | |
2807 | { PCI_DEVICE(0x1814, 0x0301), PCI_DEVICE_DATA(&rt61pci_ops) }, | |
2808 | /* RT2561 v2 */ | |
2809 | { PCI_DEVICE(0x1814, 0x0302), PCI_DEVICE_DATA(&rt61pci_ops) }, | |
2810 | /* RT2661 */ | |
2811 | { PCI_DEVICE(0x1814, 0x0401), PCI_DEVICE_DATA(&rt61pci_ops) }, | |
2812 | { 0, } | |
2813 | }; | |
2814 | ||
2815 | MODULE_AUTHOR(DRV_PROJECT); | |
2816 | MODULE_VERSION(DRV_VERSION); | |
2817 | MODULE_DESCRIPTION("Ralink RT61 PCI & PCMCIA Wireless LAN driver."); | |
2818 | MODULE_SUPPORTED_DEVICE("Ralink RT2561, RT2561s & RT2661 " | |
2819 | "PCI & PCMCIA chipset based cards"); | |
2820 | MODULE_DEVICE_TABLE(pci, rt61pci_device_table); | |
2821 | MODULE_FIRMWARE(FIRMWARE_RT2561); | |
2822 | MODULE_FIRMWARE(FIRMWARE_RT2561s); | |
2823 | MODULE_FIRMWARE(FIRMWARE_RT2661); | |
2824 | MODULE_LICENSE("GPL"); | |
2825 | ||
2826 | static struct pci_driver rt61pci_driver = { | |
2360157c | 2827 | .name = KBUILD_MODNAME, |
95ea3627 ID |
2828 | .id_table = rt61pci_device_table, |
2829 | .probe = rt2x00pci_probe, | |
2830 | .remove = __devexit_p(rt2x00pci_remove), | |
2831 | .suspend = rt2x00pci_suspend, | |
2832 | .resume = rt2x00pci_resume, | |
2833 | }; | |
2834 | ||
2835 | static int __init rt61pci_init(void) | |
2836 | { | |
2837 | return pci_register_driver(&rt61pci_driver); | |
2838 | } | |
2839 | ||
2840 | static void __exit rt61pci_exit(void) | |
2841 | { | |
2842 | pci_unregister_driver(&rt61pci_driver); | |
2843 | } | |
2844 | ||
2845 | module_init(rt61pci_init); | |
2846 | module_exit(rt61pci_exit); |