projects / deliverable / linux.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
mac80211: remove more excess kernel-doc
[deliverable/linux.git] / drivers / net / wireless / rt2x00 / rt61pci.c
CommitLineData
95ea3627 1/*
811aa9ca 2 Copyright (C) 2004 - 2008 rt2x00 SourceForge Project
95ea3627
ID		 3 <http://rt2x00.serialmonkey.com>
4
5 This program is free software; you can redistribute it and/or modify
6 it under the terms of the GNU General Public License as published by
7 the Free Software Foundation; either version 2 of the License, or
8 (at your option) any later version.
9
10 This program is distributed in the hope that it will be useful,
11 but WITHOUT ANY WARRANTY; without even the implied warranty of
12 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 GNU General Public License for more details.
14
15 You should have received a copy of the GNU General Public License
16 along with this program; if not, write to the
17 Free Software Foundation, Inc.,
18 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
19 */
20
21/*
22 Module: rt61pci
23 Abstract: rt61pci device specific routines.
24 Supported chipsets: RT2561, RT2561s, RT2661.
25 */
26
a7f3a06c 27#include <linux/crc-itu-t.h>
95ea3627
ID		 28#include <linux/delay.h>
29#include <linux/etherdevice.h>
30#include <linux/init.h>
31#include <linux/kernel.h>
32#include <linux/module.h>
33#include <linux/pci.h>
34#include <linux/eeprom_93cx6.h>
35
36#include "rt2x00.h"
37#include "rt2x00pci.h"
38#include "rt61pci.h"
39
008c4482
ID		 40/*
41 * Allow hardware encryption to be disabled.
42 */
43static int modparam_nohwcrypt = 0;
44module_param_named(nohwcrypt, modparam_nohwcrypt, bool, S_IRUGO);
45MODULE_PARM_DESC(nohwcrypt, "Disable hardware encryption.");
46
95ea3627
ID		 47/*
48 * Register access.
49 * BBP and RF register require indirect register access,
50 * and use the CSR registers PHY_CSR3 and PHY_CSR4 to achieve this.
51 * These indirect registers work with busy bits,
52 * and we will try maximal REGISTER_BUSY_COUNT times to access
53 * the register while taking a REGISTER_BUSY_DELAY us delay
54 * between each attampt. When the busy bit is still set at that time,
55 * the access attempt is considered to have failed,
56 * and we will print an error.
57 */
0e14f6d3 58static u32 rt61pci_bbp_check(struct rt2x00_dev *rt2x00dev)
95ea3627
ID		 59{
60 u32 reg;
61 unsigned int i;
62
63 for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
64 rt2x00pci_register_read(rt2x00dev, PHY_CSR3, &reg);
65 if (!rt2x00_get_field32(reg, PHY_CSR3_BUSY))
66 break;
67 udelay(REGISTER_BUSY_DELAY);
68 }
69
70 return reg;
71}
72
0e14f6d3 73static void rt61pci_bbp_write(struct rt2x00_dev *rt2x00dev,
95ea3627
ID		 74 const unsigned int word, const u8 value)
75{
76 u32 reg;
77
78 /*
79 * Wait until the BBP becomes ready.
80 */
81 reg = rt61pci_bbp_check(rt2x00dev);
82 if (rt2x00_get_field32(reg, PHY_CSR3_BUSY)) {
83 ERROR(rt2x00dev, "PHY_CSR3 register busy. Write failed.\n");
84 return;
85 }
86
87 /*
88 * Write the data into the BBP.
89 */
90 reg = 0;
91 rt2x00_set_field32(&reg, PHY_CSR3_VALUE, value);
92 rt2x00_set_field32(&reg, PHY_CSR3_REGNUM, word);
93 rt2x00_set_field32(&reg, PHY_CSR3_BUSY, 1);
94 rt2x00_set_field32(&reg, PHY_CSR3_READ_CONTROL, 0);
95
96 rt2x00pci_register_write(rt2x00dev, PHY_CSR3, reg);
97}
98
0e14f6d3 99static void rt61pci_bbp_read(struct rt2x00_dev *rt2x00dev,
95ea3627
ID		 100 const unsigned int word, u8 *value)
101{
102 u32 reg;
103
104 /*
105 * Wait until the BBP becomes ready.
106 */
107 reg = rt61pci_bbp_check(rt2x00dev);
108 if (rt2x00_get_field32(reg, PHY_CSR3_BUSY)) {
109 ERROR(rt2x00dev, "PHY_CSR3 register busy. Read failed.\n");
110 return;
111 }
112
113 /*
114 * Write the request into the BBP.
115 */
116 reg = 0;
117 rt2x00_set_field32(&reg, PHY_CSR3_REGNUM, word);
118 rt2x00_set_field32(&reg, PHY_CSR3_BUSY, 1);
119 rt2x00_set_field32(&reg, PHY_CSR3_READ_CONTROL, 1);
120
121 rt2x00pci_register_write(rt2x00dev, PHY_CSR3, reg);
122
123 /*
124 * Wait until the BBP becomes ready.
125 */
126 reg = rt61pci_bbp_check(rt2x00dev);
127 if (rt2x00_get_field32(reg, PHY_CSR3_BUSY)) {
128 ERROR(rt2x00dev, "PHY_CSR3 register busy. Read failed.\n");
129 *value = 0xff;
130 return;
131 }
132
133 *value = rt2x00_get_field32(reg, PHY_CSR3_VALUE);
134}
135
0e14f6d3 136static void rt61pci_rf_write(struct rt2x00_dev *rt2x00dev,
95ea3627
ID		 137 const unsigned int word, const u32 value)
138{
139 u32 reg;
140 unsigned int i;
141
142 if (!word)
143 return;
144
145 for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
146 rt2x00pci_register_read(rt2x00dev, PHY_CSR4, &reg);
147 if (!rt2x00_get_field32(reg, PHY_CSR4_BUSY))
148 goto rf_write;
149 udelay(REGISTER_BUSY_DELAY);
150 }
151
152 ERROR(rt2x00dev, "PHY_CSR4 register busy. Write failed.\n");
153 return;
154
155rf_write:
156 reg = 0;
157 rt2x00_set_field32(&reg, PHY_CSR4_VALUE, value);
158 rt2x00_set_field32(&reg, PHY_CSR4_NUMBER_OF_BITS, 21);
159 rt2x00_set_field32(&reg, PHY_CSR4_IF_SELECT, 0);
160 rt2x00_set_field32(&reg, PHY_CSR4_BUSY, 1);
161
162 rt2x00pci_register_write(rt2x00dev, PHY_CSR4, reg);
163 rt2x00_rf_write(rt2x00dev, word, value);
164}
165
771fd565 166#ifdef CONFIG_RT2X00_LIB_LEDS
a9450b70
ID		 167/*
168 * This function is only called from rt61pci_led_brightness()
169 * make gcc happy by placing this function inside the
170 * same ifdef statement as the caller.
171 */
0e14f6d3 172static void rt61pci_mcu_request(struct rt2x00_dev *rt2x00dev,
95ea3627
ID		 173 const u8 command, const u8 token,
174 const u8 arg0, const u8 arg1)
175{
176 u32 reg;
177
178 rt2x00pci_register_read(rt2x00dev, H2M_MAILBOX_CSR, &reg);
179
180 if (rt2x00_get_field32(reg, H2M_MAILBOX_CSR_OWNER)) {
181 ERROR(rt2x00dev, "mcu request error. "
182 "Request 0x%02x failed for token 0x%02x.\n",
183 command, token);
184 return;
185 }
186
187 rt2x00_set_field32(&reg, H2M_MAILBOX_CSR_OWNER, 1);
188 rt2x00_set_field32(&reg, H2M_MAILBOX_CSR_CMD_TOKEN, token);
189 rt2x00_set_field32(&reg, H2M_MAILBOX_CSR_ARG0, arg0);
190 rt2x00_set_field32(&reg, H2M_MAILBOX_CSR_ARG1, arg1);
191 rt2x00pci_register_write(rt2x00dev, H2M_MAILBOX_CSR, reg);
192
193 rt2x00pci_register_read(rt2x00dev, HOST_CMD_CSR, &reg);
194 rt2x00_set_field32(&reg, HOST_CMD_CSR_HOST_COMMAND, command);
195 rt2x00_set_field32(&reg, HOST_CMD_CSR_INTERRUPT_MCU, 1);
196 rt2x00pci_register_write(rt2x00dev, HOST_CMD_CSR, reg);
197}
771fd565 198#endif /* CONFIG_RT2X00_LIB_LEDS */
95ea3627
ID		 199
200static void rt61pci_eepromregister_read(struct eeprom_93cx6 *eeprom)
201{
202 struct rt2x00_dev *rt2x00dev = eeprom->data;
203 u32 reg;
204
205 rt2x00pci_register_read(rt2x00dev, E2PROM_CSR, &reg);
206
207 eeprom->reg_data_in = !!rt2x00_get_field32(reg, E2PROM_CSR_DATA_IN);
208 eeprom->reg_data_out = !!rt2x00_get_field32(reg, E2PROM_CSR_DATA_OUT);
209 eeprom->reg_data_clock =
210 !!rt2x00_get_field32(reg, E2PROM_CSR_DATA_CLOCK);
211 eeprom->reg_chip_select =
212 !!rt2x00_get_field32(reg, E2PROM_CSR_CHIP_SELECT);
213}
214
215static void rt61pci_eepromregister_write(struct eeprom_93cx6 *eeprom)
216{
217 struct rt2x00_dev *rt2x00dev = eeprom->data;
218 u32 reg = 0;
219
220 rt2x00_set_field32(&reg, E2PROM_CSR_DATA_IN, !!eeprom->reg_data_in);
221 rt2x00_set_field32(&reg, E2PROM_CSR_DATA_OUT, !!eeprom->reg_data_out);
222 rt2x00_set_field32(&reg, E2PROM_CSR_DATA_CLOCK,
223 !!eeprom->reg_data_clock);
224 rt2x00_set_field32(&reg, E2PROM_CSR_CHIP_SELECT,
225 !!eeprom->reg_chip_select);
226
227 rt2x00pci_register_write(rt2x00dev, E2PROM_CSR, reg);
228}
229
230#ifdef CONFIG_RT2X00_LIB_DEBUGFS
95ea3627
ID		 231static const struct rt2x00debug rt61pci_rt2x00debug = {
232 .owner = THIS_MODULE,
233 .csr = {
743b97ca
ID		 234 .read = rt2x00pci_register_read,
235 .write = rt2x00pci_register_write,
236 .flags = RT2X00DEBUGFS_OFFSET,
237 .word_base = CSR_REG_BASE,
95ea3627
ID		 238 .word_size = sizeof(u32),
239 .word_count = CSR_REG_SIZE / sizeof(u32),
240 },
241 .eeprom = {
242 .read = rt2x00_eeprom_read,
243 .write = rt2x00_eeprom_write,
743b97ca 244 .word_base = EEPROM_BASE,
95ea3627
ID		 245 .word_size = sizeof(u16),
246 .word_count = EEPROM_SIZE / sizeof(u16),
247 },
248 .bbp = {
249 .read = rt61pci_bbp_read,
250 .write = rt61pci_bbp_write,
743b97ca 251 .word_base = BBP_BASE,
95ea3627
ID		 252 .word_size = sizeof(u8),
253 .word_count = BBP_SIZE / sizeof(u8),
254 },
255 .rf = {
256 .read = rt2x00_rf_read,
257 .write = rt61pci_rf_write,
743b97ca 258 .word_base = RF_BASE,
95ea3627
ID		 259 .word_size = sizeof(u32),
260 .word_count = RF_SIZE / sizeof(u32),
261 },
262};
263#endif /* CONFIG_RT2X00_LIB_DEBUGFS */
264
58169529 265#ifdef CONFIG_RT2X00_LIB_RFKILL
95ea3627
ID		 266static int rt61pci_rfkill_poll(struct rt2x00_dev *rt2x00dev)
267{
268 u32 reg;
269
270 rt2x00pci_register_read(rt2x00dev, MAC_CSR13, &reg);
181d6902 271 return rt2x00_get_field32(reg, MAC_CSR13_BIT5);
95ea3627 272}
81873e9c
ID		 273#else
274#define rt61pci_rfkill_poll NULL
58169529 275#endif /* CONFIG_RT2X00_LIB_RFKILL */
95ea3627 276
771fd565 277#ifdef CONFIG_RT2X00_LIB_LEDS
a2e1d52a 278static void rt61pci_brightness_set(struct led_classdev *led_cdev,
a9450b70
ID		 279 enum led_brightness brightness)
280{
281 struct rt2x00_led *led =
282 container_of(led_cdev, struct rt2x00_led, led_dev);
283 unsigned int enabled = brightness != LED_OFF;
284 unsigned int a_mode =
285 (enabled && led->rt2x00dev->curr_band == IEEE80211_BAND_5GHZ);
286 unsigned int bg_mode =
287 (enabled && led->rt2x00dev->curr_band == IEEE80211_BAND_2GHZ);
288
289 if (led->type == LED_TYPE_RADIO) {
290 rt2x00_set_field16(&led->rt2x00dev->led_mcu_reg,
291 MCU_LEDCS_RADIO_STATUS, enabled);
292
293 rt61pci_mcu_request(led->rt2x00dev, MCU_LED, 0xff,
294 (led->rt2x00dev->led_mcu_reg & 0xff),
295 ((led->rt2x00dev->led_mcu_reg >> 8)));
296 } else if (led->type == LED_TYPE_ASSOC) {
297 rt2x00_set_field16(&led->rt2x00dev->led_mcu_reg,
298 MCU_LEDCS_LINK_BG_STATUS, bg_mode);
299 rt2x00_set_field16(&led->rt2x00dev->led_mcu_reg,
300 MCU_LEDCS_LINK_A_STATUS, a_mode);
301
302 rt61pci_mcu_request(led->rt2x00dev, MCU_LED, 0xff,
303 (led->rt2x00dev->led_mcu_reg & 0xff),
304 ((led->rt2x00dev->led_mcu_reg >> 8)));
305 } else if (led->type == LED_TYPE_QUALITY) {
306 /*
307 * The brightness is divided into 6 levels (0 - 5),
308 * this means we need to convert the brightness
309 * argument into the matching level within that range.
310 */
311 rt61pci_mcu_request(led->rt2x00dev, MCU_LED_STRENGTH, 0xff,
312 brightness / (LED_FULL / 6), 0);
313 }
314}
a2e1d52a
ID		 315
316static int rt61pci_blink_set(struct led_classdev *led_cdev,
317 unsigned long *delay_on,
318 unsigned long *delay_off)
319{
320 struct rt2x00_led *led =
321 container_of(led_cdev, struct rt2x00_led, led_dev);
322 u32 reg;
323
324 rt2x00pci_register_read(led->rt2x00dev, MAC_CSR14, &reg);
325 rt2x00_set_field32(&reg, MAC_CSR14_ON_PERIOD, *delay_on);
326 rt2x00_set_field32(&reg, MAC_CSR14_OFF_PERIOD, *delay_off);
327 rt2x00pci_register_write(led->rt2x00dev, MAC_CSR14, reg);
328
329 return 0;
330}
475433be
ID		 331
332static void rt61pci_init_led(struct rt2x00_dev *rt2x00dev,
333 struct rt2x00_led *led,
334 enum led_type type)
335{
336 led->rt2x00dev = rt2x00dev;
337 led->type = type;
338 led->led_dev.brightness_set = rt61pci_brightness_set;
339 led->led_dev.blink_set = rt61pci_blink_set;
340 led->flags = LED_INITIALIZED;
341}
771fd565 342#endif /* CONFIG_RT2X00_LIB_LEDS */
a9450b70 343
95ea3627
ID		 344/*
345 * Configuration handlers.
346 */
61e754f4
ID		 347static int rt61pci_config_shared_key(struct rt2x00_dev *rt2x00dev,
348 struct rt2x00lib_crypto *crypto,
349 struct ieee80211_key_conf *key)
350{
351 struct hw_key_entry key_entry;
352 struct rt2x00_field32 field;
353 u32 mask;
354 u32 reg;
355
356 if (crypto->cmd == SET_KEY) {
357 /*
358 * rt2x00lib can't determine the correct free
359 * key_idx for shared keys. We have 1 register
360 * with key valid bits. The goal is simple, read
361 * the register, if that is full we have no slots
362 * left.
363 * Note that each BSS is allowed to have up to 4
364 * shared keys, so put a mask over the allowed
365 * entries.
366 */
367 mask = (0xf << crypto->bssidx);
368
369 rt2x00pci_register_read(rt2x00dev, SEC_CSR0, &reg);
370 reg &= mask;
371
372 if (reg && reg == mask)
373 return -ENOSPC;
374
acaf908d 375 key->hw_key_idx += reg ? ffz(reg) : 0;
61e754f4
ID		 376
377 /*
378 * Upload key to hardware
379 */
380 memcpy(key_entry.key, crypto->key,
381 sizeof(key_entry.key));
382 memcpy(key_entry.tx_mic, crypto->tx_mic,
383 sizeof(key_entry.tx_mic));
384 memcpy(key_entry.rx_mic, crypto->rx_mic,
385 sizeof(key_entry.rx_mic));
386
387 reg = SHARED_KEY_ENTRY(key->hw_key_idx);
388 rt2x00pci_register_multiwrite(rt2x00dev, reg,
389 &key_entry, sizeof(key_entry));
390
391 /*
392 * The cipher types are stored over 2 registers.
393 * bssidx 0 and 1 keys are stored in SEC_CSR1 and
394 * bssidx 1 and 2 keys are stored in SEC_CSR5.
395 * Using the correct defines correctly will cause overhead,
396 * so just calculate the correct offset.
397 */
398 if (key->hw_key_idx < 8) {
399 field.bit_offset = (3 * key->hw_key_idx);
400 field.bit_mask = 0x7 << field.bit_offset;
401
402 rt2x00pci_register_read(rt2x00dev, SEC_CSR1, &reg);
403 rt2x00_set_field32(&reg, field, crypto->cipher);
404 rt2x00pci_register_write(rt2x00dev, SEC_CSR1, reg);
405 } else {
406 field.bit_offset = (3 * (key->hw_key_idx - 8));
407 field.bit_mask = 0x7 << field.bit_offset;
408
409 rt2x00pci_register_read(rt2x00dev, SEC_CSR5, &reg);
410 rt2x00_set_field32(&reg, field, crypto->cipher);
411 rt2x00pci_register_write(rt2x00dev, SEC_CSR5, reg);
412 }
413
414 /*
415 * The driver does not support the IV/EIV generation
416 * in hardware. However it doesn't support the IV/EIV
417 * inside the ieee80211 frame either, but requires it
418 * to be provided seperately for the descriptor.
419 * rt2x00lib will cut the IV/EIV data out of all frames
420 * given to us by mac80211, but we must tell mac80211
421 * to generate the IV/EIV data.
422 */
423 key->flags |= IEEE80211_KEY_FLAG_GENERATE_IV;
424 }
425
426 /*
427 * SEC_CSR0 contains only single-bit fields to indicate
428 * a particular key is valid. Because using the FIELD32()
429 * defines directly will cause a lot of overhead we use
430 * a calculation to determine the correct bit directly.
431 */
432 mask = 1 << key->hw_key_idx;
433
434 rt2x00pci_register_read(rt2x00dev, SEC_CSR0, &reg);
435 if (crypto->cmd == SET_KEY)
436 reg |= mask;
437 else if (crypto->cmd == DISABLE_KEY)
438 reg &= ~mask;
439 rt2x00pci_register_write(rt2x00dev, SEC_CSR0, reg);
440
441 return 0;
442}
443
444static int rt61pci_config_pairwise_key(struct rt2x00_dev *rt2x00dev,
445 struct rt2x00lib_crypto *crypto,
446 struct ieee80211_key_conf *key)
447{
448 struct hw_pairwise_ta_entry addr_entry;
449 struct hw_key_entry key_entry;
450 u32 mask;
451 u32 reg;
452
453 if (crypto->cmd == SET_KEY) {
454 /*
455 * rt2x00lib can't determine the correct free
456 * key_idx for pairwise keys. We have 2 registers
457 * with key valid bits. The goal is simple, read
458 * the first register, if that is full move to
459 * the next register.
460 * When both registers are full, we drop the key,
461 * otherwise we use the first invalid entry.
462 */
463 rt2x00pci_register_read(rt2x00dev, SEC_CSR2, &reg);
464 if (reg && reg == ~0) {
465 key->hw_key_idx = 32;
466 rt2x00pci_register_read(rt2x00dev, SEC_CSR3, &reg);
467 if (reg && reg == ~0)
468 return -ENOSPC;
469 }
470
acaf908d 471 key->hw_key_idx += reg ? ffz(reg) : 0;
61e754f4
ID		 472
473 /*
474 * Upload key to hardware
475 */
476 memcpy(key_entry.key, crypto->key,
477 sizeof(key_entry.key));
478 memcpy(key_entry.tx_mic, crypto->tx_mic,
479 sizeof(key_entry.tx_mic));
480 memcpy(key_entry.rx_mic, crypto->rx_mic,
481 sizeof(key_entry.rx_mic));
482
483 memset(&addr_entry, 0, sizeof(addr_entry));
484 memcpy(&addr_entry, crypto->address, ETH_ALEN);
485 addr_entry.cipher = crypto->cipher;
486
487 reg = PAIRWISE_KEY_ENTRY(key->hw_key_idx);
488 rt2x00pci_register_multiwrite(rt2x00dev, reg,
489 &key_entry, sizeof(key_entry));
490
491 reg = PAIRWISE_TA_ENTRY(key->hw_key_idx);
492 rt2x00pci_register_multiwrite(rt2x00dev, reg,
493 &addr_entry, sizeof(addr_entry));
494
495 /*
496 * Enable pairwise lookup table for given BSS idx,
497 * without this received frames will not be decrypted
498 * by the hardware.
499 */
500 rt2x00pci_register_read(rt2x00dev, SEC_CSR4, &reg);
501 reg |= (1 << crypto->bssidx);
502 rt2x00pci_register_write(rt2x00dev, SEC_CSR4, reg);
503
504 /*
505 * The driver does not support the IV/EIV generation
506 * in hardware. However it doesn't support the IV/EIV
507 * inside the ieee80211 frame either, but requires it
508 * to be provided seperately for the descriptor.
509 * rt2x00lib will cut the IV/EIV data out of all frames
510 * given to us by mac80211, but we must tell mac80211
511 * to generate the IV/EIV data.
512 */
513 key->flags |= IEEE80211_KEY_FLAG_GENERATE_IV;
514 }
515
516 /*
517 * SEC_CSR2 and SEC_CSR3 contain only single-bit fields to indicate
518 * a particular key is valid. Because using the FIELD32()
519 * defines directly will cause a lot of overhead we use
520 * a calculation to determine the correct bit directly.
521 */
522 if (key->hw_key_idx < 32) {
523 mask = 1 << key->hw_key_idx;
524
525 rt2x00pci_register_read(rt2x00dev, SEC_CSR2, &reg);
526 if (crypto->cmd == SET_KEY)
527 reg |= mask;
528 else if (crypto->cmd == DISABLE_KEY)
529 reg &= ~mask;
530 rt2x00pci_register_write(rt2x00dev, SEC_CSR2, reg);
531 } else {
532 mask = 1 << (key->hw_key_idx - 32);
533
534 rt2x00pci_register_read(rt2x00dev, SEC_CSR3, &reg);
535 if (crypto->cmd == SET_KEY)
536 reg |= mask;
537 else if (crypto->cmd == DISABLE_KEY)
538 reg &= ~mask;
539 rt2x00pci_register_write(rt2x00dev, SEC_CSR3, reg);
540 }
541
542 return 0;
543}
544
3a643d24
ID		 545static void rt61pci_config_filter(struct rt2x00_dev *rt2x00dev,
546 const unsigned int filter_flags)
547{
548 u32 reg;
549
550 /*
551 * Start configuration steps.
552 * Note that the version error will always be dropped
553 * and broadcast frames will always be accepted since
554 * there is no filter for it at this time.
555 */
556 rt2x00pci_register_read(rt2x00dev, TXRX_CSR0, &reg);
557 rt2x00_set_field32(&reg, TXRX_CSR0_DROP_CRC,
558 !(filter_flags & FIF_FCSFAIL));
559 rt2x00_set_field32(&reg, TXRX_CSR0_DROP_PHYSICAL,
560 !(filter_flags & FIF_PLCPFAIL));
561 rt2x00_set_field32(&reg, TXRX_CSR0_DROP_CONTROL,
562 !(filter_flags & FIF_CONTROL));
563 rt2x00_set_field32(&reg, TXRX_CSR0_DROP_NOT_TO_ME,
564 !(filter_flags & FIF_PROMISC_IN_BSS));
565 rt2x00_set_field32(&reg, TXRX_CSR0_DROP_TO_DS,
e0b005fa
ID		 566 !(filter_flags & FIF_PROMISC_IN_BSS) &&
567 !rt2x00dev->intf_ap_count);
3a643d24
ID		 568 rt2x00_set_field32(&reg, TXRX_CSR0_DROP_VERSION_ERROR, 1);
569 rt2x00_set_field32(&reg, TXRX_CSR0_DROP_MULTICAST,
570 !(filter_flags & FIF_ALLMULTI));
571 rt2x00_set_field32(&reg, TXRX_CSR0_DROP_BROADCAST, 0);
572 rt2x00_set_field32(&reg, TXRX_CSR0_DROP_ACK_CTS,
573 !(filter_flags & FIF_CONTROL));
574 rt2x00pci_register_write(rt2x00dev, TXRX_CSR0, reg);
575}
576
6bb40dd1
ID		 577static void rt61pci_config_intf(struct rt2x00_dev *rt2x00dev,
578 struct rt2x00_intf *intf,
579 struct rt2x00intf_conf *conf,
580 const unsigned int flags)
95ea3627 581{
6bb40dd1
ID		 582 unsigned int beacon_base;
583 u32 reg;
95ea3627 584
6bb40dd1
ID		 585 if (flags & CONFIG_UPDATE_TYPE) {
586 /*
587 * Clear current synchronisation setup.
588 * For the Beacon base registers we only need to clear
589 * the first byte since that byte contains the VALID and OWNER
590 * bits which (when set to 0) will invalidate the entire beacon.
591 */
592 beacon_base = HW_BEACON_OFFSET(intf->beacon->entry_idx);
6bb40dd1 593 rt2x00pci_register_write(rt2x00dev, beacon_base, 0);
95ea3627 594
6bb40dd1
ID		 595 /*
596 * Enable synchronisation.
597 */
598 rt2x00pci_register_read(rt2x00dev, TXRX_CSR9, &reg);
fd3c91c5 599 rt2x00_set_field32(&reg, TXRX_CSR9_TSF_TICKING, 1);
6bb40dd1 600 rt2x00_set_field32(&reg, TXRX_CSR9_TSF_SYNC, conf->sync);
fd3c91c5 601 rt2x00_set_field32(&reg, TXRX_CSR9_TBTT_ENABLE, 1);
6bb40dd1
ID		 602 rt2x00pci_register_write(rt2x00dev, TXRX_CSR9, reg);
603 }
95ea3627 604
6bb40dd1
ID		 605 if (flags & CONFIG_UPDATE_MAC) {
606 reg = le32_to_cpu(conf->mac[1]);
607 rt2x00_set_field32(&reg, MAC_CSR3_UNICAST_TO_ME_MASK, 0xff);
608 conf->mac[1] = cpu_to_le32(reg);
95ea3627 609
6bb40dd1
ID		 610 rt2x00pci_register_multiwrite(rt2x00dev, MAC_CSR2,
611 conf->mac, sizeof(conf->mac));
612 }
95ea3627 613
6bb40dd1
ID		 614 if (flags & CONFIG_UPDATE_BSSID) {
615 reg = le32_to_cpu(conf->bssid[1]);
616 rt2x00_set_field32(&reg, MAC_CSR5_BSS_ID_MASK, 3);
617 conf->bssid[1] = cpu_to_le32(reg);
95ea3627 618
6bb40dd1
ID		 619 rt2x00pci_register_multiwrite(rt2x00dev, MAC_CSR4,
620 conf->bssid, sizeof(conf->bssid));
621 }
95ea3627
ID		 622}
623
3a643d24
ID		 624static void rt61pci_config_erp(struct rt2x00_dev *rt2x00dev,
625 struct rt2x00lib_erp *erp)
95ea3627 626{
95ea3627 627 u32 reg;
95ea3627
ID		 628
629 rt2x00pci_register_read(rt2x00dev, TXRX_CSR0, &reg);
72810379 630 rt2x00_set_field32(&reg, TXRX_CSR0_RX_ACK_TIMEOUT, erp->ack_timeout);
95ea3627
ID		 631 rt2x00pci_register_write(rt2x00dev, TXRX_CSR0, reg);
632
633 rt2x00pci_register_read(rt2x00dev, TXRX_CSR4, &reg);
4f5af6eb 634 rt2x00_set_field32(&reg, TXRX_CSR4_AUTORESPOND_PREAMBLE,
72810379 635 !!erp->short_preamble);
95ea3627 636 rt2x00pci_register_write(rt2x00dev, TXRX_CSR4, reg);
95ea3627 637
e4ea1c40 638 rt2x00pci_register_write(rt2x00dev, TXRX_CSR5, erp->basic_rates);
95ea3627 639
e4ea1c40
ID		 640 rt2x00pci_register_read(rt2x00dev, MAC_CSR9, &reg);
641 rt2x00_set_field32(&reg, MAC_CSR9_SLOT_TIME, erp->slot_time);
642 rt2x00pci_register_write(rt2x00dev, MAC_CSR9, reg);
95ea3627 643
e4ea1c40
ID		 644 rt2x00pci_register_read(rt2x00dev, MAC_CSR8, &reg);
645 rt2x00_set_field32(&reg, MAC_CSR8_SIFS, erp->sifs);
646 rt2x00_set_field32(&reg, MAC_CSR8_SIFS_AFTER_RX_OFDM, 3);
647 rt2x00_set_field32(&reg, MAC_CSR8_EIFS, erp->eifs);
648 rt2x00pci_register_write(rt2x00dev, MAC_CSR8, reg);
95ea3627
ID		 649}
650
651static void rt61pci_config_antenna_5x(struct rt2x00_dev *rt2x00dev,
addc81bd 652 struct antenna_setup *ant)
95ea3627
ID		 653{
654 u8 r3;
655 u8 r4;
656 u8 r77;
657
658 rt61pci_bbp_read(rt2x00dev, 3, &r3);
659 rt61pci_bbp_read(rt2x00dev, 4, &r4);
660 rt61pci_bbp_read(rt2x00dev, 77, &r77);
661
662 rt2x00_set_field8(&r3, BBP_R3_SMART_MODE,
acaa410d 663 rt2x00_rf(&rt2x00dev->chip, RF5325));
e4cd2ff8
ID		 664
665 /*
666 * Configure the RX antenna.
667 */
addc81bd 668 switch (ant->rx) {
95ea3627 669 case ANTENNA_HW_DIVERSITY:
acaa410d 670 rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA_CONTROL, 2);
95ea3627 671 rt2x00_set_field8(&r4, BBP_R4_RX_FRAME_END,
8318d78a 672 (rt2x00dev->curr_band != IEEE80211_BAND_5GHZ));
95ea3627
ID		 673 break;
674 case ANTENNA_A:
acaa410d 675 rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA_CONTROL, 1);
95ea3627 676 rt2x00_set_field8(&r4, BBP_R4_RX_FRAME_END, 0);
8318d78a 677 if (rt2x00dev->curr_band == IEEE80211_BAND_5GHZ)
acaa410d
MN		 678 rt2x00_set_field8(&r77, BBP_R77_RX_ANTENNA, 0);
679 else
680 rt2x00_set_field8(&r77, BBP_R77_RX_ANTENNA, 3);
95ea3627
ID		 681 break;
682 case ANTENNA_B:
a4fe07d9 683 default:
acaa410d 684 rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA_CONTROL, 1);
95ea3627 685 rt2x00_set_field8(&r4, BBP_R4_RX_FRAME_END, 0);
8318d78a 686 if (rt2x00dev->curr_band == IEEE80211_BAND_5GHZ)
acaa410d
MN		 687 rt2x00_set_field8(&r77, BBP_R77_RX_ANTENNA, 3);
688 else
689 rt2x00_set_field8(&r77, BBP_R77_RX_ANTENNA, 0);
95ea3627
ID		 690 break;
691 }
692
693 rt61pci_bbp_write(rt2x00dev, 77, r77);
694 rt61pci_bbp_write(rt2x00dev, 3, r3);
695 rt61pci_bbp_write(rt2x00dev, 4, r4);
696}
697
698static void rt61pci_config_antenna_2x(struct rt2x00_dev *rt2x00dev,
addc81bd 699 struct antenna_setup *ant)
95ea3627
ID		 700{
701 u8 r3;
702 u8 r4;
703 u8 r77;
704
705 rt61pci_bbp_read(rt2x00dev, 3, &r3);
706 rt61pci_bbp_read(rt2x00dev, 4, &r4);
707 rt61pci_bbp_read(rt2x00dev, 77, &r77);
708
709 rt2x00_set_field8(&r3, BBP_R3_SMART_MODE,
acaa410d 710 rt2x00_rf(&rt2x00dev->chip, RF2529));
95ea3627
ID		 711 rt2x00_set_field8(&r4, BBP_R4_RX_FRAME_END,
712 !test_bit(CONFIG_FRAME_TYPE, &rt2x00dev->flags));
713
e4cd2ff8
ID		 714 /*
715 * Configure the RX antenna.
716 */
addc81bd 717 switch (ant->rx) {
95ea3627 718 case ANTENNA_HW_DIVERSITY:
acaa410d 719 rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA_CONTROL, 2);
95ea3627
ID		 720 break;
721 case ANTENNA_A:
acaa410d
MN		 722 rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA_CONTROL, 1);
723 rt2x00_set_field8(&r77, BBP_R77_RX_ANTENNA, 3);
95ea3627
ID		 724 break;
725 case ANTENNA_B:
a4fe07d9 726 default:
acaa410d
MN		 727 rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA_CONTROL, 1);
728 rt2x00_set_field8(&r77, BBP_R77_RX_ANTENNA, 0);
95ea3627
ID		 729 break;
730 }
731
732 rt61pci_bbp_write(rt2x00dev, 77, r77);
733 rt61pci_bbp_write(rt2x00dev, 3, r3);
734 rt61pci_bbp_write(rt2x00dev, 4, r4);
735}
736
737static void rt61pci_config_antenna_2529_rx(struct rt2x00_dev *rt2x00dev,
738 const int p1, const int p2)
739{
740 u32 reg;
741
742 rt2x00pci_register_read(rt2x00dev, MAC_CSR13, &reg);
743
acaa410d
MN		 744 rt2x00_set_field32(&reg, MAC_CSR13_BIT4, p1);
745 rt2x00_set_field32(&reg, MAC_CSR13_BIT12, 0);
746
747 rt2x00_set_field32(&reg, MAC_CSR13_BIT3, !p2);
748 rt2x00_set_field32(&reg, MAC_CSR13_BIT11, 0);
749
750 rt2x00pci_register_write(rt2x00dev, MAC_CSR13, reg);
95ea3627
ID		 751}
752
753static void rt61pci_config_antenna_2529(struct rt2x00_dev *rt2x00dev,
addc81bd 754 struct antenna_setup *ant)
95ea3627 755{
95ea3627
ID		 756 u8 r3;
757 u8 r4;
758 u8 r77;
759
760 rt61pci_bbp_read(rt2x00dev, 3, &r3);
761 rt61pci_bbp_read(rt2x00dev, 4, &r4);
762 rt61pci_bbp_read(rt2x00dev, 77, &r77);
e4cd2ff8 763
e4cd2ff8
ID		 764 /*
765 * Configure the RX antenna.
766 */
767 switch (ant->rx) {
768 case ANTENNA_A:
acaa410d
MN		 769 rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA_CONTROL, 1);
770 rt2x00_set_field8(&r77, BBP_R77_RX_ANTENNA, 0);
771 rt61pci_config_antenna_2529_rx(rt2x00dev, 0, 0);
e4cd2ff8 772 break;
e4cd2ff8
ID		 773 case ANTENNA_HW_DIVERSITY:
774 /*
a4fe07d9
ID		 775 * FIXME: Antenna selection for the rf 2529 is very confusing
776 * in the legacy driver. Just default to antenna B until the
777 * legacy code can be properly translated into rt2x00 code.
e4cd2ff8
ID		 778 */
779 case ANTENNA_B:
a4fe07d9 780 default:
acaa410d
MN		 781 rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA_CONTROL, 1);
782 rt2x00_set_field8(&r77, BBP_R77_RX_ANTENNA, 3);
783 rt61pci_config_antenna_2529_rx(rt2x00dev, 1, 1);
e4cd2ff8
ID		 784 break;
785 }
786
e4cd2ff8 787 rt61pci_bbp_write(rt2x00dev, 77, r77);
95ea3627
ID		 788 rt61pci_bbp_write(rt2x00dev, 3, r3);
789 rt61pci_bbp_write(rt2x00dev, 4, r4);
790}
791
792struct antenna_sel {
793 u8 word;
794 /*
795 * value[0] -> non-LNA
796 * value[1] -> LNA
797 */
798 u8 value[2];
799};
800
801static const struct antenna_sel antenna_sel_a[] = {
802 { 96, { 0x58, 0x78 } },
803 { 104, { 0x38, 0x48 } },
804 { 75, { 0xfe, 0x80 } },
805 { 86, { 0xfe, 0x80 } },
806 { 88, { 0xfe, 0x80 } },
807 { 35, { 0x60, 0x60 } },
808 { 97, { 0x58, 0x58 } },
809 { 98, { 0x58, 0x58 } },
810};
811
812static const struct antenna_sel antenna_sel_bg[] = {
813 { 96, { 0x48, 0x68 } },
814 { 104, { 0x2c, 0x3c } },
815 { 75, { 0xfe, 0x80 } },
816 { 86, { 0xfe, 0x80 } },
817 { 88, { 0xfe, 0x80 } },
818 { 35, { 0x50, 0x50 } },
819 { 97, { 0x48, 0x48 } },
820 { 98, { 0x48, 0x48 } },
821};
822
e4ea1c40
ID		 823static void rt61pci_config_ant(struct rt2x00_dev *rt2x00dev,
824 struct antenna_setup *ant)
95ea3627
ID		 825{
826 const struct antenna_sel *sel;
827 unsigned int lna;
828 unsigned int i;
829 u32 reg;
830
a4fe07d9
ID		 831 /*
832 * We should never come here because rt2x00lib is supposed
833 * to catch this and send us the correct antenna explicitely.
834 */
835 BUG_ON(ant->rx == ANTENNA_SW_DIVERSITY ||
836 ant->tx == ANTENNA_SW_DIVERSITY);
837
8318d78a 838 if (rt2x00dev->curr_band == IEEE80211_BAND_5GHZ) {
95ea3627
ID		 839 sel = antenna_sel_a;
840 lna = test_bit(CONFIG_EXTERNAL_LNA_A, &rt2x00dev->flags);
95ea3627
ID		 841 } else {
842 sel = antenna_sel_bg;
843 lna = test_bit(CONFIG_EXTERNAL_LNA_BG, &rt2x00dev->flags);
95ea3627
ID		 844 }
845
acaa410d
MN		 846 for (i = 0; i < ARRAY_SIZE(antenna_sel_a); i++)
847 rt61pci_bbp_write(rt2x00dev, sel[i].word, sel[i].value[lna]);
848
849 rt2x00pci_register_read(rt2x00dev, PHY_CSR0, &reg);
850
ddc827f9 851 rt2x00_set_field32(&reg, PHY_CSR0_PA_PE_BG,
8318d78a 852 rt2x00dev->curr_band == IEEE80211_BAND_2GHZ);
ddc827f9 853 rt2x00_set_field32(&reg, PHY_CSR0_PA_PE_A,
8318d78a 854 rt2x00dev->curr_band == IEEE80211_BAND_5GHZ);
ddc827f9 855
95ea3627
ID		 856 rt2x00pci_register_write(rt2x00dev, PHY_CSR0, reg);
857
858 if (rt2x00_rf(&rt2x00dev->chip, RF5225) ||
859 rt2x00_rf(&rt2x00dev->chip, RF5325))
addc81bd 860 rt61pci_config_antenna_5x(rt2x00dev, ant);
95ea3627 861 else if (rt2x00_rf(&rt2x00dev->chip, RF2527))
addc81bd 862 rt61pci_config_antenna_2x(rt2x00dev, ant);
95ea3627
ID		 863 else if (rt2x00_rf(&rt2x00dev->chip, RF2529)) {
864 if (test_bit(CONFIG_DOUBLE_ANTENNA, &rt2x00dev->flags))
addc81bd 865 rt61pci_config_antenna_2x(rt2x00dev, ant);
95ea3627 866 else
addc81bd 867 rt61pci_config_antenna_2529(rt2x00dev, ant);
95ea3627
ID		 868 }
869}
870
e4ea1c40
ID		 871static void rt61pci_config_lna_gain(struct rt2x00_dev *rt2x00dev,
872 struct rt2x00lib_conf *libconf)
873{
874 u16 eeprom;
875 short lna_gain = 0;
876
877 if (libconf->conf->channel->band == IEEE80211_BAND_2GHZ) {
878 if (test_bit(CONFIG_EXTERNAL_LNA_BG, &rt2x00dev->flags))
879 lna_gain += 14;
880
881 rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_OFFSET_BG, &eeprom);
882 lna_gain -= rt2x00_get_field16(eeprom, EEPROM_RSSI_OFFSET_BG_1);
883 } else {
884 if (test_bit(CONFIG_EXTERNAL_LNA_A, &rt2x00dev->flags))
885 lna_gain += 14;
886
887 rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_OFFSET_A, &eeprom);
888 lna_gain -= rt2x00_get_field16(eeprom, EEPROM_RSSI_OFFSET_A_1);
889 }
890
891 rt2x00dev->lna_gain = lna_gain;
892}
893
894static void rt61pci_config_channel(struct rt2x00_dev *rt2x00dev,
895 struct rf_channel *rf, const int txpower)
896{
897 u8 r3;
898 u8 r94;
899 u8 smart;
900
901 rt2x00_set_field32(&rf->rf3, RF3_TXPOWER, TXPOWER_TO_DEV(txpower));
902 rt2x00_set_field32(&rf->rf4, RF4_FREQ_OFFSET, rt2x00dev->freq_offset);
903
904 smart = !(rt2x00_rf(&rt2x00dev->chip, RF5225) ||
905 rt2x00_rf(&rt2x00dev->chip, RF2527));
906
907 rt61pci_bbp_read(rt2x00dev, 3, &r3);
908 rt2x00_set_field8(&r3, BBP_R3_SMART_MODE, smart);
909 rt61pci_bbp_write(rt2x00dev, 3, r3);
910
911 r94 = 6;
912 if (txpower > MAX_TXPOWER && txpower <= (MAX_TXPOWER + r94))
913 r94 += txpower - MAX_TXPOWER;
914 else if (txpower < MIN_TXPOWER && txpower >= (MIN_TXPOWER - r94))
915 r94 += txpower;
916 rt61pci_bbp_write(rt2x00dev, 94, r94);
917
918 rt61pci_rf_write(rt2x00dev, 1, rf->rf1);
919 rt61pci_rf_write(rt2x00dev, 2, rf->rf2);
920 rt61pci_rf_write(rt2x00dev, 3, rf->rf3 & ~0x00000004);
921 rt61pci_rf_write(rt2x00dev, 4, rf->rf4);
922
923 udelay(200);
924
925 rt61pci_rf_write(rt2x00dev, 1, rf->rf1);
926 rt61pci_rf_write(rt2x00dev, 2, rf->rf2);
927 rt61pci_rf_write(rt2x00dev, 3, rf->rf3 | 0x00000004);
928 rt61pci_rf_write(rt2x00dev, 4, rf->rf4);
929
930 udelay(200);
931
932 rt61pci_rf_write(rt2x00dev, 1, rf->rf1);
933 rt61pci_rf_write(rt2x00dev, 2, rf->rf2);
934 rt61pci_rf_write(rt2x00dev, 3, rf->rf3 & ~0x00000004);
935 rt61pci_rf_write(rt2x00dev, 4, rf->rf4);
936
937 msleep(1);
938}
939
940static void rt61pci_config_txpower(struct rt2x00_dev *rt2x00dev,
941 const int txpower)
942{
943 struct rf_channel rf;
944
945 rt2x00_rf_read(rt2x00dev, 1, &rf.rf1);
946 rt2x00_rf_read(rt2x00dev, 2, &rf.rf2);
947 rt2x00_rf_read(rt2x00dev, 3, &rf.rf3);
948 rt2x00_rf_read(rt2x00dev, 4, &rf.rf4);
949
950 rt61pci_config_channel(rt2x00dev, &rf, txpower);
951}
952
953static void rt61pci_config_retry_limit(struct rt2x00_dev *rt2x00dev,
5c58ee51 954 struct rt2x00lib_conf *libconf)
95ea3627
ID		 955{
956 u32 reg;
957
e4ea1c40
ID		 958 rt2x00pci_register_read(rt2x00dev, TXRX_CSR4, &reg);
959 rt2x00_set_field32(&reg, TXRX_CSR4_LONG_RETRY_LIMIT,
960 libconf->conf->long_frame_max_tx_count);
961 rt2x00_set_field32(&reg, TXRX_CSR4_SHORT_RETRY_LIMIT,
962 libconf->conf->short_frame_max_tx_count);
963 rt2x00pci_register_write(rt2x00dev, TXRX_CSR4, reg);
964}
95ea3627 965
e4ea1c40
ID		 966static void rt61pci_config_duration(struct rt2x00_dev *rt2x00dev,
967 struct rt2x00lib_conf *libconf)
968{
969 u32 reg;
95ea3627
ID		 970
971 rt2x00pci_register_read(rt2x00dev, TXRX_CSR0, &reg);
972 rt2x00_set_field32(&reg, TXRX_CSR0_TSF_OFFSET, IEEE80211_HEADER);
973 rt2x00pci_register_write(rt2x00dev, TXRX_CSR0, reg);
974
975 rt2x00pci_register_read(rt2x00dev, TXRX_CSR4, &reg);
976 rt2x00_set_field32(&reg, TXRX_CSR4_AUTORESPOND_ENABLE, 1);
977 rt2x00pci_register_write(rt2x00dev, TXRX_CSR4, reg);
978
979 rt2x00pci_register_read(rt2x00dev, TXRX_CSR9, &reg);
5c58ee51
ID		 980 rt2x00_set_field32(&reg, TXRX_CSR9_BEACON_INTERVAL,
981 libconf->conf->beacon_int * 16);
95ea3627
ID		 982 rt2x00pci_register_write(rt2x00dev, TXRX_CSR9, reg);
983}
984
985static void rt61pci_config(struct rt2x00_dev *rt2x00dev,
6bb40dd1
ID		 986 struct rt2x00lib_conf *libconf,
987 const unsigned int flags)
95ea3627 988{
ba2ab471
ID		 989 /* Always recalculate LNA gain before changing configuration */
990 rt61pci_config_lna_gain(rt2x00dev, libconf);
991
e4ea1c40 992 if (flags & IEEE80211_CONF_CHANGE_CHANNEL)
5c58ee51
ID		 993 rt61pci_config_channel(rt2x00dev, &libconf->rf,
994 libconf->conf->power_level);
e4ea1c40
ID		 995 if ((flags & IEEE80211_CONF_CHANGE_POWER) &&
996 !(flags & IEEE80211_CONF_CHANGE_CHANNEL))
5c58ee51 997 rt61pci_config_txpower(rt2x00dev, libconf->conf->power_level);
e4ea1c40
ID		 998 if (flags & IEEE80211_CONF_CHANGE_RETRY_LIMITS)
999 rt61pci_config_retry_limit(rt2x00dev, libconf);
1000 if (flags & IEEE80211_CONF_CHANGE_BEACON_INTERVAL)
5c58ee51 1001 rt61pci_config_duration(rt2x00dev, libconf);
95ea3627
ID		 1002}
1003
95ea3627
ID		 1004/*
1005 * Link tuning
1006 */
ebcf26da
ID		 1007static void rt61pci_link_stats(struct rt2x00_dev *rt2x00dev,
1008 struct link_qual *qual)
95ea3627
ID		 1009{
1010 u32 reg;
1011
1012 /*
1013 * Update FCS error count from register.
1014 */
1015 rt2x00pci_register_read(rt2x00dev, STA_CSR0, &reg);
ebcf26da 1016 qual->rx_failed = rt2x00_get_field32(reg, STA_CSR0_FCS_ERROR);
95ea3627
ID		 1017
1018 /*
1019 * Update False CCA count from register.
1020 */
1021 rt2x00pci_register_read(rt2x00dev, STA_CSR1, &reg);
ebcf26da 1022 qual->false_cca = rt2x00_get_field32(reg, STA_CSR1_FALSE_CCA_ERROR);
95ea3627
ID		 1023}
1024
1025static void rt61pci_reset_tuner(struct rt2x00_dev *rt2x00dev)
1026{
1027 rt61pci_bbp_write(rt2x00dev, 17, 0x20);
1028 rt2x00dev->link.vgc_level = 0x20;
1029}
1030
1031static void rt61pci_link_tuner(struct rt2x00_dev *rt2x00dev)
1032{
1033 int rssi = rt2x00_get_link_rssi(&rt2x00dev->link);
1034 u8 r17;
1035 u8 up_bound;
1036 u8 low_bound;
1037
95ea3627
ID		 1038 rt61pci_bbp_read(rt2x00dev, 17, &r17);
1039
1040 /*
1041 * Determine r17 bounds.
1042 */
1497074a 1043 if (rt2x00dev->rx_status.band == IEEE80211_BAND_5GHZ) {
95ea3627
ID		 1044 low_bound = 0x28;
1045 up_bound = 0x48;
1046 if (test_bit(CONFIG_EXTERNAL_LNA_A, &rt2x00dev->flags)) {
1047 low_bound += 0x10;
1048 up_bound += 0x10;
1049 }
1050 } else {
1051 low_bound = 0x20;
1052 up_bound = 0x40;
1053 if (test_bit(CONFIG_EXTERNAL_LNA_BG, &rt2x00dev->flags)) {
1054 low_bound += 0x10;
1055 up_bound += 0x10;
1056 }
1057 }
1058
6bb40dd1
ID		 1059 /*
1060 * If we are not associated, we should go straight to the
1061 * dynamic CCA tuning.
1062 */
1063 if (!rt2x00dev->intf_associated)
1064 goto dynamic_cca_tune;
1065
95ea3627
ID		 1066 /*
1067 * Special big-R17 for very short distance
1068 */
1069 if (rssi >= -35) {
1070 if (r17 != 0x60)
1071 rt61pci_bbp_write(rt2x00dev, 17, 0x60);
1072 return;
1073 }
1074
1075 /*
1076 * Special big-R17 for short distance
1077 */
1078 if (rssi >= -58) {
1079 if (r17 != up_bound)
1080 rt61pci_bbp_write(rt2x00dev, 17, up_bound);
1081 return;
1082 }
1083
1084 /*
1085 * Special big-R17 for middle-short distance
1086 */
1087 if (rssi >= -66) {
1088 low_bound += 0x10;
1089 if (r17 != low_bound)
1090 rt61pci_bbp_write(rt2x00dev, 17, low_bound);
1091 return;
1092 }
1093
1094 /*
1095 * Special mid-R17 for middle distance
1096 */
1097 if (rssi >= -74) {
1098 low_bound += 0x08;
1099 if (r17 != low_bound)
1100 rt61pci_bbp_write(rt2x00dev, 17, low_bound);
1101 return;
1102 }
1103
1104 /*
1105 * Special case: Change up_bound based on the rssi.
1106 * Lower up_bound when rssi is weaker then -74 dBm.
1107 */
1108 up_bound -= 2 * (-74 - rssi);
1109 if (low_bound > up_bound)
1110 up_bound = low_bound;
1111
1112 if (r17 > up_bound) {
1113 rt61pci_bbp_write(rt2x00dev, 17, up_bound);
1114 return;
1115 }
1116
6bb40dd1
ID		 1117dynamic_cca_tune:
1118
95ea3627
ID		 1119 /*
1120 * r17 does not yet exceed upper limit, continue and base
1121 * the r17 tuning on the false CCA count.
1122 */
ebcf26da 1123 if (rt2x00dev->link.qual.false_cca > 512 && r17 < up_bound) {
95ea3627
ID		 1124 if (++r17 > up_bound)
1125 r17 = up_bound;
1126 rt61pci_bbp_write(rt2x00dev, 17, r17);
ebcf26da 1127 } else if (rt2x00dev->link.qual.false_cca < 100 && r17 > low_bound) {
95ea3627
ID		 1128 if (--r17 < low_bound)
1129 r17 = low_bound;
1130 rt61pci_bbp_write(rt2x00dev, 17, r17);
1131 }
1132}
1133
1134/*
a7f3a06c 1135 * Firmware functions
95ea3627
ID		 1136 */
1137static char *rt61pci_get_firmware_name(struct rt2x00_dev *rt2x00dev)
1138{
1139 char *fw_name;
1140
1141 switch (rt2x00dev->chip.rt) {
1142 case RT2561:
1143 fw_name = FIRMWARE_RT2561;
1144 break;
1145 case RT2561s:
1146 fw_name = FIRMWARE_RT2561s;
1147 break;
1148 case RT2661:
1149 fw_name = FIRMWARE_RT2661;
1150 break;
1151 default:
1152 fw_name = NULL;
1153 break;
1154 }
1155
1156 return fw_name;
1157}
1158
f160ebcb 1159static u16 rt61pci_get_firmware_crc(const void *data, const size_t len)
a7f3a06c
ID		 1160{
1161 u16 crc;
1162
1163 /*
1164 * Use the crc itu-t algorithm.
1165 * The last 2 bytes in the firmware array are the crc checksum itself,
1166 * this means that we should never pass those 2 bytes to the crc
1167 * algorithm.
1168 */
1169 crc = crc_itu_t(0, data, len - 2);
1170 crc = crc_itu_t_byte(crc, 0);
1171 crc = crc_itu_t_byte(crc, 0);
1172
1173 return crc;
1174}
1175
f160ebcb 1176static int rt61pci_load_firmware(struct rt2x00_dev *rt2x00dev, const void *data,
95ea3627
ID		 1177 const size_t len)
1178{
1179 int i;
1180 u32 reg;
1181
1182 /*
1183 * Wait for stable hardware.
1184 */
1185 for (i = 0; i < 100; i++) {
1186 rt2x00pci_register_read(rt2x00dev, MAC_CSR0, &reg);
1187 if (reg)
1188 break;
1189 msleep(1);
1190 }
1191
1192 if (!reg) {
1193 ERROR(rt2x00dev, "Unstable hardware.\n");
1194 return -EBUSY;
1195 }
1196
1197 /*
1198 * Prepare MCU and mailbox for firmware loading.
1199 */
1200 reg = 0;
1201 rt2x00_set_field32(&reg, MCU_CNTL_CSR_RESET, 1);
1202 rt2x00pci_register_write(rt2x00dev, MCU_CNTL_CSR, reg);
1203 rt2x00pci_register_write(rt2x00dev, M2H_CMD_DONE_CSR, 0xffffffff);
1204 rt2x00pci_register_write(rt2x00dev, H2M_MAILBOX_CSR, 0);
1205 rt2x00pci_register_write(rt2x00dev, HOST_CMD_CSR, 0);
1206
1207 /*
1208 * Write firmware to device.
1209 */
1210 reg = 0;
1211 rt2x00_set_field32(&reg, MCU_CNTL_CSR_RESET, 1);
1212 rt2x00_set_field32(&reg, MCU_CNTL_CSR_SELECT_BANK, 1);
1213 rt2x00pci_register_write(rt2x00dev, MCU_CNTL_CSR, reg);
1214
1215 rt2x00pci_register_multiwrite(rt2x00dev, FIRMWARE_IMAGE_BASE,
1216 data, len);
1217
1218 rt2x00_set_field32(&reg, MCU_CNTL_CSR_SELECT_BANK, 0);
1219 rt2x00pci_register_write(rt2x00dev, MCU_CNTL_CSR, reg);
1220
1221 rt2x00_set_field32(&reg, MCU_CNTL_CSR_RESET, 0);
1222 rt2x00pci_register_write(rt2x00dev, MCU_CNTL_CSR, reg);
1223
1224 for (i = 0; i < 100; i++) {
1225 rt2x00pci_register_read(rt2x00dev, MCU_CNTL_CSR, &reg);
1226 if (rt2x00_get_field32(reg, MCU_CNTL_CSR_READY))
1227 break;
1228 msleep(1);
1229 }
1230
1231 if (i == 100) {
1232 ERROR(rt2x00dev, "MCU Control register not ready.\n");
1233 return -EBUSY;
1234 }
1235
e6d3e902
ID		 1236 /*
1237 * Hardware needs another millisecond before it is ready.
1238 */
1239 msleep(1);
1240
95ea3627
ID		 1241 /*
1242 * Reset MAC and BBP registers.
1243 */
1244 reg = 0;
1245 rt2x00_set_field32(&reg, MAC_CSR1_SOFT_RESET, 1);
1246 rt2x00_set_field32(&reg, MAC_CSR1_BBP_RESET, 1);
1247 rt2x00pci_register_write(rt2x00dev, MAC_CSR1, reg);
1248
1249 rt2x00pci_register_read(rt2x00dev, MAC_CSR1, &reg);
1250 rt2x00_set_field32(&reg, MAC_CSR1_SOFT_RESET, 0);
1251 rt2x00_set_field32(&reg, MAC_CSR1_BBP_RESET, 0);
1252 rt2x00pci_register_write(rt2x00dev, MAC_CSR1, reg);
1253
1254 rt2x00pci_register_read(rt2x00dev, MAC_CSR1, &reg);
1255 rt2x00_set_field32(&reg, MAC_CSR1_HOST_READY, 1);
1256 rt2x00pci_register_write(rt2x00dev, MAC_CSR1, reg);
1257
1258 return 0;
1259}
1260
a7f3a06c
ID		 1261/*
1262 * Initialization functions.
1263 */
837e7f24 1264static void rt61pci_init_rxentry(struct rt2x00_dev *rt2x00dev,
181d6902 1265 struct queue_entry *entry)
95ea3627 1266{
b8be63ff 1267 struct queue_entry_priv_pci *entry_priv = entry->priv_data;
c4da0048 1268 struct skb_frame_desc *skbdesc = get_skb_frame_desc(entry->skb);
95ea3627
ID		 1269 u32 word;
1270
b8be63ff 1271 rt2x00_desc_read(entry_priv->desc, 5, &word);
30b3a23c 1272 rt2x00_set_field32(&word, RXD_W5_BUFFER_PHYSICAL_ADDRESS,
c4da0048 1273 skbdesc->skb_dma);
b8be63ff 1274 rt2x00_desc_write(entry_priv->desc, 5, word);
95ea3627 1275
b8be63ff 1276 rt2x00_desc_read(entry_priv->desc, 0, &word);
837e7f24 1277 rt2x00_set_field32(&word, RXD_W0_OWNER_NIC, 1);
b8be63ff 1278 rt2x00_desc_write(entry_priv->desc, 0, word);
95ea3627
ID		 1279}
1280
837e7f24 1281static void rt61pci_init_txentry(struct rt2x00_dev *rt2x00dev,
181d6902 1282 struct queue_entry *entry)
95ea3627 1283{
b8be63ff 1284 struct queue_entry_priv_pci *entry_priv = entry->priv_data;
95ea3627
ID		 1285 u32 word;
1286
b8be63ff 1287 rt2x00_desc_read(entry_priv->desc, 0, &word);
837e7f24
ID		 1288 rt2x00_set_field32(&word, TXD_W0_VALID, 0);
1289 rt2x00_set_field32(&word, TXD_W0_OWNER_NIC, 0);
b8be63ff 1290 rt2x00_desc_write(entry_priv->desc, 0, word);
95ea3627
ID		 1291}
1292
181d6902 1293static int rt61pci_init_queues(struct rt2x00_dev *rt2x00dev)
95ea3627 1294{
b8be63ff 1295 struct queue_entry_priv_pci *entry_priv;
95ea3627
ID		 1296 u32 reg;
1297
95ea3627
ID		 1298 /*
1299 * Initialize registers.
1300 */
1301 rt2x00pci_register_read(rt2x00dev, TX_RING_CSR0, &reg);
1302 rt2x00_set_field32(&reg, TX_RING_CSR0_AC0_RING_SIZE,
181d6902 1303 rt2x00dev->tx[0].limit);
95ea3627 1304 rt2x00_set_field32(&reg, TX_RING_CSR0_AC1_RING_SIZE,
181d6902 1305 rt2x00dev->tx[1].limit);
95ea3627 1306 rt2x00_set_field32(&reg, TX_RING_CSR0_AC2_RING_SIZE,
181d6902 1307 rt2x00dev->tx[2].limit);
95ea3627 1308 rt2x00_set_field32(&reg, TX_RING_CSR0_AC3_RING_SIZE,
181d6902 1309 rt2x00dev->tx[3].limit);
95ea3627
ID		 1310 rt2x00pci_register_write(rt2x00dev, TX_RING_CSR0, reg);
1311
1312 rt2x00pci_register_read(rt2x00dev, TX_RING_CSR1, &reg);
95ea3627 1313 rt2x00_set_field32(&reg, TX_RING_CSR1_TXD_SIZE,
181d6902 1314 rt2x00dev->tx[0].desc_size / 4);
95ea3627
ID		 1315 rt2x00pci_register_write(rt2x00dev, TX_RING_CSR1, reg);
1316
b8be63ff 1317 entry_priv = rt2x00dev->tx[0].entries[0].priv_data;
95ea3627 1318 rt2x00pci_register_read(rt2x00dev, AC0_BASE_CSR, &reg);
30b3a23c 1319 rt2x00_set_field32(&reg, AC0_BASE_CSR_RING_REGISTER,
b8be63ff 1320 entry_priv->desc_dma);
95ea3627
ID		 1321 rt2x00pci_register_write(rt2x00dev, AC0_BASE_CSR, reg);
1322
b8be63ff 1323 entry_priv = rt2x00dev->tx[1].entries[0].priv_data;
95ea3627 1324 rt2x00pci_register_read(rt2x00dev, AC1_BASE_CSR, &reg);
30b3a23c 1325 rt2x00_set_field32(&reg, AC1_BASE_CSR_RING_REGISTER,
b8be63ff 1326 entry_priv->desc_dma);
95ea3627
ID		 1327 rt2x00pci_register_write(rt2x00dev, AC1_BASE_CSR, reg);
1328
b8be63ff 1329 entry_priv = rt2x00dev->tx[2].entries[0].priv_data;
95ea3627 1330 rt2x00pci_register_read(rt2x00dev, AC2_BASE_CSR, &reg);
30b3a23c 1331 rt2x00_set_field32(&reg, AC2_BASE_CSR_RING_REGISTER,
b8be63ff 1332 entry_priv->desc_dma);
95ea3627
ID		 1333 rt2x00pci_register_write(rt2x00dev, AC2_BASE_CSR, reg);
1334
b8be63ff 1335 entry_priv = rt2x00dev->tx[3].entries[0].priv_data;
95ea3627 1336 rt2x00pci_register_read(rt2x00dev, AC3_BASE_CSR, &reg);
30b3a23c 1337 rt2x00_set_field32(&reg, AC3_BASE_CSR_RING_REGISTER,
b8be63ff 1338 entry_priv->desc_dma);
95ea3627
ID		 1339 rt2x00pci_register_write(rt2x00dev, AC3_BASE_CSR, reg);
1340
95ea3627 1341 rt2x00pci_register_read(rt2x00dev, RX_RING_CSR, &reg);
181d6902 1342 rt2x00_set_field32(&reg, RX_RING_CSR_RING_SIZE, rt2x00dev->rx->limit);
95ea3627
ID		 1343 rt2x00_set_field32(&reg, RX_RING_CSR_RXD_SIZE,
1344 rt2x00dev->rx->desc_size / 4);
1345 rt2x00_set_field32(&reg, RX_RING_CSR_RXD_WRITEBACK_SIZE, 4);
1346 rt2x00pci_register_write(rt2x00dev, RX_RING_CSR, reg);
1347
b8be63ff 1348 entry_priv = rt2x00dev->rx->entries[0].priv_data;
95ea3627 1349 rt2x00pci_register_read(rt2x00dev, RX_BASE_CSR, &reg);
30b3a23c 1350 rt2x00_set_field32(&reg, RX_BASE_CSR_RING_REGISTER,
b8be63ff 1351 entry_priv->desc_dma);
95ea3627
ID		 1352 rt2x00pci_register_write(rt2x00dev, RX_BASE_CSR, reg);
1353
1354 rt2x00pci_register_read(rt2x00dev, TX_DMA_DST_CSR, &reg);
1355 rt2x00_set_field32(&reg, TX_DMA_DST_CSR_DEST_AC0, 2);
1356 rt2x00_set_field32(&reg, TX_DMA_DST_CSR_DEST_AC1, 2);
1357 rt2x00_set_field32(&reg, TX_DMA_DST_CSR_DEST_AC2, 2);
1358 rt2x00_set_field32(&reg, TX_DMA_DST_CSR_DEST_AC3, 2);
95ea3627
ID		 1359 rt2x00pci_register_write(rt2x00dev, TX_DMA_DST_CSR, reg);
1360
1361 rt2x00pci_register_read(rt2x00dev, LOAD_TX_RING_CSR, &reg);
1362 rt2x00_set_field32(&reg, LOAD_TX_RING_CSR_LOAD_TXD_AC0, 1);
1363 rt2x00_set_field32(&reg, LOAD_TX_RING_CSR_LOAD_TXD_AC1, 1);
1364 rt2x00_set_field32(&reg, LOAD_TX_RING_CSR_LOAD_TXD_AC2, 1);
1365 rt2x00_set_field32(&reg, LOAD_TX_RING_CSR_LOAD_TXD_AC3, 1);
95ea3627
ID		 1366 rt2x00pci_register_write(rt2x00dev, LOAD_TX_RING_CSR, reg);
1367
1368 rt2x00pci_register_read(rt2x00dev, RX_CNTL_CSR, &reg);
1369 rt2x00_set_field32(&reg, RX_CNTL_CSR_LOAD_RXD, 1);
1370 rt2x00pci_register_write(rt2x00dev, RX_CNTL_CSR, reg);
1371
1372 return 0;
1373}
1374
1375static int rt61pci_init_registers(struct rt2x00_dev *rt2x00dev)
1376{
1377 u32 reg;
1378
1379 rt2x00pci_register_read(rt2x00dev, TXRX_CSR0, &reg);
1380 rt2x00_set_field32(&reg, TXRX_CSR0_AUTO_TX_SEQ, 1);
1381 rt2x00_set_field32(&reg, TXRX_CSR0_DISABLE_RX, 0);
1382 rt2x00_set_field32(&reg, TXRX_CSR0_TX_WITHOUT_WAITING, 0);
1383 rt2x00pci_register_write(rt2x00dev, TXRX_CSR0, reg);
1384
1385 rt2x00pci_register_read(rt2x00dev, TXRX_CSR1, &reg);
1386 rt2x00_set_field32(&reg, TXRX_CSR1_BBP_ID0, 47); /* CCK Signal */
1387 rt2x00_set_field32(&reg, TXRX_CSR1_BBP_ID0_VALID, 1);
1388 rt2x00_set_field32(&reg, TXRX_CSR1_BBP_ID1, 30); /* Rssi */
1389 rt2x00_set_field32(&reg, TXRX_CSR1_BBP_ID1_VALID, 1);
1390 rt2x00_set_field32(&reg, TXRX_CSR1_BBP_ID2, 42); /* OFDM Rate */
1391 rt2x00_set_field32(&reg, TXRX_CSR1_BBP_ID2_VALID, 1);
1392 rt2x00_set_field32(&reg, TXRX_CSR1_BBP_ID3, 30); /* Rssi */
1393 rt2x00_set_field32(&reg, TXRX_CSR1_BBP_ID3_VALID, 1);
1394 rt2x00pci_register_write(rt2x00dev, TXRX_CSR1, reg);
1395
1396 /*
1397 * CCK TXD BBP registers
1398 */
1399 rt2x00pci_register_read(rt2x00dev, TXRX_CSR2, &reg);
1400 rt2x00_set_field32(&reg, TXRX_CSR2_BBP_ID0, 13);
1401 rt2x00_set_field32(&reg, TXRX_CSR2_BBP_ID0_VALID, 1);
1402 rt2x00_set_field32(&reg, TXRX_CSR2_BBP_ID1, 12);
1403 rt2x00_set_field32(&reg, TXRX_CSR2_BBP_ID1_VALID, 1);
1404 rt2x00_set_field32(&reg, TXRX_CSR2_BBP_ID2, 11);
1405 rt2x00_set_field32(&reg, TXRX_CSR2_BBP_ID2_VALID, 1);
1406 rt2x00_set_field32(&reg, TXRX_CSR2_BBP_ID3, 10);
1407 rt2x00_set_field32(&reg, TXRX_CSR2_BBP_ID3_VALID, 1);
1408 rt2x00pci_register_write(rt2x00dev, TXRX_CSR2, reg);
1409
1410 /*
1411 * OFDM TXD BBP registers
1412 */
1413 rt2x00pci_register_read(rt2x00dev, TXRX_CSR3, &reg);
1414 rt2x00_set_field32(&reg, TXRX_CSR3_BBP_ID0, 7);
1415 rt2x00_set_field32(&reg, TXRX_CSR3_BBP_ID0_VALID, 1);
1416 rt2x00_set_field32(&reg, TXRX_CSR3_BBP_ID1, 6);
1417 rt2x00_set_field32(&reg, TXRX_CSR3_BBP_ID1_VALID, 1);
1418 rt2x00_set_field32(&reg, TXRX_CSR3_BBP_ID2, 5);
1419 rt2x00_set_field32(&reg, TXRX_CSR3_BBP_ID2_VALID, 1);
1420 rt2x00pci_register_write(rt2x00dev, TXRX_CSR3, reg);
1421
1422 rt2x00pci_register_read(rt2x00dev, TXRX_CSR7, &reg);
1423 rt2x00_set_field32(&reg, TXRX_CSR7_ACK_CTS_6MBS, 59);
1424 rt2x00_set_field32(&reg, TXRX_CSR7_ACK_CTS_9MBS, 53);
1425 rt2x00_set_field32(&reg, TXRX_CSR7_ACK_CTS_12MBS, 49);
1426 rt2x00_set_field32(&reg, TXRX_CSR7_ACK_CTS_18MBS, 46);
1427 rt2x00pci_register_write(rt2x00dev, TXRX_CSR7, reg);
1428
1429 rt2x00pci_register_read(rt2x00dev, TXRX_CSR8, &reg);
1430 rt2x00_set_field32(&reg, TXRX_CSR8_ACK_CTS_24MBS, 44);
1431 rt2x00_set_field32(&reg, TXRX_CSR8_ACK_CTS_36MBS, 42);
1432 rt2x00_set_field32(&reg, TXRX_CSR8_ACK_CTS_48MBS, 42);
1433 rt2x00_set_field32(&reg, TXRX_CSR8_ACK_CTS_54MBS, 42);
1434 rt2x00pci_register_write(rt2x00dev, TXRX_CSR8, reg);
1435
1f909162
ID		 1436 rt2x00pci_register_read(rt2x00dev, TXRX_CSR9, &reg);
1437 rt2x00_set_field32(&reg, TXRX_CSR9_BEACON_INTERVAL, 0);
1438 rt2x00_set_field32(&reg, TXRX_CSR9_TSF_TICKING, 0);
1439 rt2x00_set_field32(&reg, TXRX_CSR9_TSF_SYNC, 0);
1440 rt2x00_set_field32(&reg, TXRX_CSR9_TBTT_ENABLE, 0);
1441 rt2x00_set_field32(&reg, TXRX_CSR9_BEACON_GEN, 0);
1442 rt2x00_set_field32(&reg, TXRX_CSR9_TIMESTAMP_COMPENSATE, 0);
1443 rt2x00pci_register_write(rt2x00dev, TXRX_CSR9, reg);
1444
95ea3627
ID		 1445 rt2x00pci_register_write(rt2x00dev, TXRX_CSR15, 0x0000000f);
1446
1447 rt2x00pci_register_write(rt2x00dev, MAC_CSR6, 0x00000fff);
1448
1449 rt2x00pci_register_read(rt2x00dev, MAC_CSR9, &reg);
1450 rt2x00_set_field32(&reg, MAC_CSR9_CW_SELECT, 0);
1451 rt2x00pci_register_write(rt2x00dev, MAC_CSR9, reg);
1452
1453 rt2x00pci_register_write(rt2x00dev, MAC_CSR10, 0x0000071c);
1454
1455 if (rt2x00dev->ops->lib->set_device_state(rt2x00dev, STATE_AWAKE))
1456 return -EBUSY;
1457
1458 rt2x00pci_register_write(rt2x00dev, MAC_CSR13, 0x0000e000);
1459
1460 /*
1461 * Invalidate all Shared Keys (SEC_CSR0),
1462 * and clear the Shared key Cipher algorithms (SEC_CSR1 & SEC_CSR5)
1463 */
1464 rt2x00pci_register_write(rt2x00dev, SEC_CSR0, 0x00000000);
1465 rt2x00pci_register_write(rt2x00dev, SEC_CSR1, 0x00000000);
1466 rt2x00pci_register_write(rt2x00dev, SEC_CSR5, 0x00000000);
1467
1468 rt2x00pci_register_write(rt2x00dev, PHY_CSR1, 0x000023b0);
1469 rt2x00pci_register_write(rt2x00dev, PHY_CSR5, 0x060a100c);
1470 rt2x00pci_register_write(rt2x00dev, PHY_CSR6, 0x00080606);
1471 rt2x00pci_register_write(rt2x00dev, PHY_CSR7, 0x00000a08);
1472
1473 rt2x00pci_register_write(rt2x00dev, PCI_CFG_CSR, 0x28ca4404);
1474
1475 rt2x00pci_register_write(rt2x00dev, TEST_MODE_CSR, 0x00000200);
1476
1477 rt2x00pci_register_write(rt2x00dev, M2H_CMD_DONE_CSR, 0xffffffff);
1478
6bb40dd1
ID		 1479 /*
1480 * Clear all beacons
1481 * For the Beacon base registers we only need to clear
1482 * the first byte since that byte contains the VALID and OWNER
1483 * bits which (when set to 0) will invalidate the entire beacon.
1484 */
1485 rt2x00pci_register_write(rt2x00dev, HW_BEACON_BASE0, 0);
1486 rt2x00pci_register_write(rt2x00dev, HW_BEACON_BASE1, 0);
1487 rt2x00pci_register_write(rt2x00dev, HW_BEACON_BASE2, 0);
1488 rt2x00pci_register_write(rt2x00dev, HW_BEACON_BASE3, 0);
1489
95ea3627
ID		 1490 /*
1491 * We must clear the error counters.
1492 * These registers are cleared on read,
1493 * so we may pass a useless variable to store the value.
1494 */
1495 rt2x00pci_register_read(rt2x00dev, STA_CSR0, &reg);
1496 rt2x00pci_register_read(rt2x00dev, STA_CSR1, &reg);
1497 rt2x00pci_register_read(rt2x00dev, STA_CSR2, &reg);
1498
1499 /*
1500 * Reset MAC and BBP registers.
1501 */
1502 rt2x00pci_register_read(rt2x00dev, MAC_CSR1, &reg);
1503 rt2x00_set_field32(&reg, MAC_CSR1_SOFT_RESET, 1);
1504 rt2x00_set_field32(&reg, MAC_CSR1_BBP_RESET, 1);
1505 rt2x00pci_register_write(rt2x00dev, MAC_CSR1, reg);
1506
1507 rt2x00pci_register_read(rt2x00dev, MAC_CSR1, &reg);
1508 rt2x00_set_field32(&reg, MAC_CSR1_SOFT_RESET, 0);
1509 rt2x00_set_field32(&reg, MAC_CSR1_BBP_RESET, 0);
1510 rt2x00pci_register_write(rt2x00dev, MAC_CSR1, reg);
1511
1512 rt2x00pci_register_read(rt2x00dev, MAC_CSR1, &reg);
1513 rt2x00_set_field32(&reg, MAC_CSR1_HOST_READY, 1);
1514 rt2x00pci_register_write(rt2x00dev, MAC_CSR1, reg);
1515
1516 return 0;
1517}
1518
2b08da3f 1519static int rt61pci_wait_bbp_ready(struct rt2x00_dev *rt2x00dev)
95ea3627
ID		 1520{
1521 unsigned int i;
95ea3627
ID		 1522 u8 value;
1523
1524 for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
1525 rt61pci_bbp_read(rt2x00dev, 0, &value);
1526 if ((value != 0xff) && (value != 0x00))
2b08da3f 1527 return 0;
95ea3627
ID		 1528 udelay(REGISTER_BUSY_DELAY);
1529 }
1530
1531 ERROR(rt2x00dev, "BBP register access failed, aborting.\n");
1532 return -EACCES;
2b08da3f
ID		 1533}
1534
1535static int rt61pci_init_bbp(struct rt2x00_dev *rt2x00dev)
1536{
1537 unsigned int i;
1538 u16 eeprom;
1539 u8 reg_id;
1540 u8 value;
1541
1542 if (unlikely(rt61pci_wait_bbp_ready(rt2x00dev)))
1543 return -EACCES;
95ea3627 1544
95ea3627
ID		 1545 rt61pci_bbp_write(rt2x00dev, 3, 0x00);
1546 rt61pci_bbp_write(rt2x00dev, 15, 0x30);
1547 rt61pci_bbp_write(rt2x00dev, 21, 0xc8);
1548 rt61pci_bbp_write(rt2x00dev, 22, 0x38);
1549 rt61pci_bbp_write(rt2x00dev, 23, 0x06);
1550 rt61pci_bbp_write(rt2x00dev, 24, 0xfe);
1551 rt61pci_bbp_write(rt2x00dev, 25, 0x0a);
1552 rt61pci_bbp_write(rt2x00dev, 26, 0x0d);
1553 rt61pci_bbp_write(rt2x00dev, 34, 0x12);
1554 rt61pci_bbp_write(rt2x00dev, 37, 0x07);
1555 rt61pci_bbp_write(rt2x00dev, 39, 0xf8);
1556 rt61pci_bbp_write(rt2x00dev, 41, 0x60);
1557 rt61pci_bbp_write(rt2x00dev, 53, 0x10);
1558 rt61pci_bbp_write(rt2x00dev, 54, 0x18);
1559 rt61pci_bbp_write(rt2x00dev, 60, 0x10);
1560 rt61pci_bbp_write(rt2x00dev, 61, 0x04);
1561 rt61pci_bbp_write(rt2x00dev, 62, 0x04);
1562 rt61pci_bbp_write(rt2x00dev, 75, 0xfe);
1563 rt61pci_bbp_write(rt2x00dev, 86, 0xfe);
1564 rt61pci_bbp_write(rt2x00dev, 88, 0xfe);
1565 rt61pci_bbp_write(rt2x00dev, 90, 0x0f);
1566 rt61pci_bbp_write(rt2x00dev, 99, 0x00);
1567 rt61pci_bbp_write(rt2x00dev, 102, 0x16);
1568 rt61pci_bbp_write(rt2x00dev, 107, 0x04);
1569
95ea3627
ID		 1570 for (i = 0; i < EEPROM_BBP_SIZE; i++) {
1571 rt2x00_eeprom_read(rt2x00dev, EEPROM_BBP_START + i, &eeprom);
1572
1573 if (eeprom != 0xffff && eeprom != 0x0000) {
1574 reg_id = rt2x00_get_field16(eeprom, EEPROM_BBP_REG_ID);
1575 value = rt2x00_get_field16(eeprom, EEPROM_BBP_VALUE);
95ea3627
ID		 1576 rt61pci_bbp_write(rt2x00dev, reg_id, value);
1577 }
1578 }
95ea3627
ID		 1579
1580 return 0;
1581}
1582
1583/*
1584 * Device state switch handlers.
1585 */
1586static void rt61pci_toggle_rx(struct rt2x00_dev *rt2x00dev,
1587 enum dev_state state)
1588{
1589 u32 reg;
1590
1591 rt2x00pci_register_read(rt2x00dev, TXRX_CSR0, &reg);
1592 rt2x00_set_field32(&reg, TXRX_CSR0_DISABLE_RX,
2b08da3f
ID		 1593 (state == STATE_RADIO_RX_OFF) ||
1594 (state == STATE_RADIO_RX_OFF_LINK));
95ea3627
ID		 1595 rt2x00pci_register_write(rt2x00dev, TXRX_CSR0, reg);
1596}
1597
1598static void rt61pci_toggle_irq(struct rt2x00_dev *rt2x00dev,
1599 enum dev_state state)
1600{
1601 int mask = (state == STATE_RADIO_IRQ_OFF);
1602 u32 reg;
1603
1604 /*
1605 * When interrupts are being enabled, the interrupt registers
1606 * should clear the register to assure a clean state.
1607 */
1608 if (state == STATE_RADIO_IRQ_ON) {
1609 rt2x00pci_register_read(rt2x00dev, INT_SOURCE_CSR, &reg);
1610 rt2x00pci_register_write(rt2x00dev, INT_SOURCE_CSR, reg);
1611
1612 rt2x00pci_register_read(rt2x00dev, MCU_INT_SOURCE_CSR, &reg);
1613 rt2x00pci_register_write(rt2x00dev, MCU_INT_SOURCE_CSR, reg);
1614 }
1615
1616 /*
1617 * Only toggle the interrupts bits we are going to use.
1618 * Non-checked interrupt bits are disabled by default.
1619 */
1620 rt2x00pci_register_read(rt2x00dev, INT_MASK_CSR, &reg);
1621 rt2x00_set_field32(&reg, INT_MASK_CSR_TXDONE, mask);
1622 rt2x00_set_field32(&reg, INT_MASK_CSR_RXDONE, mask);
1623 rt2x00_set_field32(&reg, INT_MASK_CSR_ENABLE_MITIGATION, mask);
1624 rt2x00_set_field32(&reg, INT_MASK_CSR_MITIGATION_PERIOD, 0xff);
1625 rt2x00pci_register_write(rt2x00dev, INT_MASK_CSR, reg);
1626
1627 rt2x00pci_register_read(rt2x00dev, MCU_INT_MASK_CSR, &reg);
1628 rt2x00_set_field32(&reg, MCU_INT_MASK_CSR_0, mask);
1629 rt2x00_set_field32(&reg, MCU_INT_MASK_CSR_1, mask);
1630 rt2x00_set_field32(&reg, MCU_INT_MASK_CSR_2, mask);
1631 rt2x00_set_field32(&reg, MCU_INT_MASK_CSR_3, mask);
1632 rt2x00_set_field32(&reg, MCU_INT_MASK_CSR_4, mask);
1633 rt2x00_set_field32(&reg, MCU_INT_MASK_CSR_5, mask);
1634 rt2x00_set_field32(&reg, MCU_INT_MASK_CSR_6, mask);
1635 rt2x00_set_field32(&reg, MCU_INT_MASK_CSR_7, mask);
1636 rt2x00pci_register_write(rt2x00dev, MCU_INT_MASK_CSR, reg);
1637}
1638
1639static int rt61pci_enable_radio(struct rt2x00_dev *rt2x00dev)
1640{
1641 u32 reg;
1642
1643 /*
1644 * Initialize all registers.
1645 */
2b08da3f
ID		 1646 if (unlikely(rt61pci_init_queues(rt2x00dev) ||
1647 rt61pci_init_registers(rt2x00dev) ||
1648 rt61pci_init_bbp(rt2x00dev)))
95ea3627 1649 return -EIO;
95ea3627
ID		 1650
1651 /*
1652 * Enable RX.
1653 */
1654 rt2x00pci_register_read(rt2x00dev, RX_CNTL_CSR, &reg);
1655 rt2x00_set_field32(&reg, RX_CNTL_CSR_ENABLE_RX_DMA, 1);
1656 rt2x00pci_register_write(rt2x00dev, RX_CNTL_CSR, reg);
1657
95ea3627
ID		 1658 return 0;
1659}
1660
1661static void rt61pci_disable_radio(struct rt2x00_dev *rt2x00dev)
1662{
1663 u32 reg;
1664
95ea3627
ID		 1665 rt2x00pci_register_write(rt2x00dev, MAC_CSR10, 0x00001818);
1666
1667 /*
1668 * Disable synchronisation.
1669 */
1670 rt2x00pci_register_write(rt2x00dev, TXRX_CSR9, 0);
1671
1672 /*
1673 * Cancel RX and TX.
1674 */
1675 rt2x00pci_register_read(rt2x00dev, TX_CNTL_CSR, &reg);
1676 rt2x00_set_field32(&reg, TX_CNTL_CSR_ABORT_TX_AC0, 1);
1677 rt2x00_set_field32(&reg, TX_CNTL_CSR_ABORT_TX_AC1, 1);
1678 rt2x00_set_field32(&reg, TX_CNTL_CSR_ABORT_TX_AC2, 1);
1679 rt2x00_set_field32(&reg, TX_CNTL_CSR_ABORT_TX_AC3, 1);
95ea3627 1680 rt2x00pci_register_write(rt2x00dev, TX_CNTL_CSR, reg);
95ea3627
ID		 1681}
1682
1683static int rt61pci_set_state(struct rt2x00_dev *rt2x00dev, enum dev_state state)
1684{
1685 u32 reg;
1686 unsigned int i;
1687 char put_to_sleep;
95ea3627
ID		 1688
1689 put_to_sleep = (state != STATE_AWAKE);
1690
1691 rt2x00pci_register_read(rt2x00dev, MAC_CSR12, &reg);
1692 rt2x00_set_field32(&reg, MAC_CSR12_FORCE_WAKEUP, !put_to_sleep);
1693 rt2x00_set_field32(&reg, MAC_CSR12_PUT_TO_SLEEP, put_to_sleep);
1694 rt2x00pci_register_write(rt2x00dev, MAC_CSR12, reg);
1695
1696 /*
1697 * Device is not guaranteed to be in the requested state yet.
1698 * We must wait until the register indicates that the
1699 * device has entered the correct state.
1700 */
1701 for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
1702 rt2x00pci_register_read(rt2x00dev, MAC_CSR12, &reg);
2b08da3f
ID		 1703 state = rt2x00_get_field32(reg, MAC_CSR12_BBP_CURRENT_STATE);
1704 if (state == !put_to_sleep)
95ea3627
ID		 1705 return 0;
1706 msleep(10);
1707 }
1708
95ea3627
ID		 1709 return -EBUSY;
1710}
1711
1712static int rt61pci_set_device_state(struct rt2x00_dev *rt2x00dev,
1713 enum dev_state state)
1714{
1715 int retval = 0;
1716
1717 switch (state) {
1718 case STATE_RADIO_ON:
1719 retval = rt61pci_enable_radio(rt2x00dev);
1720 break;
1721 case STATE_RADIO_OFF:
1722 rt61pci_disable_radio(rt2x00dev);
1723 break;
1724 case STATE_RADIO_RX_ON:
61667d8d 1725 case STATE_RADIO_RX_ON_LINK:
95ea3627 1726 case STATE_RADIO_RX_OFF:
61667d8d 1727 case STATE_RADIO_RX_OFF_LINK:
2b08da3f
ID		 1728 rt61pci_toggle_rx(rt2x00dev, state);
1729 break;
1730 case STATE_RADIO_IRQ_ON:
1731 case STATE_RADIO_IRQ_OFF:
1732 rt61pci_toggle_irq(rt2x00dev, state);
95ea3627
ID		 1733 break;
1734 case STATE_DEEP_SLEEP:
1735 case STATE_SLEEP:
1736 case STATE_STANDBY:
1737 case STATE_AWAKE:
1738 retval = rt61pci_set_state(rt2x00dev, state);
1739 break;
1740 default:
1741 retval = -ENOTSUPP;
1742 break;
1743 }
1744
2b08da3f
ID		 1745 if (unlikely(retval))
1746 ERROR(rt2x00dev, "Device failed to enter state %d (%d).\n",
1747 state, retval);
1748
95ea3627
ID		 1749 return retval;
1750}
1751
1752/*
1753 * TX descriptor initialization
1754 */
1755static void rt61pci_write_tx_desc(struct rt2x00_dev *rt2x00dev,
61e754f4
ID		 1756 struct sk_buff *skb,
1757 struct txentry_desc *txdesc)
95ea3627 1758{
181d6902 1759 struct skb_frame_desc *skbdesc = get_skb_frame_desc(skb);
dd3193e1 1760 __le32 *txd = skbdesc->desc;
95ea3627
ID		 1761 u32 word;
1762
1763 /*
1764 * Start writing the descriptor words.
1765 */
1766 rt2x00_desc_read(txd, 1, &word);
181d6902
ID		 1767 rt2x00_set_field32(&word, TXD_W1_HOST_Q_ID, txdesc->queue);
1768 rt2x00_set_field32(&word, TXD_W1_AIFSN, txdesc->aifs);
1769 rt2x00_set_field32(&word, TXD_W1_CWMIN, txdesc->cw_min);
1770 rt2x00_set_field32(&word, TXD_W1_CWMAX, txdesc->cw_max);
61e754f4 1771 rt2x00_set_field32(&word, TXD_W1_IV_OFFSET, txdesc->iv_offset);
5adf6d63
ID		 1772 rt2x00_set_field32(&word, TXD_W1_HW_SEQUENCE,
1773 test_bit(ENTRY_TXD_GENERATE_SEQ, &txdesc->flags));
4de36fe5 1774 rt2x00_set_field32(&word, TXD_W1_BUFFER_COUNT, 1);
95ea3627
ID		 1775 rt2x00_desc_write(txd, 1, word);
1776
1777 rt2x00_desc_read(txd, 2, &word);
181d6902
ID		 1778 rt2x00_set_field32(&word, TXD_W2_PLCP_SIGNAL, txdesc->signal);
1779 rt2x00_set_field32(&word, TXD_W2_PLCP_SERVICE, txdesc->service);
1780 rt2x00_set_field32(&word, TXD_W2_PLCP_LENGTH_LOW, txdesc->length_low);
1781 rt2x00_set_field32(&word, TXD_W2_PLCP_LENGTH_HIGH, txdesc->length_high);
95ea3627
ID		 1782 rt2x00_desc_write(txd, 2, word);
1783
61e754f4
ID		 1784 if (test_bit(ENTRY_TXD_ENCRYPT, &txdesc->flags)) {
1785 _rt2x00_desc_write(txd, 3, skbdesc->iv);
1786 _rt2x00_desc_write(txd, 4, skbdesc->eiv);
1787 }
1788
95ea3627 1789 rt2x00_desc_read(txd, 5, &word);
4de36fe5
GW		 1790 rt2x00_set_field32(&word, TXD_W5_PID_TYPE, skbdesc->entry->queue->qid);
1791 rt2x00_set_field32(&word, TXD_W5_PID_SUBTYPE,
1792 skbdesc->entry->entry_idx);
95ea3627 1793 rt2x00_set_field32(&word, TXD_W5_TX_POWER,
ac1aa7e4 1794 TXPOWER_TO_DEV(rt2x00dev->tx_power));
95ea3627
ID		 1795 rt2x00_set_field32(&word, TXD_W5_WAITING_DMA_DONE_INT, 1);
1796 rt2x00_desc_write(txd, 5, word);
1797
4de36fe5
GW		 1798 rt2x00_desc_read(txd, 6, &word);
1799 rt2x00_set_field32(&word, TXD_W6_BUFFER_PHYSICAL_ADDRESS,
c4da0048 1800 skbdesc->skb_dma);
4de36fe5
GW		 1801 rt2x00_desc_write(txd, 6, word);
1802
d7bafff3
AB		 1803 if (skbdesc->desc_len > TXINFO_SIZE) {
1804 rt2x00_desc_read(txd, 11, &word);
d56d453a 1805 rt2x00_set_field32(&word, TXD_W11_BUFFER_LENGTH0, skb->len);
d7bafff3
AB		 1806 rt2x00_desc_write(txd, 11, word);
1807 }
95ea3627
ID		 1808
1809 rt2x00_desc_read(txd, 0, &word);
1810 rt2x00_set_field32(&word, TXD_W0_OWNER_NIC, 1);
1811 rt2x00_set_field32(&word, TXD_W0_VALID, 1);
1812 rt2x00_set_field32(&word, TXD_W0_MORE_FRAG,
181d6902 1813 test_bit(ENTRY_TXD_MORE_FRAG, &txdesc->flags));
95ea3627 1814 rt2x00_set_field32(&word, TXD_W0_ACK,
181d6902 1815 test_bit(ENTRY_TXD_ACK, &txdesc->flags));
95ea3627 1816 rt2x00_set_field32(&word, TXD_W0_TIMESTAMP,
181d6902 1817 test_bit(ENTRY_TXD_REQ_TIMESTAMP, &txdesc->flags));
95ea3627 1818 rt2x00_set_field32(&word, TXD_W0_OFDM,
181d6902
ID		 1819 test_bit(ENTRY_TXD_OFDM_RATE, &txdesc->flags));
1820 rt2x00_set_field32(&word, TXD_W0_IFS, txdesc->ifs);
95ea3627 1821 rt2x00_set_field32(&word, TXD_W0_RETRY_MODE,
61486e0f 1822 test_bit(ENTRY_TXD_RETRY_MODE, &txdesc->flags));
61e754f4
ID		 1823 rt2x00_set_field32(&word, TXD_W0_TKIP_MIC,
1824 test_bit(ENTRY_TXD_ENCRYPT_MMIC, &txdesc->flags));
1825 rt2x00_set_field32(&word, TXD_W0_KEY_TABLE,
1826 test_bit(ENTRY_TXD_ENCRYPT_PAIRWISE, &txdesc->flags));
1827 rt2x00_set_field32(&word, TXD_W0_KEY_INDEX, txdesc->key_idx);
d56d453a 1828 rt2x00_set_field32(&word, TXD_W0_DATABYTE_COUNT, skb->len);
95ea3627 1829 rt2x00_set_field32(&word, TXD_W0_BURST,
181d6902 1830 test_bit(ENTRY_TXD_BURST, &txdesc->flags));
61e754f4 1831 rt2x00_set_field32(&word, TXD_W0_CIPHER_ALG, txdesc->cipher);
95ea3627
ID		 1832 rt2x00_desc_write(txd, 0, word);
1833}
1834
1835/*
1836 * TX data initialization
1837 */
bd88a781
ID		 1838static void rt61pci_write_beacon(struct queue_entry *entry)
1839{
1840 struct rt2x00_dev *rt2x00dev = entry->queue->rt2x00dev;
1841 struct skb_frame_desc *skbdesc = get_skb_frame_desc(entry->skb);
1842 unsigned int beacon_base;
1843 u32 reg;
1844
1845 /*
1846 * Disable beaconing while we are reloading the beacon data,
1847 * otherwise we might be sending out invalid data.
1848 */
1849 rt2x00pci_register_read(rt2x00dev, TXRX_CSR9, &reg);
1850 rt2x00_set_field32(&reg, TXRX_CSR9_TSF_TICKING, 0);
1851 rt2x00_set_field32(&reg, TXRX_CSR9_TBTT_ENABLE, 0);
1852 rt2x00_set_field32(&reg, TXRX_CSR9_BEACON_GEN, 0);
1853 rt2x00pci_register_write(rt2x00dev, TXRX_CSR9, reg);
1854
1855 /*
1856 * Write entire beacon with descriptor to register.
1857 */
1858 beacon_base = HW_BEACON_OFFSET(entry->entry_idx);
1859 rt2x00pci_register_multiwrite(rt2x00dev,
1860 beacon_base,
1861 skbdesc->desc, skbdesc->desc_len);
1862 rt2x00pci_register_multiwrite(rt2x00dev,
1863 beacon_base + skbdesc->desc_len,
1864 entry->skb->data, entry->skb->len);
1865
1866 /*
1867 * Clean up beacon skb.
1868 */
1869 dev_kfree_skb_any(entry->skb);
1870 entry->skb = NULL;
1871}
1872
95ea3627 1873static void rt61pci_kick_tx_queue(struct rt2x00_dev *rt2x00dev,
e58c6aca 1874 const enum data_queue_qid queue)
95ea3627
ID		 1875{
1876 u32 reg;
1877
e58c6aca 1878 if (queue == QID_BEACON) {
95ea3627
ID		 1879 /*
1880 * For Wi-Fi faily generated beacons between participating
1881 * stations. Set TBTT phase adaptive adjustment step to 8us.
1882 */
1883 rt2x00pci_register_write(rt2x00dev, TXRX_CSR10, 0x00001008);
1884
1885 rt2x00pci_register_read(rt2x00dev, TXRX_CSR9, &reg);
1886 if (!rt2x00_get_field32(reg, TXRX_CSR9_BEACON_GEN)) {
8af244cc
ID		 1887 rt2x00_set_field32(&reg, TXRX_CSR9_TSF_TICKING, 1);
1888 rt2x00_set_field32(&reg, TXRX_CSR9_TBTT_ENABLE, 1);
95ea3627
ID		 1889 rt2x00_set_field32(&reg, TXRX_CSR9_BEACON_GEN, 1);
1890 rt2x00pci_register_write(rt2x00dev, TXRX_CSR9, reg);
1891 }
1892 return;
1893 }
1894
1895 rt2x00pci_register_read(rt2x00dev, TX_CNTL_CSR, &reg);
e58c6aca
ID		 1896 rt2x00_set_field32(&reg, TX_CNTL_CSR_KICK_TX_AC0, (queue == QID_AC_BE));
1897 rt2x00_set_field32(&reg, TX_CNTL_CSR_KICK_TX_AC1, (queue == QID_AC_BK));
1898 rt2x00_set_field32(&reg, TX_CNTL_CSR_KICK_TX_AC2, (queue == QID_AC_VI));
1899 rt2x00_set_field32(&reg, TX_CNTL_CSR_KICK_TX_AC3, (queue == QID_AC_VO));
95ea3627
ID		 1900 rt2x00pci_register_write(rt2x00dev, TX_CNTL_CSR, reg);
1901}
1902
1903/*
1904 * RX control handlers
1905 */
1906static int rt61pci_agc_to_rssi(struct rt2x00_dev *rt2x00dev, int rxd_w1)
1907{
ba2ab471 1908 u8 offset = rt2x00dev->lna_gain;
95ea3627
ID		 1909 u8 lna;
1910
1911 lna = rt2x00_get_field32(rxd_w1, RXD_W1_RSSI_LNA);
1912 switch (lna) {
1913 case 3:
ba2ab471 1914 offset += 90;
95ea3627
ID		 1915 break;
1916 case 2:
ba2ab471 1917 offset += 74;
95ea3627
ID		 1918 break;
1919 case 1:
ba2ab471 1920 offset += 64;
95ea3627
ID		 1921 break;
1922 default:
1923 return 0;
1924 }
1925
8318d78a 1926 if (rt2x00dev->rx_status.band == IEEE80211_BAND_5GHZ) {
95ea3627
ID		 1927 if (lna == 3 || lna == 2)
1928 offset += 10;
95ea3627
ID		 1929 }
1930
1931 return rt2x00_get_field32(rxd_w1, RXD_W1_RSSI_AGC) * 2 - offset;
1932}
1933
181d6902 1934static void rt61pci_fill_rxdone(struct queue_entry *entry,
55887511 1935 struct rxdone_entry_desc *rxdesc)
95ea3627 1936{
61e754f4 1937 struct rt2x00_dev *rt2x00dev = entry->queue->rt2x00dev;
b8be63ff 1938 struct queue_entry_priv_pci *entry_priv = entry->priv_data;
95ea3627
ID		 1939 u32 word0;
1940 u32 word1;
1941
b8be63ff
ID		 1942 rt2x00_desc_read(entry_priv->desc, 0, &word0);
1943 rt2x00_desc_read(entry_priv->desc, 1, &word1);
95ea3627 1944
4150c572 1945 if (rt2x00_get_field32(word0, RXD_W0_CRC_ERROR))
181d6902 1946 rxdesc->flags |= RX_FLAG_FAILED_FCS_CRC;
95ea3627 1947
61e754f4
ID		 1948 if (test_bit(CONFIG_SUPPORT_HW_CRYPTO, &rt2x00dev->flags)) {
1949 rxdesc->cipher =
1950 rt2x00_get_field32(word0, RXD_W0_CIPHER_ALG);
1951 rxdesc->cipher_status =
1952 rt2x00_get_field32(word0, RXD_W0_CIPHER_ERROR);
1953 }
1954
1955 if (rxdesc->cipher != CIPHER_NONE) {
1956 _rt2x00_desc_read(entry_priv->desc, 2, &rxdesc->iv);
1957 _rt2x00_desc_read(entry_priv->desc, 3, &rxdesc->eiv);
1958 _rt2x00_desc_read(entry_priv->desc, 4, &rxdesc->icv);
1959
1960 /*
1961 * Hardware has stripped IV/EIV data from 802.11 frame during
1962 * decryption. It has provided the data seperately but rt2x00lib
1963 * should decide if it should be reinserted.
1964 */
1965 rxdesc->flags |= RX_FLAG_IV_STRIPPED;
1966
1967 /*
1968 * FIXME: Legacy driver indicates that the frame does
1969 * contain the Michael Mic. Unfortunately, in rt2x00
1970 * the MIC seems to be missing completely...
1971 */
1972 rxdesc->flags |= RX_FLAG_MMIC_STRIPPED;
1973
1974 if (rxdesc->cipher_status == RX_CRYPTO_SUCCESS)
1975 rxdesc->flags |= RX_FLAG_DECRYPTED;
1976 else if (rxdesc->cipher_status == RX_CRYPTO_FAIL_MIC)
1977 rxdesc->flags |= RX_FLAG_MMIC_ERROR;
1978 }
1979
95ea3627
ID		 1980 /*
1981 * Obtain the status about this packet.
89993890
ID		 1982 * When frame was received with an OFDM bitrate,
1983 * the signal is the PLCP value. If it was received with
1984 * a CCK bitrate the signal is the rate in 100kbit/s.
95ea3627 1985 */
181d6902 1986 rxdesc->signal = rt2x00_get_field32(word1, RXD_W1_SIGNAL);
61e754f4 1987 rxdesc->rssi = rt61pci_agc_to_rssi(rt2x00dev, word1);
181d6902 1988 rxdesc->size = rt2x00_get_field32(word0, RXD_W0_DATABYTE_COUNT);
19d30e02 1989
19d30e02
ID		 1990 if (rt2x00_get_field32(word0, RXD_W0_OFDM))
1991 rxdesc->dev_flags |= RXDONE_SIGNAL_PLCP;
6c6aa3c0
ID		 1992 else
1993 rxdesc->dev_flags |= RXDONE_SIGNAL_BITRATE;
19d30e02
ID		 1994 if (rt2x00_get_field32(word0, RXD_W0_MY_BSS))
1995 rxdesc->dev_flags |= RXDONE_MY_BSS;
95ea3627
ID		 1996}
1997
1998/*
1999 * Interrupt functions.
2000 */
2001static void rt61pci_txdone(struct rt2x00_dev *rt2x00dev)
2002{
181d6902
ID		 2003 struct data_queue *queue;
2004 struct queue_entry *entry;
2005 struct queue_entry *entry_done;
b8be63ff 2006 struct queue_entry_priv_pci *entry_priv;
181d6902 2007 struct txdone_entry_desc txdesc;
95ea3627
ID		 2008 u32 word;
2009 u32 reg;
2010 u32 old_reg;
2011 int type;
2012 int index;
95ea3627
ID		 2013
2014 /*
2015 * During each loop we will compare the freshly read
2016 * STA_CSR4 register value with the value read from
2017 * the previous loop. If the 2 values are equal then
2018 * we should stop processing because the chance it
2019 * quite big that the device has been unplugged and
2020 * we risk going into an endless loop.
2021 */
2022 old_reg = 0;
2023
2024 while (1) {
2025 rt2x00pci_register_read(rt2x00dev, STA_CSR4, &reg);
2026 if (!rt2x00_get_field32(reg, STA_CSR4_VALID))
2027 break;
2028
2029 if (old_reg == reg)
2030 break;
2031 old_reg = reg;
2032
2033 /*
2034 * Skip this entry when it contains an invalid
181d6902 2035 * queue identication number.
95ea3627
ID		 2036 */
2037 type = rt2x00_get_field32(reg, STA_CSR4_PID_TYPE);
181d6902
ID		 2038 queue = rt2x00queue_get_queue(rt2x00dev, type);
2039 if (unlikely(!queue))
95ea3627
ID		 2040 continue;
2041
2042 /*
2043 * Skip this entry when it contains an invalid
2044 * index number.
2045 */
2046 index = rt2x00_get_field32(reg, STA_CSR4_PID_SUBTYPE);
181d6902 2047 if (unlikely(index >= queue->limit))
95ea3627
ID		 2048 continue;
2049
181d6902 2050 entry = &queue->entries[index];
b8be63ff
ID		 2051 entry_priv = entry->priv_data;
2052 rt2x00_desc_read(entry_priv->desc, 0, &word);
95ea3627
ID		 2053
2054 if (rt2x00_get_field32(word, TXD_W0_OWNER_NIC) ||
2055 !rt2x00_get_field32(word, TXD_W0_VALID))
2056 return;
2057
181d6902 2058 entry_done = rt2x00queue_get_entry(queue, Q_INDEX_DONE);
62bc060b 2059 while (entry != entry_done) {
181d6902
ID		 2060 /* Catch up.
2061 * Just report any entries we missed as failed.
2062 */
62bc060b 2063 WARNING(rt2x00dev,
181d6902
ID		 2064 "TX status report missed for entry %d\n",
2065 entry_done->entry_idx);
2066
fb55f4d1
ID		 2067 txdesc.flags = 0;
2068 __set_bit(TXDONE_UNKNOWN, &txdesc.flags);
181d6902
ID		 2069 txdesc.retry = 0;
2070
d74f5ba4 2071 rt2x00lib_txdone(entry_done, &txdesc);
181d6902 2072 entry_done = rt2x00queue_get_entry(queue, Q_INDEX_DONE);
62bc060b
MN		 2073 }
2074
95ea3627
ID		 2075 /*
2076 * Obtain the status about this packet.
2077 */
fb55f4d1
ID		 2078 txdesc.flags = 0;
2079 switch (rt2x00_get_field32(reg, STA_CSR4_TX_RESULT)) {
2080 case 0: /* Success, maybe with retry */
2081 __set_bit(TXDONE_SUCCESS, &txdesc.flags);
2082 break;
2083 case 6: /* Failure, excessive retries */
2084 __set_bit(TXDONE_EXCESSIVE_RETRY, &txdesc.flags);
2085 /* Don't break, this is a failed frame! */
2086 default: /* Failure */
2087 __set_bit(TXDONE_FAILURE, &txdesc.flags);
2088 }
181d6902 2089 txdesc.retry = rt2x00_get_field32(reg, STA_CSR4_RETRY_COUNT);
95ea3627 2090
d74f5ba4 2091 rt2x00lib_txdone(entry, &txdesc);
95ea3627
ID		 2092 }
2093}
2094
2095static irqreturn_t rt61pci_interrupt(int irq, void *dev_instance)
2096{
2097 struct rt2x00_dev *rt2x00dev = dev_instance;
2098 u32 reg_mcu;
2099 u32 reg;
2100
2101 /*
2102 * Get the interrupt sources & saved to local variable.
2103 * Write register value back to clear pending interrupts.
2104 */
2105 rt2x00pci_register_read(rt2x00dev, MCU_INT_SOURCE_CSR, &reg_mcu);
2106 rt2x00pci_register_write(rt2x00dev, MCU_INT_SOURCE_CSR, reg_mcu);
2107
2108 rt2x00pci_register_read(rt2x00dev, INT_SOURCE_CSR, &reg);
2109 rt2x00pci_register_write(rt2x00dev, INT_SOURCE_CSR, reg);
2110
2111 if (!reg && !reg_mcu)
2112 return IRQ_NONE;
2113
0262ab0d 2114 if (!test_bit(DEVICE_STATE_ENABLED_RADIO, &rt2x00dev->flags))
95ea3627
ID		 2115 return IRQ_HANDLED;
2116
2117 /*
2118 * Handle interrupts, walk through all bits
2119 * and run the tasks, the bits are checked in order of
2120 * priority.
2121 */
2122
2123 /*
2124 * 1 - Rx ring done interrupt.
2125 */
2126 if (rt2x00_get_field32(reg, INT_SOURCE_CSR_RXDONE))
2127 rt2x00pci_rxdone(rt2x00dev);
2128
2129 /*
2130 * 2 - Tx ring done interrupt.
2131 */
2132 if (rt2x00_get_field32(reg, INT_SOURCE_CSR_TXDONE))
2133 rt61pci_txdone(rt2x00dev);
2134
2135 /*
2136 * 3 - Handle MCU command done.
2137 */
2138 if (reg_mcu)
2139 rt2x00pci_register_write(rt2x00dev,
2140 M2H_CMD_DONE_CSR, 0xffffffff);
2141
2142 return IRQ_HANDLED;
2143}
2144
2145/*
2146 * Device probe functions.
2147 */
2148static int rt61pci_validate_eeprom(struct rt2x00_dev *rt2x00dev)
2149{
2150 struct eeprom_93cx6 eeprom;
2151 u32 reg;
2152 u16 word;
2153 u8 *mac;
2154 s8 value;
2155
2156 rt2x00pci_register_read(rt2x00dev, E2PROM_CSR, &reg);
2157
2158 eeprom.data = rt2x00dev;
2159 eeprom.register_read = rt61pci_eepromregister_read;
2160 eeprom.register_write = rt61pci_eepromregister_write;
2161 eeprom.width = rt2x00_get_field32(reg, E2PROM_CSR_TYPE_93C46) ?
2162 PCI_EEPROM_WIDTH_93C46 : PCI_EEPROM_WIDTH_93C66;
2163 eeprom.reg_data_in = 0;
2164 eeprom.reg_data_out = 0;
2165 eeprom.reg_data_clock = 0;
2166 eeprom.reg_chip_select = 0;
2167
2168 eeprom_93cx6_multiread(&eeprom, EEPROM_BASE, rt2x00dev->eeprom,
2169 EEPROM_SIZE / sizeof(u16));
2170
2171 /*
2172 * Start validation of the data that has been read.
2173 */
2174 mac = rt2x00_eeprom_addr(rt2x00dev, EEPROM_MAC_ADDR_0);
2175 if (!is_valid_ether_addr(mac)) {
2176 random_ether_addr(mac);
e174961c 2177 EEPROM(rt2x00dev, "MAC: %pM\n", mac);
95ea3627
ID		 2178 }
2179
2180 rt2x00_eeprom_read(rt2x00dev, EEPROM_ANTENNA, &word);
2181 if (word == 0xffff) {
2182 rt2x00_set_field16(&word, EEPROM_ANTENNA_NUM, 2);
362f3b6b
ID		 2183 rt2x00_set_field16(&word, EEPROM_ANTENNA_TX_DEFAULT,
2184 ANTENNA_B);
2185 rt2x00_set_field16(&word, EEPROM_ANTENNA_RX_DEFAULT,
2186 ANTENNA_B);
95ea3627
ID		 2187 rt2x00_set_field16(&word, EEPROM_ANTENNA_FRAME_TYPE, 0);
2188 rt2x00_set_field16(&word, EEPROM_ANTENNA_DYN_TXAGC, 0);
2189 rt2x00_set_field16(&word, EEPROM_ANTENNA_HARDWARE_RADIO, 0);
2190 rt2x00_set_field16(&word, EEPROM_ANTENNA_RF_TYPE, RF5225);
2191 rt2x00_eeprom_write(rt2x00dev, EEPROM_ANTENNA, word);
2192 EEPROM(rt2x00dev, "Antenna: 0x%04x\n", word);
2193 }
2194
2195 rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC, &word);
2196 if (word == 0xffff) {
2197 rt2x00_set_field16(&word, EEPROM_NIC_ENABLE_DIVERSITY, 0);
2198 rt2x00_set_field16(&word, EEPROM_NIC_TX_DIVERSITY, 0);
2199 rt2x00_set_field16(&word, EEPROM_NIC_TX_RX_FIXED, 0);
2200 rt2x00_set_field16(&word, EEPROM_NIC_EXTERNAL_LNA_BG, 0);
2201 rt2x00_set_field16(&word, EEPROM_NIC_CARDBUS_ACCEL, 0);
2202 rt2x00_set_field16(&word, EEPROM_NIC_EXTERNAL_LNA_A, 0);
2203 rt2x00_eeprom_write(rt2x00dev, EEPROM_NIC, word);
2204 EEPROM(rt2x00dev, "NIC: 0x%04x\n", word);
2205 }
2206
2207 rt2x00_eeprom_read(rt2x00dev, EEPROM_LED, &word);
2208 if (word == 0xffff) {
2209 rt2x00_set_field16(&word, EEPROM_LED_LED_MODE,
2210 LED_MODE_DEFAULT);
2211 rt2x00_eeprom_write(rt2x00dev, EEPROM_LED, word);
2212 EEPROM(rt2x00dev, "Led: 0x%04x\n", word);
2213 }
2214
2215 rt2x00_eeprom_read(rt2x00dev, EEPROM_FREQ, &word);
2216 if (word == 0xffff) {
2217 rt2x00_set_field16(&word, EEPROM_FREQ_OFFSET, 0);
2218 rt2x00_set_field16(&word, EEPROM_FREQ_SEQ, 0);
2219 rt2x00_eeprom_write(rt2x00dev, EEPROM_FREQ, word);
2220 EEPROM(rt2x00dev, "Freq: 0x%04x\n", word);
2221 }
2222
2223 rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_OFFSET_BG, &word);
2224 if (word == 0xffff) {
2225 rt2x00_set_field16(&word, EEPROM_RSSI_OFFSET_BG_1, 0);
2226 rt2x00_set_field16(&word, EEPROM_RSSI_OFFSET_BG_2, 0);
2227 rt2x00_eeprom_write(rt2x00dev, EEPROM_RSSI_OFFSET_BG, word);
2228 EEPROM(rt2x00dev, "RSSI OFFSET BG: 0x%04x\n", word);
2229 } else {
2230 value = rt2x00_get_field16(word, EEPROM_RSSI_OFFSET_BG_1);
2231 if (value < -10 || value > 10)
2232 rt2x00_set_field16(&word, EEPROM_RSSI_OFFSET_BG_1, 0);
2233 value = rt2x00_get_field16(word, EEPROM_RSSI_OFFSET_BG_2);
2234 if (value < -10 || value > 10)
2235 rt2x00_set_field16(&word, EEPROM_RSSI_OFFSET_BG_2, 0);
2236 rt2x00_eeprom_write(rt2x00dev, EEPROM_RSSI_OFFSET_BG, word);
2237 }
2238
2239 rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_OFFSET_A, &word);
2240 if (word == 0xffff) {
2241 rt2x00_set_field16(&word, EEPROM_RSSI_OFFSET_A_1, 0);
2242 rt2x00_set_field16(&word, EEPROM_RSSI_OFFSET_A_2, 0);
2243 rt2x00_eeprom_write(rt2x00dev, EEPROM_RSSI_OFFSET_A, word);
417f412f 2244 EEPROM(rt2x00dev, "RSSI OFFSET A: 0x%04x\n", word);
95ea3627
ID		 2245 } else {
2246 value = rt2x00_get_field16(word, EEPROM_RSSI_OFFSET_A_1);
2247 if (value < -10 || value > 10)
2248 rt2x00_set_field16(&word, EEPROM_RSSI_OFFSET_A_1, 0);
2249 value = rt2x00_get_field16(word, EEPROM_RSSI_OFFSET_A_2);
2250 if (value < -10 || value > 10)
2251 rt2x00_set_field16(&word, EEPROM_RSSI_OFFSET_A_2, 0);
2252 rt2x00_eeprom_write(rt2x00dev, EEPROM_RSSI_OFFSET_A, word);
2253 }
2254
2255 return 0;
2256}
2257
2258static int rt61pci_init_eeprom(struct rt2x00_dev *rt2x00dev)
2259{
2260 u32 reg;
2261 u16 value;
2262 u16 eeprom;
2263 u16 device;
2264
2265 /*
2266 * Read EEPROM word for configuration.
2267 */
2268 rt2x00_eeprom_read(rt2x00dev, EEPROM_ANTENNA, &eeprom);
2269
2270 /*
2271 * Identify RF chipset.
2272 * To determine the RT chip we have to read the
2273 * PCI header of the device.
2274 */
14a3bf89 2275 pci_read_config_word(to_pci_dev(rt2x00dev->dev),
95ea3627
ID		 2276 PCI_CONFIG_HEADER_DEVICE, &device);
2277 value = rt2x00_get_field16(eeprom, EEPROM_ANTENNA_RF_TYPE);
2278 rt2x00pci_register_read(rt2x00dev, MAC_CSR0, &reg);
2279 rt2x00_set_chip(rt2x00dev, device, value, reg);
2280
2281 if (!rt2x00_rf(&rt2x00dev->chip, RF5225) &&
2282 !rt2x00_rf(&rt2x00dev->chip, RF5325) &&
2283 !rt2x00_rf(&rt2x00dev->chip, RF2527) &&
2284 !rt2x00_rf(&rt2x00dev->chip, RF2529)) {
2285 ERROR(rt2x00dev, "Invalid RF chipset detected.\n");
2286 return -ENODEV;
2287 }
2288
e4cd2ff8
ID		 2289 /*
2290 * Determine number of antenna's.
2291 */
2292 if (rt2x00_get_field16(eeprom, EEPROM_ANTENNA_NUM) == 2)
2293 __set_bit(CONFIG_DOUBLE_ANTENNA, &rt2x00dev->flags);
2294
95ea3627
ID		 2295 /*
2296 * Identify default antenna configuration.
2297 */
addc81bd 2298 rt2x00dev->default_ant.tx =
95ea3627 2299 rt2x00_get_field16(eeprom, EEPROM_ANTENNA_TX_DEFAULT);
addc81bd 2300 rt2x00dev->default_ant.rx =
95ea3627
ID		 2301 rt2x00_get_field16(eeprom, EEPROM_ANTENNA_RX_DEFAULT);
2302
2303 /*
2304 * Read the Frame type.
2305 */
2306 if (rt2x00_get_field16(eeprom, EEPROM_ANTENNA_FRAME_TYPE))
2307 __set_bit(CONFIG_FRAME_TYPE, &rt2x00dev->flags);
2308
95ea3627
ID		 2309 /*
2310 * Detect if this device has an hardware controlled radio.
2311 */
58169529 2312#ifdef CONFIG_RT2X00_LIB_RFKILL
95ea3627 2313 if (rt2x00_get_field16(eeprom, EEPROM_ANTENNA_HARDWARE_RADIO))
066cb637 2314 __set_bit(CONFIG_SUPPORT_HW_BUTTON, &rt2x00dev->flags);
58169529 2315#endif /* CONFIG_RT2X00_LIB_RFKILL */
95ea3627
ID		 2316
2317 /*
2318 * Read frequency offset and RF programming sequence.
2319 */
2320 rt2x00_eeprom_read(rt2x00dev, EEPROM_FREQ, &eeprom);
2321 if (rt2x00_get_field16(eeprom, EEPROM_FREQ_SEQ))
2322 __set_bit(CONFIG_RF_SEQUENCE, &rt2x00dev->flags);
2323
2324 rt2x00dev->freq_offset = rt2x00_get_field16(eeprom, EEPROM_FREQ_OFFSET);
2325
2326 /*
2327 * Read external LNA informations.
2328 */
2329 rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC, &eeprom);
2330
2331 if (rt2x00_get_field16(eeprom, EEPROM_NIC_EXTERNAL_LNA_A))
2332 __set_bit(CONFIG_EXTERNAL_LNA_A, &rt2x00dev->flags);
2333 if (rt2x00_get_field16(eeprom, EEPROM_NIC_EXTERNAL_LNA_BG))
2334 __set_bit(CONFIG_EXTERNAL_LNA_BG, &rt2x00dev->flags);
2335
e4cd2ff8
ID		 2336 /*
2337 * When working with a RF2529 chip without double antenna
2338 * the antenna settings should be gathered from the NIC
2339 * eeprom word.
2340 */
2341 if (rt2x00_rf(&rt2x00dev->chip, RF2529) &&
2342 !test_bit(CONFIG_DOUBLE_ANTENNA, &rt2x00dev->flags)) {
2343 switch (rt2x00_get_field16(eeprom, EEPROM_NIC_TX_RX_FIXED)) {
2344 case 0:
2345 rt2x00dev->default_ant.tx = ANTENNA_B;
2346 rt2x00dev->default_ant.rx = ANTENNA_A;
2347 break;
2348 case 1:
2349 rt2x00dev->default_ant.tx = ANTENNA_B;
2350 rt2x00dev->default_ant.rx = ANTENNA_B;
2351 break;
2352 case 2:
2353 rt2x00dev->default_ant.tx = ANTENNA_A;
2354 rt2x00dev->default_ant.rx = ANTENNA_A;
2355 break;
2356 case 3:
2357 rt2x00dev->default_ant.tx = ANTENNA_A;
2358 rt2x00dev->default_ant.rx = ANTENNA_B;
2359 break;
2360 }
2361
2362 if (rt2x00_get_field16(eeprom, EEPROM_NIC_TX_DIVERSITY))
2363 rt2x00dev->default_ant.tx = ANTENNA_SW_DIVERSITY;
2364 if (rt2x00_get_field16(eeprom, EEPROM_NIC_ENABLE_DIVERSITY))
2365 rt2x00dev->default_ant.rx = ANTENNA_SW_DIVERSITY;
2366 }
2367
95ea3627
ID		 2368 /*
2369 * Store led settings, for correct led behaviour.
2370 * If the eeprom value is invalid,
2371 * switch to default led mode.
2372 */
771fd565 2373#ifdef CONFIG_RT2X00_LIB_LEDS
95ea3627 2374 rt2x00_eeprom_read(rt2x00dev, EEPROM_LED, &eeprom);
a9450b70
ID		 2375 value = rt2x00_get_field16(eeprom, EEPROM_LED_LED_MODE);
2376
475433be
ID		 2377 rt61pci_init_led(rt2x00dev, &rt2x00dev->led_radio, LED_TYPE_RADIO);
2378 rt61pci_init_led(rt2x00dev, &rt2x00dev->led_assoc, LED_TYPE_ASSOC);
2379 if (value == LED_MODE_SIGNAL_STRENGTH)
2380 rt61pci_init_led(rt2x00dev, &rt2x00dev->led_qual,
2381 LED_TYPE_QUALITY);
95ea3627 2382
a9450b70
ID		 2383 rt2x00_set_field16(&rt2x00dev->led_mcu_reg, MCU_LEDCS_LED_MODE, value);
2384 rt2x00_set_field16(&rt2x00dev->led_mcu_reg, MCU_LEDCS_POLARITY_GPIO_0,
95ea3627
ID		 2385 rt2x00_get_field16(eeprom,
2386 EEPROM_LED_POLARITY_GPIO_0));
a9450b70 2387 rt2x00_set_field16(&rt2x00dev->led_mcu_reg, MCU_LEDCS_POLARITY_GPIO_1,
95ea3627
ID		 2388 rt2x00_get_field16(eeprom,
2389 EEPROM_LED_POLARITY_GPIO_1));
a9450b70 2390 rt2x00_set_field16(&rt2x00dev->led_mcu_reg, MCU_LEDCS_POLARITY_GPIO_2,
95ea3627
ID		 2391 rt2x00_get_field16(eeprom,
2392 EEPROM_LED_POLARITY_GPIO_2));
a9450b70 2393 rt2x00_set_field16(&rt2x00dev->led_mcu_reg, MCU_LEDCS_POLARITY_GPIO_3,
95ea3627
ID		 2394 rt2x00_get_field16(eeprom,
2395 EEPROM_LED_POLARITY_GPIO_3));
a9450b70 2396 rt2x00_set_field16(&rt2x00dev->led_mcu_reg, MCU_LEDCS_POLARITY_GPIO_4,
95ea3627
ID		 2397 rt2x00_get_field16(eeprom,
2398 EEPROM_LED_POLARITY_GPIO_4));
a9450b70 2399 rt2x00_set_field16(&rt2x00dev->led_mcu_reg, MCU_LEDCS_POLARITY_ACT,
95ea3627 2400 rt2x00_get_field16(eeprom, EEPROM_LED_POLARITY_ACT));
a9450b70 2401 rt2x00_set_field16(&rt2x00dev->led_mcu_reg, MCU_LEDCS_POLARITY_READY_BG,
95ea3627
ID		 2402 rt2x00_get_field16(eeprom,
2403 EEPROM_LED_POLARITY_RDY_G));
a9450b70 2404 rt2x00_set_field16(&rt2x00dev->led_mcu_reg, MCU_LEDCS_POLARITY_READY_A,
95ea3627
ID		 2405 rt2x00_get_field16(eeprom,
2406 EEPROM_LED_POLARITY_RDY_A));
771fd565 2407#endif /* CONFIG_RT2X00_LIB_LEDS */
95ea3627
ID		 2408
2409 return 0;
2410}
2411
2412/*
2413 * RF value list for RF5225 & RF5325
2414 * Supports: 2.4 GHz & 5.2 GHz, rf_sequence disabled
2415 */
2416static const struct rf_channel rf_vals_noseq[] = {
2417 { 1, 0x00002ccc, 0x00004786, 0x00068455, 0x000ffa0b },
2418 { 2, 0x00002ccc, 0x00004786, 0x00068455, 0x000ffa1f },
2419 { 3, 0x00002ccc, 0x0000478a, 0x00068455, 0x000ffa0b },
2420 { 4, 0x00002ccc, 0x0000478a, 0x00068455, 0x000ffa1f },
2421 { 5, 0x00002ccc, 0x0000478e, 0x00068455, 0x000ffa0b },
2422 { 6, 0x00002ccc, 0x0000478e, 0x00068455, 0x000ffa1f },
2423 { 7, 0x00002ccc, 0x00004792, 0x00068455, 0x000ffa0b },
2424 { 8, 0x00002ccc, 0x00004792, 0x00068455, 0x000ffa1f },
2425 { 9, 0x00002ccc, 0x00004796, 0x00068455, 0x000ffa0b },
2426 { 10, 0x00002ccc, 0x00004796, 0x00068455, 0x000ffa1f },
2427 { 11, 0x00002ccc, 0x0000479a, 0x00068455, 0x000ffa0b },
2428 { 12, 0x00002ccc, 0x0000479a, 0x00068455, 0x000ffa1f },
2429 { 13, 0x00002ccc, 0x0000479e, 0x00068455, 0x000ffa0b },
2430 { 14, 0x00002ccc, 0x000047a2, 0x00068455, 0x000ffa13 },
2431
2432 /* 802.11 UNI / HyperLan 2 */
2433 { 36, 0x00002ccc, 0x0000499a, 0x0009be55, 0x000ffa23 },
2434 { 40, 0x00002ccc, 0x000049a2, 0x0009be55, 0x000ffa03 },
2435 { 44, 0x00002ccc, 0x000049a6, 0x0009be55, 0x000ffa0b },
2436 { 48, 0x00002ccc, 0x000049aa, 0x0009be55, 0x000ffa13 },
2437 { 52, 0x00002ccc, 0x000049ae, 0x0009ae55, 0x000ffa1b },
2438 { 56, 0x00002ccc, 0x000049b2, 0x0009ae55, 0x000ffa23 },
2439 { 60, 0x00002ccc, 0x000049ba, 0x0009ae55, 0x000ffa03 },
2440 { 64, 0x00002ccc, 0x000049be, 0x0009ae55, 0x000ffa0b },
2441
2442 /* 802.11 HyperLan 2 */
2443 { 100, 0x00002ccc, 0x00004a2a, 0x000bae55, 0x000ffa03 },
2444 { 104, 0x00002ccc, 0x00004a2e, 0x000bae55, 0x000ffa0b },
2445 { 108, 0x00002ccc, 0x00004a32, 0x000bae55, 0x000ffa13 },
2446 { 112, 0x00002ccc, 0x00004a36, 0x000bae55, 0x000ffa1b },
2447 { 116, 0x00002ccc, 0x00004a3a, 0x000bbe55, 0x000ffa23 },
2448 { 120, 0x00002ccc, 0x00004a82, 0x000bbe55, 0x000ffa03 },
2449 { 124, 0x00002ccc, 0x00004a86, 0x000bbe55, 0x000ffa0b },
2450 { 128, 0x00002ccc, 0x00004a8a, 0x000bbe55, 0x000ffa13 },
2451 { 132, 0x00002ccc, 0x00004a8e, 0x000bbe55, 0x000ffa1b },
2452 { 136, 0x00002ccc, 0x00004a92, 0x000bbe55, 0x000ffa23 },
2453
2454 /* 802.11 UNII */
2455 { 140, 0x00002ccc, 0x00004a9a, 0x000bbe55, 0x000ffa03 },
2456 { 149, 0x00002ccc, 0x00004aa2, 0x000bbe55, 0x000ffa1f },
2457 { 153, 0x00002ccc, 0x00004aa6, 0x000bbe55, 0x000ffa27 },
2458 { 157, 0x00002ccc, 0x00004aae, 0x000bbe55, 0x000ffa07 },
2459 { 161, 0x00002ccc, 0x00004ab2, 0x000bbe55, 0x000ffa0f },
2460 { 165, 0x00002ccc, 0x00004ab6, 0x000bbe55, 0x000ffa17 },
2461
2462 /* MMAC(Japan)J52 ch 34,38,42,46 */
2463 { 34, 0x00002ccc, 0x0000499a, 0x0009be55, 0x000ffa0b },
2464 { 38, 0x00002ccc, 0x0000499e, 0x0009be55, 0x000ffa13 },
2465 { 42, 0x00002ccc, 0x000049a2, 0x0009be55, 0x000ffa1b },
2466 { 46, 0x00002ccc, 0x000049a6, 0x0009be55, 0x000ffa23 },
2467};
2468
2469/*
2470 * RF value list for RF5225 & RF5325
2471 * Supports: 2.4 GHz & 5.2 GHz, rf_sequence enabled
2472 */
2473static const struct rf_channel rf_vals_seq[] = {
2474 { 1, 0x00002ccc, 0x00004786, 0x00068455, 0x000ffa0b },
2475 { 2, 0x00002ccc, 0x00004786, 0x00068455, 0x000ffa1f },
2476 { 3, 0x00002ccc, 0x0000478a, 0x00068455, 0x000ffa0b },
2477 { 4, 0x00002ccc, 0x0000478a, 0x00068455, 0x000ffa1f },
2478 { 5, 0x00002ccc, 0x0000478e, 0x00068455, 0x000ffa0b },
2479 { 6, 0x00002ccc, 0x0000478e, 0x00068455, 0x000ffa1f },
2480 { 7, 0x00002ccc, 0x00004792, 0x00068455, 0x000ffa0b },
2481 { 8, 0x00002ccc, 0x00004792, 0x00068455, 0x000ffa1f },
2482 { 9, 0x00002ccc, 0x00004796, 0x00068455, 0x000ffa0b },
2483 { 10, 0x00002ccc, 0x00004796, 0x00068455, 0x000ffa1f },
2484 { 11, 0x00002ccc, 0x0000479a, 0x00068455, 0x000ffa0b },
2485 { 12, 0x00002ccc, 0x0000479a, 0x00068455, 0x000ffa1f },
2486 { 13, 0x00002ccc, 0x0000479e, 0x00068455, 0x000ffa0b },
2487 { 14, 0x00002ccc, 0x000047a2, 0x00068455, 0x000ffa13 },
2488
2489 /* 802.11 UNI / HyperLan 2 */
2490 { 36, 0x00002cd4, 0x0004481a, 0x00098455, 0x000c0a03 },
2491 { 40, 0x00002cd0, 0x00044682, 0x00098455, 0x000c0a03 },
2492 { 44, 0x00002cd0, 0x00044686, 0x00098455, 0x000c0a1b },
2493 { 48, 0x00002cd0, 0x0004468e, 0x00098655, 0x000c0a0b },
2494 { 52, 0x00002cd0, 0x00044692, 0x00098855, 0x000c0a23 },
2495 { 56, 0x00002cd0, 0x0004469a, 0x00098c55, 0x000c0a13 },
2496 { 60, 0x00002cd0, 0x000446a2, 0x00098e55, 0x000c0a03 },
2497 { 64, 0x00002cd0, 0x000446a6, 0x00099255, 0x000c0a1b },
2498
2499 /* 802.11 HyperLan 2 */
2500 { 100, 0x00002cd4, 0x0004489a, 0x000b9855, 0x000c0a03 },
2501 { 104, 0x00002cd4, 0x000448a2, 0x000b9855, 0x000c0a03 },
2502 { 108, 0x00002cd4, 0x000448aa, 0x000b9855, 0x000c0a03 },
2503 { 112, 0x00002cd4, 0x000448b2, 0x000b9a55, 0x000c0a03 },
2504 { 116, 0x00002cd4, 0x000448ba, 0x000b9a55, 0x000c0a03 },
2505 { 120, 0x00002cd0, 0x00044702, 0x000b9a55, 0x000c0a03 },
2506 { 124, 0x00002cd0, 0x00044706, 0x000b9a55, 0x000c0a1b },
2507 { 128, 0x00002cd0, 0x0004470e, 0x000b9c55, 0x000c0a0b },
2508 { 132, 0x00002cd0, 0x00044712, 0x000b9c55, 0x000c0a23 },
2509 { 136, 0x00002cd0, 0x0004471a, 0x000b9e55, 0x000c0a13 },
2510
2511 /* 802.11 UNII */
2512 { 140, 0x00002cd0, 0x00044722, 0x000b9e55, 0x000c0a03 },
2513 { 149, 0x00002cd0, 0x0004472e, 0x000ba255, 0x000c0a1b },
2514 { 153, 0x00002cd0, 0x00044736, 0x000ba255, 0x000c0a0b },
2515 { 157, 0x00002cd4, 0x0004490a, 0x000ba255, 0x000c0a17 },
2516 { 161, 0x00002cd4, 0x00044912, 0x000ba255, 0x000c0a17 },
2517 { 165, 0x00002cd4, 0x0004491a, 0x000ba255, 0x000c0a17 },
2518
2519 /* MMAC(Japan)J52 ch 34,38,42,46 */
2520 { 34, 0x00002ccc, 0x0000499a, 0x0009be55, 0x000c0a0b },
2521 { 38, 0x00002ccc, 0x0000499e, 0x0009be55, 0x000c0a13 },
2522 { 42, 0x00002ccc, 0x000049a2, 0x0009be55, 0x000c0a1b },
2523 { 46, 0x00002ccc, 0x000049a6, 0x0009be55, 0x000c0a23 },
2524};
2525
8c5e7a5f 2526static int rt61pci_probe_hw_mode(struct rt2x00_dev *rt2x00dev)
95ea3627
ID		 2527{
2528 struct hw_mode_spec *spec = &rt2x00dev->spec;
8c5e7a5f
ID		 2529 struct channel_info *info;
2530 char *tx_power;
95ea3627
ID		 2531 unsigned int i;
2532
2533 /*
2534 * Initialize all hw fields.
2535 */
2536 rt2x00dev->hw->flags =
566bfe5a
BR		 2537 IEEE80211_HW_HOST_BROADCAST_PS_BUFFERING |
2538 IEEE80211_HW_SIGNAL_DBM;
95ea3627 2539 rt2x00dev->hw->extra_tx_headroom = 0;
95ea3627 2540
14a3bf89 2541 SET_IEEE80211_DEV(rt2x00dev->hw, rt2x00dev->dev);
95ea3627
ID		 2542 SET_IEEE80211_PERM_ADDR(rt2x00dev->hw,
2543 rt2x00_eeprom_addr(rt2x00dev,
2544 EEPROM_MAC_ADDR_0));
2545
95ea3627
ID		 2546 /*
2547 * Initialize hw_mode information.
2548 */
31562e80
ID		 2549 spec->supported_bands = SUPPORT_BAND_2GHZ;
2550 spec->supported_rates = SUPPORT_RATE_CCK | SUPPORT_RATE_OFDM;
95ea3627
ID		 2551
2552 if (!test_bit(CONFIG_RF_SEQUENCE, &rt2x00dev->flags)) {
2553 spec->num_channels = 14;
2554 spec->channels = rf_vals_noseq;
2555 } else {
2556 spec->num_channels = 14;
2557 spec->channels = rf_vals_seq;
2558 }
2559
2560 if (rt2x00_rf(&rt2x00dev->chip, RF5225) ||
2561 rt2x00_rf(&rt2x00dev->chip, RF5325)) {
31562e80 2562 spec->supported_bands |= SUPPORT_BAND_5GHZ;
95ea3627 2563 spec->num_channels = ARRAY_SIZE(rf_vals_seq);
8c5e7a5f
ID		 2564 }
2565
2566 /*
2567 * Create channel information array
2568 */
2569 info = kzalloc(spec->num_channels * sizeof(*info), GFP_KERNEL);
2570 if (!info)
2571 return -ENOMEM;
2572
2573 spec->channels_info = info;
95ea3627 2574
8c5e7a5f
ID		 2575 tx_power = rt2x00_eeprom_addr(rt2x00dev, EEPROM_TXPOWER_G_START);
2576 for (i = 0; i < 14; i++)
2577 info[i].tx_power1 = TXPOWER_FROM_DEV(tx_power[i]);
95ea3627 2578
8c5e7a5f
ID		 2579 if (spec->num_channels > 14) {
2580 tx_power = rt2x00_eeprom_addr(rt2x00dev, EEPROM_TXPOWER_A_START);
2581 for (i = 14; i < spec->num_channels; i++)
2582 info[i].tx_power1 = TXPOWER_FROM_DEV(tx_power[i]);
95ea3627 2583 }
8c5e7a5f
ID		 2584
2585 return 0;
95ea3627
ID		 2586}
2587
2588static int rt61pci_probe_hw(struct rt2x00_dev *rt2x00dev)
2589{
2590 int retval;
2591
2592 /*
2593 * Allocate eeprom data.
2594 */
2595 retval = rt61pci_validate_eeprom(rt2x00dev);
2596 if (retval)
2597 return retval;
2598
2599 retval = rt61pci_init_eeprom(rt2x00dev);
2600 if (retval)
2601 return retval;
2602
2603 /*
2604 * Initialize hw specifications.
2605 */
8c5e7a5f
ID		 2606 retval = rt61pci_probe_hw_mode(rt2x00dev);
2607 if (retval)
2608 return retval;
95ea3627
ID		 2609
2610 /*
c4da0048 2611 * This device requires firmware and DMA mapped skbs.
95ea3627 2612 */
066cb637 2613 __set_bit(DRIVER_REQUIRE_FIRMWARE, &rt2x00dev->flags);
c4da0048 2614 __set_bit(DRIVER_REQUIRE_DMA, &rt2x00dev->flags);
008c4482
ID		 2615 if (!modparam_nohwcrypt)
2616 __set_bit(CONFIG_SUPPORT_HW_CRYPTO, &rt2x00dev->flags);
95ea3627
ID		 2617
2618 /*
2619 * Set the rssi offset.
2620 */
2621 rt2x00dev->rssi_offset = DEFAULT_RSSI_OFFSET;
2622
2623 return 0;
2624}
2625
2626/*
2627 * IEEE80211 stack callback functions.
2628 */
2af0a570
ID		 2629static int rt61pci_conf_tx(struct ieee80211_hw *hw, u16 queue_idx,
2630 const struct ieee80211_tx_queue_params *params)
2631{
2632 struct rt2x00_dev *rt2x00dev = hw->priv;
2633 struct data_queue *queue;
2634 struct rt2x00_field32 field;
2635 int retval;
2636 u32 reg;
2637
2638 /*
2639 * First pass the configuration through rt2x00lib, that will
2640 * update the queue settings and validate the input. After that
2641 * we are free to update the registers based on the value
2642 * in the queue parameter.
2643 */
2644 retval = rt2x00mac_conf_tx(hw, queue_idx, params);
2645 if (retval)
2646 return retval;
2647
2648 queue = rt2x00queue_get_queue(rt2x00dev, queue_idx);
2649
2650 /* Update WMM TXOP register */
2651 if (queue_idx < 2) {
2652 field.bit_offset = queue_idx * 16;
2653 field.bit_mask = 0xffff << field.bit_offset;
2654
2655 rt2x00pci_register_read(rt2x00dev, AC_TXOP_CSR0, &reg);
2656 rt2x00_set_field32(&reg, field, queue->txop);
2657 rt2x00pci_register_write(rt2x00dev, AC_TXOP_CSR0, reg);
2658 } else if (queue_idx < 4) {
2659 field.bit_offset = (queue_idx - 2) * 16;
2660 field.bit_mask = 0xffff << field.bit_offset;
2661
2662 rt2x00pci_register_read(rt2x00dev, AC_TXOP_CSR1, &reg);
2663 rt2x00_set_field32(&reg, field, queue->txop);
2664 rt2x00pci_register_write(rt2x00dev, AC_TXOP_CSR1, reg);
2665 }
2666
2667 /* Update WMM registers */
2668 field.bit_offset = queue_idx * 4;
2669 field.bit_mask = 0xf << field.bit_offset;
2670
2671 rt2x00pci_register_read(rt2x00dev, AIFSN_CSR, &reg);
2672 rt2x00_set_field32(&reg, field, queue->aifs);
2673 rt2x00pci_register_write(rt2x00dev, AIFSN_CSR, reg);
2674
2675 rt2x00pci_register_read(rt2x00dev, CWMIN_CSR, &reg);
2676 rt2x00_set_field32(&reg, field, queue->cw_min);
2677 rt2x00pci_register_write(rt2x00dev, CWMIN_CSR, reg);
2678
2679 rt2x00pci_register_read(rt2x00dev, CWMAX_CSR, &reg);
2680 rt2x00_set_field32(&reg, field, queue->cw_max);
2681 rt2x00pci_register_write(rt2x00dev, CWMAX_CSR, reg);
2682
2683 return 0;
2684}
2685
95ea3627
ID		 2686static u64 rt61pci_get_tsf(struct ieee80211_hw *hw)
2687{
2688 struct rt2x00_dev *rt2x00dev = hw->priv;
2689 u64 tsf;
2690 u32 reg;
2691
2692 rt2x00pci_register_read(rt2x00dev, TXRX_CSR13, &reg);
2693 tsf = (u64) rt2x00_get_field32(reg, TXRX_CSR13_HIGH_TSFTIMER) << 32;
2694 rt2x00pci_register_read(rt2x00dev, TXRX_CSR12, &reg);
2695 tsf |= rt2x00_get_field32(reg, TXRX_CSR12_LOW_TSFTIMER);
2696
2697 return tsf;
2698}
2699
95ea3627
ID		 2700static const struct ieee80211_ops rt61pci_mac80211_ops = {
2701 .tx = rt2x00mac_tx,
4150c572
JB		 2702 .start = rt2x00mac_start,
2703 .stop = rt2x00mac_stop,
95ea3627
ID		 2704 .add_interface = rt2x00mac_add_interface,
2705 .remove_interface = rt2x00mac_remove_interface,
2706 .config = rt2x00mac_config,
2707 .config_interface = rt2x00mac_config_interface,
3a643d24 2708 .configure_filter = rt2x00mac_configure_filter,
61e754f4 2709 .set_key = rt2x00mac_set_key,
95ea3627 2710 .get_stats = rt2x00mac_get_stats,
471b3efd 2711 .bss_info_changed = rt2x00mac_bss_info_changed,
2af0a570 2712 .conf_tx = rt61pci_conf_tx,
95ea3627
ID		 2713 .get_tx_stats = rt2x00mac_get_tx_stats,
2714 .get_tsf = rt61pci_get_tsf,
95ea3627
ID		 2715};
2716
2717static const struct rt2x00lib_ops rt61pci_rt2x00_ops = {
2718 .irq_handler = rt61pci_interrupt,
2719 .probe_hw = rt61pci_probe_hw,
2720 .get_firmware_name = rt61pci_get_firmware_name,
a7f3a06c 2721 .get_firmware_crc = rt61pci_get_firmware_crc,
95ea3627
ID		 2722 .load_firmware = rt61pci_load_firmware,
2723 .initialize = rt2x00pci_initialize,
2724 .uninitialize = rt2x00pci_uninitialize,
837e7f24
ID		 2725 .init_rxentry = rt61pci_init_rxentry,
2726 .init_txentry = rt61pci_init_txentry,
95ea3627 2727 .set_device_state = rt61pci_set_device_state,
95ea3627 2728 .rfkill_poll = rt61pci_rfkill_poll,
95ea3627
ID		 2729 .link_stats = rt61pci_link_stats,
2730 .reset_tuner = rt61pci_reset_tuner,
2731 .link_tuner = rt61pci_link_tuner,
2732 .write_tx_desc = rt61pci_write_tx_desc,
2733 .write_tx_data = rt2x00pci_write_tx_data,
bd88a781 2734 .write_beacon = rt61pci_write_beacon,
95ea3627
ID		 2735 .kick_tx_queue = rt61pci_kick_tx_queue,
2736 .fill_rxdone = rt61pci_fill_rxdone,
61e754f4
ID		 2737 .config_shared_key = rt61pci_config_shared_key,
2738 .config_pairwise_key = rt61pci_config_pairwise_key,
3a643d24 2739 .config_filter = rt61pci_config_filter,
6bb40dd1 2740 .config_intf = rt61pci_config_intf,
72810379 2741 .config_erp = rt61pci_config_erp,
e4ea1c40 2742 .config_ant = rt61pci_config_ant,
95ea3627
ID		 2743 .config = rt61pci_config,
2744};
2745
181d6902
ID		 2746static const struct data_queue_desc rt61pci_queue_rx = {
2747 .entry_num = RX_ENTRIES,
2748 .data_size = DATA_FRAME_SIZE,
2749 .desc_size = RXD_DESC_SIZE,
b8be63ff 2750 .priv_size = sizeof(struct queue_entry_priv_pci),
181d6902
ID		 2751};
2752
2753static const struct data_queue_desc rt61pci_queue_tx = {
2754 .entry_num = TX_ENTRIES,
2755 .data_size = DATA_FRAME_SIZE,
2756 .desc_size = TXD_DESC_SIZE,
b8be63ff 2757 .priv_size = sizeof(struct queue_entry_priv_pci),
181d6902
ID		 2758};
2759
2760static const struct data_queue_desc rt61pci_queue_bcn = {
6bb40dd1 2761 .entry_num = 4 * BEACON_ENTRIES,
78720897 2762 .data_size = 0, /* No DMA required for beacons */
181d6902 2763 .desc_size = TXINFO_SIZE,
b8be63ff 2764 .priv_size = sizeof(struct queue_entry_priv_pci),
181d6902
ID		 2765};
2766
95ea3627 2767static const struct rt2x00_ops rt61pci_ops = {
2360157c 2768 .name = KBUILD_MODNAME,
6bb40dd1
ID		 2769 .max_sta_intf = 1,
2770 .max_ap_intf = 4,
95ea3627
ID		 2771 .eeprom_size = EEPROM_SIZE,
2772 .rf_size = RF_SIZE,
61448f88 2773 .tx_queues = NUM_TX_QUEUES,
181d6902
ID		 2774 .rx = &rt61pci_queue_rx,
2775 .tx = &rt61pci_queue_tx,
2776 .bcn = &rt61pci_queue_bcn,
95ea3627
ID		 2777 .lib = &rt61pci_rt2x00_ops,
2778 .hw = &rt61pci_mac80211_ops,
2779#ifdef CONFIG_RT2X00_LIB_DEBUGFS
2780 .debugfs = &rt61pci_rt2x00debug,
2781#endif /* CONFIG_RT2X00_LIB_DEBUGFS */
2782};
2783
2784/*
2785 * RT61pci module information.
2786 */
2787static struct pci_device_id rt61pci_device_table[] = {
2788 /* RT2561s */
2789 { PCI_DEVICE(0x1814, 0x0301), PCI_DEVICE_DATA(&rt61pci_ops) },
2790 /* RT2561 v2 */
2791 { PCI_DEVICE(0x1814, 0x0302), PCI_DEVICE_DATA(&rt61pci_ops) },
2792 /* RT2661 */
2793 { PCI_DEVICE(0x1814, 0x0401), PCI_DEVICE_DATA(&rt61pci_ops) },
2794 { 0, }
2795};
2796
2797MODULE_AUTHOR(DRV_PROJECT);
2798MODULE_VERSION(DRV_VERSION);
2799MODULE_DESCRIPTION("Ralink RT61 PCI & PCMCIA Wireless LAN driver.");
2800MODULE_SUPPORTED_DEVICE("Ralink RT2561, RT2561s & RT2661 "
2801 "PCI & PCMCIA chipset based cards");
2802MODULE_DEVICE_TABLE(pci, rt61pci_device_table);
2803MODULE_FIRMWARE(FIRMWARE_RT2561);
2804MODULE_FIRMWARE(FIRMWARE_RT2561s);
2805MODULE_FIRMWARE(FIRMWARE_RT2661);
2806MODULE_LICENSE("GPL");
2807
2808static struct pci_driver rt61pci_driver = {
2360157c 2809 .name = KBUILD_MODNAME,
95ea3627
ID		 2810 .id_table = rt61pci_device_table,
2811 .probe = rt2x00pci_probe,
2812 .remove = __devexit_p(rt2x00pci_remove),
2813 .suspend = rt2x00pci_suspend,
2814 .resume = rt2x00pci_resume,
2815};
2816
2817static int __init rt61pci_init(void)
2818{
2819 return pci_register_driver(&rt61pci_driver);
2820}
2821
2822static void __exit rt61pci_exit(void)
2823{
2824 pci_unregister_driver(&rt61pci_driver);
2825}
2826
2827module_init(rt61pci_init);
2828module_exit(rt61pci_exit);
Linux kernel - Deliverables
This page took 0.385618 seconds and 5 git commands to generate.