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rt2x00: Hardcode TX ack timeout and consume time
[deliverable/linux.git] / drivers / net / wireless / rt2x00 / rt61pci.c
CommitLineData
95ea3627 1/*
4e54c711 2 Copyright (C) 2004 - 2009 rt2x00 SourceForge Project
95ea3627
ID		 3 <http://rt2x00.serialmonkey.com>
4
5 This program is free software; you can redistribute it and/or modify
6 it under the terms of the GNU General Public License as published by
7 the Free Software Foundation; either version 2 of the License, or
8 (at your option) any later version.
9
10 This program is distributed in the hope that it will be useful,
11 but WITHOUT ANY WARRANTY; without even the implied warranty of
12 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 GNU General Public License for more details.
14
15 You should have received a copy of the GNU General Public License
16 along with this program; if not, write to the
17 Free Software Foundation, Inc.,
18 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
19 */
20
21/*
22 Module: rt61pci
23 Abstract: rt61pci device specific routines.
24 Supported chipsets: RT2561, RT2561s, RT2661.
25 */
26
a7f3a06c 27#include <linux/crc-itu-t.h>
95ea3627
ID		 28#include <linux/delay.h>
29#include <linux/etherdevice.h>
30#include <linux/init.h>
31#include <linux/kernel.h>
32#include <linux/module.h>
33#include <linux/pci.h>
34#include <linux/eeprom_93cx6.h>
35
36#include "rt2x00.h"
37#include "rt2x00pci.h"
38#include "rt61pci.h"
39
008c4482
ID		 40/*
41 * Allow hardware encryption to be disabled.
42 */
43static int modparam_nohwcrypt = 0;
44module_param_named(nohwcrypt, modparam_nohwcrypt, bool, S_IRUGO);
45MODULE_PARM_DESC(nohwcrypt, "Disable hardware encryption.");
46
95ea3627
ID		 47/*
48 * Register access.
49 * BBP and RF register require indirect register access,
50 * and use the CSR registers PHY_CSR3 and PHY_CSR4 to achieve this.
51 * These indirect registers work with busy bits,
52 * and we will try maximal REGISTER_BUSY_COUNT times to access
53 * the register while taking a REGISTER_BUSY_DELAY us delay
54 * between each attampt. When the busy bit is still set at that time,
55 * the access attempt is considered to have failed,
56 * and we will print an error.
57 */
c9c3b1a5
ID		 58#define WAIT_FOR_BBP(__dev, __reg) \
59 rt2x00pci_regbusy_read((__dev), PHY_CSR3, PHY_CSR3_BUSY, (__reg))
60#define WAIT_FOR_RF(__dev, __reg) \
61 rt2x00pci_regbusy_read((__dev), PHY_CSR4, PHY_CSR4_BUSY, (__reg))
62#define WAIT_FOR_MCU(__dev, __reg) \
63 rt2x00pci_regbusy_read((__dev), H2M_MAILBOX_CSR, \
64 H2M_MAILBOX_CSR_OWNER, (__reg))
95ea3627 65
0e14f6d3 66static void rt61pci_bbp_write(struct rt2x00_dev *rt2x00dev,
95ea3627
ID		 67 const unsigned int word, const u8 value)
68{
69 u32 reg;
70
8ff48a8b
ID		 71 mutex_lock(&rt2x00dev->csr_mutex);
72
95ea3627 73 /*
c9c3b1a5
ID		 74 * Wait until the BBP becomes available, afterwards we
75 * can safely write the new data into the register.
95ea3627 76 */
c9c3b1a5
ID		 77 if (WAIT_FOR_BBP(rt2x00dev, &reg)) {
78 reg = 0;
79 rt2x00_set_field32(&reg, PHY_CSR3_VALUE, value);
80 rt2x00_set_field32(&reg, PHY_CSR3_REGNUM, word);
81 rt2x00_set_field32(&reg, PHY_CSR3_BUSY, 1);
82 rt2x00_set_field32(&reg, PHY_CSR3_READ_CONTROL, 0);
83
84 rt2x00pci_register_write(rt2x00dev, PHY_CSR3, reg);
85 }
8ff48a8b 86
8ff48a8b 87 mutex_unlock(&rt2x00dev->csr_mutex);
95ea3627
ID		 88}
89
0e14f6d3 90static void rt61pci_bbp_read(struct rt2x00_dev *rt2x00dev,
95ea3627
ID		 91 const unsigned int word, u8 *value)
92{
93 u32 reg;
94
8ff48a8b
ID		 95 mutex_lock(&rt2x00dev->csr_mutex);
96
95ea3627 97 /*
c9c3b1a5
ID		 98 * Wait until the BBP becomes available, afterwards we
99 * can safely write the read request into the register.
100 * After the data has been written, we wait until hardware
101 * returns the correct value, if at any time the register
102 * doesn't become available in time, reg will be 0xffffffff
103 * which means we return 0xff to the caller.
95ea3627 104 */
c9c3b1a5
ID		 105 if (WAIT_FOR_BBP(rt2x00dev, &reg)) {
106 reg = 0;
107 rt2x00_set_field32(&reg, PHY_CSR3_REGNUM, word);
108 rt2x00_set_field32(&reg, PHY_CSR3_BUSY, 1);
109 rt2x00_set_field32(&reg, PHY_CSR3_READ_CONTROL, 1);
95ea3627 110
c9c3b1a5 111 rt2x00pci_register_write(rt2x00dev, PHY_CSR3, reg);
95ea3627 112
c9c3b1a5
ID		 113 WAIT_FOR_BBP(rt2x00dev, &reg);
114 }
95ea3627
ID		 115
116 *value = rt2x00_get_field32(reg, PHY_CSR3_VALUE);
8ff48a8b 117
8ff48a8b 118 mutex_unlock(&rt2x00dev->csr_mutex);
95ea3627
ID		 119}
120
0e14f6d3 121static void rt61pci_rf_write(struct rt2x00_dev *rt2x00dev,
95ea3627
ID		 122 const unsigned int word, const u32 value)
123{
124 u32 reg;
95ea3627 125
8ff48a8b
ID		 126 mutex_lock(&rt2x00dev->csr_mutex);
127
c9c3b1a5
ID		 128 /*
129 * Wait until the RF becomes available, afterwards we
130 * can safely write the new data into the register.
131 */
132 if (WAIT_FOR_RF(rt2x00dev, &reg)) {
133 reg = 0;
134 rt2x00_set_field32(&reg, PHY_CSR4_VALUE, value);
135 rt2x00_set_field32(&reg, PHY_CSR4_NUMBER_OF_BITS, 21);
136 rt2x00_set_field32(&reg, PHY_CSR4_IF_SELECT, 0);
137 rt2x00_set_field32(&reg, PHY_CSR4_BUSY, 1);
138
139 rt2x00pci_register_write(rt2x00dev, PHY_CSR4, reg);
140 rt2x00_rf_write(rt2x00dev, word, value);
95ea3627
ID		 141 }
142
8ff48a8b 143 mutex_unlock(&rt2x00dev->csr_mutex);
95ea3627
ID		 144}
145
0e14f6d3 146static void rt61pci_mcu_request(struct rt2x00_dev *rt2x00dev,
95ea3627
ID		 147 const u8 command, const u8 token,
148 const u8 arg0, const u8 arg1)
149{
150 u32 reg;
151
8ff48a8b
ID		 152 mutex_lock(&rt2x00dev->csr_mutex);
153
c9c3b1a5
ID		 154 /*
155 * Wait until the MCU becomes available, afterwards we
156 * can safely write the new data into the register.
157 */
158 if (WAIT_FOR_MCU(rt2x00dev, &reg)) {
159 rt2x00_set_field32(&reg, H2M_MAILBOX_CSR_OWNER, 1);
160 rt2x00_set_field32(&reg, H2M_MAILBOX_CSR_CMD_TOKEN, token);
161 rt2x00_set_field32(&reg, H2M_MAILBOX_CSR_ARG0, arg0);
162 rt2x00_set_field32(&reg, H2M_MAILBOX_CSR_ARG1, arg1);
163 rt2x00pci_register_write(rt2x00dev, H2M_MAILBOX_CSR, reg);
164
165 rt2x00pci_register_read(rt2x00dev, HOST_CMD_CSR, &reg);
166 rt2x00_set_field32(&reg, HOST_CMD_CSR_HOST_COMMAND, command);
167 rt2x00_set_field32(&reg, HOST_CMD_CSR_INTERRUPT_MCU, 1);
168 rt2x00pci_register_write(rt2x00dev, HOST_CMD_CSR, reg);
169 }
8ff48a8b 170
8ff48a8b
ID		 171 mutex_unlock(&rt2x00dev->csr_mutex);
172
95ea3627
ID		 173}
174
175static void rt61pci_eepromregister_read(struct eeprom_93cx6 *eeprom)
176{
177 struct rt2x00_dev *rt2x00dev = eeprom->data;
178 u32 reg;
179
180 rt2x00pci_register_read(rt2x00dev, E2PROM_CSR, &reg);
181
182 eeprom->reg_data_in = !!rt2x00_get_field32(reg, E2PROM_CSR_DATA_IN);
183 eeprom->reg_data_out = !!rt2x00_get_field32(reg, E2PROM_CSR_DATA_OUT);
184 eeprom->reg_data_clock =
185 !!rt2x00_get_field32(reg, E2PROM_CSR_DATA_CLOCK);
186 eeprom->reg_chip_select =
187 !!rt2x00_get_field32(reg, E2PROM_CSR_CHIP_SELECT);
188}
189
190static void rt61pci_eepromregister_write(struct eeprom_93cx6 *eeprom)
191{
192 struct rt2x00_dev *rt2x00dev = eeprom->data;
193 u32 reg = 0;
194
195 rt2x00_set_field32(&reg, E2PROM_CSR_DATA_IN, !!eeprom->reg_data_in);
196 rt2x00_set_field32(&reg, E2PROM_CSR_DATA_OUT, !!eeprom->reg_data_out);
197 rt2x00_set_field32(&reg, E2PROM_CSR_DATA_CLOCK,
198 !!eeprom->reg_data_clock);
199 rt2x00_set_field32(&reg, E2PROM_CSR_CHIP_SELECT,
200 !!eeprom->reg_chip_select);
201
202 rt2x00pci_register_write(rt2x00dev, E2PROM_CSR, reg);
203}
204
205#ifdef CONFIG_RT2X00_LIB_DEBUGFS
95ea3627
ID		 206static const struct rt2x00debug rt61pci_rt2x00debug = {
207 .owner = THIS_MODULE,
208 .csr = {
743b97ca
ID		 209 .read = rt2x00pci_register_read,
210 .write = rt2x00pci_register_write,
211 .flags = RT2X00DEBUGFS_OFFSET,
212 .word_base = CSR_REG_BASE,
95ea3627
ID		 213 .word_size = sizeof(u32),
214 .word_count = CSR_REG_SIZE / sizeof(u32),
215 },
216 .eeprom = {
217 .read = rt2x00_eeprom_read,
218 .write = rt2x00_eeprom_write,
743b97ca 219 .word_base = EEPROM_BASE,
95ea3627
ID		 220 .word_size = sizeof(u16),
221 .word_count = EEPROM_SIZE / sizeof(u16),
222 },
223 .bbp = {
224 .read = rt61pci_bbp_read,
225 .write = rt61pci_bbp_write,
743b97ca 226 .word_base = BBP_BASE,
95ea3627
ID		 227 .word_size = sizeof(u8),
228 .word_count = BBP_SIZE / sizeof(u8),
229 },
230 .rf = {
231 .read = rt2x00_rf_read,
232 .write = rt61pci_rf_write,
743b97ca 233 .word_base = RF_BASE,
95ea3627
ID		 234 .word_size = sizeof(u32),
235 .word_count = RF_SIZE / sizeof(u32),
236 },
237};
238#endif /* CONFIG_RT2X00_LIB_DEBUGFS */
239
95ea3627
ID		 240static int rt61pci_rfkill_poll(struct rt2x00_dev *rt2x00dev)
241{
242 u32 reg;
243
244 rt2x00pci_register_read(rt2x00dev, MAC_CSR13, &reg);
181d6902 245 return rt2x00_get_field32(reg, MAC_CSR13_BIT5);
95ea3627 246}
95ea3627 247
771fd565 248#ifdef CONFIG_RT2X00_LIB_LEDS
a2e1d52a 249static void rt61pci_brightness_set(struct led_classdev *led_cdev,
a9450b70
ID		 250 enum led_brightness brightness)
251{
252 struct rt2x00_led *led =
253 container_of(led_cdev, struct rt2x00_led, led_dev);
254 unsigned int enabled = brightness != LED_OFF;
255 unsigned int a_mode =
256 (enabled && led->rt2x00dev->curr_band == IEEE80211_BAND_5GHZ);
257 unsigned int bg_mode =
258 (enabled && led->rt2x00dev->curr_band == IEEE80211_BAND_2GHZ);
259
260 if (led->type == LED_TYPE_RADIO) {
261 rt2x00_set_field16(&led->rt2x00dev->led_mcu_reg,
262 MCU_LEDCS_RADIO_STATUS, enabled);
263
264 rt61pci_mcu_request(led->rt2x00dev, MCU_LED, 0xff,
265 (led->rt2x00dev->led_mcu_reg & 0xff),
266 ((led->rt2x00dev->led_mcu_reg >> 8)));
267 } else if (led->type == LED_TYPE_ASSOC) {
268 rt2x00_set_field16(&led->rt2x00dev->led_mcu_reg,
269 MCU_LEDCS_LINK_BG_STATUS, bg_mode);
270 rt2x00_set_field16(&led->rt2x00dev->led_mcu_reg,
271 MCU_LEDCS_LINK_A_STATUS, a_mode);
272
273 rt61pci_mcu_request(led->rt2x00dev, MCU_LED, 0xff,
274 (led->rt2x00dev->led_mcu_reg & 0xff),
275 ((led->rt2x00dev->led_mcu_reg >> 8)));
276 } else if (led->type == LED_TYPE_QUALITY) {
277 /*
278 * The brightness is divided into 6 levels (0 - 5),
279 * this means we need to convert the brightness
280 * argument into the matching level within that range.
281 */
282 rt61pci_mcu_request(led->rt2x00dev, MCU_LED_STRENGTH, 0xff,
283 brightness / (LED_FULL / 6), 0);
284 }
285}
a2e1d52a
ID		 286
287static int rt61pci_blink_set(struct led_classdev *led_cdev,
288 unsigned long *delay_on,
289 unsigned long *delay_off)
290{
291 struct rt2x00_led *led =
292 container_of(led_cdev, struct rt2x00_led, led_dev);
293 u32 reg;
294
295 rt2x00pci_register_read(led->rt2x00dev, MAC_CSR14, &reg);
296 rt2x00_set_field32(&reg, MAC_CSR14_ON_PERIOD, *delay_on);
297 rt2x00_set_field32(&reg, MAC_CSR14_OFF_PERIOD, *delay_off);
298 rt2x00pci_register_write(led->rt2x00dev, MAC_CSR14, reg);
299
300 return 0;
301}
475433be
ID		 302
303static void rt61pci_init_led(struct rt2x00_dev *rt2x00dev,
304 struct rt2x00_led *led,
305 enum led_type type)
306{
307 led->rt2x00dev = rt2x00dev;
308 led->type = type;
309 led->led_dev.brightness_set = rt61pci_brightness_set;
310 led->led_dev.blink_set = rt61pci_blink_set;
311 led->flags = LED_INITIALIZED;
312}
771fd565 313#endif /* CONFIG_RT2X00_LIB_LEDS */
a9450b70 314
95ea3627
ID		 315/*
316 * Configuration handlers.
317 */
61e754f4
ID		 318static int rt61pci_config_shared_key(struct rt2x00_dev *rt2x00dev,
319 struct rt2x00lib_crypto *crypto,
320 struct ieee80211_key_conf *key)
321{
322 struct hw_key_entry key_entry;
323 struct rt2x00_field32 field;
324 u32 mask;
325 u32 reg;
326
327 if (crypto->cmd == SET_KEY) {
328 /*
329 * rt2x00lib can't determine the correct free
330 * key_idx for shared keys. We have 1 register
331 * with key valid bits. The goal is simple, read
332 * the register, if that is full we have no slots
333 * left.
334 * Note that each BSS is allowed to have up to 4
335 * shared keys, so put a mask over the allowed
336 * entries.
337 */
338 mask = (0xf << crypto->bssidx);
339
340 rt2x00pci_register_read(rt2x00dev, SEC_CSR0, &reg);
341 reg &= mask;
342
343 if (reg && reg == mask)
344 return -ENOSPC;
345
acaf908d 346 key->hw_key_idx += reg ? ffz(reg) : 0;
61e754f4
ID		 347
348 /*
349 * Upload key to hardware
350 */
351 memcpy(key_entry.key, crypto->key,
352 sizeof(key_entry.key));
353 memcpy(key_entry.tx_mic, crypto->tx_mic,
354 sizeof(key_entry.tx_mic));
355 memcpy(key_entry.rx_mic, crypto->rx_mic,
356 sizeof(key_entry.rx_mic));
357
358 reg = SHARED_KEY_ENTRY(key->hw_key_idx);
359 rt2x00pci_register_multiwrite(rt2x00dev, reg,
360 &key_entry, sizeof(key_entry));
361
362 /*
363 * The cipher types are stored over 2 registers.
364 * bssidx 0 and 1 keys are stored in SEC_CSR1 and
365 * bssidx 1 and 2 keys are stored in SEC_CSR5.
366 * Using the correct defines correctly will cause overhead,
367 * so just calculate the correct offset.
368 */
369 if (key->hw_key_idx < 8) {
370 field.bit_offset = (3 * key->hw_key_idx);
371 field.bit_mask = 0x7 << field.bit_offset;
372
373 rt2x00pci_register_read(rt2x00dev, SEC_CSR1, &reg);
374 rt2x00_set_field32(&reg, field, crypto->cipher);
375 rt2x00pci_register_write(rt2x00dev, SEC_CSR1, reg);
376 } else {
377 field.bit_offset = (3 * (key->hw_key_idx - 8));
378 field.bit_mask = 0x7 << field.bit_offset;
379
380 rt2x00pci_register_read(rt2x00dev, SEC_CSR5, &reg);
381 rt2x00_set_field32(&reg, field, crypto->cipher);
382 rt2x00pci_register_write(rt2x00dev, SEC_CSR5, reg);
383 }
384
385 /*
386 * The driver does not support the IV/EIV generation
387 * in hardware. However it doesn't support the IV/EIV
388 * inside the ieee80211 frame either, but requires it
389 * to be provided seperately for the descriptor.
390 * rt2x00lib will cut the IV/EIV data out of all frames
391 * given to us by mac80211, but we must tell mac80211
392 * to generate the IV/EIV data.
393 */
394 key->flags |= IEEE80211_KEY_FLAG_GENERATE_IV;
395 }
396
397 /*
398 * SEC_CSR0 contains only single-bit fields to indicate
399 * a particular key is valid. Because using the FIELD32()
400 * defines directly will cause a lot of overhead we use
401 * a calculation to determine the correct bit directly.
402 */
403 mask = 1 << key->hw_key_idx;
404
405 rt2x00pci_register_read(rt2x00dev, SEC_CSR0, &reg);
406 if (crypto->cmd == SET_KEY)
407 reg |= mask;
408 else if (crypto->cmd == DISABLE_KEY)
409 reg &= ~mask;
410 rt2x00pci_register_write(rt2x00dev, SEC_CSR0, reg);
411
412 return 0;
413}
414
415static int rt61pci_config_pairwise_key(struct rt2x00_dev *rt2x00dev,
416 struct rt2x00lib_crypto *crypto,
417 struct ieee80211_key_conf *key)
418{
419 struct hw_pairwise_ta_entry addr_entry;
420 struct hw_key_entry key_entry;
421 u32 mask;
422 u32 reg;
423
424 if (crypto->cmd == SET_KEY) {
425 /*
426 * rt2x00lib can't determine the correct free
427 * key_idx for pairwise keys. We have 2 registers
428 * with key valid bits. The goal is simple, read
429 * the first register, if that is full move to
430 * the next register.
431 * When both registers are full, we drop the key,
432 * otherwise we use the first invalid entry.
433 */
434 rt2x00pci_register_read(rt2x00dev, SEC_CSR2, &reg);
435 if (reg && reg == ~0) {
436 key->hw_key_idx = 32;
437 rt2x00pci_register_read(rt2x00dev, SEC_CSR3, &reg);
438 if (reg && reg == ~0)
439 return -ENOSPC;
440 }
441
acaf908d 442 key->hw_key_idx += reg ? ffz(reg) : 0;
61e754f4
ID		 443
444 /*
445 * Upload key to hardware
446 */
447 memcpy(key_entry.key, crypto->key,
448 sizeof(key_entry.key));
449 memcpy(key_entry.tx_mic, crypto->tx_mic,
450 sizeof(key_entry.tx_mic));
451 memcpy(key_entry.rx_mic, crypto->rx_mic,
452 sizeof(key_entry.rx_mic));
453
454 memset(&addr_entry, 0, sizeof(addr_entry));
455 memcpy(&addr_entry, crypto->address, ETH_ALEN);
456 addr_entry.cipher = crypto->cipher;
457
458 reg = PAIRWISE_KEY_ENTRY(key->hw_key_idx);
459 rt2x00pci_register_multiwrite(rt2x00dev, reg,
460 &key_entry, sizeof(key_entry));
461
462 reg = PAIRWISE_TA_ENTRY(key->hw_key_idx);
463 rt2x00pci_register_multiwrite(rt2x00dev, reg,
464 &addr_entry, sizeof(addr_entry));
465
466 /*
467 * Enable pairwise lookup table for given BSS idx,
468 * without this received frames will not be decrypted
469 * by the hardware.
470 */
471 rt2x00pci_register_read(rt2x00dev, SEC_CSR4, &reg);
472 reg |= (1 << crypto->bssidx);
473 rt2x00pci_register_write(rt2x00dev, SEC_CSR4, reg);
474
475 /*
476 * The driver does not support the IV/EIV generation
477 * in hardware. However it doesn't support the IV/EIV
478 * inside the ieee80211 frame either, but requires it
479 * to be provided seperately for the descriptor.
480 * rt2x00lib will cut the IV/EIV data out of all frames
481 * given to us by mac80211, but we must tell mac80211
482 * to generate the IV/EIV data.
483 */
484 key->flags |= IEEE80211_KEY_FLAG_GENERATE_IV;
485 }
486
487 /*
488 * SEC_CSR2 and SEC_CSR3 contain only single-bit fields to indicate
489 * a particular key is valid. Because using the FIELD32()
490 * defines directly will cause a lot of overhead we use
491 * a calculation to determine the correct bit directly.
492 */
493 if (key->hw_key_idx < 32) {
494 mask = 1 << key->hw_key_idx;
495
496 rt2x00pci_register_read(rt2x00dev, SEC_CSR2, &reg);
497 if (crypto->cmd == SET_KEY)
498 reg |= mask;
499 else if (crypto->cmd == DISABLE_KEY)
500 reg &= ~mask;
501 rt2x00pci_register_write(rt2x00dev, SEC_CSR2, reg);
502 } else {
503 mask = 1 << (key->hw_key_idx - 32);
504
505 rt2x00pci_register_read(rt2x00dev, SEC_CSR3, &reg);
506 if (crypto->cmd == SET_KEY)
507 reg |= mask;
508 else if (crypto->cmd == DISABLE_KEY)
509 reg &= ~mask;
510 rt2x00pci_register_write(rt2x00dev, SEC_CSR3, reg);
511 }
512
513 return 0;
514}
515
3a643d24
ID		 516static void rt61pci_config_filter(struct rt2x00_dev *rt2x00dev,
517 const unsigned int filter_flags)
518{
519 u32 reg;
520
521 /*
522 * Start configuration steps.
523 * Note that the version error will always be dropped
524 * and broadcast frames will always be accepted since
525 * there is no filter for it at this time.
526 */
527 rt2x00pci_register_read(rt2x00dev, TXRX_CSR0, &reg);
528 rt2x00_set_field32(&reg, TXRX_CSR0_DROP_CRC,
529 !(filter_flags & FIF_FCSFAIL));
530 rt2x00_set_field32(&reg, TXRX_CSR0_DROP_PHYSICAL,
531 !(filter_flags & FIF_PLCPFAIL));
532 rt2x00_set_field32(&reg, TXRX_CSR0_DROP_CONTROL,
1afcfd54 533 !(filter_flags & (FIF_CONTROL | FIF_PSPOLL)));
3a643d24
ID		 534 rt2x00_set_field32(&reg, TXRX_CSR0_DROP_NOT_TO_ME,
535 !(filter_flags & FIF_PROMISC_IN_BSS));
536 rt2x00_set_field32(&reg, TXRX_CSR0_DROP_TO_DS,
e0b005fa
ID		 537 !(filter_flags & FIF_PROMISC_IN_BSS) &&
538 !rt2x00dev->intf_ap_count);
3a643d24
ID		 539 rt2x00_set_field32(&reg, TXRX_CSR0_DROP_VERSION_ERROR, 1);
540 rt2x00_set_field32(&reg, TXRX_CSR0_DROP_MULTICAST,
541 !(filter_flags & FIF_ALLMULTI));
542 rt2x00_set_field32(&reg, TXRX_CSR0_DROP_BROADCAST, 0);
543 rt2x00_set_field32(&reg, TXRX_CSR0_DROP_ACK_CTS,
544 !(filter_flags & FIF_CONTROL));
545 rt2x00pci_register_write(rt2x00dev, TXRX_CSR0, reg);
546}
547
6bb40dd1
ID		 548static void rt61pci_config_intf(struct rt2x00_dev *rt2x00dev,
549 struct rt2x00_intf *intf,
550 struct rt2x00intf_conf *conf,
551 const unsigned int flags)
95ea3627 552{
6bb40dd1
ID		 553 unsigned int beacon_base;
554 u32 reg;
95ea3627 555
6bb40dd1
ID		 556 if (flags & CONFIG_UPDATE_TYPE) {
557 /*
558 * Clear current synchronisation setup.
559 * For the Beacon base registers we only need to clear
560 * the first byte since that byte contains the VALID and OWNER
561 * bits which (when set to 0) will invalidate the entire beacon.
562 */
563 beacon_base = HW_BEACON_OFFSET(intf->beacon->entry_idx);
6bb40dd1 564 rt2x00pci_register_write(rt2x00dev, beacon_base, 0);
95ea3627 565
6bb40dd1
ID		 566 /*
567 * Enable synchronisation.
568 */
569 rt2x00pci_register_read(rt2x00dev, TXRX_CSR9, &reg);
fd3c91c5 570 rt2x00_set_field32(&reg, TXRX_CSR9_TSF_TICKING, 1);
6bb40dd1 571 rt2x00_set_field32(&reg, TXRX_CSR9_TSF_SYNC, conf->sync);
fd3c91c5 572 rt2x00_set_field32(&reg, TXRX_CSR9_TBTT_ENABLE, 1);
6bb40dd1
ID		 573 rt2x00pci_register_write(rt2x00dev, TXRX_CSR9, reg);
574 }
95ea3627 575
6bb40dd1
ID		 576 if (flags & CONFIG_UPDATE_MAC) {
577 reg = le32_to_cpu(conf->mac[1]);
578 rt2x00_set_field32(&reg, MAC_CSR3_UNICAST_TO_ME_MASK, 0xff);
579 conf->mac[1] = cpu_to_le32(reg);
95ea3627 580
6bb40dd1
ID		 581 rt2x00pci_register_multiwrite(rt2x00dev, MAC_CSR2,
582 conf->mac, sizeof(conf->mac));
583 }
95ea3627 584
6bb40dd1
ID		 585 if (flags & CONFIG_UPDATE_BSSID) {
586 reg = le32_to_cpu(conf->bssid[1]);
587 rt2x00_set_field32(&reg, MAC_CSR5_BSS_ID_MASK, 3);
588 conf->bssid[1] = cpu_to_le32(reg);
95ea3627 589
6bb40dd1
ID		 590 rt2x00pci_register_multiwrite(rt2x00dev, MAC_CSR4,
591 conf->bssid, sizeof(conf->bssid));
592 }
95ea3627
ID		 593}
594
3a643d24
ID		 595static void rt61pci_config_erp(struct rt2x00_dev *rt2x00dev,
596 struct rt2x00lib_erp *erp)
95ea3627 597{
95ea3627 598 u32 reg;
95ea3627
ID		 599
600 rt2x00pci_register_read(rt2x00dev, TXRX_CSR0, &reg);
4789666e 601 rt2x00_set_field32(&reg, TXRX_CSR0_RX_ACK_TIMEOUT, 0x32);
8a566afe 602 rt2x00_set_field32(&reg, TXRX_CSR0_TSF_OFFSET, IEEE80211_HEADER);
95ea3627
ID		 603 rt2x00pci_register_write(rt2x00dev, TXRX_CSR0, reg);
604
605 rt2x00pci_register_read(rt2x00dev, TXRX_CSR4, &reg);
8a566afe 606 rt2x00_set_field32(&reg, TXRX_CSR4_AUTORESPOND_ENABLE, 1);
4f5af6eb 607 rt2x00_set_field32(&reg, TXRX_CSR4_AUTORESPOND_PREAMBLE,
72810379 608 !!erp->short_preamble);
95ea3627 609 rt2x00pci_register_write(rt2x00dev, TXRX_CSR4, reg);
95ea3627 610
e4ea1c40 611 rt2x00pci_register_write(rt2x00dev, TXRX_CSR5, erp->basic_rates);
95ea3627 612
8a566afe
ID		 613 rt2x00pci_register_read(rt2x00dev, TXRX_CSR9, &reg);
614 rt2x00_set_field32(&reg, TXRX_CSR9_BEACON_INTERVAL,
615 erp->beacon_int * 16);
616 rt2x00pci_register_write(rt2x00dev, TXRX_CSR9, reg);
617
e4ea1c40
ID		 618 rt2x00pci_register_read(rt2x00dev, MAC_CSR9, &reg);
619 rt2x00_set_field32(&reg, MAC_CSR9_SLOT_TIME, erp->slot_time);
620 rt2x00pci_register_write(rt2x00dev, MAC_CSR9, reg);
95ea3627 621
e4ea1c40
ID		 622 rt2x00pci_register_read(rt2x00dev, MAC_CSR8, &reg);
623 rt2x00_set_field32(&reg, MAC_CSR8_SIFS, erp->sifs);
624 rt2x00_set_field32(&reg, MAC_CSR8_SIFS_AFTER_RX_OFDM, 3);
625 rt2x00_set_field32(&reg, MAC_CSR8_EIFS, erp->eifs);
626 rt2x00pci_register_write(rt2x00dev, MAC_CSR8, reg);
95ea3627
ID		 627}
628
629static void rt61pci_config_antenna_5x(struct rt2x00_dev *rt2x00dev,
addc81bd 630 struct antenna_setup *ant)
95ea3627
ID		 631{
632 u8 r3;
633 u8 r4;
634 u8 r77;
635
636 rt61pci_bbp_read(rt2x00dev, 3, &r3);
637 rt61pci_bbp_read(rt2x00dev, 4, &r4);
638 rt61pci_bbp_read(rt2x00dev, 77, &r77);
639
640 rt2x00_set_field8(&r3, BBP_R3_SMART_MODE,
acaa410d 641 rt2x00_rf(&rt2x00dev->chip, RF5325));
e4cd2ff8
ID		 642
643 /*
644 * Configure the RX antenna.
645 */
addc81bd 646 switch (ant->rx) {
95ea3627 647 case ANTENNA_HW_DIVERSITY:
acaa410d 648 rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA_CONTROL, 2);
95ea3627 649 rt2x00_set_field8(&r4, BBP_R4_RX_FRAME_END,
8318d78a 650 (rt2x00dev->curr_band != IEEE80211_BAND_5GHZ));
95ea3627
ID		 651 break;
652 case ANTENNA_A:
acaa410d 653 rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA_CONTROL, 1);
95ea3627 654 rt2x00_set_field8(&r4, BBP_R4_RX_FRAME_END, 0);
8318d78a 655 if (rt2x00dev->curr_band == IEEE80211_BAND_5GHZ)
acaa410d
MN		 656 rt2x00_set_field8(&r77, BBP_R77_RX_ANTENNA, 0);
657 else
658 rt2x00_set_field8(&r77, BBP_R77_RX_ANTENNA, 3);
95ea3627
ID		 659 break;
660 case ANTENNA_B:
a4fe07d9 661 default:
acaa410d 662 rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA_CONTROL, 1);
95ea3627 663 rt2x00_set_field8(&r4, BBP_R4_RX_FRAME_END, 0);
8318d78a 664 if (rt2x00dev->curr_band == IEEE80211_BAND_5GHZ)
acaa410d
MN		 665 rt2x00_set_field8(&r77, BBP_R77_RX_ANTENNA, 3);
666 else
667 rt2x00_set_field8(&r77, BBP_R77_RX_ANTENNA, 0);
95ea3627
ID		 668 break;
669 }
670
671 rt61pci_bbp_write(rt2x00dev, 77, r77);
672 rt61pci_bbp_write(rt2x00dev, 3, r3);
673 rt61pci_bbp_write(rt2x00dev, 4, r4);
674}
675
676static void rt61pci_config_antenna_2x(struct rt2x00_dev *rt2x00dev,
addc81bd 677 struct antenna_setup *ant)
95ea3627
ID		 678{
679 u8 r3;
680 u8 r4;
681 u8 r77;
682
683 rt61pci_bbp_read(rt2x00dev, 3, &r3);
684 rt61pci_bbp_read(rt2x00dev, 4, &r4);
685 rt61pci_bbp_read(rt2x00dev, 77, &r77);
686
687 rt2x00_set_field8(&r3, BBP_R3_SMART_MODE,
acaa410d 688 rt2x00_rf(&rt2x00dev->chip, RF2529));
95ea3627
ID		 689 rt2x00_set_field8(&r4, BBP_R4_RX_FRAME_END,
690 !test_bit(CONFIG_FRAME_TYPE, &rt2x00dev->flags));
691
e4cd2ff8
ID		 692 /*
693 * Configure the RX antenna.
694 */
addc81bd 695 switch (ant->rx) {
95ea3627 696 case ANTENNA_HW_DIVERSITY:
acaa410d 697 rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA_CONTROL, 2);
95ea3627
ID		 698 break;
699 case ANTENNA_A:
acaa410d
MN		 700 rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA_CONTROL, 1);
701 rt2x00_set_field8(&r77, BBP_R77_RX_ANTENNA, 3);
95ea3627
ID		 702 break;
703 case ANTENNA_B:
a4fe07d9 704 default:
acaa410d
MN		 705 rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA_CONTROL, 1);
706 rt2x00_set_field8(&r77, BBP_R77_RX_ANTENNA, 0);
95ea3627
ID		 707 break;
708 }
709
710 rt61pci_bbp_write(rt2x00dev, 77, r77);
711 rt61pci_bbp_write(rt2x00dev, 3, r3);
712 rt61pci_bbp_write(rt2x00dev, 4, r4);
713}
714
715static void rt61pci_config_antenna_2529_rx(struct rt2x00_dev *rt2x00dev,
716 const int p1, const int p2)
717{
718 u32 reg;
719
720 rt2x00pci_register_read(rt2x00dev, MAC_CSR13, &reg);
721
acaa410d
MN		 722 rt2x00_set_field32(&reg, MAC_CSR13_BIT4, p1);
723 rt2x00_set_field32(&reg, MAC_CSR13_BIT12, 0);
724
725 rt2x00_set_field32(&reg, MAC_CSR13_BIT3, !p2);
726 rt2x00_set_field32(&reg, MAC_CSR13_BIT11, 0);
727
728 rt2x00pci_register_write(rt2x00dev, MAC_CSR13, reg);
95ea3627
ID		 729}
730
731static void rt61pci_config_antenna_2529(struct rt2x00_dev *rt2x00dev,
addc81bd 732 struct antenna_setup *ant)
95ea3627 733{
95ea3627
ID		 734 u8 r3;
735 u8 r4;
736 u8 r77;
737
738 rt61pci_bbp_read(rt2x00dev, 3, &r3);
739 rt61pci_bbp_read(rt2x00dev, 4, &r4);
740 rt61pci_bbp_read(rt2x00dev, 77, &r77);
e4cd2ff8 741
e4cd2ff8
ID		 742 /*
743 * Configure the RX antenna.
744 */
745 switch (ant->rx) {
746 case ANTENNA_A:
acaa410d
MN		 747 rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA_CONTROL, 1);
748 rt2x00_set_field8(&r77, BBP_R77_RX_ANTENNA, 0);
749 rt61pci_config_antenna_2529_rx(rt2x00dev, 0, 0);
e4cd2ff8 750 break;
e4cd2ff8
ID		 751 case ANTENNA_HW_DIVERSITY:
752 /*
a4fe07d9
ID		 753 * FIXME: Antenna selection for the rf 2529 is very confusing
754 * in the legacy driver. Just default to antenna B until the
755 * legacy code can be properly translated into rt2x00 code.
e4cd2ff8
ID		 756 */
757 case ANTENNA_B:
a4fe07d9 758 default:
acaa410d
MN		 759 rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA_CONTROL, 1);
760 rt2x00_set_field8(&r77, BBP_R77_RX_ANTENNA, 3);
761 rt61pci_config_antenna_2529_rx(rt2x00dev, 1, 1);
e4cd2ff8
ID		 762 break;
763 }
764
e4cd2ff8 765 rt61pci_bbp_write(rt2x00dev, 77, r77);
95ea3627
ID		 766 rt61pci_bbp_write(rt2x00dev, 3, r3);
767 rt61pci_bbp_write(rt2x00dev, 4, r4);
768}
769
770struct antenna_sel {
771 u8 word;
772 /*
773 * value[0] -> non-LNA
774 * value[1] -> LNA
775 */
776 u8 value[2];
777};
778
779static const struct antenna_sel antenna_sel_a[] = {
780 { 96, { 0x58, 0x78 } },
781 { 104, { 0x38, 0x48 } },
782 { 75, { 0xfe, 0x80 } },
783 { 86, { 0xfe, 0x80 } },
784 { 88, { 0xfe, 0x80 } },
785 { 35, { 0x60, 0x60 } },
786 { 97, { 0x58, 0x58 } },
787 { 98, { 0x58, 0x58 } },
788};
789
790static const struct antenna_sel antenna_sel_bg[] = {
791 { 96, { 0x48, 0x68 } },
792 { 104, { 0x2c, 0x3c } },
793 { 75, { 0xfe, 0x80 } },
794 { 86, { 0xfe, 0x80 } },
795 { 88, { 0xfe, 0x80 } },
796 { 35, { 0x50, 0x50 } },
797 { 97, { 0x48, 0x48 } },
798 { 98, { 0x48, 0x48 } },
799};
800
e4ea1c40
ID		 801static void rt61pci_config_ant(struct rt2x00_dev *rt2x00dev,
802 struct antenna_setup *ant)
95ea3627
ID		 803{
804 const struct antenna_sel *sel;
805 unsigned int lna;
806 unsigned int i;
807 u32 reg;
808
a4fe07d9
ID		 809 /*
810 * We should never come here because rt2x00lib is supposed
811 * to catch this and send us the correct antenna explicitely.
812 */
813 BUG_ON(ant->rx == ANTENNA_SW_DIVERSITY ||
814 ant->tx == ANTENNA_SW_DIVERSITY);
815
8318d78a 816 if (rt2x00dev->curr_band == IEEE80211_BAND_5GHZ) {
95ea3627
ID		 817 sel = antenna_sel_a;
818 lna = test_bit(CONFIG_EXTERNAL_LNA_A, &rt2x00dev->flags);
95ea3627
ID		 819 } else {
820 sel = antenna_sel_bg;
821 lna = test_bit(CONFIG_EXTERNAL_LNA_BG, &rt2x00dev->flags);
95ea3627
ID		 822 }
823
acaa410d
MN		 824 for (i = 0; i < ARRAY_SIZE(antenna_sel_a); i++)
825 rt61pci_bbp_write(rt2x00dev, sel[i].word, sel[i].value[lna]);
826
827 rt2x00pci_register_read(rt2x00dev, PHY_CSR0, &reg);
828
ddc827f9 829 rt2x00_set_field32(&reg, PHY_CSR0_PA_PE_BG,
8318d78a 830 rt2x00dev->curr_band == IEEE80211_BAND_2GHZ);
ddc827f9 831 rt2x00_set_field32(&reg, PHY_CSR0_PA_PE_A,
8318d78a 832 rt2x00dev->curr_band == IEEE80211_BAND_5GHZ);
ddc827f9 833
95ea3627
ID		 834 rt2x00pci_register_write(rt2x00dev, PHY_CSR0, reg);
835
836 if (rt2x00_rf(&rt2x00dev->chip, RF5225) ||
837 rt2x00_rf(&rt2x00dev->chip, RF5325))
addc81bd 838 rt61pci_config_antenna_5x(rt2x00dev, ant);
95ea3627 839 else if (rt2x00_rf(&rt2x00dev->chip, RF2527))
addc81bd 840 rt61pci_config_antenna_2x(rt2x00dev, ant);
95ea3627
ID		 841 else if (rt2x00_rf(&rt2x00dev->chip, RF2529)) {
842 if (test_bit(CONFIG_DOUBLE_ANTENNA, &rt2x00dev->flags))
addc81bd 843 rt61pci_config_antenna_2x(rt2x00dev, ant);
95ea3627 844 else
addc81bd 845 rt61pci_config_antenna_2529(rt2x00dev, ant);
95ea3627
ID		 846 }
847}
848
e4ea1c40
ID		 849static void rt61pci_config_lna_gain(struct rt2x00_dev *rt2x00dev,
850 struct rt2x00lib_conf *libconf)
851{
852 u16 eeprom;
853 short lna_gain = 0;
854
855 if (libconf->conf->channel->band == IEEE80211_BAND_2GHZ) {
856 if (test_bit(CONFIG_EXTERNAL_LNA_BG, &rt2x00dev->flags))
857 lna_gain += 14;
858
859 rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_OFFSET_BG, &eeprom);
860 lna_gain -= rt2x00_get_field16(eeprom, EEPROM_RSSI_OFFSET_BG_1);
861 } else {
862 if (test_bit(CONFIG_EXTERNAL_LNA_A, &rt2x00dev->flags))
863 lna_gain += 14;
864
865 rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_OFFSET_A, &eeprom);
866 lna_gain -= rt2x00_get_field16(eeprom, EEPROM_RSSI_OFFSET_A_1);
867 }
868
869 rt2x00dev->lna_gain = lna_gain;
870}
871
872static void rt61pci_config_channel(struct rt2x00_dev *rt2x00dev,
873 struct rf_channel *rf, const int txpower)
874{
875 u8 r3;
876 u8 r94;
877 u8 smart;
878
879 rt2x00_set_field32(&rf->rf3, RF3_TXPOWER, TXPOWER_TO_DEV(txpower));
880 rt2x00_set_field32(&rf->rf4, RF4_FREQ_OFFSET, rt2x00dev->freq_offset);
881
882 smart = !(rt2x00_rf(&rt2x00dev->chip, RF5225) ||
883 rt2x00_rf(&rt2x00dev->chip, RF2527));
884
885 rt61pci_bbp_read(rt2x00dev, 3, &r3);
886 rt2x00_set_field8(&r3, BBP_R3_SMART_MODE, smart);
887 rt61pci_bbp_write(rt2x00dev, 3, r3);
888
889 r94 = 6;
890 if (txpower > MAX_TXPOWER && txpower <= (MAX_TXPOWER + r94))
891 r94 += txpower - MAX_TXPOWER;
892 else if (txpower < MIN_TXPOWER && txpower >= (MIN_TXPOWER - r94))
893 r94 += txpower;
894 rt61pci_bbp_write(rt2x00dev, 94, r94);
895
896 rt61pci_rf_write(rt2x00dev, 1, rf->rf1);
897 rt61pci_rf_write(rt2x00dev, 2, rf->rf2);
898 rt61pci_rf_write(rt2x00dev, 3, rf->rf3 & ~0x00000004);
899 rt61pci_rf_write(rt2x00dev, 4, rf->rf4);
900
901 udelay(200);
902
903 rt61pci_rf_write(rt2x00dev, 1, rf->rf1);
904 rt61pci_rf_write(rt2x00dev, 2, rf->rf2);
905 rt61pci_rf_write(rt2x00dev, 3, rf->rf3 | 0x00000004);
906 rt61pci_rf_write(rt2x00dev, 4, rf->rf4);
907
908 udelay(200);
909
910 rt61pci_rf_write(rt2x00dev, 1, rf->rf1);
911 rt61pci_rf_write(rt2x00dev, 2, rf->rf2);
912 rt61pci_rf_write(rt2x00dev, 3, rf->rf3 & ~0x00000004);
913 rt61pci_rf_write(rt2x00dev, 4, rf->rf4);
914
915 msleep(1);
916}
917
918static void rt61pci_config_txpower(struct rt2x00_dev *rt2x00dev,
919 const int txpower)
920{
921 struct rf_channel rf;
922
923 rt2x00_rf_read(rt2x00dev, 1, &rf.rf1);
924 rt2x00_rf_read(rt2x00dev, 2, &rf.rf2);
925 rt2x00_rf_read(rt2x00dev, 3, &rf.rf3);
926 rt2x00_rf_read(rt2x00dev, 4, &rf.rf4);
927
928 rt61pci_config_channel(rt2x00dev, &rf, txpower);
929}
930
931static void rt61pci_config_retry_limit(struct rt2x00_dev *rt2x00dev,
5c58ee51 932 struct rt2x00lib_conf *libconf)
95ea3627
ID		 933{
934 u32 reg;
935
e4ea1c40
ID		 936 rt2x00pci_register_read(rt2x00dev, TXRX_CSR4, &reg);
937 rt2x00_set_field32(&reg, TXRX_CSR4_LONG_RETRY_LIMIT,
938 libconf->conf->long_frame_max_tx_count);
939 rt2x00_set_field32(&reg, TXRX_CSR4_SHORT_RETRY_LIMIT,
940 libconf->conf->short_frame_max_tx_count);
941 rt2x00pci_register_write(rt2x00dev, TXRX_CSR4, reg);
942}
95ea3627 943
7d7f19cc
ID		 944static void rt61pci_config_ps(struct rt2x00_dev *rt2x00dev,
945 struct rt2x00lib_conf *libconf)
946{
947 enum dev_state state =
948 (libconf->conf->flags & IEEE80211_CONF_PS) ?
949 STATE_SLEEP : STATE_AWAKE;
950 u32 reg;
951
952 if (state == STATE_SLEEP) {
953 rt2x00pci_register_read(rt2x00dev, MAC_CSR11, &reg);
954 rt2x00_set_field32(&reg, MAC_CSR11_DELAY_AFTER_TBCN,
6b347bff 955 rt2x00dev->beacon_int - 10);
7d7f19cc
ID		 956 rt2x00_set_field32(&reg, MAC_CSR11_TBCN_BEFORE_WAKEUP,
957 libconf->conf->listen_interval - 1);
958 rt2x00_set_field32(&reg, MAC_CSR11_WAKEUP_LATENCY, 5);
959
960 /* We must first disable autowake before it can be enabled */
961 rt2x00_set_field32(&reg, MAC_CSR11_AUTOWAKE, 0);
962 rt2x00pci_register_write(rt2x00dev, MAC_CSR11, reg);
963
964 rt2x00_set_field32(&reg, MAC_CSR11_AUTOWAKE, 1);
965 rt2x00pci_register_write(rt2x00dev, MAC_CSR11, reg);
966
967 rt2x00pci_register_write(rt2x00dev, SOFT_RESET_CSR, 0x00000005);
968 rt2x00pci_register_write(rt2x00dev, IO_CNTL_CSR, 0x0000001c);
969 rt2x00pci_register_write(rt2x00dev, PCI_USEC_CSR, 0x00000060);
970
971 rt61pci_mcu_request(rt2x00dev, MCU_SLEEP, 0xff, 0, 0);
972 } else {
973 rt2x00pci_register_read(rt2x00dev, MAC_CSR11, &reg);
974 rt2x00_set_field32(&reg, MAC_CSR11_DELAY_AFTER_TBCN, 0);
975 rt2x00_set_field32(&reg, MAC_CSR11_TBCN_BEFORE_WAKEUP, 0);
976 rt2x00_set_field32(&reg, MAC_CSR11_AUTOWAKE, 0);
977 rt2x00_set_field32(&reg, MAC_CSR11_WAKEUP_LATENCY, 0);
978 rt2x00pci_register_write(rt2x00dev, MAC_CSR11, reg);
979
980 rt2x00pci_register_write(rt2x00dev, SOFT_RESET_CSR, 0x00000007);
981 rt2x00pci_register_write(rt2x00dev, IO_CNTL_CSR, 0x00000018);
982 rt2x00pci_register_write(rt2x00dev, PCI_USEC_CSR, 0x00000020);
983
984 rt61pci_mcu_request(rt2x00dev, MCU_WAKEUP, 0xff, 0, 0);
985 }
986}
987
95ea3627 988static void rt61pci_config(struct rt2x00_dev *rt2x00dev,
6bb40dd1
ID		 989 struct rt2x00lib_conf *libconf,
990 const unsigned int flags)
95ea3627 991{
ba2ab471
ID		 992 /* Always recalculate LNA gain before changing configuration */
993 rt61pci_config_lna_gain(rt2x00dev, libconf);
994
e4ea1c40 995 if (flags & IEEE80211_CONF_CHANGE_CHANNEL)
5c58ee51
ID		 996 rt61pci_config_channel(rt2x00dev, &libconf->rf,
997 libconf->conf->power_level);
e4ea1c40
ID		 998 if ((flags & IEEE80211_CONF_CHANGE_POWER) &&
999 !(flags & IEEE80211_CONF_CHANGE_CHANNEL))
5c58ee51 1000 rt61pci_config_txpower(rt2x00dev, libconf->conf->power_level);
e4ea1c40
ID		 1001 if (flags & IEEE80211_CONF_CHANGE_RETRY_LIMITS)
1002 rt61pci_config_retry_limit(rt2x00dev, libconf);
7d7f19cc
ID		 1003 if (flags & IEEE80211_CONF_CHANGE_PS)
1004 rt61pci_config_ps(rt2x00dev, libconf);
95ea3627
ID		 1005}
1006
95ea3627
ID		 1007/*
1008 * Link tuning
1009 */
ebcf26da
ID		 1010static void rt61pci_link_stats(struct rt2x00_dev *rt2x00dev,
1011 struct link_qual *qual)
95ea3627
ID		 1012{
1013 u32 reg;
1014
1015 /*
1016 * Update FCS error count from register.
1017 */
1018 rt2x00pci_register_read(rt2x00dev, STA_CSR0, &reg);
ebcf26da 1019 qual->rx_failed = rt2x00_get_field32(reg, STA_CSR0_FCS_ERROR);
95ea3627
ID		 1020
1021 /*
1022 * Update False CCA count from register.
1023 */
1024 rt2x00pci_register_read(rt2x00dev, STA_CSR1, &reg);
ebcf26da 1025 qual->false_cca = rt2x00_get_field32(reg, STA_CSR1_FALSE_CCA_ERROR);
95ea3627
ID		 1026}
1027
5352ff65
ID		 1028static inline void rt61pci_set_vgc(struct rt2x00_dev *rt2x00dev,
1029 struct link_qual *qual, u8 vgc_level)
eb20b4e8 1030{
5352ff65 1031 if (qual->vgc_level != vgc_level) {
eb20b4e8 1032 rt61pci_bbp_write(rt2x00dev, 17, vgc_level);
5352ff65
ID		 1033 qual->vgc_level = vgc_level;
1034 qual->vgc_level_reg = vgc_level;
eb20b4e8
ID		 1035 }
1036}
1037
5352ff65
ID		 1038static void rt61pci_reset_tuner(struct rt2x00_dev *rt2x00dev,
1039 struct link_qual *qual)
95ea3627 1040{
5352ff65 1041 rt61pci_set_vgc(rt2x00dev, qual, 0x20);
95ea3627
ID		 1042}
1043
5352ff65
ID		 1044static void rt61pci_link_tuner(struct rt2x00_dev *rt2x00dev,
1045 struct link_qual *qual, const u32 count)
95ea3627 1046{
95ea3627
ID		 1047 u8 up_bound;
1048 u8 low_bound;
1049
95ea3627
ID		 1050 /*
1051 * Determine r17 bounds.
1052 */
1497074a 1053 if (rt2x00dev->rx_status.band == IEEE80211_BAND_5GHZ) {
95ea3627
ID		 1054 low_bound = 0x28;
1055 up_bound = 0x48;
1056 if (test_bit(CONFIG_EXTERNAL_LNA_A, &rt2x00dev->flags)) {
1057 low_bound += 0x10;
1058 up_bound += 0x10;
1059 }
1060 } else {
1061 low_bound = 0x20;
1062 up_bound = 0x40;
1063 if (test_bit(CONFIG_EXTERNAL_LNA_BG, &rt2x00dev->flags)) {
1064 low_bound += 0x10;
1065 up_bound += 0x10;
1066 }
1067 }
1068
6bb40dd1
ID		 1069 /*
1070 * If we are not associated, we should go straight to the
1071 * dynamic CCA tuning.
1072 */
1073 if (!rt2x00dev->intf_associated)
1074 goto dynamic_cca_tune;
1075
95ea3627
ID		 1076 /*
1077 * Special big-R17 for very short distance
1078 */
5352ff65
ID		 1079 if (qual->rssi >= -35) {
1080 rt61pci_set_vgc(rt2x00dev, qual, 0x60);
95ea3627
ID		 1081 return;
1082 }
1083
1084 /*
1085 * Special big-R17 for short distance
1086 */
5352ff65
ID		 1087 if (qual->rssi >= -58) {
1088 rt61pci_set_vgc(rt2x00dev, qual, up_bound);
95ea3627
ID		 1089 return;
1090 }
1091
1092 /*
1093 * Special big-R17 for middle-short distance
1094 */
5352ff65
ID		 1095 if (qual->rssi >= -66) {
1096 rt61pci_set_vgc(rt2x00dev, qual, low_bound + 0x10);
95ea3627
ID		 1097 return;
1098 }
1099
1100 /*
1101 * Special mid-R17 for middle distance
1102 */
5352ff65
ID		 1103 if (qual->rssi >= -74) {
1104 rt61pci_set_vgc(rt2x00dev, qual, low_bound + 0x08);
95ea3627
ID		 1105 return;
1106 }
1107
1108 /*
1109 * Special case: Change up_bound based on the rssi.
1110 * Lower up_bound when rssi is weaker then -74 dBm.
1111 */
5352ff65 1112 up_bound -= 2 * (-74 - qual->rssi);
95ea3627
ID		 1113 if (low_bound > up_bound)
1114 up_bound = low_bound;
1115
5352ff65
ID		 1116 if (qual->vgc_level > up_bound) {
1117 rt61pci_set_vgc(rt2x00dev, qual, up_bound);
95ea3627
ID		 1118 return;
1119 }
1120
6bb40dd1
ID		 1121dynamic_cca_tune:
1122
95ea3627
ID		 1123 /*
1124 * r17 does not yet exceed upper limit, continue and base
1125 * the r17 tuning on the false CCA count.
1126 */
5352ff65
ID		 1127 if ((qual->false_cca > 512) && (qual->vgc_level < up_bound))
1128 rt61pci_set_vgc(rt2x00dev, qual, ++qual->vgc_level);
1129 else if ((qual->false_cca < 100) && (qual->vgc_level > low_bound))
1130 rt61pci_set_vgc(rt2x00dev, qual, --qual->vgc_level);
95ea3627
ID		 1131}
1132
1133/*
a7f3a06c 1134 * Firmware functions
95ea3627
ID		 1135 */
1136static char *rt61pci_get_firmware_name(struct rt2x00_dev *rt2x00dev)
1137{
1138 char *fw_name;
1139
1140 switch (rt2x00dev->chip.rt) {
1141 case RT2561:
1142 fw_name = FIRMWARE_RT2561;
1143 break;
1144 case RT2561s:
1145 fw_name = FIRMWARE_RT2561s;
1146 break;
1147 case RT2661:
1148 fw_name = FIRMWARE_RT2661;
1149 break;
1150 default:
1151 fw_name = NULL;
1152 break;
1153 }
1154
1155 return fw_name;
1156}
1157
0cbe0064
ID		 1158static int rt61pci_check_firmware(struct rt2x00_dev *rt2x00dev,
1159 const u8 *data, const size_t len)
a7f3a06c 1160{
0cbe0064 1161 u16 fw_crc;
a7f3a06c
ID		 1162 u16 crc;
1163
1164 /*
0cbe0064
ID		 1165 * Only support 8kb firmware files.
1166 */
1167 if (len != 8192)
1168 return FW_BAD_LENGTH;
1169
1170 /*
a7f3a06c
ID		 1171 * The last 2 bytes in the firmware array are the crc checksum itself,
1172 * this means that we should never pass those 2 bytes to the crc
1173 * algorithm.
1174 */
0cbe0064
ID		 1175 fw_crc = (data[len - 2] << 8 | data[len - 1]);
1176
1177 /*
1178 * Use the crc itu-t algorithm.
1179 */
a7f3a06c
ID		 1180 crc = crc_itu_t(0, data, len - 2);
1181 crc = crc_itu_t_byte(crc, 0);
1182 crc = crc_itu_t_byte(crc, 0);
1183
0cbe0064 1184 return (fw_crc == crc) ? FW_OK : FW_BAD_CRC;
a7f3a06c
ID		 1185}
1186
0cbe0064
ID		 1187static int rt61pci_load_firmware(struct rt2x00_dev *rt2x00dev,
1188 const u8 *data, const size_t len)
95ea3627
ID		 1189{
1190 int i;
1191 u32 reg;
1192
1193 /*
1194 * Wait for stable hardware.
1195 */
1196 for (i = 0; i < 100; i++) {
1197 rt2x00pci_register_read(rt2x00dev, MAC_CSR0, &reg);
1198 if (reg)
1199 break;
1200 msleep(1);
1201 }
1202
1203 if (!reg) {
1204 ERROR(rt2x00dev, "Unstable hardware.\n");
1205 return -EBUSY;
1206 }
1207
1208 /*
1209 * Prepare MCU and mailbox for firmware loading.
1210 */
1211 reg = 0;
1212 rt2x00_set_field32(&reg, MCU_CNTL_CSR_RESET, 1);
1213 rt2x00pci_register_write(rt2x00dev, MCU_CNTL_CSR, reg);
1214 rt2x00pci_register_write(rt2x00dev, M2H_CMD_DONE_CSR, 0xffffffff);
1215 rt2x00pci_register_write(rt2x00dev, H2M_MAILBOX_CSR, 0);
1216 rt2x00pci_register_write(rt2x00dev, HOST_CMD_CSR, 0);
1217
1218 /*
1219 * Write firmware to device.
1220 */
1221 reg = 0;
1222 rt2x00_set_field32(&reg, MCU_CNTL_CSR_RESET, 1);
1223 rt2x00_set_field32(&reg, MCU_CNTL_CSR_SELECT_BANK, 1);
1224 rt2x00pci_register_write(rt2x00dev, MCU_CNTL_CSR, reg);
1225
1226 rt2x00pci_register_multiwrite(rt2x00dev, FIRMWARE_IMAGE_BASE,
1227 data, len);
1228
1229 rt2x00_set_field32(&reg, MCU_CNTL_CSR_SELECT_BANK, 0);
1230 rt2x00pci_register_write(rt2x00dev, MCU_CNTL_CSR, reg);
1231
1232 rt2x00_set_field32(&reg, MCU_CNTL_CSR_RESET, 0);
1233 rt2x00pci_register_write(rt2x00dev, MCU_CNTL_CSR, reg);
1234
1235 for (i = 0; i < 100; i++) {
1236 rt2x00pci_register_read(rt2x00dev, MCU_CNTL_CSR, &reg);
1237 if (rt2x00_get_field32(reg, MCU_CNTL_CSR_READY))
1238 break;
1239 msleep(1);
1240 }
1241
1242 if (i == 100) {
1243 ERROR(rt2x00dev, "MCU Control register not ready.\n");
1244 return -EBUSY;
1245 }
1246
e6d3e902
ID		 1247 /*
1248 * Hardware needs another millisecond before it is ready.
1249 */
1250 msleep(1);
1251
95ea3627
ID		 1252 /*
1253 * Reset MAC and BBP registers.
1254 */
1255 reg = 0;
1256 rt2x00_set_field32(&reg, MAC_CSR1_SOFT_RESET, 1);
1257 rt2x00_set_field32(&reg, MAC_CSR1_BBP_RESET, 1);
1258 rt2x00pci_register_write(rt2x00dev, MAC_CSR1, reg);
1259
1260 rt2x00pci_register_read(rt2x00dev, MAC_CSR1, &reg);
1261 rt2x00_set_field32(&reg, MAC_CSR1_SOFT_RESET, 0);
1262 rt2x00_set_field32(&reg, MAC_CSR1_BBP_RESET, 0);
1263 rt2x00pci_register_write(rt2x00dev, MAC_CSR1, reg);
1264
1265 rt2x00pci_register_read(rt2x00dev, MAC_CSR1, &reg);
1266 rt2x00_set_field32(&reg, MAC_CSR1_HOST_READY, 1);
1267 rt2x00pci_register_write(rt2x00dev, MAC_CSR1, reg);
1268
1269 return 0;
1270}
1271
a7f3a06c
ID		 1272/*
1273 * Initialization functions.
1274 */
798b7adb 1275static bool rt61pci_get_entry_state(struct queue_entry *entry)
95ea3627 1276{
b8be63ff 1277 struct queue_entry_priv_pci *entry_priv = entry->priv_data;
95ea3627
ID		 1278 u32 word;
1279
798b7adb
ID		 1280 if (entry->queue->qid == QID_RX) {
1281 rt2x00_desc_read(entry_priv->desc, 0, &word);
95ea3627 1282
798b7adb
ID		 1283 return rt2x00_get_field32(word, RXD_W0_OWNER_NIC);
1284 } else {
1285 rt2x00_desc_read(entry_priv->desc, 0, &word);
1286
1287 return (rt2x00_get_field32(word, TXD_W0_OWNER_NIC) ||
1288 rt2x00_get_field32(word, TXD_W0_VALID));
1289 }
95ea3627
ID		 1290}
1291
798b7adb 1292static void rt61pci_clear_entry(struct queue_entry *entry)
95ea3627 1293{
b8be63ff 1294 struct queue_entry_priv_pci *entry_priv = entry->priv_data;
798b7adb 1295 struct skb_frame_desc *skbdesc = get_skb_frame_desc(entry->skb);
95ea3627
ID		 1296 u32 word;
1297
798b7adb
ID		 1298 if (entry->queue->qid == QID_RX) {
1299 rt2x00_desc_read(entry_priv->desc, 5, &word);
1300 rt2x00_set_field32(&word, RXD_W5_BUFFER_PHYSICAL_ADDRESS,
1301 skbdesc->skb_dma);
1302 rt2x00_desc_write(entry_priv->desc, 5, word);
1303
1304 rt2x00_desc_read(entry_priv->desc, 0, &word);
1305 rt2x00_set_field32(&word, RXD_W0_OWNER_NIC, 1);
1306 rt2x00_desc_write(entry_priv->desc, 0, word);
1307 } else {
1308 rt2x00_desc_read(entry_priv->desc, 0, &word);
1309 rt2x00_set_field32(&word, TXD_W0_VALID, 0);
1310 rt2x00_set_field32(&word, TXD_W0_OWNER_NIC, 0);
1311 rt2x00_desc_write(entry_priv->desc, 0, word);
1312 }
95ea3627
ID		 1313}
1314
181d6902 1315static int rt61pci_init_queues(struct rt2x00_dev *rt2x00dev)
95ea3627 1316{
b8be63ff 1317 struct queue_entry_priv_pci *entry_priv;
95ea3627
ID		 1318 u32 reg;
1319
95ea3627
ID		 1320 /*
1321 * Initialize registers.
1322 */
1323 rt2x00pci_register_read(rt2x00dev, TX_RING_CSR0, &reg);
1324 rt2x00_set_field32(&reg, TX_RING_CSR0_AC0_RING_SIZE,
181d6902 1325 rt2x00dev->tx[0].limit);
95ea3627 1326 rt2x00_set_field32(&reg, TX_RING_CSR0_AC1_RING_SIZE,
181d6902 1327 rt2x00dev->tx[1].limit);
95ea3627 1328 rt2x00_set_field32(&reg, TX_RING_CSR0_AC2_RING_SIZE,
181d6902 1329 rt2x00dev->tx[2].limit);
95ea3627 1330 rt2x00_set_field32(&reg, TX_RING_CSR0_AC3_RING_SIZE,
181d6902 1331 rt2x00dev->tx[3].limit);
95ea3627
ID		 1332 rt2x00pci_register_write(rt2x00dev, TX_RING_CSR0, reg);
1333
1334 rt2x00pci_register_read(rt2x00dev, TX_RING_CSR1, &reg);
95ea3627 1335 rt2x00_set_field32(&reg, TX_RING_CSR1_TXD_SIZE,
181d6902 1336 rt2x00dev->tx[0].desc_size / 4);
95ea3627
ID		 1337 rt2x00pci_register_write(rt2x00dev, TX_RING_CSR1, reg);
1338
b8be63ff 1339 entry_priv = rt2x00dev->tx[0].entries[0].priv_data;
95ea3627 1340 rt2x00pci_register_read(rt2x00dev, AC0_BASE_CSR, &reg);
30b3a23c 1341 rt2x00_set_field32(&reg, AC0_BASE_CSR_RING_REGISTER,
b8be63ff 1342 entry_priv->desc_dma);
95ea3627
ID		 1343 rt2x00pci_register_write(rt2x00dev, AC0_BASE_CSR, reg);
1344
b8be63ff 1345 entry_priv = rt2x00dev->tx[1].entries[0].priv_data;
95ea3627 1346 rt2x00pci_register_read(rt2x00dev, AC1_BASE_CSR, &reg);
30b3a23c 1347 rt2x00_set_field32(&reg, AC1_BASE_CSR_RING_REGISTER,
b8be63ff 1348 entry_priv->desc_dma);
95ea3627
ID		 1349 rt2x00pci_register_write(rt2x00dev, AC1_BASE_CSR, reg);
1350
b8be63ff 1351 entry_priv = rt2x00dev->tx[2].entries[0].priv_data;
95ea3627 1352 rt2x00pci_register_read(rt2x00dev, AC2_BASE_CSR, &reg);
30b3a23c 1353 rt2x00_set_field32(&reg, AC2_BASE_CSR_RING_REGISTER,
b8be63ff 1354 entry_priv->desc_dma);
95ea3627
ID		 1355 rt2x00pci_register_write(rt2x00dev, AC2_BASE_CSR, reg);
1356
b8be63ff 1357 entry_priv = rt2x00dev->tx[3].entries[0].priv_data;
95ea3627 1358 rt2x00pci_register_read(rt2x00dev, AC3_BASE_CSR, &reg);
30b3a23c 1359 rt2x00_set_field32(&reg, AC3_BASE_CSR_RING_REGISTER,
b8be63ff 1360 entry_priv->desc_dma);
95ea3627
ID		 1361 rt2x00pci_register_write(rt2x00dev, AC3_BASE_CSR, reg);
1362
95ea3627 1363 rt2x00pci_register_read(rt2x00dev, RX_RING_CSR, &reg);
181d6902 1364 rt2x00_set_field32(&reg, RX_RING_CSR_RING_SIZE, rt2x00dev->rx->limit);
95ea3627
ID		 1365 rt2x00_set_field32(&reg, RX_RING_CSR_RXD_SIZE,
1366 rt2x00dev->rx->desc_size / 4);
1367 rt2x00_set_field32(&reg, RX_RING_CSR_RXD_WRITEBACK_SIZE, 4);
1368 rt2x00pci_register_write(rt2x00dev, RX_RING_CSR, reg);
1369
b8be63ff 1370 entry_priv = rt2x00dev->rx->entries[0].priv_data;
95ea3627 1371 rt2x00pci_register_read(rt2x00dev, RX_BASE_CSR, &reg);
30b3a23c 1372 rt2x00_set_field32(&reg, RX_BASE_CSR_RING_REGISTER,
b8be63ff 1373 entry_priv->desc_dma);
95ea3627
ID		 1374 rt2x00pci_register_write(rt2x00dev, RX_BASE_CSR, reg);
1375
1376 rt2x00pci_register_read(rt2x00dev, TX_DMA_DST_CSR, &reg);
1377 rt2x00_set_field32(&reg, TX_DMA_DST_CSR_DEST_AC0, 2);
1378 rt2x00_set_field32(&reg, TX_DMA_DST_CSR_DEST_AC1, 2);
1379 rt2x00_set_field32(&reg, TX_DMA_DST_CSR_DEST_AC2, 2);
1380 rt2x00_set_field32(&reg, TX_DMA_DST_CSR_DEST_AC3, 2);
95ea3627
ID		 1381 rt2x00pci_register_write(rt2x00dev, TX_DMA_DST_CSR, reg);
1382
1383 rt2x00pci_register_read(rt2x00dev, LOAD_TX_RING_CSR, &reg);
1384 rt2x00_set_field32(&reg, LOAD_TX_RING_CSR_LOAD_TXD_AC0, 1);
1385 rt2x00_set_field32(&reg, LOAD_TX_RING_CSR_LOAD_TXD_AC1, 1);
1386 rt2x00_set_field32(&reg, LOAD_TX_RING_CSR_LOAD_TXD_AC2, 1);
1387 rt2x00_set_field32(&reg, LOAD_TX_RING_CSR_LOAD_TXD_AC3, 1);
95ea3627
ID		 1388 rt2x00pci_register_write(rt2x00dev, LOAD_TX_RING_CSR, reg);
1389
1390 rt2x00pci_register_read(rt2x00dev, RX_CNTL_CSR, &reg);
1391 rt2x00_set_field32(&reg, RX_CNTL_CSR_LOAD_RXD, 1);
1392 rt2x00pci_register_write(rt2x00dev, RX_CNTL_CSR, reg);
1393
1394 return 0;
1395}
1396
1397static int rt61pci_init_registers(struct rt2x00_dev *rt2x00dev)
1398{
1399 u32 reg;
1400
1401 rt2x00pci_register_read(rt2x00dev, TXRX_CSR0, &reg);
1402 rt2x00_set_field32(&reg, TXRX_CSR0_AUTO_TX_SEQ, 1);
1403 rt2x00_set_field32(&reg, TXRX_CSR0_DISABLE_RX, 0);
1404 rt2x00_set_field32(&reg, TXRX_CSR0_TX_WITHOUT_WAITING, 0);
1405 rt2x00pci_register_write(rt2x00dev, TXRX_CSR0, reg);
1406
1407 rt2x00pci_register_read(rt2x00dev, TXRX_CSR1, &reg);
1408 rt2x00_set_field32(&reg, TXRX_CSR1_BBP_ID0, 47); /* CCK Signal */
1409 rt2x00_set_field32(&reg, TXRX_CSR1_BBP_ID0_VALID, 1);
1410 rt2x00_set_field32(&reg, TXRX_CSR1_BBP_ID1, 30); /* Rssi */
1411 rt2x00_set_field32(&reg, TXRX_CSR1_BBP_ID1_VALID, 1);
1412 rt2x00_set_field32(&reg, TXRX_CSR1_BBP_ID2, 42); /* OFDM Rate */
1413 rt2x00_set_field32(&reg, TXRX_CSR1_BBP_ID2_VALID, 1);
1414 rt2x00_set_field32(&reg, TXRX_CSR1_BBP_ID3, 30); /* Rssi */
1415 rt2x00_set_field32(&reg, TXRX_CSR1_BBP_ID3_VALID, 1);
1416 rt2x00pci_register_write(rt2x00dev, TXRX_CSR1, reg);
1417
1418 /*
1419 * CCK TXD BBP registers
1420 */
1421 rt2x00pci_register_read(rt2x00dev, TXRX_CSR2, &reg);
1422 rt2x00_set_field32(&reg, TXRX_CSR2_BBP_ID0, 13);
1423 rt2x00_set_field32(&reg, TXRX_CSR2_BBP_ID0_VALID, 1);
1424 rt2x00_set_field32(&reg, TXRX_CSR2_BBP_ID1, 12);
1425 rt2x00_set_field32(&reg, TXRX_CSR2_BBP_ID1_VALID, 1);
1426 rt2x00_set_field32(&reg, TXRX_CSR2_BBP_ID2, 11);
1427 rt2x00_set_field32(&reg, TXRX_CSR2_BBP_ID2_VALID, 1);
1428 rt2x00_set_field32(&reg, TXRX_CSR2_BBP_ID3, 10);
1429 rt2x00_set_field32(&reg, TXRX_CSR2_BBP_ID3_VALID, 1);
1430 rt2x00pci_register_write(rt2x00dev, TXRX_CSR2, reg);
1431
1432 /*
1433 * OFDM TXD BBP registers
1434 */
1435 rt2x00pci_register_read(rt2x00dev, TXRX_CSR3, &reg);
1436 rt2x00_set_field32(&reg, TXRX_CSR3_BBP_ID0, 7);
1437 rt2x00_set_field32(&reg, TXRX_CSR3_BBP_ID0_VALID, 1);
1438 rt2x00_set_field32(&reg, TXRX_CSR3_BBP_ID1, 6);
1439 rt2x00_set_field32(&reg, TXRX_CSR3_BBP_ID1_VALID, 1);
1440 rt2x00_set_field32(&reg, TXRX_CSR3_BBP_ID2, 5);
1441 rt2x00_set_field32(&reg, TXRX_CSR3_BBP_ID2_VALID, 1);
1442 rt2x00pci_register_write(rt2x00dev, TXRX_CSR3, reg);
1443
1444 rt2x00pci_register_read(rt2x00dev, TXRX_CSR7, &reg);
1445 rt2x00_set_field32(&reg, TXRX_CSR7_ACK_CTS_6MBS, 59);
1446 rt2x00_set_field32(&reg, TXRX_CSR7_ACK_CTS_9MBS, 53);
1447 rt2x00_set_field32(&reg, TXRX_CSR7_ACK_CTS_12MBS, 49);
1448 rt2x00_set_field32(&reg, TXRX_CSR7_ACK_CTS_18MBS, 46);
1449 rt2x00pci_register_write(rt2x00dev, TXRX_CSR7, reg);
1450
1451 rt2x00pci_register_read(rt2x00dev, TXRX_CSR8, &reg);
1452 rt2x00_set_field32(&reg, TXRX_CSR8_ACK_CTS_24MBS, 44);
1453 rt2x00_set_field32(&reg, TXRX_CSR8_ACK_CTS_36MBS, 42);
1454 rt2x00_set_field32(&reg, TXRX_CSR8_ACK_CTS_48MBS, 42);
1455 rt2x00_set_field32(&reg, TXRX_CSR8_ACK_CTS_54MBS, 42);
1456 rt2x00pci_register_write(rt2x00dev, TXRX_CSR8, reg);
1457
1f909162
ID		 1458 rt2x00pci_register_read(rt2x00dev, TXRX_CSR9, &reg);
1459 rt2x00_set_field32(&reg, TXRX_CSR9_BEACON_INTERVAL, 0);
1460 rt2x00_set_field32(&reg, TXRX_CSR9_TSF_TICKING, 0);
1461 rt2x00_set_field32(&reg, TXRX_CSR9_TSF_SYNC, 0);
1462 rt2x00_set_field32(&reg, TXRX_CSR9_TBTT_ENABLE, 0);
1463 rt2x00_set_field32(&reg, TXRX_CSR9_BEACON_GEN, 0);
1464 rt2x00_set_field32(&reg, TXRX_CSR9_TIMESTAMP_COMPENSATE, 0);
1465 rt2x00pci_register_write(rt2x00dev, TXRX_CSR9, reg);
1466
95ea3627
ID		 1467 rt2x00pci_register_write(rt2x00dev, TXRX_CSR15, 0x0000000f);
1468
1469 rt2x00pci_register_write(rt2x00dev, MAC_CSR6, 0x00000fff);
1470
1471 rt2x00pci_register_read(rt2x00dev, MAC_CSR9, &reg);
1472 rt2x00_set_field32(&reg, MAC_CSR9_CW_SELECT, 0);
1473 rt2x00pci_register_write(rt2x00dev, MAC_CSR9, reg);
1474
1475 rt2x00pci_register_write(rt2x00dev, MAC_CSR10, 0x0000071c);
1476
1477 if (rt2x00dev->ops->lib->set_device_state(rt2x00dev, STATE_AWAKE))
1478 return -EBUSY;
1479
1480 rt2x00pci_register_write(rt2x00dev, MAC_CSR13, 0x0000e000);
1481
1482 /*
1483 * Invalidate all Shared Keys (SEC_CSR0),
1484 * and clear the Shared key Cipher algorithms (SEC_CSR1 & SEC_CSR5)
1485 */
1486 rt2x00pci_register_write(rt2x00dev, SEC_CSR0, 0x00000000);
1487 rt2x00pci_register_write(rt2x00dev, SEC_CSR1, 0x00000000);
1488 rt2x00pci_register_write(rt2x00dev, SEC_CSR5, 0x00000000);
1489
1490 rt2x00pci_register_write(rt2x00dev, PHY_CSR1, 0x000023b0);
1491 rt2x00pci_register_write(rt2x00dev, PHY_CSR5, 0x060a100c);
1492 rt2x00pci_register_write(rt2x00dev, PHY_CSR6, 0x00080606);
1493 rt2x00pci_register_write(rt2x00dev, PHY_CSR7, 0x00000a08);
1494
1495 rt2x00pci_register_write(rt2x00dev, PCI_CFG_CSR, 0x28ca4404);
1496
1497 rt2x00pci_register_write(rt2x00dev, TEST_MODE_CSR, 0x00000200);
1498
1499 rt2x00pci_register_write(rt2x00dev, M2H_CMD_DONE_CSR, 0xffffffff);
1500
6bb40dd1
ID		 1501 /*
1502 * Clear all beacons
1503 * For the Beacon base registers we only need to clear
1504 * the first byte since that byte contains the VALID and OWNER
1505 * bits which (when set to 0) will invalidate the entire beacon.
1506 */
1507 rt2x00pci_register_write(rt2x00dev, HW_BEACON_BASE0, 0);
1508 rt2x00pci_register_write(rt2x00dev, HW_BEACON_BASE1, 0);
1509 rt2x00pci_register_write(rt2x00dev, HW_BEACON_BASE2, 0);
1510 rt2x00pci_register_write(rt2x00dev, HW_BEACON_BASE3, 0);
1511
95ea3627
ID		 1512 /*
1513 * We must clear the error counters.
1514 * These registers are cleared on read,
1515 * so we may pass a useless variable to store the value.
1516 */
1517 rt2x00pci_register_read(rt2x00dev, STA_CSR0, &reg);
1518 rt2x00pci_register_read(rt2x00dev, STA_CSR1, &reg);
1519 rt2x00pci_register_read(rt2x00dev, STA_CSR2, &reg);
1520
1521 /*
1522 * Reset MAC and BBP registers.
1523 */
1524 rt2x00pci_register_read(rt2x00dev, MAC_CSR1, &reg);
1525 rt2x00_set_field32(&reg, MAC_CSR1_SOFT_RESET, 1);
1526 rt2x00_set_field32(&reg, MAC_CSR1_BBP_RESET, 1);
1527 rt2x00pci_register_write(rt2x00dev, MAC_CSR1, reg);
1528
1529 rt2x00pci_register_read(rt2x00dev, MAC_CSR1, &reg);
1530 rt2x00_set_field32(&reg, MAC_CSR1_SOFT_RESET, 0);
1531 rt2x00_set_field32(&reg, MAC_CSR1_BBP_RESET, 0);
1532 rt2x00pci_register_write(rt2x00dev, MAC_CSR1, reg);
1533
1534 rt2x00pci_register_read(rt2x00dev, MAC_CSR1, &reg);
1535 rt2x00_set_field32(&reg, MAC_CSR1_HOST_READY, 1);
1536 rt2x00pci_register_write(rt2x00dev, MAC_CSR1, reg);
1537
1538 return 0;
1539}
1540
2b08da3f 1541static int rt61pci_wait_bbp_ready(struct rt2x00_dev *rt2x00dev)
95ea3627
ID		 1542{
1543 unsigned int i;
95ea3627
ID		 1544 u8 value;
1545
1546 for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
1547 rt61pci_bbp_read(rt2x00dev, 0, &value);
1548 if ((value != 0xff) && (value != 0x00))
2b08da3f 1549 return 0;
95ea3627
ID		 1550 udelay(REGISTER_BUSY_DELAY);
1551 }
1552
1553 ERROR(rt2x00dev, "BBP register access failed, aborting.\n");
1554 return -EACCES;
2b08da3f
ID		 1555}
1556
1557static int rt61pci_init_bbp(struct rt2x00_dev *rt2x00dev)
1558{
1559 unsigned int i;
1560 u16 eeprom;
1561 u8 reg_id;
1562 u8 value;
1563
1564 if (unlikely(rt61pci_wait_bbp_ready(rt2x00dev)))
1565 return -EACCES;
95ea3627 1566
95ea3627
ID		 1567 rt61pci_bbp_write(rt2x00dev, 3, 0x00);
1568 rt61pci_bbp_write(rt2x00dev, 15, 0x30);
1569 rt61pci_bbp_write(rt2x00dev, 21, 0xc8);
1570 rt61pci_bbp_write(rt2x00dev, 22, 0x38);
1571 rt61pci_bbp_write(rt2x00dev, 23, 0x06);
1572 rt61pci_bbp_write(rt2x00dev, 24, 0xfe);
1573 rt61pci_bbp_write(rt2x00dev, 25, 0x0a);
1574 rt61pci_bbp_write(rt2x00dev, 26, 0x0d);
1575 rt61pci_bbp_write(rt2x00dev, 34, 0x12);
1576 rt61pci_bbp_write(rt2x00dev, 37, 0x07);
1577 rt61pci_bbp_write(rt2x00dev, 39, 0xf8);
1578 rt61pci_bbp_write(rt2x00dev, 41, 0x60);
1579 rt61pci_bbp_write(rt2x00dev, 53, 0x10);
1580 rt61pci_bbp_write(rt2x00dev, 54, 0x18);
1581 rt61pci_bbp_write(rt2x00dev, 60, 0x10);
1582 rt61pci_bbp_write(rt2x00dev, 61, 0x04);
1583 rt61pci_bbp_write(rt2x00dev, 62, 0x04);
1584 rt61pci_bbp_write(rt2x00dev, 75, 0xfe);
1585 rt61pci_bbp_write(rt2x00dev, 86, 0xfe);
1586 rt61pci_bbp_write(rt2x00dev, 88, 0xfe);
1587 rt61pci_bbp_write(rt2x00dev, 90, 0x0f);
1588 rt61pci_bbp_write(rt2x00dev, 99, 0x00);
1589 rt61pci_bbp_write(rt2x00dev, 102, 0x16);
1590 rt61pci_bbp_write(rt2x00dev, 107, 0x04);
1591
95ea3627
ID		 1592 for (i = 0; i < EEPROM_BBP_SIZE; i++) {
1593 rt2x00_eeprom_read(rt2x00dev, EEPROM_BBP_START + i, &eeprom);
1594
1595 if (eeprom != 0xffff && eeprom != 0x0000) {
1596 reg_id = rt2x00_get_field16(eeprom, EEPROM_BBP_REG_ID);
1597 value = rt2x00_get_field16(eeprom, EEPROM_BBP_VALUE);
95ea3627
ID		 1598 rt61pci_bbp_write(rt2x00dev, reg_id, value);
1599 }
1600 }
95ea3627
ID		 1601
1602 return 0;
1603}
1604
1605/*
1606 * Device state switch handlers.
1607 */
1608static void rt61pci_toggle_rx(struct rt2x00_dev *rt2x00dev,
1609 enum dev_state state)
1610{
1611 u32 reg;
1612
1613 rt2x00pci_register_read(rt2x00dev, TXRX_CSR0, &reg);
1614 rt2x00_set_field32(&reg, TXRX_CSR0_DISABLE_RX,
2b08da3f
ID		 1615 (state == STATE_RADIO_RX_OFF) ||
1616 (state == STATE_RADIO_RX_OFF_LINK));
95ea3627
ID		 1617 rt2x00pci_register_write(rt2x00dev, TXRX_CSR0, reg);
1618}
1619
1620static void rt61pci_toggle_irq(struct rt2x00_dev *rt2x00dev,
1621 enum dev_state state)
1622{
1623 int mask = (state == STATE_RADIO_IRQ_OFF);
1624 u32 reg;
1625
1626 /*
1627 * When interrupts are being enabled, the interrupt registers
1628 * should clear the register to assure a clean state.
1629 */
1630 if (state == STATE_RADIO_IRQ_ON) {
1631 rt2x00pci_register_read(rt2x00dev, INT_SOURCE_CSR, &reg);
1632 rt2x00pci_register_write(rt2x00dev, INT_SOURCE_CSR, reg);
1633
1634 rt2x00pci_register_read(rt2x00dev, MCU_INT_SOURCE_CSR, &reg);
1635 rt2x00pci_register_write(rt2x00dev, MCU_INT_SOURCE_CSR, reg);
1636 }
1637
1638 /*
1639 * Only toggle the interrupts bits we are going to use.
1640 * Non-checked interrupt bits are disabled by default.
1641 */
1642 rt2x00pci_register_read(rt2x00dev, INT_MASK_CSR, &reg);
1643 rt2x00_set_field32(&reg, INT_MASK_CSR_TXDONE, mask);
1644 rt2x00_set_field32(&reg, INT_MASK_CSR_RXDONE, mask);
1645 rt2x00_set_field32(&reg, INT_MASK_CSR_ENABLE_MITIGATION, mask);
1646 rt2x00_set_field32(&reg, INT_MASK_CSR_MITIGATION_PERIOD, 0xff);
1647 rt2x00pci_register_write(rt2x00dev, INT_MASK_CSR, reg);
1648
1649 rt2x00pci_register_read(rt2x00dev, MCU_INT_MASK_CSR, &reg);
1650 rt2x00_set_field32(&reg, MCU_INT_MASK_CSR_0, mask);
1651 rt2x00_set_field32(&reg, MCU_INT_MASK_CSR_1, mask);
1652 rt2x00_set_field32(&reg, MCU_INT_MASK_CSR_2, mask);
1653 rt2x00_set_field32(&reg, MCU_INT_MASK_CSR_3, mask);
1654 rt2x00_set_field32(&reg, MCU_INT_MASK_CSR_4, mask);
1655 rt2x00_set_field32(&reg, MCU_INT_MASK_CSR_5, mask);
1656 rt2x00_set_field32(&reg, MCU_INT_MASK_CSR_6, mask);
1657 rt2x00_set_field32(&reg, MCU_INT_MASK_CSR_7, mask);
1658 rt2x00pci_register_write(rt2x00dev, MCU_INT_MASK_CSR, reg);
1659}
1660
1661static int rt61pci_enable_radio(struct rt2x00_dev *rt2x00dev)
1662{
1663 u32 reg;
1664
1665 /*
1666 * Initialize all registers.
1667 */
2b08da3f
ID		 1668 if (unlikely(rt61pci_init_queues(rt2x00dev) ||
1669 rt61pci_init_registers(rt2x00dev) ||
1670 rt61pci_init_bbp(rt2x00dev)))
95ea3627 1671 return -EIO;
95ea3627
ID		 1672
1673 /*
1674 * Enable RX.
1675 */
1676 rt2x00pci_register_read(rt2x00dev, RX_CNTL_CSR, &reg);
1677 rt2x00_set_field32(&reg, RX_CNTL_CSR_ENABLE_RX_DMA, 1);
1678 rt2x00pci_register_write(rt2x00dev, RX_CNTL_CSR, reg);
1679
95ea3627
ID		 1680 return 0;
1681}
1682
1683static void rt61pci_disable_radio(struct rt2x00_dev *rt2x00dev)
1684{
95ea3627 1685 /*
a2c9b652 1686 * Disable power
95ea3627 1687 */
a2c9b652 1688 rt2x00pci_register_write(rt2x00dev, MAC_CSR10, 0x00001818);
95ea3627
ID		 1689}
1690
1691static int rt61pci_set_state(struct rt2x00_dev *rt2x00dev, enum dev_state state)
1692{
1693 u32 reg;
1694 unsigned int i;
1695 char put_to_sleep;
95ea3627
ID		 1696
1697 put_to_sleep = (state != STATE_AWAKE);
1698
1699 rt2x00pci_register_read(rt2x00dev, MAC_CSR12, &reg);
1700 rt2x00_set_field32(&reg, MAC_CSR12_FORCE_WAKEUP, !put_to_sleep);
1701 rt2x00_set_field32(&reg, MAC_CSR12_PUT_TO_SLEEP, put_to_sleep);
1702 rt2x00pci_register_write(rt2x00dev, MAC_CSR12, reg);
1703
1704 /*
1705 * Device is not guaranteed to be in the requested state yet.
1706 * We must wait until the register indicates that the
1707 * device has entered the correct state.
1708 */
1709 for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
1710 rt2x00pci_register_read(rt2x00dev, MAC_CSR12, &reg);
2b08da3f
ID		 1711 state = rt2x00_get_field32(reg, MAC_CSR12_BBP_CURRENT_STATE);
1712 if (state == !put_to_sleep)
95ea3627
ID		 1713 return 0;
1714 msleep(10);
1715 }
1716
95ea3627
ID		 1717 return -EBUSY;
1718}
1719
1720static int rt61pci_set_device_state(struct rt2x00_dev *rt2x00dev,
1721 enum dev_state state)
1722{
1723 int retval = 0;
1724
1725 switch (state) {
1726 case STATE_RADIO_ON:
1727 retval = rt61pci_enable_radio(rt2x00dev);
1728 break;
1729 case STATE_RADIO_OFF:
1730 rt61pci_disable_radio(rt2x00dev);
1731 break;
1732 case STATE_RADIO_RX_ON:
61667d8d 1733 case STATE_RADIO_RX_ON_LINK:
95ea3627 1734 case STATE_RADIO_RX_OFF:
61667d8d 1735 case STATE_RADIO_RX_OFF_LINK:
2b08da3f
ID		 1736 rt61pci_toggle_rx(rt2x00dev, state);
1737 break;
1738 case STATE_RADIO_IRQ_ON:
1739 case STATE_RADIO_IRQ_OFF:
1740 rt61pci_toggle_irq(rt2x00dev, state);
95ea3627
ID		 1741 break;
1742 case STATE_DEEP_SLEEP:
1743 case STATE_SLEEP:
1744 case STATE_STANDBY:
1745 case STATE_AWAKE:
1746 retval = rt61pci_set_state(rt2x00dev, state);
1747 break;
1748 default:
1749 retval = -ENOTSUPP;
1750 break;
1751 }
1752
2b08da3f
ID		 1753 if (unlikely(retval))
1754 ERROR(rt2x00dev, "Device failed to enter state %d (%d).\n",
1755 state, retval);
1756
95ea3627
ID		 1757 return retval;
1758}
1759
1760/*
1761 * TX descriptor initialization
1762 */
1763static void rt61pci_write_tx_desc(struct rt2x00_dev *rt2x00dev,
61e754f4
ID		 1764 struct sk_buff *skb,
1765 struct txentry_desc *txdesc)
95ea3627 1766{
181d6902 1767 struct skb_frame_desc *skbdesc = get_skb_frame_desc(skb);
dd3193e1 1768 __le32 *txd = skbdesc->desc;
95ea3627
ID		 1769 u32 word;
1770
1771 /*
1772 * Start writing the descriptor words.
1773 */
1774 rt2x00_desc_read(txd, 1, &word);
181d6902
ID		 1775 rt2x00_set_field32(&word, TXD_W1_HOST_Q_ID, txdesc->queue);
1776 rt2x00_set_field32(&word, TXD_W1_AIFSN, txdesc->aifs);
1777 rt2x00_set_field32(&word, TXD_W1_CWMIN, txdesc->cw_min);
1778 rt2x00_set_field32(&word, TXD_W1_CWMAX, txdesc->cw_max);
61e754f4 1779 rt2x00_set_field32(&word, TXD_W1_IV_OFFSET, txdesc->iv_offset);
5adf6d63
ID		 1780 rt2x00_set_field32(&word, TXD_W1_HW_SEQUENCE,
1781 test_bit(ENTRY_TXD_GENERATE_SEQ, &txdesc->flags));
4de36fe5 1782 rt2x00_set_field32(&word, TXD_W1_BUFFER_COUNT, 1);
95ea3627
ID		 1783 rt2x00_desc_write(txd, 1, word);
1784
1785 rt2x00_desc_read(txd, 2, &word);
181d6902
ID		 1786 rt2x00_set_field32(&word, TXD_W2_PLCP_SIGNAL, txdesc->signal);
1787 rt2x00_set_field32(&word, TXD_W2_PLCP_SERVICE, txdesc->service);
1788 rt2x00_set_field32(&word, TXD_W2_PLCP_LENGTH_LOW, txdesc->length_low);
1789 rt2x00_set_field32(&word, TXD_W2_PLCP_LENGTH_HIGH, txdesc->length_high);
95ea3627
ID		 1790 rt2x00_desc_write(txd, 2, word);
1791
61e754f4 1792 if (test_bit(ENTRY_TXD_ENCRYPT, &txdesc->flags)) {
1ce9cdac
ID		 1793 _rt2x00_desc_write(txd, 3, skbdesc->iv[0]);
1794 _rt2x00_desc_write(txd, 4, skbdesc->iv[1]);
61e754f4
ID		 1795 }
1796
95ea3627 1797 rt2x00_desc_read(txd, 5, &word);
4de36fe5
GW		 1798 rt2x00_set_field32(&word, TXD_W5_PID_TYPE, skbdesc->entry->queue->qid);
1799 rt2x00_set_field32(&word, TXD_W5_PID_SUBTYPE,
1800 skbdesc->entry->entry_idx);
95ea3627 1801 rt2x00_set_field32(&word, TXD_W5_TX_POWER,
ac1aa7e4 1802 TXPOWER_TO_DEV(rt2x00dev->tx_power));
95ea3627
ID		 1803 rt2x00_set_field32(&word, TXD_W5_WAITING_DMA_DONE_INT, 1);
1804 rt2x00_desc_write(txd, 5, word);
1805
4de36fe5
GW		 1806 rt2x00_desc_read(txd, 6, &word);
1807 rt2x00_set_field32(&word, TXD_W6_BUFFER_PHYSICAL_ADDRESS,
c4da0048 1808 skbdesc->skb_dma);
4de36fe5
GW		 1809 rt2x00_desc_write(txd, 6, word);
1810
d7bafff3
AB		 1811 if (skbdesc->desc_len > TXINFO_SIZE) {
1812 rt2x00_desc_read(txd, 11, &word);
d56d453a 1813 rt2x00_set_field32(&word, TXD_W11_BUFFER_LENGTH0, skb->len);
d7bafff3
AB		 1814 rt2x00_desc_write(txd, 11, word);
1815 }
95ea3627
ID		 1816
1817 rt2x00_desc_read(txd, 0, &word);
1818 rt2x00_set_field32(&word, TXD_W0_OWNER_NIC, 1);
1819 rt2x00_set_field32(&word, TXD_W0_VALID, 1);
1820 rt2x00_set_field32(&word, TXD_W0_MORE_FRAG,
181d6902 1821 test_bit(ENTRY_TXD_MORE_FRAG, &txdesc->flags));
95ea3627 1822 rt2x00_set_field32(&word, TXD_W0_ACK,
181d6902 1823 test_bit(ENTRY_TXD_ACK, &txdesc->flags));
95ea3627 1824 rt2x00_set_field32(&word, TXD_W0_TIMESTAMP,
181d6902 1825 test_bit(ENTRY_TXD_REQ_TIMESTAMP, &txdesc->flags));
95ea3627 1826 rt2x00_set_field32(&word, TXD_W0_OFDM,
076f9582 1827 (txdesc->rate_mode == RATE_MODE_OFDM));
181d6902 1828 rt2x00_set_field32(&word, TXD_W0_IFS, txdesc->ifs);
95ea3627 1829 rt2x00_set_field32(&word, TXD_W0_RETRY_MODE,
61486e0f 1830 test_bit(ENTRY_TXD_RETRY_MODE, &txdesc->flags));
61e754f4
ID		 1831 rt2x00_set_field32(&word, TXD_W0_TKIP_MIC,
1832 test_bit(ENTRY_TXD_ENCRYPT_MMIC, &txdesc->flags));
1833 rt2x00_set_field32(&word, TXD_W0_KEY_TABLE,
1834 test_bit(ENTRY_TXD_ENCRYPT_PAIRWISE, &txdesc->flags));
1835 rt2x00_set_field32(&word, TXD_W0_KEY_INDEX, txdesc->key_idx);
d56d453a 1836 rt2x00_set_field32(&word, TXD_W0_DATABYTE_COUNT, skb->len);
95ea3627 1837 rt2x00_set_field32(&word, TXD_W0_BURST,
181d6902 1838 test_bit(ENTRY_TXD_BURST, &txdesc->flags));
61e754f4 1839 rt2x00_set_field32(&word, TXD_W0_CIPHER_ALG, txdesc->cipher);
95ea3627
ID		 1840 rt2x00_desc_write(txd, 0, word);
1841}
1842
1843/*
1844 * TX data initialization
1845 */
bd88a781
ID		 1846static void rt61pci_write_beacon(struct queue_entry *entry)
1847{
1848 struct rt2x00_dev *rt2x00dev = entry->queue->rt2x00dev;
1849 struct skb_frame_desc *skbdesc = get_skb_frame_desc(entry->skb);
1850 unsigned int beacon_base;
1851 u32 reg;
1852
1853 /*
1854 * Disable beaconing while we are reloading the beacon data,
1855 * otherwise we might be sending out invalid data.
1856 */
1857 rt2x00pci_register_read(rt2x00dev, TXRX_CSR9, &reg);
bd88a781
ID		 1858 rt2x00_set_field32(&reg, TXRX_CSR9_BEACON_GEN, 0);
1859 rt2x00pci_register_write(rt2x00dev, TXRX_CSR9, reg);
1860
1861 /*
1862 * Write entire beacon with descriptor to register.
1863 */
1864 beacon_base = HW_BEACON_OFFSET(entry->entry_idx);
1865 rt2x00pci_register_multiwrite(rt2x00dev,
1866 beacon_base,
1867 skbdesc->desc, skbdesc->desc_len);
1868 rt2x00pci_register_multiwrite(rt2x00dev,
1869 beacon_base + skbdesc->desc_len,
1870 entry->skb->data, entry->skb->len);
1871
1872 /*
1873 * Clean up beacon skb.
1874 */
1875 dev_kfree_skb_any(entry->skb);
1876 entry->skb = NULL;
1877}
1878
95ea3627 1879static void rt61pci_kick_tx_queue(struct rt2x00_dev *rt2x00dev,
e58c6aca 1880 const enum data_queue_qid queue)
95ea3627
ID		 1881{
1882 u32 reg;
1883
e58c6aca 1884 if (queue == QID_BEACON) {
95ea3627
ID		 1885 /*
1886 * For Wi-Fi faily generated beacons between participating
1887 * stations. Set TBTT phase adaptive adjustment step to 8us.
1888 */
1889 rt2x00pci_register_write(rt2x00dev, TXRX_CSR10, 0x00001008);
1890
1891 rt2x00pci_register_read(rt2x00dev, TXRX_CSR9, &reg);
1892 if (!rt2x00_get_field32(reg, TXRX_CSR9_BEACON_GEN)) {
8af244cc
ID		 1893 rt2x00_set_field32(&reg, TXRX_CSR9_TSF_TICKING, 1);
1894 rt2x00_set_field32(&reg, TXRX_CSR9_TBTT_ENABLE, 1);
95ea3627
ID		 1895 rt2x00_set_field32(&reg, TXRX_CSR9_BEACON_GEN, 1);
1896 rt2x00pci_register_write(rt2x00dev, TXRX_CSR9, reg);
1897 }
1898 return;
1899 }
1900
1901 rt2x00pci_register_read(rt2x00dev, TX_CNTL_CSR, &reg);
e58c6aca
ID		 1902 rt2x00_set_field32(&reg, TX_CNTL_CSR_KICK_TX_AC0, (queue == QID_AC_BE));
1903 rt2x00_set_field32(&reg, TX_CNTL_CSR_KICK_TX_AC1, (queue == QID_AC_BK));
1904 rt2x00_set_field32(&reg, TX_CNTL_CSR_KICK_TX_AC2, (queue == QID_AC_VI));
1905 rt2x00_set_field32(&reg, TX_CNTL_CSR_KICK_TX_AC3, (queue == QID_AC_VO));
95ea3627
ID		 1906 rt2x00pci_register_write(rt2x00dev, TX_CNTL_CSR, reg);
1907}
1908
a2c9b652
ID		 1909static void rt61pci_kill_tx_queue(struct rt2x00_dev *rt2x00dev,
1910 const enum data_queue_qid qid)
1911{
1912 u32 reg;
1913
1914 if (qid == QID_BEACON) {
1915 rt2x00pci_register_write(rt2x00dev, TXRX_CSR9, 0);
1916 return;
1917 }
1918
1919 rt2x00pci_register_read(rt2x00dev, TX_CNTL_CSR, &reg);
1920 rt2x00_set_field32(&reg, TX_CNTL_CSR_ABORT_TX_AC0, (qid == QID_AC_BE));
1921 rt2x00_set_field32(&reg, TX_CNTL_CSR_ABORT_TX_AC1, (qid == QID_AC_BK));
1922 rt2x00_set_field32(&reg, TX_CNTL_CSR_ABORT_TX_AC2, (qid == QID_AC_VI));
1923 rt2x00_set_field32(&reg, TX_CNTL_CSR_ABORT_TX_AC3, (qid == QID_AC_VO));
1924 rt2x00pci_register_write(rt2x00dev, TX_CNTL_CSR, reg);
1925}
1926
95ea3627
ID		 1927/*
1928 * RX control handlers
1929 */
1930static int rt61pci_agc_to_rssi(struct rt2x00_dev *rt2x00dev, int rxd_w1)
1931{
ba2ab471 1932 u8 offset = rt2x00dev->lna_gain;
95ea3627
ID		 1933 u8 lna;
1934
1935 lna = rt2x00_get_field32(rxd_w1, RXD_W1_RSSI_LNA);
1936 switch (lna) {
1937 case 3:
ba2ab471 1938 offset += 90;
95ea3627
ID		 1939 break;
1940 case 2:
ba2ab471 1941 offset += 74;
95ea3627
ID		 1942 break;
1943 case 1:
ba2ab471 1944 offset += 64;
95ea3627
ID		 1945 break;
1946 default:
1947 return 0;
1948 }
1949
8318d78a 1950 if (rt2x00dev->rx_status.band == IEEE80211_BAND_5GHZ) {
95ea3627
ID		 1951 if (lna == 3 || lna == 2)
1952 offset += 10;
95ea3627
ID		 1953 }
1954
1955 return rt2x00_get_field32(rxd_w1, RXD_W1_RSSI_AGC) * 2 - offset;
1956}
1957
181d6902 1958static void rt61pci_fill_rxdone(struct queue_entry *entry,
55887511 1959 struct rxdone_entry_desc *rxdesc)
95ea3627 1960{
61e754f4 1961 struct rt2x00_dev *rt2x00dev = entry->queue->rt2x00dev;
b8be63ff 1962 struct queue_entry_priv_pci *entry_priv = entry->priv_data;
95ea3627
ID		 1963 u32 word0;
1964 u32 word1;
1965
b8be63ff
ID		 1966 rt2x00_desc_read(entry_priv->desc, 0, &word0);
1967 rt2x00_desc_read(entry_priv->desc, 1, &word1);
95ea3627 1968
4150c572 1969 if (rt2x00_get_field32(word0, RXD_W0_CRC_ERROR))
181d6902 1970 rxdesc->flags |= RX_FLAG_FAILED_FCS_CRC;
95ea3627 1971
61e754f4
ID		 1972 if (test_bit(CONFIG_SUPPORT_HW_CRYPTO, &rt2x00dev->flags)) {
1973 rxdesc->cipher =
1974 rt2x00_get_field32(word0, RXD_W0_CIPHER_ALG);
1975 rxdesc->cipher_status =
1976 rt2x00_get_field32(word0, RXD_W0_CIPHER_ERROR);
1977 }
1978
1979 if (rxdesc->cipher != CIPHER_NONE) {
1ce9cdac
ID		 1980 _rt2x00_desc_read(entry_priv->desc, 2, &rxdesc->iv[0]);
1981 _rt2x00_desc_read(entry_priv->desc, 3, &rxdesc->iv[1]);
74415edb
ID		 1982 rxdesc->dev_flags |= RXDONE_CRYPTO_IV;
1983
61e754f4 1984 _rt2x00_desc_read(entry_priv->desc, 4, &rxdesc->icv);
74415edb 1985 rxdesc->dev_flags |= RXDONE_CRYPTO_ICV;
61e754f4
ID		 1986
1987 /*
1988 * Hardware has stripped IV/EIV data from 802.11 frame during
1989 * decryption. It has provided the data seperately but rt2x00lib
1990 * should decide if it should be reinserted.
1991 */
1992 rxdesc->flags |= RX_FLAG_IV_STRIPPED;
1993
1994 /*
1995 * FIXME: Legacy driver indicates that the frame does
1996 * contain the Michael Mic. Unfortunately, in rt2x00
1997 * the MIC seems to be missing completely...
1998 */
1999 rxdesc->flags |= RX_FLAG_MMIC_STRIPPED;
2000
2001 if (rxdesc->cipher_status == RX_CRYPTO_SUCCESS)
2002 rxdesc->flags |= RX_FLAG_DECRYPTED;
2003 else if (rxdesc->cipher_status == RX_CRYPTO_FAIL_MIC)
2004 rxdesc->flags |= RX_FLAG_MMIC_ERROR;
2005 }
2006
95ea3627
ID		 2007 /*
2008 * Obtain the status about this packet.
89993890
ID		 2009 * When frame was received with an OFDM bitrate,
2010 * the signal is the PLCP value. If it was received with
2011 * a CCK bitrate the signal is the rate in 100kbit/s.
95ea3627 2012 */
181d6902 2013 rxdesc->signal = rt2x00_get_field32(word1, RXD_W1_SIGNAL);
61e754f4 2014 rxdesc->rssi = rt61pci_agc_to_rssi(rt2x00dev, word1);
181d6902 2015 rxdesc->size = rt2x00_get_field32(word0, RXD_W0_DATABYTE_COUNT);
19d30e02 2016
19d30e02
ID		 2017 if (rt2x00_get_field32(word0, RXD_W0_OFDM))
2018 rxdesc->dev_flags |= RXDONE_SIGNAL_PLCP;
6c6aa3c0
ID		 2019 else
2020 rxdesc->dev_flags |= RXDONE_SIGNAL_BITRATE;
19d30e02
ID		 2021 if (rt2x00_get_field32(word0, RXD_W0_MY_BSS))
2022 rxdesc->dev_flags |= RXDONE_MY_BSS;
95ea3627
ID		 2023}
2024
2025/*
2026 * Interrupt functions.
2027 */
2028static void rt61pci_txdone(struct rt2x00_dev *rt2x00dev)
2029{
181d6902
ID		 2030 struct data_queue *queue;
2031 struct queue_entry *entry;
2032 struct queue_entry *entry_done;
b8be63ff 2033 struct queue_entry_priv_pci *entry_priv;
181d6902 2034 struct txdone_entry_desc txdesc;
95ea3627
ID		 2035 u32 word;
2036 u32 reg;
2037 u32 old_reg;
2038 int type;
2039 int index;
95ea3627
ID		 2040
2041 /*
2042 * During each loop we will compare the freshly read
2043 * STA_CSR4 register value with the value read from
2044 * the previous loop. If the 2 values are equal then
2045 * we should stop processing because the chance it
2046 * quite big that the device has been unplugged and
2047 * we risk going into an endless loop.
2048 */
2049 old_reg = 0;
2050
2051 while (1) {
2052 rt2x00pci_register_read(rt2x00dev, STA_CSR4, &reg);
2053 if (!rt2x00_get_field32(reg, STA_CSR4_VALID))
2054 break;
2055
2056 if (old_reg == reg)
2057 break;
2058 old_reg = reg;
2059
2060 /*
2061 * Skip this entry when it contains an invalid
181d6902 2062 * queue identication number.
95ea3627
ID		 2063 */
2064 type = rt2x00_get_field32(reg, STA_CSR4_PID_TYPE);
181d6902
ID		 2065 queue = rt2x00queue_get_queue(rt2x00dev, type);
2066 if (unlikely(!queue))
95ea3627
ID		 2067 continue;
2068
2069 /*
2070 * Skip this entry when it contains an invalid
2071 * index number.
2072 */
2073 index = rt2x00_get_field32(reg, STA_CSR4_PID_SUBTYPE);
181d6902 2074 if (unlikely(index >= queue->limit))
95ea3627
ID		 2075 continue;
2076
181d6902 2077 entry = &queue->entries[index];
b8be63ff
ID		 2078 entry_priv = entry->priv_data;
2079 rt2x00_desc_read(entry_priv->desc, 0, &word);
95ea3627
ID		 2080
2081 if (rt2x00_get_field32(word, TXD_W0_OWNER_NIC) ||
2082 !rt2x00_get_field32(word, TXD_W0_VALID))
2083 return;
2084
181d6902 2085 entry_done = rt2x00queue_get_entry(queue, Q_INDEX_DONE);
62bc060b 2086 while (entry != entry_done) {
181d6902
ID		 2087 /* Catch up.
2088 * Just report any entries we missed as failed.
2089 */
62bc060b 2090 WARNING(rt2x00dev,
181d6902
ID		 2091 "TX status report missed for entry %d\n",
2092 entry_done->entry_idx);
2093
fb55f4d1
ID		 2094 txdesc.flags = 0;
2095 __set_bit(TXDONE_UNKNOWN, &txdesc.flags);
181d6902
ID		 2096 txdesc.retry = 0;
2097
d74f5ba4 2098 rt2x00lib_txdone(entry_done, &txdesc);
181d6902 2099 entry_done = rt2x00queue_get_entry(queue, Q_INDEX_DONE);
62bc060b
MN		 2100 }
2101
95ea3627
ID		 2102 /*
2103 * Obtain the status about this packet.
2104 */
fb55f4d1
ID		 2105 txdesc.flags = 0;
2106 switch (rt2x00_get_field32(reg, STA_CSR4_TX_RESULT)) {
2107 case 0: /* Success, maybe with retry */
2108 __set_bit(TXDONE_SUCCESS, &txdesc.flags);
2109 break;
2110 case 6: /* Failure, excessive retries */
2111 __set_bit(TXDONE_EXCESSIVE_RETRY, &txdesc.flags);
2112 /* Don't break, this is a failed frame! */
2113 default: /* Failure */
2114 __set_bit(TXDONE_FAILURE, &txdesc.flags);
2115 }
181d6902 2116 txdesc.retry = rt2x00_get_field32(reg, STA_CSR4_RETRY_COUNT);
95ea3627 2117
d74f5ba4 2118 rt2x00lib_txdone(entry, &txdesc);
95ea3627
ID		 2119 }
2120}
2121
2122static irqreturn_t rt61pci_interrupt(int irq, void *dev_instance)
2123{
2124 struct rt2x00_dev *rt2x00dev = dev_instance;
2125 u32 reg_mcu;
2126 u32 reg;
2127
2128 /*
2129 * Get the interrupt sources & saved to local variable.
2130 * Write register value back to clear pending interrupts.
2131 */
2132 rt2x00pci_register_read(rt2x00dev, MCU_INT_SOURCE_CSR, &reg_mcu);
2133 rt2x00pci_register_write(rt2x00dev, MCU_INT_SOURCE_CSR, reg_mcu);
2134
2135 rt2x00pci_register_read(rt2x00dev, INT_SOURCE_CSR, &reg);
2136 rt2x00pci_register_write(rt2x00dev, INT_SOURCE_CSR, reg);
2137
2138 if (!reg && !reg_mcu)
2139 return IRQ_NONE;
2140
0262ab0d 2141 if (!test_bit(DEVICE_STATE_ENABLED_RADIO, &rt2x00dev->flags))
95ea3627
ID		 2142 return IRQ_HANDLED;
2143
2144 /*
2145 * Handle interrupts, walk through all bits
2146 * and run the tasks, the bits are checked in order of
2147 * priority.
2148 */
2149
2150 /*
2151 * 1 - Rx ring done interrupt.
2152 */
2153 if (rt2x00_get_field32(reg, INT_SOURCE_CSR_RXDONE))
2154 rt2x00pci_rxdone(rt2x00dev);
2155
2156 /*
2157 * 2 - Tx ring done interrupt.
2158 */
2159 if (rt2x00_get_field32(reg, INT_SOURCE_CSR_TXDONE))
2160 rt61pci_txdone(rt2x00dev);
2161
2162 /*
2163 * 3 - Handle MCU command done.
2164 */
2165 if (reg_mcu)
2166 rt2x00pci_register_write(rt2x00dev,
2167 M2H_CMD_DONE_CSR, 0xffffffff);
2168
2169 return IRQ_HANDLED;
2170}
2171
2172/*
2173 * Device probe functions.
2174 */
2175static int rt61pci_validate_eeprom(struct rt2x00_dev *rt2x00dev)
2176{
2177 struct eeprom_93cx6 eeprom;
2178 u32 reg;
2179 u16 word;
2180 u8 *mac;
2181 s8 value;
2182
2183 rt2x00pci_register_read(rt2x00dev, E2PROM_CSR, &reg);
2184
2185 eeprom.data = rt2x00dev;
2186 eeprom.register_read = rt61pci_eepromregister_read;
2187 eeprom.register_write = rt61pci_eepromregister_write;
2188 eeprom.width = rt2x00_get_field32(reg, E2PROM_CSR_TYPE_93C46) ?
2189 PCI_EEPROM_WIDTH_93C46 : PCI_EEPROM_WIDTH_93C66;
2190 eeprom.reg_data_in = 0;
2191 eeprom.reg_data_out = 0;
2192 eeprom.reg_data_clock = 0;
2193 eeprom.reg_chip_select = 0;
2194
2195 eeprom_93cx6_multiread(&eeprom, EEPROM_BASE, rt2x00dev->eeprom,
2196 EEPROM_SIZE / sizeof(u16));
2197
2198 /*
2199 * Start validation of the data that has been read.
2200 */
2201 mac = rt2x00_eeprom_addr(rt2x00dev, EEPROM_MAC_ADDR_0);
2202 if (!is_valid_ether_addr(mac)) {
2203 random_ether_addr(mac);
e174961c 2204 EEPROM(rt2x00dev, "MAC: %pM\n", mac);
95ea3627
ID		 2205 }
2206
2207 rt2x00_eeprom_read(rt2x00dev, EEPROM_ANTENNA, &word);
2208 if (word == 0xffff) {
2209 rt2x00_set_field16(&word, EEPROM_ANTENNA_NUM, 2);
362f3b6b
ID		 2210 rt2x00_set_field16(&word, EEPROM_ANTENNA_TX_DEFAULT,
2211 ANTENNA_B);
2212 rt2x00_set_field16(&word, EEPROM_ANTENNA_RX_DEFAULT,
2213 ANTENNA_B);
95ea3627
ID		 2214 rt2x00_set_field16(&word, EEPROM_ANTENNA_FRAME_TYPE, 0);
2215 rt2x00_set_field16(&word, EEPROM_ANTENNA_DYN_TXAGC, 0);
2216 rt2x00_set_field16(&word, EEPROM_ANTENNA_HARDWARE_RADIO, 0);
2217 rt2x00_set_field16(&word, EEPROM_ANTENNA_RF_TYPE, RF5225);
2218 rt2x00_eeprom_write(rt2x00dev, EEPROM_ANTENNA, word);
2219 EEPROM(rt2x00dev, "Antenna: 0x%04x\n", word);
2220 }
2221
2222 rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC, &word);
2223 if (word == 0xffff) {
2224 rt2x00_set_field16(&word, EEPROM_NIC_ENABLE_DIVERSITY, 0);
2225 rt2x00_set_field16(&word, EEPROM_NIC_TX_DIVERSITY, 0);
91581b62
ID		 2226 rt2x00_set_field16(&word, EEPROM_NIC_RX_FIXED, 0);
2227 rt2x00_set_field16(&word, EEPROM_NIC_TX_FIXED, 0);
95ea3627
ID		 2228 rt2x00_set_field16(&word, EEPROM_NIC_EXTERNAL_LNA_BG, 0);
2229 rt2x00_set_field16(&word, EEPROM_NIC_CARDBUS_ACCEL, 0);
2230 rt2x00_set_field16(&word, EEPROM_NIC_EXTERNAL_LNA_A, 0);
2231 rt2x00_eeprom_write(rt2x00dev, EEPROM_NIC, word);
2232 EEPROM(rt2x00dev, "NIC: 0x%04x\n", word);
2233 }
2234
2235 rt2x00_eeprom_read(rt2x00dev, EEPROM_LED, &word);
2236 if (word == 0xffff) {
2237 rt2x00_set_field16(&word, EEPROM_LED_LED_MODE,
2238 LED_MODE_DEFAULT);
2239 rt2x00_eeprom_write(rt2x00dev, EEPROM_LED, word);
2240 EEPROM(rt2x00dev, "Led: 0x%04x\n", word);
2241 }
2242
2243 rt2x00_eeprom_read(rt2x00dev, EEPROM_FREQ, &word);
2244 if (word == 0xffff) {
2245 rt2x00_set_field16(&word, EEPROM_FREQ_OFFSET, 0);
2246 rt2x00_set_field16(&word, EEPROM_FREQ_SEQ, 0);
2247 rt2x00_eeprom_write(rt2x00dev, EEPROM_FREQ, word);
2248 EEPROM(rt2x00dev, "Freq: 0x%04x\n", word);
2249 }
2250
2251 rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_OFFSET_BG, &word);
2252 if (word == 0xffff) {
2253 rt2x00_set_field16(&word, EEPROM_RSSI_OFFSET_BG_1, 0);
2254 rt2x00_set_field16(&word, EEPROM_RSSI_OFFSET_BG_2, 0);
2255 rt2x00_eeprom_write(rt2x00dev, EEPROM_RSSI_OFFSET_BG, word);
2256 EEPROM(rt2x00dev, "RSSI OFFSET BG: 0x%04x\n", word);
2257 } else {
2258 value = rt2x00_get_field16(word, EEPROM_RSSI_OFFSET_BG_1);
2259 if (value < -10 || value > 10)
2260 rt2x00_set_field16(&word, EEPROM_RSSI_OFFSET_BG_1, 0);
2261 value = rt2x00_get_field16(word, EEPROM_RSSI_OFFSET_BG_2);
2262 if (value < -10 || value > 10)
2263 rt2x00_set_field16(&word, EEPROM_RSSI_OFFSET_BG_2, 0);
2264 rt2x00_eeprom_write(rt2x00dev, EEPROM_RSSI_OFFSET_BG, word);
2265 }
2266
2267 rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_OFFSET_A, &word);
2268 if (word == 0xffff) {
2269 rt2x00_set_field16(&word, EEPROM_RSSI_OFFSET_A_1, 0);
2270 rt2x00_set_field16(&word, EEPROM_RSSI_OFFSET_A_2, 0);
2271 rt2x00_eeprom_write(rt2x00dev, EEPROM_RSSI_OFFSET_A, word);
417f412f 2272 EEPROM(rt2x00dev, "RSSI OFFSET A: 0x%04x\n", word);
95ea3627
ID		 2273 } else {
2274 value = rt2x00_get_field16(word, EEPROM_RSSI_OFFSET_A_1);
2275 if (value < -10 || value > 10)
2276 rt2x00_set_field16(&word, EEPROM_RSSI_OFFSET_A_1, 0);
2277 value = rt2x00_get_field16(word, EEPROM_RSSI_OFFSET_A_2);
2278 if (value < -10 || value > 10)
2279 rt2x00_set_field16(&word, EEPROM_RSSI_OFFSET_A_2, 0);
2280 rt2x00_eeprom_write(rt2x00dev, EEPROM_RSSI_OFFSET_A, word);
2281 }
2282
2283 return 0;
2284}
2285
2286static int rt61pci_init_eeprom(struct rt2x00_dev *rt2x00dev)
2287{
2288 u32 reg;
2289 u16 value;
2290 u16 eeprom;
95ea3627
ID		 2291
2292 /*
2293 * Read EEPROM word for configuration.
2294 */
2295 rt2x00_eeprom_read(rt2x00dev, EEPROM_ANTENNA, &eeprom);
2296
2297 /*
2298 * Identify RF chipset.
95ea3627 2299 */
95ea3627
ID		 2300 value = rt2x00_get_field16(eeprom, EEPROM_ANTENNA_RF_TYPE);
2301 rt2x00pci_register_read(rt2x00dev, MAC_CSR0, &reg);
440ddada 2302 rt2x00_set_chip_rf(rt2x00dev, value, reg);
95ea3627
ID		 2303
2304 if (!rt2x00_rf(&rt2x00dev->chip, RF5225) &&
2305 !rt2x00_rf(&rt2x00dev->chip, RF5325) &&
2306 !rt2x00_rf(&rt2x00dev->chip, RF2527) &&
2307 !rt2x00_rf(&rt2x00dev->chip, RF2529)) {
2308 ERROR(rt2x00dev, "Invalid RF chipset detected.\n");
2309 return -ENODEV;
2310 }
2311
e4cd2ff8 2312 /*
49513481 2313 * Determine number of antennas.
e4cd2ff8
ID		 2314 */
2315 if (rt2x00_get_field16(eeprom, EEPROM_ANTENNA_NUM) == 2)
2316 __set_bit(CONFIG_DOUBLE_ANTENNA, &rt2x00dev->flags);
2317
95ea3627
ID		 2318 /*
2319 * Identify default antenna configuration.
2320 */
addc81bd 2321 rt2x00dev->default_ant.tx =
95ea3627 2322 rt2x00_get_field16(eeprom, EEPROM_ANTENNA_TX_DEFAULT);
addc81bd 2323 rt2x00dev->default_ant.rx =
95ea3627
ID		 2324 rt2x00_get_field16(eeprom, EEPROM_ANTENNA_RX_DEFAULT);
2325
2326 /*
2327 * Read the Frame type.
2328 */
2329 if (rt2x00_get_field16(eeprom, EEPROM_ANTENNA_FRAME_TYPE))
2330 __set_bit(CONFIG_FRAME_TYPE, &rt2x00dev->flags);
2331
95ea3627
ID		 2332 /*
2333 * Detect if this device has an hardware controlled radio.
2334 */
2335 if (rt2x00_get_field16(eeprom, EEPROM_ANTENNA_HARDWARE_RADIO))
066cb637 2336 __set_bit(CONFIG_SUPPORT_HW_BUTTON, &rt2x00dev->flags);
95ea3627
ID		 2337
2338 /*
2339 * Read frequency offset and RF programming sequence.
2340 */
2341 rt2x00_eeprom_read(rt2x00dev, EEPROM_FREQ, &eeprom);
2342 if (rt2x00_get_field16(eeprom, EEPROM_FREQ_SEQ))
2343 __set_bit(CONFIG_RF_SEQUENCE, &rt2x00dev->flags);
2344
2345 rt2x00dev->freq_offset = rt2x00_get_field16(eeprom, EEPROM_FREQ_OFFSET);
2346
2347 /*
2348 * Read external LNA informations.
2349 */
2350 rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC, &eeprom);
2351
2352 if (rt2x00_get_field16(eeprom, EEPROM_NIC_EXTERNAL_LNA_A))
2353 __set_bit(CONFIG_EXTERNAL_LNA_A, &rt2x00dev->flags);
2354 if (rt2x00_get_field16(eeprom, EEPROM_NIC_EXTERNAL_LNA_BG))
2355 __set_bit(CONFIG_EXTERNAL_LNA_BG, &rt2x00dev->flags);
2356
e4cd2ff8
ID		 2357 /*
2358 * When working with a RF2529 chip without double antenna
2359 * the antenna settings should be gathered from the NIC
2360 * eeprom word.
2361 */
2362 if (rt2x00_rf(&rt2x00dev->chip, RF2529) &&
2363 !test_bit(CONFIG_DOUBLE_ANTENNA, &rt2x00dev->flags)) {
91581b62
ID		 2364 rt2x00dev->default_ant.rx =
2365 ANTENNA_A + rt2x00_get_field16(eeprom, EEPROM_NIC_RX_FIXED);
2366 rt2x00dev->default_ant.tx =
2367 ANTENNA_B - rt2x00_get_field16(eeprom, EEPROM_NIC_TX_FIXED);
e4cd2ff8
ID		 2368
2369 if (rt2x00_get_field16(eeprom, EEPROM_NIC_TX_DIVERSITY))
2370 rt2x00dev->default_ant.tx = ANTENNA_SW_DIVERSITY;
2371 if (rt2x00_get_field16(eeprom, EEPROM_NIC_ENABLE_DIVERSITY))
2372 rt2x00dev->default_ant.rx = ANTENNA_SW_DIVERSITY;
2373 }
2374
95ea3627
ID		 2375 /*
2376 * Store led settings, for correct led behaviour.
2377 * If the eeprom value is invalid,
2378 * switch to default led mode.
2379 */
771fd565 2380#ifdef CONFIG_RT2X00_LIB_LEDS
95ea3627 2381 rt2x00_eeprom_read(rt2x00dev, EEPROM_LED, &eeprom);
a9450b70
ID		 2382 value = rt2x00_get_field16(eeprom, EEPROM_LED_LED_MODE);
2383
475433be
ID		 2384 rt61pci_init_led(rt2x00dev, &rt2x00dev->led_radio, LED_TYPE_RADIO);
2385 rt61pci_init_led(rt2x00dev, &rt2x00dev->led_assoc, LED_TYPE_ASSOC);
2386 if (value == LED_MODE_SIGNAL_STRENGTH)
2387 rt61pci_init_led(rt2x00dev, &rt2x00dev->led_qual,
2388 LED_TYPE_QUALITY);
95ea3627 2389
a9450b70
ID		 2390 rt2x00_set_field16(&rt2x00dev->led_mcu_reg, MCU_LEDCS_LED_MODE, value);
2391 rt2x00_set_field16(&rt2x00dev->led_mcu_reg, MCU_LEDCS_POLARITY_GPIO_0,
95ea3627
ID		 2392 rt2x00_get_field16(eeprom,
2393 EEPROM_LED_POLARITY_GPIO_0));
a9450b70 2394 rt2x00_set_field16(&rt2x00dev->led_mcu_reg, MCU_LEDCS_POLARITY_GPIO_1,
95ea3627
ID		 2395 rt2x00_get_field16(eeprom,
2396 EEPROM_LED_POLARITY_GPIO_1));
a9450b70 2397 rt2x00_set_field16(&rt2x00dev->led_mcu_reg, MCU_LEDCS_POLARITY_GPIO_2,
95ea3627
ID		 2398 rt2x00_get_field16(eeprom,
2399 EEPROM_LED_POLARITY_GPIO_2));
a9450b70 2400 rt2x00_set_field16(&rt2x00dev->led_mcu_reg, MCU_LEDCS_POLARITY_GPIO_3,
95ea3627
ID		 2401 rt2x00_get_field16(eeprom,
2402 EEPROM_LED_POLARITY_GPIO_3));
a9450b70 2403 rt2x00_set_field16(&rt2x00dev->led_mcu_reg, MCU_LEDCS_POLARITY_GPIO_4,
95ea3627
ID		 2404 rt2x00_get_field16(eeprom,
2405 EEPROM_LED_POLARITY_GPIO_4));
a9450b70 2406 rt2x00_set_field16(&rt2x00dev->led_mcu_reg, MCU_LEDCS_POLARITY_ACT,
95ea3627 2407 rt2x00_get_field16(eeprom, EEPROM_LED_POLARITY_ACT));
a9450b70 2408 rt2x00_set_field16(&rt2x00dev->led_mcu_reg, MCU_LEDCS_POLARITY_READY_BG,
95ea3627
ID		 2409 rt2x00_get_field16(eeprom,
2410 EEPROM_LED_POLARITY_RDY_G));
a9450b70 2411 rt2x00_set_field16(&rt2x00dev->led_mcu_reg, MCU_LEDCS_POLARITY_READY_A,
95ea3627
ID		 2412 rt2x00_get_field16(eeprom,
2413 EEPROM_LED_POLARITY_RDY_A));
771fd565 2414#endif /* CONFIG_RT2X00_LIB_LEDS */
95ea3627
ID		 2415
2416 return 0;
2417}
2418
2419/*
2420 * RF value list for RF5225 & RF5325
2421 * Supports: 2.4 GHz & 5.2 GHz, rf_sequence disabled
2422 */
2423static const struct rf_channel rf_vals_noseq[] = {
2424 { 1, 0x00002ccc, 0x00004786, 0x00068455, 0x000ffa0b },
2425 { 2, 0x00002ccc, 0x00004786, 0x00068455, 0x000ffa1f },
2426 { 3, 0x00002ccc, 0x0000478a, 0x00068455, 0x000ffa0b },
2427 { 4, 0x00002ccc, 0x0000478a, 0x00068455, 0x000ffa1f },
2428 { 5, 0x00002ccc, 0x0000478e, 0x00068455, 0x000ffa0b },
2429 { 6, 0x00002ccc, 0x0000478e, 0x00068455, 0x000ffa1f },
2430 { 7, 0x00002ccc, 0x00004792, 0x00068455, 0x000ffa0b },
2431 { 8, 0x00002ccc, 0x00004792, 0x00068455, 0x000ffa1f },
2432 { 9, 0x00002ccc, 0x00004796, 0x00068455, 0x000ffa0b },
2433 { 10, 0x00002ccc, 0x00004796, 0x00068455, 0x000ffa1f },
2434 { 11, 0x00002ccc, 0x0000479a, 0x00068455, 0x000ffa0b },
2435 { 12, 0x00002ccc, 0x0000479a, 0x00068455, 0x000ffa1f },
2436 { 13, 0x00002ccc, 0x0000479e, 0x00068455, 0x000ffa0b },
2437 { 14, 0x00002ccc, 0x000047a2, 0x00068455, 0x000ffa13 },
2438
2439 /* 802.11 UNI / HyperLan 2 */
2440 { 36, 0x00002ccc, 0x0000499a, 0x0009be55, 0x000ffa23 },
2441 { 40, 0x00002ccc, 0x000049a2, 0x0009be55, 0x000ffa03 },
2442 { 44, 0x00002ccc, 0x000049a6, 0x0009be55, 0x000ffa0b },
2443 { 48, 0x00002ccc, 0x000049aa, 0x0009be55, 0x000ffa13 },
2444 { 52, 0x00002ccc, 0x000049ae, 0x0009ae55, 0x000ffa1b },
2445 { 56, 0x00002ccc, 0x000049b2, 0x0009ae55, 0x000ffa23 },
2446 { 60, 0x00002ccc, 0x000049ba, 0x0009ae55, 0x000ffa03 },
2447 { 64, 0x00002ccc, 0x000049be, 0x0009ae55, 0x000ffa0b },
2448
2449 /* 802.11 HyperLan 2 */
2450 { 100, 0x00002ccc, 0x00004a2a, 0x000bae55, 0x000ffa03 },
2451 { 104, 0x00002ccc, 0x00004a2e, 0x000bae55, 0x000ffa0b },
2452 { 108, 0x00002ccc, 0x00004a32, 0x000bae55, 0x000ffa13 },
2453 { 112, 0x00002ccc, 0x00004a36, 0x000bae55, 0x000ffa1b },
2454 { 116, 0x00002ccc, 0x00004a3a, 0x000bbe55, 0x000ffa23 },
2455 { 120, 0x00002ccc, 0x00004a82, 0x000bbe55, 0x000ffa03 },
2456 { 124, 0x00002ccc, 0x00004a86, 0x000bbe55, 0x000ffa0b },
2457 { 128, 0x00002ccc, 0x00004a8a, 0x000bbe55, 0x000ffa13 },
2458 { 132, 0x00002ccc, 0x00004a8e, 0x000bbe55, 0x000ffa1b },
2459 { 136, 0x00002ccc, 0x00004a92, 0x000bbe55, 0x000ffa23 },
2460
2461 /* 802.11 UNII */
2462 { 140, 0x00002ccc, 0x00004a9a, 0x000bbe55, 0x000ffa03 },
2463 { 149, 0x00002ccc, 0x00004aa2, 0x000bbe55, 0x000ffa1f },
2464 { 153, 0x00002ccc, 0x00004aa6, 0x000bbe55, 0x000ffa27 },
2465 { 157, 0x00002ccc, 0x00004aae, 0x000bbe55, 0x000ffa07 },
2466 { 161, 0x00002ccc, 0x00004ab2, 0x000bbe55, 0x000ffa0f },
2467 { 165, 0x00002ccc, 0x00004ab6, 0x000bbe55, 0x000ffa17 },
2468
2469 /* MMAC(Japan)J52 ch 34,38,42,46 */
2470 { 34, 0x00002ccc, 0x0000499a, 0x0009be55, 0x000ffa0b },
2471 { 38, 0x00002ccc, 0x0000499e, 0x0009be55, 0x000ffa13 },
2472 { 42, 0x00002ccc, 0x000049a2, 0x0009be55, 0x000ffa1b },
2473 { 46, 0x00002ccc, 0x000049a6, 0x0009be55, 0x000ffa23 },
2474};
2475
2476/*
2477 * RF value list for RF5225 & RF5325
2478 * Supports: 2.4 GHz & 5.2 GHz, rf_sequence enabled
2479 */
2480static const struct rf_channel rf_vals_seq[] = {
2481 { 1, 0x00002ccc, 0x00004786, 0x00068455, 0x000ffa0b },
2482 { 2, 0x00002ccc, 0x00004786, 0x00068455, 0x000ffa1f },
2483 { 3, 0x00002ccc, 0x0000478a, 0x00068455, 0x000ffa0b },
2484 { 4, 0x00002ccc, 0x0000478a, 0x00068455, 0x000ffa1f },
2485 { 5, 0x00002ccc, 0x0000478e, 0x00068455, 0x000ffa0b },
2486 { 6, 0x00002ccc, 0x0000478e, 0x00068455, 0x000ffa1f },
2487 { 7, 0x00002ccc, 0x00004792, 0x00068455, 0x000ffa0b },
2488 { 8, 0x00002ccc, 0x00004792, 0x00068455, 0x000ffa1f },
2489 { 9, 0x00002ccc, 0x00004796, 0x00068455, 0x000ffa0b },
2490 { 10, 0x00002ccc, 0x00004796, 0x00068455, 0x000ffa1f },
2491 { 11, 0x00002ccc, 0x0000479a, 0x00068455, 0x000ffa0b },
2492 { 12, 0x00002ccc, 0x0000479a, 0x00068455, 0x000ffa1f },
2493 { 13, 0x00002ccc, 0x0000479e, 0x00068455, 0x000ffa0b },
2494 { 14, 0x00002ccc, 0x000047a2, 0x00068455, 0x000ffa13 },
2495
2496 /* 802.11 UNI / HyperLan 2 */
2497 { 36, 0x00002cd4, 0x0004481a, 0x00098455, 0x000c0a03 },
2498 { 40, 0x00002cd0, 0x00044682, 0x00098455, 0x000c0a03 },
2499 { 44, 0x00002cd0, 0x00044686, 0x00098455, 0x000c0a1b },
2500 { 48, 0x00002cd0, 0x0004468e, 0x00098655, 0x000c0a0b },
2501 { 52, 0x00002cd0, 0x00044692, 0x00098855, 0x000c0a23 },
2502 { 56, 0x00002cd0, 0x0004469a, 0x00098c55, 0x000c0a13 },
2503 { 60, 0x00002cd0, 0x000446a2, 0x00098e55, 0x000c0a03 },
2504 { 64, 0x00002cd0, 0x000446a6, 0x00099255, 0x000c0a1b },
2505
2506 /* 802.11 HyperLan 2 */
2507 { 100, 0x00002cd4, 0x0004489a, 0x000b9855, 0x000c0a03 },
2508 { 104, 0x00002cd4, 0x000448a2, 0x000b9855, 0x000c0a03 },
2509 { 108, 0x00002cd4, 0x000448aa, 0x000b9855, 0x000c0a03 },
2510 { 112, 0x00002cd4, 0x000448b2, 0x000b9a55, 0x000c0a03 },
2511 { 116, 0x00002cd4, 0x000448ba, 0x000b9a55, 0x000c0a03 },
2512 { 120, 0x00002cd0, 0x00044702, 0x000b9a55, 0x000c0a03 },
2513 { 124, 0x00002cd0, 0x00044706, 0x000b9a55, 0x000c0a1b },
2514 { 128, 0x00002cd0, 0x0004470e, 0x000b9c55, 0x000c0a0b },
2515 { 132, 0x00002cd0, 0x00044712, 0x000b9c55, 0x000c0a23 },
2516 { 136, 0x00002cd0, 0x0004471a, 0x000b9e55, 0x000c0a13 },
2517
2518 /* 802.11 UNII */
2519 { 140, 0x00002cd0, 0x00044722, 0x000b9e55, 0x000c0a03 },
2520 { 149, 0x00002cd0, 0x0004472e, 0x000ba255, 0x000c0a1b },
2521 { 153, 0x00002cd0, 0x00044736, 0x000ba255, 0x000c0a0b },
2522 { 157, 0x00002cd4, 0x0004490a, 0x000ba255, 0x000c0a17 },
2523 { 161, 0x00002cd4, 0x00044912, 0x000ba255, 0x000c0a17 },
2524 { 165, 0x00002cd4, 0x0004491a, 0x000ba255, 0x000c0a17 },
2525
2526 /* MMAC(Japan)J52 ch 34,38,42,46 */
2527 { 34, 0x00002ccc, 0x0000499a, 0x0009be55, 0x000c0a0b },
2528 { 38, 0x00002ccc, 0x0000499e, 0x0009be55, 0x000c0a13 },
2529 { 42, 0x00002ccc, 0x000049a2, 0x0009be55, 0x000c0a1b },
2530 { 46, 0x00002ccc, 0x000049a6, 0x0009be55, 0x000c0a23 },
2531};
2532
8c5e7a5f 2533static int rt61pci_probe_hw_mode(struct rt2x00_dev *rt2x00dev)
95ea3627
ID		 2534{
2535 struct hw_mode_spec *spec = &rt2x00dev->spec;
8c5e7a5f
ID		 2536 struct channel_info *info;
2537 char *tx_power;
95ea3627
ID		 2538 unsigned int i;
2539
2540 /*
2541 * Initialize all hw fields.
2542 */
2543 rt2x00dev->hw->flags =
566bfe5a 2544 IEEE80211_HW_HOST_BROADCAST_PS_BUFFERING |
4be8c387
JB		 2545 IEEE80211_HW_SIGNAL_DBM |
2546 IEEE80211_HW_SUPPORTS_PS |
2547 IEEE80211_HW_PS_NULLFUNC_STACK;
95ea3627 2548 rt2x00dev->hw->extra_tx_headroom = 0;
95ea3627 2549
14a3bf89 2550 SET_IEEE80211_DEV(rt2x00dev->hw, rt2x00dev->dev);
95ea3627
ID		 2551 SET_IEEE80211_PERM_ADDR(rt2x00dev->hw,
2552 rt2x00_eeprom_addr(rt2x00dev,
2553 EEPROM_MAC_ADDR_0));
2554
95ea3627
ID		 2555 /*
2556 * Initialize hw_mode information.
2557 */
31562e80
ID		 2558 spec->supported_bands = SUPPORT_BAND_2GHZ;
2559 spec->supported_rates = SUPPORT_RATE_CCK | SUPPORT_RATE_OFDM;
95ea3627
ID		 2560
2561 if (!test_bit(CONFIG_RF_SEQUENCE, &rt2x00dev->flags)) {
2562 spec->num_channels = 14;
2563 spec->channels = rf_vals_noseq;
2564 } else {
2565 spec->num_channels = 14;
2566 spec->channels = rf_vals_seq;
2567 }
2568
2569 if (rt2x00_rf(&rt2x00dev->chip, RF5225) ||
2570 rt2x00_rf(&rt2x00dev->chip, RF5325)) {
31562e80 2571 spec->supported_bands |= SUPPORT_BAND_5GHZ;
95ea3627 2572 spec->num_channels = ARRAY_SIZE(rf_vals_seq);
8c5e7a5f
ID		 2573 }
2574
2575 /*
2576 * Create channel information array
2577 */
2578 info = kzalloc(spec->num_channels * sizeof(*info), GFP_KERNEL);
2579 if (!info)
2580 return -ENOMEM;
2581
2582 spec->channels_info = info;
95ea3627 2583
8c5e7a5f
ID		 2584 tx_power = rt2x00_eeprom_addr(rt2x00dev, EEPROM_TXPOWER_G_START);
2585 for (i = 0; i < 14; i++)
2586 info[i].tx_power1 = TXPOWER_FROM_DEV(tx_power[i]);
95ea3627 2587
8c5e7a5f
ID		 2588 if (spec->num_channels > 14) {
2589 tx_power = rt2x00_eeprom_addr(rt2x00dev, EEPROM_TXPOWER_A_START);
2590 for (i = 14; i < spec->num_channels; i++)
2591 info[i].tx_power1 = TXPOWER_FROM_DEV(tx_power[i]);
95ea3627 2592 }
8c5e7a5f
ID		 2593
2594 return 0;
95ea3627
ID		 2595}
2596
2597static int rt61pci_probe_hw(struct rt2x00_dev *rt2x00dev)
2598{
2599 int retval;
2600
117839bd
PR		 2601 /*
2602 * Disable power saving.
2603 */
2604 rt2x00pci_register_write(rt2x00dev, SOFT_RESET_CSR, 0x00000007);
2605
95ea3627
ID		 2606 /*
2607 * Allocate eeprom data.
2608 */
2609 retval = rt61pci_validate_eeprom(rt2x00dev);
2610 if (retval)
2611 return retval;
2612
2613 retval = rt61pci_init_eeprom(rt2x00dev);
2614 if (retval)
2615 return retval;
2616
2617 /*
2618 * Initialize hw specifications.
2619 */
8c5e7a5f
ID		 2620 retval = rt61pci_probe_hw_mode(rt2x00dev);
2621 if (retval)
2622 return retval;
95ea3627 2623
1afcfd54
IP		 2624 /*
2625 * This device has multiple filters for control frames,
2626 * but has no a separate filter for PS Poll frames.
2627 */
2628 __set_bit(DRIVER_SUPPORT_CONTROL_FILTERS, &rt2x00dev->flags);
2629
95ea3627 2630 /*
c4da0048 2631 * This device requires firmware and DMA mapped skbs.
95ea3627 2632 */
066cb637 2633 __set_bit(DRIVER_REQUIRE_FIRMWARE, &rt2x00dev->flags);
c4da0048 2634 __set_bit(DRIVER_REQUIRE_DMA, &rt2x00dev->flags);
008c4482
ID		 2635 if (!modparam_nohwcrypt)
2636 __set_bit(CONFIG_SUPPORT_HW_CRYPTO, &rt2x00dev->flags);
95ea3627
ID		 2637
2638 /*
2639 * Set the rssi offset.
2640 */
2641 rt2x00dev->rssi_offset = DEFAULT_RSSI_OFFSET;
2642
2643 return 0;
2644}
2645
2646/*
2647 * IEEE80211 stack callback functions.
2648 */
2af0a570
ID		 2649static int rt61pci_conf_tx(struct ieee80211_hw *hw, u16 queue_idx,
2650 const struct ieee80211_tx_queue_params *params)
2651{
2652 struct rt2x00_dev *rt2x00dev = hw->priv;
2653 struct data_queue *queue;
2654 struct rt2x00_field32 field;
2655 int retval;
2656 u32 reg;
5e790023 2657 u32 offset;
2af0a570
ID		 2658
2659 /*
2660 * First pass the configuration through rt2x00lib, that will
2661 * update the queue settings and validate the input. After that
2662 * we are free to update the registers based on the value
2663 * in the queue parameter.
2664 */
2665 retval = rt2x00mac_conf_tx(hw, queue_idx, params);
2666 if (retval)
2667 return retval;
2668
5e790023
ID		 2669 /*
2670 * We only need to perform additional register initialization
2671 * for WMM queues/
2672 */
2673 if (queue_idx >= 4)
2674 return 0;
2675
2af0a570
ID		 2676 queue = rt2x00queue_get_queue(rt2x00dev, queue_idx);
2677
2678 /* Update WMM TXOP register */
5e790023
ID		 2679 offset = AC_TXOP_CSR0 + (sizeof(u32) * (!!(queue_idx & 2)));
2680 field.bit_offset = (queue_idx & 1) * 16;
2681 field.bit_mask = 0xffff << field.bit_offset;
2682
2683 rt2x00pci_register_read(rt2x00dev, offset, &reg);
2684 rt2x00_set_field32(&reg, field, queue->txop);
2685 rt2x00pci_register_write(rt2x00dev, offset, reg);
2af0a570
ID		 2686
2687 /* Update WMM registers */
2688 field.bit_offset = queue_idx * 4;
2689 field.bit_mask = 0xf << field.bit_offset;
2690
2691 rt2x00pci_register_read(rt2x00dev, AIFSN_CSR, &reg);
2692 rt2x00_set_field32(&reg, field, queue->aifs);
2693 rt2x00pci_register_write(rt2x00dev, AIFSN_CSR, reg);
2694
2695 rt2x00pci_register_read(rt2x00dev, CWMIN_CSR, &reg);
2696 rt2x00_set_field32(&reg, field, queue->cw_min);
2697 rt2x00pci_register_write(rt2x00dev, CWMIN_CSR, reg);
2698
2699 rt2x00pci_register_read(rt2x00dev, CWMAX_CSR, &reg);
2700 rt2x00_set_field32(&reg, field, queue->cw_max);
2701 rt2x00pci_register_write(rt2x00dev, CWMAX_CSR, reg);
2702
2703 return 0;
2704}
2705
95ea3627
ID		 2706static u64 rt61pci_get_tsf(struct ieee80211_hw *hw)
2707{
2708 struct rt2x00_dev *rt2x00dev = hw->priv;
2709 u64 tsf;
2710 u32 reg;
2711
2712 rt2x00pci_register_read(rt2x00dev, TXRX_CSR13, &reg);
2713 tsf = (u64) rt2x00_get_field32(reg, TXRX_CSR13_HIGH_TSFTIMER) << 32;
2714 rt2x00pci_register_read(rt2x00dev, TXRX_CSR12, &reg);
2715 tsf |= rt2x00_get_field32(reg, TXRX_CSR12_LOW_TSFTIMER);
2716
2717 return tsf;
2718}
2719
95ea3627
ID		 2720static const struct ieee80211_ops rt61pci_mac80211_ops = {
2721 .tx = rt2x00mac_tx,
4150c572
JB		 2722 .start = rt2x00mac_start,
2723 .stop = rt2x00mac_stop,
95ea3627
ID		 2724 .add_interface = rt2x00mac_add_interface,
2725 .remove_interface = rt2x00mac_remove_interface,
2726 .config = rt2x00mac_config,
3a643d24 2727 .configure_filter = rt2x00mac_configure_filter,
930c06f2 2728 .set_tim = rt2x00mac_set_tim,
61e754f4 2729 .set_key = rt2x00mac_set_key,
95ea3627 2730 .get_stats = rt2x00mac_get_stats,
471b3efd 2731 .bss_info_changed = rt2x00mac_bss_info_changed,
2af0a570 2732 .conf_tx = rt61pci_conf_tx,
95ea3627
ID		 2733 .get_tx_stats = rt2x00mac_get_tx_stats,
2734 .get_tsf = rt61pci_get_tsf,
e47a5cdd 2735 .rfkill_poll = rt2x00mac_rfkill_poll,
95ea3627
ID		 2736};
2737
2738static const struct rt2x00lib_ops rt61pci_rt2x00_ops = {
2739 .irq_handler = rt61pci_interrupt,
2740 .probe_hw = rt61pci_probe_hw,
2741 .get_firmware_name = rt61pci_get_firmware_name,
0cbe0064 2742 .check_firmware = rt61pci_check_firmware,
95ea3627
ID		 2743 .load_firmware = rt61pci_load_firmware,
2744 .initialize = rt2x00pci_initialize,
2745 .uninitialize = rt2x00pci_uninitialize,
798b7adb
ID		 2746 .get_entry_state = rt61pci_get_entry_state,
2747 .clear_entry = rt61pci_clear_entry,
95ea3627 2748 .set_device_state = rt61pci_set_device_state,
95ea3627 2749 .rfkill_poll = rt61pci_rfkill_poll,
95ea3627
ID		 2750 .link_stats = rt61pci_link_stats,
2751 .reset_tuner = rt61pci_reset_tuner,
2752 .link_tuner = rt61pci_link_tuner,
2753 .write_tx_desc = rt61pci_write_tx_desc,
2754 .write_tx_data = rt2x00pci_write_tx_data,
bd88a781 2755 .write_beacon = rt61pci_write_beacon,
95ea3627 2756 .kick_tx_queue = rt61pci_kick_tx_queue,
a2c9b652 2757 .kill_tx_queue = rt61pci_kill_tx_queue,
95ea3627 2758 .fill_rxdone = rt61pci_fill_rxdone,
61e754f4
ID		 2759 .config_shared_key = rt61pci_config_shared_key,
2760 .config_pairwise_key = rt61pci_config_pairwise_key,
3a643d24 2761 .config_filter = rt61pci_config_filter,
6bb40dd1 2762 .config_intf = rt61pci_config_intf,
72810379 2763 .config_erp = rt61pci_config_erp,
e4ea1c40 2764 .config_ant = rt61pci_config_ant,
95ea3627
ID		 2765 .config = rt61pci_config,
2766};
2767
181d6902
ID		 2768static const struct data_queue_desc rt61pci_queue_rx = {
2769 .entry_num = RX_ENTRIES,
2770 .data_size = DATA_FRAME_SIZE,
2771 .desc_size = RXD_DESC_SIZE,
b8be63ff 2772 .priv_size = sizeof(struct queue_entry_priv_pci),
181d6902
ID		 2773};
2774
2775static const struct data_queue_desc rt61pci_queue_tx = {
2776 .entry_num = TX_ENTRIES,
2777 .data_size = DATA_FRAME_SIZE,
2778 .desc_size = TXD_DESC_SIZE,
b8be63ff 2779 .priv_size = sizeof(struct queue_entry_priv_pci),
181d6902
ID		 2780};
2781
2782static const struct data_queue_desc rt61pci_queue_bcn = {
6bb40dd1 2783 .entry_num = 4 * BEACON_ENTRIES,
78720897 2784 .data_size = 0, /* No DMA required for beacons */
181d6902 2785 .desc_size = TXINFO_SIZE,
b8be63ff 2786 .priv_size = sizeof(struct queue_entry_priv_pci),
181d6902
ID		 2787};
2788
95ea3627 2789static const struct rt2x00_ops rt61pci_ops = {
2360157c 2790 .name = KBUILD_MODNAME,
6bb40dd1
ID		 2791 .max_sta_intf = 1,
2792 .max_ap_intf = 4,
95ea3627
ID		 2793 .eeprom_size = EEPROM_SIZE,
2794 .rf_size = RF_SIZE,
61448f88 2795 .tx_queues = NUM_TX_QUEUES,
181d6902
ID		 2796 .rx = &rt61pci_queue_rx,
2797 .tx = &rt61pci_queue_tx,
2798 .bcn = &rt61pci_queue_bcn,
95ea3627
ID		 2799 .lib = &rt61pci_rt2x00_ops,
2800 .hw = &rt61pci_mac80211_ops,
2801#ifdef CONFIG_RT2X00_LIB_DEBUGFS
2802 .debugfs = &rt61pci_rt2x00debug,
2803#endif /* CONFIG_RT2X00_LIB_DEBUGFS */
2804};
2805
2806/*
2807 * RT61pci module information.
2808 */
2809static struct pci_device_id rt61pci_device_table[] = {
2810 /* RT2561s */
2811 { PCI_DEVICE(0x1814, 0x0301), PCI_DEVICE_DATA(&rt61pci_ops) },
2812 /* RT2561 v2 */
2813 { PCI_DEVICE(0x1814, 0x0302), PCI_DEVICE_DATA(&rt61pci_ops) },
2814 /* RT2661 */
2815 { PCI_DEVICE(0x1814, 0x0401), PCI_DEVICE_DATA(&rt61pci_ops) },
2816 { 0, }
2817};
2818
2819MODULE_AUTHOR(DRV_PROJECT);
2820MODULE_VERSION(DRV_VERSION);
2821MODULE_DESCRIPTION("Ralink RT61 PCI & PCMCIA Wireless LAN driver.");
2822MODULE_SUPPORTED_DEVICE("Ralink RT2561, RT2561s & RT2661 "
2823 "PCI & PCMCIA chipset based cards");
2824MODULE_DEVICE_TABLE(pci, rt61pci_device_table);
2825MODULE_FIRMWARE(FIRMWARE_RT2561);
2826MODULE_FIRMWARE(FIRMWARE_RT2561s);
2827MODULE_FIRMWARE(FIRMWARE_RT2661);
2828MODULE_LICENSE("GPL");
2829
2830static struct pci_driver rt61pci_driver = {
2360157c 2831 .name = KBUILD_MODNAME,
95ea3627
ID		 2832 .id_table = rt61pci_device_table,
2833 .probe = rt2x00pci_probe,
2834 .remove = __devexit_p(rt2x00pci_remove),
2835 .suspend = rt2x00pci_suspend,
2836 .resume = rt2x00pci_resume,
2837};
2838
2839static int __init rt61pci_init(void)
2840{
2841 return pci_register_driver(&rt61pci_driver);
2842}
2843
2844static void __exit rt61pci_exit(void)
2845{
2846 pci_unregister_driver(&rt61pci_driver);
2847}
2848
2849module_init(rt61pci_init);
2850module_exit(rt61pci_exit);
Linux kernel - Deliverables
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