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rt2x00: Add queue statistics to debugfs
[deliverable/linux.git] / drivers / net / wireless / rt2x00 / rt61pci.c
CommitLineData
95ea3627 1/*
811aa9ca 2 Copyright (C) 2004 - 2008 rt2x00 SourceForge Project
95ea3627
ID		 3 <http://rt2x00.serialmonkey.com>
4
5 This program is free software; you can redistribute it and/or modify
6 it under the terms of the GNU General Public License as published by
7 the Free Software Foundation; either version 2 of the License, or
8 (at your option) any later version.
9
10 This program is distributed in the hope that it will be useful,
11 but WITHOUT ANY WARRANTY; without even the implied warranty of
12 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 GNU General Public License for more details.
14
15 You should have received a copy of the GNU General Public License
16 along with this program; if not, write to the
17 Free Software Foundation, Inc.,
18 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
19 */
20
21/*
22 Module: rt61pci
23 Abstract: rt61pci device specific routines.
24 Supported chipsets: RT2561, RT2561s, RT2661.
25 */
26
95ea3627
ID		 27#include <linux/delay.h>
28#include <linux/etherdevice.h>
29#include <linux/init.h>
30#include <linux/kernel.h>
31#include <linux/module.h>
32#include <linux/pci.h>
33#include <linux/eeprom_93cx6.h>
34
35#include "rt2x00.h"
36#include "rt2x00pci.h"
37#include "rt61pci.h"
38
39/*
40 * Register access.
41 * BBP and RF register require indirect register access,
42 * and use the CSR registers PHY_CSR3 and PHY_CSR4 to achieve this.
43 * These indirect registers work with busy bits,
44 * and we will try maximal REGISTER_BUSY_COUNT times to access
45 * the register while taking a REGISTER_BUSY_DELAY us delay
46 * between each attampt. When the busy bit is still set at that time,
47 * the access attempt is considered to have failed,
48 * and we will print an error.
49 */
0e14f6d3 50static u32 rt61pci_bbp_check(struct rt2x00_dev *rt2x00dev)
95ea3627
ID		 51{
52 u32 reg;
53 unsigned int i;
54
55 for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
56 rt2x00pci_register_read(rt2x00dev, PHY_CSR3, &reg);
57 if (!rt2x00_get_field32(reg, PHY_CSR3_BUSY))
58 break;
59 udelay(REGISTER_BUSY_DELAY);
60 }
61
62 return reg;
63}
64
0e14f6d3 65static void rt61pci_bbp_write(struct rt2x00_dev *rt2x00dev,
95ea3627
ID		 66 const unsigned int word, const u8 value)
67{
68 u32 reg;
69
70 /*
71 * Wait until the BBP becomes ready.
72 */
73 reg = rt61pci_bbp_check(rt2x00dev);
74 if (rt2x00_get_field32(reg, PHY_CSR3_BUSY)) {
75 ERROR(rt2x00dev, "PHY_CSR3 register busy. Write failed.\n");
76 return;
77 }
78
79 /*
80 * Write the data into the BBP.
81 */
82 reg = 0;
83 rt2x00_set_field32(&reg, PHY_CSR3_VALUE, value);
84 rt2x00_set_field32(&reg, PHY_CSR3_REGNUM, word);
85 rt2x00_set_field32(&reg, PHY_CSR3_BUSY, 1);
86 rt2x00_set_field32(&reg, PHY_CSR3_READ_CONTROL, 0);
87
88 rt2x00pci_register_write(rt2x00dev, PHY_CSR3, reg);
89}
90
0e14f6d3 91static void rt61pci_bbp_read(struct rt2x00_dev *rt2x00dev,
95ea3627
ID		 92 const unsigned int word, u8 *value)
93{
94 u32 reg;
95
96 /*
97 * Wait until the BBP becomes ready.
98 */
99 reg = rt61pci_bbp_check(rt2x00dev);
100 if (rt2x00_get_field32(reg, PHY_CSR3_BUSY)) {
101 ERROR(rt2x00dev, "PHY_CSR3 register busy. Read failed.\n");
102 return;
103 }
104
105 /*
106 * Write the request into the BBP.
107 */
108 reg = 0;
109 rt2x00_set_field32(&reg, PHY_CSR3_REGNUM, word);
110 rt2x00_set_field32(&reg, PHY_CSR3_BUSY, 1);
111 rt2x00_set_field32(&reg, PHY_CSR3_READ_CONTROL, 1);
112
113 rt2x00pci_register_write(rt2x00dev, PHY_CSR3, reg);
114
115 /*
116 * Wait until the BBP becomes ready.
117 */
118 reg = rt61pci_bbp_check(rt2x00dev);
119 if (rt2x00_get_field32(reg, PHY_CSR3_BUSY)) {
120 ERROR(rt2x00dev, "PHY_CSR3 register busy. Read failed.\n");
121 *value = 0xff;
122 return;
123 }
124
125 *value = rt2x00_get_field32(reg, PHY_CSR3_VALUE);
126}
127
0e14f6d3 128static void rt61pci_rf_write(struct rt2x00_dev *rt2x00dev,
95ea3627
ID		 129 const unsigned int word, const u32 value)
130{
131 u32 reg;
132 unsigned int i;
133
134 if (!word)
135 return;
136
137 for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
138 rt2x00pci_register_read(rt2x00dev, PHY_CSR4, &reg);
139 if (!rt2x00_get_field32(reg, PHY_CSR4_BUSY))
140 goto rf_write;
141 udelay(REGISTER_BUSY_DELAY);
142 }
143
144 ERROR(rt2x00dev, "PHY_CSR4 register busy. Write failed.\n");
145 return;
146
147rf_write:
148 reg = 0;
149 rt2x00_set_field32(&reg, PHY_CSR4_VALUE, value);
150 rt2x00_set_field32(&reg, PHY_CSR4_NUMBER_OF_BITS, 21);
151 rt2x00_set_field32(&reg, PHY_CSR4_IF_SELECT, 0);
152 rt2x00_set_field32(&reg, PHY_CSR4_BUSY, 1);
153
154 rt2x00pci_register_write(rt2x00dev, PHY_CSR4, reg);
155 rt2x00_rf_write(rt2x00dev, word, value);
156}
157
a9450b70
ID		 158#ifdef CONFIG_RT61PCI_LEDS
159/*
160 * This function is only called from rt61pci_led_brightness()
161 * make gcc happy by placing this function inside the
162 * same ifdef statement as the caller.
163 */
0e14f6d3 164static void rt61pci_mcu_request(struct rt2x00_dev *rt2x00dev,
95ea3627
ID		 165 const u8 command, const u8 token,
166 const u8 arg0, const u8 arg1)
167{
168 u32 reg;
169
170 rt2x00pci_register_read(rt2x00dev, H2M_MAILBOX_CSR, &reg);
171
172 if (rt2x00_get_field32(reg, H2M_MAILBOX_CSR_OWNER)) {
173 ERROR(rt2x00dev, "mcu request error. "
174 "Request 0x%02x failed for token 0x%02x.\n",
175 command, token);
176 return;
177 }
178
179 rt2x00_set_field32(&reg, H2M_MAILBOX_CSR_OWNER, 1);
180 rt2x00_set_field32(&reg, H2M_MAILBOX_CSR_CMD_TOKEN, token);
181 rt2x00_set_field32(&reg, H2M_MAILBOX_CSR_ARG0, arg0);
182 rt2x00_set_field32(&reg, H2M_MAILBOX_CSR_ARG1, arg1);
183 rt2x00pci_register_write(rt2x00dev, H2M_MAILBOX_CSR, reg);
184
185 rt2x00pci_register_read(rt2x00dev, HOST_CMD_CSR, &reg);
186 rt2x00_set_field32(&reg, HOST_CMD_CSR_HOST_COMMAND, command);
187 rt2x00_set_field32(&reg, HOST_CMD_CSR_INTERRUPT_MCU, 1);
188 rt2x00pci_register_write(rt2x00dev, HOST_CMD_CSR, reg);
189}
a9450b70 190#endif /* CONFIG_RT61PCI_LEDS */
95ea3627
ID		 191
192static void rt61pci_eepromregister_read(struct eeprom_93cx6 *eeprom)
193{
194 struct rt2x00_dev *rt2x00dev = eeprom->data;
195 u32 reg;
196
197 rt2x00pci_register_read(rt2x00dev, E2PROM_CSR, &reg);
198
199 eeprom->reg_data_in = !!rt2x00_get_field32(reg, E2PROM_CSR_DATA_IN);
200 eeprom->reg_data_out = !!rt2x00_get_field32(reg, E2PROM_CSR_DATA_OUT);
201 eeprom->reg_data_clock =
202 !!rt2x00_get_field32(reg, E2PROM_CSR_DATA_CLOCK);
203 eeprom->reg_chip_select =
204 !!rt2x00_get_field32(reg, E2PROM_CSR_CHIP_SELECT);
205}
206
207static void rt61pci_eepromregister_write(struct eeprom_93cx6 *eeprom)
208{
209 struct rt2x00_dev *rt2x00dev = eeprom->data;
210 u32 reg = 0;
211
212 rt2x00_set_field32(&reg, E2PROM_CSR_DATA_IN, !!eeprom->reg_data_in);
213 rt2x00_set_field32(&reg, E2PROM_CSR_DATA_OUT, !!eeprom->reg_data_out);
214 rt2x00_set_field32(&reg, E2PROM_CSR_DATA_CLOCK,
215 !!eeprom->reg_data_clock);
216 rt2x00_set_field32(&reg, E2PROM_CSR_CHIP_SELECT,
217 !!eeprom->reg_chip_select);
218
219 rt2x00pci_register_write(rt2x00dev, E2PROM_CSR, reg);
220}
221
222#ifdef CONFIG_RT2X00_LIB_DEBUGFS
223#define CSR_OFFSET(__word) ( CSR_REG_BASE + ((__word) * sizeof(u32)) )
224
0e14f6d3 225static void rt61pci_read_csr(struct rt2x00_dev *rt2x00dev,
95ea3627
ID		 226 const unsigned int word, u32 *data)
227{
228 rt2x00pci_register_read(rt2x00dev, CSR_OFFSET(word), data);
229}
230
0e14f6d3 231static void rt61pci_write_csr(struct rt2x00_dev *rt2x00dev,
95ea3627
ID		 232 const unsigned int word, u32 data)
233{
234 rt2x00pci_register_write(rt2x00dev, CSR_OFFSET(word), data);
235}
236
237static const struct rt2x00debug rt61pci_rt2x00debug = {
238 .owner = THIS_MODULE,
239 .csr = {
240 .read = rt61pci_read_csr,
241 .write = rt61pci_write_csr,
242 .word_size = sizeof(u32),
243 .word_count = CSR_REG_SIZE / sizeof(u32),
244 },
245 .eeprom = {
246 .read = rt2x00_eeprom_read,
247 .write = rt2x00_eeprom_write,
248 .word_size = sizeof(u16),
249 .word_count = EEPROM_SIZE / sizeof(u16),
250 },
251 .bbp = {
252 .read = rt61pci_bbp_read,
253 .write = rt61pci_bbp_write,
254 .word_size = sizeof(u8),
255 .word_count = BBP_SIZE / sizeof(u8),
256 },
257 .rf = {
258 .read = rt2x00_rf_read,
259 .write = rt61pci_rf_write,
260 .word_size = sizeof(u32),
261 .word_count = RF_SIZE / sizeof(u32),
262 },
263};
264#endif /* CONFIG_RT2X00_LIB_DEBUGFS */
265
266#ifdef CONFIG_RT61PCI_RFKILL
267static int rt61pci_rfkill_poll(struct rt2x00_dev *rt2x00dev)
268{
269 u32 reg;
270
271 rt2x00pci_register_read(rt2x00dev, MAC_CSR13, &reg);
181d6902 272 return rt2x00_get_field32(reg, MAC_CSR13_BIT5);
95ea3627 273}
81873e9c
ID		 274#else
275#define rt61pci_rfkill_poll NULL
dcf5475b 276#endif /* CONFIG_RT61PCI_RFKILL */
95ea3627 277
a9450b70
ID		 278#ifdef CONFIG_RT61PCI_LEDS
279static void rt61pci_led_brightness(struct led_classdev *led_cdev,
280 enum led_brightness brightness)
281{
282 struct rt2x00_led *led =
283 container_of(led_cdev, struct rt2x00_led, led_dev);
284 unsigned int enabled = brightness != LED_OFF;
285 unsigned int a_mode =
286 (enabled && led->rt2x00dev->curr_band == IEEE80211_BAND_5GHZ);
287 unsigned int bg_mode =
288 (enabled && led->rt2x00dev->curr_band == IEEE80211_BAND_2GHZ);
289
290 if (led->type == LED_TYPE_RADIO) {
291 rt2x00_set_field16(&led->rt2x00dev->led_mcu_reg,
292 MCU_LEDCS_RADIO_STATUS, enabled);
293
294 rt61pci_mcu_request(led->rt2x00dev, MCU_LED, 0xff,
295 (led->rt2x00dev->led_mcu_reg & 0xff),
296 ((led->rt2x00dev->led_mcu_reg >> 8)));
297 } else if (led->type == LED_TYPE_ASSOC) {
298 rt2x00_set_field16(&led->rt2x00dev->led_mcu_reg,
299 MCU_LEDCS_LINK_BG_STATUS, bg_mode);
300 rt2x00_set_field16(&led->rt2x00dev->led_mcu_reg,
301 MCU_LEDCS_LINK_A_STATUS, a_mode);
302
303 rt61pci_mcu_request(led->rt2x00dev, MCU_LED, 0xff,
304 (led->rt2x00dev->led_mcu_reg & 0xff),
305 ((led->rt2x00dev->led_mcu_reg >> 8)));
306 } else if (led->type == LED_TYPE_QUALITY) {
307 /*
308 * The brightness is divided into 6 levels (0 - 5),
309 * this means we need to convert the brightness
310 * argument into the matching level within that range.
311 */
312 rt61pci_mcu_request(led->rt2x00dev, MCU_LED_STRENGTH, 0xff,
313 brightness / (LED_FULL / 6), 0);
314 }
315}
316#else
317#define rt61pci_led_brightness NULL
318#endif /* CONFIG_RT61PCI_LEDS */
319
95ea3627
ID		 320/*
321 * Configuration handlers.
322 */
6bb40dd1
ID		 323static void rt61pci_config_intf(struct rt2x00_dev *rt2x00dev,
324 struct rt2x00_intf *intf,
325 struct rt2x00intf_conf *conf,
326 const unsigned int flags)
95ea3627 327{
6bb40dd1
ID		 328 unsigned int beacon_base;
329 u32 reg;
95ea3627 330
6bb40dd1
ID		 331 if (flags & CONFIG_UPDATE_TYPE) {
332 /*
333 * Clear current synchronisation setup.
334 * For the Beacon base registers we only need to clear
335 * the first byte since that byte contains the VALID and OWNER
336 * bits which (when set to 0) will invalidate the entire beacon.
337 */
338 beacon_base = HW_BEACON_OFFSET(intf->beacon->entry_idx);
339 rt2x00pci_register_write(rt2x00dev, TXRX_CSR9, 0);
340 rt2x00pci_register_write(rt2x00dev, beacon_base, 0);
95ea3627 341
6bb40dd1
ID		 342 /*
343 * Enable synchronisation.
344 */
345 rt2x00pci_register_read(rt2x00dev, TXRX_CSR9, &reg);
346 rt2x00_set_field32(&reg, TXRX_CSR9_TSF_TICKING, 1);
347 rt2x00_set_field32(&reg, TXRX_CSR9_TBTT_ENABLE,
348 (conf->sync == TSF_SYNC_BEACON));
349 rt2x00_set_field32(&reg, TXRX_CSR9_BEACON_GEN, 0);
350 rt2x00_set_field32(&reg, TXRX_CSR9_TSF_SYNC, conf->sync);
351 rt2x00pci_register_write(rt2x00dev, TXRX_CSR9, reg);
352 }
95ea3627 353
6bb40dd1
ID		 354 if (flags & CONFIG_UPDATE_MAC) {
355 reg = le32_to_cpu(conf->mac[1]);
356 rt2x00_set_field32(&reg, MAC_CSR3_UNICAST_TO_ME_MASK, 0xff);
357 conf->mac[1] = cpu_to_le32(reg);
95ea3627 358
6bb40dd1
ID		 359 rt2x00pci_register_multiwrite(rt2x00dev, MAC_CSR2,
360 conf->mac, sizeof(conf->mac));
361 }
95ea3627 362
6bb40dd1
ID		 363 if (flags & CONFIG_UPDATE_BSSID) {
364 reg = le32_to_cpu(conf->bssid[1]);
365 rt2x00_set_field32(&reg, MAC_CSR5_BSS_ID_MASK, 3);
366 conf->bssid[1] = cpu_to_le32(reg);
95ea3627 367
6bb40dd1
ID		 368 rt2x00pci_register_multiwrite(rt2x00dev, MAC_CSR4,
369 conf->bssid, sizeof(conf->bssid));
370 }
95ea3627
ID		 371}
372
6bb40dd1
ID		 373static int rt61pci_config_preamble(struct rt2x00_dev *rt2x00dev,
374 const int short_preamble,
375 const int ack_timeout,
376 const int ack_consume_time)
95ea3627 377{
95ea3627 378 u32 reg;
95ea3627
ID		 379
380 rt2x00pci_register_read(rt2x00dev, TXRX_CSR0, &reg);
5c58ee51 381 rt2x00_set_field32(&reg, TXRX_CSR0_RX_ACK_TIMEOUT, ack_timeout);
95ea3627
ID		 382 rt2x00pci_register_write(rt2x00dev, TXRX_CSR0, reg);
383
384 rt2x00pci_register_read(rt2x00dev, TXRX_CSR4, &reg);
4f5af6eb 385 rt2x00_set_field32(&reg, TXRX_CSR4_AUTORESPOND_PREAMBLE,
5c58ee51 386 !!short_preamble);
95ea3627 387 rt2x00pci_register_write(rt2x00dev, TXRX_CSR4, reg);
6bb40dd1
ID		 388
389 return 0;
95ea3627
ID		 390}
391
392static void rt61pci_config_phymode(struct rt2x00_dev *rt2x00dev,
5c58ee51 393 const int basic_rate_mask)
95ea3627 394{
5c58ee51 395 rt2x00pci_register_write(rt2x00dev, TXRX_CSR5, basic_rate_mask);
95ea3627
ID		 396}
397
5c58ee51
ID		 398static void rt61pci_config_channel(struct rt2x00_dev *rt2x00dev,
399 struct rf_channel *rf, const int txpower)
95ea3627
ID		 400{
401 u8 r3;
402 u8 r94;
403 u8 smart;
404
405 rt2x00_set_field32(&rf->rf3, RF3_TXPOWER, TXPOWER_TO_DEV(txpower));
406 rt2x00_set_field32(&rf->rf4, RF4_FREQ_OFFSET, rt2x00dev->freq_offset);
407
408 smart = !(rt2x00_rf(&rt2x00dev->chip, RF5225) ||
409 rt2x00_rf(&rt2x00dev->chip, RF2527));
410
411 rt61pci_bbp_read(rt2x00dev, 3, &r3);
412 rt2x00_set_field8(&r3, BBP_R3_SMART_MODE, smart);
413 rt61pci_bbp_write(rt2x00dev, 3, r3);
414
415 r94 = 6;
416 if (txpower > MAX_TXPOWER && txpower <= (MAX_TXPOWER + r94))
417 r94 += txpower - MAX_TXPOWER;
418 else if (txpower < MIN_TXPOWER && txpower >= (MIN_TXPOWER - r94))
419 r94 += txpower;
420 rt61pci_bbp_write(rt2x00dev, 94, r94);
421
422 rt61pci_rf_write(rt2x00dev, 1, rf->rf1);
423 rt61pci_rf_write(rt2x00dev, 2, rf->rf2);
424 rt61pci_rf_write(rt2x00dev, 3, rf->rf3 & ~0x00000004);
425 rt61pci_rf_write(rt2x00dev, 4, rf->rf4);
426
427 udelay(200);
428
429 rt61pci_rf_write(rt2x00dev, 1, rf->rf1);
430 rt61pci_rf_write(rt2x00dev, 2, rf->rf2);
431 rt61pci_rf_write(rt2x00dev, 3, rf->rf3 | 0x00000004);
432 rt61pci_rf_write(rt2x00dev, 4, rf->rf4);
433
434 udelay(200);
435
436 rt61pci_rf_write(rt2x00dev, 1, rf->rf1);
437 rt61pci_rf_write(rt2x00dev, 2, rf->rf2);
438 rt61pci_rf_write(rt2x00dev, 3, rf->rf3 & ~0x00000004);
439 rt61pci_rf_write(rt2x00dev, 4, rf->rf4);
440
441 msleep(1);
442}
443
95ea3627
ID		 444static void rt61pci_config_txpower(struct rt2x00_dev *rt2x00dev,
445 const int txpower)
446{
447 struct rf_channel rf;
448
449 rt2x00_rf_read(rt2x00dev, 1, &rf.rf1);
450 rt2x00_rf_read(rt2x00dev, 2, &rf.rf2);
451 rt2x00_rf_read(rt2x00dev, 3, &rf.rf3);
452 rt2x00_rf_read(rt2x00dev, 4, &rf.rf4);
453
5c58ee51 454 rt61pci_config_channel(rt2x00dev, &rf, txpower);
95ea3627
ID		 455}
456
457static void rt61pci_config_antenna_5x(struct rt2x00_dev *rt2x00dev,
addc81bd 458 struct antenna_setup *ant)
95ea3627
ID		 459{
460 u8 r3;
461 u8 r4;
462 u8 r77;
463
464 rt61pci_bbp_read(rt2x00dev, 3, &r3);
465 rt61pci_bbp_read(rt2x00dev, 4, &r4);
466 rt61pci_bbp_read(rt2x00dev, 77, &r77);
467
468 rt2x00_set_field8(&r3, BBP_R3_SMART_MODE,
acaa410d 469 rt2x00_rf(&rt2x00dev->chip, RF5325));
e4cd2ff8
ID		 470
471 /*
472 * Configure the RX antenna.
473 */
addc81bd 474 switch (ant->rx) {
95ea3627 475 case ANTENNA_HW_DIVERSITY:
acaa410d 476 rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA_CONTROL, 2);
95ea3627 477 rt2x00_set_field8(&r4, BBP_R4_RX_FRAME_END,
8318d78a 478 (rt2x00dev->curr_band != IEEE80211_BAND_5GHZ));
95ea3627
ID		 479 break;
480 case ANTENNA_A:
acaa410d 481 rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA_CONTROL, 1);
95ea3627 482 rt2x00_set_field8(&r4, BBP_R4_RX_FRAME_END, 0);
8318d78a 483 if (rt2x00dev->curr_band == IEEE80211_BAND_5GHZ)
acaa410d
MN		 484 rt2x00_set_field8(&r77, BBP_R77_RX_ANTENNA, 0);
485 else
486 rt2x00_set_field8(&r77, BBP_R77_RX_ANTENNA, 3);
95ea3627 487 break;
39e75857
ID		 488 case ANTENNA_SW_DIVERSITY:
489 /*
490 * NOTE: We should never come here because rt2x00lib is
491 * supposed to catch this and send us the correct antenna
492 * explicitely. However we are nog going to bug about this.
493 * Instead, just default to antenna B.
494 */
95ea3627 495 case ANTENNA_B:
acaa410d 496 rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA_CONTROL, 1);
95ea3627 497 rt2x00_set_field8(&r4, BBP_R4_RX_FRAME_END, 0);
8318d78a 498 if (rt2x00dev->curr_band == IEEE80211_BAND_5GHZ)
acaa410d
MN		 499 rt2x00_set_field8(&r77, BBP_R77_RX_ANTENNA, 3);
500 else
501 rt2x00_set_field8(&r77, BBP_R77_RX_ANTENNA, 0);
95ea3627
ID		 502 break;
503 }
504
505 rt61pci_bbp_write(rt2x00dev, 77, r77);
506 rt61pci_bbp_write(rt2x00dev, 3, r3);
507 rt61pci_bbp_write(rt2x00dev, 4, r4);
508}
509
510static void rt61pci_config_antenna_2x(struct rt2x00_dev *rt2x00dev,
addc81bd 511 struct antenna_setup *ant)
95ea3627
ID		 512{
513 u8 r3;
514 u8 r4;
515 u8 r77;
516
517 rt61pci_bbp_read(rt2x00dev, 3, &r3);
518 rt61pci_bbp_read(rt2x00dev, 4, &r4);
519 rt61pci_bbp_read(rt2x00dev, 77, &r77);
520
521 rt2x00_set_field8(&r3, BBP_R3_SMART_MODE,
acaa410d 522 rt2x00_rf(&rt2x00dev->chip, RF2529));
95ea3627
ID		 523 rt2x00_set_field8(&r4, BBP_R4_RX_FRAME_END,
524 !test_bit(CONFIG_FRAME_TYPE, &rt2x00dev->flags));
525
e4cd2ff8
ID		 526 /*
527 * Configure the RX antenna.
528 */
addc81bd 529 switch (ant->rx) {
95ea3627 530 case ANTENNA_HW_DIVERSITY:
acaa410d 531 rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA_CONTROL, 2);
95ea3627
ID		 532 break;
533 case ANTENNA_A:
acaa410d
MN		 534 rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA_CONTROL, 1);
535 rt2x00_set_field8(&r77, BBP_R77_RX_ANTENNA, 3);
95ea3627 536 break;
39e75857
ID		 537 case ANTENNA_SW_DIVERSITY:
538 /*
539 * NOTE: We should never come here because rt2x00lib is
540 * supposed to catch this and send us the correct antenna
541 * explicitely. However we are nog going to bug about this.
542 * Instead, just default to antenna B.
543 */
95ea3627 544 case ANTENNA_B:
acaa410d
MN		 545 rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA_CONTROL, 1);
546 rt2x00_set_field8(&r77, BBP_R77_RX_ANTENNA, 0);
95ea3627
ID		 547 break;
548 }
549
550 rt61pci_bbp_write(rt2x00dev, 77, r77);
551 rt61pci_bbp_write(rt2x00dev, 3, r3);
552 rt61pci_bbp_write(rt2x00dev, 4, r4);
553}
554
555static void rt61pci_config_antenna_2529_rx(struct rt2x00_dev *rt2x00dev,
556 const int p1, const int p2)
557{
558 u32 reg;
559
560 rt2x00pci_register_read(rt2x00dev, MAC_CSR13, &reg);
561
acaa410d
MN		 562 rt2x00_set_field32(&reg, MAC_CSR13_BIT4, p1);
563 rt2x00_set_field32(&reg, MAC_CSR13_BIT12, 0);
564
565 rt2x00_set_field32(&reg, MAC_CSR13_BIT3, !p2);
566 rt2x00_set_field32(&reg, MAC_CSR13_BIT11, 0);
567
568 rt2x00pci_register_write(rt2x00dev, MAC_CSR13, reg);
95ea3627
ID		 569}
570
571static void rt61pci_config_antenna_2529(struct rt2x00_dev *rt2x00dev,
addc81bd 572 struct antenna_setup *ant)
95ea3627 573{
95ea3627
ID		 574 u8 r3;
575 u8 r4;
576 u8 r77;
577
578 rt61pci_bbp_read(rt2x00dev, 3, &r3);
579 rt61pci_bbp_read(rt2x00dev, 4, &r4);
580 rt61pci_bbp_read(rt2x00dev, 77, &r77);
e4cd2ff8 581
acaa410d
MN		 582 /* FIXME: Antenna selection for the rf 2529 is very confusing in the
583 * legacy driver. The code below should be ok for non-diversity setups.
e4cd2ff8 584 */
95ea3627 585
e4cd2ff8
ID		 586 /*
587 * Configure the RX antenna.
588 */
589 switch (ant->rx) {
590 case ANTENNA_A:
acaa410d
MN		 591 rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA_CONTROL, 1);
592 rt2x00_set_field8(&r77, BBP_R77_RX_ANTENNA, 0);
593 rt61pci_config_antenna_2529_rx(rt2x00dev, 0, 0);
e4cd2ff8
ID		 594 break;
595 case ANTENNA_SW_DIVERSITY:
596 case ANTENNA_HW_DIVERSITY:
597 /*
598 * NOTE: We should never come here because rt2x00lib is
599 * supposed to catch this and send us the correct antenna
600 * explicitely. However we are nog going to bug about this.
601 * Instead, just default to antenna B.
602 */
603 case ANTENNA_B:
acaa410d
MN		 604 rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA_CONTROL, 1);
605 rt2x00_set_field8(&r77, BBP_R77_RX_ANTENNA, 3);
606 rt61pci_config_antenna_2529_rx(rt2x00dev, 1, 1);
e4cd2ff8
ID		 607 break;
608 }
609
e4cd2ff8 610 rt61pci_bbp_write(rt2x00dev, 77, r77);
95ea3627
ID		 611 rt61pci_bbp_write(rt2x00dev, 3, r3);
612 rt61pci_bbp_write(rt2x00dev, 4, r4);
613}
614
615struct antenna_sel {
616 u8 word;
617 /*
618 * value[0] -> non-LNA
619 * value[1] -> LNA
620 */
621 u8 value[2];
622};
623
624static const struct antenna_sel antenna_sel_a[] = {
625 { 96, { 0x58, 0x78 } },
626 { 104, { 0x38, 0x48 } },
627 { 75, { 0xfe, 0x80 } },
628 { 86, { 0xfe, 0x80 } },
629 { 88, { 0xfe, 0x80 } },
630 { 35, { 0x60, 0x60 } },
631 { 97, { 0x58, 0x58 } },
632 { 98, { 0x58, 0x58 } },
633};
634
635static const struct antenna_sel antenna_sel_bg[] = {
636 { 96, { 0x48, 0x68 } },
637 { 104, { 0x2c, 0x3c } },
638 { 75, { 0xfe, 0x80 } },
639 { 86, { 0xfe, 0x80 } },
640 { 88, { 0xfe, 0x80 } },
641 { 35, { 0x50, 0x50 } },
642 { 97, { 0x48, 0x48 } },
643 { 98, { 0x48, 0x48 } },
644};
645
646static void rt61pci_config_antenna(struct rt2x00_dev *rt2x00dev,
addc81bd 647 struct antenna_setup *ant)
95ea3627
ID		 648{
649 const struct antenna_sel *sel;
650 unsigned int lna;
651 unsigned int i;
652 u32 reg;
653
8318d78a 654 if (rt2x00dev->curr_band == IEEE80211_BAND_5GHZ) {
95ea3627
ID		 655 sel = antenna_sel_a;
656 lna = test_bit(CONFIG_EXTERNAL_LNA_A, &rt2x00dev->flags);
95ea3627
ID		 657 } else {
658 sel = antenna_sel_bg;
659 lna = test_bit(CONFIG_EXTERNAL_LNA_BG, &rt2x00dev->flags);
95ea3627
ID		 660 }
661
acaa410d
MN		 662 for (i = 0; i < ARRAY_SIZE(antenna_sel_a); i++)
663 rt61pci_bbp_write(rt2x00dev, sel[i].word, sel[i].value[lna]);
664
665 rt2x00pci_register_read(rt2x00dev, PHY_CSR0, &reg);
666
ddc827f9 667 rt2x00_set_field32(&reg, PHY_CSR0_PA_PE_BG,
8318d78a 668 rt2x00dev->curr_band == IEEE80211_BAND_2GHZ);
ddc827f9 669 rt2x00_set_field32(&reg, PHY_CSR0_PA_PE_A,
8318d78a 670 rt2x00dev->curr_band == IEEE80211_BAND_5GHZ);
ddc827f9 671
95ea3627
ID		 672 rt2x00pci_register_write(rt2x00dev, PHY_CSR0, reg);
673
674 if (rt2x00_rf(&rt2x00dev->chip, RF5225) ||
675 rt2x00_rf(&rt2x00dev->chip, RF5325))
addc81bd 676 rt61pci_config_antenna_5x(rt2x00dev, ant);
95ea3627 677 else if (rt2x00_rf(&rt2x00dev->chip, RF2527))
addc81bd 678 rt61pci_config_antenna_2x(rt2x00dev, ant);
95ea3627
ID		 679 else if (rt2x00_rf(&rt2x00dev->chip, RF2529)) {
680 if (test_bit(CONFIG_DOUBLE_ANTENNA, &rt2x00dev->flags))
addc81bd 681 rt61pci_config_antenna_2x(rt2x00dev, ant);
95ea3627 682 else
addc81bd 683 rt61pci_config_antenna_2529(rt2x00dev, ant);
95ea3627
ID		 684 }
685}
686
687static void rt61pci_config_duration(struct rt2x00_dev *rt2x00dev,
5c58ee51 688 struct rt2x00lib_conf *libconf)
95ea3627
ID		 689{
690 u32 reg;
691
692 rt2x00pci_register_read(rt2x00dev, MAC_CSR9, &reg);
5c58ee51 693 rt2x00_set_field32(&reg, MAC_CSR9_SLOT_TIME, libconf->slot_time);
95ea3627
ID		 694 rt2x00pci_register_write(rt2x00dev, MAC_CSR9, reg);
695
696 rt2x00pci_register_read(rt2x00dev, MAC_CSR8, &reg);
5c58ee51 697 rt2x00_set_field32(&reg, MAC_CSR8_SIFS, libconf->sifs);
95ea3627 698 rt2x00_set_field32(&reg, MAC_CSR8_SIFS_AFTER_RX_OFDM, 3);
5c58ee51 699 rt2x00_set_field32(&reg, MAC_CSR8_EIFS, libconf->eifs);
95ea3627
ID		 700 rt2x00pci_register_write(rt2x00dev, MAC_CSR8, reg);
701
702 rt2x00pci_register_read(rt2x00dev, TXRX_CSR0, &reg);
703 rt2x00_set_field32(&reg, TXRX_CSR0_TSF_OFFSET, IEEE80211_HEADER);
704 rt2x00pci_register_write(rt2x00dev, TXRX_CSR0, reg);
705
706 rt2x00pci_register_read(rt2x00dev, TXRX_CSR4, &reg);
707 rt2x00_set_field32(&reg, TXRX_CSR4_AUTORESPOND_ENABLE, 1);
708 rt2x00pci_register_write(rt2x00dev, TXRX_CSR4, reg);
709
710 rt2x00pci_register_read(rt2x00dev, TXRX_CSR9, &reg);
5c58ee51
ID		 711 rt2x00_set_field32(&reg, TXRX_CSR9_BEACON_INTERVAL,
712 libconf->conf->beacon_int * 16);
95ea3627
ID		 713 rt2x00pci_register_write(rt2x00dev, TXRX_CSR9, reg);
714}
715
716static void rt61pci_config(struct rt2x00_dev *rt2x00dev,
6bb40dd1
ID		 717 struct rt2x00lib_conf *libconf,
718 const unsigned int flags)
95ea3627 719{
95ea3627 720 if (flags & CONFIG_UPDATE_PHYMODE)
5c58ee51 721 rt61pci_config_phymode(rt2x00dev, libconf->basic_rates);
95ea3627 722 if (flags & CONFIG_UPDATE_CHANNEL)
5c58ee51
ID		 723 rt61pci_config_channel(rt2x00dev, &libconf->rf,
724 libconf->conf->power_level);
95ea3627 725 if ((flags & CONFIG_UPDATE_TXPOWER) && !(flags & CONFIG_UPDATE_CHANNEL))
5c58ee51 726 rt61pci_config_txpower(rt2x00dev, libconf->conf->power_level);
95ea3627 727 if (flags & CONFIG_UPDATE_ANTENNA)
addc81bd 728 rt61pci_config_antenna(rt2x00dev, &libconf->ant);
95ea3627 729 if (flags & (CONFIG_UPDATE_SLOT_TIME | CONFIG_UPDATE_BEACON_INT))
5c58ee51 730 rt61pci_config_duration(rt2x00dev, libconf);
95ea3627
ID		 731}
732
95ea3627
ID		 733/*
734 * Link tuning
735 */
ebcf26da
ID		 736static void rt61pci_link_stats(struct rt2x00_dev *rt2x00dev,
737 struct link_qual *qual)
95ea3627
ID		 738{
739 u32 reg;
740
741 /*
742 * Update FCS error count from register.
743 */
744 rt2x00pci_register_read(rt2x00dev, STA_CSR0, &reg);
ebcf26da 745 qual->rx_failed = rt2x00_get_field32(reg, STA_CSR0_FCS_ERROR);
95ea3627
ID		 746
747 /*
748 * Update False CCA count from register.
749 */
750 rt2x00pci_register_read(rt2x00dev, STA_CSR1, &reg);
ebcf26da 751 qual->false_cca = rt2x00_get_field32(reg, STA_CSR1_FALSE_CCA_ERROR);
95ea3627
ID		 752}
753
754static void rt61pci_reset_tuner(struct rt2x00_dev *rt2x00dev)
755{
756 rt61pci_bbp_write(rt2x00dev, 17, 0x20);
757 rt2x00dev->link.vgc_level = 0x20;
758}
759
760static void rt61pci_link_tuner(struct rt2x00_dev *rt2x00dev)
761{
762 int rssi = rt2x00_get_link_rssi(&rt2x00dev->link);
763 u8 r17;
764 u8 up_bound;
765 u8 low_bound;
766
95ea3627
ID		 767 rt61pci_bbp_read(rt2x00dev, 17, &r17);
768
769 /*
770 * Determine r17 bounds.
771 */
8318d78a 772 if (rt2x00dev->rx_status.band == IEEE80211_BAND_2GHZ) {
95ea3627
ID		 773 low_bound = 0x28;
774 up_bound = 0x48;
775 if (test_bit(CONFIG_EXTERNAL_LNA_A, &rt2x00dev->flags)) {
776 low_bound += 0x10;
777 up_bound += 0x10;
778 }
779 } else {
780 low_bound = 0x20;
781 up_bound = 0x40;
782 if (test_bit(CONFIG_EXTERNAL_LNA_BG, &rt2x00dev->flags)) {
783 low_bound += 0x10;
784 up_bound += 0x10;
785 }
786 }
787
6bb40dd1
ID		 788 /*
789 * If we are not associated, we should go straight to the
790 * dynamic CCA tuning.
791 */
792 if (!rt2x00dev->intf_associated)
793 goto dynamic_cca_tune;
794
95ea3627
ID		 795 /*
796 * Special big-R17 for very short distance
797 */
798 if (rssi >= -35) {
799 if (r17 != 0x60)
800 rt61pci_bbp_write(rt2x00dev, 17, 0x60);
801 return;
802 }
803
804 /*
805 * Special big-R17 for short distance
806 */
807 if (rssi >= -58) {
808 if (r17 != up_bound)
809 rt61pci_bbp_write(rt2x00dev, 17, up_bound);
810 return;
811 }
812
813 /*
814 * Special big-R17 for middle-short distance
815 */
816 if (rssi >= -66) {
817 low_bound += 0x10;
818 if (r17 != low_bound)
819 rt61pci_bbp_write(rt2x00dev, 17, low_bound);
820 return;
821 }
822
823 /*
824 * Special mid-R17 for middle distance
825 */
826 if (rssi >= -74) {
827 low_bound += 0x08;
828 if (r17 != low_bound)
829 rt61pci_bbp_write(rt2x00dev, 17, low_bound);
830 return;
831 }
832
833 /*
834 * Special case: Change up_bound based on the rssi.
835 * Lower up_bound when rssi is weaker then -74 dBm.
836 */
837 up_bound -= 2 * (-74 - rssi);
838 if (low_bound > up_bound)
839 up_bound = low_bound;
840
841 if (r17 > up_bound) {
842 rt61pci_bbp_write(rt2x00dev, 17, up_bound);
843 return;
844 }
845
6bb40dd1
ID		 846dynamic_cca_tune:
847
95ea3627
ID		 848 /*
849 * r17 does not yet exceed upper limit, continue and base
850 * the r17 tuning on the false CCA count.
851 */
ebcf26da 852 if (rt2x00dev->link.qual.false_cca > 512 && r17 < up_bound) {
95ea3627
ID		 853 if (++r17 > up_bound)
854 r17 = up_bound;
855 rt61pci_bbp_write(rt2x00dev, 17, r17);
ebcf26da 856 } else if (rt2x00dev->link.qual.false_cca < 100 && r17 > low_bound) {
95ea3627
ID		 857 if (--r17 < low_bound)
858 r17 = low_bound;
859 rt61pci_bbp_write(rt2x00dev, 17, r17);
860 }
861}
862
863/*
864 * Firmware name function.
865 */
866static char *rt61pci_get_firmware_name(struct rt2x00_dev *rt2x00dev)
867{
868 char *fw_name;
869
870 switch (rt2x00dev->chip.rt) {
871 case RT2561:
872 fw_name = FIRMWARE_RT2561;
873 break;
874 case RT2561s:
875 fw_name = FIRMWARE_RT2561s;
876 break;
877 case RT2661:
878 fw_name = FIRMWARE_RT2661;
879 break;
880 default:
881 fw_name = NULL;
882 break;
883 }
884
885 return fw_name;
886}
887
888/*
889 * Initialization functions.
890 */
891static int rt61pci_load_firmware(struct rt2x00_dev *rt2x00dev, void *data,
892 const size_t len)
893{
894 int i;
895 u32 reg;
896
897 /*
898 * Wait for stable hardware.
899 */
900 for (i = 0; i < 100; i++) {
901 rt2x00pci_register_read(rt2x00dev, MAC_CSR0, &reg);
902 if (reg)
903 break;
904 msleep(1);
905 }
906
907 if (!reg) {
908 ERROR(rt2x00dev, "Unstable hardware.\n");
909 return -EBUSY;
910 }
911
912 /*
913 * Prepare MCU and mailbox for firmware loading.
914 */
915 reg = 0;
916 rt2x00_set_field32(&reg, MCU_CNTL_CSR_RESET, 1);
917 rt2x00pci_register_write(rt2x00dev, MCU_CNTL_CSR, reg);
918 rt2x00pci_register_write(rt2x00dev, M2H_CMD_DONE_CSR, 0xffffffff);
919 rt2x00pci_register_write(rt2x00dev, H2M_MAILBOX_CSR, 0);
920 rt2x00pci_register_write(rt2x00dev, HOST_CMD_CSR, 0);
921
922 /*
923 * Write firmware to device.
924 */
925 reg = 0;
926 rt2x00_set_field32(&reg, MCU_CNTL_CSR_RESET, 1);
927 rt2x00_set_field32(&reg, MCU_CNTL_CSR_SELECT_BANK, 1);
928 rt2x00pci_register_write(rt2x00dev, MCU_CNTL_CSR, reg);
929
930 rt2x00pci_register_multiwrite(rt2x00dev, FIRMWARE_IMAGE_BASE,
931 data, len);
932
933 rt2x00_set_field32(&reg, MCU_CNTL_CSR_SELECT_BANK, 0);
934 rt2x00pci_register_write(rt2x00dev, MCU_CNTL_CSR, reg);
935
936 rt2x00_set_field32(&reg, MCU_CNTL_CSR_RESET, 0);
937 rt2x00pci_register_write(rt2x00dev, MCU_CNTL_CSR, reg);
938
939 for (i = 0; i < 100; i++) {
940 rt2x00pci_register_read(rt2x00dev, MCU_CNTL_CSR, &reg);
941 if (rt2x00_get_field32(reg, MCU_CNTL_CSR_READY))
942 break;
943 msleep(1);
944 }
945
946 if (i == 100) {
947 ERROR(rt2x00dev, "MCU Control register not ready.\n");
948 return -EBUSY;
949 }
950
951 /*
952 * Reset MAC and BBP registers.
953 */
954 reg = 0;
955 rt2x00_set_field32(&reg, MAC_CSR1_SOFT_RESET, 1);
956 rt2x00_set_field32(&reg, MAC_CSR1_BBP_RESET, 1);
957 rt2x00pci_register_write(rt2x00dev, MAC_CSR1, reg);
958
959 rt2x00pci_register_read(rt2x00dev, MAC_CSR1, &reg);
960 rt2x00_set_field32(&reg, MAC_CSR1_SOFT_RESET, 0);
961 rt2x00_set_field32(&reg, MAC_CSR1_BBP_RESET, 0);
962 rt2x00pci_register_write(rt2x00dev, MAC_CSR1, reg);
963
964 rt2x00pci_register_read(rt2x00dev, MAC_CSR1, &reg);
965 rt2x00_set_field32(&reg, MAC_CSR1_HOST_READY, 1);
966 rt2x00pci_register_write(rt2x00dev, MAC_CSR1, reg);
967
968 return 0;
969}
970
837e7f24 971static void rt61pci_init_rxentry(struct rt2x00_dev *rt2x00dev,
181d6902 972 struct queue_entry *entry)
95ea3627 973{
181d6902 974 struct queue_entry_priv_pci_rx *priv_rx = entry->priv_data;
95ea3627
ID		 975 u32 word;
976
181d6902
ID		 977 rt2x00_desc_read(priv_rx->desc, 5, &word);
978 rt2x00_set_field32(&word, RXD_W5_BUFFER_PHYSICAL_ADDRESS, priv_rx->dma);
979 rt2x00_desc_write(priv_rx->desc, 5, word);
95ea3627 980
181d6902 981 rt2x00_desc_read(priv_rx->desc, 0, &word);
837e7f24 982 rt2x00_set_field32(&word, RXD_W0_OWNER_NIC, 1);
181d6902 983 rt2x00_desc_write(priv_rx->desc, 0, word);
95ea3627
ID		 984}
985
837e7f24 986static void rt61pci_init_txentry(struct rt2x00_dev *rt2x00dev,
181d6902 987 struct queue_entry *entry)
95ea3627 988{
181d6902 989 struct queue_entry_priv_pci_tx *priv_tx = entry->priv_data;
95ea3627
ID		 990 u32 word;
991
181d6902 992 rt2x00_desc_read(priv_tx->desc, 1, &word);
837e7f24 993 rt2x00_set_field32(&word, TXD_W1_BUFFER_COUNT, 1);
181d6902 994 rt2x00_desc_write(priv_tx->desc, 1, word);
95ea3627 995
181d6902
ID		 996 rt2x00_desc_read(priv_tx->desc, 5, &word);
997 rt2x00_set_field32(&word, TXD_W5_PID_TYPE, entry->queue->qid);
837e7f24 998 rt2x00_set_field32(&word, TXD_W5_PID_SUBTYPE, entry->entry_idx);
181d6902 999 rt2x00_desc_write(priv_tx->desc, 5, word);
95ea3627 1000
181d6902
ID		 1001 rt2x00_desc_read(priv_tx->desc, 6, &word);
1002 rt2x00_set_field32(&word, TXD_W6_BUFFER_PHYSICAL_ADDRESS, priv_tx->dma);
1003 rt2x00_desc_write(priv_tx->desc, 6, word);
95ea3627 1004
181d6902 1005 rt2x00_desc_read(priv_tx->desc, 0, &word);
837e7f24
ID		 1006 rt2x00_set_field32(&word, TXD_W0_VALID, 0);
1007 rt2x00_set_field32(&word, TXD_W0_OWNER_NIC, 0);
181d6902 1008 rt2x00_desc_write(priv_tx->desc, 0, word);
95ea3627
ID		 1009}
1010
181d6902 1011static int rt61pci_init_queues(struct rt2x00_dev *rt2x00dev)
95ea3627 1012{
181d6902
ID		 1013 struct queue_entry_priv_pci_rx *priv_rx;
1014 struct queue_entry_priv_pci_tx *priv_tx;
95ea3627
ID		 1015 u32 reg;
1016
95ea3627
ID		 1017 /*
1018 * Initialize registers.
1019 */
1020 rt2x00pci_register_read(rt2x00dev, TX_RING_CSR0, &reg);
1021 rt2x00_set_field32(&reg, TX_RING_CSR0_AC0_RING_SIZE,
181d6902 1022 rt2x00dev->tx[0].limit);
95ea3627 1023 rt2x00_set_field32(&reg, TX_RING_CSR0_AC1_RING_SIZE,
181d6902 1024 rt2x00dev->tx[1].limit);
95ea3627 1025 rt2x00_set_field32(&reg, TX_RING_CSR0_AC2_RING_SIZE,
181d6902 1026 rt2x00dev->tx[2].limit);
95ea3627 1027 rt2x00_set_field32(&reg, TX_RING_CSR0_AC3_RING_SIZE,
181d6902 1028 rt2x00dev->tx[3].limit);
95ea3627
ID		 1029 rt2x00pci_register_write(rt2x00dev, TX_RING_CSR0, reg);
1030
1031 rt2x00pci_register_read(rt2x00dev, TX_RING_CSR1, &reg);
95ea3627 1032 rt2x00_set_field32(&reg, TX_RING_CSR1_TXD_SIZE,
181d6902 1033 rt2x00dev->tx[0].desc_size / 4);
95ea3627
ID		 1034 rt2x00pci_register_write(rt2x00dev, TX_RING_CSR1, reg);
1035
181d6902 1036 priv_tx = rt2x00dev->tx[0].entries[0].priv_data;
95ea3627 1037 rt2x00pci_register_read(rt2x00dev, AC0_BASE_CSR, &reg);
181d6902 1038 rt2x00_set_field32(&reg, AC0_BASE_CSR_RING_REGISTER, priv_tx->dma);
95ea3627
ID		 1039 rt2x00pci_register_write(rt2x00dev, AC0_BASE_CSR, reg);
1040
181d6902 1041 priv_tx = rt2x00dev->tx[1].entries[0].priv_data;
95ea3627 1042 rt2x00pci_register_read(rt2x00dev, AC1_BASE_CSR, &reg);
181d6902 1043 rt2x00_set_field32(&reg, AC1_BASE_CSR_RING_REGISTER, priv_tx->dma);
95ea3627
ID		 1044 rt2x00pci_register_write(rt2x00dev, AC1_BASE_CSR, reg);
1045
181d6902 1046 priv_tx = rt2x00dev->tx[2].entries[0].priv_data;
95ea3627 1047 rt2x00pci_register_read(rt2x00dev, AC2_BASE_CSR, &reg);
181d6902 1048 rt2x00_set_field32(&reg, AC2_BASE_CSR_RING_REGISTER, priv_tx->dma);
95ea3627
ID		 1049 rt2x00pci_register_write(rt2x00dev, AC2_BASE_CSR, reg);
1050
181d6902 1051 priv_tx = rt2x00dev->tx[3].entries[0].priv_data;
95ea3627 1052 rt2x00pci_register_read(rt2x00dev, AC3_BASE_CSR, &reg);
181d6902 1053 rt2x00_set_field32(&reg, AC3_BASE_CSR_RING_REGISTER, priv_tx->dma);
95ea3627
ID		 1054 rt2x00pci_register_write(rt2x00dev, AC3_BASE_CSR, reg);
1055
95ea3627 1056 rt2x00pci_register_read(rt2x00dev, RX_RING_CSR, &reg);
181d6902 1057 rt2x00_set_field32(&reg, RX_RING_CSR_RING_SIZE, rt2x00dev->rx->limit);
95ea3627
ID		 1058 rt2x00_set_field32(&reg, RX_RING_CSR_RXD_SIZE,
1059 rt2x00dev->rx->desc_size / 4);
1060 rt2x00_set_field32(&reg, RX_RING_CSR_RXD_WRITEBACK_SIZE, 4);
1061 rt2x00pci_register_write(rt2x00dev, RX_RING_CSR, reg);
1062
181d6902 1063 priv_rx = rt2x00dev->rx->entries[0].priv_data;
95ea3627 1064 rt2x00pci_register_read(rt2x00dev, RX_BASE_CSR, &reg);
181d6902 1065 rt2x00_set_field32(&reg, RX_BASE_CSR_RING_REGISTER, priv_rx->dma);
95ea3627
ID		 1066 rt2x00pci_register_write(rt2x00dev, RX_BASE_CSR, reg);
1067
1068 rt2x00pci_register_read(rt2x00dev, TX_DMA_DST_CSR, &reg);
1069 rt2x00_set_field32(&reg, TX_DMA_DST_CSR_DEST_AC0, 2);
1070 rt2x00_set_field32(&reg, TX_DMA_DST_CSR_DEST_AC1, 2);
1071 rt2x00_set_field32(&reg, TX_DMA_DST_CSR_DEST_AC2, 2);
1072 rt2x00_set_field32(&reg, TX_DMA_DST_CSR_DEST_AC3, 2);
95ea3627
ID		 1073 rt2x00pci_register_write(rt2x00dev, TX_DMA_DST_CSR, reg);
1074
1075 rt2x00pci_register_read(rt2x00dev, LOAD_TX_RING_CSR, &reg);
1076 rt2x00_set_field32(&reg, LOAD_TX_RING_CSR_LOAD_TXD_AC0, 1);
1077 rt2x00_set_field32(&reg, LOAD_TX_RING_CSR_LOAD_TXD_AC1, 1);
1078 rt2x00_set_field32(&reg, LOAD_TX_RING_CSR_LOAD_TXD_AC2, 1);
1079 rt2x00_set_field32(&reg, LOAD_TX_RING_CSR_LOAD_TXD_AC3, 1);
95ea3627
ID		 1080 rt2x00pci_register_write(rt2x00dev, LOAD_TX_RING_CSR, reg);
1081
1082 rt2x00pci_register_read(rt2x00dev, RX_CNTL_CSR, &reg);
1083 rt2x00_set_field32(&reg, RX_CNTL_CSR_LOAD_RXD, 1);
1084 rt2x00pci_register_write(rt2x00dev, RX_CNTL_CSR, reg);
1085
1086 return 0;
1087}
1088
1089static int rt61pci_init_registers(struct rt2x00_dev *rt2x00dev)
1090{
1091 u32 reg;
1092
1093 rt2x00pci_register_read(rt2x00dev, TXRX_CSR0, &reg);
1094 rt2x00_set_field32(&reg, TXRX_CSR0_AUTO_TX_SEQ, 1);
1095 rt2x00_set_field32(&reg, TXRX_CSR0_DISABLE_RX, 0);
1096 rt2x00_set_field32(&reg, TXRX_CSR0_TX_WITHOUT_WAITING, 0);
1097 rt2x00pci_register_write(rt2x00dev, TXRX_CSR0, reg);
1098
1099 rt2x00pci_register_read(rt2x00dev, TXRX_CSR1, &reg);
1100 rt2x00_set_field32(&reg, TXRX_CSR1_BBP_ID0, 47); /* CCK Signal */
1101 rt2x00_set_field32(&reg, TXRX_CSR1_BBP_ID0_VALID, 1);
1102 rt2x00_set_field32(&reg, TXRX_CSR1_BBP_ID1, 30); /* Rssi */
1103 rt2x00_set_field32(&reg, TXRX_CSR1_BBP_ID1_VALID, 1);
1104 rt2x00_set_field32(&reg, TXRX_CSR1_BBP_ID2, 42); /* OFDM Rate */
1105 rt2x00_set_field32(&reg, TXRX_CSR1_BBP_ID2_VALID, 1);
1106 rt2x00_set_field32(&reg, TXRX_CSR1_BBP_ID3, 30); /* Rssi */
1107 rt2x00_set_field32(&reg, TXRX_CSR1_BBP_ID3_VALID, 1);
1108 rt2x00pci_register_write(rt2x00dev, TXRX_CSR1, reg);
1109
1110 /*
1111 * CCK TXD BBP registers
1112 */
1113 rt2x00pci_register_read(rt2x00dev, TXRX_CSR2, &reg);
1114 rt2x00_set_field32(&reg, TXRX_CSR2_BBP_ID0, 13);
1115 rt2x00_set_field32(&reg, TXRX_CSR2_BBP_ID0_VALID, 1);
1116 rt2x00_set_field32(&reg, TXRX_CSR2_BBP_ID1, 12);
1117 rt2x00_set_field32(&reg, TXRX_CSR2_BBP_ID1_VALID, 1);
1118 rt2x00_set_field32(&reg, TXRX_CSR2_BBP_ID2, 11);
1119 rt2x00_set_field32(&reg, TXRX_CSR2_BBP_ID2_VALID, 1);
1120 rt2x00_set_field32(&reg, TXRX_CSR2_BBP_ID3, 10);
1121 rt2x00_set_field32(&reg, TXRX_CSR2_BBP_ID3_VALID, 1);
1122 rt2x00pci_register_write(rt2x00dev, TXRX_CSR2, reg);
1123
1124 /*
1125 * OFDM TXD BBP registers
1126 */
1127 rt2x00pci_register_read(rt2x00dev, TXRX_CSR3, &reg);
1128 rt2x00_set_field32(&reg, TXRX_CSR3_BBP_ID0, 7);
1129 rt2x00_set_field32(&reg, TXRX_CSR3_BBP_ID0_VALID, 1);
1130 rt2x00_set_field32(&reg, TXRX_CSR3_BBP_ID1, 6);
1131 rt2x00_set_field32(&reg, TXRX_CSR3_BBP_ID1_VALID, 1);
1132 rt2x00_set_field32(&reg, TXRX_CSR3_BBP_ID2, 5);
1133 rt2x00_set_field32(&reg, TXRX_CSR3_BBP_ID2_VALID, 1);
1134 rt2x00pci_register_write(rt2x00dev, TXRX_CSR3, reg);
1135
1136 rt2x00pci_register_read(rt2x00dev, TXRX_CSR7, &reg);
1137 rt2x00_set_field32(&reg, TXRX_CSR7_ACK_CTS_6MBS, 59);
1138 rt2x00_set_field32(&reg, TXRX_CSR7_ACK_CTS_9MBS, 53);
1139 rt2x00_set_field32(&reg, TXRX_CSR7_ACK_CTS_12MBS, 49);
1140 rt2x00_set_field32(&reg, TXRX_CSR7_ACK_CTS_18MBS, 46);
1141 rt2x00pci_register_write(rt2x00dev, TXRX_CSR7, reg);
1142
1143 rt2x00pci_register_read(rt2x00dev, TXRX_CSR8, &reg);
1144 rt2x00_set_field32(&reg, TXRX_CSR8_ACK_CTS_24MBS, 44);
1145 rt2x00_set_field32(&reg, TXRX_CSR8_ACK_CTS_36MBS, 42);
1146 rt2x00_set_field32(&reg, TXRX_CSR8_ACK_CTS_48MBS, 42);
1147 rt2x00_set_field32(&reg, TXRX_CSR8_ACK_CTS_54MBS, 42);
1148 rt2x00pci_register_write(rt2x00dev, TXRX_CSR8, reg);
1149
1150 rt2x00pci_register_write(rt2x00dev, TXRX_CSR15, 0x0000000f);
1151
1152 rt2x00pci_register_write(rt2x00dev, MAC_CSR6, 0x00000fff);
1153
1154 rt2x00pci_register_read(rt2x00dev, MAC_CSR9, &reg);
1155 rt2x00_set_field32(&reg, MAC_CSR9_CW_SELECT, 0);
1156 rt2x00pci_register_write(rt2x00dev, MAC_CSR9, reg);
1157
1158 rt2x00pci_register_write(rt2x00dev, MAC_CSR10, 0x0000071c);
1159
1160 if (rt2x00dev->ops->lib->set_device_state(rt2x00dev, STATE_AWAKE))
1161 return -EBUSY;
1162
1163 rt2x00pci_register_write(rt2x00dev, MAC_CSR13, 0x0000e000);
1164
a9450b70
ID		 1165 rt2x00pci_register_read(rt2x00dev, MAC_CSR14, &reg);
1166 rt2x00_set_field32(&reg, MAC_CSR14_ON_PERIOD, 70);
1167 rt2x00_set_field32(&reg, MAC_CSR14_OFF_PERIOD, 30);
1168 rt2x00pci_register_write(rt2x00dev, MAC_CSR14, reg);
1169
95ea3627
ID		 1170 /*
1171 * Invalidate all Shared Keys (SEC_CSR0),
1172 * and clear the Shared key Cipher algorithms (SEC_CSR1 & SEC_CSR5)
1173 */
1174 rt2x00pci_register_write(rt2x00dev, SEC_CSR0, 0x00000000);
1175 rt2x00pci_register_write(rt2x00dev, SEC_CSR1, 0x00000000);
1176 rt2x00pci_register_write(rt2x00dev, SEC_CSR5, 0x00000000);
1177
1178 rt2x00pci_register_write(rt2x00dev, PHY_CSR1, 0x000023b0);
1179 rt2x00pci_register_write(rt2x00dev, PHY_CSR5, 0x060a100c);
1180 rt2x00pci_register_write(rt2x00dev, PHY_CSR6, 0x00080606);
1181 rt2x00pci_register_write(rt2x00dev, PHY_CSR7, 0x00000a08);
1182
1183 rt2x00pci_register_write(rt2x00dev, PCI_CFG_CSR, 0x28ca4404);
1184
1185 rt2x00pci_register_write(rt2x00dev, TEST_MODE_CSR, 0x00000200);
1186
1187 rt2x00pci_register_write(rt2x00dev, M2H_CMD_DONE_CSR, 0xffffffff);
1188
1189 rt2x00pci_register_read(rt2x00dev, AC_TXOP_CSR0, &reg);
1190 rt2x00_set_field32(&reg, AC_TXOP_CSR0_AC0_TX_OP, 0);
1191 rt2x00_set_field32(&reg, AC_TXOP_CSR0_AC1_TX_OP, 0);
1192 rt2x00pci_register_write(rt2x00dev, AC_TXOP_CSR0, reg);
1193
1194 rt2x00pci_register_read(rt2x00dev, AC_TXOP_CSR1, &reg);
1195 rt2x00_set_field32(&reg, AC_TXOP_CSR1_AC2_TX_OP, 192);
1196 rt2x00_set_field32(&reg, AC_TXOP_CSR1_AC3_TX_OP, 48);
1197 rt2x00pci_register_write(rt2x00dev, AC_TXOP_CSR1, reg);
1198
6bb40dd1
ID		 1199 /*
1200 * Clear all beacons
1201 * For the Beacon base registers we only need to clear
1202 * the first byte since that byte contains the VALID and OWNER
1203 * bits which (when set to 0) will invalidate the entire beacon.
1204 */
1205 rt2x00pci_register_write(rt2x00dev, HW_BEACON_BASE0, 0);
1206 rt2x00pci_register_write(rt2x00dev, HW_BEACON_BASE1, 0);
1207 rt2x00pci_register_write(rt2x00dev, HW_BEACON_BASE2, 0);
1208 rt2x00pci_register_write(rt2x00dev, HW_BEACON_BASE3, 0);
1209
95ea3627
ID		 1210 /*
1211 * We must clear the error counters.
1212 * These registers are cleared on read,
1213 * so we may pass a useless variable to store the value.
1214 */
1215 rt2x00pci_register_read(rt2x00dev, STA_CSR0, &reg);
1216 rt2x00pci_register_read(rt2x00dev, STA_CSR1, &reg);
1217 rt2x00pci_register_read(rt2x00dev, STA_CSR2, &reg);
1218
1219 /*
1220 * Reset MAC and BBP registers.
1221 */
1222 rt2x00pci_register_read(rt2x00dev, MAC_CSR1, &reg);
1223 rt2x00_set_field32(&reg, MAC_CSR1_SOFT_RESET, 1);
1224 rt2x00_set_field32(&reg, MAC_CSR1_BBP_RESET, 1);
1225 rt2x00pci_register_write(rt2x00dev, MAC_CSR1, reg);
1226
1227 rt2x00pci_register_read(rt2x00dev, MAC_CSR1, &reg);
1228 rt2x00_set_field32(&reg, MAC_CSR1_SOFT_RESET, 0);
1229 rt2x00_set_field32(&reg, MAC_CSR1_BBP_RESET, 0);
1230 rt2x00pci_register_write(rt2x00dev, MAC_CSR1, reg);
1231
1232 rt2x00pci_register_read(rt2x00dev, MAC_CSR1, &reg);
1233 rt2x00_set_field32(&reg, MAC_CSR1_HOST_READY, 1);
1234 rt2x00pci_register_write(rt2x00dev, MAC_CSR1, reg);
1235
1236 return 0;
1237}
1238
1239static int rt61pci_init_bbp(struct rt2x00_dev *rt2x00dev)
1240{
1241 unsigned int i;
1242 u16 eeprom;
1243 u8 reg_id;
1244 u8 value;
1245
1246 for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
1247 rt61pci_bbp_read(rt2x00dev, 0, &value);
1248 if ((value != 0xff) && (value != 0x00))
1249 goto continue_csr_init;
1250 NOTICE(rt2x00dev, "Waiting for BBP register.\n");
1251 udelay(REGISTER_BUSY_DELAY);
1252 }
1253
1254 ERROR(rt2x00dev, "BBP register access failed, aborting.\n");
1255 return -EACCES;
1256
1257continue_csr_init:
1258 rt61pci_bbp_write(rt2x00dev, 3, 0x00);
1259 rt61pci_bbp_write(rt2x00dev, 15, 0x30);
1260 rt61pci_bbp_write(rt2x00dev, 21, 0xc8);
1261 rt61pci_bbp_write(rt2x00dev, 22, 0x38);
1262 rt61pci_bbp_write(rt2x00dev, 23, 0x06);
1263 rt61pci_bbp_write(rt2x00dev, 24, 0xfe);
1264 rt61pci_bbp_write(rt2x00dev, 25, 0x0a);
1265 rt61pci_bbp_write(rt2x00dev, 26, 0x0d);
1266 rt61pci_bbp_write(rt2x00dev, 34, 0x12);
1267 rt61pci_bbp_write(rt2x00dev, 37, 0x07);
1268 rt61pci_bbp_write(rt2x00dev, 39, 0xf8);
1269 rt61pci_bbp_write(rt2x00dev, 41, 0x60);
1270 rt61pci_bbp_write(rt2x00dev, 53, 0x10);
1271 rt61pci_bbp_write(rt2x00dev, 54, 0x18);
1272 rt61pci_bbp_write(rt2x00dev, 60, 0x10);
1273 rt61pci_bbp_write(rt2x00dev, 61, 0x04);
1274 rt61pci_bbp_write(rt2x00dev, 62, 0x04);
1275 rt61pci_bbp_write(rt2x00dev, 75, 0xfe);
1276 rt61pci_bbp_write(rt2x00dev, 86, 0xfe);
1277 rt61pci_bbp_write(rt2x00dev, 88, 0xfe);
1278 rt61pci_bbp_write(rt2x00dev, 90, 0x0f);
1279 rt61pci_bbp_write(rt2x00dev, 99, 0x00);
1280 rt61pci_bbp_write(rt2x00dev, 102, 0x16);
1281 rt61pci_bbp_write(rt2x00dev, 107, 0x04);
1282
95ea3627
ID		 1283 for (i = 0; i < EEPROM_BBP_SIZE; i++) {
1284 rt2x00_eeprom_read(rt2x00dev, EEPROM_BBP_START + i, &eeprom);
1285
1286 if (eeprom != 0xffff && eeprom != 0x0000) {
1287 reg_id = rt2x00_get_field16(eeprom, EEPROM_BBP_REG_ID);
1288 value = rt2x00_get_field16(eeprom, EEPROM_BBP_VALUE);
95ea3627
ID		 1289 rt61pci_bbp_write(rt2x00dev, reg_id, value);
1290 }
1291 }
95ea3627
ID		 1292
1293 return 0;
1294}
1295
1296/*
1297 * Device state switch handlers.
1298 */
1299static void rt61pci_toggle_rx(struct rt2x00_dev *rt2x00dev,
1300 enum dev_state state)
1301{
1302 u32 reg;
1303
1304 rt2x00pci_register_read(rt2x00dev, TXRX_CSR0, &reg);
1305 rt2x00_set_field32(&reg, TXRX_CSR0_DISABLE_RX,
1306 state == STATE_RADIO_RX_OFF);
1307 rt2x00pci_register_write(rt2x00dev, TXRX_CSR0, reg);
1308}
1309
1310static void rt61pci_toggle_irq(struct rt2x00_dev *rt2x00dev,
1311 enum dev_state state)
1312{
1313 int mask = (state == STATE_RADIO_IRQ_OFF);
1314 u32 reg;
1315
1316 /*
1317 * When interrupts are being enabled, the interrupt registers
1318 * should clear the register to assure a clean state.
1319 */
1320 if (state == STATE_RADIO_IRQ_ON) {
1321 rt2x00pci_register_read(rt2x00dev, INT_SOURCE_CSR, &reg);
1322 rt2x00pci_register_write(rt2x00dev, INT_SOURCE_CSR, reg);
1323
1324 rt2x00pci_register_read(rt2x00dev, MCU_INT_SOURCE_CSR, &reg);
1325 rt2x00pci_register_write(rt2x00dev, MCU_INT_SOURCE_CSR, reg);
1326 }
1327
1328 /*
1329 * Only toggle the interrupts bits we are going to use.
1330 * Non-checked interrupt bits are disabled by default.
1331 */
1332 rt2x00pci_register_read(rt2x00dev, INT_MASK_CSR, &reg);
1333 rt2x00_set_field32(&reg, INT_MASK_CSR_TXDONE, mask);
1334 rt2x00_set_field32(&reg, INT_MASK_CSR_RXDONE, mask);
1335 rt2x00_set_field32(&reg, INT_MASK_CSR_ENABLE_MITIGATION, mask);
1336 rt2x00_set_field32(&reg, INT_MASK_CSR_MITIGATION_PERIOD, 0xff);
1337 rt2x00pci_register_write(rt2x00dev, INT_MASK_CSR, reg);
1338
1339 rt2x00pci_register_read(rt2x00dev, MCU_INT_MASK_CSR, &reg);
1340 rt2x00_set_field32(&reg, MCU_INT_MASK_CSR_0, mask);
1341 rt2x00_set_field32(&reg, MCU_INT_MASK_CSR_1, mask);
1342 rt2x00_set_field32(&reg, MCU_INT_MASK_CSR_2, mask);
1343 rt2x00_set_field32(&reg, MCU_INT_MASK_CSR_3, mask);
1344 rt2x00_set_field32(&reg, MCU_INT_MASK_CSR_4, mask);
1345 rt2x00_set_field32(&reg, MCU_INT_MASK_CSR_5, mask);
1346 rt2x00_set_field32(&reg, MCU_INT_MASK_CSR_6, mask);
1347 rt2x00_set_field32(&reg, MCU_INT_MASK_CSR_7, mask);
1348 rt2x00pci_register_write(rt2x00dev, MCU_INT_MASK_CSR, reg);
1349}
1350
1351static int rt61pci_enable_radio(struct rt2x00_dev *rt2x00dev)
1352{
1353 u32 reg;
1354
1355 /*
1356 * Initialize all registers.
1357 */
181d6902 1358 if (rt61pci_init_queues(rt2x00dev) ||
95ea3627
ID		 1359 rt61pci_init_registers(rt2x00dev) ||
1360 rt61pci_init_bbp(rt2x00dev)) {
1361 ERROR(rt2x00dev, "Register initialization failed.\n");
1362 return -EIO;
1363 }
1364
1365 /*
1366 * Enable interrupts.
1367 */
1368 rt61pci_toggle_irq(rt2x00dev, STATE_RADIO_IRQ_ON);
1369
1370 /*
1371 * Enable RX.
1372 */
1373 rt2x00pci_register_read(rt2x00dev, RX_CNTL_CSR, &reg);
1374 rt2x00_set_field32(&reg, RX_CNTL_CSR_ENABLE_RX_DMA, 1);
1375 rt2x00pci_register_write(rt2x00dev, RX_CNTL_CSR, reg);
1376
95ea3627
ID		 1377 return 0;
1378}
1379
1380static void rt61pci_disable_radio(struct rt2x00_dev *rt2x00dev)
1381{
1382 u32 reg;
1383
95ea3627
ID		 1384 rt2x00pci_register_write(rt2x00dev, MAC_CSR10, 0x00001818);
1385
1386 /*
1387 * Disable synchronisation.
1388 */
1389 rt2x00pci_register_write(rt2x00dev, TXRX_CSR9, 0);
1390
1391 /*
1392 * Cancel RX and TX.
1393 */
1394 rt2x00pci_register_read(rt2x00dev, TX_CNTL_CSR, &reg);
1395 rt2x00_set_field32(&reg, TX_CNTL_CSR_ABORT_TX_AC0, 1);
1396 rt2x00_set_field32(&reg, TX_CNTL_CSR_ABORT_TX_AC1, 1);
1397 rt2x00_set_field32(&reg, TX_CNTL_CSR_ABORT_TX_AC2, 1);
1398 rt2x00_set_field32(&reg, TX_CNTL_CSR_ABORT_TX_AC3, 1);
95ea3627
ID		 1399 rt2x00pci_register_write(rt2x00dev, TX_CNTL_CSR, reg);
1400
1401 /*
1402 * Disable interrupts.
1403 */
1404 rt61pci_toggle_irq(rt2x00dev, STATE_RADIO_IRQ_OFF);
1405}
1406
1407static int rt61pci_set_state(struct rt2x00_dev *rt2x00dev, enum dev_state state)
1408{
1409 u32 reg;
1410 unsigned int i;
1411 char put_to_sleep;
1412 char current_state;
1413
1414 put_to_sleep = (state != STATE_AWAKE);
1415
1416 rt2x00pci_register_read(rt2x00dev, MAC_CSR12, &reg);
1417 rt2x00_set_field32(&reg, MAC_CSR12_FORCE_WAKEUP, !put_to_sleep);
1418 rt2x00_set_field32(&reg, MAC_CSR12_PUT_TO_SLEEP, put_to_sleep);
1419 rt2x00pci_register_write(rt2x00dev, MAC_CSR12, reg);
1420
1421 /*
1422 * Device is not guaranteed to be in the requested state yet.
1423 * We must wait until the register indicates that the
1424 * device has entered the correct state.
1425 */
1426 for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
1427 rt2x00pci_register_read(rt2x00dev, MAC_CSR12, &reg);
1428 current_state =
1429 rt2x00_get_field32(reg, MAC_CSR12_BBP_CURRENT_STATE);
1430 if (current_state == !put_to_sleep)
1431 return 0;
1432 msleep(10);
1433 }
1434
1435 NOTICE(rt2x00dev, "Device failed to enter state %d, "
1436 "current device state %d.\n", !put_to_sleep, current_state);
1437
1438 return -EBUSY;
1439}
1440
1441static int rt61pci_set_device_state(struct rt2x00_dev *rt2x00dev,
1442 enum dev_state state)
1443{
1444 int retval = 0;
1445
1446 switch (state) {
1447 case STATE_RADIO_ON:
1448 retval = rt61pci_enable_radio(rt2x00dev);
1449 break;
1450 case STATE_RADIO_OFF:
1451 rt61pci_disable_radio(rt2x00dev);
1452 break;
1453 case STATE_RADIO_RX_ON:
61667d8d
ID		 1454 case STATE_RADIO_RX_ON_LINK:
1455 rt61pci_toggle_rx(rt2x00dev, STATE_RADIO_RX_ON);
1456 break;
95ea3627 1457 case STATE_RADIO_RX_OFF:
61667d8d
ID		 1458 case STATE_RADIO_RX_OFF_LINK:
1459 rt61pci_toggle_rx(rt2x00dev, STATE_RADIO_RX_OFF);
95ea3627
ID		 1460 break;
1461 case STATE_DEEP_SLEEP:
1462 case STATE_SLEEP:
1463 case STATE_STANDBY:
1464 case STATE_AWAKE:
1465 retval = rt61pci_set_state(rt2x00dev, state);
1466 break;
1467 default:
1468 retval = -ENOTSUPP;
1469 break;
1470 }
1471
1472 return retval;
1473}
1474
1475/*
1476 * TX descriptor initialization
1477 */
1478static void rt61pci_write_tx_desc(struct rt2x00_dev *rt2x00dev,
dd3193e1 1479 struct sk_buff *skb,
181d6902 1480 struct txentry_desc *txdesc,
dd3193e1 1481 struct ieee80211_tx_control *control)
95ea3627 1482{
181d6902 1483 struct skb_frame_desc *skbdesc = get_skb_frame_desc(skb);
dd3193e1 1484 __le32 *txd = skbdesc->desc;
95ea3627
ID		 1485 u32 word;
1486
1487 /*
1488 * Start writing the descriptor words.
1489 */
1490 rt2x00_desc_read(txd, 1, &word);
181d6902
ID		 1491 rt2x00_set_field32(&word, TXD_W1_HOST_Q_ID, txdesc->queue);
1492 rt2x00_set_field32(&word, TXD_W1_AIFSN, txdesc->aifs);
1493 rt2x00_set_field32(&word, TXD_W1_CWMIN, txdesc->cw_min);
1494 rt2x00_set_field32(&word, TXD_W1_CWMAX, txdesc->cw_max);
95ea3627
ID		 1495 rt2x00_set_field32(&word, TXD_W1_IV_OFFSET, IEEE80211_HEADER);
1496 rt2x00_set_field32(&word, TXD_W1_HW_SEQUENCE, 1);
1497 rt2x00_desc_write(txd, 1, word);
1498
1499 rt2x00_desc_read(txd, 2, &word);
181d6902
ID		 1500 rt2x00_set_field32(&word, TXD_W2_PLCP_SIGNAL, txdesc->signal);
1501 rt2x00_set_field32(&word, TXD_W2_PLCP_SERVICE, txdesc->service);
1502 rt2x00_set_field32(&word, TXD_W2_PLCP_LENGTH_LOW, txdesc->length_low);
1503 rt2x00_set_field32(&word, TXD_W2_PLCP_LENGTH_HIGH, txdesc->length_high);
95ea3627
ID		 1504 rt2x00_desc_write(txd, 2, word);
1505
1506 rt2x00_desc_read(txd, 5, &word);
8318d78a 1507/* XXX: removed for now
95ea3627
ID		 1508 rt2x00_set_field32(&word, TXD_W5_TX_POWER,
1509 TXPOWER_TO_DEV(control->power_level));
8318d78a 1510 */
95ea3627
ID		 1511 rt2x00_set_field32(&word, TXD_W5_WAITING_DMA_DONE_INT, 1);
1512 rt2x00_desc_write(txd, 5, word);
1513
d7bafff3
AB		 1514 if (skbdesc->desc_len > TXINFO_SIZE) {
1515 rt2x00_desc_read(txd, 11, &word);
1516 rt2x00_set_field32(&word, TXD_W11_BUFFER_LENGTH0, skbdesc->data_len);
1517 rt2x00_desc_write(txd, 11, word);
1518 }
95ea3627
ID		 1519
1520 rt2x00_desc_read(txd, 0, &word);
1521 rt2x00_set_field32(&word, TXD_W0_OWNER_NIC, 1);
1522 rt2x00_set_field32(&word, TXD_W0_VALID, 1);
1523 rt2x00_set_field32(&word, TXD_W0_MORE_FRAG,
181d6902 1524 test_bit(ENTRY_TXD_MORE_FRAG, &txdesc->flags));
95ea3627 1525 rt2x00_set_field32(&word, TXD_W0_ACK,
181d6902 1526 test_bit(ENTRY_TXD_ACK, &txdesc->flags));
95ea3627 1527 rt2x00_set_field32(&word, TXD_W0_TIMESTAMP,
181d6902 1528 test_bit(ENTRY_TXD_REQ_TIMESTAMP, &txdesc->flags));
95ea3627 1529 rt2x00_set_field32(&word, TXD_W0_OFDM,
181d6902
ID		 1530 test_bit(ENTRY_TXD_OFDM_RATE, &txdesc->flags));
1531 rt2x00_set_field32(&word, TXD_W0_IFS, txdesc->ifs);
95ea3627
ID		 1532 rt2x00_set_field32(&word, TXD_W0_RETRY_MODE,
1533 !!(control->flags &
1534 IEEE80211_TXCTL_LONG_RETRY_LIMIT));
1535 rt2x00_set_field32(&word, TXD_W0_TKIP_MIC, 0);
dd3193e1 1536 rt2x00_set_field32(&word, TXD_W0_DATABYTE_COUNT, skbdesc->data_len);
95ea3627 1537 rt2x00_set_field32(&word, TXD_W0_BURST,
181d6902 1538 test_bit(ENTRY_TXD_BURST, &txdesc->flags));
95ea3627
ID		 1539 rt2x00_set_field32(&word, TXD_W0_CIPHER_ALG, CIPHER_NONE);
1540 rt2x00_desc_write(txd, 0, word);
1541}
1542
1543/*
1544 * TX data initialization
1545 */
1546static void rt61pci_kick_tx_queue(struct rt2x00_dev *rt2x00dev,
5957da4c 1547 const unsigned int queue)
95ea3627
ID		 1548{
1549 u32 reg;
1550
5957da4c 1551 if (queue == RT2X00_BCN_QUEUE_BEACON) {
95ea3627
ID		 1552 /*
1553 * For Wi-Fi faily generated beacons between participating
1554 * stations. Set TBTT phase adaptive adjustment step to 8us.
1555 */
1556 rt2x00pci_register_write(rt2x00dev, TXRX_CSR10, 0x00001008);
1557
1558 rt2x00pci_register_read(rt2x00dev, TXRX_CSR9, &reg);
1559 if (!rt2x00_get_field32(reg, TXRX_CSR9_BEACON_GEN)) {
1560 rt2x00_set_field32(&reg, TXRX_CSR9_BEACON_GEN, 1);
1561 rt2x00pci_register_write(rt2x00dev, TXRX_CSR9, reg);
1562 }
1563 return;
1564 }
1565
1566 rt2x00pci_register_read(rt2x00dev, TX_CNTL_CSR, &reg);
ddc827f9
ID		 1567 rt2x00_set_field32(&reg, TX_CNTL_CSR_KICK_TX_AC0,
1568 (queue == IEEE80211_TX_QUEUE_DATA0));
1569 rt2x00_set_field32(&reg, TX_CNTL_CSR_KICK_TX_AC1,
1570 (queue == IEEE80211_TX_QUEUE_DATA1));
1571 rt2x00_set_field32(&reg, TX_CNTL_CSR_KICK_TX_AC2,
1572 (queue == IEEE80211_TX_QUEUE_DATA2));
1573 rt2x00_set_field32(&reg, TX_CNTL_CSR_KICK_TX_AC3,
1574 (queue == IEEE80211_TX_QUEUE_DATA3));
95ea3627
ID		 1575 rt2x00pci_register_write(rt2x00dev, TX_CNTL_CSR, reg);
1576}
1577
1578/*
1579 * RX control handlers
1580 */
1581static int rt61pci_agc_to_rssi(struct rt2x00_dev *rt2x00dev, int rxd_w1)
1582{
1583 u16 eeprom;
1584 u8 offset;
1585 u8 lna;
1586
1587 lna = rt2x00_get_field32(rxd_w1, RXD_W1_RSSI_LNA);
1588 switch (lna) {
1589 case 3:
1590 offset = 90;
1591 break;
1592 case 2:
1593 offset = 74;
1594 break;
1595 case 1:
1596 offset = 64;
1597 break;
1598 default:
1599 return 0;
1600 }
1601
8318d78a 1602 if (rt2x00dev->rx_status.band == IEEE80211_BAND_5GHZ) {
95ea3627
ID		 1603 if (test_bit(CONFIG_EXTERNAL_LNA_A, &rt2x00dev->flags))
1604 offset += 14;
1605
1606 if (lna == 3 || lna == 2)
1607 offset += 10;
1608
1609 rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_OFFSET_A, &eeprom);
1610 offset -= rt2x00_get_field16(eeprom, EEPROM_RSSI_OFFSET_A_1);
1611 } else {
1612 if (test_bit(CONFIG_EXTERNAL_LNA_BG, &rt2x00dev->flags))
1613 offset += 14;
1614
1615 rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_OFFSET_BG, &eeprom);
1616 offset -= rt2x00_get_field16(eeprom, EEPROM_RSSI_OFFSET_BG_1);
1617 }
1618
1619 return rt2x00_get_field32(rxd_w1, RXD_W1_RSSI_AGC) * 2 - offset;
1620}
1621
181d6902
ID		 1622static void rt61pci_fill_rxdone(struct queue_entry *entry,
1623 struct rxdone_entry_desc *rxdesc)
95ea3627 1624{
181d6902 1625 struct queue_entry_priv_pci_rx *priv_rx = entry->priv_data;
95ea3627
ID		 1626 u32 word0;
1627 u32 word1;
1628
181d6902
ID		 1629 rt2x00_desc_read(priv_rx->desc, 0, &word0);
1630 rt2x00_desc_read(priv_rx->desc, 1, &word1);
95ea3627 1631
181d6902 1632 rxdesc->flags = 0;
4150c572 1633 if (rt2x00_get_field32(word0, RXD_W0_CRC_ERROR))
181d6902 1634 rxdesc->flags |= RX_FLAG_FAILED_FCS_CRC;
95ea3627
ID		 1635
1636 /*
1637 * Obtain the status about this packet.
1638 */
181d6902
ID		 1639 rxdesc->signal = rt2x00_get_field32(word1, RXD_W1_SIGNAL);
1640 rxdesc->rssi = rt61pci_agc_to_rssi(entry->queue->rt2x00dev, word1);
1641 rxdesc->ofdm = rt2x00_get_field32(word0, RXD_W0_OFDM);
1642 rxdesc->size = rt2x00_get_field32(word0, RXD_W0_DATABYTE_COUNT);
1643 rxdesc->my_bss = !!rt2x00_get_field32(word0, RXD_W0_MY_BSS);
95ea3627
ID		 1644}
1645
1646/*
1647 * Interrupt functions.
1648 */
1649static void rt61pci_txdone(struct rt2x00_dev *rt2x00dev)
1650{
181d6902
ID		 1651 struct data_queue *queue;
1652 struct queue_entry *entry;
1653 struct queue_entry *entry_done;
1654 struct queue_entry_priv_pci_tx *priv_tx;
1655 struct txdone_entry_desc txdesc;
95ea3627
ID		 1656 u32 word;
1657 u32 reg;
1658 u32 old_reg;
1659 int type;
1660 int index;
95ea3627
ID		 1661
1662 /*
1663 * During each loop we will compare the freshly read
1664 * STA_CSR4 register value with the value read from
1665 * the previous loop. If the 2 values are equal then
1666 * we should stop processing because the chance it
1667 * quite big that the device has been unplugged and
1668 * we risk going into an endless loop.
1669 */
1670 old_reg = 0;
1671
1672 while (1) {
1673 rt2x00pci_register_read(rt2x00dev, STA_CSR4, &reg);
1674 if (!rt2x00_get_field32(reg, STA_CSR4_VALID))
1675 break;
1676
1677 if (old_reg == reg)
1678 break;
1679 old_reg = reg;
1680
1681 /*
1682 * Skip this entry when it contains an invalid
181d6902 1683 * queue identication number.
95ea3627
ID		 1684 */
1685 type = rt2x00_get_field32(reg, STA_CSR4_PID_TYPE);
181d6902
ID		 1686 queue = rt2x00queue_get_queue(rt2x00dev, type);
1687 if (unlikely(!queue))
95ea3627
ID		 1688 continue;
1689
1690 /*
1691 * Skip this entry when it contains an invalid
1692 * index number.
1693 */
1694 index = rt2x00_get_field32(reg, STA_CSR4_PID_SUBTYPE);
181d6902 1695 if (unlikely(index >= queue->limit))
95ea3627
ID		 1696 continue;
1697
181d6902
ID		 1698 entry = &queue->entries[index];
1699 priv_tx = entry->priv_data;
1700 rt2x00_desc_read(priv_tx->desc, 0, &word);
95ea3627
ID		 1701
1702 if (rt2x00_get_field32(word, TXD_W0_OWNER_NIC) ||
1703 !rt2x00_get_field32(word, TXD_W0_VALID))
1704 return;
1705
181d6902 1706 entry_done = rt2x00queue_get_entry(queue, Q_INDEX_DONE);
62bc060b 1707 while (entry != entry_done) {
181d6902
ID		 1708 /* Catch up.
1709 * Just report any entries we missed as failed.
1710 */
62bc060b 1711 WARNING(rt2x00dev,
181d6902
ID		 1712 "TX status report missed for entry %d\n",
1713 entry_done->entry_idx);
1714
1715 txdesc.status = TX_FAIL_OTHER;
1716 txdesc.retry = 0;
1717
1718 rt2x00pci_txdone(rt2x00dev, entry_done, &txdesc);
1719 entry_done = rt2x00queue_get_entry(queue, Q_INDEX_DONE);
62bc060b
MN		 1720 }
1721
95ea3627
ID		 1722 /*
1723 * Obtain the status about this packet.
1724 */
181d6902
ID		 1725 txdesc.status = rt2x00_get_field32(reg, STA_CSR4_TX_RESULT);
1726 txdesc.retry = rt2x00_get_field32(reg, STA_CSR4_RETRY_COUNT);
95ea3627 1727
181d6902 1728 rt2x00pci_txdone(rt2x00dev, entry, &txdesc);
95ea3627
ID		 1729 }
1730}
1731
1732static irqreturn_t rt61pci_interrupt(int irq, void *dev_instance)
1733{
1734 struct rt2x00_dev *rt2x00dev = dev_instance;
1735 u32 reg_mcu;
1736 u32 reg;
1737
1738 /*
1739 * Get the interrupt sources & saved to local variable.
1740 * Write register value back to clear pending interrupts.
1741 */
1742 rt2x00pci_register_read(rt2x00dev, MCU_INT_SOURCE_CSR, &reg_mcu);
1743 rt2x00pci_register_write(rt2x00dev, MCU_INT_SOURCE_CSR, reg_mcu);
1744
1745 rt2x00pci_register_read(rt2x00dev, INT_SOURCE_CSR, &reg);
1746 rt2x00pci_register_write(rt2x00dev, INT_SOURCE_CSR, reg);
1747
1748 if (!reg && !reg_mcu)
1749 return IRQ_NONE;
1750
1751 if (!test_bit(DEVICE_ENABLED_RADIO, &rt2x00dev->flags))
1752 return IRQ_HANDLED;
1753
1754 /*
1755 * Handle interrupts, walk through all bits
1756 * and run the tasks, the bits are checked in order of
1757 * priority.
1758 */
1759
1760 /*
1761 * 1 - Rx ring done interrupt.
1762 */
1763 if (rt2x00_get_field32(reg, INT_SOURCE_CSR_RXDONE))
1764 rt2x00pci_rxdone(rt2x00dev);
1765
1766 /*
1767 * 2 - Tx ring done interrupt.
1768 */
1769 if (rt2x00_get_field32(reg, INT_SOURCE_CSR_TXDONE))
1770 rt61pci_txdone(rt2x00dev);
1771
1772 /*
1773 * 3 - Handle MCU command done.
1774 */
1775 if (reg_mcu)
1776 rt2x00pci_register_write(rt2x00dev,
1777 M2H_CMD_DONE_CSR, 0xffffffff);
1778
1779 return IRQ_HANDLED;
1780}
1781
1782/*
1783 * Device probe functions.
1784 */
1785static int rt61pci_validate_eeprom(struct rt2x00_dev *rt2x00dev)
1786{
1787 struct eeprom_93cx6 eeprom;
1788 u32 reg;
1789 u16 word;
1790 u8 *mac;
1791 s8 value;
1792
1793 rt2x00pci_register_read(rt2x00dev, E2PROM_CSR, &reg);
1794
1795 eeprom.data = rt2x00dev;
1796 eeprom.register_read = rt61pci_eepromregister_read;
1797 eeprom.register_write = rt61pci_eepromregister_write;
1798 eeprom.width = rt2x00_get_field32(reg, E2PROM_CSR_TYPE_93C46) ?
1799 PCI_EEPROM_WIDTH_93C46 : PCI_EEPROM_WIDTH_93C66;
1800 eeprom.reg_data_in = 0;
1801 eeprom.reg_data_out = 0;
1802 eeprom.reg_data_clock = 0;
1803 eeprom.reg_chip_select = 0;
1804
1805 eeprom_93cx6_multiread(&eeprom, EEPROM_BASE, rt2x00dev->eeprom,
1806 EEPROM_SIZE / sizeof(u16));
1807
1808 /*
1809 * Start validation of the data that has been read.
1810 */
1811 mac = rt2x00_eeprom_addr(rt2x00dev, EEPROM_MAC_ADDR_0);
1812 if (!is_valid_ether_addr(mac)) {
0795af57
JP		 1813 DECLARE_MAC_BUF(macbuf);
1814
95ea3627 1815 random_ether_addr(mac);
0795af57 1816 EEPROM(rt2x00dev, "MAC: %s\n", print_mac(macbuf, mac));
95ea3627
ID		 1817 }
1818
1819 rt2x00_eeprom_read(rt2x00dev, EEPROM_ANTENNA, &word);
1820 if (word == 0xffff) {
1821 rt2x00_set_field16(&word, EEPROM_ANTENNA_NUM, 2);
362f3b6b
ID		 1822 rt2x00_set_field16(&word, EEPROM_ANTENNA_TX_DEFAULT,
1823 ANTENNA_B);
1824 rt2x00_set_field16(&word, EEPROM_ANTENNA_RX_DEFAULT,
1825 ANTENNA_B);
95ea3627
ID		 1826 rt2x00_set_field16(&word, EEPROM_ANTENNA_FRAME_TYPE, 0);
1827 rt2x00_set_field16(&word, EEPROM_ANTENNA_DYN_TXAGC, 0);
1828 rt2x00_set_field16(&word, EEPROM_ANTENNA_HARDWARE_RADIO, 0);
1829 rt2x00_set_field16(&word, EEPROM_ANTENNA_RF_TYPE, RF5225);
1830 rt2x00_eeprom_write(rt2x00dev, EEPROM_ANTENNA, word);
1831 EEPROM(rt2x00dev, "Antenna: 0x%04x\n", word);
1832 }
1833
1834 rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC, &word);
1835 if (word == 0xffff) {
1836 rt2x00_set_field16(&word, EEPROM_NIC_ENABLE_DIVERSITY, 0);
1837 rt2x00_set_field16(&word, EEPROM_NIC_TX_DIVERSITY, 0);
1838 rt2x00_set_field16(&word, EEPROM_NIC_TX_RX_FIXED, 0);
1839 rt2x00_set_field16(&word, EEPROM_NIC_EXTERNAL_LNA_BG, 0);
1840 rt2x00_set_field16(&word, EEPROM_NIC_CARDBUS_ACCEL, 0);
1841 rt2x00_set_field16(&word, EEPROM_NIC_EXTERNAL_LNA_A, 0);
1842 rt2x00_eeprom_write(rt2x00dev, EEPROM_NIC, word);
1843 EEPROM(rt2x00dev, "NIC: 0x%04x\n", word);
1844 }
1845
1846 rt2x00_eeprom_read(rt2x00dev, EEPROM_LED, &word);
1847 if (word == 0xffff) {
1848 rt2x00_set_field16(&word, EEPROM_LED_LED_MODE,
1849 LED_MODE_DEFAULT);
1850 rt2x00_eeprom_write(rt2x00dev, EEPROM_LED, word);
1851 EEPROM(rt2x00dev, "Led: 0x%04x\n", word);
1852 }
1853
1854 rt2x00_eeprom_read(rt2x00dev, EEPROM_FREQ, &word);
1855 if (word == 0xffff) {
1856 rt2x00_set_field16(&word, EEPROM_FREQ_OFFSET, 0);
1857 rt2x00_set_field16(&word, EEPROM_FREQ_SEQ, 0);
1858 rt2x00_eeprom_write(rt2x00dev, EEPROM_FREQ, word);
1859 EEPROM(rt2x00dev, "Freq: 0x%04x\n", word);
1860 }
1861
1862 rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_OFFSET_BG, &word);
1863 if (word == 0xffff) {
1864 rt2x00_set_field16(&word, EEPROM_RSSI_OFFSET_BG_1, 0);
1865 rt2x00_set_field16(&word, EEPROM_RSSI_OFFSET_BG_2, 0);
1866 rt2x00_eeprom_write(rt2x00dev, EEPROM_RSSI_OFFSET_BG, word);
1867 EEPROM(rt2x00dev, "RSSI OFFSET BG: 0x%04x\n", word);
1868 } else {
1869 value = rt2x00_get_field16(word, EEPROM_RSSI_OFFSET_BG_1);
1870 if (value < -10 || value > 10)
1871 rt2x00_set_field16(&word, EEPROM_RSSI_OFFSET_BG_1, 0);
1872 value = rt2x00_get_field16(word, EEPROM_RSSI_OFFSET_BG_2);
1873 if (value < -10 || value > 10)
1874 rt2x00_set_field16(&word, EEPROM_RSSI_OFFSET_BG_2, 0);
1875 rt2x00_eeprom_write(rt2x00dev, EEPROM_RSSI_OFFSET_BG, word);
1876 }
1877
1878 rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_OFFSET_A, &word);
1879 if (word == 0xffff) {
1880 rt2x00_set_field16(&word, EEPROM_RSSI_OFFSET_A_1, 0);
1881 rt2x00_set_field16(&word, EEPROM_RSSI_OFFSET_A_2, 0);
1882 rt2x00_eeprom_write(rt2x00dev, EEPROM_RSSI_OFFSET_A, word);
1883 EEPROM(rt2x00dev, "RSSI OFFSET BG: 0x%04x\n", word);
1884 } else {
1885 value = rt2x00_get_field16(word, EEPROM_RSSI_OFFSET_A_1);
1886 if (value < -10 || value > 10)
1887 rt2x00_set_field16(&word, EEPROM_RSSI_OFFSET_A_1, 0);
1888 value = rt2x00_get_field16(word, EEPROM_RSSI_OFFSET_A_2);
1889 if (value < -10 || value > 10)
1890 rt2x00_set_field16(&word, EEPROM_RSSI_OFFSET_A_2, 0);
1891 rt2x00_eeprom_write(rt2x00dev, EEPROM_RSSI_OFFSET_A, word);
1892 }
1893
1894 return 0;
1895}
1896
1897static int rt61pci_init_eeprom(struct rt2x00_dev *rt2x00dev)
1898{
1899 u32 reg;
1900 u16 value;
1901 u16 eeprom;
1902 u16 device;
1903
1904 /*
1905 * Read EEPROM word for configuration.
1906 */
1907 rt2x00_eeprom_read(rt2x00dev, EEPROM_ANTENNA, &eeprom);
1908
1909 /*
1910 * Identify RF chipset.
1911 * To determine the RT chip we have to read the
1912 * PCI header of the device.
1913 */
1914 pci_read_config_word(rt2x00dev_pci(rt2x00dev),
1915 PCI_CONFIG_HEADER_DEVICE, &device);
1916 value = rt2x00_get_field16(eeprom, EEPROM_ANTENNA_RF_TYPE);
1917 rt2x00pci_register_read(rt2x00dev, MAC_CSR0, &reg);
1918 rt2x00_set_chip(rt2x00dev, device, value, reg);
1919
1920 if (!rt2x00_rf(&rt2x00dev->chip, RF5225) &&
1921 !rt2x00_rf(&rt2x00dev->chip, RF5325) &&
1922 !rt2x00_rf(&rt2x00dev->chip, RF2527) &&
1923 !rt2x00_rf(&rt2x00dev->chip, RF2529)) {
1924 ERROR(rt2x00dev, "Invalid RF chipset detected.\n");
1925 return -ENODEV;
1926 }
1927
e4cd2ff8
ID		 1928 /*
1929 * Determine number of antenna's.
1930 */
1931 if (rt2x00_get_field16(eeprom, EEPROM_ANTENNA_NUM) == 2)
1932 __set_bit(CONFIG_DOUBLE_ANTENNA, &rt2x00dev->flags);
1933
95ea3627
ID		 1934 /*
1935 * Identify default antenna configuration.
1936 */
addc81bd 1937 rt2x00dev->default_ant.tx =
95ea3627 1938 rt2x00_get_field16(eeprom, EEPROM_ANTENNA_TX_DEFAULT);
addc81bd 1939 rt2x00dev->default_ant.rx =
95ea3627
ID		 1940 rt2x00_get_field16(eeprom, EEPROM_ANTENNA_RX_DEFAULT);
1941
1942 /*
1943 * Read the Frame type.
1944 */
1945 if (rt2x00_get_field16(eeprom, EEPROM_ANTENNA_FRAME_TYPE))
1946 __set_bit(CONFIG_FRAME_TYPE, &rt2x00dev->flags);
1947
95ea3627
ID		 1948 /*
1949 * Detect if this device has an hardware controlled radio.
1950 */
81873e9c 1951#ifdef CONFIG_RT61PCI_RFKILL
95ea3627 1952 if (rt2x00_get_field16(eeprom, EEPROM_ANTENNA_HARDWARE_RADIO))
066cb637 1953 __set_bit(CONFIG_SUPPORT_HW_BUTTON, &rt2x00dev->flags);
81873e9c 1954#endif /* CONFIG_RT61PCI_RFKILL */
95ea3627
ID		 1955
1956 /*
1957 * Read frequency offset and RF programming sequence.
1958 */
1959 rt2x00_eeprom_read(rt2x00dev, EEPROM_FREQ, &eeprom);
1960 if (rt2x00_get_field16(eeprom, EEPROM_FREQ_SEQ))
1961 __set_bit(CONFIG_RF_SEQUENCE, &rt2x00dev->flags);
1962
1963 rt2x00dev->freq_offset = rt2x00_get_field16(eeprom, EEPROM_FREQ_OFFSET);
1964
1965 /*
1966 * Read external LNA informations.
1967 */
1968 rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC, &eeprom);
1969
1970 if (rt2x00_get_field16(eeprom, EEPROM_NIC_EXTERNAL_LNA_A))
1971 __set_bit(CONFIG_EXTERNAL_LNA_A, &rt2x00dev->flags);
1972 if (rt2x00_get_field16(eeprom, EEPROM_NIC_EXTERNAL_LNA_BG))
1973 __set_bit(CONFIG_EXTERNAL_LNA_BG, &rt2x00dev->flags);
1974
e4cd2ff8
ID		 1975 /*
1976 * When working with a RF2529 chip without double antenna
1977 * the antenna settings should be gathered from the NIC
1978 * eeprom word.
1979 */
1980 if (rt2x00_rf(&rt2x00dev->chip, RF2529) &&
1981 !test_bit(CONFIG_DOUBLE_ANTENNA, &rt2x00dev->flags)) {
1982 switch (rt2x00_get_field16(eeprom, EEPROM_NIC_TX_RX_FIXED)) {
1983 case 0:
1984 rt2x00dev->default_ant.tx = ANTENNA_B;
1985 rt2x00dev->default_ant.rx = ANTENNA_A;
1986 break;
1987 case 1:
1988 rt2x00dev->default_ant.tx = ANTENNA_B;
1989 rt2x00dev->default_ant.rx = ANTENNA_B;
1990 break;
1991 case 2:
1992 rt2x00dev->default_ant.tx = ANTENNA_A;
1993 rt2x00dev->default_ant.rx = ANTENNA_A;
1994 break;
1995 case 3:
1996 rt2x00dev->default_ant.tx = ANTENNA_A;
1997 rt2x00dev->default_ant.rx = ANTENNA_B;
1998 break;
1999 }
2000
2001 if (rt2x00_get_field16(eeprom, EEPROM_NIC_TX_DIVERSITY))
2002 rt2x00dev->default_ant.tx = ANTENNA_SW_DIVERSITY;
2003 if (rt2x00_get_field16(eeprom, EEPROM_NIC_ENABLE_DIVERSITY))
2004 rt2x00dev->default_ant.rx = ANTENNA_SW_DIVERSITY;
2005 }
2006
95ea3627
ID		 2007 /*
2008 * Store led settings, for correct led behaviour.
2009 * If the eeprom value is invalid,
2010 * switch to default led mode.
2011 */
a9450b70 2012#ifdef CONFIG_RT61PCI_LEDS
95ea3627
ID		 2013 rt2x00_eeprom_read(rt2x00dev, EEPROM_LED, &eeprom);
2014
a9450b70
ID		 2015 value = rt2x00_get_field16(eeprom, EEPROM_LED_LED_MODE);
2016
2017 switch (value) {
2018 case LED_MODE_TXRX_ACTIVITY:
2019 case LED_MODE_ASUS:
2020 case LED_MODE_ALPHA:
2021 case LED_MODE_DEFAULT:
2022 rt2x00dev->led_flags =
2023 LED_SUPPORT_RADIO | LED_SUPPORT_ASSOC;
2024 break;
2025 case LED_MODE_SIGNAL_STRENGTH:
2026 rt2x00dev->led_flags =
2027 LED_SUPPORT_RADIO | LED_SUPPORT_ASSOC |
2028 LED_SUPPORT_QUALITY;
2029 break;
2030 }
95ea3627 2031
a9450b70
ID		 2032 rt2x00_set_field16(&rt2x00dev->led_mcu_reg, MCU_LEDCS_LED_MODE, value);
2033 rt2x00_set_field16(&rt2x00dev->led_mcu_reg, MCU_LEDCS_POLARITY_GPIO_0,
95ea3627
ID		 2034 rt2x00_get_field16(eeprom,
2035 EEPROM_LED_POLARITY_GPIO_0));
a9450b70 2036 rt2x00_set_field16(&rt2x00dev->led_mcu_reg, MCU_LEDCS_POLARITY_GPIO_1,
95ea3627
ID		 2037 rt2x00_get_field16(eeprom,
2038 EEPROM_LED_POLARITY_GPIO_1));
a9450b70 2039 rt2x00_set_field16(&rt2x00dev->led_mcu_reg, MCU_LEDCS_POLARITY_GPIO_2,
95ea3627
ID		 2040 rt2x00_get_field16(eeprom,
2041 EEPROM_LED_POLARITY_GPIO_2));
a9450b70 2042 rt2x00_set_field16(&rt2x00dev->led_mcu_reg, MCU_LEDCS_POLARITY_GPIO_3,
95ea3627
ID		 2043 rt2x00_get_field16(eeprom,
2044 EEPROM_LED_POLARITY_GPIO_3));
a9450b70 2045 rt2x00_set_field16(&rt2x00dev->led_mcu_reg, MCU_LEDCS_POLARITY_GPIO_4,
95ea3627
ID		 2046 rt2x00_get_field16(eeprom,
2047 EEPROM_LED_POLARITY_GPIO_4));
a9450b70 2048 rt2x00_set_field16(&rt2x00dev->led_mcu_reg, MCU_LEDCS_POLARITY_ACT,
95ea3627 2049 rt2x00_get_field16(eeprom, EEPROM_LED_POLARITY_ACT));
a9450b70 2050 rt2x00_set_field16(&rt2x00dev->led_mcu_reg, MCU_LEDCS_POLARITY_READY_BG,
95ea3627
ID		 2051 rt2x00_get_field16(eeprom,
2052 EEPROM_LED_POLARITY_RDY_G));
a9450b70 2053 rt2x00_set_field16(&rt2x00dev->led_mcu_reg, MCU_LEDCS_POLARITY_READY_A,
95ea3627
ID		 2054 rt2x00_get_field16(eeprom,
2055 EEPROM_LED_POLARITY_RDY_A));
a9450b70 2056#endif /* CONFIG_RT61PCI_LEDS */
95ea3627
ID		 2057
2058 return 0;
2059}
2060
2061/*
2062 * RF value list for RF5225 & RF5325
2063 * Supports: 2.4 GHz & 5.2 GHz, rf_sequence disabled
2064 */
2065static const struct rf_channel rf_vals_noseq[] = {
2066 { 1, 0x00002ccc, 0x00004786, 0x00068455, 0x000ffa0b },
2067 { 2, 0x00002ccc, 0x00004786, 0x00068455, 0x000ffa1f },
2068 { 3, 0x00002ccc, 0x0000478a, 0x00068455, 0x000ffa0b },
2069 { 4, 0x00002ccc, 0x0000478a, 0x00068455, 0x000ffa1f },
2070 { 5, 0x00002ccc, 0x0000478e, 0x00068455, 0x000ffa0b },
2071 { 6, 0x00002ccc, 0x0000478e, 0x00068455, 0x000ffa1f },
2072 { 7, 0x00002ccc, 0x00004792, 0x00068455, 0x000ffa0b },
2073 { 8, 0x00002ccc, 0x00004792, 0x00068455, 0x000ffa1f },
2074 { 9, 0x00002ccc, 0x00004796, 0x00068455, 0x000ffa0b },
2075 { 10, 0x00002ccc, 0x00004796, 0x00068455, 0x000ffa1f },
2076 { 11, 0x00002ccc, 0x0000479a, 0x00068455, 0x000ffa0b },
2077 { 12, 0x00002ccc, 0x0000479a, 0x00068455, 0x000ffa1f },
2078 { 13, 0x00002ccc, 0x0000479e, 0x00068455, 0x000ffa0b },
2079 { 14, 0x00002ccc, 0x000047a2, 0x00068455, 0x000ffa13 },
2080
2081 /* 802.11 UNI / HyperLan 2 */
2082 { 36, 0x00002ccc, 0x0000499a, 0x0009be55, 0x000ffa23 },
2083 { 40, 0x00002ccc, 0x000049a2, 0x0009be55, 0x000ffa03 },
2084 { 44, 0x00002ccc, 0x000049a6, 0x0009be55, 0x000ffa0b },
2085 { 48, 0x00002ccc, 0x000049aa, 0x0009be55, 0x000ffa13 },
2086 { 52, 0x00002ccc, 0x000049ae, 0x0009ae55, 0x000ffa1b },
2087 { 56, 0x00002ccc, 0x000049b2, 0x0009ae55, 0x000ffa23 },
2088 { 60, 0x00002ccc, 0x000049ba, 0x0009ae55, 0x000ffa03 },
2089 { 64, 0x00002ccc, 0x000049be, 0x0009ae55, 0x000ffa0b },
2090
2091 /* 802.11 HyperLan 2 */
2092 { 100, 0x00002ccc, 0x00004a2a, 0x000bae55, 0x000ffa03 },
2093 { 104, 0x00002ccc, 0x00004a2e, 0x000bae55, 0x000ffa0b },
2094 { 108, 0x00002ccc, 0x00004a32, 0x000bae55, 0x000ffa13 },
2095 { 112, 0x00002ccc, 0x00004a36, 0x000bae55, 0x000ffa1b },
2096 { 116, 0x00002ccc, 0x00004a3a, 0x000bbe55, 0x000ffa23 },
2097 { 120, 0x00002ccc, 0x00004a82, 0x000bbe55, 0x000ffa03 },
2098 { 124, 0x00002ccc, 0x00004a86, 0x000bbe55, 0x000ffa0b },
2099 { 128, 0x00002ccc, 0x00004a8a, 0x000bbe55, 0x000ffa13 },
2100 { 132, 0x00002ccc, 0x00004a8e, 0x000bbe55, 0x000ffa1b },
2101 { 136, 0x00002ccc, 0x00004a92, 0x000bbe55, 0x000ffa23 },
2102
2103 /* 802.11 UNII */
2104 { 140, 0x00002ccc, 0x00004a9a, 0x000bbe55, 0x000ffa03 },
2105 { 149, 0x00002ccc, 0x00004aa2, 0x000bbe55, 0x000ffa1f },
2106 { 153, 0x00002ccc, 0x00004aa6, 0x000bbe55, 0x000ffa27 },
2107 { 157, 0x00002ccc, 0x00004aae, 0x000bbe55, 0x000ffa07 },
2108 { 161, 0x00002ccc, 0x00004ab2, 0x000bbe55, 0x000ffa0f },
2109 { 165, 0x00002ccc, 0x00004ab6, 0x000bbe55, 0x000ffa17 },
2110
2111 /* MMAC(Japan)J52 ch 34,38,42,46 */
2112 { 34, 0x00002ccc, 0x0000499a, 0x0009be55, 0x000ffa0b },
2113 { 38, 0x00002ccc, 0x0000499e, 0x0009be55, 0x000ffa13 },
2114 { 42, 0x00002ccc, 0x000049a2, 0x0009be55, 0x000ffa1b },
2115 { 46, 0x00002ccc, 0x000049a6, 0x0009be55, 0x000ffa23 },
2116};
2117
2118/*
2119 * RF value list for RF5225 & RF5325
2120 * Supports: 2.4 GHz & 5.2 GHz, rf_sequence enabled
2121 */
2122static const struct rf_channel rf_vals_seq[] = {
2123 { 1, 0x00002ccc, 0x00004786, 0x00068455, 0x000ffa0b },
2124 { 2, 0x00002ccc, 0x00004786, 0x00068455, 0x000ffa1f },
2125 { 3, 0x00002ccc, 0x0000478a, 0x00068455, 0x000ffa0b },
2126 { 4, 0x00002ccc, 0x0000478a, 0x00068455, 0x000ffa1f },
2127 { 5, 0x00002ccc, 0x0000478e, 0x00068455, 0x000ffa0b },
2128 { 6, 0x00002ccc, 0x0000478e, 0x00068455, 0x000ffa1f },
2129 { 7, 0x00002ccc, 0x00004792, 0x00068455, 0x000ffa0b },
2130 { 8, 0x00002ccc, 0x00004792, 0x00068455, 0x000ffa1f },
2131 { 9, 0x00002ccc, 0x00004796, 0x00068455, 0x000ffa0b },
2132 { 10, 0x00002ccc, 0x00004796, 0x00068455, 0x000ffa1f },
2133 { 11, 0x00002ccc, 0x0000479a, 0x00068455, 0x000ffa0b },
2134 { 12, 0x00002ccc, 0x0000479a, 0x00068455, 0x000ffa1f },
2135 { 13, 0x00002ccc, 0x0000479e, 0x00068455, 0x000ffa0b },
2136 { 14, 0x00002ccc, 0x000047a2, 0x00068455, 0x000ffa13 },
2137
2138 /* 802.11 UNI / HyperLan 2 */
2139 { 36, 0x00002cd4, 0x0004481a, 0x00098455, 0x000c0a03 },
2140 { 40, 0x00002cd0, 0x00044682, 0x00098455, 0x000c0a03 },
2141 { 44, 0x00002cd0, 0x00044686, 0x00098455, 0x000c0a1b },
2142 { 48, 0x00002cd0, 0x0004468e, 0x00098655, 0x000c0a0b },
2143 { 52, 0x00002cd0, 0x00044692, 0x00098855, 0x000c0a23 },
2144 { 56, 0x00002cd0, 0x0004469a, 0x00098c55, 0x000c0a13 },
2145 { 60, 0x00002cd0, 0x000446a2, 0x00098e55, 0x000c0a03 },
2146 { 64, 0x00002cd0, 0x000446a6, 0x00099255, 0x000c0a1b },
2147
2148 /* 802.11 HyperLan 2 */
2149 { 100, 0x00002cd4, 0x0004489a, 0x000b9855, 0x000c0a03 },
2150 { 104, 0x00002cd4, 0x000448a2, 0x000b9855, 0x000c0a03 },
2151 { 108, 0x00002cd4, 0x000448aa, 0x000b9855, 0x000c0a03 },
2152 { 112, 0x00002cd4, 0x000448b2, 0x000b9a55, 0x000c0a03 },
2153 { 116, 0x00002cd4, 0x000448ba, 0x000b9a55, 0x000c0a03 },
2154 { 120, 0x00002cd0, 0x00044702, 0x000b9a55, 0x000c0a03 },
2155 { 124, 0x00002cd0, 0x00044706, 0x000b9a55, 0x000c0a1b },
2156 { 128, 0x00002cd0, 0x0004470e, 0x000b9c55, 0x000c0a0b },
2157 { 132, 0x00002cd0, 0x00044712, 0x000b9c55, 0x000c0a23 },
2158 { 136, 0x00002cd0, 0x0004471a, 0x000b9e55, 0x000c0a13 },
2159
2160 /* 802.11 UNII */
2161 { 140, 0x00002cd0, 0x00044722, 0x000b9e55, 0x000c0a03 },
2162 { 149, 0x00002cd0, 0x0004472e, 0x000ba255, 0x000c0a1b },
2163 { 153, 0x00002cd0, 0x00044736, 0x000ba255, 0x000c0a0b },
2164 { 157, 0x00002cd4, 0x0004490a, 0x000ba255, 0x000c0a17 },
2165 { 161, 0x00002cd4, 0x00044912, 0x000ba255, 0x000c0a17 },
2166 { 165, 0x00002cd4, 0x0004491a, 0x000ba255, 0x000c0a17 },
2167
2168 /* MMAC(Japan)J52 ch 34,38,42,46 */
2169 { 34, 0x00002ccc, 0x0000499a, 0x0009be55, 0x000c0a0b },
2170 { 38, 0x00002ccc, 0x0000499e, 0x0009be55, 0x000c0a13 },
2171 { 42, 0x00002ccc, 0x000049a2, 0x0009be55, 0x000c0a1b },
2172 { 46, 0x00002ccc, 0x000049a6, 0x0009be55, 0x000c0a23 },
2173};
2174
2175static void rt61pci_probe_hw_mode(struct rt2x00_dev *rt2x00dev)
2176{
2177 struct hw_mode_spec *spec = &rt2x00dev->spec;
2178 u8 *txpower;
2179 unsigned int i;
2180
2181 /*
2182 * Initialize all hw fields.
2183 */
2184 rt2x00dev->hw->flags =
2185 IEEE80211_HW_HOST_GEN_BEACON_TEMPLATE |
4150c572 2186 IEEE80211_HW_HOST_BROADCAST_PS_BUFFERING;
95ea3627
ID		 2187 rt2x00dev->hw->extra_tx_headroom = 0;
2188 rt2x00dev->hw->max_signal = MAX_SIGNAL;
2189 rt2x00dev->hw->max_rssi = MAX_RX_SSI;
871ff6ed 2190 rt2x00dev->hw->queues = 4;
95ea3627
ID		 2191
2192 SET_IEEE80211_DEV(rt2x00dev->hw, &rt2x00dev_pci(rt2x00dev)->dev);
2193 SET_IEEE80211_PERM_ADDR(rt2x00dev->hw,
2194 rt2x00_eeprom_addr(rt2x00dev,
2195 EEPROM_MAC_ADDR_0));
2196
2197 /*
2198 * Convert tx_power array in eeprom.
2199 */
2200 txpower = rt2x00_eeprom_addr(rt2x00dev, EEPROM_TXPOWER_G_START);
2201 for (i = 0; i < 14; i++)
2202 txpower[i] = TXPOWER_FROM_DEV(txpower[i]);
2203
2204 /*
2205 * Initialize hw_mode information.
2206 */
2207 spec->num_modes = 2;
2208 spec->num_rates = 12;
2209 spec->tx_power_a = NULL;
2210 spec->tx_power_bg = txpower;
2211 spec->tx_power_default = DEFAULT_TXPOWER;
2212
2213 if (!test_bit(CONFIG_RF_SEQUENCE, &rt2x00dev->flags)) {
2214 spec->num_channels = 14;
2215 spec->channels = rf_vals_noseq;
2216 } else {
2217 spec->num_channels = 14;
2218 spec->channels = rf_vals_seq;
2219 }
2220
2221 if (rt2x00_rf(&rt2x00dev->chip, RF5225) ||
2222 rt2x00_rf(&rt2x00dev->chip, RF5325)) {
2223 spec->num_modes = 3;
2224 spec->num_channels = ARRAY_SIZE(rf_vals_seq);
2225
2226 txpower = rt2x00_eeprom_addr(rt2x00dev, EEPROM_TXPOWER_A_START);
2227 for (i = 0; i < 14; i++)
2228 txpower[i] = TXPOWER_FROM_DEV(txpower[i]);
2229
2230 spec->tx_power_a = txpower;
2231 }
2232}
2233
2234static int rt61pci_probe_hw(struct rt2x00_dev *rt2x00dev)
2235{
2236 int retval;
2237
2238 /*
2239 * Allocate eeprom data.
2240 */
2241 retval = rt61pci_validate_eeprom(rt2x00dev);
2242 if (retval)
2243 return retval;
2244
2245 retval = rt61pci_init_eeprom(rt2x00dev);
2246 if (retval)
2247 return retval;
2248
2249 /*
2250 * Initialize hw specifications.
2251 */
2252 rt61pci_probe_hw_mode(rt2x00dev);
2253
2254 /*
9404ef34 2255 * This device requires firmware.
95ea3627 2256 */
066cb637 2257 __set_bit(DRIVER_REQUIRE_FIRMWARE, &rt2x00dev->flags);
9404ef34 2258 __set_bit(DRIVER_REQUIRE_FIRMWARE_CRC_ITU_T, &rt2x00dev->flags);
95ea3627
ID		 2259
2260 /*
2261 * Set the rssi offset.
2262 */
2263 rt2x00dev->rssi_offset = DEFAULT_RSSI_OFFSET;
2264
2265 return 0;
2266}
2267
2268/*
2269 * IEEE80211 stack callback functions.
2270 */
4150c572
JB		 2271static void rt61pci_configure_filter(struct ieee80211_hw *hw,
2272 unsigned int changed_flags,
2273 unsigned int *total_flags,
2274 int mc_count,
2275 struct dev_addr_list *mc_list)
2276{
2277 struct rt2x00_dev *rt2x00dev = hw->priv;
4150c572
JB		 2278 u32 reg;
2279
2280 /*
2281 * Mask off any flags we are going to ignore from
2282 * the total_flags field.
2283 */
2284 *total_flags &=
2285 FIF_ALLMULTI |
2286 FIF_FCSFAIL |
2287 FIF_PLCPFAIL |
2288 FIF_CONTROL |
2289 FIF_OTHER_BSS |
2290 FIF_PROMISC_IN_BSS;
2291
2292 /*
2293 * Apply some rules to the filters:
2294 * - Some filters imply different filters to be set.
2295 * - Some things we can't filter out at all.
4150c572
JB		 2296 */
2297 if (mc_count)
2298 *total_flags |= FIF_ALLMULTI;
5886d0db
ID		 2299 if (*total_flags & FIF_OTHER_BSS ||
2300 *total_flags & FIF_PROMISC_IN_BSS)
4150c572 2301 *total_flags |= FIF_PROMISC_IN_BSS | FIF_OTHER_BSS;
4150c572
JB		 2302
2303 /*
2304 * Check if there is any work left for us.
2305 */
3c4f2085 2306 if (rt2x00dev->packet_filter == *total_flags)
4150c572 2307 return;
3c4f2085 2308 rt2x00dev->packet_filter = *total_flags;
4150c572
JB		 2309
2310 /*
2311 * Start configuration steps.
2312 * Note that the version error will always be dropped
2313 * and broadcast frames will always be accepted since
2314 * there is no filter for it at this time.
2315 */
2316 rt2x00pci_register_read(rt2x00dev, TXRX_CSR0, &reg);
2317 rt2x00_set_field32(&reg, TXRX_CSR0_DROP_CRC,
2318 !(*total_flags & FIF_FCSFAIL));
2319 rt2x00_set_field32(&reg, TXRX_CSR0_DROP_PHYSICAL,
2320 !(*total_flags & FIF_PLCPFAIL));
2321 rt2x00_set_field32(&reg, TXRX_CSR0_DROP_CONTROL,
2322 !(*total_flags & FIF_CONTROL));
2323 rt2x00_set_field32(&reg, TXRX_CSR0_DROP_NOT_TO_ME,
2324 !(*total_flags & FIF_PROMISC_IN_BSS));
2325 rt2x00_set_field32(&reg, TXRX_CSR0_DROP_TO_DS,
2326 !(*total_flags & FIF_PROMISC_IN_BSS));
2327 rt2x00_set_field32(&reg, TXRX_CSR0_DROP_VERSION_ERROR, 1);
2328 rt2x00_set_field32(&reg, TXRX_CSR0_DROP_MULTICAST,
2329 !(*total_flags & FIF_ALLMULTI));
2330 rt2x00_set_field32(&reg, TXRX_CSR0_DROP_BORADCAST, 0);
2331 rt2x00_set_field32(&reg, TXRX_CSR0_DROP_ACK_CTS, 1);
2332 rt2x00pci_register_write(rt2x00dev, TXRX_CSR0, reg);
2333}
2334
95ea3627
ID		 2335static int rt61pci_set_retry_limit(struct ieee80211_hw *hw,
2336 u32 short_retry, u32 long_retry)
2337{
2338 struct rt2x00_dev *rt2x00dev = hw->priv;
2339 u32 reg;
2340
2341 rt2x00pci_register_read(rt2x00dev, TXRX_CSR4, &reg);
2342 rt2x00_set_field32(&reg, TXRX_CSR4_LONG_RETRY_LIMIT, long_retry);
2343 rt2x00_set_field32(&reg, TXRX_CSR4_SHORT_RETRY_LIMIT, short_retry);
2344 rt2x00pci_register_write(rt2x00dev, TXRX_CSR4, reg);
2345
2346 return 0;
2347}
2348
2349static u64 rt61pci_get_tsf(struct ieee80211_hw *hw)
2350{
2351 struct rt2x00_dev *rt2x00dev = hw->priv;
2352 u64 tsf;
2353 u32 reg;
2354
2355 rt2x00pci_register_read(rt2x00dev, TXRX_CSR13, &reg);
2356 tsf = (u64) rt2x00_get_field32(reg, TXRX_CSR13_HIGH_TSFTIMER) << 32;
2357 rt2x00pci_register_read(rt2x00dev, TXRX_CSR12, &reg);
2358 tsf |= rt2x00_get_field32(reg, TXRX_CSR12_LOW_TSFTIMER);
2359
2360 return tsf;
2361}
2362
2363static void rt61pci_reset_tsf(struct ieee80211_hw *hw)
2364{
2365 struct rt2x00_dev *rt2x00dev = hw->priv;
2366
2367 rt2x00pci_register_write(rt2x00dev, TXRX_CSR12, 0);
2368 rt2x00pci_register_write(rt2x00dev, TXRX_CSR13, 0);
2369}
2370
24845910 2371static int rt61pci_beacon_update(struct ieee80211_hw *hw, struct sk_buff *skb,
95ea3627
ID		 2372 struct ieee80211_tx_control *control)
2373{
2374 struct rt2x00_dev *rt2x00dev = hw->priv;
6bb40dd1 2375 struct rt2x00_intf *intf = vif_to_intf(control->vif);
181d6902 2376 struct skb_frame_desc *skbdesc;
6bb40dd1 2377 unsigned int beacon_base;
95ea3627 2378
6bb40dd1
ID		 2379 if (unlikely(!intf->beacon))
2380 return -ENOBUFS;
95ea3627
ID		 2381
2382 /*
2383 * We need to append the descriptor in front of the
2384 * beacon frame.
2385 */
6bb40dd1
ID		 2386 if (skb_headroom(skb) < intf->beacon->queue->desc_size) {
2387 if (pskb_expand_head(skb, intf->beacon->queue->desc_size,
2388 0, GFP_ATOMIC)) {
95ea3627
ID		 2389 dev_kfree_skb(skb);
2390 return -ENOMEM;
2391 }
2392 }
2393
2394 /*
08992f7f
ID		 2395 * Add the descriptor in front of the skb.
2396 */
6bb40dd1
ID		 2397 skb_push(skb, intf->beacon->queue->desc_size);
2398 memset(skb->data, 0, intf->beacon->queue->desc_size);
08992f7f
ID		 2399
2400 /*
2401 * Fill in skb descriptor
95ea3627 2402 */
181d6902
ID		 2403 skbdesc = get_skb_frame_desc(skb);
2404 memset(skbdesc, 0, sizeof(*skbdesc));
6bb40dd1
ID		 2405 skbdesc->data = skb->data + intf->beacon->queue->desc_size;
2406 skbdesc->data_len = skb->len - intf->beacon->queue->desc_size;
181d6902 2407 skbdesc->desc = skb->data;
6bb40dd1
ID		 2408 skbdesc->desc_len = intf->beacon->queue->desc_size;
2409 skbdesc->entry = intf->beacon;
c22eb87b 2410
6bb40dd1 2411 /*
5957da4c
ID		 2412 * mac80211 doesn't provide the control->queue variable
2413 * for beacons. Set our own queue identification so
2414 * it can be used during descriptor initialization.
6bb40dd1 2415 */
5957da4c 2416 control->queue = RT2X00_BCN_QUEUE_BEACON;
08992f7f 2417 rt2x00lib_write_tx_desc(rt2x00dev, skb, control);
95ea3627
ID		 2418
2419 /*
2420 * Write entire beacon with descriptor to register,
2421 * and kick the beacon generator.
2422 */
6bb40dd1
ID		 2423 beacon_base = HW_BEACON_OFFSET(intf->beacon->entry_idx);
2424 rt2x00pci_register_multiwrite(rt2x00dev, beacon_base,
9ee8f57e 2425 skb->data, skb->len);
6bb40dd1 2426 rt61pci_kick_tx_queue(rt2x00dev, control->queue);
95ea3627
ID		 2427
2428 return 0;
2429}
2430
2431static const struct ieee80211_ops rt61pci_mac80211_ops = {
2432 .tx = rt2x00mac_tx,
4150c572
JB		 2433 .start = rt2x00mac_start,
2434 .stop = rt2x00mac_stop,
95ea3627
ID		 2435 .add_interface = rt2x00mac_add_interface,
2436 .remove_interface = rt2x00mac_remove_interface,
2437 .config = rt2x00mac_config,
2438 .config_interface = rt2x00mac_config_interface,
4150c572 2439 .configure_filter = rt61pci_configure_filter,
95ea3627
ID		 2440 .get_stats = rt2x00mac_get_stats,
2441 .set_retry_limit = rt61pci_set_retry_limit,
471b3efd 2442 .bss_info_changed = rt2x00mac_bss_info_changed,
95ea3627
ID		 2443 .conf_tx = rt2x00mac_conf_tx,
2444 .get_tx_stats = rt2x00mac_get_tx_stats,
2445 .get_tsf = rt61pci_get_tsf,
2446 .reset_tsf = rt61pci_reset_tsf,
2447 .beacon_update = rt61pci_beacon_update,
2448};
2449
2450static const struct rt2x00lib_ops rt61pci_rt2x00_ops = {
2451 .irq_handler = rt61pci_interrupt,
2452 .probe_hw = rt61pci_probe_hw,
2453 .get_firmware_name = rt61pci_get_firmware_name,
2454 .load_firmware = rt61pci_load_firmware,
2455 .initialize = rt2x00pci_initialize,
2456 .uninitialize = rt2x00pci_uninitialize,
837e7f24
ID		 2457 .init_rxentry = rt61pci_init_rxentry,
2458 .init_txentry = rt61pci_init_txentry,
95ea3627 2459 .set_device_state = rt61pci_set_device_state,
95ea3627 2460 .rfkill_poll = rt61pci_rfkill_poll,
95ea3627
ID		 2461 .link_stats = rt61pci_link_stats,
2462 .reset_tuner = rt61pci_reset_tuner,
2463 .link_tuner = rt61pci_link_tuner,
a9450b70 2464 .led_brightness = rt61pci_led_brightness,
95ea3627
ID		 2465 .write_tx_desc = rt61pci_write_tx_desc,
2466 .write_tx_data = rt2x00pci_write_tx_data,
2467 .kick_tx_queue = rt61pci_kick_tx_queue,
2468 .fill_rxdone = rt61pci_fill_rxdone,
6bb40dd1 2469 .config_intf = rt61pci_config_intf,
5c58ee51 2470 .config_preamble = rt61pci_config_preamble,
95ea3627
ID		 2471 .config = rt61pci_config,
2472};
2473
181d6902
ID		 2474static const struct data_queue_desc rt61pci_queue_rx = {
2475 .entry_num = RX_ENTRIES,
2476 .data_size = DATA_FRAME_SIZE,
2477 .desc_size = RXD_DESC_SIZE,
2478 .priv_size = sizeof(struct queue_entry_priv_pci_rx),
2479};
2480
2481static const struct data_queue_desc rt61pci_queue_tx = {
2482 .entry_num = TX_ENTRIES,
2483 .data_size = DATA_FRAME_SIZE,
2484 .desc_size = TXD_DESC_SIZE,
2485 .priv_size = sizeof(struct queue_entry_priv_pci_tx),
2486};
2487
2488static const struct data_queue_desc rt61pci_queue_bcn = {
6bb40dd1 2489 .entry_num = 4 * BEACON_ENTRIES,
181d6902
ID		 2490 .data_size = MGMT_FRAME_SIZE,
2491 .desc_size = TXINFO_SIZE,
2492 .priv_size = sizeof(struct queue_entry_priv_pci_tx),
2493};
2494
95ea3627 2495static const struct rt2x00_ops rt61pci_ops = {
2360157c 2496 .name = KBUILD_MODNAME,
6bb40dd1
ID		 2497 .max_sta_intf = 1,
2498 .max_ap_intf = 4,
95ea3627
ID		 2499 .eeprom_size = EEPROM_SIZE,
2500 .rf_size = RF_SIZE,
181d6902
ID		 2501 .rx = &rt61pci_queue_rx,
2502 .tx = &rt61pci_queue_tx,
2503 .bcn = &rt61pci_queue_bcn,
95ea3627
ID		 2504 .lib = &rt61pci_rt2x00_ops,
2505 .hw = &rt61pci_mac80211_ops,
2506#ifdef CONFIG_RT2X00_LIB_DEBUGFS
2507 .debugfs = &rt61pci_rt2x00debug,
2508#endif /* CONFIG_RT2X00_LIB_DEBUGFS */
2509};
2510
2511/*
2512 * RT61pci module information.
2513 */
2514static struct pci_device_id rt61pci_device_table[] = {
2515 /* RT2561s */
2516 { PCI_DEVICE(0x1814, 0x0301), PCI_DEVICE_DATA(&rt61pci_ops) },
2517 /* RT2561 v2 */
2518 { PCI_DEVICE(0x1814, 0x0302), PCI_DEVICE_DATA(&rt61pci_ops) },
2519 /* RT2661 */
2520 { PCI_DEVICE(0x1814, 0x0401), PCI_DEVICE_DATA(&rt61pci_ops) },
2521 { 0, }
2522};
2523
2524MODULE_AUTHOR(DRV_PROJECT);
2525MODULE_VERSION(DRV_VERSION);
2526MODULE_DESCRIPTION("Ralink RT61 PCI & PCMCIA Wireless LAN driver.");
2527MODULE_SUPPORTED_DEVICE("Ralink RT2561, RT2561s & RT2661 "
2528 "PCI & PCMCIA chipset based cards");
2529MODULE_DEVICE_TABLE(pci, rt61pci_device_table);
2530MODULE_FIRMWARE(FIRMWARE_RT2561);
2531MODULE_FIRMWARE(FIRMWARE_RT2561s);
2532MODULE_FIRMWARE(FIRMWARE_RT2661);
2533MODULE_LICENSE("GPL");
2534
2535static struct pci_driver rt61pci_driver = {
2360157c 2536 .name = KBUILD_MODNAME,
95ea3627
ID		 2537 .id_table = rt61pci_device_table,
2538 .probe = rt2x00pci_probe,
2539 .remove = __devexit_p(rt2x00pci_remove),
2540 .suspend = rt2x00pci_suspend,
2541 .resume = rt2x00pci_resume,
2542};
2543
2544static int __init rt61pci_init(void)
2545{
2546 return pci_register_driver(&rt61pci_driver);
2547}
2548
2549static void __exit rt61pci_exit(void)
2550{
2551 pci_unregister_driver(&rt61pci_driver);
2552}
2553
2554module_init(rt61pci_init);
2555module_exit(rt61pci_exit);
Linux kernel - Deliverables
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