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Merge branch 'for-linus' of git://neil.brown.name/md
[deliverable/linux.git] / drivers / net / wireless / rt2x00 / rt61pci.c
CommitLineData
95ea3627 1/*
4e54c711 2 Copyright (C) 2004 - 2009 rt2x00 SourceForge Project
95ea3627
ID		 3 <http://rt2x00.serialmonkey.com>
4
5 This program is free software; you can redistribute it and/or modify
6 it under the terms of the GNU General Public License as published by
7 the Free Software Foundation; either version 2 of the License, or
8 (at your option) any later version.
9
10 This program is distributed in the hope that it will be useful,
11 but WITHOUT ANY WARRANTY; without even the implied warranty of
12 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 GNU General Public License for more details.
14
15 You should have received a copy of the GNU General Public License
16 along with this program; if not, write to the
17 Free Software Foundation, Inc.,
18 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
19 */
20
21/*
22 Module: rt61pci
23 Abstract: rt61pci device specific routines.
24 Supported chipsets: RT2561, RT2561s, RT2661.
25 */
26
a7f3a06c 27#include <linux/crc-itu-t.h>
95ea3627
ID		 28#include <linux/delay.h>
29#include <linux/etherdevice.h>
30#include <linux/init.h>
31#include <linux/kernel.h>
32#include <linux/module.h>
33#include <linux/pci.h>
34#include <linux/eeprom_93cx6.h>
35
36#include "rt2x00.h"
37#include "rt2x00pci.h"
38#include "rt61pci.h"
39
008c4482
ID		 40/*
41 * Allow hardware encryption to be disabled.
42 */
43static int modparam_nohwcrypt = 0;
44module_param_named(nohwcrypt, modparam_nohwcrypt, bool, S_IRUGO);
45MODULE_PARM_DESC(nohwcrypt, "Disable hardware encryption.");
46
95ea3627
ID		 47/*
48 * Register access.
49 * BBP and RF register require indirect register access,
50 * and use the CSR registers PHY_CSR3 and PHY_CSR4 to achieve this.
51 * These indirect registers work with busy bits,
52 * and we will try maximal REGISTER_BUSY_COUNT times to access
53 * the register while taking a REGISTER_BUSY_DELAY us delay
54 * between each attampt. When the busy bit is still set at that time,
55 * the access attempt is considered to have failed,
56 * and we will print an error.
57 */
c9c3b1a5
ID		 58#define WAIT_FOR_BBP(__dev, __reg) \
59 rt2x00pci_regbusy_read((__dev), PHY_CSR3, PHY_CSR3_BUSY, (__reg))
60#define WAIT_FOR_RF(__dev, __reg) \
61 rt2x00pci_regbusy_read((__dev), PHY_CSR4, PHY_CSR4_BUSY, (__reg))
62#define WAIT_FOR_MCU(__dev, __reg) \
63 rt2x00pci_regbusy_read((__dev), H2M_MAILBOX_CSR, \
64 H2M_MAILBOX_CSR_OWNER, (__reg))
95ea3627 65
0e14f6d3 66static void rt61pci_bbp_write(struct rt2x00_dev *rt2x00dev,
95ea3627
ID		 67 const unsigned int word, const u8 value)
68{
69 u32 reg;
70
8ff48a8b
ID		 71 mutex_lock(&rt2x00dev->csr_mutex);
72
95ea3627 73 /*
c9c3b1a5
ID		 74 * Wait until the BBP becomes available, afterwards we
75 * can safely write the new data into the register.
95ea3627 76 */
c9c3b1a5
ID		 77 if (WAIT_FOR_BBP(rt2x00dev, &reg)) {
78 reg = 0;
79 rt2x00_set_field32(&reg, PHY_CSR3_VALUE, value);
80 rt2x00_set_field32(&reg, PHY_CSR3_REGNUM, word);
81 rt2x00_set_field32(&reg, PHY_CSR3_BUSY, 1);
82 rt2x00_set_field32(&reg, PHY_CSR3_READ_CONTROL, 0);
83
84 rt2x00pci_register_write(rt2x00dev, PHY_CSR3, reg);
85 }
8ff48a8b 86
8ff48a8b 87 mutex_unlock(&rt2x00dev->csr_mutex);
95ea3627
ID		 88}
89
0e14f6d3 90static void rt61pci_bbp_read(struct rt2x00_dev *rt2x00dev,
95ea3627
ID		 91 const unsigned int word, u8 *value)
92{
93 u32 reg;
94
8ff48a8b
ID		 95 mutex_lock(&rt2x00dev->csr_mutex);
96
95ea3627 97 /*
c9c3b1a5
ID		 98 * Wait until the BBP becomes available, afterwards we
99 * can safely write the read request into the register.
100 * After the data has been written, we wait until hardware
101 * returns the correct value, if at any time the register
102 * doesn't become available in time, reg will be 0xffffffff
103 * which means we return 0xff to the caller.
95ea3627 104 */
c9c3b1a5
ID		 105 if (WAIT_FOR_BBP(rt2x00dev, &reg)) {
106 reg = 0;
107 rt2x00_set_field32(&reg, PHY_CSR3_REGNUM, word);
108 rt2x00_set_field32(&reg, PHY_CSR3_BUSY, 1);
109 rt2x00_set_field32(&reg, PHY_CSR3_READ_CONTROL, 1);
95ea3627 110
c9c3b1a5 111 rt2x00pci_register_write(rt2x00dev, PHY_CSR3, reg);
95ea3627 112
c9c3b1a5
ID		 113 WAIT_FOR_BBP(rt2x00dev, &reg);
114 }
95ea3627
ID		 115
116 *value = rt2x00_get_field32(reg, PHY_CSR3_VALUE);
8ff48a8b 117
8ff48a8b 118 mutex_unlock(&rt2x00dev->csr_mutex);
95ea3627
ID		 119}
120
0e14f6d3 121static void rt61pci_rf_write(struct rt2x00_dev *rt2x00dev,
95ea3627
ID		 122 const unsigned int word, const u32 value)
123{
124 u32 reg;
95ea3627 125
8ff48a8b
ID		 126 mutex_lock(&rt2x00dev->csr_mutex);
127
c9c3b1a5
ID		 128 /*
129 * Wait until the RF becomes available, afterwards we
130 * can safely write the new data into the register.
131 */
132 if (WAIT_FOR_RF(rt2x00dev, &reg)) {
133 reg = 0;
134 rt2x00_set_field32(&reg, PHY_CSR4_VALUE, value);
135 rt2x00_set_field32(&reg, PHY_CSR4_NUMBER_OF_BITS, 21);
136 rt2x00_set_field32(&reg, PHY_CSR4_IF_SELECT, 0);
137 rt2x00_set_field32(&reg, PHY_CSR4_BUSY, 1);
138
139 rt2x00pci_register_write(rt2x00dev, PHY_CSR4, reg);
140 rt2x00_rf_write(rt2x00dev, word, value);
95ea3627
ID		 141 }
142
8ff48a8b 143 mutex_unlock(&rt2x00dev->csr_mutex);
95ea3627
ID		 144}
145
0e14f6d3 146static void rt61pci_mcu_request(struct rt2x00_dev *rt2x00dev,
95ea3627
ID		 147 const u8 command, const u8 token,
148 const u8 arg0, const u8 arg1)
149{
150 u32 reg;
151
8ff48a8b
ID		 152 mutex_lock(&rt2x00dev->csr_mutex);
153
c9c3b1a5
ID		 154 /*
155 * Wait until the MCU becomes available, afterwards we
156 * can safely write the new data into the register.
157 */
158 if (WAIT_FOR_MCU(rt2x00dev, &reg)) {
159 rt2x00_set_field32(&reg, H2M_MAILBOX_CSR_OWNER, 1);
160 rt2x00_set_field32(&reg, H2M_MAILBOX_CSR_CMD_TOKEN, token);
161 rt2x00_set_field32(&reg, H2M_MAILBOX_CSR_ARG0, arg0);
162 rt2x00_set_field32(&reg, H2M_MAILBOX_CSR_ARG1, arg1);
163 rt2x00pci_register_write(rt2x00dev, H2M_MAILBOX_CSR, reg);
164
165 rt2x00pci_register_read(rt2x00dev, HOST_CMD_CSR, &reg);
166 rt2x00_set_field32(&reg, HOST_CMD_CSR_HOST_COMMAND, command);
167 rt2x00_set_field32(&reg, HOST_CMD_CSR_INTERRUPT_MCU, 1);
168 rt2x00pci_register_write(rt2x00dev, HOST_CMD_CSR, reg);
169 }
8ff48a8b 170
8ff48a8b
ID		 171 mutex_unlock(&rt2x00dev->csr_mutex);
172
95ea3627
ID		 173}
174
175static void rt61pci_eepromregister_read(struct eeprom_93cx6 *eeprom)
176{
177 struct rt2x00_dev *rt2x00dev = eeprom->data;
178 u32 reg;
179
180 rt2x00pci_register_read(rt2x00dev, E2PROM_CSR, &reg);
181
182 eeprom->reg_data_in = !!rt2x00_get_field32(reg, E2PROM_CSR_DATA_IN);
183 eeprom->reg_data_out = !!rt2x00_get_field32(reg, E2PROM_CSR_DATA_OUT);
184 eeprom->reg_data_clock =
185 !!rt2x00_get_field32(reg, E2PROM_CSR_DATA_CLOCK);
186 eeprom->reg_chip_select =
187 !!rt2x00_get_field32(reg, E2PROM_CSR_CHIP_SELECT);
188}
189
190static void rt61pci_eepromregister_write(struct eeprom_93cx6 *eeprom)
191{
192 struct rt2x00_dev *rt2x00dev = eeprom->data;
193 u32 reg = 0;
194
195 rt2x00_set_field32(&reg, E2PROM_CSR_DATA_IN, !!eeprom->reg_data_in);
196 rt2x00_set_field32(&reg, E2PROM_CSR_DATA_OUT, !!eeprom->reg_data_out);
197 rt2x00_set_field32(&reg, E2PROM_CSR_DATA_CLOCK,
198 !!eeprom->reg_data_clock);
199 rt2x00_set_field32(&reg, E2PROM_CSR_CHIP_SELECT,
200 !!eeprom->reg_chip_select);
201
202 rt2x00pci_register_write(rt2x00dev, E2PROM_CSR, reg);
203}
204
205#ifdef CONFIG_RT2X00_LIB_DEBUGFS
95ea3627
ID		 206static const struct rt2x00debug rt61pci_rt2x00debug = {
207 .owner = THIS_MODULE,
208 .csr = {
743b97ca
ID		 209 .read = rt2x00pci_register_read,
210 .write = rt2x00pci_register_write,
211 .flags = RT2X00DEBUGFS_OFFSET,
212 .word_base = CSR_REG_BASE,
95ea3627
ID		 213 .word_size = sizeof(u32),
214 .word_count = CSR_REG_SIZE / sizeof(u32),
215 },
216 .eeprom = {
217 .read = rt2x00_eeprom_read,
218 .write = rt2x00_eeprom_write,
743b97ca 219 .word_base = EEPROM_BASE,
95ea3627
ID		 220 .word_size = sizeof(u16),
221 .word_count = EEPROM_SIZE / sizeof(u16),
222 },
223 .bbp = {
224 .read = rt61pci_bbp_read,
225 .write = rt61pci_bbp_write,
743b97ca 226 .word_base = BBP_BASE,
95ea3627
ID		 227 .word_size = sizeof(u8),
228 .word_count = BBP_SIZE / sizeof(u8),
229 },
230 .rf = {
231 .read = rt2x00_rf_read,
232 .write = rt61pci_rf_write,
743b97ca 233 .word_base = RF_BASE,
95ea3627
ID		 234 .word_size = sizeof(u32),
235 .word_count = RF_SIZE / sizeof(u32),
236 },
237};
238#endif /* CONFIG_RT2X00_LIB_DEBUGFS */
239
58169529 240#ifdef CONFIG_RT2X00_LIB_RFKILL
95ea3627
ID		 241static int rt61pci_rfkill_poll(struct rt2x00_dev *rt2x00dev)
242{
243 u32 reg;
244
245 rt2x00pci_register_read(rt2x00dev, MAC_CSR13, &reg);
181d6902 246 return rt2x00_get_field32(reg, MAC_CSR13_BIT5);
95ea3627 247}
81873e9c
ID		 248#else
249#define rt61pci_rfkill_poll NULL
58169529 250#endif /* CONFIG_RT2X00_LIB_RFKILL */
95ea3627 251
771fd565 252#ifdef CONFIG_RT2X00_LIB_LEDS
a2e1d52a 253static void rt61pci_brightness_set(struct led_classdev *led_cdev,
a9450b70
ID		 254 enum led_brightness brightness)
255{
256 struct rt2x00_led *led =
257 container_of(led_cdev, struct rt2x00_led, led_dev);
258 unsigned int enabled = brightness != LED_OFF;
259 unsigned int a_mode =
260 (enabled && led->rt2x00dev->curr_band == IEEE80211_BAND_5GHZ);
261 unsigned int bg_mode =
262 (enabled && led->rt2x00dev->curr_band == IEEE80211_BAND_2GHZ);
263
264 if (led->type == LED_TYPE_RADIO) {
265 rt2x00_set_field16(&led->rt2x00dev->led_mcu_reg,
266 MCU_LEDCS_RADIO_STATUS, enabled);
267
268 rt61pci_mcu_request(led->rt2x00dev, MCU_LED, 0xff,
269 (led->rt2x00dev->led_mcu_reg & 0xff),
270 ((led->rt2x00dev->led_mcu_reg >> 8)));
271 } else if (led->type == LED_TYPE_ASSOC) {
272 rt2x00_set_field16(&led->rt2x00dev->led_mcu_reg,
273 MCU_LEDCS_LINK_BG_STATUS, bg_mode);
274 rt2x00_set_field16(&led->rt2x00dev->led_mcu_reg,
275 MCU_LEDCS_LINK_A_STATUS, a_mode);
276
277 rt61pci_mcu_request(led->rt2x00dev, MCU_LED, 0xff,
278 (led->rt2x00dev->led_mcu_reg & 0xff),
279 ((led->rt2x00dev->led_mcu_reg >> 8)));
280 } else if (led->type == LED_TYPE_QUALITY) {
281 /*
282 * The brightness is divided into 6 levels (0 - 5),
283 * this means we need to convert the brightness
284 * argument into the matching level within that range.
285 */
286 rt61pci_mcu_request(led->rt2x00dev, MCU_LED_STRENGTH, 0xff,
287 brightness / (LED_FULL / 6), 0);
288 }
289}
a2e1d52a
ID		 290
291static int rt61pci_blink_set(struct led_classdev *led_cdev,
292 unsigned long *delay_on,
293 unsigned long *delay_off)
294{
295 struct rt2x00_led *led =
296 container_of(led_cdev, struct rt2x00_led, led_dev);
297 u32 reg;
298
299 rt2x00pci_register_read(led->rt2x00dev, MAC_CSR14, &reg);
300 rt2x00_set_field32(&reg, MAC_CSR14_ON_PERIOD, *delay_on);
301 rt2x00_set_field32(&reg, MAC_CSR14_OFF_PERIOD, *delay_off);
302 rt2x00pci_register_write(led->rt2x00dev, MAC_CSR14, reg);
303
304 return 0;
305}
475433be
ID		 306
307static void rt61pci_init_led(struct rt2x00_dev *rt2x00dev,
308 struct rt2x00_led *led,
309 enum led_type type)
310{
311 led->rt2x00dev = rt2x00dev;
312 led->type = type;
313 led->led_dev.brightness_set = rt61pci_brightness_set;
314 led->led_dev.blink_set = rt61pci_blink_set;
315 led->flags = LED_INITIALIZED;
316}
771fd565 317#endif /* CONFIG_RT2X00_LIB_LEDS */
a9450b70 318
95ea3627
ID		 319/*
320 * Configuration handlers.
321 */
61e754f4
ID		 322static int rt61pci_config_shared_key(struct rt2x00_dev *rt2x00dev,
323 struct rt2x00lib_crypto *crypto,
324 struct ieee80211_key_conf *key)
325{
326 struct hw_key_entry key_entry;
327 struct rt2x00_field32 field;
328 u32 mask;
329 u32 reg;
330
331 if (crypto->cmd == SET_KEY) {
332 /*
333 * rt2x00lib can't determine the correct free
334 * key_idx for shared keys. We have 1 register
335 * with key valid bits. The goal is simple, read
336 * the register, if that is full we have no slots
337 * left.
338 * Note that each BSS is allowed to have up to 4
339 * shared keys, so put a mask over the allowed
340 * entries.
341 */
342 mask = (0xf << crypto->bssidx);
343
344 rt2x00pci_register_read(rt2x00dev, SEC_CSR0, &reg);
345 reg &= mask;
346
347 if (reg && reg == mask)
348 return -ENOSPC;
349
acaf908d 350 key->hw_key_idx += reg ? ffz(reg) : 0;
61e754f4
ID		 351
352 /*
353 * Upload key to hardware
354 */
355 memcpy(key_entry.key, crypto->key,
356 sizeof(key_entry.key));
357 memcpy(key_entry.tx_mic, crypto->tx_mic,
358 sizeof(key_entry.tx_mic));
359 memcpy(key_entry.rx_mic, crypto->rx_mic,
360 sizeof(key_entry.rx_mic));
361
362 reg = SHARED_KEY_ENTRY(key->hw_key_idx);
363 rt2x00pci_register_multiwrite(rt2x00dev, reg,
364 &key_entry, sizeof(key_entry));
365
366 /*
367 * The cipher types are stored over 2 registers.
368 * bssidx 0 and 1 keys are stored in SEC_CSR1 and
369 * bssidx 1 and 2 keys are stored in SEC_CSR5.
370 * Using the correct defines correctly will cause overhead,
371 * so just calculate the correct offset.
372 */
373 if (key->hw_key_idx < 8) {
374 field.bit_offset = (3 * key->hw_key_idx);
375 field.bit_mask = 0x7 << field.bit_offset;
376
377 rt2x00pci_register_read(rt2x00dev, SEC_CSR1, &reg);
378 rt2x00_set_field32(&reg, field, crypto->cipher);
379 rt2x00pci_register_write(rt2x00dev, SEC_CSR1, reg);
380 } else {
381 field.bit_offset = (3 * (key->hw_key_idx - 8));
382 field.bit_mask = 0x7 << field.bit_offset;
383
384 rt2x00pci_register_read(rt2x00dev, SEC_CSR5, &reg);
385 rt2x00_set_field32(&reg, field, crypto->cipher);
386 rt2x00pci_register_write(rt2x00dev, SEC_CSR5, reg);
387 }
388
389 /*
390 * The driver does not support the IV/EIV generation
391 * in hardware. However it doesn't support the IV/EIV
392 * inside the ieee80211 frame either, but requires it
393 * to be provided seperately for the descriptor.
394 * rt2x00lib will cut the IV/EIV data out of all frames
395 * given to us by mac80211, but we must tell mac80211
396 * to generate the IV/EIV data.
397 */
398 key->flags |= IEEE80211_KEY_FLAG_GENERATE_IV;
399 }
400
401 /*
402 * SEC_CSR0 contains only single-bit fields to indicate
403 * a particular key is valid. Because using the FIELD32()
404 * defines directly will cause a lot of overhead we use
405 * a calculation to determine the correct bit directly.
406 */
407 mask = 1 << key->hw_key_idx;
408
409 rt2x00pci_register_read(rt2x00dev, SEC_CSR0, &reg);
410 if (crypto->cmd == SET_KEY)
411 reg |= mask;
412 else if (crypto->cmd == DISABLE_KEY)
413 reg &= ~mask;
414 rt2x00pci_register_write(rt2x00dev, SEC_CSR0, reg);
415
416 return 0;
417}
418
419static int rt61pci_config_pairwise_key(struct rt2x00_dev *rt2x00dev,
420 struct rt2x00lib_crypto *crypto,
421 struct ieee80211_key_conf *key)
422{
423 struct hw_pairwise_ta_entry addr_entry;
424 struct hw_key_entry key_entry;
425 u32 mask;
426 u32 reg;
427
428 if (crypto->cmd == SET_KEY) {
429 /*
430 * rt2x00lib can't determine the correct free
431 * key_idx for pairwise keys. We have 2 registers
432 * with key valid bits. The goal is simple, read
433 * the first register, if that is full move to
434 * the next register.
435 * When both registers are full, we drop the key,
436 * otherwise we use the first invalid entry.
437 */
438 rt2x00pci_register_read(rt2x00dev, SEC_CSR2, &reg);
439 if (reg && reg == ~0) {
440 key->hw_key_idx = 32;
441 rt2x00pci_register_read(rt2x00dev, SEC_CSR3, &reg);
442 if (reg && reg == ~0)
443 return -ENOSPC;
444 }
445
acaf908d 446 key->hw_key_idx += reg ? ffz(reg) : 0;
61e754f4
ID		 447
448 /*
449 * Upload key to hardware
450 */
451 memcpy(key_entry.key, crypto->key,
452 sizeof(key_entry.key));
453 memcpy(key_entry.tx_mic, crypto->tx_mic,
454 sizeof(key_entry.tx_mic));
455 memcpy(key_entry.rx_mic, crypto->rx_mic,
456 sizeof(key_entry.rx_mic));
457
458 memset(&addr_entry, 0, sizeof(addr_entry));
459 memcpy(&addr_entry, crypto->address, ETH_ALEN);
460 addr_entry.cipher = crypto->cipher;
461
462 reg = PAIRWISE_KEY_ENTRY(key->hw_key_idx);
463 rt2x00pci_register_multiwrite(rt2x00dev, reg,
464 &key_entry, sizeof(key_entry));
465
466 reg = PAIRWISE_TA_ENTRY(key->hw_key_idx);
467 rt2x00pci_register_multiwrite(rt2x00dev, reg,
468 &addr_entry, sizeof(addr_entry));
469
470 /*
471 * Enable pairwise lookup table for given BSS idx,
472 * without this received frames will not be decrypted
473 * by the hardware.
474 */
475 rt2x00pci_register_read(rt2x00dev, SEC_CSR4, &reg);
476 reg |= (1 << crypto->bssidx);
477 rt2x00pci_register_write(rt2x00dev, SEC_CSR4, reg);
478
479 /*
480 * The driver does not support the IV/EIV generation
481 * in hardware. However it doesn't support the IV/EIV
482 * inside the ieee80211 frame either, but requires it
483 * to be provided seperately for the descriptor.
484 * rt2x00lib will cut the IV/EIV data out of all frames
485 * given to us by mac80211, but we must tell mac80211
486 * to generate the IV/EIV data.
487 */
488 key->flags |= IEEE80211_KEY_FLAG_GENERATE_IV;
489 }
490
491 /*
492 * SEC_CSR2 and SEC_CSR3 contain only single-bit fields to indicate
493 * a particular key is valid. Because using the FIELD32()
494 * defines directly will cause a lot of overhead we use
495 * a calculation to determine the correct bit directly.
496 */
497 if (key->hw_key_idx < 32) {
498 mask = 1 << key->hw_key_idx;
499
500 rt2x00pci_register_read(rt2x00dev, SEC_CSR2, &reg);
501 if (crypto->cmd == SET_KEY)
502 reg |= mask;
503 else if (crypto->cmd == DISABLE_KEY)
504 reg &= ~mask;
505 rt2x00pci_register_write(rt2x00dev, SEC_CSR2, reg);
506 } else {
507 mask = 1 << (key->hw_key_idx - 32);
508
509 rt2x00pci_register_read(rt2x00dev, SEC_CSR3, &reg);
510 if (crypto->cmd == SET_KEY)
511 reg |= mask;
512 else if (crypto->cmd == DISABLE_KEY)
513 reg &= ~mask;
514 rt2x00pci_register_write(rt2x00dev, SEC_CSR3, reg);
515 }
516
517 return 0;
518}
519
3a643d24
ID		 520static void rt61pci_config_filter(struct rt2x00_dev *rt2x00dev,
521 const unsigned int filter_flags)
522{
523 u32 reg;
524
525 /*
526 * Start configuration steps.
527 * Note that the version error will always be dropped
528 * and broadcast frames will always be accepted since
529 * there is no filter for it at this time.
530 */
531 rt2x00pci_register_read(rt2x00dev, TXRX_CSR0, &reg);
532 rt2x00_set_field32(&reg, TXRX_CSR0_DROP_CRC,
533 !(filter_flags & FIF_FCSFAIL));
534 rt2x00_set_field32(&reg, TXRX_CSR0_DROP_PHYSICAL,
535 !(filter_flags & FIF_PLCPFAIL));
536 rt2x00_set_field32(&reg, TXRX_CSR0_DROP_CONTROL,
537 !(filter_flags & FIF_CONTROL));
538 rt2x00_set_field32(&reg, TXRX_CSR0_DROP_NOT_TO_ME,
539 !(filter_flags & FIF_PROMISC_IN_BSS));
540 rt2x00_set_field32(&reg, TXRX_CSR0_DROP_TO_DS,
e0b005fa
ID		 541 !(filter_flags & FIF_PROMISC_IN_BSS) &&
542 !rt2x00dev->intf_ap_count);
3a643d24
ID		 543 rt2x00_set_field32(&reg, TXRX_CSR0_DROP_VERSION_ERROR, 1);
544 rt2x00_set_field32(&reg, TXRX_CSR0_DROP_MULTICAST,
545 !(filter_flags & FIF_ALLMULTI));
546 rt2x00_set_field32(&reg, TXRX_CSR0_DROP_BROADCAST, 0);
547 rt2x00_set_field32(&reg, TXRX_CSR0_DROP_ACK_CTS,
548 !(filter_flags & FIF_CONTROL));
549 rt2x00pci_register_write(rt2x00dev, TXRX_CSR0, reg);
550}
551
6bb40dd1
ID		 552static void rt61pci_config_intf(struct rt2x00_dev *rt2x00dev,
553 struct rt2x00_intf *intf,
554 struct rt2x00intf_conf *conf,
555 const unsigned int flags)
95ea3627 556{
6bb40dd1
ID		 557 unsigned int beacon_base;
558 u32 reg;
95ea3627 559
6bb40dd1
ID		 560 if (flags & CONFIG_UPDATE_TYPE) {
561 /*
562 * Clear current synchronisation setup.
563 * For the Beacon base registers we only need to clear
564 * the first byte since that byte contains the VALID and OWNER
565 * bits which (when set to 0) will invalidate the entire beacon.
566 */
567 beacon_base = HW_BEACON_OFFSET(intf->beacon->entry_idx);
6bb40dd1 568 rt2x00pci_register_write(rt2x00dev, beacon_base, 0);
95ea3627 569
6bb40dd1
ID		 570 /*
571 * Enable synchronisation.
572 */
573 rt2x00pci_register_read(rt2x00dev, TXRX_CSR9, &reg);
fd3c91c5 574 rt2x00_set_field32(&reg, TXRX_CSR9_TSF_TICKING, 1);
6bb40dd1 575 rt2x00_set_field32(&reg, TXRX_CSR9_TSF_SYNC, conf->sync);
fd3c91c5 576 rt2x00_set_field32(&reg, TXRX_CSR9_TBTT_ENABLE, 1);
6bb40dd1
ID		 577 rt2x00pci_register_write(rt2x00dev, TXRX_CSR9, reg);
578 }
95ea3627 579
6bb40dd1
ID		 580 if (flags & CONFIG_UPDATE_MAC) {
581 reg = le32_to_cpu(conf->mac[1]);
582 rt2x00_set_field32(&reg, MAC_CSR3_UNICAST_TO_ME_MASK, 0xff);
583 conf->mac[1] = cpu_to_le32(reg);
95ea3627 584
6bb40dd1
ID		 585 rt2x00pci_register_multiwrite(rt2x00dev, MAC_CSR2,
586 conf->mac, sizeof(conf->mac));
587 }
95ea3627 588
6bb40dd1
ID		 589 if (flags & CONFIG_UPDATE_BSSID) {
590 reg = le32_to_cpu(conf->bssid[1]);
591 rt2x00_set_field32(&reg, MAC_CSR5_BSS_ID_MASK, 3);
592 conf->bssid[1] = cpu_to_le32(reg);
95ea3627 593
6bb40dd1
ID		 594 rt2x00pci_register_multiwrite(rt2x00dev, MAC_CSR4,
595 conf->bssid, sizeof(conf->bssid));
596 }
95ea3627
ID		 597}
598
3a643d24
ID		 599static void rt61pci_config_erp(struct rt2x00_dev *rt2x00dev,
600 struct rt2x00lib_erp *erp)
95ea3627 601{
95ea3627 602 u32 reg;
95ea3627
ID		 603
604 rt2x00pci_register_read(rt2x00dev, TXRX_CSR0, &reg);
72810379 605 rt2x00_set_field32(&reg, TXRX_CSR0_RX_ACK_TIMEOUT, erp->ack_timeout);
8a566afe 606 rt2x00_set_field32(&reg, TXRX_CSR0_TSF_OFFSET, IEEE80211_HEADER);
95ea3627
ID		 607 rt2x00pci_register_write(rt2x00dev, TXRX_CSR0, reg);
608
609 rt2x00pci_register_read(rt2x00dev, TXRX_CSR4, &reg);
8a566afe 610 rt2x00_set_field32(&reg, TXRX_CSR4_AUTORESPOND_ENABLE, 1);
4f5af6eb 611 rt2x00_set_field32(&reg, TXRX_CSR4_AUTORESPOND_PREAMBLE,
72810379 612 !!erp->short_preamble);
95ea3627 613 rt2x00pci_register_write(rt2x00dev, TXRX_CSR4, reg);
95ea3627 614
e4ea1c40 615 rt2x00pci_register_write(rt2x00dev, TXRX_CSR5, erp->basic_rates);
95ea3627 616
8a566afe
ID		 617 rt2x00pci_register_read(rt2x00dev, TXRX_CSR9, &reg);
618 rt2x00_set_field32(&reg, TXRX_CSR9_BEACON_INTERVAL,
619 erp->beacon_int * 16);
620 rt2x00pci_register_write(rt2x00dev, TXRX_CSR9, reg);
621
e4ea1c40
ID		 622 rt2x00pci_register_read(rt2x00dev, MAC_CSR9, &reg);
623 rt2x00_set_field32(&reg, MAC_CSR9_SLOT_TIME, erp->slot_time);
624 rt2x00pci_register_write(rt2x00dev, MAC_CSR9, reg);
95ea3627 625
e4ea1c40
ID		 626 rt2x00pci_register_read(rt2x00dev, MAC_CSR8, &reg);
627 rt2x00_set_field32(&reg, MAC_CSR8_SIFS, erp->sifs);
628 rt2x00_set_field32(&reg, MAC_CSR8_SIFS_AFTER_RX_OFDM, 3);
629 rt2x00_set_field32(&reg, MAC_CSR8_EIFS, erp->eifs);
630 rt2x00pci_register_write(rt2x00dev, MAC_CSR8, reg);
95ea3627
ID		 631}
632
633static void rt61pci_config_antenna_5x(struct rt2x00_dev *rt2x00dev,
addc81bd 634 struct antenna_setup *ant)
95ea3627
ID		 635{
636 u8 r3;
637 u8 r4;
638 u8 r77;
639
640 rt61pci_bbp_read(rt2x00dev, 3, &r3);
641 rt61pci_bbp_read(rt2x00dev, 4, &r4);
642 rt61pci_bbp_read(rt2x00dev, 77, &r77);
643
644 rt2x00_set_field8(&r3, BBP_R3_SMART_MODE,
acaa410d 645 rt2x00_rf(&rt2x00dev->chip, RF5325));
e4cd2ff8
ID		 646
647 /*
648 * Configure the RX antenna.
649 */
addc81bd 650 switch (ant->rx) {
95ea3627 651 case ANTENNA_HW_DIVERSITY:
acaa410d 652 rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA_CONTROL, 2);
95ea3627 653 rt2x00_set_field8(&r4, BBP_R4_RX_FRAME_END,
8318d78a 654 (rt2x00dev->curr_band != IEEE80211_BAND_5GHZ));
95ea3627
ID		 655 break;
656 case ANTENNA_A:
acaa410d 657 rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA_CONTROL, 1);
95ea3627 658 rt2x00_set_field8(&r4, BBP_R4_RX_FRAME_END, 0);
8318d78a 659 if (rt2x00dev->curr_band == IEEE80211_BAND_5GHZ)
acaa410d
MN		 660 rt2x00_set_field8(&r77, BBP_R77_RX_ANTENNA, 0);
661 else
662 rt2x00_set_field8(&r77, BBP_R77_RX_ANTENNA, 3);
95ea3627
ID		 663 break;
664 case ANTENNA_B:
a4fe07d9 665 default:
acaa410d 666 rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA_CONTROL, 1);
95ea3627 667 rt2x00_set_field8(&r4, BBP_R4_RX_FRAME_END, 0);
8318d78a 668 if (rt2x00dev->curr_band == IEEE80211_BAND_5GHZ)
acaa410d
MN		 669 rt2x00_set_field8(&r77, BBP_R77_RX_ANTENNA, 3);
670 else
671 rt2x00_set_field8(&r77, BBP_R77_RX_ANTENNA, 0);
95ea3627
ID		 672 break;
673 }
674
675 rt61pci_bbp_write(rt2x00dev, 77, r77);
676 rt61pci_bbp_write(rt2x00dev, 3, r3);
677 rt61pci_bbp_write(rt2x00dev, 4, r4);
678}
679
680static void rt61pci_config_antenna_2x(struct rt2x00_dev *rt2x00dev,
addc81bd 681 struct antenna_setup *ant)
95ea3627
ID		 682{
683 u8 r3;
684 u8 r4;
685 u8 r77;
686
687 rt61pci_bbp_read(rt2x00dev, 3, &r3);
688 rt61pci_bbp_read(rt2x00dev, 4, &r4);
689 rt61pci_bbp_read(rt2x00dev, 77, &r77);
690
691 rt2x00_set_field8(&r3, BBP_R3_SMART_MODE,
acaa410d 692 rt2x00_rf(&rt2x00dev->chip, RF2529));
95ea3627
ID		 693 rt2x00_set_field8(&r4, BBP_R4_RX_FRAME_END,
694 !test_bit(CONFIG_FRAME_TYPE, &rt2x00dev->flags));
695
e4cd2ff8
ID		 696 /*
697 * Configure the RX antenna.
698 */
addc81bd 699 switch (ant->rx) {
95ea3627 700 case ANTENNA_HW_DIVERSITY:
acaa410d 701 rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA_CONTROL, 2);
95ea3627
ID		 702 break;
703 case ANTENNA_A:
acaa410d
MN		 704 rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA_CONTROL, 1);
705 rt2x00_set_field8(&r77, BBP_R77_RX_ANTENNA, 3);
95ea3627
ID		 706 break;
707 case ANTENNA_B:
a4fe07d9 708 default:
acaa410d
MN		 709 rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA_CONTROL, 1);
710 rt2x00_set_field8(&r77, BBP_R77_RX_ANTENNA, 0);
95ea3627
ID		 711 break;
712 }
713
714 rt61pci_bbp_write(rt2x00dev, 77, r77);
715 rt61pci_bbp_write(rt2x00dev, 3, r3);
716 rt61pci_bbp_write(rt2x00dev, 4, r4);
717}
718
719static void rt61pci_config_antenna_2529_rx(struct rt2x00_dev *rt2x00dev,
720 const int p1, const int p2)
721{
722 u32 reg;
723
724 rt2x00pci_register_read(rt2x00dev, MAC_CSR13, &reg);
725
acaa410d
MN		 726 rt2x00_set_field32(&reg, MAC_CSR13_BIT4, p1);
727 rt2x00_set_field32(&reg, MAC_CSR13_BIT12, 0);
728
729 rt2x00_set_field32(&reg, MAC_CSR13_BIT3, !p2);
730 rt2x00_set_field32(&reg, MAC_CSR13_BIT11, 0);
731
732 rt2x00pci_register_write(rt2x00dev, MAC_CSR13, reg);
95ea3627
ID		 733}
734
735static void rt61pci_config_antenna_2529(struct rt2x00_dev *rt2x00dev,
addc81bd 736 struct antenna_setup *ant)
95ea3627 737{
95ea3627
ID		 738 u8 r3;
739 u8 r4;
740 u8 r77;
741
742 rt61pci_bbp_read(rt2x00dev, 3, &r3);
743 rt61pci_bbp_read(rt2x00dev, 4, &r4);
744 rt61pci_bbp_read(rt2x00dev, 77, &r77);
e4cd2ff8 745
e4cd2ff8
ID		 746 /*
747 * Configure the RX antenna.
748 */
749 switch (ant->rx) {
750 case ANTENNA_A:
acaa410d
MN		 751 rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA_CONTROL, 1);
752 rt2x00_set_field8(&r77, BBP_R77_RX_ANTENNA, 0);
753 rt61pci_config_antenna_2529_rx(rt2x00dev, 0, 0);
e4cd2ff8 754 break;
e4cd2ff8
ID		 755 case ANTENNA_HW_DIVERSITY:
756 /*
a4fe07d9
ID		 757 * FIXME: Antenna selection for the rf 2529 is very confusing
758 * in the legacy driver. Just default to antenna B until the
759 * legacy code can be properly translated into rt2x00 code.
e4cd2ff8
ID		 760 */
761 case ANTENNA_B:
a4fe07d9 762 default:
acaa410d
MN		 763 rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA_CONTROL, 1);
764 rt2x00_set_field8(&r77, BBP_R77_RX_ANTENNA, 3);
765 rt61pci_config_antenna_2529_rx(rt2x00dev, 1, 1);
e4cd2ff8
ID		 766 break;
767 }
768
e4cd2ff8 769 rt61pci_bbp_write(rt2x00dev, 77, r77);
95ea3627
ID		 770 rt61pci_bbp_write(rt2x00dev, 3, r3);
771 rt61pci_bbp_write(rt2x00dev, 4, r4);
772}
773
774struct antenna_sel {
775 u8 word;
776 /*
777 * value[0] -> non-LNA
778 * value[1] -> LNA
779 */
780 u8 value[2];
781};
782
783static const struct antenna_sel antenna_sel_a[] = {
784 { 96, { 0x58, 0x78 } },
785 { 104, { 0x38, 0x48 } },
786 { 75, { 0xfe, 0x80 } },
787 { 86, { 0xfe, 0x80 } },
788 { 88, { 0xfe, 0x80 } },
789 { 35, { 0x60, 0x60 } },
790 { 97, { 0x58, 0x58 } },
791 { 98, { 0x58, 0x58 } },
792};
793
794static const struct antenna_sel antenna_sel_bg[] = {
795 { 96, { 0x48, 0x68 } },
796 { 104, { 0x2c, 0x3c } },
797 { 75, { 0xfe, 0x80 } },
798 { 86, { 0xfe, 0x80 } },
799 { 88, { 0xfe, 0x80 } },
800 { 35, { 0x50, 0x50 } },
801 { 97, { 0x48, 0x48 } },
802 { 98, { 0x48, 0x48 } },
803};
804
e4ea1c40
ID		 805static void rt61pci_config_ant(struct rt2x00_dev *rt2x00dev,
806 struct antenna_setup *ant)
95ea3627
ID		 807{
808 const struct antenna_sel *sel;
809 unsigned int lna;
810 unsigned int i;
811 u32 reg;
812
a4fe07d9
ID		 813 /*
814 * We should never come here because rt2x00lib is supposed
815 * to catch this and send us the correct antenna explicitely.
816 */
817 BUG_ON(ant->rx == ANTENNA_SW_DIVERSITY ||
818 ant->tx == ANTENNA_SW_DIVERSITY);
819
8318d78a 820 if (rt2x00dev->curr_band == IEEE80211_BAND_5GHZ) {
95ea3627
ID		 821 sel = antenna_sel_a;
822 lna = test_bit(CONFIG_EXTERNAL_LNA_A, &rt2x00dev->flags);
95ea3627
ID		 823 } else {
824 sel = antenna_sel_bg;
825 lna = test_bit(CONFIG_EXTERNAL_LNA_BG, &rt2x00dev->flags);
95ea3627
ID		 826 }
827
acaa410d
MN		 828 for (i = 0; i < ARRAY_SIZE(antenna_sel_a); i++)
829 rt61pci_bbp_write(rt2x00dev, sel[i].word, sel[i].value[lna]);
830
831 rt2x00pci_register_read(rt2x00dev, PHY_CSR0, &reg);
832
ddc827f9 833 rt2x00_set_field32(&reg, PHY_CSR0_PA_PE_BG,
8318d78a 834 rt2x00dev->curr_band == IEEE80211_BAND_2GHZ);
ddc827f9 835 rt2x00_set_field32(&reg, PHY_CSR0_PA_PE_A,
8318d78a 836 rt2x00dev->curr_band == IEEE80211_BAND_5GHZ);
ddc827f9 837
95ea3627
ID		 838 rt2x00pci_register_write(rt2x00dev, PHY_CSR0, reg);
839
840 if (rt2x00_rf(&rt2x00dev->chip, RF5225) ||
841 rt2x00_rf(&rt2x00dev->chip, RF5325))
addc81bd 842 rt61pci_config_antenna_5x(rt2x00dev, ant);
95ea3627 843 else if (rt2x00_rf(&rt2x00dev->chip, RF2527))
addc81bd 844 rt61pci_config_antenna_2x(rt2x00dev, ant);
95ea3627
ID		 845 else if (rt2x00_rf(&rt2x00dev->chip, RF2529)) {
846 if (test_bit(CONFIG_DOUBLE_ANTENNA, &rt2x00dev->flags))
addc81bd 847 rt61pci_config_antenna_2x(rt2x00dev, ant);
95ea3627 848 else
addc81bd 849 rt61pci_config_antenna_2529(rt2x00dev, ant);
95ea3627
ID		 850 }
851}
852
e4ea1c40
ID		 853static void rt61pci_config_lna_gain(struct rt2x00_dev *rt2x00dev,
854 struct rt2x00lib_conf *libconf)
855{
856 u16 eeprom;
857 short lna_gain = 0;
858
859 if (libconf->conf->channel->band == IEEE80211_BAND_2GHZ) {
860 if (test_bit(CONFIG_EXTERNAL_LNA_BG, &rt2x00dev->flags))
861 lna_gain += 14;
862
863 rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_OFFSET_BG, &eeprom);
864 lna_gain -= rt2x00_get_field16(eeprom, EEPROM_RSSI_OFFSET_BG_1);
865 } else {
866 if (test_bit(CONFIG_EXTERNAL_LNA_A, &rt2x00dev->flags))
867 lna_gain += 14;
868
869 rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_OFFSET_A, &eeprom);
870 lna_gain -= rt2x00_get_field16(eeprom, EEPROM_RSSI_OFFSET_A_1);
871 }
872
873 rt2x00dev->lna_gain = lna_gain;
874}
875
876static void rt61pci_config_channel(struct rt2x00_dev *rt2x00dev,
877 struct rf_channel *rf, const int txpower)
878{
879 u8 r3;
880 u8 r94;
881 u8 smart;
882
883 rt2x00_set_field32(&rf->rf3, RF3_TXPOWER, TXPOWER_TO_DEV(txpower));
884 rt2x00_set_field32(&rf->rf4, RF4_FREQ_OFFSET, rt2x00dev->freq_offset);
885
886 smart = !(rt2x00_rf(&rt2x00dev->chip, RF5225) ||
887 rt2x00_rf(&rt2x00dev->chip, RF2527));
888
889 rt61pci_bbp_read(rt2x00dev, 3, &r3);
890 rt2x00_set_field8(&r3, BBP_R3_SMART_MODE, smart);
891 rt61pci_bbp_write(rt2x00dev, 3, r3);
892
893 r94 = 6;
894 if (txpower > MAX_TXPOWER && txpower <= (MAX_TXPOWER + r94))
895 r94 += txpower - MAX_TXPOWER;
896 else if (txpower < MIN_TXPOWER && txpower >= (MIN_TXPOWER - r94))
897 r94 += txpower;
898 rt61pci_bbp_write(rt2x00dev, 94, r94);
899
900 rt61pci_rf_write(rt2x00dev, 1, rf->rf1);
901 rt61pci_rf_write(rt2x00dev, 2, rf->rf2);
902 rt61pci_rf_write(rt2x00dev, 3, rf->rf3 & ~0x00000004);
903 rt61pci_rf_write(rt2x00dev, 4, rf->rf4);
904
905 udelay(200);
906
907 rt61pci_rf_write(rt2x00dev, 1, rf->rf1);
908 rt61pci_rf_write(rt2x00dev, 2, rf->rf2);
909 rt61pci_rf_write(rt2x00dev, 3, rf->rf3 | 0x00000004);
910 rt61pci_rf_write(rt2x00dev, 4, rf->rf4);
911
912 udelay(200);
913
914 rt61pci_rf_write(rt2x00dev, 1, rf->rf1);
915 rt61pci_rf_write(rt2x00dev, 2, rf->rf2);
916 rt61pci_rf_write(rt2x00dev, 3, rf->rf3 & ~0x00000004);
917 rt61pci_rf_write(rt2x00dev, 4, rf->rf4);
918
919 msleep(1);
920}
921
922static void rt61pci_config_txpower(struct rt2x00_dev *rt2x00dev,
923 const int txpower)
924{
925 struct rf_channel rf;
926
927 rt2x00_rf_read(rt2x00dev, 1, &rf.rf1);
928 rt2x00_rf_read(rt2x00dev, 2, &rf.rf2);
929 rt2x00_rf_read(rt2x00dev, 3, &rf.rf3);
930 rt2x00_rf_read(rt2x00dev, 4, &rf.rf4);
931
932 rt61pci_config_channel(rt2x00dev, &rf, txpower);
933}
934
935static void rt61pci_config_retry_limit(struct rt2x00_dev *rt2x00dev,
5c58ee51 936 struct rt2x00lib_conf *libconf)
95ea3627
ID		 937{
938 u32 reg;
939
e4ea1c40
ID		 940 rt2x00pci_register_read(rt2x00dev, TXRX_CSR4, &reg);
941 rt2x00_set_field32(&reg, TXRX_CSR4_LONG_RETRY_LIMIT,
942 libconf->conf->long_frame_max_tx_count);
943 rt2x00_set_field32(&reg, TXRX_CSR4_SHORT_RETRY_LIMIT,
944 libconf->conf->short_frame_max_tx_count);
945 rt2x00pci_register_write(rt2x00dev, TXRX_CSR4, reg);
946}
95ea3627 947
7d7f19cc
ID		 948static void rt61pci_config_ps(struct rt2x00_dev *rt2x00dev,
949 struct rt2x00lib_conf *libconf)
950{
951 enum dev_state state =
952 (libconf->conf->flags & IEEE80211_CONF_PS) ?
953 STATE_SLEEP : STATE_AWAKE;
954 u32 reg;
955
956 if (state == STATE_SLEEP) {
957 rt2x00pci_register_read(rt2x00dev, MAC_CSR11, &reg);
958 rt2x00_set_field32(&reg, MAC_CSR11_DELAY_AFTER_TBCN,
6b347bff 959 rt2x00dev->beacon_int - 10);
7d7f19cc
ID		 960 rt2x00_set_field32(&reg, MAC_CSR11_TBCN_BEFORE_WAKEUP,
961 libconf->conf->listen_interval - 1);
962 rt2x00_set_field32(&reg, MAC_CSR11_WAKEUP_LATENCY, 5);
963
964 /* We must first disable autowake before it can be enabled */
965 rt2x00_set_field32(&reg, MAC_CSR11_AUTOWAKE, 0);
966 rt2x00pci_register_write(rt2x00dev, MAC_CSR11, reg);
967
968 rt2x00_set_field32(&reg, MAC_CSR11_AUTOWAKE, 1);
969 rt2x00pci_register_write(rt2x00dev, MAC_CSR11, reg);
970
971 rt2x00pci_register_write(rt2x00dev, SOFT_RESET_CSR, 0x00000005);
972 rt2x00pci_register_write(rt2x00dev, IO_CNTL_CSR, 0x0000001c);
973 rt2x00pci_register_write(rt2x00dev, PCI_USEC_CSR, 0x00000060);
974
975 rt61pci_mcu_request(rt2x00dev, MCU_SLEEP, 0xff, 0, 0);
976 } else {
977 rt2x00pci_register_read(rt2x00dev, MAC_CSR11, &reg);
978 rt2x00_set_field32(&reg, MAC_CSR11_DELAY_AFTER_TBCN, 0);
979 rt2x00_set_field32(&reg, MAC_CSR11_TBCN_BEFORE_WAKEUP, 0);
980 rt2x00_set_field32(&reg, MAC_CSR11_AUTOWAKE, 0);
981 rt2x00_set_field32(&reg, MAC_CSR11_WAKEUP_LATENCY, 0);
982 rt2x00pci_register_write(rt2x00dev, MAC_CSR11, reg);
983
984 rt2x00pci_register_write(rt2x00dev, SOFT_RESET_CSR, 0x00000007);
985 rt2x00pci_register_write(rt2x00dev, IO_CNTL_CSR, 0x00000018);
986 rt2x00pci_register_write(rt2x00dev, PCI_USEC_CSR, 0x00000020);
987
988 rt61pci_mcu_request(rt2x00dev, MCU_WAKEUP, 0xff, 0, 0);
989 }
990}
991
95ea3627 992static void rt61pci_config(struct rt2x00_dev *rt2x00dev,
6bb40dd1
ID		 993 struct rt2x00lib_conf *libconf,
994 const unsigned int flags)
95ea3627 995{
ba2ab471
ID		 996 /* Always recalculate LNA gain before changing configuration */
997 rt61pci_config_lna_gain(rt2x00dev, libconf);
998
e4ea1c40 999 if (flags & IEEE80211_CONF_CHANGE_CHANNEL)
5c58ee51
ID		 1000 rt61pci_config_channel(rt2x00dev, &libconf->rf,
1001 libconf->conf->power_level);
e4ea1c40
ID		 1002 if ((flags & IEEE80211_CONF_CHANGE_POWER) &&
1003 !(flags & IEEE80211_CONF_CHANGE_CHANNEL))
5c58ee51 1004 rt61pci_config_txpower(rt2x00dev, libconf->conf->power_level);
e4ea1c40
ID		 1005 if (flags & IEEE80211_CONF_CHANGE_RETRY_LIMITS)
1006 rt61pci_config_retry_limit(rt2x00dev, libconf);
7d7f19cc
ID		 1007 if (flags & IEEE80211_CONF_CHANGE_PS)
1008 rt61pci_config_ps(rt2x00dev, libconf);
95ea3627
ID		 1009}
1010
95ea3627
ID		 1011/*
1012 * Link tuning
1013 */
ebcf26da
ID		 1014static void rt61pci_link_stats(struct rt2x00_dev *rt2x00dev,
1015 struct link_qual *qual)
95ea3627
ID		 1016{
1017 u32 reg;
1018
1019 /*
1020 * Update FCS error count from register.
1021 */
1022 rt2x00pci_register_read(rt2x00dev, STA_CSR0, &reg);
ebcf26da 1023 qual->rx_failed = rt2x00_get_field32(reg, STA_CSR0_FCS_ERROR);
95ea3627
ID		 1024
1025 /*
1026 * Update False CCA count from register.
1027 */
1028 rt2x00pci_register_read(rt2x00dev, STA_CSR1, &reg);
ebcf26da 1029 qual->false_cca = rt2x00_get_field32(reg, STA_CSR1_FALSE_CCA_ERROR);
95ea3627
ID		 1030}
1031
5352ff65
ID		 1032static inline void rt61pci_set_vgc(struct rt2x00_dev *rt2x00dev,
1033 struct link_qual *qual, u8 vgc_level)
eb20b4e8 1034{
5352ff65 1035 if (qual->vgc_level != vgc_level) {
eb20b4e8 1036 rt61pci_bbp_write(rt2x00dev, 17, vgc_level);
5352ff65
ID		 1037 qual->vgc_level = vgc_level;
1038 qual->vgc_level_reg = vgc_level;
eb20b4e8
ID		 1039 }
1040}
1041
5352ff65
ID		 1042static void rt61pci_reset_tuner(struct rt2x00_dev *rt2x00dev,
1043 struct link_qual *qual)
95ea3627 1044{
5352ff65 1045 rt61pci_set_vgc(rt2x00dev, qual, 0x20);
95ea3627
ID		 1046}
1047
5352ff65
ID		 1048static void rt61pci_link_tuner(struct rt2x00_dev *rt2x00dev,
1049 struct link_qual *qual, const u32 count)
95ea3627 1050{
95ea3627
ID		 1051 u8 up_bound;
1052 u8 low_bound;
1053
95ea3627
ID		 1054 /*
1055 * Determine r17 bounds.
1056 */
1497074a 1057 if (rt2x00dev->rx_status.band == IEEE80211_BAND_5GHZ) {
95ea3627
ID		 1058 low_bound = 0x28;
1059 up_bound = 0x48;
1060 if (test_bit(CONFIG_EXTERNAL_LNA_A, &rt2x00dev->flags)) {
1061 low_bound += 0x10;
1062 up_bound += 0x10;
1063 }
1064 } else {
1065 low_bound = 0x20;
1066 up_bound = 0x40;
1067 if (test_bit(CONFIG_EXTERNAL_LNA_BG, &rt2x00dev->flags)) {
1068 low_bound += 0x10;
1069 up_bound += 0x10;
1070 }
1071 }
1072
6bb40dd1
ID		 1073 /*
1074 * If we are not associated, we should go straight to the
1075 * dynamic CCA tuning.
1076 */
1077 if (!rt2x00dev->intf_associated)
1078 goto dynamic_cca_tune;
1079
95ea3627
ID		 1080 /*
1081 * Special big-R17 for very short distance
1082 */
5352ff65
ID		 1083 if (qual->rssi >= -35) {
1084 rt61pci_set_vgc(rt2x00dev, qual, 0x60);
95ea3627
ID		 1085 return;
1086 }
1087
1088 /*
1089 * Special big-R17 for short distance
1090 */
5352ff65
ID		 1091 if (qual->rssi >= -58) {
1092 rt61pci_set_vgc(rt2x00dev, qual, up_bound);
95ea3627
ID		 1093 return;
1094 }
1095
1096 /*
1097 * Special big-R17 for middle-short distance
1098 */
5352ff65
ID		 1099 if (qual->rssi >= -66) {
1100 rt61pci_set_vgc(rt2x00dev, qual, low_bound + 0x10);
95ea3627
ID		 1101 return;
1102 }
1103
1104 /*
1105 * Special mid-R17 for middle distance
1106 */
5352ff65
ID		 1107 if (qual->rssi >= -74) {
1108 rt61pci_set_vgc(rt2x00dev, qual, low_bound + 0x08);
95ea3627
ID		 1109 return;
1110 }
1111
1112 /*
1113 * Special case: Change up_bound based on the rssi.
1114 * Lower up_bound when rssi is weaker then -74 dBm.
1115 */
5352ff65 1116 up_bound -= 2 * (-74 - qual->rssi);
95ea3627
ID		 1117 if (low_bound > up_bound)
1118 up_bound = low_bound;
1119
5352ff65
ID		 1120 if (qual->vgc_level > up_bound) {
1121 rt61pci_set_vgc(rt2x00dev, qual, up_bound);
95ea3627
ID		 1122 return;
1123 }
1124
6bb40dd1
ID		 1125dynamic_cca_tune:
1126
95ea3627
ID		 1127 /*
1128 * r17 does not yet exceed upper limit, continue and base
1129 * the r17 tuning on the false CCA count.
1130 */
5352ff65
ID		 1131 if ((qual->false_cca > 512) && (qual->vgc_level < up_bound))
1132 rt61pci_set_vgc(rt2x00dev, qual, ++qual->vgc_level);
1133 else if ((qual->false_cca < 100) && (qual->vgc_level > low_bound))
1134 rt61pci_set_vgc(rt2x00dev, qual, --qual->vgc_level);
95ea3627
ID		 1135}
1136
1137/*
a7f3a06c 1138 * Firmware functions
95ea3627
ID		 1139 */
1140static char *rt61pci_get_firmware_name(struct rt2x00_dev *rt2x00dev)
1141{
1142 char *fw_name;
1143
1144 switch (rt2x00dev->chip.rt) {
1145 case RT2561:
1146 fw_name = FIRMWARE_RT2561;
1147 break;
1148 case RT2561s:
1149 fw_name = FIRMWARE_RT2561s;
1150 break;
1151 case RT2661:
1152 fw_name = FIRMWARE_RT2661;
1153 break;
1154 default:
1155 fw_name = NULL;
1156 break;
1157 }
1158
1159 return fw_name;
1160}
1161
0cbe0064
ID		 1162static int rt61pci_check_firmware(struct rt2x00_dev *rt2x00dev,
1163 const u8 *data, const size_t len)
a7f3a06c 1164{
0cbe0064 1165 u16 fw_crc;
a7f3a06c
ID		 1166 u16 crc;
1167
1168 /*
0cbe0064
ID		 1169 * Only support 8kb firmware files.
1170 */
1171 if (len != 8192)
1172 return FW_BAD_LENGTH;
1173
1174 /*
a7f3a06c
ID		 1175 * The last 2 bytes in the firmware array are the crc checksum itself,
1176 * this means that we should never pass those 2 bytes to the crc
1177 * algorithm.
1178 */
0cbe0064
ID		 1179 fw_crc = (data[len - 2] << 8 | data[len - 1]);
1180
1181 /*
1182 * Use the crc itu-t algorithm.
1183 */
a7f3a06c
ID		 1184 crc = crc_itu_t(0, data, len - 2);
1185 crc = crc_itu_t_byte(crc, 0);
1186 crc = crc_itu_t_byte(crc, 0);
1187
0cbe0064 1188 return (fw_crc == crc) ? FW_OK : FW_BAD_CRC;
a7f3a06c
ID		 1189}
1190
0cbe0064
ID		 1191static int rt61pci_load_firmware(struct rt2x00_dev *rt2x00dev,
1192 const u8 *data, const size_t len)
95ea3627
ID		 1193{
1194 int i;
1195 u32 reg;
1196
1197 /*
1198 * Wait for stable hardware.
1199 */
1200 for (i = 0; i < 100; i++) {
1201 rt2x00pci_register_read(rt2x00dev, MAC_CSR0, &reg);
1202 if (reg)
1203 break;
1204 msleep(1);
1205 }
1206
1207 if (!reg) {
1208 ERROR(rt2x00dev, "Unstable hardware.\n");
1209 return -EBUSY;
1210 }
1211
1212 /*
1213 * Prepare MCU and mailbox for firmware loading.
1214 */
1215 reg = 0;
1216 rt2x00_set_field32(&reg, MCU_CNTL_CSR_RESET, 1);
1217 rt2x00pci_register_write(rt2x00dev, MCU_CNTL_CSR, reg);
1218 rt2x00pci_register_write(rt2x00dev, M2H_CMD_DONE_CSR, 0xffffffff);
1219 rt2x00pci_register_write(rt2x00dev, H2M_MAILBOX_CSR, 0);
1220 rt2x00pci_register_write(rt2x00dev, HOST_CMD_CSR, 0);
1221
1222 /*
1223 * Write firmware to device.
1224 */
1225 reg = 0;
1226 rt2x00_set_field32(&reg, MCU_CNTL_CSR_RESET, 1);
1227 rt2x00_set_field32(&reg, MCU_CNTL_CSR_SELECT_BANK, 1);
1228 rt2x00pci_register_write(rt2x00dev, MCU_CNTL_CSR, reg);
1229
1230 rt2x00pci_register_multiwrite(rt2x00dev, FIRMWARE_IMAGE_BASE,
1231 data, len);
1232
1233 rt2x00_set_field32(&reg, MCU_CNTL_CSR_SELECT_BANK, 0);
1234 rt2x00pci_register_write(rt2x00dev, MCU_CNTL_CSR, reg);
1235
1236 rt2x00_set_field32(&reg, MCU_CNTL_CSR_RESET, 0);
1237 rt2x00pci_register_write(rt2x00dev, MCU_CNTL_CSR, reg);
1238
1239 for (i = 0; i < 100; i++) {
1240 rt2x00pci_register_read(rt2x00dev, MCU_CNTL_CSR, &reg);
1241 if (rt2x00_get_field32(reg, MCU_CNTL_CSR_READY))
1242 break;
1243 msleep(1);
1244 }
1245
1246 if (i == 100) {
1247 ERROR(rt2x00dev, "MCU Control register not ready.\n");
1248 return -EBUSY;
1249 }
1250
e6d3e902
ID		 1251 /*
1252 * Hardware needs another millisecond before it is ready.
1253 */
1254 msleep(1);
1255
95ea3627
ID		 1256 /*
1257 * Reset MAC and BBP registers.
1258 */
1259 reg = 0;
1260 rt2x00_set_field32(&reg, MAC_CSR1_SOFT_RESET, 1);
1261 rt2x00_set_field32(&reg, MAC_CSR1_BBP_RESET, 1);
1262 rt2x00pci_register_write(rt2x00dev, MAC_CSR1, reg);
1263
1264 rt2x00pci_register_read(rt2x00dev, MAC_CSR1, &reg);
1265 rt2x00_set_field32(&reg, MAC_CSR1_SOFT_RESET, 0);
1266 rt2x00_set_field32(&reg, MAC_CSR1_BBP_RESET, 0);
1267 rt2x00pci_register_write(rt2x00dev, MAC_CSR1, reg);
1268
1269 rt2x00pci_register_read(rt2x00dev, MAC_CSR1, &reg);
1270 rt2x00_set_field32(&reg, MAC_CSR1_HOST_READY, 1);
1271 rt2x00pci_register_write(rt2x00dev, MAC_CSR1, reg);
1272
1273 return 0;
1274}
1275
a7f3a06c
ID		 1276/*
1277 * Initialization functions.
1278 */
798b7adb 1279static bool rt61pci_get_entry_state(struct queue_entry *entry)
95ea3627 1280{
b8be63ff 1281 struct queue_entry_priv_pci *entry_priv = entry->priv_data;
95ea3627
ID		 1282 u32 word;
1283
798b7adb
ID		 1284 if (entry->queue->qid == QID_RX) {
1285 rt2x00_desc_read(entry_priv->desc, 0, &word);
95ea3627 1286
798b7adb
ID		 1287 return rt2x00_get_field32(word, RXD_W0_OWNER_NIC);
1288 } else {
1289 rt2x00_desc_read(entry_priv->desc, 0, &word);
1290
1291 return (rt2x00_get_field32(word, TXD_W0_OWNER_NIC) ||
1292 rt2x00_get_field32(word, TXD_W0_VALID));
1293 }
95ea3627
ID		 1294}
1295
798b7adb 1296static void rt61pci_clear_entry(struct queue_entry *entry)
95ea3627 1297{
b8be63ff 1298 struct queue_entry_priv_pci *entry_priv = entry->priv_data;
798b7adb 1299 struct skb_frame_desc *skbdesc = get_skb_frame_desc(entry->skb);
95ea3627
ID		 1300 u32 word;
1301
798b7adb
ID		 1302 if (entry->queue->qid == QID_RX) {
1303 rt2x00_desc_read(entry_priv->desc, 5, &word);
1304 rt2x00_set_field32(&word, RXD_W5_BUFFER_PHYSICAL_ADDRESS,
1305 skbdesc->skb_dma);
1306 rt2x00_desc_write(entry_priv->desc, 5, word);
1307
1308 rt2x00_desc_read(entry_priv->desc, 0, &word);
1309 rt2x00_set_field32(&word, RXD_W0_OWNER_NIC, 1);
1310 rt2x00_desc_write(entry_priv->desc, 0, word);
1311 } else {
1312 rt2x00_desc_read(entry_priv->desc, 0, &word);
1313 rt2x00_set_field32(&word, TXD_W0_VALID, 0);
1314 rt2x00_set_field32(&word, TXD_W0_OWNER_NIC, 0);
1315 rt2x00_desc_write(entry_priv->desc, 0, word);
1316 }
95ea3627
ID		 1317}
1318
181d6902 1319static int rt61pci_init_queues(struct rt2x00_dev *rt2x00dev)
95ea3627 1320{
b8be63ff 1321 struct queue_entry_priv_pci *entry_priv;
95ea3627
ID		 1322 u32 reg;
1323
95ea3627
ID		 1324 /*
1325 * Initialize registers.
1326 */
1327 rt2x00pci_register_read(rt2x00dev, TX_RING_CSR0, &reg);
1328 rt2x00_set_field32(&reg, TX_RING_CSR0_AC0_RING_SIZE,
181d6902 1329 rt2x00dev->tx[0].limit);
95ea3627 1330 rt2x00_set_field32(&reg, TX_RING_CSR0_AC1_RING_SIZE,
181d6902 1331 rt2x00dev->tx[1].limit);
95ea3627 1332 rt2x00_set_field32(&reg, TX_RING_CSR0_AC2_RING_SIZE,
181d6902 1333 rt2x00dev->tx[2].limit);
95ea3627 1334 rt2x00_set_field32(&reg, TX_RING_CSR0_AC3_RING_SIZE,
181d6902 1335 rt2x00dev->tx[3].limit);
95ea3627
ID		 1336 rt2x00pci_register_write(rt2x00dev, TX_RING_CSR0, reg);
1337
1338 rt2x00pci_register_read(rt2x00dev, TX_RING_CSR1, &reg);
95ea3627 1339 rt2x00_set_field32(&reg, TX_RING_CSR1_TXD_SIZE,
181d6902 1340 rt2x00dev->tx[0].desc_size / 4);
95ea3627
ID		 1341 rt2x00pci_register_write(rt2x00dev, TX_RING_CSR1, reg);
1342
b8be63ff 1343 entry_priv = rt2x00dev->tx[0].entries[0].priv_data;
95ea3627 1344 rt2x00pci_register_read(rt2x00dev, AC0_BASE_CSR, &reg);
30b3a23c 1345 rt2x00_set_field32(&reg, AC0_BASE_CSR_RING_REGISTER,
b8be63ff 1346 entry_priv->desc_dma);
95ea3627
ID		 1347 rt2x00pci_register_write(rt2x00dev, AC0_BASE_CSR, reg);
1348
b8be63ff 1349 entry_priv = rt2x00dev->tx[1].entries[0].priv_data;
95ea3627 1350 rt2x00pci_register_read(rt2x00dev, AC1_BASE_CSR, &reg);
30b3a23c 1351 rt2x00_set_field32(&reg, AC1_BASE_CSR_RING_REGISTER,
b8be63ff 1352 entry_priv->desc_dma);
95ea3627
ID		 1353 rt2x00pci_register_write(rt2x00dev, AC1_BASE_CSR, reg);
1354
b8be63ff 1355 entry_priv = rt2x00dev->tx[2].entries[0].priv_data;
95ea3627 1356 rt2x00pci_register_read(rt2x00dev, AC2_BASE_CSR, &reg);
30b3a23c 1357 rt2x00_set_field32(&reg, AC2_BASE_CSR_RING_REGISTER,
b8be63ff 1358 entry_priv->desc_dma);
95ea3627
ID		 1359 rt2x00pci_register_write(rt2x00dev, AC2_BASE_CSR, reg);
1360
b8be63ff 1361 entry_priv = rt2x00dev->tx[3].entries[0].priv_data;
95ea3627 1362 rt2x00pci_register_read(rt2x00dev, AC3_BASE_CSR, &reg);
30b3a23c 1363 rt2x00_set_field32(&reg, AC3_BASE_CSR_RING_REGISTER,
b8be63ff 1364 entry_priv->desc_dma);
95ea3627
ID		 1365 rt2x00pci_register_write(rt2x00dev, AC3_BASE_CSR, reg);
1366
95ea3627 1367 rt2x00pci_register_read(rt2x00dev, RX_RING_CSR, &reg);
181d6902 1368 rt2x00_set_field32(&reg, RX_RING_CSR_RING_SIZE, rt2x00dev->rx->limit);
95ea3627
ID		 1369 rt2x00_set_field32(&reg, RX_RING_CSR_RXD_SIZE,
1370 rt2x00dev->rx->desc_size / 4);
1371 rt2x00_set_field32(&reg, RX_RING_CSR_RXD_WRITEBACK_SIZE, 4);
1372 rt2x00pci_register_write(rt2x00dev, RX_RING_CSR, reg);
1373
b8be63ff 1374 entry_priv = rt2x00dev->rx->entries[0].priv_data;
95ea3627 1375 rt2x00pci_register_read(rt2x00dev, RX_BASE_CSR, &reg);
30b3a23c 1376 rt2x00_set_field32(&reg, RX_BASE_CSR_RING_REGISTER,
b8be63ff 1377 entry_priv->desc_dma);
95ea3627
ID		 1378 rt2x00pci_register_write(rt2x00dev, RX_BASE_CSR, reg);
1379
1380 rt2x00pci_register_read(rt2x00dev, TX_DMA_DST_CSR, &reg);
1381 rt2x00_set_field32(&reg, TX_DMA_DST_CSR_DEST_AC0, 2);
1382 rt2x00_set_field32(&reg, TX_DMA_DST_CSR_DEST_AC1, 2);
1383 rt2x00_set_field32(&reg, TX_DMA_DST_CSR_DEST_AC2, 2);
1384 rt2x00_set_field32(&reg, TX_DMA_DST_CSR_DEST_AC3, 2);
95ea3627
ID		 1385 rt2x00pci_register_write(rt2x00dev, TX_DMA_DST_CSR, reg);
1386
1387 rt2x00pci_register_read(rt2x00dev, LOAD_TX_RING_CSR, &reg);
1388 rt2x00_set_field32(&reg, LOAD_TX_RING_CSR_LOAD_TXD_AC0, 1);
1389 rt2x00_set_field32(&reg, LOAD_TX_RING_CSR_LOAD_TXD_AC1, 1);
1390 rt2x00_set_field32(&reg, LOAD_TX_RING_CSR_LOAD_TXD_AC2, 1);
1391 rt2x00_set_field32(&reg, LOAD_TX_RING_CSR_LOAD_TXD_AC3, 1);
95ea3627
ID		 1392 rt2x00pci_register_write(rt2x00dev, LOAD_TX_RING_CSR, reg);
1393
1394 rt2x00pci_register_read(rt2x00dev, RX_CNTL_CSR, &reg);
1395 rt2x00_set_field32(&reg, RX_CNTL_CSR_LOAD_RXD, 1);
1396 rt2x00pci_register_write(rt2x00dev, RX_CNTL_CSR, reg);
1397
1398 return 0;
1399}
1400
1401static int rt61pci_init_registers(struct rt2x00_dev *rt2x00dev)
1402{
1403 u32 reg;
1404
1405 rt2x00pci_register_read(rt2x00dev, TXRX_CSR0, &reg);
1406 rt2x00_set_field32(&reg, TXRX_CSR0_AUTO_TX_SEQ, 1);
1407 rt2x00_set_field32(&reg, TXRX_CSR0_DISABLE_RX, 0);
1408 rt2x00_set_field32(&reg, TXRX_CSR0_TX_WITHOUT_WAITING, 0);
1409 rt2x00pci_register_write(rt2x00dev, TXRX_CSR0, reg);
1410
1411 rt2x00pci_register_read(rt2x00dev, TXRX_CSR1, &reg);
1412 rt2x00_set_field32(&reg, TXRX_CSR1_BBP_ID0, 47); /* CCK Signal */
1413 rt2x00_set_field32(&reg, TXRX_CSR1_BBP_ID0_VALID, 1);
1414 rt2x00_set_field32(&reg, TXRX_CSR1_BBP_ID1, 30); /* Rssi */
1415 rt2x00_set_field32(&reg, TXRX_CSR1_BBP_ID1_VALID, 1);
1416 rt2x00_set_field32(&reg, TXRX_CSR1_BBP_ID2, 42); /* OFDM Rate */
1417 rt2x00_set_field32(&reg, TXRX_CSR1_BBP_ID2_VALID, 1);
1418 rt2x00_set_field32(&reg, TXRX_CSR1_BBP_ID3, 30); /* Rssi */
1419 rt2x00_set_field32(&reg, TXRX_CSR1_BBP_ID3_VALID, 1);
1420 rt2x00pci_register_write(rt2x00dev, TXRX_CSR1, reg);
1421
1422 /*
1423 * CCK TXD BBP registers
1424 */
1425 rt2x00pci_register_read(rt2x00dev, TXRX_CSR2, &reg);
1426 rt2x00_set_field32(&reg, TXRX_CSR2_BBP_ID0, 13);
1427 rt2x00_set_field32(&reg, TXRX_CSR2_BBP_ID0_VALID, 1);
1428 rt2x00_set_field32(&reg, TXRX_CSR2_BBP_ID1, 12);
1429 rt2x00_set_field32(&reg, TXRX_CSR2_BBP_ID1_VALID, 1);
1430 rt2x00_set_field32(&reg, TXRX_CSR2_BBP_ID2, 11);
1431 rt2x00_set_field32(&reg, TXRX_CSR2_BBP_ID2_VALID, 1);
1432 rt2x00_set_field32(&reg, TXRX_CSR2_BBP_ID3, 10);
1433 rt2x00_set_field32(&reg, TXRX_CSR2_BBP_ID3_VALID, 1);
1434 rt2x00pci_register_write(rt2x00dev, TXRX_CSR2, reg);
1435
1436 /*
1437 * OFDM TXD BBP registers
1438 */
1439 rt2x00pci_register_read(rt2x00dev, TXRX_CSR3, &reg);
1440 rt2x00_set_field32(&reg, TXRX_CSR3_BBP_ID0, 7);
1441 rt2x00_set_field32(&reg, TXRX_CSR3_BBP_ID0_VALID, 1);
1442 rt2x00_set_field32(&reg, TXRX_CSR3_BBP_ID1, 6);
1443 rt2x00_set_field32(&reg, TXRX_CSR3_BBP_ID1_VALID, 1);
1444 rt2x00_set_field32(&reg, TXRX_CSR3_BBP_ID2, 5);
1445 rt2x00_set_field32(&reg, TXRX_CSR3_BBP_ID2_VALID, 1);
1446 rt2x00pci_register_write(rt2x00dev, TXRX_CSR3, reg);
1447
1448 rt2x00pci_register_read(rt2x00dev, TXRX_CSR7, &reg);
1449 rt2x00_set_field32(&reg, TXRX_CSR7_ACK_CTS_6MBS, 59);
1450 rt2x00_set_field32(&reg, TXRX_CSR7_ACK_CTS_9MBS, 53);
1451 rt2x00_set_field32(&reg, TXRX_CSR7_ACK_CTS_12MBS, 49);
1452 rt2x00_set_field32(&reg, TXRX_CSR7_ACK_CTS_18MBS, 46);
1453 rt2x00pci_register_write(rt2x00dev, TXRX_CSR7, reg);
1454
1455 rt2x00pci_register_read(rt2x00dev, TXRX_CSR8, &reg);
1456 rt2x00_set_field32(&reg, TXRX_CSR8_ACK_CTS_24MBS, 44);
1457 rt2x00_set_field32(&reg, TXRX_CSR8_ACK_CTS_36MBS, 42);
1458 rt2x00_set_field32(&reg, TXRX_CSR8_ACK_CTS_48MBS, 42);
1459 rt2x00_set_field32(&reg, TXRX_CSR8_ACK_CTS_54MBS, 42);
1460 rt2x00pci_register_write(rt2x00dev, TXRX_CSR8, reg);
1461
1f909162
ID		 1462 rt2x00pci_register_read(rt2x00dev, TXRX_CSR9, &reg);
1463 rt2x00_set_field32(&reg, TXRX_CSR9_BEACON_INTERVAL, 0);
1464 rt2x00_set_field32(&reg, TXRX_CSR9_TSF_TICKING, 0);
1465 rt2x00_set_field32(&reg, TXRX_CSR9_TSF_SYNC, 0);
1466 rt2x00_set_field32(&reg, TXRX_CSR9_TBTT_ENABLE, 0);
1467 rt2x00_set_field32(&reg, TXRX_CSR9_BEACON_GEN, 0);
1468 rt2x00_set_field32(&reg, TXRX_CSR9_TIMESTAMP_COMPENSATE, 0);
1469 rt2x00pci_register_write(rt2x00dev, TXRX_CSR9, reg);
1470
95ea3627
ID		 1471 rt2x00pci_register_write(rt2x00dev, TXRX_CSR15, 0x0000000f);
1472
1473 rt2x00pci_register_write(rt2x00dev, MAC_CSR6, 0x00000fff);
1474
1475 rt2x00pci_register_read(rt2x00dev, MAC_CSR9, &reg);
1476 rt2x00_set_field32(&reg, MAC_CSR9_CW_SELECT, 0);
1477 rt2x00pci_register_write(rt2x00dev, MAC_CSR9, reg);
1478
1479 rt2x00pci_register_write(rt2x00dev, MAC_CSR10, 0x0000071c);
1480
1481 if (rt2x00dev->ops->lib->set_device_state(rt2x00dev, STATE_AWAKE))
1482 return -EBUSY;
1483
1484 rt2x00pci_register_write(rt2x00dev, MAC_CSR13, 0x0000e000);
1485
1486 /*
1487 * Invalidate all Shared Keys (SEC_CSR0),
1488 * and clear the Shared key Cipher algorithms (SEC_CSR1 & SEC_CSR5)
1489 */
1490 rt2x00pci_register_write(rt2x00dev, SEC_CSR0, 0x00000000);
1491 rt2x00pci_register_write(rt2x00dev, SEC_CSR1, 0x00000000);
1492 rt2x00pci_register_write(rt2x00dev, SEC_CSR5, 0x00000000);
1493
1494 rt2x00pci_register_write(rt2x00dev, PHY_CSR1, 0x000023b0);
1495 rt2x00pci_register_write(rt2x00dev, PHY_CSR5, 0x060a100c);
1496 rt2x00pci_register_write(rt2x00dev, PHY_CSR6, 0x00080606);
1497 rt2x00pci_register_write(rt2x00dev, PHY_CSR7, 0x00000a08);
1498
1499 rt2x00pci_register_write(rt2x00dev, PCI_CFG_CSR, 0x28ca4404);
1500
1501 rt2x00pci_register_write(rt2x00dev, TEST_MODE_CSR, 0x00000200);
1502
1503 rt2x00pci_register_write(rt2x00dev, M2H_CMD_DONE_CSR, 0xffffffff);
1504
6bb40dd1
ID		 1505 /*
1506 * Clear all beacons
1507 * For the Beacon base registers we only need to clear
1508 * the first byte since that byte contains the VALID and OWNER
1509 * bits which (when set to 0) will invalidate the entire beacon.
1510 */
1511 rt2x00pci_register_write(rt2x00dev, HW_BEACON_BASE0, 0);
1512 rt2x00pci_register_write(rt2x00dev, HW_BEACON_BASE1, 0);
1513 rt2x00pci_register_write(rt2x00dev, HW_BEACON_BASE2, 0);
1514 rt2x00pci_register_write(rt2x00dev, HW_BEACON_BASE3, 0);
1515
95ea3627
ID		 1516 /*
1517 * We must clear the error counters.
1518 * These registers are cleared on read,
1519 * so we may pass a useless variable to store the value.
1520 */
1521 rt2x00pci_register_read(rt2x00dev, STA_CSR0, &reg);
1522 rt2x00pci_register_read(rt2x00dev, STA_CSR1, &reg);
1523 rt2x00pci_register_read(rt2x00dev, STA_CSR2, &reg);
1524
1525 /*
1526 * Reset MAC and BBP registers.
1527 */
1528 rt2x00pci_register_read(rt2x00dev, MAC_CSR1, &reg);
1529 rt2x00_set_field32(&reg, MAC_CSR1_SOFT_RESET, 1);
1530 rt2x00_set_field32(&reg, MAC_CSR1_BBP_RESET, 1);
1531 rt2x00pci_register_write(rt2x00dev, MAC_CSR1, reg);
1532
1533 rt2x00pci_register_read(rt2x00dev, MAC_CSR1, &reg);
1534 rt2x00_set_field32(&reg, MAC_CSR1_SOFT_RESET, 0);
1535 rt2x00_set_field32(&reg, MAC_CSR1_BBP_RESET, 0);
1536 rt2x00pci_register_write(rt2x00dev, MAC_CSR1, reg);
1537
1538 rt2x00pci_register_read(rt2x00dev, MAC_CSR1, &reg);
1539 rt2x00_set_field32(&reg, MAC_CSR1_HOST_READY, 1);
1540 rt2x00pci_register_write(rt2x00dev, MAC_CSR1, reg);
1541
1542 return 0;
1543}
1544
2b08da3f 1545static int rt61pci_wait_bbp_ready(struct rt2x00_dev *rt2x00dev)
95ea3627
ID		 1546{
1547 unsigned int i;
95ea3627
ID		 1548 u8 value;
1549
1550 for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
1551 rt61pci_bbp_read(rt2x00dev, 0, &value);
1552 if ((value != 0xff) && (value != 0x00))
2b08da3f 1553 return 0;
95ea3627
ID		 1554 udelay(REGISTER_BUSY_DELAY);
1555 }
1556
1557 ERROR(rt2x00dev, "BBP register access failed, aborting.\n");
1558 return -EACCES;
2b08da3f
ID		 1559}
1560
1561static int rt61pci_init_bbp(struct rt2x00_dev *rt2x00dev)
1562{
1563 unsigned int i;
1564 u16 eeprom;
1565 u8 reg_id;
1566 u8 value;
1567
1568 if (unlikely(rt61pci_wait_bbp_ready(rt2x00dev)))
1569 return -EACCES;
95ea3627 1570
95ea3627
ID		 1571 rt61pci_bbp_write(rt2x00dev, 3, 0x00);
1572 rt61pci_bbp_write(rt2x00dev, 15, 0x30);
1573 rt61pci_bbp_write(rt2x00dev, 21, 0xc8);
1574 rt61pci_bbp_write(rt2x00dev, 22, 0x38);
1575 rt61pci_bbp_write(rt2x00dev, 23, 0x06);
1576 rt61pci_bbp_write(rt2x00dev, 24, 0xfe);
1577 rt61pci_bbp_write(rt2x00dev, 25, 0x0a);
1578 rt61pci_bbp_write(rt2x00dev, 26, 0x0d);
1579 rt61pci_bbp_write(rt2x00dev, 34, 0x12);
1580 rt61pci_bbp_write(rt2x00dev, 37, 0x07);
1581 rt61pci_bbp_write(rt2x00dev, 39, 0xf8);
1582 rt61pci_bbp_write(rt2x00dev, 41, 0x60);
1583 rt61pci_bbp_write(rt2x00dev, 53, 0x10);
1584 rt61pci_bbp_write(rt2x00dev, 54, 0x18);
1585 rt61pci_bbp_write(rt2x00dev, 60, 0x10);
1586 rt61pci_bbp_write(rt2x00dev, 61, 0x04);
1587 rt61pci_bbp_write(rt2x00dev, 62, 0x04);
1588 rt61pci_bbp_write(rt2x00dev, 75, 0xfe);
1589 rt61pci_bbp_write(rt2x00dev, 86, 0xfe);
1590 rt61pci_bbp_write(rt2x00dev, 88, 0xfe);
1591 rt61pci_bbp_write(rt2x00dev, 90, 0x0f);
1592 rt61pci_bbp_write(rt2x00dev, 99, 0x00);
1593 rt61pci_bbp_write(rt2x00dev, 102, 0x16);
1594 rt61pci_bbp_write(rt2x00dev, 107, 0x04);
1595
95ea3627
ID		 1596 for (i = 0; i < EEPROM_BBP_SIZE; i++) {
1597 rt2x00_eeprom_read(rt2x00dev, EEPROM_BBP_START + i, &eeprom);
1598
1599 if (eeprom != 0xffff && eeprom != 0x0000) {
1600 reg_id = rt2x00_get_field16(eeprom, EEPROM_BBP_REG_ID);
1601 value = rt2x00_get_field16(eeprom, EEPROM_BBP_VALUE);
95ea3627
ID		 1602 rt61pci_bbp_write(rt2x00dev, reg_id, value);
1603 }
1604 }
95ea3627
ID		 1605
1606 return 0;
1607}
1608
1609/*
1610 * Device state switch handlers.
1611 */
1612static void rt61pci_toggle_rx(struct rt2x00_dev *rt2x00dev,
1613 enum dev_state state)
1614{
1615 u32 reg;
1616
1617 rt2x00pci_register_read(rt2x00dev, TXRX_CSR0, &reg);
1618 rt2x00_set_field32(&reg, TXRX_CSR0_DISABLE_RX,
2b08da3f
ID		 1619 (state == STATE_RADIO_RX_OFF) ||
1620 (state == STATE_RADIO_RX_OFF_LINK));
95ea3627
ID		 1621 rt2x00pci_register_write(rt2x00dev, TXRX_CSR0, reg);
1622}
1623
1624static void rt61pci_toggle_irq(struct rt2x00_dev *rt2x00dev,
1625 enum dev_state state)
1626{
1627 int mask = (state == STATE_RADIO_IRQ_OFF);
1628 u32 reg;
1629
1630 /*
1631 * When interrupts are being enabled, the interrupt registers
1632 * should clear the register to assure a clean state.
1633 */
1634 if (state == STATE_RADIO_IRQ_ON) {
1635 rt2x00pci_register_read(rt2x00dev, INT_SOURCE_CSR, &reg);
1636 rt2x00pci_register_write(rt2x00dev, INT_SOURCE_CSR, reg);
1637
1638 rt2x00pci_register_read(rt2x00dev, MCU_INT_SOURCE_CSR, &reg);
1639 rt2x00pci_register_write(rt2x00dev, MCU_INT_SOURCE_CSR, reg);
1640 }
1641
1642 /*
1643 * Only toggle the interrupts bits we are going to use.
1644 * Non-checked interrupt bits are disabled by default.
1645 */
1646 rt2x00pci_register_read(rt2x00dev, INT_MASK_CSR, &reg);
1647 rt2x00_set_field32(&reg, INT_MASK_CSR_TXDONE, mask);
1648 rt2x00_set_field32(&reg, INT_MASK_CSR_RXDONE, mask);
1649 rt2x00_set_field32(&reg, INT_MASK_CSR_ENABLE_MITIGATION, mask);
1650 rt2x00_set_field32(&reg, INT_MASK_CSR_MITIGATION_PERIOD, 0xff);
1651 rt2x00pci_register_write(rt2x00dev, INT_MASK_CSR, reg);
1652
1653 rt2x00pci_register_read(rt2x00dev, MCU_INT_MASK_CSR, &reg);
1654 rt2x00_set_field32(&reg, MCU_INT_MASK_CSR_0, mask);
1655 rt2x00_set_field32(&reg, MCU_INT_MASK_CSR_1, mask);
1656 rt2x00_set_field32(&reg, MCU_INT_MASK_CSR_2, mask);
1657 rt2x00_set_field32(&reg, MCU_INT_MASK_CSR_3, mask);
1658 rt2x00_set_field32(&reg, MCU_INT_MASK_CSR_4, mask);
1659 rt2x00_set_field32(&reg, MCU_INT_MASK_CSR_5, mask);
1660 rt2x00_set_field32(&reg, MCU_INT_MASK_CSR_6, mask);
1661 rt2x00_set_field32(&reg, MCU_INT_MASK_CSR_7, mask);
1662 rt2x00pci_register_write(rt2x00dev, MCU_INT_MASK_CSR, reg);
1663}
1664
1665static int rt61pci_enable_radio(struct rt2x00_dev *rt2x00dev)
1666{
1667 u32 reg;
1668
1669 /*
1670 * Initialize all registers.
1671 */
2b08da3f
ID		 1672 if (unlikely(rt61pci_init_queues(rt2x00dev) ||
1673 rt61pci_init_registers(rt2x00dev) ||
1674 rt61pci_init_bbp(rt2x00dev)))
95ea3627 1675 return -EIO;
95ea3627
ID		 1676
1677 /*
1678 * Enable RX.
1679 */
1680 rt2x00pci_register_read(rt2x00dev, RX_CNTL_CSR, &reg);
1681 rt2x00_set_field32(&reg, RX_CNTL_CSR_ENABLE_RX_DMA, 1);
1682 rt2x00pci_register_write(rt2x00dev, RX_CNTL_CSR, reg);
1683
95ea3627
ID		 1684 return 0;
1685}
1686
1687static void rt61pci_disable_radio(struct rt2x00_dev *rt2x00dev)
1688{
95ea3627 1689 /*
a2c9b652 1690 * Disable power
95ea3627 1691 */
a2c9b652 1692 rt2x00pci_register_write(rt2x00dev, MAC_CSR10, 0x00001818);
95ea3627
ID		 1693}
1694
1695static int rt61pci_set_state(struct rt2x00_dev *rt2x00dev, enum dev_state state)
1696{
1697 u32 reg;
1698 unsigned int i;
1699 char put_to_sleep;
95ea3627
ID		 1700
1701 put_to_sleep = (state != STATE_AWAKE);
1702
1703 rt2x00pci_register_read(rt2x00dev, MAC_CSR12, &reg);
1704 rt2x00_set_field32(&reg, MAC_CSR12_FORCE_WAKEUP, !put_to_sleep);
1705 rt2x00_set_field32(&reg, MAC_CSR12_PUT_TO_SLEEP, put_to_sleep);
1706 rt2x00pci_register_write(rt2x00dev, MAC_CSR12, reg);
1707
1708 /*
1709 * Device is not guaranteed to be in the requested state yet.
1710 * We must wait until the register indicates that the
1711 * device has entered the correct state.
1712 */
1713 for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
1714 rt2x00pci_register_read(rt2x00dev, MAC_CSR12, &reg);
2b08da3f
ID		 1715 state = rt2x00_get_field32(reg, MAC_CSR12_BBP_CURRENT_STATE);
1716 if (state == !put_to_sleep)
95ea3627
ID		 1717 return 0;
1718 msleep(10);
1719 }
1720
95ea3627
ID		 1721 return -EBUSY;
1722}
1723
1724static int rt61pci_set_device_state(struct rt2x00_dev *rt2x00dev,
1725 enum dev_state state)
1726{
1727 int retval = 0;
1728
1729 switch (state) {
1730 case STATE_RADIO_ON:
1731 retval = rt61pci_enable_radio(rt2x00dev);
1732 break;
1733 case STATE_RADIO_OFF:
1734 rt61pci_disable_radio(rt2x00dev);
1735 break;
1736 case STATE_RADIO_RX_ON:
61667d8d 1737 case STATE_RADIO_RX_ON_LINK:
95ea3627 1738 case STATE_RADIO_RX_OFF:
61667d8d 1739 case STATE_RADIO_RX_OFF_LINK:
2b08da3f
ID		 1740 rt61pci_toggle_rx(rt2x00dev, state);
1741 break;
1742 case STATE_RADIO_IRQ_ON:
1743 case STATE_RADIO_IRQ_OFF:
1744 rt61pci_toggle_irq(rt2x00dev, state);
95ea3627
ID		 1745 break;
1746 case STATE_DEEP_SLEEP:
1747 case STATE_SLEEP:
1748 case STATE_STANDBY:
1749 case STATE_AWAKE:
1750 retval = rt61pci_set_state(rt2x00dev, state);
1751 break;
1752 default:
1753 retval = -ENOTSUPP;
1754 break;
1755 }
1756
2b08da3f
ID		 1757 if (unlikely(retval))
1758 ERROR(rt2x00dev, "Device failed to enter state %d (%d).\n",
1759 state, retval);
1760
95ea3627
ID		 1761 return retval;
1762}
1763
1764/*
1765 * TX descriptor initialization
1766 */
1767static void rt61pci_write_tx_desc(struct rt2x00_dev *rt2x00dev,
61e754f4
ID		 1768 struct sk_buff *skb,
1769 struct txentry_desc *txdesc)
95ea3627 1770{
181d6902 1771 struct skb_frame_desc *skbdesc = get_skb_frame_desc(skb);
dd3193e1 1772 __le32 *txd = skbdesc->desc;
95ea3627
ID		 1773 u32 word;
1774
1775 /*
1776 * Start writing the descriptor words.
1777 */
1778 rt2x00_desc_read(txd, 1, &word);
181d6902
ID		 1779 rt2x00_set_field32(&word, TXD_W1_HOST_Q_ID, txdesc->queue);
1780 rt2x00_set_field32(&word, TXD_W1_AIFSN, txdesc->aifs);
1781 rt2x00_set_field32(&word, TXD_W1_CWMIN, txdesc->cw_min);
1782 rt2x00_set_field32(&word, TXD_W1_CWMAX, txdesc->cw_max);
61e754f4 1783 rt2x00_set_field32(&word, TXD_W1_IV_OFFSET, txdesc->iv_offset);
5adf6d63
ID		 1784 rt2x00_set_field32(&word, TXD_W1_HW_SEQUENCE,
1785 test_bit(ENTRY_TXD_GENERATE_SEQ, &txdesc->flags));
4de36fe5 1786 rt2x00_set_field32(&word, TXD_W1_BUFFER_COUNT, 1);
95ea3627
ID		 1787 rt2x00_desc_write(txd, 1, word);
1788
1789 rt2x00_desc_read(txd, 2, &word);
181d6902
ID		 1790 rt2x00_set_field32(&word, TXD_W2_PLCP_SIGNAL, txdesc->signal);
1791 rt2x00_set_field32(&word, TXD_W2_PLCP_SERVICE, txdesc->service);
1792 rt2x00_set_field32(&word, TXD_W2_PLCP_LENGTH_LOW, txdesc->length_low);
1793 rt2x00_set_field32(&word, TXD_W2_PLCP_LENGTH_HIGH, txdesc->length_high);
95ea3627
ID		 1794 rt2x00_desc_write(txd, 2, word);
1795
61e754f4 1796 if (test_bit(ENTRY_TXD_ENCRYPT, &txdesc->flags)) {
1ce9cdac
ID		 1797 _rt2x00_desc_write(txd, 3, skbdesc->iv[0]);
1798 _rt2x00_desc_write(txd, 4, skbdesc->iv[1]);
61e754f4
ID		 1799 }
1800
95ea3627 1801 rt2x00_desc_read(txd, 5, &word);
4de36fe5
GW		 1802 rt2x00_set_field32(&word, TXD_W5_PID_TYPE, skbdesc->entry->queue->qid);
1803 rt2x00_set_field32(&word, TXD_W5_PID_SUBTYPE,
1804 skbdesc->entry->entry_idx);
95ea3627 1805 rt2x00_set_field32(&word, TXD_W5_TX_POWER,
ac1aa7e4 1806 TXPOWER_TO_DEV(rt2x00dev->tx_power));
95ea3627
ID		 1807 rt2x00_set_field32(&word, TXD_W5_WAITING_DMA_DONE_INT, 1);
1808 rt2x00_desc_write(txd, 5, word);
1809
4de36fe5
GW		 1810 rt2x00_desc_read(txd, 6, &word);
1811 rt2x00_set_field32(&word, TXD_W6_BUFFER_PHYSICAL_ADDRESS,
c4da0048 1812 skbdesc->skb_dma);
4de36fe5
GW		 1813 rt2x00_desc_write(txd, 6, word);
1814
d7bafff3
AB		 1815 if (skbdesc->desc_len > TXINFO_SIZE) {
1816 rt2x00_desc_read(txd, 11, &word);
d56d453a 1817 rt2x00_set_field32(&word, TXD_W11_BUFFER_LENGTH0, skb->len);
d7bafff3
AB		 1818 rt2x00_desc_write(txd, 11, word);
1819 }
95ea3627
ID		 1820
1821 rt2x00_desc_read(txd, 0, &word);
1822 rt2x00_set_field32(&word, TXD_W0_OWNER_NIC, 1);
1823 rt2x00_set_field32(&word, TXD_W0_VALID, 1);
1824 rt2x00_set_field32(&word, TXD_W0_MORE_FRAG,
181d6902 1825 test_bit(ENTRY_TXD_MORE_FRAG, &txdesc->flags));
95ea3627 1826 rt2x00_set_field32(&word, TXD_W0_ACK,
181d6902 1827 test_bit(ENTRY_TXD_ACK, &txdesc->flags));
95ea3627 1828 rt2x00_set_field32(&word, TXD_W0_TIMESTAMP,
181d6902 1829 test_bit(ENTRY_TXD_REQ_TIMESTAMP, &txdesc->flags));
95ea3627 1830 rt2x00_set_field32(&word, TXD_W0_OFDM,
076f9582 1831 (txdesc->rate_mode == RATE_MODE_OFDM));
181d6902 1832 rt2x00_set_field32(&word, TXD_W0_IFS, txdesc->ifs);
95ea3627 1833 rt2x00_set_field32(&word, TXD_W0_RETRY_MODE,
61486e0f 1834 test_bit(ENTRY_TXD_RETRY_MODE, &txdesc->flags));
61e754f4
ID		 1835 rt2x00_set_field32(&word, TXD_W0_TKIP_MIC,
1836 test_bit(ENTRY_TXD_ENCRYPT_MMIC, &txdesc->flags));
1837 rt2x00_set_field32(&word, TXD_W0_KEY_TABLE,
1838 test_bit(ENTRY_TXD_ENCRYPT_PAIRWISE, &txdesc->flags));
1839 rt2x00_set_field32(&word, TXD_W0_KEY_INDEX, txdesc->key_idx);
d56d453a 1840 rt2x00_set_field32(&word, TXD_W0_DATABYTE_COUNT, skb->len);
95ea3627 1841 rt2x00_set_field32(&word, TXD_W0_BURST,
181d6902 1842 test_bit(ENTRY_TXD_BURST, &txdesc->flags));
61e754f4 1843 rt2x00_set_field32(&word, TXD_W0_CIPHER_ALG, txdesc->cipher);
95ea3627
ID		 1844 rt2x00_desc_write(txd, 0, word);
1845}
1846
1847/*
1848 * TX data initialization
1849 */
bd88a781
ID		 1850static void rt61pci_write_beacon(struct queue_entry *entry)
1851{
1852 struct rt2x00_dev *rt2x00dev = entry->queue->rt2x00dev;
1853 struct skb_frame_desc *skbdesc = get_skb_frame_desc(entry->skb);
1854 unsigned int beacon_base;
1855 u32 reg;
1856
1857 /*
1858 * Disable beaconing while we are reloading the beacon data,
1859 * otherwise we might be sending out invalid data.
1860 */
1861 rt2x00pci_register_read(rt2x00dev, TXRX_CSR9, &reg);
1862 rt2x00_set_field32(&reg, TXRX_CSR9_TSF_TICKING, 0);
1863 rt2x00_set_field32(&reg, TXRX_CSR9_TBTT_ENABLE, 0);
1864 rt2x00_set_field32(&reg, TXRX_CSR9_BEACON_GEN, 0);
1865 rt2x00pci_register_write(rt2x00dev, TXRX_CSR9, reg);
1866
1867 /*
1868 * Write entire beacon with descriptor to register.
1869 */
1870 beacon_base = HW_BEACON_OFFSET(entry->entry_idx);
1871 rt2x00pci_register_multiwrite(rt2x00dev,
1872 beacon_base,
1873 skbdesc->desc, skbdesc->desc_len);
1874 rt2x00pci_register_multiwrite(rt2x00dev,
1875 beacon_base + skbdesc->desc_len,
1876 entry->skb->data, entry->skb->len);
1877
1878 /*
1879 * Clean up beacon skb.
1880 */
1881 dev_kfree_skb_any(entry->skb);
1882 entry->skb = NULL;
1883}
1884
95ea3627 1885static void rt61pci_kick_tx_queue(struct rt2x00_dev *rt2x00dev,
e58c6aca 1886 const enum data_queue_qid queue)
95ea3627
ID		 1887{
1888 u32 reg;
1889
e58c6aca 1890 if (queue == QID_BEACON) {
95ea3627
ID		 1891 /*
1892 * For Wi-Fi faily generated beacons between participating
1893 * stations. Set TBTT phase adaptive adjustment step to 8us.
1894 */
1895 rt2x00pci_register_write(rt2x00dev, TXRX_CSR10, 0x00001008);
1896
1897 rt2x00pci_register_read(rt2x00dev, TXRX_CSR9, &reg);
1898 if (!rt2x00_get_field32(reg, TXRX_CSR9_BEACON_GEN)) {
8af244cc
ID		 1899 rt2x00_set_field32(&reg, TXRX_CSR9_TSF_TICKING, 1);
1900 rt2x00_set_field32(&reg, TXRX_CSR9_TBTT_ENABLE, 1);
95ea3627
ID		 1901 rt2x00_set_field32(&reg, TXRX_CSR9_BEACON_GEN, 1);
1902 rt2x00pci_register_write(rt2x00dev, TXRX_CSR9, reg);
1903 }
1904 return;
1905 }
1906
1907 rt2x00pci_register_read(rt2x00dev, TX_CNTL_CSR, &reg);
e58c6aca
ID		 1908 rt2x00_set_field32(&reg, TX_CNTL_CSR_KICK_TX_AC0, (queue == QID_AC_BE));
1909 rt2x00_set_field32(&reg, TX_CNTL_CSR_KICK_TX_AC1, (queue == QID_AC_BK));
1910 rt2x00_set_field32(&reg, TX_CNTL_CSR_KICK_TX_AC2, (queue == QID_AC_VI));
1911 rt2x00_set_field32(&reg, TX_CNTL_CSR_KICK_TX_AC3, (queue == QID_AC_VO));
95ea3627
ID		 1912 rt2x00pci_register_write(rt2x00dev, TX_CNTL_CSR, reg);
1913}
1914
a2c9b652
ID		 1915static void rt61pci_kill_tx_queue(struct rt2x00_dev *rt2x00dev,
1916 const enum data_queue_qid qid)
1917{
1918 u32 reg;
1919
1920 if (qid == QID_BEACON) {
1921 rt2x00pci_register_write(rt2x00dev, TXRX_CSR9, 0);
1922 return;
1923 }
1924
1925 rt2x00pci_register_read(rt2x00dev, TX_CNTL_CSR, &reg);
1926 rt2x00_set_field32(&reg, TX_CNTL_CSR_ABORT_TX_AC0, (qid == QID_AC_BE));
1927 rt2x00_set_field32(&reg, TX_CNTL_CSR_ABORT_TX_AC1, (qid == QID_AC_BK));
1928 rt2x00_set_field32(&reg, TX_CNTL_CSR_ABORT_TX_AC2, (qid == QID_AC_VI));
1929 rt2x00_set_field32(&reg, TX_CNTL_CSR_ABORT_TX_AC3, (qid == QID_AC_VO));
1930 rt2x00pci_register_write(rt2x00dev, TX_CNTL_CSR, reg);
1931}
1932
95ea3627
ID		 1933/*
1934 * RX control handlers
1935 */
1936static int rt61pci_agc_to_rssi(struct rt2x00_dev *rt2x00dev, int rxd_w1)
1937{
ba2ab471 1938 u8 offset = rt2x00dev->lna_gain;
95ea3627
ID		 1939 u8 lna;
1940
1941 lna = rt2x00_get_field32(rxd_w1, RXD_W1_RSSI_LNA);
1942 switch (lna) {
1943 case 3:
ba2ab471 1944 offset += 90;
95ea3627
ID		 1945 break;
1946 case 2:
ba2ab471 1947 offset += 74;
95ea3627
ID		 1948 break;
1949 case 1:
ba2ab471 1950 offset += 64;
95ea3627
ID		 1951 break;
1952 default:
1953 return 0;
1954 }
1955
8318d78a 1956 if (rt2x00dev->rx_status.band == IEEE80211_BAND_5GHZ) {
95ea3627
ID		 1957 if (lna == 3 || lna == 2)
1958 offset += 10;
95ea3627
ID		 1959 }
1960
1961 return rt2x00_get_field32(rxd_w1, RXD_W1_RSSI_AGC) * 2 - offset;
1962}
1963
181d6902 1964static void rt61pci_fill_rxdone(struct queue_entry *entry,
55887511 1965 struct rxdone_entry_desc *rxdesc)
95ea3627 1966{
61e754f4 1967 struct rt2x00_dev *rt2x00dev = entry->queue->rt2x00dev;
b8be63ff 1968 struct queue_entry_priv_pci *entry_priv = entry->priv_data;
95ea3627
ID		 1969 u32 word0;
1970 u32 word1;
1971
b8be63ff
ID		 1972 rt2x00_desc_read(entry_priv->desc, 0, &word0);
1973 rt2x00_desc_read(entry_priv->desc, 1, &word1);
95ea3627 1974
4150c572 1975 if (rt2x00_get_field32(word0, RXD_W0_CRC_ERROR))
181d6902 1976 rxdesc->flags |= RX_FLAG_FAILED_FCS_CRC;
95ea3627 1977
61e754f4
ID		 1978 if (test_bit(CONFIG_SUPPORT_HW_CRYPTO, &rt2x00dev->flags)) {
1979 rxdesc->cipher =
1980 rt2x00_get_field32(word0, RXD_W0_CIPHER_ALG);
1981 rxdesc->cipher_status =
1982 rt2x00_get_field32(word0, RXD_W0_CIPHER_ERROR);
1983 }
1984
1985 if (rxdesc->cipher != CIPHER_NONE) {
1ce9cdac
ID		 1986 _rt2x00_desc_read(entry_priv->desc, 2, &rxdesc->iv[0]);
1987 _rt2x00_desc_read(entry_priv->desc, 3, &rxdesc->iv[1]);
74415edb
ID		 1988 rxdesc->dev_flags |= RXDONE_CRYPTO_IV;
1989
61e754f4 1990 _rt2x00_desc_read(entry_priv->desc, 4, &rxdesc->icv);
74415edb 1991 rxdesc->dev_flags |= RXDONE_CRYPTO_ICV;
61e754f4
ID		 1992
1993 /*
1994 * Hardware has stripped IV/EIV data from 802.11 frame during
1995 * decryption. It has provided the data seperately but rt2x00lib
1996 * should decide if it should be reinserted.
1997 */
1998 rxdesc->flags |= RX_FLAG_IV_STRIPPED;
1999
2000 /*
2001 * FIXME: Legacy driver indicates that the frame does
2002 * contain the Michael Mic. Unfortunately, in rt2x00
2003 * the MIC seems to be missing completely...
2004 */
2005 rxdesc->flags |= RX_FLAG_MMIC_STRIPPED;
2006
2007 if (rxdesc->cipher_status == RX_CRYPTO_SUCCESS)
2008 rxdesc->flags |= RX_FLAG_DECRYPTED;
2009 else if (rxdesc->cipher_status == RX_CRYPTO_FAIL_MIC)
2010 rxdesc->flags |= RX_FLAG_MMIC_ERROR;
2011 }
2012
95ea3627
ID		 2013 /*
2014 * Obtain the status about this packet.
89993890
ID		 2015 * When frame was received with an OFDM bitrate,
2016 * the signal is the PLCP value. If it was received with
2017 * a CCK bitrate the signal is the rate in 100kbit/s.
95ea3627 2018 */
181d6902 2019 rxdesc->signal = rt2x00_get_field32(word1, RXD_W1_SIGNAL);
61e754f4 2020 rxdesc->rssi = rt61pci_agc_to_rssi(rt2x00dev, word1);
181d6902 2021 rxdesc->size = rt2x00_get_field32(word0, RXD_W0_DATABYTE_COUNT);
19d30e02 2022
19d30e02
ID		 2023 if (rt2x00_get_field32(word0, RXD_W0_OFDM))
2024 rxdesc->dev_flags |= RXDONE_SIGNAL_PLCP;
6c6aa3c0
ID		 2025 else
2026 rxdesc->dev_flags |= RXDONE_SIGNAL_BITRATE;
19d30e02
ID		 2027 if (rt2x00_get_field32(word0, RXD_W0_MY_BSS))
2028 rxdesc->dev_flags |= RXDONE_MY_BSS;
95ea3627
ID		 2029}
2030
2031/*
2032 * Interrupt functions.
2033 */
2034static void rt61pci_txdone(struct rt2x00_dev *rt2x00dev)
2035{
181d6902
ID		 2036 struct data_queue *queue;
2037 struct queue_entry *entry;
2038 struct queue_entry *entry_done;
b8be63ff 2039 struct queue_entry_priv_pci *entry_priv;
181d6902 2040 struct txdone_entry_desc txdesc;
95ea3627
ID		 2041 u32 word;
2042 u32 reg;
2043 u32 old_reg;
2044 int type;
2045 int index;
95ea3627
ID		 2046
2047 /*
2048 * During each loop we will compare the freshly read
2049 * STA_CSR4 register value with the value read from
2050 * the previous loop. If the 2 values are equal then
2051 * we should stop processing because the chance it
2052 * quite big that the device has been unplugged and
2053 * we risk going into an endless loop.
2054 */
2055 old_reg = 0;
2056
2057 while (1) {
2058 rt2x00pci_register_read(rt2x00dev, STA_CSR4, &reg);
2059 if (!rt2x00_get_field32(reg, STA_CSR4_VALID))
2060 break;
2061
2062 if (old_reg == reg)
2063 break;
2064 old_reg = reg;
2065
2066 /*
2067 * Skip this entry when it contains an invalid
181d6902 2068 * queue identication number.
95ea3627
ID		 2069 */
2070 type = rt2x00_get_field32(reg, STA_CSR4_PID_TYPE);
181d6902
ID		 2071 queue = rt2x00queue_get_queue(rt2x00dev, type);
2072 if (unlikely(!queue))
95ea3627
ID		 2073 continue;
2074
2075 /*
2076 * Skip this entry when it contains an invalid
2077 * index number.
2078 */
2079 index = rt2x00_get_field32(reg, STA_CSR4_PID_SUBTYPE);
181d6902 2080 if (unlikely(index >= queue->limit))
95ea3627
ID		 2081 continue;
2082
181d6902 2083 entry = &queue->entries[index];
b8be63ff
ID		 2084 entry_priv = entry->priv_data;
2085 rt2x00_desc_read(entry_priv->desc, 0, &word);
95ea3627
ID		 2086
2087 if (rt2x00_get_field32(word, TXD_W0_OWNER_NIC) ||
2088 !rt2x00_get_field32(word, TXD_W0_VALID))
2089 return;
2090
181d6902 2091 entry_done = rt2x00queue_get_entry(queue, Q_INDEX_DONE);
62bc060b 2092 while (entry != entry_done) {
181d6902
ID		 2093 /* Catch up.
2094 * Just report any entries we missed as failed.
2095 */
62bc060b 2096 WARNING(rt2x00dev,
181d6902
ID		 2097 "TX status report missed for entry %d\n",
2098 entry_done->entry_idx);
2099
fb55f4d1
ID		 2100 txdesc.flags = 0;
2101 __set_bit(TXDONE_UNKNOWN, &txdesc.flags);
181d6902
ID		 2102 txdesc.retry = 0;
2103
d74f5ba4 2104 rt2x00lib_txdone(entry_done, &txdesc);
181d6902 2105 entry_done = rt2x00queue_get_entry(queue, Q_INDEX_DONE);
62bc060b
MN		 2106 }
2107
95ea3627
ID		 2108 /*
2109 * Obtain the status about this packet.
2110 */
fb55f4d1
ID		 2111 txdesc.flags = 0;
2112 switch (rt2x00_get_field32(reg, STA_CSR4_TX_RESULT)) {
2113 case 0: /* Success, maybe with retry */
2114 __set_bit(TXDONE_SUCCESS, &txdesc.flags);
2115 break;
2116 case 6: /* Failure, excessive retries */
2117 __set_bit(TXDONE_EXCESSIVE_RETRY, &txdesc.flags);
2118 /* Don't break, this is a failed frame! */
2119 default: /* Failure */
2120 __set_bit(TXDONE_FAILURE, &txdesc.flags);
2121 }
181d6902 2122 txdesc.retry = rt2x00_get_field32(reg, STA_CSR4_RETRY_COUNT);
95ea3627 2123
d74f5ba4 2124 rt2x00lib_txdone(entry, &txdesc);
95ea3627
ID		 2125 }
2126}
2127
2128static irqreturn_t rt61pci_interrupt(int irq, void *dev_instance)
2129{
2130 struct rt2x00_dev *rt2x00dev = dev_instance;
2131 u32 reg_mcu;
2132 u32 reg;
2133
2134 /*
2135 * Get the interrupt sources & saved to local variable.
2136 * Write register value back to clear pending interrupts.
2137 */
2138 rt2x00pci_register_read(rt2x00dev, MCU_INT_SOURCE_CSR, &reg_mcu);
2139 rt2x00pci_register_write(rt2x00dev, MCU_INT_SOURCE_CSR, reg_mcu);
2140
2141 rt2x00pci_register_read(rt2x00dev, INT_SOURCE_CSR, &reg);
2142 rt2x00pci_register_write(rt2x00dev, INT_SOURCE_CSR, reg);
2143
2144 if (!reg && !reg_mcu)
2145 return IRQ_NONE;
2146
0262ab0d 2147 if (!test_bit(DEVICE_STATE_ENABLED_RADIO, &rt2x00dev->flags))
95ea3627
ID		 2148 return IRQ_HANDLED;
2149
2150 /*
2151 * Handle interrupts, walk through all bits
2152 * and run the tasks, the bits are checked in order of
2153 * priority.
2154 */
2155
2156 /*
2157 * 1 - Rx ring done interrupt.
2158 */
2159 if (rt2x00_get_field32(reg, INT_SOURCE_CSR_RXDONE))
2160 rt2x00pci_rxdone(rt2x00dev);
2161
2162 /*
2163 * 2 - Tx ring done interrupt.
2164 */
2165 if (rt2x00_get_field32(reg, INT_SOURCE_CSR_TXDONE))
2166 rt61pci_txdone(rt2x00dev);
2167
2168 /*
2169 * 3 - Handle MCU command done.
2170 */
2171 if (reg_mcu)
2172 rt2x00pci_register_write(rt2x00dev,
2173 M2H_CMD_DONE_CSR, 0xffffffff);
2174
2175 return IRQ_HANDLED;
2176}
2177
2178/*
2179 * Device probe functions.
2180 */
2181static int rt61pci_validate_eeprom(struct rt2x00_dev *rt2x00dev)
2182{
2183 struct eeprom_93cx6 eeprom;
2184 u32 reg;
2185 u16 word;
2186 u8 *mac;
2187 s8 value;
2188
2189 rt2x00pci_register_read(rt2x00dev, E2PROM_CSR, &reg);
2190
2191 eeprom.data = rt2x00dev;
2192 eeprom.register_read = rt61pci_eepromregister_read;
2193 eeprom.register_write = rt61pci_eepromregister_write;
2194 eeprom.width = rt2x00_get_field32(reg, E2PROM_CSR_TYPE_93C46) ?
2195 PCI_EEPROM_WIDTH_93C46 : PCI_EEPROM_WIDTH_93C66;
2196 eeprom.reg_data_in = 0;
2197 eeprom.reg_data_out = 0;
2198 eeprom.reg_data_clock = 0;
2199 eeprom.reg_chip_select = 0;
2200
2201 eeprom_93cx6_multiread(&eeprom, EEPROM_BASE, rt2x00dev->eeprom,
2202 EEPROM_SIZE / sizeof(u16));
2203
2204 /*
2205 * Start validation of the data that has been read.
2206 */
2207 mac = rt2x00_eeprom_addr(rt2x00dev, EEPROM_MAC_ADDR_0);
2208 if (!is_valid_ether_addr(mac)) {
2209 random_ether_addr(mac);
e174961c 2210 EEPROM(rt2x00dev, "MAC: %pM\n", mac);
95ea3627
ID		 2211 }
2212
2213 rt2x00_eeprom_read(rt2x00dev, EEPROM_ANTENNA, &word);
2214 if (word == 0xffff) {
2215 rt2x00_set_field16(&word, EEPROM_ANTENNA_NUM, 2);
362f3b6b
ID		 2216 rt2x00_set_field16(&word, EEPROM_ANTENNA_TX_DEFAULT,
2217 ANTENNA_B);
2218 rt2x00_set_field16(&word, EEPROM_ANTENNA_RX_DEFAULT,
2219 ANTENNA_B);
95ea3627
ID		 2220 rt2x00_set_field16(&word, EEPROM_ANTENNA_FRAME_TYPE, 0);
2221 rt2x00_set_field16(&word, EEPROM_ANTENNA_DYN_TXAGC, 0);
2222 rt2x00_set_field16(&word, EEPROM_ANTENNA_HARDWARE_RADIO, 0);
2223 rt2x00_set_field16(&word, EEPROM_ANTENNA_RF_TYPE, RF5225);
2224 rt2x00_eeprom_write(rt2x00dev, EEPROM_ANTENNA, word);
2225 EEPROM(rt2x00dev, "Antenna: 0x%04x\n", word);
2226 }
2227
2228 rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC, &word);
2229 if (word == 0xffff) {
2230 rt2x00_set_field16(&word, EEPROM_NIC_ENABLE_DIVERSITY, 0);
2231 rt2x00_set_field16(&word, EEPROM_NIC_TX_DIVERSITY, 0);
91581b62
ID		 2232 rt2x00_set_field16(&word, EEPROM_NIC_RX_FIXED, 0);
2233 rt2x00_set_field16(&word, EEPROM_NIC_TX_FIXED, 0);
95ea3627
ID		 2234 rt2x00_set_field16(&word, EEPROM_NIC_EXTERNAL_LNA_BG, 0);
2235 rt2x00_set_field16(&word, EEPROM_NIC_CARDBUS_ACCEL, 0);
2236 rt2x00_set_field16(&word, EEPROM_NIC_EXTERNAL_LNA_A, 0);
2237 rt2x00_eeprom_write(rt2x00dev, EEPROM_NIC, word);
2238 EEPROM(rt2x00dev, "NIC: 0x%04x\n", word);
2239 }
2240
2241 rt2x00_eeprom_read(rt2x00dev, EEPROM_LED, &word);
2242 if (word == 0xffff) {
2243 rt2x00_set_field16(&word, EEPROM_LED_LED_MODE,
2244 LED_MODE_DEFAULT);
2245 rt2x00_eeprom_write(rt2x00dev, EEPROM_LED, word);
2246 EEPROM(rt2x00dev, "Led: 0x%04x\n", word);
2247 }
2248
2249 rt2x00_eeprom_read(rt2x00dev, EEPROM_FREQ, &word);
2250 if (word == 0xffff) {
2251 rt2x00_set_field16(&word, EEPROM_FREQ_OFFSET, 0);
2252 rt2x00_set_field16(&word, EEPROM_FREQ_SEQ, 0);
2253 rt2x00_eeprom_write(rt2x00dev, EEPROM_FREQ, word);
2254 EEPROM(rt2x00dev, "Freq: 0x%04x\n", word);
2255 }
2256
2257 rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_OFFSET_BG, &word);
2258 if (word == 0xffff) {
2259 rt2x00_set_field16(&word, EEPROM_RSSI_OFFSET_BG_1, 0);
2260 rt2x00_set_field16(&word, EEPROM_RSSI_OFFSET_BG_2, 0);
2261 rt2x00_eeprom_write(rt2x00dev, EEPROM_RSSI_OFFSET_BG, word);
2262 EEPROM(rt2x00dev, "RSSI OFFSET BG: 0x%04x\n", word);
2263 } else {
2264 value = rt2x00_get_field16(word, EEPROM_RSSI_OFFSET_BG_1);
2265 if (value < -10 || value > 10)
2266 rt2x00_set_field16(&word, EEPROM_RSSI_OFFSET_BG_1, 0);
2267 value = rt2x00_get_field16(word, EEPROM_RSSI_OFFSET_BG_2);
2268 if (value < -10 || value > 10)
2269 rt2x00_set_field16(&word, EEPROM_RSSI_OFFSET_BG_2, 0);
2270 rt2x00_eeprom_write(rt2x00dev, EEPROM_RSSI_OFFSET_BG, word);
2271 }
2272
2273 rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_OFFSET_A, &word);
2274 if (word == 0xffff) {
2275 rt2x00_set_field16(&word, EEPROM_RSSI_OFFSET_A_1, 0);
2276 rt2x00_set_field16(&word, EEPROM_RSSI_OFFSET_A_2, 0);
2277 rt2x00_eeprom_write(rt2x00dev, EEPROM_RSSI_OFFSET_A, word);
417f412f 2278 EEPROM(rt2x00dev, "RSSI OFFSET A: 0x%04x\n", word);
95ea3627
ID		 2279 } else {
2280 value = rt2x00_get_field16(word, EEPROM_RSSI_OFFSET_A_1);
2281 if (value < -10 || value > 10)
2282 rt2x00_set_field16(&word, EEPROM_RSSI_OFFSET_A_1, 0);
2283 value = rt2x00_get_field16(word, EEPROM_RSSI_OFFSET_A_2);
2284 if (value < -10 || value > 10)
2285 rt2x00_set_field16(&word, EEPROM_RSSI_OFFSET_A_2, 0);
2286 rt2x00_eeprom_write(rt2x00dev, EEPROM_RSSI_OFFSET_A, word);
2287 }
2288
2289 return 0;
2290}
2291
2292static int rt61pci_init_eeprom(struct rt2x00_dev *rt2x00dev)
2293{
2294 u32 reg;
2295 u16 value;
2296 u16 eeprom;
95ea3627
ID		 2297
2298 /*
2299 * Read EEPROM word for configuration.
2300 */
2301 rt2x00_eeprom_read(rt2x00dev, EEPROM_ANTENNA, &eeprom);
2302
2303 /*
2304 * Identify RF chipset.
95ea3627 2305 */
95ea3627
ID		 2306 value = rt2x00_get_field16(eeprom, EEPROM_ANTENNA_RF_TYPE);
2307 rt2x00pci_register_read(rt2x00dev, MAC_CSR0, &reg);
440ddada 2308 rt2x00_set_chip_rf(rt2x00dev, value, reg);
95ea3627
ID		 2309
2310 if (!rt2x00_rf(&rt2x00dev->chip, RF5225) &&
2311 !rt2x00_rf(&rt2x00dev->chip, RF5325) &&
2312 !rt2x00_rf(&rt2x00dev->chip, RF2527) &&
2313 !rt2x00_rf(&rt2x00dev->chip, RF2529)) {
2314 ERROR(rt2x00dev, "Invalid RF chipset detected.\n");
2315 return -ENODEV;
2316 }
2317
e4cd2ff8
ID		 2318 /*
2319 * Determine number of antenna's.
2320 */
2321 if (rt2x00_get_field16(eeprom, EEPROM_ANTENNA_NUM) == 2)
2322 __set_bit(CONFIG_DOUBLE_ANTENNA, &rt2x00dev->flags);
2323
95ea3627
ID		 2324 /*
2325 * Identify default antenna configuration.
2326 */
addc81bd 2327 rt2x00dev->default_ant.tx =
95ea3627 2328 rt2x00_get_field16(eeprom, EEPROM_ANTENNA_TX_DEFAULT);
addc81bd 2329 rt2x00dev->default_ant.rx =
95ea3627
ID		 2330 rt2x00_get_field16(eeprom, EEPROM_ANTENNA_RX_DEFAULT);
2331
2332 /*
2333 * Read the Frame type.
2334 */
2335 if (rt2x00_get_field16(eeprom, EEPROM_ANTENNA_FRAME_TYPE))
2336 __set_bit(CONFIG_FRAME_TYPE, &rt2x00dev->flags);
2337
95ea3627
ID		 2338 /*
2339 * Detect if this device has an hardware controlled radio.
2340 */
58169529 2341#ifdef CONFIG_RT2X00_LIB_RFKILL
95ea3627 2342 if (rt2x00_get_field16(eeprom, EEPROM_ANTENNA_HARDWARE_RADIO))
066cb637 2343 __set_bit(CONFIG_SUPPORT_HW_BUTTON, &rt2x00dev->flags);
58169529 2344#endif /* CONFIG_RT2X00_LIB_RFKILL */
95ea3627
ID		 2345
2346 /*
2347 * Read frequency offset and RF programming sequence.
2348 */
2349 rt2x00_eeprom_read(rt2x00dev, EEPROM_FREQ, &eeprom);
2350 if (rt2x00_get_field16(eeprom, EEPROM_FREQ_SEQ))
2351 __set_bit(CONFIG_RF_SEQUENCE, &rt2x00dev->flags);
2352
2353 rt2x00dev->freq_offset = rt2x00_get_field16(eeprom, EEPROM_FREQ_OFFSET);
2354
2355 /*
2356 * Read external LNA informations.
2357 */
2358 rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC, &eeprom);
2359
2360 if (rt2x00_get_field16(eeprom, EEPROM_NIC_EXTERNAL_LNA_A))
2361 __set_bit(CONFIG_EXTERNAL_LNA_A, &rt2x00dev->flags);
2362 if (rt2x00_get_field16(eeprom, EEPROM_NIC_EXTERNAL_LNA_BG))
2363 __set_bit(CONFIG_EXTERNAL_LNA_BG, &rt2x00dev->flags);
2364
e4cd2ff8
ID		 2365 /*
2366 * When working with a RF2529 chip without double antenna
2367 * the antenna settings should be gathered from the NIC
2368 * eeprom word.
2369 */
2370 if (rt2x00_rf(&rt2x00dev->chip, RF2529) &&
2371 !test_bit(CONFIG_DOUBLE_ANTENNA, &rt2x00dev->flags)) {
91581b62
ID		 2372 rt2x00dev->default_ant.rx =
2373 ANTENNA_A + rt2x00_get_field16(eeprom, EEPROM_NIC_RX_FIXED);
2374 rt2x00dev->default_ant.tx =
2375 ANTENNA_B - rt2x00_get_field16(eeprom, EEPROM_NIC_TX_FIXED);
e4cd2ff8
ID		 2376
2377 if (rt2x00_get_field16(eeprom, EEPROM_NIC_TX_DIVERSITY))
2378 rt2x00dev->default_ant.tx = ANTENNA_SW_DIVERSITY;
2379 if (rt2x00_get_field16(eeprom, EEPROM_NIC_ENABLE_DIVERSITY))
2380 rt2x00dev->default_ant.rx = ANTENNA_SW_DIVERSITY;
2381 }
2382
95ea3627
ID		 2383 /*
2384 * Store led settings, for correct led behaviour.
2385 * If the eeprom value is invalid,
2386 * switch to default led mode.
2387 */
771fd565 2388#ifdef CONFIG_RT2X00_LIB_LEDS
95ea3627 2389 rt2x00_eeprom_read(rt2x00dev, EEPROM_LED, &eeprom);
a9450b70
ID		 2390 value = rt2x00_get_field16(eeprom, EEPROM_LED_LED_MODE);
2391
475433be
ID		 2392 rt61pci_init_led(rt2x00dev, &rt2x00dev->led_radio, LED_TYPE_RADIO);
2393 rt61pci_init_led(rt2x00dev, &rt2x00dev->led_assoc, LED_TYPE_ASSOC);
2394 if (value == LED_MODE_SIGNAL_STRENGTH)
2395 rt61pci_init_led(rt2x00dev, &rt2x00dev->led_qual,
2396 LED_TYPE_QUALITY);
95ea3627 2397
a9450b70
ID		 2398 rt2x00_set_field16(&rt2x00dev->led_mcu_reg, MCU_LEDCS_LED_MODE, value);
2399 rt2x00_set_field16(&rt2x00dev->led_mcu_reg, MCU_LEDCS_POLARITY_GPIO_0,
95ea3627
ID		 2400 rt2x00_get_field16(eeprom,
2401 EEPROM_LED_POLARITY_GPIO_0));
a9450b70 2402 rt2x00_set_field16(&rt2x00dev->led_mcu_reg, MCU_LEDCS_POLARITY_GPIO_1,
95ea3627
ID		 2403 rt2x00_get_field16(eeprom,
2404 EEPROM_LED_POLARITY_GPIO_1));
a9450b70 2405 rt2x00_set_field16(&rt2x00dev->led_mcu_reg, MCU_LEDCS_POLARITY_GPIO_2,
95ea3627
ID		 2406 rt2x00_get_field16(eeprom,
2407 EEPROM_LED_POLARITY_GPIO_2));
a9450b70 2408 rt2x00_set_field16(&rt2x00dev->led_mcu_reg, MCU_LEDCS_POLARITY_GPIO_3,
95ea3627
ID		 2409 rt2x00_get_field16(eeprom,
2410 EEPROM_LED_POLARITY_GPIO_3));
a9450b70 2411 rt2x00_set_field16(&rt2x00dev->led_mcu_reg, MCU_LEDCS_POLARITY_GPIO_4,
95ea3627
ID		 2412 rt2x00_get_field16(eeprom,
2413 EEPROM_LED_POLARITY_GPIO_4));
a9450b70 2414 rt2x00_set_field16(&rt2x00dev->led_mcu_reg, MCU_LEDCS_POLARITY_ACT,
95ea3627 2415 rt2x00_get_field16(eeprom, EEPROM_LED_POLARITY_ACT));
a9450b70 2416 rt2x00_set_field16(&rt2x00dev->led_mcu_reg, MCU_LEDCS_POLARITY_READY_BG,
95ea3627
ID		 2417 rt2x00_get_field16(eeprom,
2418 EEPROM_LED_POLARITY_RDY_G));
a9450b70 2419 rt2x00_set_field16(&rt2x00dev->led_mcu_reg, MCU_LEDCS_POLARITY_READY_A,
95ea3627
ID		 2420 rt2x00_get_field16(eeprom,
2421 EEPROM_LED_POLARITY_RDY_A));
771fd565 2422#endif /* CONFIG_RT2X00_LIB_LEDS */
95ea3627
ID		 2423
2424 return 0;
2425}
2426
2427/*
2428 * RF value list for RF5225 & RF5325
2429 * Supports: 2.4 GHz & 5.2 GHz, rf_sequence disabled
2430 */
2431static const struct rf_channel rf_vals_noseq[] = {
2432 { 1, 0x00002ccc, 0x00004786, 0x00068455, 0x000ffa0b },
2433 { 2, 0x00002ccc, 0x00004786, 0x00068455, 0x000ffa1f },
2434 { 3, 0x00002ccc, 0x0000478a, 0x00068455, 0x000ffa0b },
2435 { 4, 0x00002ccc, 0x0000478a, 0x00068455, 0x000ffa1f },
2436 { 5, 0x00002ccc, 0x0000478e, 0x00068455, 0x000ffa0b },
2437 { 6, 0x00002ccc, 0x0000478e, 0x00068455, 0x000ffa1f },
2438 { 7, 0x00002ccc, 0x00004792, 0x00068455, 0x000ffa0b },
2439 { 8, 0x00002ccc, 0x00004792, 0x00068455, 0x000ffa1f },
2440 { 9, 0x00002ccc, 0x00004796, 0x00068455, 0x000ffa0b },
2441 { 10, 0x00002ccc, 0x00004796, 0x00068455, 0x000ffa1f },
2442 { 11, 0x00002ccc, 0x0000479a, 0x00068455, 0x000ffa0b },
2443 { 12, 0x00002ccc, 0x0000479a, 0x00068455, 0x000ffa1f },
2444 { 13, 0x00002ccc, 0x0000479e, 0x00068455, 0x000ffa0b },
2445 { 14, 0x00002ccc, 0x000047a2, 0x00068455, 0x000ffa13 },
2446
2447 /* 802.11 UNI / HyperLan 2 */
2448 { 36, 0x00002ccc, 0x0000499a, 0x0009be55, 0x000ffa23 },
2449 { 40, 0x00002ccc, 0x000049a2, 0x0009be55, 0x000ffa03 },
2450 { 44, 0x00002ccc, 0x000049a6, 0x0009be55, 0x000ffa0b },
2451 { 48, 0x00002ccc, 0x000049aa, 0x0009be55, 0x000ffa13 },
2452 { 52, 0x00002ccc, 0x000049ae, 0x0009ae55, 0x000ffa1b },
2453 { 56, 0x00002ccc, 0x000049b2, 0x0009ae55, 0x000ffa23 },
2454 { 60, 0x00002ccc, 0x000049ba, 0x0009ae55, 0x000ffa03 },
2455 { 64, 0x00002ccc, 0x000049be, 0x0009ae55, 0x000ffa0b },
2456
2457 /* 802.11 HyperLan 2 */
2458 { 100, 0x00002ccc, 0x00004a2a, 0x000bae55, 0x000ffa03 },
2459 { 104, 0x00002ccc, 0x00004a2e, 0x000bae55, 0x000ffa0b },
2460 { 108, 0x00002ccc, 0x00004a32, 0x000bae55, 0x000ffa13 },
2461 { 112, 0x00002ccc, 0x00004a36, 0x000bae55, 0x000ffa1b },
2462 { 116, 0x00002ccc, 0x00004a3a, 0x000bbe55, 0x000ffa23 },
2463 { 120, 0x00002ccc, 0x00004a82, 0x000bbe55, 0x000ffa03 },
2464 { 124, 0x00002ccc, 0x00004a86, 0x000bbe55, 0x000ffa0b },
2465 { 128, 0x00002ccc, 0x00004a8a, 0x000bbe55, 0x000ffa13 },
2466 { 132, 0x00002ccc, 0x00004a8e, 0x000bbe55, 0x000ffa1b },
2467 { 136, 0x00002ccc, 0x00004a92, 0x000bbe55, 0x000ffa23 },
2468
2469 /* 802.11 UNII */
2470 { 140, 0x00002ccc, 0x00004a9a, 0x000bbe55, 0x000ffa03 },
2471 { 149, 0x00002ccc, 0x00004aa2, 0x000bbe55, 0x000ffa1f },
2472 { 153, 0x00002ccc, 0x00004aa6, 0x000bbe55, 0x000ffa27 },
2473 { 157, 0x00002ccc, 0x00004aae, 0x000bbe55, 0x000ffa07 },
2474 { 161, 0x00002ccc, 0x00004ab2, 0x000bbe55, 0x000ffa0f },
2475 { 165, 0x00002ccc, 0x00004ab6, 0x000bbe55, 0x000ffa17 },
2476
2477 /* MMAC(Japan)J52 ch 34,38,42,46 */
2478 { 34, 0x00002ccc, 0x0000499a, 0x0009be55, 0x000ffa0b },
2479 { 38, 0x00002ccc, 0x0000499e, 0x0009be55, 0x000ffa13 },
2480 { 42, 0x00002ccc, 0x000049a2, 0x0009be55, 0x000ffa1b },
2481 { 46, 0x00002ccc, 0x000049a6, 0x0009be55, 0x000ffa23 },
2482};
2483
2484/*
2485 * RF value list for RF5225 & RF5325
2486 * Supports: 2.4 GHz & 5.2 GHz, rf_sequence enabled
2487 */
2488static const struct rf_channel rf_vals_seq[] = {
2489 { 1, 0x00002ccc, 0x00004786, 0x00068455, 0x000ffa0b },
2490 { 2, 0x00002ccc, 0x00004786, 0x00068455, 0x000ffa1f },
2491 { 3, 0x00002ccc, 0x0000478a, 0x00068455, 0x000ffa0b },
2492 { 4, 0x00002ccc, 0x0000478a, 0x00068455, 0x000ffa1f },
2493 { 5, 0x00002ccc, 0x0000478e, 0x00068455, 0x000ffa0b },
2494 { 6, 0x00002ccc, 0x0000478e, 0x00068455, 0x000ffa1f },
2495 { 7, 0x00002ccc, 0x00004792, 0x00068455, 0x000ffa0b },
2496 { 8, 0x00002ccc, 0x00004792, 0x00068455, 0x000ffa1f },
2497 { 9, 0x00002ccc, 0x00004796, 0x00068455, 0x000ffa0b },
2498 { 10, 0x00002ccc, 0x00004796, 0x00068455, 0x000ffa1f },
2499 { 11, 0x00002ccc, 0x0000479a, 0x00068455, 0x000ffa0b },
2500 { 12, 0x00002ccc, 0x0000479a, 0x00068455, 0x000ffa1f },
2501 { 13, 0x00002ccc, 0x0000479e, 0x00068455, 0x000ffa0b },
2502 { 14, 0x00002ccc, 0x000047a2, 0x00068455, 0x000ffa13 },
2503
2504 /* 802.11 UNI / HyperLan 2 */
2505 { 36, 0x00002cd4, 0x0004481a, 0x00098455, 0x000c0a03 },
2506 { 40, 0x00002cd0, 0x00044682, 0x00098455, 0x000c0a03 },
2507 { 44, 0x00002cd0, 0x00044686, 0x00098455, 0x000c0a1b },
2508 { 48, 0x00002cd0, 0x0004468e, 0x00098655, 0x000c0a0b },
2509 { 52, 0x00002cd0, 0x00044692, 0x00098855, 0x000c0a23 },
2510 { 56, 0x00002cd0, 0x0004469a, 0x00098c55, 0x000c0a13 },
2511 { 60, 0x00002cd0, 0x000446a2, 0x00098e55, 0x000c0a03 },
2512 { 64, 0x00002cd0, 0x000446a6, 0x00099255, 0x000c0a1b },
2513
2514 /* 802.11 HyperLan 2 */
2515 { 100, 0x00002cd4, 0x0004489a, 0x000b9855, 0x000c0a03 },
2516 { 104, 0x00002cd4, 0x000448a2, 0x000b9855, 0x000c0a03 },
2517 { 108, 0x00002cd4, 0x000448aa, 0x000b9855, 0x000c0a03 },
2518 { 112, 0x00002cd4, 0x000448b2, 0x000b9a55, 0x000c0a03 },
2519 { 116, 0x00002cd4, 0x000448ba, 0x000b9a55, 0x000c0a03 },
2520 { 120, 0x00002cd0, 0x00044702, 0x000b9a55, 0x000c0a03 },
2521 { 124, 0x00002cd0, 0x00044706, 0x000b9a55, 0x000c0a1b },
2522 { 128, 0x00002cd0, 0x0004470e, 0x000b9c55, 0x000c0a0b },
2523 { 132, 0x00002cd0, 0x00044712, 0x000b9c55, 0x000c0a23 },
2524 { 136, 0x00002cd0, 0x0004471a, 0x000b9e55, 0x000c0a13 },
2525
2526 /* 802.11 UNII */
2527 { 140, 0x00002cd0, 0x00044722, 0x000b9e55, 0x000c0a03 },
2528 { 149, 0x00002cd0, 0x0004472e, 0x000ba255, 0x000c0a1b },
2529 { 153, 0x00002cd0, 0x00044736, 0x000ba255, 0x000c0a0b },
2530 { 157, 0x00002cd4, 0x0004490a, 0x000ba255, 0x000c0a17 },
2531 { 161, 0x00002cd4, 0x00044912, 0x000ba255, 0x000c0a17 },
2532 { 165, 0x00002cd4, 0x0004491a, 0x000ba255, 0x000c0a17 },
2533
2534 /* MMAC(Japan)J52 ch 34,38,42,46 */
2535 { 34, 0x00002ccc, 0x0000499a, 0x0009be55, 0x000c0a0b },
2536 { 38, 0x00002ccc, 0x0000499e, 0x0009be55, 0x000c0a13 },
2537 { 42, 0x00002ccc, 0x000049a2, 0x0009be55, 0x000c0a1b },
2538 { 46, 0x00002ccc, 0x000049a6, 0x0009be55, 0x000c0a23 },
2539};
2540
8c5e7a5f 2541static int rt61pci_probe_hw_mode(struct rt2x00_dev *rt2x00dev)
95ea3627
ID		 2542{
2543 struct hw_mode_spec *spec = &rt2x00dev->spec;
8c5e7a5f
ID		 2544 struct channel_info *info;
2545 char *tx_power;
95ea3627
ID		 2546 unsigned int i;
2547
2548 /*
2549 * Initialize all hw fields.
2550 */
2551 rt2x00dev->hw->flags =
566bfe5a 2552 IEEE80211_HW_HOST_BROADCAST_PS_BUFFERING |
4be8c387
JB		 2553 IEEE80211_HW_SIGNAL_DBM |
2554 IEEE80211_HW_SUPPORTS_PS |
2555 IEEE80211_HW_PS_NULLFUNC_STACK;
95ea3627 2556 rt2x00dev->hw->extra_tx_headroom = 0;
95ea3627 2557
14a3bf89 2558 SET_IEEE80211_DEV(rt2x00dev->hw, rt2x00dev->dev);
95ea3627
ID		 2559 SET_IEEE80211_PERM_ADDR(rt2x00dev->hw,
2560 rt2x00_eeprom_addr(rt2x00dev,
2561 EEPROM_MAC_ADDR_0));
2562
95ea3627
ID		 2563 /*
2564 * Initialize hw_mode information.
2565 */
31562e80
ID		 2566 spec->supported_bands = SUPPORT_BAND_2GHZ;
2567 spec->supported_rates = SUPPORT_RATE_CCK | SUPPORT_RATE_OFDM;
95ea3627
ID		 2568
2569 if (!test_bit(CONFIG_RF_SEQUENCE, &rt2x00dev->flags)) {
2570 spec->num_channels = 14;
2571 spec->channels = rf_vals_noseq;
2572 } else {
2573 spec->num_channels = 14;
2574 spec->channels = rf_vals_seq;
2575 }
2576
2577 if (rt2x00_rf(&rt2x00dev->chip, RF5225) ||
2578 rt2x00_rf(&rt2x00dev->chip, RF5325)) {
31562e80 2579 spec->supported_bands |= SUPPORT_BAND_5GHZ;
95ea3627 2580 spec->num_channels = ARRAY_SIZE(rf_vals_seq);
8c5e7a5f
ID		 2581 }
2582
2583 /*
2584 * Create channel information array
2585 */
2586 info = kzalloc(spec->num_channels * sizeof(*info), GFP_KERNEL);
2587 if (!info)
2588 return -ENOMEM;
2589
2590 spec->channels_info = info;
95ea3627 2591
8c5e7a5f
ID		 2592 tx_power = rt2x00_eeprom_addr(rt2x00dev, EEPROM_TXPOWER_G_START);
2593 for (i = 0; i < 14; i++)
2594 info[i].tx_power1 = TXPOWER_FROM_DEV(tx_power[i]);
95ea3627 2595
8c5e7a5f
ID		 2596 if (spec->num_channels > 14) {
2597 tx_power = rt2x00_eeprom_addr(rt2x00dev, EEPROM_TXPOWER_A_START);
2598 for (i = 14; i < spec->num_channels; i++)
2599 info[i].tx_power1 = TXPOWER_FROM_DEV(tx_power[i]);
95ea3627 2600 }
8c5e7a5f
ID		 2601
2602 return 0;
95ea3627
ID		 2603}
2604
2605static int rt61pci_probe_hw(struct rt2x00_dev *rt2x00dev)
2606{
2607 int retval;
2608
2609 /*
2610 * Allocate eeprom data.
2611 */
2612 retval = rt61pci_validate_eeprom(rt2x00dev);
2613 if (retval)
2614 return retval;
2615
2616 retval = rt61pci_init_eeprom(rt2x00dev);
2617 if (retval)
2618 return retval;
2619
2620 /*
2621 * Initialize hw specifications.
2622 */
8c5e7a5f
ID		 2623 retval = rt61pci_probe_hw_mode(rt2x00dev);
2624 if (retval)
2625 return retval;
95ea3627
ID		 2626
2627 /*
c4da0048 2628 * This device requires firmware and DMA mapped skbs.
95ea3627 2629 */
066cb637 2630 __set_bit(DRIVER_REQUIRE_FIRMWARE, &rt2x00dev->flags);
c4da0048 2631 __set_bit(DRIVER_REQUIRE_DMA, &rt2x00dev->flags);
008c4482
ID		 2632 if (!modparam_nohwcrypt)
2633 __set_bit(CONFIG_SUPPORT_HW_CRYPTO, &rt2x00dev->flags);
95ea3627
ID		 2634
2635 /*
2636 * Set the rssi offset.
2637 */
2638 rt2x00dev->rssi_offset = DEFAULT_RSSI_OFFSET;
2639
2640 return 0;
2641}
2642
2643/*
2644 * IEEE80211 stack callback functions.
2645 */
2af0a570
ID		 2646static int rt61pci_conf_tx(struct ieee80211_hw *hw, u16 queue_idx,
2647 const struct ieee80211_tx_queue_params *params)
2648{
2649 struct rt2x00_dev *rt2x00dev = hw->priv;
2650 struct data_queue *queue;
2651 struct rt2x00_field32 field;
2652 int retval;
2653 u32 reg;
5e790023 2654 u32 offset;
2af0a570
ID		 2655
2656 /*
2657 * First pass the configuration through rt2x00lib, that will
2658 * update the queue settings and validate the input. After that
2659 * we are free to update the registers based on the value
2660 * in the queue parameter.
2661 */
2662 retval = rt2x00mac_conf_tx(hw, queue_idx, params);
2663 if (retval)
2664 return retval;
2665
5e790023
ID		 2666 /*
2667 * We only need to perform additional register initialization
2668 * for WMM queues/
2669 */
2670 if (queue_idx >= 4)
2671 return 0;
2672
2af0a570
ID		 2673 queue = rt2x00queue_get_queue(rt2x00dev, queue_idx);
2674
2675 /* Update WMM TXOP register */
5e790023
ID		 2676 offset = AC_TXOP_CSR0 + (sizeof(u32) * (!!(queue_idx & 2)));
2677 field.bit_offset = (queue_idx & 1) * 16;
2678 field.bit_mask = 0xffff << field.bit_offset;
2679
2680 rt2x00pci_register_read(rt2x00dev, offset, &reg);
2681 rt2x00_set_field32(&reg, field, queue->txop);
2682 rt2x00pci_register_write(rt2x00dev, offset, reg);
2af0a570
ID		 2683
2684 /* Update WMM registers */
2685 field.bit_offset = queue_idx * 4;
2686 field.bit_mask = 0xf << field.bit_offset;
2687
2688 rt2x00pci_register_read(rt2x00dev, AIFSN_CSR, &reg);
2689 rt2x00_set_field32(&reg, field, queue->aifs);
2690 rt2x00pci_register_write(rt2x00dev, AIFSN_CSR, reg);
2691
2692 rt2x00pci_register_read(rt2x00dev, CWMIN_CSR, &reg);
2693 rt2x00_set_field32(&reg, field, queue->cw_min);
2694 rt2x00pci_register_write(rt2x00dev, CWMIN_CSR, reg);
2695
2696 rt2x00pci_register_read(rt2x00dev, CWMAX_CSR, &reg);
2697 rt2x00_set_field32(&reg, field, queue->cw_max);
2698 rt2x00pci_register_write(rt2x00dev, CWMAX_CSR, reg);
2699
2700 return 0;
2701}
2702
95ea3627
ID		 2703static u64 rt61pci_get_tsf(struct ieee80211_hw *hw)
2704{
2705 struct rt2x00_dev *rt2x00dev = hw->priv;
2706 u64 tsf;
2707 u32 reg;
2708
2709 rt2x00pci_register_read(rt2x00dev, TXRX_CSR13, &reg);
2710 tsf = (u64) rt2x00_get_field32(reg, TXRX_CSR13_HIGH_TSFTIMER) << 32;
2711 rt2x00pci_register_read(rt2x00dev, TXRX_CSR12, &reg);
2712 tsf |= rt2x00_get_field32(reg, TXRX_CSR12_LOW_TSFTIMER);
2713
2714 return tsf;
2715}
2716
95ea3627
ID		 2717static const struct ieee80211_ops rt61pci_mac80211_ops = {
2718 .tx = rt2x00mac_tx,
4150c572
JB		 2719 .start = rt2x00mac_start,
2720 .stop = rt2x00mac_stop,
95ea3627
ID		 2721 .add_interface = rt2x00mac_add_interface,
2722 .remove_interface = rt2x00mac_remove_interface,
2723 .config = rt2x00mac_config,
3a643d24 2724 .configure_filter = rt2x00mac_configure_filter,
61e754f4 2725 .set_key = rt2x00mac_set_key,
95ea3627 2726 .get_stats = rt2x00mac_get_stats,
471b3efd 2727 .bss_info_changed = rt2x00mac_bss_info_changed,
2af0a570 2728 .conf_tx = rt61pci_conf_tx,
95ea3627
ID		 2729 .get_tx_stats = rt2x00mac_get_tx_stats,
2730 .get_tsf = rt61pci_get_tsf,
95ea3627
ID		 2731};
2732
2733static const struct rt2x00lib_ops rt61pci_rt2x00_ops = {
2734 .irq_handler = rt61pci_interrupt,
2735 .probe_hw = rt61pci_probe_hw,
2736 .get_firmware_name = rt61pci_get_firmware_name,
0cbe0064 2737 .check_firmware = rt61pci_check_firmware,
95ea3627
ID		 2738 .load_firmware = rt61pci_load_firmware,
2739 .initialize = rt2x00pci_initialize,
2740 .uninitialize = rt2x00pci_uninitialize,
798b7adb
ID		 2741 .get_entry_state = rt61pci_get_entry_state,
2742 .clear_entry = rt61pci_clear_entry,
95ea3627 2743 .set_device_state = rt61pci_set_device_state,
95ea3627 2744 .rfkill_poll = rt61pci_rfkill_poll,
95ea3627
ID		 2745 .link_stats = rt61pci_link_stats,
2746 .reset_tuner = rt61pci_reset_tuner,
2747 .link_tuner = rt61pci_link_tuner,
2748 .write_tx_desc = rt61pci_write_tx_desc,
2749 .write_tx_data = rt2x00pci_write_tx_data,
bd88a781 2750 .write_beacon = rt61pci_write_beacon,
95ea3627 2751 .kick_tx_queue = rt61pci_kick_tx_queue,
a2c9b652 2752 .kill_tx_queue = rt61pci_kill_tx_queue,
95ea3627 2753 .fill_rxdone = rt61pci_fill_rxdone,
61e754f4
ID		 2754 .config_shared_key = rt61pci_config_shared_key,
2755 .config_pairwise_key = rt61pci_config_pairwise_key,
3a643d24 2756 .config_filter = rt61pci_config_filter,
6bb40dd1 2757 .config_intf = rt61pci_config_intf,
72810379 2758 .config_erp = rt61pci_config_erp,
e4ea1c40 2759 .config_ant = rt61pci_config_ant,
95ea3627
ID		 2760 .config = rt61pci_config,
2761};
2762
181d6902
ID		 2763static const struct data_queue_desc rt61pci_queue_rx = {
2764 .entry_num = RX_ENTRIES,
2765 .data_size = DATA_FRAME_SIZE,
2766 .desc_size = RXD_DESC_SIZE,
b8be63ff 2767 .priv_size = sizeof(struct queue_entry_priv_pci),
181d6902
ID		 2768};
2769
2770static const struct data_queue_desc rt61pci_queue_tx = {
2771 .entry_num = TX_ENTRIES,
2772 .data_size = DATA_FRAME_SIZE,
2773 .desc_size = TXD_DESC_SIZE,
b8be63ff 2774 .priv_size = sizeof(struct queue_entry_priv_pci),
181d6902
ID		 2775};
2776
2777static const struct data_queue_desc rt61pci_queue_bcn = {
6bb40dd1 2778 .entry_num = 4 * BEACON_ENTRIES,
78720897 2779 .data_size = 0, /* No DMA required for beacons */
181d6902 2780 .desc_size = TXINFO_SIZE,
b8be63ff 2781 .priv_size = sizeof(struct queue_entry_priv_pci),
181d6902
ID		 2782};
2783
95ea3627 2784static const struct rt2x00_ops rt61pci_ops = {
2360157c 2785 .name = KBUILD_MODNAME,
6bb40dd1
ID		 2786 .max_sta_intf = 1,
2787 .max_ap_intf = 4,
95ea3627
ID		 2788 .eeprom_size = EEPROM_SIZE,
2789 .rf_size = RF_SIZE,
61448f88 2790 .tx_queues = NUM_TX_QUEUES,
181d6902
ID		 2791 .rx = &rt61pci_queue_rx,
2792 .tx = &rt61pci_queue_tx,
2793 .bcn = &rt61pci_queue_bcn,
95ea3627
ID		 2794 .lib = &rt61pci_rt2x00_ops,
2795 .hw = &rt61pci_mac80211_ops,
2796#ifdef CONFIG_RT2X00_LIB_DEBUGFS
2797 .debugfs = &rt61pci_rt2x00debug,
2798#endif /* CONFIG_RT2X00_LIB_DEBUGFS */
2799};
2800
2801/*
2802 * RT61pci module information.
2803 */
2804static struct pci_device_id rt61pci_device_table[] = {
2805 /* RT2561s */
2806 { PCI_DEVICE(0x1814, 0x0301), PCI_DEVICE_DATA(&rt61pci_ops) },
2807 /* RT2561 v2 */
2808 { PCI_DEVICE(0x1814, 0x0302), PCI_DEVICE_DATA(&rt61pci_ops) },
2809 /* RT2661 */
2810 { PCI_DEVICE(0x1814, 0x0401), PCI_DEVICE_DATA(&rt61pci_ops) },
2811 { 0, }
2812};
2813
2814MODULE_AUTHOR(DRV_PROJECT);
2815MODULE_VERSION(DRV_VERSION);
2816MODULE_DESCRIPTION("Ralink RT61 PCI & PCMCIA Wireless LAN driver.");
2817MODULE_SUPPORTED_DEVICE("Ralink RT2561, RT2561s & RT2661 "
2818 "PCI & PCMCIA chipset based cards");
2819MODULE_DEVICE_TABLE(pci, rt61pci_device_table);
2820MODULE_FIRMWARE(FIRMWARE_RT2561);
2821MODULE_FIRMWARE(FIRMWARE_RT2561s);
2822MODULE_FIRMWARE(FIRMWARE_RT2661);
2823MODULE_LICENSE("GPL");
2824
2825static struct pci_driver rt61pci_driver = {
2360157c 2826 .name = KBUILD_MODNAME,
95ea3627
ID		 2827 .id_table = rt61pci_device_table,
2828 .probe = rt2x00pci_probe,
2829 .remove = __devexit_p(rt2x00pci_remove),
2830 .suspend = rt2x00pci_suspend,
2831 .resume = rt2x00pci_resume,
2832};
2833
2834static int __init rt61pci_init(void)
2835{
2836 return pci_register_driver(&rt61pci_driver);
2837}
2838
2839static void __exit rt61pci_exit(void)
2840{
2841 pci_unregister_driver(&rt61pci_driver);
2842}
2843
2844module_init(rt61pci_init);
2845module_exit(rt61pci_exit);
Linux kernel - Deliverables
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