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rt2x00: Reorganize queue callback functions
[deliverable/linux.git] / drivers / net / wireless / rt2x00 / rt61pci.c
CommitLineData
95ea3627 1/*
9c9a0d14 2 Copyright (C) 2004 - 2009 Ivo van Doorn <IvDoorn@gmail.com>
95ea3627
ID		 3 <http://rt2x00.serialmonkey.com>
4
5 This program is free software; you can redistribute it and/or modify
6 it under the terms of the GNU General Public License as published by
7 the Free Software Foundation; either version 2 of the License, or
8 (at your option) any later version.
9
10 This program is distributed in the hope that it will be useful,
11 but WITHOUT ANY WARRANTY; without even the implied warranty of
12 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 GNU General Public License for more details.
14
15 You should have received a copy of the GNU General Public License
16 along with this program; if not, write to the
17 Free Software Foundation, Inc.,
18 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
19 */
20
21/*
22 Module: rt61pci
23 Abstract: rt61pci device specific routines.
24 Supported chipsets: RT2561, RT2561s, RT2661.
25 */
26
a7f3a06c 27#include <linux/crc-itu-t.h>
95ea3627
ID		 28#include <linux/delay.h>
29#include <linux/etherdevice.h>
30#include <linux/init.h>
31#include <linux/kernel.h>
32#include <linux/module.h>
5a0e3ad6 33#include <linux/slab.h>
95ea3627
ID		 34#include <linux/pci.h>
35#include <linux/eeprom_93cx6.h>
36
37#include "rt2x00.h"
38#include "rt2x00pci.h"
39#include "rt61pci.h"
40
008c4482
ID		 41/*
42 * Allow hardware encryption to be disabled.
43 */
44static int modparam_nohwcrypt = 0;
45module_param_named(nohwcrypt, modparam_nohwcrypt, bool, S_IRUGO);
46MODULE_PARM_DESC(nohwcrypt, "Disable hardware encryption.");
47
95ea3627
ID		 48/*
49 * Register access.
50 * BBP and RF register require indirect register access,
51 * and use the CSR registers PHY_CSR3 and PHY_CSR4 to achieve this.
52 * These indirect registers work with busy bits,
53 * and we will try maximal REGISTER_BUSY_COUNT times to access
54 * the register while taking a REGISTER_BUSY_DELAY us delay
b34e620f 55 * between each attempt. When the busy bit is still set at that time,
95ea3627
ID		 56 * the access attempt is considered to have failed,
57 * and we will print an error.
58 */
c9c3b1a5
ID		 59#define WAIT_FOR_BBP(__dev, __reg) \
60 rt2x00pci_regbusy_read((__dev), PHY_CSR3, PHY_CSR3_BUSY, (__reg))
61#define WAIT_FOR_RF(__dev, __reg) \
62 rt2x00pci_regbusy_read((__dev), PHY_CSR4, PHY_CSR4_BUSY, (__reg))
63#define WAIT_FOR_MCU(__dev, __reg) \
64 rt2x00pci_regbusy_read((__dev), H2M_MAILBOX_CSR, \
65 H2M_MAILBOX_CSR_OWNER, (__reg))
95ea3627 66
0e14f6d3 67static void rt61pci_bbp_write(struct rt2x00_dev *rt2x00dev,
95ea3627
ID		 68 const unsigned int word, const u8 value)
69{
70 u32 reg;
71
8ff48a8b
ID		 72 mutex_lock(&rt2x00dev->csr_mutex);
73
95ea3627 74 /*
c9c3b1a5
ID		 75 * Wait until the BBP becomes available, afterwards we
76 * can safely write the new data into the register.
95ea3627 77 */
c9c3b1a5
ID		 78 if (WAIT_FOR_BBP(rt2x00dev, &reg)) {
79 reg = 0;
80 rt2x00_set_field32(&reg, PHY_CSR3_VALUE, value);
81 rt2x00_set_field32(&reg, PHY_CSR3_REGNUM, word);
82 rt2x00_set_field32(&reg, PHY_CSR3_BUSY, 1);
83 rt2x00_set_field32(&reg, PHY_CSR3_READ_CONTROL, 0);
84
85 rt2x00pci_register_write(rt2x00dev, PHY_CSR3, reg);
86 }
8ff48a8b 87
8ff48a8b 88 mutex_unlock(&rt2x00dev->csr_mutex);
95ea3627
ID		 89}
90
0e14f6d3 91static void rt61pci_bbp_read(struct rt2x00_dev *rt2x00dev,
95ea3627
ID		 92 const unsigned int word, u8 *value)
93{
94 u32 reg;
95
8ff48a8b
ID		 96 mutex_lock(&rt2x00dev->csr_mutex);
97
95ea3627 98 /*
c9c3b1a5
ID		 99 * Wait until the BBP becomes available, afterwards we
100 * can safely write the read request into the register.
101 * After the data has been written, we wait until hardware
102 * returns the correct value, if at any time the register
103 * doesn't become available in time, reg will be 0xffffffff
104 * which means we return 0xff to the caller.
95ea3627 105 */
c9c3b1a5
ID		 106 if (WAIT_FOR_BBP(rt2x00dev, &reg)) {
107 reg = 0;
108 rt2x00_set_field32(&reg, PHY_CSR3_REGNUM, word);
109 rt2x00_set_field32(&reg, PHY_CSR3_BUSY, 1);
110 rt2x00_set_field32(&reg, PHY_CSR3_READ_CONTROL, 1);
95ea3627 111
c9c3b1a5 112 rt2x00pci_register_write(rt2x00dev, PHY_CSR3, reg);
95ea3627 113
c9c3b1a5
ID		 114 WAIT_FOR_BBP(rt2x00dev, &reg);
115 }
95ea3627
ID		 116
117 *value = rt2x00_get_field32(reg, PHY_CSR3_VALUE);
8ff48a8b 118
8ff48a8b 119 mutex_unlock(&rt2x00dev->csr_mutex);
95ea3627
ID		 120}
121
0e14f6d3 122static void rt61pci_rf_write(struct rt2x00_dev *rt2x00dev,
95ea3627
ID		 123 const unsigned int word, const u32 value)
124{
125 u32 reg;
95ea3627 126
8ff48a8b
ID		 127 mutex_lock(&rt2x00dev->csr_mutex);
128
c9c3b1a5
ID		 129 /*
130 * Wait until the RF becomes available, afterwards we
131 * can safely write the new data into the register.
132 */
133 if (WAIT_FOR_RF(rt2x00dev, &reg)) {
134 reg = 0;
135 rt2x00_set_field32(&reg, PHY_CSR4_VALUE, value);
136 rt2x00_set_field32(&reg, PHY_CSR4_NUMBER_OF_BITS, 21);
137 rt2x00_set_field32(&reg, PHY_CSR4_IF_SELECT, 0);
138 rt2x00_set_field32(&reg, PHY_CSR4_BUSY, 1);
139
140 rt2x00pci_register_write(rt2x00dev, PHY_CSR4, reg);
141 rt2x00_rf_write(rt2x00dev, word, value);
95ea3627
ID		 142 }
143
8ff48a8b 144 mutex_unlock(&rt2x00dev->csr_mutex);
95ea3627
ID		 145}
146
0e14f6d3 147static void rt61pci_mcu_request(struct rt2x00_dev *rt2x00dev,
95ea3627
ID		 148 const u8 command, const u8 token,
149 const u8 arg0, const u8 arg1)
150{
151 u32 reg;
152
8ff48a8b
ID		 153 mutex_lock(&rt2x00dev->csr_mutex);
154
c9c3b1a5
ID		 155 /*
156 * Wait until the MCU becomes available, afterwards we
157 * can safely write the new data into the register.
158 */
159 if (WAIT_FOR_MCU(rt2x00dev, &reg)) {
160 rt2x00_set_field32(&reg, H2M_MAILBOX_CSR_OWNER, 1);
161 rt2x00_set_field32(&reg, H2M_MAILBOX_CSR_CMD_TOKEN, token);
162 rt2x00_set_field32(&reg, H2M_MAILBOX_CSR_ARG0, arg0);
163 rt2x00_set_field32(&reg, H2M_MAILBOX_CSR_ARG1, arg1);
164 rt2x00pci_register_write(rt2x00dev, H2M_MAILBOX_CSR, reg);
165
166 rt2x00pci_register_read(rt2x00dev, HOST_CMD_CSR, &reg);
167 rt2x00_set_field32(&reg, HOST_CMD_CSR_HOST_COMMAND, command);
168 rt2x00_set_field32(&reg, HOST_CMD_CSR_INTERRUPT_MCU, 1);
169 rt2x00pci_register_write(rt2x00dev, HOST_CMD_CSR, reg);
170 }
8ff48a8b 171
8ff48a8b
ID		 172 mutex_unlock(&rt2x00dev->csr_mutex);
173
95ea3627
ID		 174}
175
176static void rt61pci_eepromregister_read(struct eeprom_93cx6 *eeprom)
177{
178 struct rt2x00_dev *rt2x00dev = eeprom->data;
179 u32 reg;
180
181 rt2x00pci_register_read(rt2x00dev, E2PROM_CSR, &reg);
182
183 eeprom->reg_data_in = !!rt2x00_get_field32(reg, E2PROM_CSR_DATA_IN);
184 eeprom->reg_data_out = !!rt2x00_get_field32(reg, E2PROM_CSR_DATA_OUT);
185 eeprom->reg_data_clock =
186 !!rt2x00_get_field32(reg, E2PROM_CSR_DATA_CLOCK);
187 eeprom->reg_chip_select =
188 !!rt2x00_get_field32(reg, E2PROM_CSR_CHIP_SELECT);
189}
190
191static void rt61pci_eepromregister_write(struct eeprom_93cx6 *eeprom)
192{
193 struct rt2x00_dev *rt2x00dev = eeprom->data;
194 u32 reg = 0;
195
196 rt2x00_set_field32(&reg, E2PROM_CSR_DATA_IN, !!eeprom->reg_data_in);
197 rt2x00_set_field32(&reg, E2PROM_CSR_DATA_OUT, !!eeprom->reg_data_out);
198 rt2x00_set_field32(&reg, E2PROM_CSR_DATA_CLOCK,
199 !!eeprom->reg_data_clock);
200 rt2x00_set_field32(&reg, E2PROM_CSR_CHIP_SELECT,
201 !!eeprom->reg_chip_select);
202
203 rt2x00pci_register_write(rt2x00dev, E2PROM_CSR, reg);
204}
205
206#ifdef CONFIG_RT2X00_LIB_DEBUGFS
95ea3627
ID		 207static const struct rt2x00debug rt61pci_rt2x00debug = {
208 .owner = THIS_MODULE,
209 .csr = {
743b97ca
ID		 210 .read = rt2x00pci_register_read,
211 .write = rt2x00pci_register_write,
212 .flags = RT2X00DEBUGFS_OFFSET,
213 .word_base = CSR_REG_BASE,
95ea3627
ID		 214 .word_size = sizeof(u32),
215 .word_count = CSR_REG_SIZE / sizeof(u32),
216 },
217 .eeprom = {
218 .read = rt2x00_eeprom_read,
219 .write = rt2x00_eeprom_write,
743b97ca 220 .word_base = EEPROM_BASE,
95ea3627
ID		 221 .word_size = sizeof(u16),
222 .word_count = EEPROM_SIZE / sizeof(u16),
223 },
224 .bbp = {
225 .read = rt61pci_bbp_read,
226 .write = rt61pci_bbp_write,
743b97ca 227 .word_base = BBP_BASE,
95ea3627
ID		 228 .word_size = sizeof(u8),
229 .word_count = BBP_SIZE / sizeof(u8),
230 },
231 .rf = {
232 .read = rt2x00_rf_read,
233 .write = rt61pci_rf_write,
743b97ca 234 .word_base = RF_BASE,
95ea3627
ID		 235 .word_size = sizeof(u32),
236 .word_count = RF_SIZE / sizeof(u32),
237 },
238};
239#endif /* CONFIG_RT2X00_LIB_DEBUGFS */
240
95ea3627
ID		 241static int rt61pci_rfkill_poll(struct rt2x00_dev *rt2x00dev)
242{
243 u32 reg;
244
245 rt2x00pci_register_read(rt2x00dev, MAC_CSR13, &reg);
181d6902 246 return rt2x00_get_field32(reg, MAC_CSR13_BIT5);
95ea3627 247}
95ea3627 248
771fd565 249#ifdef CONFIG_RT2X00_LIB_LEDS
a2e1d52a 250static void rt61pci_brightness_set(struct led_classdev *led_cdev,
a9450b70
ID		 251 enum led_brightness brightness)
252{
253 struct rt2x00_led *led =
254 container_of(led_cdev, struct rt2x00_led, led_dev);
255 unsigned int enabled = brightness != LED_OFF;
256 unsigned int a_mode =
257 (enabled && led->rt2x00dev->curr_band == IEEE80211_BAND_5GHZ);
258 unsigned int bg_mode =
259 (enabled && led->rt2x00dev->curr_band == IEEE80211_BAND_2GHZ);
260
261 if (led->type == LED_TYPE_RADIO) {
262 rt2x00_set_field16(&led->rt2x00dev->led_mcu_reg,
263 MCU_LEDCS_RADIO_STATUS, enabled);
264
265 rt61pci_mcu_request(led->rt2x00dev, MCU_LED, 0xff,
266 (led->rt2x00dev->led_mcu_reg & 0xff),
267 ((led->rt2x00dev->led_mcu_reg >> 8)));
268 } else if (led->type == LED_TYPE_ASSOC) {
269 rt2x00_set_field16(&led->rt2x00dev->led_mcu_reg,
270 MCU_LEDCS_LINK_BG_STATUS, bg_mode);
271 rt2x00_set_field16(&led->rt2x00dev->led_mcu_reg,
272 MCU_LEDCS_LINK_A_STATUS, a_mode);
273
274 rt61pci_mcu_request(led->rt2x00dev, MCU_LED, 0xff,
275 (led->rt2x00dev->led_mcu_reg & 0xff),
276 ((led->rt2x00dev->led_mcu_reg >> 8)));
277 } else if (led->type == LED_TYPE_QUALITY) {
278 /*
279 * The brightness is divided into 6 levels (0 - 5),
280 * this means we need to convert the brightness
281 * argument into the matching level within that range.
282 */
283 rt61pci_mcu_request(led->rt2x00dev, MCU_LED_STRENGTH, 0xff,
284 brightness / (LED_FULL / 6), 0);
285 }
286}
a2e1d52a
ID		 287
288static int rt61pci_blink_set(struct led_classdev *led_cdev,
289 unsigned long *delay_on,
290 unsigned long *delay_off)
291{
292 struct rt2x00_led *led =
293 container_of(led_cdev, struct rt2x00_led, led_dev);
294 u32 reg;
295
296 rt2x00pci_register_read(led->rt2x00dev, MAC_CSR14, &reg);
297 rt2x00_set_field32(&reg, MAC_CSR14_ON_PERIOD, *delay_on);
298 rt2x00_set_field32(&reg, MAC_CSR14_OFF_PERIOD, *delay_off);
299 rt2x00pci_register_write(led->rt2x00dev, MAC_CSR14, reg);
300
301 return 0;
302}
475433be
ID		 303
304static void rt61pci_init_led(struct rt2x00_dev *rt2x00dev,
305 struct rt2x00_led *led,
306 enum led_type type)
307{
308 led->rt2x00dev = rt2x00dev;
309 led->type = type;
310 led->led_dev.brightness_set = rt61pci_brightness_set;
311 led->led_dev.blink_set = rt61pci_blink_set;
312 led->flags = LED_INITIALIZED;
313}
771fd565 314#endif /* CONFIG_RT2X00_LIB_LEDS */
a9450b70 315
95ea3627
ID		 316/*
317 * Configuration handlers.
318 */
61e754f4
ID		 319static int rt61pci_config_shared_key(struct rt2x00_dev *rt2x00dev,
320 struct rt2x00lib_crypto *crypto,
321 struct ieee80211_key_conf *key)
322{
323 struct hw_key_entry key_entry;
324 struct rt2x00_field32 field;
325 u32 mask;
326 u32 reg;
327
328 if (crypto->cmd == SET_KEY) {
329 /*
330 * rt2x00lib can't determine the correct free
331 * key_idx for shared keys. We have 1 register
332 * with key valid bits. The goal is simple, read
333 * the register, if that is full we have no slots
334 * left.
335 * Note that each BSS is allowed to have up to 4
336 * shared keys, so put a mask over the allowed
337 * entries.
338 */
339 mask = (0xf << crypto->bssidx);
340
341 rt2x00pci_register_read(rt2x00dev, SEC_CSR0, &reg);
342 reg &= mask;
343
344 if (reg && reg == mask)
345 return -ENOSPC;
346
acaf908d 347 key->hw_key_idx += reg ? ffz(reg) : 0;
61e754f4
ID		 348
349 /*
350 * Upload key to hardware
351 */
352 memcpy(key_entry.key, crypto->key,
353 sizeof(key_entry.key));
354 memcpy(key_entry.tx_mic, crypto->tx_mic,
355 sizeof(key_entry.tx_mic));
356 memcpy(key_entry.rx_mic, crypto->rx_mic,
357 sizeof(key_entry.rx_mic));
358
359 reg = SHARED_KEY_ENTRY(key->hw_key_idx);
360 rt2x00pci_register_multiwrite(rt2x00dev, reg,
361 &key_entry, sizeof(key_entry));
362
363 /*
364 * The cipher types are stored over 2 registers.
365 * bssidx 0 and 1 keys are stored in SEC_CSR1 and
366 * bssidx 1 and 2 keys are stored in SEC_CSR5.
367 * Using the correct defines correctly will cause overhead,
368 * so just calculate the correct offset.
369 */
370 if (key->hw_key_idx < 8) {
371 field.bit_offset = (3 * key->hw_key_idx);
372 field.bit_mask = 0x7 << field.bit_offset;
373
374 rt2x00pci_register_read(rt2x00dev, SEC_CSR1, &reg);
375 rt2x00_set_field32(&reg, field, crypto->cipher);
376 rt2x00pci_register_write(rt2x00dev, SEC_CSR1, reg);
377 } else {
378 field.bit_offset = (3 * (key->hw_key_idx - 8));
379 field.bit_mask = 0x7 << field.bit_offset;
380
381 rt2x00pci_register_read(rt2x00dev, SEC_CSR5, &reg);
382 rt2x00_set_field32(&reg, field, crypto->cipher);
383 rt2x00pci_register_write(rt2x00dev, SEC_CSR5, reg);
384 }
385
386 /*
387 * The driver does not support the IV/EIV generation
388 * in hardware. However it doesn't support the IV/EIV
389 * inside the ieee80211 frame either, but requires it
b34e620f 390 * to be provided separately for the descriptor.
61e754f4
ID		 391 * rt2x00lib will cut the IV/EIV data out of all frames
392 * given to us by mac80211, but we must tell mac80211
393 * to generate the IV/EIV data.
394 */
395 key->flags |= IEEE80211_KEY_FLAG_GENERATE_IV;
396 }
397
398 /*
399 * SEC_CSR0 contains only single-bit fields to indicate
400 * a particular key is valid. Because using the FIELD32()
b34e620f 401 * defines directly will cause a lot of overhead, we use
61e754f4
ID		 402 * a calculation to determine the correct bit directly.
403 */
404 mask = 1 << key->hw_key_idx;
405
406 rt2x00pci_register_read(rt2x00dev, SEC_CSR0, &reg);
407 if (crypto->cmd == SET_KEY)
408 reg |= mask;
409 else if (crypto->cmd == DISABLE_KEY)
410 reg &= ~mask;
411 rt2x00pci_register_write(rt2x00dev, SEC_CSR0, reg);
412
413 return 0;
414}
415
416static int rt61pci_config_pairwise_key(struct rt2x00_dev *rt2x00dev,
417 struct rt2x00lib_crypto *crypto,
418 struct ieee80211_key_conf *key)
419{
420 struct hw_pairwise_ta_entry addr_entry;
421 struct hw_key_entry key_entry;
422 u32 mask;
423 u32 reg;
424
425 if (crypto->cmd == SET_KEY) {
426 /*
427 * rt2x00lib can't determine the correct free
428 * key_idx for pairwise keys. We have 2 registers
b34e620f
TLSC		 429 * with key valid bits. The goal is simple: read
430 * the first register. If that is full, move to
61e754f4 431 * the next register.
b34e620f
TLSC		 432 * When both registers are full, we drop the key.
433 * Otherwise, we use the first invalid entry.
61e754f4
ID		 434 */
435 rt2x00pci_register_read(rt2x00dev, SEC_CSR2, &reg);
436 if (reg && reg == ~0) {
437 key->hw_key_idx = 32;
438 rt2x00pci_register_read(rt2x00dev, SEC_CSR3, &reg);
439 if (reg && reg == ~0)
440 return -ENOSPC;
441 }
442
acaf908d 443 key->hw_key_idx += reg ? ffz(reg) : 0;
61e754f4
ID		 444
445 /*
446 * Upload key to hardware
447 */
448 memcpy(key_entry.key, crypto->key,
449 sizeof(key_entry.key));
450 memcpy(key_entry.tx_mic, crypto->tx_mic,
451 sizeof(key_entry.tx_mic));
452 memcpy(key_entry.rx_mic, crypto->rx_mic,
453 sizeof(key_entry.rx_mic));
454
455 memset(&addr_entry, 0, sizeof(addr_entry));
456 memcpy(&addr_entry, crypto->address, ETH_ALEN);
457 addr_entry.cipher = crypto->cipher;
458
459 reg = PAIRWISE_KEY_ENTRY(key->hw_key_idx);
460 rt2x00pci_register_multiwrite(rt2x00dev, reg,
461 &key_entry, sizeof(key_entry));
462
463 reg = PAIRWISE_TA_ENTRY(key->hw_key_idx);
464 rt2x00pci_register_multiwrite(rt2x00dev, reg,
465 &addr_entry, sizeof(addr_entry));
466
467 /*
b34e620f
TLSC		 468 * Enable pairwise lookup table for given BSS idx.
469 * Without this, received frames will not be decrypted
61e754f4
ID		 470 * by the hardware.
471 */
472 rt2x00pci_register_read(rt2x00dev, SEC_CSR4, &reg);
473 reg |= (1 << crypto->bssidx);
474 rt2x00pci_register_write(rt2x00dev, SEC_CSR4, reg);
475
476 /*
477 * The driver does not support the IV/EIV generation
478 * in hardware. However it doesn't support the IV/EIV
479 * inside the ieee80211 frame either, but requires it
3ad2f3fb 480 * to be provided separately for the descriptor.
61e754f4
ID		 481 * rt2x00lib will cut the IV/EIV data out of all frames
482 * given to us by mac80211, but we must tell mac80211
483 * to generate the IV/EIV data.
484 */
485 key->flags |= IEEE80211_KEY_FLAG_GENERATE_IV;
486 }
487
488 /*
489 * SEC_CSR2 and SEC_CSR3 contain only single-bit fields to indicate
490 * a particular key is valid. Because using the FIELD32()
b34e620f 491 * defines directly will cause a lot of overhead, we use
61e754f4
ID		 492 * a calculation to determine the correct bit directly.
493 */
494 if (key->hw_key_idx < 32) {
495 mask = 1 << key->hw_key_idx;
496
497 rt2x00pci_register_read(rt2x00dev, SEC_CSR2, &reg);
498 if (crypto->cmd == SET_KEY)
499 reg |= mask;
500 else if (crypto->cmd == DISABLE_KEY)
501 reg &= ~mask;
502 rt2x00pci_register_write(rt2x00dev, SEC_CSR2, reg);
503 } else {
504 mask = 1 << (key->hw_key_idx - 32);
505
506 rt2x00pci_register_read(rt2x00dev, SEC_CSR3, &reg);
507 if (crypto->cmd == SET_KEY)
508 reg |= mask;
509 else if (crypto->cmd == DISABLE_KEY)
510 reg &= ~mask;
511 rt2x00pci_register_write(rt2x00dev, SEC_CSR3, reg);
512 }
513
514 return 0;
515}
516
3a643d24
ID		 517static void rt61pci_config_filter(struct rt2x00_dev *rt2x00dev,
518 const unsigned int filter_flags)
519{
520 u32 reg;
521
522 /*
523 * Start configuration steps.
524 * Note that the version error will always be dropped
525 * and broadcast frames will always be accepted since
526 * there is no filter for it at this time.
527 */
528 rt2x00pci_register_read(rt2x00dev, TXRX_CSR0, &reg);
529 rt2x00_set_field32(&reg, TXRX_CSR0_DROP_CRC,
530 !(filter_flags & FIF_FCSFAIL));
531 rt2x00_set_field32(&reg, TXRX_CSR0_DROP_PHYSICAL,
532 !(filter_flags & FIF_PLCPFAIL));
533 rt2x00_set_field32(&reg, TXRX_CSR0_DROP_CONTROL,
1afcfd54 534 !(filter_flags & (FIF_CONTROL | FIF_PSPOLL)));
3a643d24
ID		 535 rt2x00_set_field32(&reg, TXRX_CSR0_DROP_NOT_TO_ME,
536 !(filter_flags & FIF_PROMISC_IN_BSS));
537 rt2x00_set_field32(&reg, TXRX_CSR0_DROP_TO_DS,
e0b005fa
ID		 538 !(filter_flags & FIF_PROMISC_IN_BSS) &&
539 !rt2x00dev->intf_ap_count);
3a643d24
ID		 540 rt2x00_set_field32(&reg, TXRX_CSR0_DROP_VERSION_ERROR, 1);
541 rt2x00_set_field32(&reg, TXRX_CSR0_DROP_MULTICAST,
542 !(filter_flags & FIF_ALLMULTI));
543 rt2x00_set_field32(&reg, TXRX_CSR0_DROP_BROADCAST, 0);
544 rt2x00_set_field32(&reg, TXRX_CSR0_DROP_ACK_CTS,
545 !(filter_flags & FIF_CONTROL));
546 rt2x00pci_register_write(rt2x00dev, TXRX_CSR0, reg);
547}
548
6bb40dd1
ID		 549static void rt61pci_config_intf(struct rt2x00_dev *rt2x00dev,
550 struct rt2x00_intf *intf,
551 struct rt2x00intf_conf *conf,
552 const unsigned int flags)
95ea3627 553{
6bb40dd1
ID		 554 unsigned int beacon_base;
555 u32 reg;
95ea3627 556
6bb40dd1
ID		 557 if (flags & CONFIG_UPDATE_TYPE) {
558 /*
559 * Clear current synchronisation setup.
b34e620f 560 * For the Beacon base registers, we only need to clear
6bb40dd1
ID		 561 * the first byte since that byte contains the VALID and OWNER
562 * bits which (when set to 0) will invalidate the entire beacon.
563 */
564 beacon_base = HW_BEACON_OFFSET(intf->beacon->entry_idx);
6bb40dd1 565 rt2x00pci_register_write(rt2x00dev, beacon_base, 0);
95ea3627 566
6bb40dd1
ID		 567 /*
568 * Enable synchronisation.
569 */
570 rt2x00pci_register_read(rt2x00dev, TXRX_CSR9, &reg);
fd3c91c5 571 rt2x00_set_field32(&reg, TXRX_CSR9_TSF_TICKING, 1);
6bb40dd1 572 rt2x00_set_field32(&reg, TXRX_CSR9_TSF_SYNC, conf->sync);
fd3c91c5 573 rt2x00_set_field32(&reg, TXRX_CSR9_TBTT_ENABLE, 1);
6bb40dd1
ID		 574 rt2x00pci_register_write(rt2x00dev, TXRX_CSR9, reg);
575 }
95ea3627 576
6bb40dd1
ID		 577 if (flags & CONFIG_UPDATE_MAC) {
578 reg = le32_to_cpu(conf->mac[1]);
579 rt2x00_set_field32(&reg, MAC_CSR3_UNICAST_TO_ME_MASK, 0xff);
580 conf->mac[1] = cpu_to_le32(reg);
95ea3627 581
6bb40dd1
ID		 582 rt2x00pci_register_multiwrite(rt2x00dev, MAC_CSR2,
583 conf->mac, sizeof(conf->mac));
584 }
95ea3627 585
6bb40dd1
ID		 586 if (flags & CONFIG_UPDATE_BSSID) {
587 reg = le32_to_cpu(conf->bssid[1]);
588 rt2x00_set_field32(&reg, MAC_CSR5_BSS_ID_MASK, 3);
589 conf->bssid[1] = cpu_to_le32(reg);
95ea3627 590
6bb40dd1
ID		 591 rt2x00pci_register_multiwrite(rt2x00dev, MAC_CSR4,
592 conf->bssid, sizeof(conf->bssid));
593 }
95ea3627
ID		 594}
595
3a643d24 596static void rt61pci_config_erp(struct rt2x00_dev *rt2x00dev,
02044643
HS		 597 struct rt2x00lib_erp *erp,
598 u32 changed)
95ea3627 599{
95ea3627 600 u32 reg;
95ea3627
ID		 601
602 rt2x00pci_register_read(rt2x00dev, TXRX_CSR0, &reg);
4789666e 603 rt2x00_set_field32(&reg, TXRX_CSR0_RX_ACK_TIMEOUT, 0x32);
8a566afe 604 rt2x00_set_field32(&reg, TXRX_CSR0_TSF_OFFSET, IEEE80211_HEADER);
95ea3627
ID		 605 rt2x00pci_register_write(rt2x00dev, TXRX_CSR0, reg);
606
02044643
HS		 607 if (changed & BSS_CHANGED_ERP_PREAMBLE) {
608 rt2x00pci_register_read(rt2x00dev, TXRX_CSR4, &reg);
609 rt2x00_set_field32(&reg, TXRX_CSR4_AUTORESPOND_ENABLE, 1);
610 rt2x00_set_field32(&reg, TXRX_CSR4_AUTORESPOND_PREAMBLE,
611 !!erp->short_preamble);
612 rt2x00pci_register_write(rt2x00dev, TXRX_CSR4, reg);
613 }
95ea3627 614
02044643
HS		 615 if (changed & BSS_CHANGED_BASIC_RATES)
616 rt2x00pci_register_write(rt2x00dev, TXRX_CSR5,
617 erp->basic_rates);
95ea3627 618
02044643
HS		 619 if (changed & BSS_CHANGED_BEACON_INT) {
620 rt2x00pci_register_read(rt2x00dev, TXRX_CSR9, &reg);
621 rt2x00_set_field32(&reg, TXRX_CSR9_BEACON_INTERVAL,
622 erp->beacon_int * 16);
623 rt2x00pci_register_write(rt2x00dev, TXRX_CSR9, reg);
624 }
8a566afe 625
02044643
HS		 626 if (changed & BSS_CHANGED_ERP_SLOT) {
627 rt2x00pci_register_read(rt2x00dev, MAC_CSR9, &reg);
628 rt2x00_set_field32(&reg, MAC_CSR9_SLOT_TIME, erp->slot_time);
629 rt2x00pci_register_write(rt2x00dev, MAC_CSR9, reg);
95ea3627 630
02044643
HS		 631 rt2x00pci_register_read(rt2x00dev, MAC_CSR8, &reg);
632 rt2x00_set_field32(&reg, MAC_CSR8_SIFS, erp->sifs);
633 rt2x00_set_field32(&reg, MAC_CSR8_SIFS_AFTER_RX_OFDM, 3);
634 rt2x00_set_field32(&reg, MAC_CSR8_EIFS, erp->eifs);
635 rt2x00pci_register_write(rt2x00dev, MAC_CSR8, reg);
636 }
95ea3627
ID		 637}
638
639static void rt61pci_config_antenna_5x(struct rt2x00_dev *rt2x00dev,
addc81bd 640 struct antenna_setup *ant)
95ea3627
ID		 641{
642 u8 r3;
643 u8 r4;
644 u8 r77;
645
646 rt61pci_bbp_read(rt2x00dev, 3, &r3);
647 rt61pci_bbp_read(rt2x00dev, 4, &r4);
648 rt61pci_bbp_read(rt2x00dev, 77, &r77);
649
5122d898 650 rt2x00_set_field8(&r3, BBP_R3_SMART_MODE, rt2x00_rf(rt2x00dev, RF5325));
e4cd2ff8
ID		 651
652 /*
653 * Configure the RX antenna.
654 */
addc81bd 655 switch (ant->rx) {
95ea3627 656 case ANTENNA_HW_DIVERSITY:
acaa410d 657 rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA_CONTROL, 2);
95ea3627 658 rt2x00_set_field8(&r4, BBP_R4_RX_FRAME_END,
8318d78a 659 (rt2x00dev->curr_band != IEEE80211_BAND_5GHZ));
95ea3627
ID		 660 break;
661 case ANTENNA_A:
acaa410d 662 rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA_CONTROL, 1);
95ea3627 663 rt2x00_set_field8(&r4, BBP_R4_RX_FRAME_END, 0);
8318d78a 664 if (rt2x00dev->curr_band == IEEE80211_BAND_5GHZ)
acaa410d
MN		 665 rt2x00_set_field8(&r77, BBP_R77_RX_ANTENNA, 0);
666 else
667 rt2x00_set_field8(&r77, BBP_R77_RX_ANTENNA, 3);
95ea3627
ID		 668 break;
669 case ANTENNA_B:
a4fe07d9 670 default:
acaa410d 671 rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA_CONTROL, 1);
95ea3627 672 rt2x00_set_field8(&r4, BBP_R4_RX_FRAME_END, 0);
8318d78a 673 if (rt2x00dev->curr_band == IEEE80211_BAND_5GHZ)
acaa410d
MN		 674 rt2x00_set_field8(&r77, BBP_R77_RX_ANTENNA, 3);
675 else
676 rt2x00_set_field8(&r77, BBP_R77_RX_ANTENNA, 0);
95ea3627
ID		 677 break;
678 }
679
680 rt61pci_bbp_write(rt2x00dev, 77, r77);
681 rt61pci_bbp_write(rt2x00dev, 3, r3);
682 rt61pci_bbp_write(rt2x00dev, 4, r4);
683}
684
685static void rt61pci_config_antenna_2x(struct rt2x00_dev *rt2x00dev,
addc81bd 686 struct antenna_setup *ant)
95ea3627
ID		 687{
688 u8 r3;
689 u8 r4;
690 u8 r77;
691
692 rt61pci_bbp_read(rt2x00dev, 3, &r3);
693 rt61pci_bbp_read(rt2x00dev, 4, &r4);
694 rt61pci_bbp_read(rt2x00dev, 77, &r77);
695
5122d898 696 rt2x00_set_field8(&r3, BBP_R3_SMART_MODE, rt2x00_rf(rt2x00dev, RF2529));
95ea3627
ID		 697 rt2x00_set_field8(&r4, BBP_R4_RX_FRAME_END,
698 !test_bit(CONFIG_FRAME_TYPE, &rt2x00dev->flags));
699
e4cd2ff8
ID		 700 /*
701 * Configure the RX antenna.
702 */
addc81bd 703 switch (ant->rx) {
95ea3627 704 case ANTENNA_HW_DIVERSITY:
acaa410d 705 rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA_CONTROL, 2);
95ea3627
ID		 706 break;
707 case ANTENNA_A:
acaa410d
MN		 708 rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA_CONTROL, 1);
709 rt2x00_set_field8(&r77, BBP_R77_RX_ANTENNA, 3);
95ea3627
ID		 710 break;
711 case ANTENNA_B:
a4fe07d9 712 default:
acaa410d
MN		 713 rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA_CONTROL, 1);
714 rt2x00_set_field8(&r77, BBP_R77_RX_ANTENNA, 0);
95ea3627
ID		 715 break;
716 }
717
718 rt61pci_bbp_write(rt2x00dev, 77, r77);
719 rt61pci_bbp_write(rt2x00dev, 3, r3);
720 rt61pci_bbp_write(rt2x00dev, 4, r4);
721}
722
723static void rt61pci_config_antenna_2529_rx(struct rt2x00_dev *rt2x00dev,
724 const int p1, const int p2)
725{
726 u32 reg;
727
728 rt2x00pci_register_read(rt2x00dev, MAC_CSR13, &reg);
729
acaa410d
MN		 730 rt2x00_set_field32(&reg, MAC_CSR13_BIT4, p1);
731 rt2x00_set_field32(&reg, MAC_CSR13_BIT12, 0);
732
733 rt2x00_set_field32(&reg, MAC_CSR13_BIT3, !p2);
734 rt2x00_set_field32(&reg, MAC_CSR13_BIT11, 0);
735
736 rt2x00pci_register_write(rt2x00dev, MAC_CSR13, reg);
95ea3627
ID		 737}
738
739static void rt61pci_config_antenna_2529(struct rt2x00_dev *rt2x00dev,
addc81bd 740 struct antenna_setup *ant)
95ea3627 741{
95ea3627
ID		 742 u8 r3;
743 u8 r4;
744 u8 r77;
745
746 rt61pci_bbp_read(rt2x00dev, 3, &r3);
747 rt61pci_bbp_read(rt2x00dev, 4, &r4);
748 rt61pci_bbp_read(rt2x00dev, 77, &r77);
e4cd2ff8 749
e4cd2ff8
ID		 750 /*
751 * Configure the RX antenna.
752 */
753 switch (ant->rx) {
754 case ANTENNA_A:
acaa410d
MN		 755 rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA_CONTROL, 1);
756 rt2x00_set_field8(&r77, BBP_R77_RX_ANTENNA, 0);
757 rt61pci_config_antenna_2529_rx(rt2x00dev, 0, 0);
e4cd2ff8 758 break;
e4cd2ff8
ID		 759 case ANTENNA_HW_DIVERSITY:
760 /*
a4fe07d9
ID		 761 * FIXME: Antenna selection for the rf 2529 is very confusing
762 * in the legacy driver. Just default to antenna B until the
763 * legacy code can be properly translated into rt2x00 code.
e4cd2ff8
ID		 764 */
765 case ANTENNA_B:
a4fe07d9 766 default:
acaa410d
MN		 767 rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA_CONTROL, 1);
768 rt2x00_set_field8(&r77, BBP_R77_RX_ANTENNA, 3);
769 rt61pci_config_antenna_2529_rx(rt2x00dev, 1, 1);
e4cd2ff8
ID		 770 break;
771 }
772
e4cd2ff8 773 rt61pci_bbp_write(rt2x00dev, 77, r77);
95ea3627
ID		 774 rt61pci_bbp_write(rt2x00dev, 3, r3);
775 rt61pci_bbp_write(rt2x00dev, 4, r4);
776}
777
778struct antenna_sel {
779 u8 word;
780 /*
781 * value[0] -> non-LNA
782 * value[1] -> LNA
783 */
784 u8 value[2];
785};
786
787static const struct antenna_sel antenna_sel_a[] = {
788 { 96, { 0x58, 0x78 } },
789 { 104, { 0x38, 0x48 } },
790 { 75, { 0xfe, 0x80 } },
791 { 86, { 0xfe, 0x80 } },
792 { 88, { 0xfe, 0x80 } },
793 { 35, { 0x60, 0x60 } },
794 { 97, { 0x58, 0x58 } },
795 { 98, { 0x58, 0x58 } },
796};
797
798static const struct antenna_sel antenna_sel_bg[] = {
799 { 96, { 0x48, 0x68 } },
800 { 104, { 0x2c, 0x3c } },
801 { 75, { 0xfe, 0x80 } },
802 { 86, { 0xfe, 0x80 } },
803 { 88, { 0xfe, 0x80 } },
804 { 35, { 0x50, 0x50 } },
805 { 97, { 0x48, 0x48 } },
806 { 98, { 0x48, 0x48 } },
807};
808
e4ea1c40
ID		 809static void rt61pci_config_ant(struct rt2x00_dev *rt2x00dev,
810 struct antenna_setup *ant)
95ea3627
ID		 811{
812 const struct antenna_sel *sel;
813 unsigned int lna;
814 unsigned int i;
815 u32 reg;
816
a4fe07d9
ID		 817 /*
818 * We should never come here because rt2x00lib is supposed
819 * to catch this and send us the correct antenna explicitely.
820 */
821 BUG_ON(ant->rx == ANTENNA_SW_DIVERSITY ||
822 ant->tx == ANTENNA_SW_DIVERSITY);
823
8318d78a 824 if (rt2x00dev->curr_band == IEEE80211_BAND_5GHZ) {
95ea3627
ID		 825 sel = antenna_sel_a;
826 lna = test_bit(CONFIG_EXTERNAL_LNA_A, &rt2x00dev->flags);
95ea3627
ID		 827 } else {
828 sel = antenna_sel_bg;
829 lna = test_bit(CONFIG_EXTERNAL_LNA_BG, &rt2x00dev->flags);
95ea3627
ID		 830 }
831
acaa410d
MN		 832 for (i = 0; i < ARRAY_SIZE(antenna_sel_a); i++)
833 rt61pci_bbp_write(rt2x00dev, sel[i].word, sel[i].value[lna]);
834
835 rt2x00pci_register_read(rt2x00dev, PHY_CSR0, &reg);
836
ddc827f9 837 rt2x00_set_field32(&reg, PHY_CSR0_PA_PE_BG,
8318d78a 838 rt2x00dev->curr_band == IEEE80211_BAND_2GHZ);
ddc827f9 839 rt2x00_set_field32(&reg, PHY_CSR0_PA_PE_A,
8318d78a 840 rt2x00dev->curr_band == IEEE80211_BAND_5GHZ);
ddc827f9 841
95ea3627
ID		 842 rt2x00pci_register_write(rt2x00dev, PHY_CSR0, reg);
843
5122d898 844 if (rt2x00_rf(rt2x00dev, RF5225) || rt2x00_rf(rt2x00dev, RF5325))
addc81bd 845 rt61pci_config_antenna_5x(rt2x00dev, ant);
5122d898 846 else if (rt2x00_rf(rt2x00dev, RF2527))
addc81bd 847 rt61pci_config_antenna_2x(rt2x00dev, ant);
5122d898 848 else if (rt2x00_rf(rt2x00dev, RF2529)) {
95ea3627 849 if (test_bit(CONFIG_DOUBLE_ANTENNA, &rt2x00dev->flags))
addc81bd 850 rt61pci_config_antenna_2x(rt2x00dev, ant);
95ea3627 851 else
addc81bd 852 rt61pci_config_antenna_2529(rt2x00dev, ant);
95ea3627
ID		 853 }
854}
855
e4ea1c40
ID		 856static void rt61pci_config_lna_gain(struct rt2x00_dev *rt2x00dev,
857 struct rt2x00lib_conf *libconf)
858{
859 u16 eeprom;
860 short lna_gain = 0;
861
862 if (libconf->conf->channel->band == IEEE80211_BAND_2GHZ) {
863 if (test_bit(CONFIG_EXTERNAL_LNA_BG, &rt2x00dev->flags))
864 lna_gain += 14;
865
866 rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_OFFSET_BG, &eeprom);
867 lna_gain -= rt2x00_get_field16(eeprom, EEPROM_RSSI_OFFSET_BG_1);
868 } else {
869 if (test_bit(CONFIG_EXTERNAL_LNA_A, &rt2x00dev->flags))
870 lna_gain += 14;
871
872 rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_OFFSET_A, &eeprom);
873 lna_gain -= rt2x00_get_field16(eeprom, EEPROM_RSSI_OFFSET_A_1);
874 }
875
876 rt2x00dev->lna_gain = lna_gain;
877}
878
879static void rt61pci_config_channel(struct rt2x00_dev *rt2x00dev,
880 struct rf_channel *rf, const int txpower)
881{
882 u8 r3;
883 u8 r94;
884 u8 smart;
885
886 rt2x00_set_field32(&rf->rf3, RF3_TXPOWER, TXPOWER_TO_DEV(txpower));
887 rt2x00_set_field32(&rf->rf4, RF4_FREQ_OFFSET, rt2x00dev->freq_offset);
888
5122d898 889 smart = !(rt2x00_rf(rt2x00dev, RF5225) || rt2x00_rf(rt2x00dev, RF2527));
e4ea1c40
ID		 890
891 rt61pci_bbp_read(rt2x00dev, 3, &r3);
892 rt2x00_set_field8(&r3, BBP_R3_SMART_MODE, smart);
893 rt61pci_bbp_write(rt2x00dev, 3, r3);
894
895 r94 = 6;
896 if (txpower > MAX_TXPOWER && txpower <= (MAX_TXPOWER + r94))
897 r94 += txpower - MAX_TXPOWER;
898 else if (txpower < MIN_TXPOWER && txpower >= (MIN_TXPOWER - r94))
899 r94 += txpower;
900 rt61pci_bbp_write(rt2x00dev, 94, r94);
901
902 rt61pci_rf_write(rt2x00dev, 1, rf->rf1);
903 rt61pci_rf_write(rt2x00dev, 2, rf->rf2);
904 rt61pci_rf_write(rt2x00dev, 3, rf->rf3 & ~0x00000004);
905 rt61pci_rf_write(rt2x00dev, 4, rf->rf4);
906
907 udelay(200);
908
909 rt61pci_rf_write(rt2x00dev, 1, rf->rf1);
910 rt61pci_rf_write(rt2x00dev, 2, rf->rf2);
911 rt61pci_rf_write(rt2x00dev, 3, rf->rf3 | 0x00000004);
912 rt61pci_rf_write(rt2x00dev, 4, rf->rf4);
913
914 udelay(200);
915
916 rt61pci_rf_write(rt2x00dev, 1, rf->rf1);
917 rt61pci_rf_write(rt2x00dev, 2, rf->rf2);
918 rt61pci_rf_write(rt2x00dev, 3, rf->rf3 & ~0x00000004);
919 rt61pci_rf_write(rt2x00dev, 4, rf->rf4);
920
921 msleep(1);
922}
923
924static void rt61pci_config_txpower(struct rt2x00_dev *rt2x00dev,
925 const int txpower)
926{
927 struct rf_channel rf;
928
929 rt2x00_rf_read(rt2x00dev, 1, &rf.rf1);
930 rt2x00_rf_read(rt2x00dev, 2, &rf.rf2);
931 rt2x00_rf_read(rt2x00dev, 3, &rf.rf3);
932 rt2x00_rf_read(rt2x00dev, 4, &rf.rf4);
933
934 rt61pci_config_channel(rt2x00dev, &rf, txpower);
935}
936
937static void rt61pci_config_retry_limit(struct rt2x00_dev *rt2x00dev,
5c58ee51 938 struct rt2x00lib_conf *libconf)
95ea3627
ID		 939{
940 u32 reg;
941
e4ea1c40 942 rt2x00pci_register_read(rt2x00dev, TXRX_CSR4, &reg);
e1b4d7b7
ID		 943 rt2x00_set_field32(&reg, TXRX_CSR4_OFDM_TX_RATE_DOWN, 1);
944 rt2x00_set_field32(&reg, TXRX_CSR4_OFDM_TX_RATE_STEP, 0);
945 rt2x00_set_field32(&reg, TXRX_CSR4_OFDM_TX_FALLBACK_CCK, 0);
e4ea1c40
ID		 946 rt2x00_set_field32(&reg, TXRX_CSR4_LONG_RETRY_LIMIT,
947 libconf->conf->long_frame_max_tx_count);
948 rt2x00_set_field32(&reg, TXRX_CSR4_SHORT_RETRY_LIMIT,
949 libconf->conf->short_frame_max_tx_count);
950 rt2x00pci_register_write(rt2x00dev, TXRX_CSR4, reg);
951}
95ea3627 952
7d7f19cc
ID		 953static void rt61pci_config_ps(struct rt2x00_dev *rt2x00dev,
954 struct rt2x00lib_conf *libconf)
955{
956 enum dev_state state =
957 (libconf->conf->flags & IEEE80211_CONF_PS) ?
958 STATE_SLEEP : STATE_AWAKE;
959 u32 reg;
960
961 if (state == STATE_SLEEP) {
962 rt2x00pci_register_read(rt2x00dev, MAC_CSR11, &reg);
963 rt2x00_set_field32(&reg, MAC_CSR11_DELAY_AFTER_TBCN,
6b347bff 964 rt2x00dev->beacon_int - 10);
7d7f19cc
ID		 965 rt2x00_set_field32(&reg, MAC_CSR11_TBCN_BEFORE_WAKEUP,
966 libconf->conf->listen_interval - 1);
967 rt2x00_set_field32(&reg, MAC_CSR11_WAKEUP_LATENCY, 5);
968
969 /* We must first disable autowake before it can be enabled */
970 rt2x00_set_field32(&reg, MAC_CSR11_AUTOWAKE, 0);
971 rt2x00pci_register_write(rt2x00dev, MAC_CSR11, reg);
972
973 rt2x00_set_field32(&reg, MAC_CSR11_AUTOWAKE, 1);
974 rt2x00pci_register_write(rt2x00dev, MAC_CSR11, reg);
975
976 rt2x00pci_register_write(rt2x00dev, SOFT_RESET_CSR, 0x00000005);
977 rt2x00pci_register_write(rt2x00dev, IO_CNTL_CSR, 0x0000001c);
978 rt2x00pci_register_write(rt2x00dev, PCI_USEC_CSR, 0x00000060);
979
980 rt61pci_mcu_request(rt2x00dev, MCU_SLEEP, 0xff, 0, 0);
981 } else {
982 rt2x00pci_register_read(rt2x00dev, MAC_CSR11, &reg);
983 rt2x00_set_field32(&reg, MAC_CSR11_DELAY_AFTER_TBCN, 0);
984 rt2x00_set_field32(&reg, MAC_CSR11_TBCN_BEFORE_WAKEUP, 0);
985 rt2x00_set_field32(&reg, MAC_CSR11_AUTOWAKE, 0);
986 rt2x00_set_field32(&reg, MAC_CSR11_WAKEUP_LATENCY, 0);
987 rt2x00pci_register_write(rt2x00dev, MAC_CSR11, reg);
988
989 rt2x00pci_register_write(rt2x00dev, SOFT_RESET_CSR, 0x00000007);
990 rt2x00pci_register_write(rt2x00dev, IO_CNTL_CSR, 0x00000018);
991 rt2x00pci_register_write(rt2x00dev, PCI_USEC_CSR, 0x00000020);
992
993 rt61pci_mcu_request(rt2x00dev, MCU_WAKEUP, 0xff, 0, 0);
994 }
995}
996
95ea3627 997static void rt61pci_config(struct rt2x00_dev *rt2x00dev,
6bb40dd1
ID		 998 struct rt2x00lib_conf *libconf,
999 const unsigned int flags)
95ea3627 1000{
ba2ab471
ID		 1001 /* Always recalculate LNA gain before changing configuration */
1002 rt61pci_config_lna_gain(rt2x00dev, libconf);
1003
e4ea1c40 1004 if (flags & IEEE80211_CONF_CHANGE_CHANNEL)
5c58ee51
ID		 1005 rt61pci_config_channel(rt2x00dev, &libconf->rf,
1006 libconf->conf->power_level);
e4ea1c40
ID		 1007 if ((flags & IEEE80211_CONF_CHANGE_POWER) &&
1008 !(flags & IEEE80211_CONF_CHANGE_CHANNEL))
5c58ee51 1009 rt61pci_config_txpower(rt2x00dev, libconf->conf->power_level);
e4ea1c40
ID		 1010 if (flags & IEEE80211_CONF_CHANGE_RETRY_LIMITS)
1011 rt61pci_config_retry_limit(rt2x00dev, libconf);
7d7f19cc
ID		 1012 if (flags & IEEE80211_CONF_CHANGE_PS)
1013 rt61pci_config_ps(rt2x00dev, libconf);
95ea3627
ID		 1014}
1015
95ea3627
ID		 1016/*
1017 * Link tuning
1018 */
ebcf26da
ID		 1019static void rt61pci_link_stats(struct rt2x00_dev *rt2x00dev,
1020 struct link_qual *qual)
95ea3627
ID		 1021{
1022 u32 reg;
1023
1024 /*
1025 * Update FCS error count from register.
1026 */
1027 rt2x00pci_register_read(rt2x00dev, STA_CSR0, &reg);
ebcf26da 1028 qual->rx_failed = rt2x00_get_field32(reg, STA_CSR0_FCS_ERROR);
95ea3627
ID		 1029
1030 /*
1031 * Update False CCA count from register.
1032 */
1033 rt2x00pci_register_read(rt2x00dev, STA_CSR1, &reg);
ebcf26da 1034 qual->false_cca = rt2x00_get_field32(reg, STA_CSR1_FALSE_CCA_ERROR);
95ea3627
ID		 1035}
1036
5352ff65
ID		 1037static inline void rt61pci_set_vgc(struct rt2x00_dev *rt2x00dev,
1038 struct link_qual *qual, u8 vgc_level)
eb20b4e8 1039{
5352ff65 1040 if (qual->vgc_level != vgc_level) {
eb20b4e8 1041 rt61pci_bbp_write(rt2x00dev, 17, vgc_level);
5352ff65
ID		 1042 qual->vgc_level = vgc_level;
1043 qual->vgc_level_reg = vgc_level;
eb20b4e8
ID		 1044 }
1045}
1046
5352ff65
ID		 1047static void rt61pci_reset_tuner(struct rt2x00_dev *rt2x00dev,
1048 struct link_qual *qual)
95ea3627 1049{
5352ff65 1050 rt61pci_set_vgc(rt2x00dev, qual, 0x20);
95ea3627
ID		 1051}
1052
5352ff65
ID		 1053static void rt61pci_link_tuner(struct rt2x00_dev *rt2x00dev,
1054 struct link_qual *qual, const u32 count)
95ea3627 1055{
95ea3627
ID		 1056 u8 up_bound;
1057 u8 low_bound;
1058
95ea3627
ID		 1059 /*
1060 * Determine r17 bounds.
1061 */
e5ef5bad 1062 if (rt2x00dev->curr_band == IEEE80211_BAND_5GHZ) {
95ea3627
ID		 1063 low_bound = 0x28;
1064 up_bound = 0x48;
1065 if (test_bit(CONFIG_EXTERNAL_LNA_A, &rt2x00dev->flags)) {
1066 low_bound += 0x10;
1067 up_bound += 0x10;
1068 }
1069 } else {
1070 low_bound = 0x20;
1071 up_bound = 0x40;
1072 if (test_bit(CONFIG_EXTERNAL_LNA_BG, &rt2x00dev->flags)) {
1073 low_bound += 0x10;
1074 up_bound += 0x10;
1075 }
1076 }
1077
6bb40dd1
ID		 1078 /*
1079 * If we are not associated, we should go straight to the
1080 * dynamic CCA tuning.
1081 */
1082 if (!rt2x00dev->intf_associated)
1083 goto dynamic_cca_tune;
1084
95ea3627
ID		 1085 /*
1086 * Special big-R17 for very short distance
1087 */
5352ff65
ID		 1088 if (qual->rssi >= -35) {
1089 rt61pci_set_vgc(rt2x00dev, qual, 0x60);
95ea3627
ID		 1090 return;
1091 }
1092
1093 /*
1094 * Special big-R17 for short distance
1095 */
5352ff65
ID		 1096 if (qual->rssi >= -58) {
1097 rt61pci_set_vgc(rt2x00dev, qual, up_bound);
95ea3627
ID		 1098 return;
1099 }
1100
1101 /*
1102 * Special big-R17 for middle-short distance
1103 */
5352ff65
ID		 1104 if (qual->rssi >= -66) {
1105 rt61pci_set_vgc(rt2x00dev, qual, low_bound + 0x10);
95ea3627
ID		 1106 return;
1107 }
1108
1109 /*
1110 * Special mid-R17 for middle distance
1111 */
5352ff65
ID		 1112 if (qual->rssi >= -74) {
1113 rt61pci_set_vgc(rt2x00dev, qual, low_bound + 0x08);
95ea3627
ID		 1114 return;
1115 }
1116
1117 /*
1118 * Special case: Change up_bound based on the rssi.
1119 * Lower up_bound when rssi is weaker then -74 dBm.
1120 */
5352ff65 1121 up_bound -= 2 * (-74 - qual->rssi);
95ea3627
ID		 1122 if (low_bound > up_bound)
1123 up_bound = low_bound;
1124
5352ff65
ID		 1125 if (qual->vgc_level > up_bound) {
1126 rt61pci_set_vgc(rt2x00dev, qual, up_bound);
95ea3627
ID		 1127 return;
1128 }
1129
6bb40dd1
ID		 1130dynamic_cca_tune:
1131
95ea3627
ID		 1132 /*
1133 * r17 does not yet exceed upper limit, continue and base
1134 * the r17 tuning on the false CCA count.
1135 */
5352ff65
ID		 1136 if ((qual->false_cca > 512) && (qual->vgc_level < up_bound))
1137 rt61pci_set_vgc(rt2x00dev, qual, ++qual->vgc_level);
1138 else if ((qual->false_cca < 100) && (qual->vgc_level > low_bound))
1139 rt61pci_set_vgc(rt2x00dev, qual, --qual->vgc_level);
95ea3627
ID		 1140}
1141
5450b7e2
ID		 1142/*
1143 * Queue handlers.
1144 */
1145static void rt61pci_start_queue(struct data_queue *queue)
1146{
1147 struct rt2x00_dev *rt2x00dev = queue->rt2x00dev;
1148 u32 reg;
1149
1150 switch (queue->qid) {
1151 case QID_RX:
1152 rt2x00pci_register_read(rt2x00dev, TXRX_CSR0, &reg);
1153 rt2x00_set_field32(&reg, TXRX_CSR0_DISABLE_RX, 0);
1154 rt2x00pci_register_write(rt2x00dev, TXRX_CSR0, reg);
1155 break;
1156 case QID_BEACON:
1157 rt2x00pci_register_read(rt2x00dev, TXRX_CSR9, &reg);
1158 rt2x00_set_field32(&reg, TXRX_CSR9_TSF_TICKING, 1);
1159 rt2x00_set_field32(&reg, TXRX_CSR9_TBTT_ENABLE, 1);
1160 rt2x00_set_field32(&reg, TXRX_CSR9_BEACON_GEN, 1);
1161 rt2x00pci_register_write(rt2x00dev, TXRX_CSR9, reg);
1162 break;
1163 default:
1164 break;
1165 }
1166}
1167
1168static void rt61pci_kick_queue(struct data_queue *queue)
1169{
1170 struct rt2x00_dev *rt2x00dev = queue->rt2x00dev;
1171 u32 reg;
1172
1173 switch (queue->qid) {
1174 case QID_AC_BE:
1175 rt2x00pci_register_read(rt2x00dev, TX_CNTL_CSR, &reg);
1176 rt2x00_set_field32(&reg, TX_CNTL_CSR_KICK_TX_AC0, 1);
1177 rt2x00pci_register_write(rt2x00dev, TX_CNTL_CSR, reg);
1178 break;
1179 case QID_AC_BK:
1180 rt2x00pci_register_read(rt2x00dev, TX_CNTL_CSR, &reg);
1181 rt2x00_set_field32(&reg, TX_CNTL_CSR_KICK_TX_AC1, 1);
1182 rt2x00pci_register_write(rt2x00dev, TX_CNTL_CSR, reg);
1183 break;
1184 case QID_AC_VI:
1185 rt2x00pci_register_read(rt2x00dev, TX_CNTL_CSR, &reg);
1186 rt2x00_set_field32(&reg, TX_CNTL_CSR_KICK_TX_AC2, 1);
1187 rt2x00pci_register_write(rt2x00dev, TX_CNTL_CSR, reg);
1188 break;
1189 case QID_AC_VO:
1190 rt2x00pci_register_read(rt2x00dev, TX_CNTL_CSR, &reg);
1191 rt2x00_set_field32(&reg, TX_CNTL_CSR_KICK_TX_AC3, 1);
1192 rt2x00pci_register_write(rt2x00dev, TX_CNTL_CSR, reg);
1193 break;
1194 default:
1195 break;
1196 }
1197}
1198
1199static void rt61pci_stop_queue(struct data_queue *queue)
1200{
1201 struct rt2x00_dev *rt2x00dev = queue->rt2x00dev;
1202 u32 reg;
1203
1204 switch (queue->qid) {
1205 case QID_AC_BE:
1206 rt2x00pci_register_read(rt2x00dev, TX_CNTL_CSR, &reg);
1207 rt2x00_set_field32(&reg, TX_CNTL_CSR_ABORT_TX_AC0, 1);
1208 rt2x00pci_register_write(rt2x00dev, TX_CNTL_CSR, reg);
1209 break;
1210 case QID_AC_BK:
1211 rt2x00pci_register_read(rt2x00dev, TX_CNTL_CSR, &reg);
1212 rt2x00_set_field32(&reg, TX_CNTL_CSR_ABORT_TX_AC1, 1);
1213 rt2x00pci_register_write(rt2x00dev, TX_CNTL_CSR, reg);
1214 break;
1215 case QID_AC_VI:
1216 rt2x00pci_register_read(rt2x00dev, TX_CNTL_CSR, &reg);
1217 rt2x00_set_field32(&reg, TX_CNTL_CSR_ABORT_TX_AC2, 1);
1218 rt2x00pci_register_write(rt2x00dev, TX_CNTL_CSR, reg);
1219 break;
1220 case QID_AC_VO:
1221 rt2x00pci_register_read(rt2x00dev, TX_CNTL_CSR, &reg);
1222 rt2x00_set_field32(&reg, TX_CNTL_CSR_ABORT_TX_AC3, 1);
1223 rt2x00pci_register_write(rt2x00dev, TX_CNTL_CSR, reg);
1224 break;
1225 case QID_RX:
1226 rt2x00pci_register_read(rt2x00dev, TXRX_CSR0, &reg);
1227 rt2x00_set_field32(&reg, TXRX_CSR0_DISABLE_RX, 1);
1228 rt2x00pci_register_write(rt2x00dev, TXRX_CSR0, reg);
1229 break;
1230 case QID_BEACON:
1231 rt2x00pci_register_read(rt2x00dev, TXRX_CSR9, &reg);
1232 rt2x00_set_field32(&reg, TXRX_CSR9_TSF_TICKING, 0);
1233 rt2x00_set_field32(&reg, TXRX_CSR9_TBTT_ENABLE, 0);
1234 rt2x00_set_field32(&reg, TXRX_CSR9_BEACON_GEN, 0);
1235 rt2x00pci_register_write(rt2x00dev, TXRX_CSR9, reg);
1236 break;
1237 default:
1238 break;
1239 }
1240}
1241
95ea3627 1242/*
a7f3a06c 1243 * Firmware functions
95ea3627
ID		 1244 */
1245static char *rt61pci_get_firmware_name(struct rt2x00_dev *rt2x00dev)
1246{
49e721ec 1247 u16 chip;
95ea3627
ID		 1248 char *fw_name;
1249
49e721ec
GW		 1250 pci_read_config_word(to_pci_dev(rt2x00dev->dev), PCI_DEVICE_ID, &chip);
1251 switch (chip) {
1252 case RT2561_PCI_ID:
95ea3627
ID		 1253 fw_name = FIRMWARE_RT2561;
1254 break;
49e721ec 1255 case RT2561s_PCI_ID:
95ea3627
ID		 1256 fw_name = FIRMWARE_RT2561s;
1257 break;
49e721ec 1258 case RT2661_PCI_ID:
95ea3627
ID		 1259 fw_name = FIRMWARE_RT2661;
1260 break;
1261 default:
1262 fw_name = NULL;
1263 break;
1264 }
1265
1266 return fw_name;
1267}
1268
0cbe0064
ID		 1269static int rt61pci_check_firmware(struct rt2x00_dev *rt2x00dev,
1270 const u8 *data, const size_t len)
a7f3a06c 1271{
0cbe0064 1272 u16 fw_crc;
a7f3a06c
ID		 1273 u16 crc;
1274
1275 /*
0cbe0064
ID		 1276 * Only support 8kb firmware files.
1277 */
1278 if (len != 8192)
1279 return FW_BAD_LENGTH;
1280
1281 /*
b34e620f
TLSC		 1282 * The last 2 bytes in the firmware array are the crc checksum itself.
1283 * This means that we should never pass those 2 bytes to the crc
a7f3a06c
ID		 1284 * algorithm.
1285 */
0cbe0064
ID		 1286 fw_crc = (data[len - 2] << 8 | data[len - 1]);
1287
1288 /*
1289 * Use the crc itu-t algorithm.
1290 */
a7f3a06c
ID		 1291 crc = crc_itu_t(0, data, len - 2);
1292 crc = crc_itu_t_byte(crc, 0);
1293 crc = crc_itu_t_byte(crc, 0);
1294
0cbe0064 1295 return (fw_crc == crc) ? FW_OK : FW_BAD_CRC;
a7f3a06c
ID		 1296}
1297
0cbe0064
ID		 1298static int rt61pci_load_firmware(struct rt2x00_dev *rt2x00dev,
1299 const u8 *data, const size_t len)
95ea3627
ID		 1300{
1301 int i;
1302 u32 reg;
1303
1304 /*
1305 * Wait for stable hardware.
1306 */
1307 for (i = 0; i < 100; i++) {
1308 rt2x00pci_register_read(rt2x00dev, MAC_CSR0, &reg);
1309 if (reg)
1310 break;
1311 msleep(1);
1312 }
1313
1314 if (!reg) {
1315 ERROR(rt2x00dev, "Unstable hardware.\n");
1316 return -EBUSY;
1317 }
1318
1319 /*
1320 * Prepare MCU and mailbox for firmware loading.
1321 */
1322 reg = 0;
1323 rt2x00_set_field32(&reg, MCU_CNTL_CSR_RESET, 1);
1324 rt2x00pci_register_write(rt2x00dev, MCU_CNTL_CSR, reg);
1325 rt2x00pci_register_write(rt2x00dev, M2H_CMD_DONE_CSR, 0xffffffff);
1326 rt2x00pci_register_write(rt2x00dev, H2M_MAILBOX_CSR, 0);
1327 rt2x00pci_register_write(rt2x00dev, HOST_CMD_CSR, 0);
1328
1329 /*
1330 * Write firmware to device.
1331 */
1332 reg = 0;
1333 rt2x00_set_field32(&reg, MCU_CNTL_CSR_RESET, 1);
1334 rt2x00_set_field32(&reg, MCU_CNTL_CSR_SELECT_BANK, 1);
1335 rt2x00pci_register_write(rt2x00dev, MCU_CNTL_CSR, reg);
1336
1337 rt2x00pci_register_multiwrite(rt2x00dev, FIRMWARE_IMAGE_BASE,
1338 data, len);
1339
1340 rt2x00_set_field32(&reg, MCU_CNTL_CSR_SELECT_BANK, 0);
1341 rt2x00pci_register_write(rt2x00dev, MCU_CNTL_CSR, reg);
1342
1343 rt2x00_set_field32(&reg, MCU_CNTL_CSR_RESET, 0);
1344 rt2x00pci_register_write(rt2x00dev, MCU_CNTL_CSR, reg);
1345
1346 for (i = 0; i < 100; i++) {
1347 rt2x00pci_register_read(rt2x00dev, MCU_CNTL_CSR, &reg);
1348 if (rt2x00_get_field32(reg, MCU_CNTL_CSR_READY))
1349 break;
1350 msleep(1);
1351 }
1352
1353 if (i == 100) {
1354 ERROR(rt2x00dev, "MCU Control register not ready.\n");
1355 return -EBUSY;
1356 }
1357
e6d3e902
ID		 1358 /*
1359 * Hardware needs another millisecond before it is ready.
1360 */
1361 msleep(1);
1362
95ea3627
ID		 1363 /*
1364 * Reset MAC and BBP registers.
1365 */
1366 reg = 0;
1367 rt2x00_set_field32(&reg, MAC_CSR1_SOFT_RESET, 1);
1368 rt2x00_set_field32(&reg, MAC_CSR1_BBP_RESET, 1);
1369 rt2x00pci_register_write(rt2x00dev, MAC_CSR1, reg);
1370
1371 rt2x00pci_register_read(rt2x00dev, MAC_CSR1, &reg);
1372 rt2x00_set_field32(&reg, MAC_CSR1_SOFT_RESET, 0);
1373 rt2x00_set_field32(&reg, MAC_CSR1_BBP_RESET, 0);
1374 rt2x00pci_register_write(rt2x00dev, MAC_CSR1, reg);
1375
1376 rt2x00pci_register_read(rt2x00dev, MAC_CSR1, &reg);
1377 rt2x00_set_field32(&reg, MAC_CSR1_HOST_READY, 1);
1378 rt2x00pci_register_write(rt2x00dev, MAC_CSR1, reg);
1379
1380 return 0;
1381}
1382
a7f3a06c
ID		 1383/*
1384 * Initialization functions.
1385 */
798b7adb 1386static bool rt61pci_get_entry_state(struct queue_entry *entry)
95ea3627 1387{
b8be63ff 1388 struct queue_entry_priv_pci *entry_priv = entry->priv_data;
95ea3627
ID		 1389 u32 word;
1390
798b7adb
ID		 1391 if (entry->queue->qid == QID_RX) {
1392 rt2x00_desc_read(entry_priv->desc, 0, &word);
95ea3627 1393
798b7adb
ID		 1394 return rt2x00_get_field32(word, RXD_W0_OWNER_NIC);
1395 } else {
1396 rt2x00_desc_read(entry_priv->desc, 0, &word);
1397
1398 return (rt2x00_get_field32(word, TXD_W0_OWNER_NIC) ||
1399 rt2x00_get_field32(word, TXD_W0_VALID));
1400 }
95ea3627
ID		 1401}
1402
798b7adb 1403static void rt61pci_clear_entry(struct queue_entry *entry)
95ea3627 1404{
b8be63ff 1405 struct queue_entry_priv_pci *entry_priv = entry->priv_data;
798b7adb 1406 struct skb_frame_desc *skbdesc = get_skb_frame_desc(entry->skb);
95ea3627
ID		 1407 u32 word;
1408
798b7adb
ID		 1409 if (entry->queue->qid == QID_RX) {
1410 rt2x00_desc_read(entry_priv->desc, 5, &word);
1411 rt2x00_set_field32(&word, RXD_W5_BUFFER_PHYSICAL_ADDRESS,
1412 skbdesc->skb_dma);
1413 rt2x00_desc_write(entry_priv->desc, 5, word);
1414
1415 rt2x00_desc_read(entry_priv->desc, 0, &word);
1416 rt2x00_set_field32(&word, RXD_W0_OWNER_NIC, 1);
1417 rt2x00_desc_write(entry_priv->desc, 0, word);
1418 } else {
1419 rt2x00_desc_read(entry_priv->desc, 0, &word);
1420 rt2x00_set_field32(&word, TXD_W0_VALID, 0);
1421 rt2x00_set_field32(&word, TXD_W0_OWNER_NIC, 0);
1422 rt2x00_desc_write(entry_priv->desc, 0, word);
1423 }
95ea3627
ID		 1424}
1425
181d6902 1426static int rt61pci_init_queues(struct rt2x00_dev *rt2x00dev)
95ea3627 1427{
b8be63ff 1428 struct queue_entry_priv_pci *entry_priv;
95ea3627
ID		 1429 u32 reg;
1430
95ea3627
ID		 1431 /*
1432 * Initialize registers.
1433 */
1434 rt2x00pci_register_read(rt2x00dev, TX_RING_CSR0, &reg);
1435 rt2x00_set_field32(&reg, TX_RING_CSR0_AC0_RING_SIZE,
181d6902 1436 rt2x00dev->tx[0].limit);
95ea3627 1437 rt2x00_set_field32(&reg, TX_RING_CSR0_AC1_RING_SIZE,
181d6902 1438 rt2x00dev->tx[1].limit);
95ea3627 1439 rt2x00_set_field32(&reg, TX_RING_CSR0_AC2_RING_SIZE,
181d6902 1440 rt2x00dev->tx[2].limit);
95ea3627 1441 rt2x00_set_field32(&reg, TX_RING_CSR0_AC3_RING_SIZE,
181d6902 1442 rt2x00dev->tx[3].limit);
95ea3627
ID		 1443 rt2x00pci_register_write(rt2x00dev, TX_RING_CSR0, reg);
1444
1445 rt2x00pci_register_read(rt2x00dev, TX_RING_CSR1, &reg);
95ea3627 1446 rt2x00_set_field32(&reg, TX_RING_CSR1_TXD_SIZE,
181d6902 1447 rt2x00dev->tx[0].desc_size / 4);
95ea3627
ID		 1448 rt2x00pci_register_write(rt2x00dev, TX_RING_CSR1, reg);
1449
b8be63ff 1450 entry_priv = rt2x00dev->tx[0].entries[0].priv_data;
95ea3627 1451 rt2x00pci_register_read(rt2x00dev, AC0_BASE_CSR, &reg);
30b3a23c 1452 rt2x00_set_field32(&reg, AC0_BASE_CSR_RING_REGISTER,
b8be63ff 1453 entry_priv->desc_dma);
95ea3627
ID		 1454 rt2x00pci_register_write(rt2x00dev, AC0_BASE_CSR, reg);
1455
b8be63ff 1456 entry_priv = rt2x00dev->tx[1].entries[0].priv_data;
95ea3627 1457 rt2x00pci_register_read(rt2x00dev, AC1_BASE_CSR, &reg);
30b3a23c 1458 rt2x00_set_field32(&reg, AC1_BASE_CSR_RING_REGISTER,
b8be63ff 1459 entry_priv->desc_dma);
95ea3627
ID		 1460 rt2x00pci_register_write(rt2x00dev, AC1_BASE_CSR, reg);
1461
b8be63ff 1462 entry_priv = rt2x00dev->tx[2].entries[0].priv_data;
95ea3627 1463 rt2x00pci_register_read(rt2x00dev, AC2_BASE_CSR, &reg);
30b3a23c 1464 rt2x00_set_field32(&reg, AC2_BASE_CSR_RING_REGISTER,
b8be63ff 1465 entry_priv->desc_dma);
95ea3627
ID		 1466 rt2x00pci_register_write(rt2x00dev, AC2_BASE_CSR, reg);
1467
b8be63ff 1468 entry_priv = rt2x00dev->tx[3].entries[0].priv_data;
95ea3627 1469 rt2x00pci_register_read(rt2x00dev, AC3_BASE_CSR, &reg);
30b3a23c 1470 rt2x00_set_field32(&reg, AC3_BASE_CSR_RING_REGISTER,
b8be63ff 1471 entry_priv->desc_dma);
95ea3627
ID		 1472 rt2x00pci_register_write(rt2x00dev, AC3_BASE_CSR, reg);
1473
95ea3627 1474 rt2x00pci_register_read(rt2x00dev, RX_RING_CSR, &reg);
181d6902 1475 rt2x00_set_field32(&reg, RX_RING_CSR_RING_SIZE, rt2x00dev->rx->limit);
95ea3627
ID		 1476 rt2x00_set_field32(&reg, RX_RING_CSR_RXD_SIZE,
1477 rt2x00dev->rx->desc_size / 4);
1478 rt2x00_set_field32(&reg, RX_RING_CSR_RXD_WRITEBACK_SIZE, 4);
1479 rt2x00pci_register_write(rt2x00dev, RX_RING_CSR, reg);
1480
b8be63ff 1481 entry_priv = rt2x00dev->rx->entries[0].priv_data;
95ea3627 1482 rt2x00pci_register_read(rt2x00dev, RX_BASE_CSR, &reg);
30b3a23c 1483 rt2x00_set_field32(&reg, RX_BASE_CSR_RING_REGISTER,
b8be63ff 1484 entry_priv->desc_dma);
95ea3627
ID		 1485 rt2x00pci_register_write(rt2x00dev, RX_BASE_CSR, reg);
1486
1487 rt2x00pci_register_read(rt2x00dev, TX_DMA_DST_CSR, &reg);
1488 rt2x00_set_field32(&reg, TX_DMA_DST_CSR_DEST_AC0, 2);
1489 rt2x00_set_field32(&reg, TX_DMA_DST_CSR_DEST_AC1, 2);
1490 rt2x00_set_field32(&reg, TX_DMA_DST_CSR_DEST_AC2, 2);
1491 rt2x00_set_field32(&reg, TX_DMA_DST_CSR_DEST_AC3, 2);
95ea3627
ID		 1492 rt2x00pci_register_write(rt2x00dev, TX_DMA_DST_CSR, reg);
1493
1494 rt2x00pci_register_read(rt2x00dev, LOAD_TX_RING_CSR, &reg);
1495 rt2x00_set_field32(&reg, LOAD_TX_RING_CSR_LOAD_TXD_AC0, 1);
1496 rt2x00_set_field32(&reg, LOAD_TX_RING_CSR_LOAD_TXD_AC1, 1);
1497 rt2x00_set_field32(&reg, LOAD_TX_RING_CSR_LOAD_TXD_AC2, 1);
1498 rt2x00_set_field32(&reg, LOAD_TX_RING_CSR_LOAD_TXD_AC3, 1);
95ea3627
ID		 1499 rt2x00pci_register_write(rt2x00dev, LOAD_TX_RING_CSR, reg);
1500
1501 rt2x00pci_register_read(rt2x00dev, RX_CNTL_CSR, &reg);
1502 rt2x00_set_field32(&reg, RX_CNTL_CSR_LOAD_RXD, 1);
1503 rt2x00pci_register_write(rt2x00dev, RX_CNTL_CSR, reg);
1504
1505 return 0;
1506}
1507
1508static int rt61pci_init_registers(struct rt2x00_dev *rt2x00dev)
1509{
1510 u32 reg;
1511
1512 rt2x00pci_register_read(rt2x00dev, TXRX_CSR0, &reg);
1513 rt2x00_set_field32(&reg, TXRX_CSR0_AUTO_TX_SEQ, 1);
1514 rt2x00_set_field32(&reg, TXRX_CSR0_DISABLE_RX, 0);
1515 rt2x00_set_field32(&reg, TXRX_CSR0_TX_WITHOUT_WAITING, 0);
1516 rt2x00pci_register_write(rt2x00dev, TXRX_CSR0, reg);
1517
1518 rt2x00pci_register_read(rt2x00dev, TXRX_CSR1, &reg);
1519 rt2x00_set_field32(&reg, TXRX_CSR1_BBP_ID0, 47); /* CCK Signal */
1520 rt2x00_set_field32(&reg, TXRX_CSR1_BBP_ID0_VALID, 1);
1521 rt2x00_set_field32(&reg, TXRX_CSR1_BBP_ID1, 30); /* Rssi */
1522 rt2x00_set_field32(&reg, TXRX_CSR1_BBP_ID1_VALID, 1);
1523 rt2x00_set_field32(&reg, TXRX_CSR1_BBP_ID2, 42); /* OFDM Rate */
1524 rt2x00_set_field32(&reg, TXRX_CSR1_BBP_ID2_VALID, 1);
1525 rt2x00_set_field32(&reg, TXRX_CSR1_BBP_ID3, 30); /* Rssi */
1526 rt2x00_set_field32(&reg, TXRX_CSR1_BBP_ID3_VALID, 1);
1527 rt2x00pci_register_write(rt2x00dev, TXRX_CSR1, reg);
1528
1529 /*
1530 * CCK TXD BBP registers
1531 */
1532 rt2x00pci_register_read(rt2x00dev, TXRX_CSR2, &reg);
1533 rt2x00_set_field32(&reg, TXRX_CSR2_BBP_ID0, 13);
1534 rt2x00_set_field32(&reg, TXRX_CSR2_BBP_ID0_VALID, 1);
1535 rt2x00_set_field32(&reg, TXRX_CSR2_BBP_ID1, 12);
1536 rt2x00_set_field32(&reg, TXRX_CSR2_BBP_ID1_VALID, 1);
1537 rt2x00_set_field32(&reg, TXRX_CSR2_BBP_ID2, 11);
1538 rt2x00_set_field32(&reg, TXRX_CSR2_BBP_ID2_VALID, 1);
1539 rt2x00_set_field32(&reg, TXRX_CSR2_BBP_ID3, 10);
1540 rt2x00_set_field32(&reg, TXRX_CSR2_BBP_ID3_VALID, 1);
1541 rt2x00pci_register_write(rt2x00dev, TXRX_CSR2, reg);
1542
1543 /*
1544 * OFDM TXD BBP registers
1545 */
1546 rt2x00pci_register_read(rt2x00dev, TXRX_CSR3, &reg);
1547 rt2x00_set_field32(&reg, TXRX_CSR3_BBP_ID0, 7);
1548 rt2x00_set_field32(&reg, TXRX_CSR3_BBP_ID0_VALID, 1);
1549 rt2x00_set_field32(&reg, TXRX_CSR3_BBP_ID1, 6);
1550 rt2x00_set_field32(&reg, TXRX_CSR3_BBP_ID1_VALID, 1);
1551 rt2x00_set_field32(&reg, TXRX_CSR3_BBP_ID2, 5);
1552 rt2x00_set_field32(&reg, TXRX_CSR3_BBP_ID2_VALID, 1);
1553 rt2x00pci_register_write(rt2x00dev, TXRX_CSR3, reg);
1554
1555 rt2x00pci_register_read(rt2x00dev, TXRX_CSR7, &reg);
1556 rt2x00_set_field32(&reg, TXRX_CSR7_ACK_CTS_6MBS, 59);
1557 rt2x00_set_field32(&reg, TXRX_CSR7_ACK_CTS_9MBS, 53);
1558 rt2x00_set_field32(&reg, TXRX_CSR7_ACK_CTS_12MBS, 49);
1559 rt2x00_set_field32(&reg, TXRX_CSR7_ACK_CTS_18MBS, 46);
1560 rt2x00pci_register_write(rt2x00dev, TXRX_CSR7, reg);
1561
1562 rt2x00pci_register_read(rt2x00dev, TXRX_CSR8, &reg);
1563 rt2x00_set_field32(&reg, TXRX_CSR8_ACK_CTS_24MBS, 44);
1564 rt2x00_set_field32(&reg, TXRX_CSR8_ACK_CTS_36MBS, 42);
1565 rt2x00_set_field32(&reg, TXRX_CSR8_ACK_CTS_48MBS, 42);
1566 rt2x00_set_field32(&reg, TXRX_CSR8_ACK_CTS_54MBS, 42);
1567 rt2x00pci_register_write(rt2x00dev, TXRX_CSR8, reg);
1568
1f909162
ID		 1569 rt2x00pci_register_read(rt2x00dev, TXRX_CSR9, &reg);
1570 rt2x00_set_field32(&reg, TXRX_CSR9_BEACON_INTERVAL, 0);
1571 rt2x00_set_field32(&reg, TXRX_CSR9_TSF_TICKING, 0);
1572 rt2x00_set_field32(&reg, TXRX_CSR9_TSF_SYNC, 0);
1573 rt2x00_set_field32(&reg, TXRX_CSR9_TBTT_ENABLE, 0);
1574 rt2x00_set_field32(&reg, TXRX_CSR9_BEACON_GEN, 0);
1575 rt2x00_set_field32(&reg, TXRX_CSR9_TIMESTAMP_COMPENSATE, 0);
1576 rt2x00pci_register_write(rt2x00dev, TXRX_CSR9, reg);
1577
95ea3627
ID		 1578 rt2x00pci_register_write(rt2x00dev, TXRX_CSR15, 0x0000000f);
1579
1580 rt2x00pci_register_write(rt2x00dev, MAC_CSR6, 0x00000fff);
1581
1582 rt2x00pci_register_read(rt2x00dev, MAC_CSR9, &reg);
1583 rt2x00_set_field32(&reg, MAC_CSR9_CW_SELECT, 0);
1584 rt2x00pci_register_write(rt2x00dev, MAC_CSR9, reg);
1585
1586 rt2x00pci_register_write(rt2x00dev, MAC_CSR10, 0x0000071c);
1587
1588 if (rt2x00dev->ops->lib->set_device_state(rt2x00dev, STATE_AWAKE))
1589 return -EBUSY;
1590
1591 rt2x00pci_register_write(rt2x00dev, MAC_CSR13, 0x0000e000);
1592
1593 /*
1594 * Invalidate all Shared Keys (SEC_CSR0),
1595 * and clear the Shared key Cipher algorithms (SEC_CSR1 & SEC_CSR5)
1596 */
1597 rt2x00pci_register_write(rt2x00dev, SEC_CSR0, 0x00000000);
1598 rt2x00pci_register_write(rt2x00dev, SEC_CSR1, 0x00000000);
1599 rt2x00pci_register_write(rt2x00dev, SEC_CSR5, 0x00000000);
1600
1601 rt2x00pci_register_write(rt2x00dev, PHY_CSR1, 0x000023b0);
1602 rt2x00pci_register_write(rt2x00dev, PHY_CSR5, 0x060a100c);
1603 rt2x00pci_register_write(rt2x00dev, PHY_CSR6, 0x00080606);
1604 rt2x00pci_register_write(rt2x00dev, PHY_CSR7, 0x00000a08);
1605
1606 rt2x00pci_register_write(rt2x00dev, PCI_CFG_CSR, 0x28ca4404);
1607
1608 rt2x00pci_register_write(rt2x00dev, TEST_MODE_CSR, 0x00000200);
1609
1610 rt2x00pci_register_write(rt2x00dev, M2H_CMD_DONE_CSR, 0xffffffff);
1611
6bb40dd1
ID		 1612 /*
1613 * Clear all beacons
1614 * For the Beacon base registers we only need to clear
1615 * the first byte since that byte contains the VALID and OWNER
1616 * bits which (when set to 0) will invalidate the entire beacon.
1617 */
1618 rt2x00pci_register_write(rt2x00dev, HW_BEACON_BASE0, 0);
1619 rt2x00pci_register_write(rt2x00dev, HW_BEACON_BASE1, 0);
1620 rt2x00pci_register_write(rt2x00dev, HW_BEACON_BASE2, 0);
1621 rt2x00pci_register_write(rt2x00dev, HW_BEACON_BASE3, 0);
1622
95ea3627
ID		 1623 /*
1624 * We must clear the error counters.
1625 * These registers are cleared on read,
1626 * so we may pass a useless variable to store the value.
1627 */
1628 rt2x00pci_register_read(rt2x00dev, STA_CSR0, &reg);
1629 rt2x00pci_register_read(rt2x00dev, STA_CSR1, &reg);
1630 rt2x00pci_register_read(rt2x00dev, STA_CSR2, &reg);
1631
1632 /*
1633 * Reset MAC and BBP registers.
1634 */
1635 rt2x00pci_register_read(rt2x00dev, MAC_CSR1, &reg);
1636 rt2x00_set_field32(&reg, MAC_CSR1_SOFT_RESET, 1);
1637 rt2x00_set_field32(&reg, MAC_CSR1_BBP_RESET, 1);
1638 rt2x00pci_register_write(rt2x00dev, MAC_CSR1, reg);
1639
1640 rt2x00pci_register_read(rt2x00dev, MAC_CSR1, &reg);
1641 rt2x00_set_field32(&reg, MAC_CSR1_SOFT_RESET, 0);
1642 rt2x00_set_field32(&reg, MAC_CSR1_BBP_RESET, 0);
1643 rt2x00pci_register_write(rt2x00dev, MAC_CSR1, reg);
1644
1645 rt2x00pci_register_read(rt2x00dev, MAC_CSR1, &reg);
1646 rt2x00_set_field32(&reg, MAC_CSR1_HOST_READY, 1);
1647 rt2x00pci_register_write(rt2x00dev, MAC_CSR1, reg);
1648
1649 return 0;
1650}
1651
2b08da3f 1652static int rt61pci_wait_bbp_ready(struct rt2x00_dev *rt2x00dev)
95ea3627
ID		 1653{
1654 unsigned int i;
95ea3627
ID		 1655 u8 value;
1656
1657 for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
1658 rt61pci_bbp_read(rt2x00dev, 0, &value);
1659 if ((value != 0xff) && (value != 0x00))
2b08da3f 1660 return 0;
95ea3627
ID		 1661 udelay(REGISTER_BUSY_DELAY);
1662 }
1663
1664 ERROR(rt2x00dev, "BBP register access failed, aborting.\n");
1665 return -EACCES;
2b08da3f
ID		 1666}
1667
1668static int rt61pci_init_bbp(struct rt2x00_dev *rt2x00dev)
1669{
1670 unsigned int i;
1671 u16 eeprom;
1672 u8 reg_id;
1673 u8 value;
1674
1675 if (unlikely(rt61pci_wait_bbp_ready(rt2x00dev)))
1676 return -EACCES;
95ea3627 1677
95ea3627
ID		 1678 rt61pci_bbp_write(rt2x00dev, 3, 0x00);
1679 rt61pci_bbp_write(rt2x00dev, 15, 0x30);
1680 rt61pci_bbp_write(rt2x00dev, 21, 0xc8);
1681 rt61pci_bbp_write(rt2x00dev, 22, 0x38);
1682 rt61pci_bbp_write(rt2x00dev, 23, 0x06);
1683 rt61pci_bbp_write(rt2x00dev, 24, 0xfe);
1684 rt61pci_bbp_write(rt2x00dev, 25, 0x0a);
1685 rt61pci_bbp_write(rt2x00dev, 26, 0x0d);
1686 rt61pci_bbp_write(rt2x00dev, 34, 0x12);
1687 rt61pci_bbp_write(rt2x00dev, 37, 0x07);
1688 rt61pci_bbp_write(rt2x00dev, 39, 0xf8);
1689 rt61pci_bbp_write(rt2x00dev, 41, 0x60);
1690 rt61pci_bbp_write(rt2x00dev, 53, 0x10);
1691 rt61pci_bbp_write(rt2x00dev, 54, 0x18);
1692 rt61pci_bbp_write(rt2x00dev, 60, 0x10);
1693 rt61pci_bbp_write(rt2x00dev, 61, 0x04);
1694 rt61pci_bbp_write(rt2x00dev, 62, 0x04);
1695 rt61pci_bbp_write(rt2x00dev, 75, 0xfe);
1696 rt61pci_bbp_write(rt2x00dev, 86, 0xfe);
1697 rt61pci_bbp_write(rt2x00dev, 88, 0xfe);
1698 rt61pci_bbp_write(rt2x00dev, 90, 0x0f);
1699 rt61pci_bbp_write(rt2x00dev, 99, 0x00);
1700 rt61pci_bbp_write(rt2x00dev, 102, 0x16);
1701 rt61pci_bbp_write(rt2x00dev, 107, 0x04);
1702
95ea3627
ID		 1703 for (i = 0; i < EEPROM_BBP_SIZE; i++) {
1704 rt2x00_eeprom_read(rt2x00dev, EEPROM_BBP_START + i, &eeprom);
1705
1706 if (eeprom != 0xffff && eeprom != 0x0000) {
1707 reg_id = rt2x00_get_field16(eeprom, EEPROM_BBP_REG_ID);
1708 value = rt2x00_get_field16(eeprom, EEPROM_BBP_VALUE);
95ea3627
ID		 1709 rt61pci_bbp_write(rt2x00dev, reg_id, value);
1710 }
1711 }
95ea3627
ID		 1712
1713 return 0;
1714}
1715
1716/*
1717 * Device state switch handlers.
1718 */
95ea3627
ID		 1719static void rt61pci_toggle_irq(struct rt2x00_dev *rt2x00dev,
1720 enum dev_state state)
1721{
78e256c9
HS		 1722 int mask = (state == STATE_RADIO_IRQ_OFF) ||
1723 (state == STATE_RADIO_IRQ_OFF_ISR);
95ea3627
ID		 1724 u32 reg;
1725
1726 /*
1727 * When interrupts are being enabled, the interrupt registers
1728 * should clear the register to assure a clean state.
1729 */
1730 if (state == STATE_RADIO_IRQ_ON) {
1731 rt2x00pci_register_read(rt2x00dev, INT_SOURCE_CSR, &reg);
1732 rt2x00pci_register_write(rt2x00dev, INT_SOURCE_CSR, reg);
1733
1734 rt2x00pci_register_read(rt2x00dev, MCU_INT_SOURCE_CSR, &reg);
1735 rt2x00pci_register_write(rt2x00dev, MCU_INT_SOURCE_CSR, reg);
1736 }
1737
1738 /*
1739 * Only toggle the interrupts bits we are going to use.
1740 * Non-checked interrupt bits are disabled by default.
1741 */
1742 rt2x00pci_register_read(rt2x00dev, INT_MASK_CSR, &reg);
1743 rt2x00_set_field32(&reg, INT_MASK_CSR_TXDONE, mask);
1744 rt2x00_set_field32(&reg, INT_MASK_CSR_RXDONE, mask);
6646505d 1745 rt2x00_set_field32(&reg, INT_MASK_CSR_BEACON_DONE, mask);
95ea3627
ID		 1746 rt2x00_set_field32(&reg, INT_MASK_CSR_ENABLE_MITIGATION, mask);
1747 rt2x00_set_field32(&reg, INT_MASK_CSR_MITIGATION_PERIOD, 0xff);
1748 rt2x00pci_register_write(rt2x00dev, INT_MASK_CSR, reg);
1749
1750 rt2x00pci_register_read(rt2x00dev, MCU_INT_MASK_CSR, &reg);
1751 rt2x00_set_field32(&reg, MCU_INT_MASK_CSR_0, mask);
1752 rt2x00_set_field32(&reg, MCU_INT_MASK_CSR_1, mask);
1753 rt2x00_set_field32(&reg, MCU_INT_MASK_CSR_2, mask);
1754 rt2x00_set_field32(&reg, MCU_INT_MASK_CSR_3, mask);
1755 rt2x00_set_field32(&reg, MCU_INT_MASK_CSR_4, mask);
1756 rt2x00_set_field32(&reg, MCU_INT_MASK_CSR_5, mask);
1757 rt2x00_set_field32(&reg, MCU_INT_MASK_CSR_6, mask);
1758 rt2x00_set_field32(&reg, MCU_INT_MASK_CSR_7, mask);
6646505d 1759 rt2x00_set_field32(&reg, MCU_INT_MASK_CSR_TWAKEUP, mask);
95ea3627
ID		 1760 rt2x00pci_register_write(rt2x00dev, MCU_INT_MASK_CSR, reg);
1761}
1762
1763static int rt61pci_enable_radio(struct rt2x00_dev *rt2x00dev)
1764{
1765 u32 reg;
1766
1767 /*
1768 * Initialize all registers.
1769 */
2b08da3f
ID		 1770 if (unlikely(rt61pci_init_queues(rt2x00dev) ||
1771 rt61pci_init_registers(rt2x00dev) ||
1772 rt61pci_init_bbp(rt2x00dev)))
95ea3627 1773 return -EIO;
95ea3627
ID		 1774
1775 /*
1776 * Enable RX.
1777 */
1778 rt2x00pci_register_read(rt2x00dev, RX_CNTL_CSR, &reg);
1779 rt2x00_set_field32(&reg, RX_CNTL_CSR_ENABLE_RX_DMA, 1);
1780 rt2x00pci_register_write(rt2x00dev, RX_CNTL_CSR, reg);
1781
95ea3627
ID		 1782 return 0;
1783}
1784
1785static void rt61pci_disable_radio(struct rt2x00_dev *rt2x00dev)
1786{
95ea3627 1787 /*
a2c9b652 1788 * Disable power
95ea3627 1789 */
a2c9b652 1790 rt2x00pci_register_write(rt2x00dev, MAC_CSR10, 0x00001818);
95ea3627
ID		 1791}
1792
1793static int rt61pci_set_state(struct rt2x00_dev *rt2x00dev, enum dev_state state)
1794{
9655a6ec 1795 u32 reg, reg2;
95ea3627
ID		 1796 unsigned int i;
1797 char put_to_sleep;
95ea3627
ID		 1798
1799 put_to_sleep = (state != STATE_AWAKE);
1800
1801 rt2x00pci_register_read(rt2x00dev, MAC_CSR12, &reg);
1802 rt2x00_set_field32(&reg, MAC_CSR12_FORCE_WAKEUP, !put_to_sleep);
1803 rt2x00_set_field32(&reg, MAC_CSR12_PUT_TO_SLEEP, put_to_sleep);
1804 rt2x00pci_register_write(rt2x00dev, MAC_CSR12, reg);
1805
1806 /*
1807 * Device is not guaranteed to be in the requested state yet.
1808 * We must wait until the register indicates that the
1809 * device has entered the correct state.
1810 */
1811 for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
9655a6ec
GW		 1812 rt2x00pci_register_read(rt2x00dev, MAC_CSR12, &reg2);
1813 state = rt2x00_get_field32(reg2, MAC_CSR12_BBP_CURRENT_STATE);
2b08da3f 1814 if (state == !put_to_sleep)
95ea3627 1815 return 0;
9655a6ec 1816 rt2x00pci_register_write(rt2x00dev, MAC_CSR12, reg);
95ea3627
ID		 1817 msleep(10);
1818 }
1819
95ea3627
ID		 1820 return -EBUSY;
1821}
1822
1823static int rt61pci_set_device_state(struct rt2x00_dev *rt2x00dev,
1824 enum dev_state state)
1825{
1826 int retval = 0;
1827
1828 switch (state) {
1829 case STATE_RADIO_ON:
1830 retval = rt61pci_enable_radio(rt2x00dev);
1831 break;
1832 case STATE_RADIO_OFF:
1833 rt61pci_disable_radio(rt2x00dev);
1834 break;
2b08da3f 1835 case STATE_RADIO_IRQ_ON:
78e256c9 1836 case STATE_RADIO_IRQ_ON_ISR:
2b08da3f 1837 case STATE_RADIO_IRQ_OFF:
78e256c9 1838 case STATE_RADIO_IRQ_OFF_ISR:
2b08da3f 1839 rt61pci_toggle_irq(rt2x00dev, state);
95ea3627
ID		 1840 break;
1841 case STATE_DEEP_SLEEP:
1842 case STATE_SLEEP:
1843 case STATE_STANDBY:
1844 case STATE_AWAKE:
1845 retval = rt61pci_set_state(rt2x00dev, state);
1846 break;
1847 default:
1848 retval = -ENOTSUPP;
1849 break;
1850 }
1851
2b08da3f
ID		 1852 if (unlikely(retval))
1853 ERROR(rt2x00dev, "Device failed to enter state %d (%d).\n",
1854 state, retval);
1855
95ea3627
ID		 1856 return retval;
1857}
1858
1859/*
1860 * TX descriptor initialization
1861 */
93331458 1862static void rt61pci_write_tx_desc(struct queue_entry *entry,
61e754f4 1863 struct txentry_desc *txdesc)
95ea3627 1864{
93331458
ID		 1865 struct skb_frame_desc *skbdesc = get_skb_frame_desc(entry->skb);
1866 struct queue_entry_priv_pci *entry_priv = entry->priv_data;
85b7a8b3 1867 __le32 *txd = entry_priv->desc;
95ea3627
ID		 1868 u32 word;
1869
1870 /*
1871 * Start writing the descriptor words.
1872 */
1873 rt2x00_desc_read(txd, 1, &word);
2b23cdaa
HS		 1874 rt2x00_set_field32(&word, TXD_W1_HOST_Q_ID, entry->queue->qid);
1875 rt2x00_set_field32(&word, TXD_W1_AIFSN, entry->queue->aifs);
1876 rt2x00_set_field32(&word, TXD_W1_CWMIN, entry->queue->cw_min);
1877 rt2x00_set_field32(&word, TXD_W1_CWMAX, entry->queue->cw_max);
61e754f4 1878 rt2x00_set_field32(&word, TXD_W1_IV_OFFSET, txdesc->iv_offset);
5adf6d63
ID		 1879 rt2x00_set_field32(&word, TXD_W1_HW_SEQUENCE,
1880 test_bit(ENTRY_TXD_GENERATE_SEQ, &txdesc->flags));
4de36fe5 1881 rt2x00_set_field32(&word, TXD_W1_BUFFER_COUNT, 1);
95ea3627
ID		 1882 rt2x00_desc_write(txd, 1, word);
1883
1884 rt2x00_desc_read(txd, 2, &word);
181d6902
ID		 1885 rt2x00_set_field32(&word, TXD_W2_PLCP_SIGNAL, txdesc->signal);
1886 rt2x00_set_field32(&word, TXD_W2_PLCP_SERVICE, txdesc->service);
1887 rt2x00_set_field32(&word, TXD_W2_PLCP_LENGTH_LOW, txdesc->length_low);
1888 rt2x00_set_field32(&word, TXD_W2_PLCP_LENGTH_HIGH, txdesc->length_high);
95ea3627
ID		 1889 rt2x00_desc_write(txd, 2, word);
1890
61e754f4 1891 if (test_bit(ENTRY_TXD_ENCRYPT, &txdesc->flags)) {
1ce9cdac
ID		 1892 _rt2x00_desc_write(txd, 3, skbdesc->iv[0]);
1893 _rt2x00_desc_write(txd, 4, skbdesc->iv[1]);
61e754f4
ID		 1894 }
1895
95ea3627 1896 rt2x00_desc_read(txd, 5, &word);
93331458 1897 rt2x00_set_field32(&word, TXD_W5_PID_TYPE, entry->queue->qid);
4de36fe5
GW		 1898 rt2x00_set_field32(&word, TXD_W5_PID_SUBTYPE,
1899 skbdesc->entry->entry_idx);
95ea3627 1900 rt2x00_set_field32(&word, TXD_W5_TX_POWER,
93331458 1901 TXPOWER_TO_DEV(entry->queue->rt2x00dev->tx_power));
95ea3627
ID		 1902 rt2x00_set_field32(&word, TXD_W5_WAITING_DMA_DONE_INT, 1);
1903 rt2x00_desc_write(txd, 5, word);
1904
2b23cdaa 1905 if (entry->queue->qid != QID_BEACON) {
6b97cb04
GW		 1906 rt2x00_desc_read(txd, 6, &word);
1907 rt2x00_set_field32(&word, TXD_W6_BUFFER_PHYSICAL_ADDRESS,
1908 skbdesc->skb_dma);
1909 rt2x00_desc_write(txd, 6, word);
4de36fe5 1910
d7bafff3 1911 rt2x00_desc_read(txd, 11, &word);
df624ca5
GW		 1912 rt2x00_set_field32(&word, TXD_W11_BUFFER_LENGTH0,
1913 txdesc->length);
d7bafff3
AB		 1914 rt2x00_desc_write(txd, 11, word);
1915 }
95ea3627 1916
e01f1ec3
GW		 1917 /*
1918 * Writing TXD word 0 must the last to prevent a race condition with
1919 * the device, whereby the device may take hold of the TXD before we
1920 * finished updating it.
1921 */
95ea3627
ID		 1922 rt2x00_desc_read(txd, 0, &word);
1923 rt2x00_set_field32(&word, TXD_W0_OWNER_NIC, 1);
1924 rt2x00_set_field32(&word, TXD_W0_VALID, 1);
1925 rt2x00_set_field32(&word, TXD_W0_MORE_FRAG,
181d6902 1926 test_bit(ENTRY_TXD_MORE_FRAG, &txdesc->flags));
95ea3627 1927 rt2x00_set_field32(&word, TXD_W0_ACK,
181d6902 1928 test_bit(ENTRY_TXD_ACK, &txdesc->flags));
95ea3627 1929 rt2x00_set_field32(&word, TXD_W0_TIMESTAMP,
181d6902 1930 test_bit(ENTRY_TXD_REQ_TIMESTAMP, &txdesc->flags));
95ea3627 1931 rt2x00_set_field32(&word, TXD_W0_OFDM,
076f9582 1932 (txdesc->rate_mode == RATE_MODE_OFDM));
181d6902 1933 rt2x00_set_field32(&word, TXD_W0_IFS, txdesc->ifs);
95ea3627 1934 rt2x00_set_field32(&word, TXD_W0_RETRY_MODE,
61486e0f 1935 test_bit(ENTRY_TXD_RETRY_MODE, &txdesc->flags));
61e754f4
ID		 1936 rt2x00_set_field32(&word, TXD_W0_TKIP_MIC,
1937 test_bit(ENTRY_TXD_ENCRYPT_MMIC, &txdesc->flags));
1938 rt2x00_set_field32(&word, TXD_W0_KEY_TABLE,
1939 test_bit(ENTRY_TXD_ENCRYPT_PAIRWISE, &txdesc->flags));
1940 rt2x00_set_field32(&word, TXD_W0_KEY_INDEX, txdesc->key_idx);
df624ca5 1941 rt2x00_set_field32(&word, TXD_W0_DATABYTE_COUNT, txdesc->length);
95ea3627 1942 rt2x00_set_field32(&word, TXD_W0_BURST,
181d6902 1943 test_bit(ENTRY_TXD_BURST, &txdesc->flags));
61e754f4 1944 rt2x00_set_field32(&word, TXD_W0_CIPHER_ALG, txdesc->cipher);
95ea3627 1945 rt2x00_desc_write(txd, 0, word);
85b7a8b3
GW		 1946
1947 /*
1948 * Register descriptor details in skb frame descriptor.
1949 */
1950 skbdesc->desc = txd;
2b23cdaa
HS		 1951 skbdesc->desc_len = (entry->queue->qid == QID_BEACON) ? TXINFO_SIZE :
1952 TXD_DESC_SIZE;
95ea3627
ID		 1953}
1954
1955/*
1956 * TX data initialization
1957 */
f224f4ef
GW		 1958static void rt61pci_write_beacon(struct queue_entry *entry,
1959 struct txentry_desc *txdesc)
bd88a781
ID		 1960{
1961 struct rt2x00_dev *rt2x00dev = entry->queue->rt2x00dev;
85b7a8b3 1962 struct queue_entry_priv_pci *entry_priv = entry->priv_data;
bd88a781
ID		 1963 unsigned int beacon_base;
1964 u32 reg;
1965
1966 /*
1967 * Disable beaconing while we are reloading the beacon data,
1968 * otherwise we might be sending out invalid data.
1969 */
1970 rt2x00pci_register_read(rt2x00dev, TXRX_CSR9, &reg);
bd88a781
ID		 1971 rt2x00_set_field32(&reg, TXRX_CSR9_BEACON_GEN, 0);
1972 rt2x00pci_register_write(rt2x00dev, TXRX_CSR9, reg);
1973
5c3b685c
GW		 1974 /*
1975 * Write the TX descriptor for the beacon.
1976 */
93331458 1977 rt61pci_write_tx_desc(entry, txdesc);
5c3b685c
GW		 1978
1979 /*
1980 * Dump beacon to userspace through debugfs.
1981 */
1982 rt2x00debug_dump_frame(rt2x00dev, DUMP_FRAME_BEACON, entry->skb);
1983
bd88a781
ID		 1984 /*
1985 * Write entire beacon with descriptor to register.
1986 */
1987 beacon_base = HW_BEACON_OFFSET(entry->entry_idx);
85b7a8b3
GW		 1988 rt2x00pci_register_multiwrite(rt2x00dev, beacon_base,
1989 entry_priv->desc, TXINFO_SIZE);
1990 rt2x00pci_register_multiwrite(rt2x00dev, beacon_base + TXINFO_SIZE,
bd88a781
ID		 1991 entry->skb->data, entry->skb->len);
1992
d61cb266
GW		 1993 /*
1994 * Enable beaconing again.
1995 *
1996 * For Wi-Fi faily generated beacons between participating
1997 * stations. Set TBTT phase adaptive adjustment step to 8us.
1998 */
1999 rt2x00pci_register_write(rt2x00dev, TXRX_CSR10, 0x00001008);
2000
2001 rt2x00_set_field32(&reg, TXRX_CSR9_TSF_TICKING, 1);
2002 rt2x00_set_field32(&reg, TXRX_CSR9_TBTT_ENABLE, 1);
2003 rt2x00_set_field32(&reg, TXRX_CSR9_BEACON_GEN, 1);
2004 rt2x00pci_register_write(rt2x00dev, TXRX_CSR9, reg);
2005
bd88a781
ID		 2006 /*
2007 * Clean up beacon skb.
2008 */
2009 dev_kfree_skb_any(entry->skb);
2010 entry->skb = NULL;
2011}
2012
95ea3627
ID		 2013/*
2014 * RX control handlers
2015 */
2016static int rt61pci_agc_to_rssi(struct rt2x00_dev *rt2x00dev, int rxd_w1)
2017{
ba2ab471 2018 u8 offset = rt2x00dev->lna_gain;
95ea3627
ID		 2019 u8 lna;
2020
2021 lna = rt2x00_get_field32(rxd_w1, RXD_W1_RSSI_LNA);
2022 switch (lna) {
2023 case 3:
ba2ab471 2024 offset += 90;
95ea3627
ID		 2025 break;
2026 case 2:
ba2ab471 2027 offset += 74;
95ea3627
ID		 2028 break;
2029 case 1:
ba2ab471 2030 offset += 64;
95ea3627
ID		 2031 break;
2032 default:
2033 return 0;
2034 }
2035
e5ef5bad 2036 if (rt2x00dev->curr_band == IEEE80211_BAND_5GHZ) {
95ea3627
ID		 2037 if (lna == 3 || lna == 2)
2038 offset += 10;
95ea3627
ID		 2039 }
2040
2041 return rt2x00_get_field32(rxd_w1, RXD_W1_RSSI_AGC) * 2 - offset;
2042}
2043
181d6902 2044static void rt61pci_fill_rxdone(struct queue_entry *entry,
55887511 2045 struct rxdone_entry_desc *rxdesc)
95ea3627 2046{
61e754f4 2047 struct rt2x00_dev *rt2x00dev = entry->queue->rt2x00dev;
b8be63ff 2048 struct queue_entry_priv_pci *entry_priv = entry->priv_data;
95ea3627
ID		 2049 u32 word0;
2050 u32 word1;
2051
b8be63ff
ID		 2052 rt2x00_desc_read(entry_priv->desc, 0, &word0);
2053 rt2x00_desc_read(entry_priv->desc, 1, &word1);
95ea3627 2054
4150c572 2055 if (rt2x00_get_field32(word0, RXD_W0_CRC_ERROR))
181d6902 2056 rxdesc->flags |= RX_FLAG_FAILED_FCS_CRC;
95ea3627 2057
78b8f3b0
GW		 2058 rxdesc->cipher = rt2x00_get_field32(word0, RXD_W0_CIPHER_ALG);
2059 rxdesc->cipher_status = rt2x00_get_field32(word0, RXD_W0_CIPHER_ERROR);
61e754f4
ID		 2060
2061 if (rxdesc->cipher != CIPHER_NONE) {
1ce9cdac
ID		 2062 _rt2x00_desc_read(entry_priv->desc, 2, &rxdesc->iv[0]);
2063 _rt2x00_desc_read(entry_priv->desc, 3, &rxdesc->iv[1]);
74415edb
ID		 2064 rxdesc->dev_flags |= RXDONE_CRYPTO_IV;
2065
61e754f4 2066 _rt2x00_desc_read(entry_priv->desc, 4, &rxdesc->icv);
74415edb 2067 rxdesc->dev_flags |= RXDONE_CRYPTO_ICV;
61e754f4
ID		 2068
2069 /*
2070 * Hardware has stripped IV/EIV data from 802.11 frame during
b34e620f 2071 * decryption. It has provided the data separately but rt2x00lib
61e754f4
ID		 2072 * should decide if it should be reinserted.
2073 */
2074 rxdesc->flags |= RX_FLAG_IV_STRIPPED;
2075
2076 /*
2077 * FIXME: Legacy driver indicates that the frame does
2078 * contain the Michael Mic. Unfortunately, in rt2x00
2079 * the MIC seems to be missing completely...
2080 */
2081 rxdesc->flags |= RX_FLAG_MMIC_STRIPPED;
2082
2083 if (rxdesc->cipher_status == RX_CRYPTO_SUCCESS)
2084 rxdesc->flags |= RX_FLAG_DECRYPTED;
2085 else if (rxdesc->cipher_status == RX_CRYPTO_FAIL_MIC)
2086 rxdesc->flags |= RX_FLAG_MMIC_ERROR;
2087 }
2088
95ea3627
ID		 2089 /*
2090 * Obtain the status about this packet.
89993890
ID		 2091 * When frame was received with an OFDM bitrate,
2092 * the signal is the PLCP value. If it was received with
2093 * a CCK bitrate the signal is the rate in 100kbit/s.
95ea3627 2094 */
181d6902 2095 rxdesc->signal = rt2x00_get_field32(word1, RXD_W1_SIGNAL);
61e754f4 2096 rxdesc->rssi = rt61pci_agc_to_rssi(rt2x00dev, word1);
181d6902 2097 rxdesc->size = rt2x00_get_field32(word0, RXD_W0_DATABYTE_COUNT);
19d30e02 2098
19d30e02
ID		 2099 if (rt2x00_get_field32(word0, RXD_W0_OFDM))
2100 rxdesc->dev_flags |= RXDONE_SIGNAL_PLCP;
6c6aa3c0
ID		 2101 else
2102 rxdesc->dev_flags |= RXDONE_SIGNAL_BITRATE;
19d30e02
ID		 2103 if (rt2x00_get_field32(word0, RXD_W0_MY_BSS))
2104 rxdesc->dev_flags |= RXDONE_MY_BSS;
95ea3627
ID		 2105}
2106
2107/*
2108 * Interrupt functions.
2109 */
2110static void rt61pci_txdone(struct rt2x00_dev *rt2x00dev)
2111{
181d6902
ID		 2112 struct data_queue *queue;
2113 struct queue_entry *entry;
2114 struct queue_entry *entry_done;
b8be63ff 2115 struct queue_entry_priv_pci *entry_priv;
181d6902 2116 struct txdone_entry_desc txdesc;
95ea3627
ID		 2117 u32 word;
2118 u32 reg;
95ea3627
ID		 2119 int type;
2120 int index;
e6474c3c 2121 int i;
95ea3627
ID		 2122
2123 /*
e6474c3c
ID		 2124 * TX_STA_FIFO is a stack of X entries, hence read TX_STA_FIFO
2125 * at most X times and also stop processing once the TX_STA_FIFO_VALID
2126 * flag is not set anymore.
2127 *
2128 * The legacy drivers use X=TX_RING_SIZE but state in a comment
2129 * that the TX_STA_FIFO stack has a size of 16. We stick to our
2130 * tx ring size for now.
95ea3627 2131 */
efd2f271 2132 for (i = 0; i < rt2x00dev->ops->tx->entry_num; i++) {
95ea3627
ID		 2133 rt2x00pci_register_read(rt2x00dev, STA_CSR4, &reg);
2134 if (!rt2x00_get_field32(reg, STA_CSR4_VALID))
2135 break;
2136
95ea3627
ID		 2137 /*
2138 * Skip this entry when it contains an invalid
181d6902 2139 * queue identication number.
95ea3627
ID		 2140 */
2141 type = rt2x00_get_field32(reg, STA_CSR4_PID_TYPE);
181d6902
ID		 2142 queue = rt2x00queue_get_queue(rt2x00dev, type);
2143 if (unlikely(!queue))
95ea3627
ID		 2144 continue;
2145
2146 /*
2147 * Skip this entry when it contains an invalid
2148 * index number.
2149 */
2150 index = rt2x00_get_field32(reg, STA_CSR4_PID_SUBTYPE);
181d6902 2151 if (unlikely(index >= queue->limit))
95ea3627
ID		 2152 continue;
2153
181d6902 2154 entry = &queue->entries[index];
b8be63ff
ID		 2155 entry_priv = entry->priv_data;
2156 rt2x00_desc_read(entry_priv->desc, 0, &word);
95ea3627
ID		 2157
2158 if (rt2x00_get_field32(word, TXD_W0_OWNER_NIC) ||
2159 !rt2x00_get_field32(word, TXD_W0_VALID))
2160 return;
2161
181d6902 2162 entry_done = rt2x00queue_get_entry(queue, Q_INDEX_DONE);
62bc060b 2163 while (entry != entry_done) {
181d6902
ID		 2164 /* Catch up.
2165 * Just report any entries we missed as failed.
2166 */
62bc060b 2167 WARNING(rt2x00dev,
181d6902
ID		 2168 "TX status report missed for entry %d\n",
2169 entry_done->entry_idx);
2170
65b7fc97 2171 rt2x00lib_txdone_noinfo(entry_done, TXDONE_UNKNOWN);
181d6902 2172 entry_done = rt2x00queue_get_entry(queue, Q_INDEX_DONE);
62bc060b
MN		 2173 }
2174
95ea3627
ID		 2175 /*
2176 * Obtain the status about this packet.
2177 */
fb55f4d1
ID		 2178 txdesc.flags = 0;
2179 switch (rt2x00_get_field32(reg, STA_CSR4_TX_RESULT)) {
2180 case 0: /* Success, maybe with retry */
2181 __set_bit(TXDONE_SUCCESS, &txdesc.flags);
2182 break;
2183 case 6: /* Failure, excessive retries */
2184 __set_bit(TXDONE_EXCESSIVE_RETRY, &txdesc.flags);
2185 /* Don't break, this is a failed frame! */
2186 default: /* Failure */
2187 __set_bit(TXDONE_FAILURE, &txdesc.flags);
2188 }
181d6902 2189 txdesc.retry = rt2x00_get_field32(reg, STA_CSR4_RETRY_COUNT);
95ea3627 2190
e1b4d7b7
ID		 2191 /*
2192 * the frame was retried at least once
2193 * -> hw used fallback rates
2194 */
2195 if (txdesc.retry)
2196 __set_bit(TXDONE_FALLBACK, &txdesc.flags);
2197
e513a0b6 2198 rt2x00lib_txdone(entry, &txdesc);
95ea3627
ID		 2199 }
2200}
2201
9e189446
GW		 2202static void rt61pci_wakeup(struct rt2x00_dev *rt2x00dev)
2203{
2204 struct ieee80211_conf conf = { .flags = 0 };
2205 struct rt2x00lib_conf libconf = { .conf = &conf };
2206
2207 rt61pci_config(rt2x00dev, &libconf, IEEE80211_CONF_CHANGE_PS);
2208}
2209
78e256c9 2210static irqreturn_t rt61pci_interrupt_thread(int irq, void *dev_instance)
95ea3627
ID		 2211{
2212 struct rt2x00_dev *rt2x00dev = dev_instance;
78e256c9
HS		 2213 u32 reg = rt2x00dev->irqvalue[0];
2214 u32 reg_mcu = rt2x00dev->irqvalue[1];
95ea3627
ID		 2215
2216 /*
2217 * Handle interrupts, walk through all bits
2218 * and run the tasks, the bits are checked in order of
2219 * priority.
2220 */
2221
2222 /*
2223 * 1 - Rx ring done interrupt.
2224 */
2225 if (rt2x00_get_field32(reg, INT_SOURCE_CSR_RXDONE))
2226 rt2x00pci_rxdone(rt2x00dev);
2227
2228 /*
2229 * 2 - Tx ring done interrupt.
2230 */
2231 if (rt2x00_get_field32(reg, INT_SOURCE_CSR_TXDONE))
2232 rt61pci_txdone(rt2x00dev);
2233
2234 /*
2235 * 3 - Handle MCU command done.
2236 */
2237 if (reg_mcu)
2238 rt2x00pci_register_write(rt2x00dev,
2239 M2H_CMD_DONE_CSR, 0xffffffff);
2240
9e189446
GW		 2241 /*
2242 * 4 - MCU Autowakeup interrupt.
2243 */
2244 if (rt2x00_get_field32(reg_mcu, MCU_INT_SOURCE_CSR_TWAKEUP))
2245 rt61pci_wakeup(rt2x00dev);
2246
fa43750f
HS		 2247 /*
2248 * 5 - Beacon done interrupt.
2249 */
2250 if (rt2x00_get_field32(reg, INT_SOURCE_CSR_BEACON_DONE))
2251 rt2x00lib_beacondone(rt2x00dev);
2252
78e256c9
HS		 2253 /* Enable interrupts again. */
2254 rt2x00dev->ops->lib->set_device_state(rt2x00dev,
2255 STATE_RADIO_IRQ_ON_ISR);
95ea3627
ID		 2256 return IRQ_HANDLED;
2257}
2258
78e256c9
HS		 2259
2260static irqreturn_t rt61pci_interrupt(int irq, void *dev_instance)
2261{
2262 struct rt2x00_dev *rt2x00dev = dev_instance;
2263 u32 reg_mcu;
2264 u32 reg;
2265
2266 /*
2267 * Get the interrupt sources & saved to local variable.
2268 * Write register value back to clear pending interrupts.
2269 */
2270 rt2x00pci_register_read(rt2x00dev, MCU_INT_SOURCE_CSR, &reg_mcu);
2271 rt2x00pci_register_write(rt2x00dev, MCU_INT_SOURCE_CSR, reg_mcu);
2272
2273 rt2x00pci_register_read(rt2x00dev, INT_SOURCE_CSR, &reg);
2274 rt2x00pci_register_write(rt2x00dev, INT_SOURCE_CSR, reg);
2275
2276 if (!reg && !reg_mcu)
2277 return IRQ_NONE;
2278
2279 if (!test_bit(DEVICE_STATE_ENABLED_RADIO, &rt2x00dev->flags))
2280 return IRQ_HANDLED;
2281
2282 /* Store irqvalues for use in the interrupt thread. */
2283 rt2x00dev->irqvalue[0] = reg;
2284 rt2x00dev->irqvalue[1] = reg_mcu;
2285
2286 /* Disable interrupts, will be enabled again in the interrupt thread. */
2287 rt2x00dev->ops->lib->set_device_state(rt2x00dev,
2288 STATE_RADIO_IRQ_OFF_ISR);
2289 return IRQ_WAKE_THREAD;
2290}
2291
95ea3627
ID		 2292/*
2293 * Device probe functions.
2294 */
2295static int rt61pci_validate_eeprom(struct rt2x00_dev *rt2x00dev)
2296{
2297 struct eeprom_93cx6 eeprom;
2298 u32 reg;
2299 u16 word;
2300 u8 *mac;
2301 s8 value;
2302
2303 rt2x00pci_register_read(rt2x00dev, E2PROM_CSR, &reg);
2304
2305 eeprom.data = rt2x00dev;
2306 eeprom.register_read = rt61pci_eepromregister_read;
2307 eeprom.register_write = rt61pci_eepromregister_write;
2308 eeprom.width = rt2x00_get_field32(reg, E2PROM_CSR_TYPE_93C46) ?
2309 PCI_EEPROM_WIDTH_93C46 : PCI_EEPROM_WIDTH_93C66;
2310 eeprom.reg_data_in = 0;
2311 eeprom.reg_data_out = 0;
2312 eeprom.reg_data_clock = 0;
2313 eeprom.reg_chip_select = 0;
2314
2315 eeprom_93cx6_multiread(&eeprom, EEPROM_BASE, rt2x00dev->eeprom,
2316 EEPROM_SIZE / sizeof(u16));
2317
2318 /*
2319 * Start validation of the data that has been read.
2320 */
2321 mac = rt2x00_eeprom_addr(rt2x00dev, EEPROM_MAC_ADDR_0);
2322 if (!is_valid_ether_addr(mac)) {
2323 random_ether_addr(mac);
e174961c 2324 EEPROM(rt2x00dev, "MAC: %pM\n", mac);
95ea3627
ID		 2325 }
2326
2327 rt2x00_eeprom_read(rt2x00dev, EEPROM_ANTENNA, &word);
2328 if (word == 0xffff) {
2329 rt2x00_set_field16(&word, EEPROM_ANTENNA_NUM, 2);
362f3b6b
ID		 2330 rt2x00_set_field16(&word, EEPROM_ANTENNA_TX_DEFAULT,
2331 ANTENNA_B);
2332 rt2x00_set_field16(&word, EEPROM_ANTENNA_RX_DEFAULT,
2333 ANTENNA_B);
95ea3627
ID		 2334 rt2x00_set_field16(&word, EEPROM_ANTENNA_FRAME_TYPE, 0);
2335 rt2x00_set_field16(&word, EEPROM_ANTENNA_DYN_TXAGC, 0);
2336 rt2x00_set_field16(&word, EEPROM_ANTENNA_HARDWARE_RADIO, 0);
2337 rt2x00_set_field16(&word, EEPROM_ANTENNA_RF_TYPE, RF5225);
2338 rt2x00_eeprom_write(rt2x00dev, EEPROM_ANTENNA, word);
2339 EEPROM(rt2x00dev, "Antenna: 0x%04x\n", word);
2340 }
2341
2342 rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC, &word);
2343 if (word == 0xffff) {
2344 rt2x00_set_field16(&word, EEPROM_NIC_ENABLE_DIVERSITY, 0);
2345 rt2x00_set_field16(&word, EEPROM_NIC_TX_DIVERSITY, 0);
91581b62
ID		 2346 rt2x00_set_field16(&word, EEPROM_NIC_RX_FIXED, 0);
2347 rt2x00_set_field16(&word, EEPROM_NIC_TX_FIXED, 0);
95ea3627
ID		 2348 rt2x00_set_field16(&word, EEPROM_NIC_EXTERNAL_LNA_BG, 0);
2349 rt2x00_set_field16(&word, EEPROM_NIC_CARDBUS_ACCEL, 0);
2350 rt2x00_set_field16(&word, EEPROM_NIC_EXTERNAL_LNA_A, 0);
2351 rt2x00_eeprom_write(rt2x00dev, EEPROM_NIC, word);
2352 EEPROM(rt2x00dev, "NIC: 0x%04x\n", word);
2353 }
2354
2355 rt2x00_eeprom_read(rt2x00dev, EEPROM_LED, &word);
2356 if (word == 0xffff) {
2357 rt2x00_set_field16(&word, EEPROM_LED_LED_MODE,
2358 LED_MODE_DEFAULT);
2359 rt2x00_eeprom_write(rt2x00dev, EEPROM_LED, word);
2360 EEPROM(rt2x00dev, "Led: 0x%04x\n", word);
2361 }
2362
2363 rt2x00_eeprom_read(rt2x00dev, EEPROM_FREQ, &word);
2364 if (word == 0xffff) {
2365 rt2x00_set_field16(&word, EEPROM_FREQ_OFFSET, 0);
2366 rt2x00_set_field16(&word, EEPROM_FREQ_SEQ, 0);
2367 rt2x00_eeprom_write(rt2x00dev, EEPROM_FREQ, word);
2368 EEPROM(rt2x00dev, "Freq: 0x%04x\n", word);
2369 }
2370
2371 rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_OFFSET_BG, &word);
2372 if (word == 0xffff) {
2373 rt2x00_set_field16(&word, EEPROM_RSSI_OFFSET_BG_1, 0);
2374 rt2x00_set_field16(&word, EEPROM_RSSI_OFFSET_BG_2, 0);
2375 rt2x00_eeprom_write(rt2x00dev, EEPROM_RSSI_OFFSET_BG, word);
2376 EEPROM(rt2x00dev, "RSSI OFFSET BG: 0x%04x\n", word);
2377 } else {
2378 value = rt2x00_get_field16(word, EEPROM_RSSI_OFFSET_BG_1);
2379 if (value < -10 || value > 10)
2380 rt2x00_set_field16(&word, EEPROM_RSSI_OFFSET_BG_1, 0);
2381 value = rt2x00_get_field16(word, EEPROM_RSSI_OFFSET_BG_2);
2382 if (value < -10 || value > 10)
2383 rt2x00_set_field16(&word, EEPROM_RSSI_OFFSET_BG_2, 0);
2384 rt2x00_eeprom_write(rt2x00dev, EEPROM_RSSI_OFFSET_BG, word);
2385 }
2386
2387 rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_OFFSET_A, &word);
2388 if (word == 0xffff) {
2389 rt2x00_set_field16(&word, EEPROM_RSSI_OFFSET_A_1, 0);
2390 rt2x00_set_field16(&word, EEPROM_RSSI_OFFSET_A_2, 0);
2391 rt2x00_eeprom_write(rt2x00dev, EEPROM_RSSI_OFFSET_A, word);
417f412f 2392 EEPROM(rt2x00dev, "RSSI OFFSET A: 0x%04x\n", word);
95ea3627
ID		 2393 } else {
2394 value = rt2x00_get_field16(word, EEPROM_RSSI_OFFSET_A_1);
2395 if (value < -10 || value > 10)
2396 rt2x00_set_field16(&word, EEPROM_RSSI_OFFSET_A_1, 0);
2397 value = rt2x00_get_field16(word, EEPROM_RSSI_OFFSET_A_2);
2398 if (value < -10 || value > 10)
2399 rt2x00_set_field16(&word, EEPROM_RSSI_OFFSET_A_2, 0);
2400 rt2x00_eeprom_write(rt2x00dev, EEPROM_RSSI_OFFSET_A, word);
2401 }
2402
2403 return 0;
2404}
2405
2406static int rt61pci_init_eeprom(struct rt2x00_dev *rt2x00dev)
2407{
2408 u32 reg;
2409 u16 value;
2410 u16 eeprom;
95ea3627
ID		 2411
2412 /*
2413 * Read EEPROM word for configuration.
2414 */
2415 rt2x00_eeprom_read(rt2x00dev, EEPROM_ANTENNA, &eeprom);
2416
2417 /*
2418 * Identify RF chipset.
95ea3627 2419 */
95ea3627
ID		 2420 value = rt2x00_get_field16(eeprom, EEPROM_ANTENNA_RF_TYPE);
2421 rt2x00pci_register_read(rt2x00dev, MAC_CSR0, &reg);
49e721ec
GW		 2422 rt2x00_set_chip(rt2x00dev, rt2x00_get_field32(reg, MAC_CSR0_CHIPSET),
2423 value, rt2x00_get_field32(reg, MAC_CSR0_REVISION));
95ea3627 2424
5122d898
GW		 2425 if (!rt2x00_rf(rt2x00dev, RF5225) &&
2426 !rt2x00_rf(rt2x00dev, RF5325) &&
2427 !rt2x00_rf(rt2x00dev, RF2527) &&
2428 !rt2x00_rf(rt2x00dev, RF2529)) {
95ea3627
ID		 2429 ERROR(rt2x00dev, "Invalid RF chipset detected.\n");
2430 return -ENODEV;
2431 }
2432
e4cd2ff8 2433 /*
49513481 2434 * Determine number of antennas.
e4cd2ff8
ID		 2435 */
2436 if (rt2x00_get_field16(eeprom, EEPROM_ANTENNA_NUM) == 2)
2437 __set_bit(CONFIG_DOUBLE_ANTENNA, &rt2x00dev->flags);
2438
95ea3627
ID		 2439 /*
2440 * Identify default antenna configuration.
2441 */
addc81bd 2442 rt2x00dev->default_ant.tx =
95ea3627 2443 rt2x00_get_field16(eeprom, EEPROM_ANTENNA_TX_DEFAULT);
addc81bd 2444 rt2x00dev->default_ant.rx =
95ea3627
ID		 2445 rt2x00_get_field16(eeprom, EEPROM_ANTENNA_RX_DEFAULT);
2446
2447 /*
2448 * Read the Frame type.
2449 */
2450 if (rt2x00_get_field16(eeprom, EEPROM_ANTENNA_FRAME_TYPE))
2451 __set_bit(CONFIG_FRAME_TYPE, &rt2x00dev->flags);
2452
95ea3627 2453 /*
b34e620f 2454 * Detect if this device has a hardware controlled radio.
95ea3627
ID		 2455 */
2456 if (rt2x00_get_field16(eeprom, EEPROM_ANTENNA_HARDWARE_RADIO))
066cb637 2457 __set_bit(CONFIG_SUPPORT_HW_BUTTON, &rt2x00dev->flags);
95ea3627
ID		 2458
2459 /*
2460 * Read frequency offset and RF programming sequence.
2461 */
2462 rt2x00_eeprom_read(rt2x00dev, EEPROM_FREQ, &eeprom);
2463 if (rt2x00_get_field16(eeprom, EEPROM_FREQ_SEQ))
2464 __set_bit(CONFIG_RF_SEQUENCE, &rt2x00dev->flags);
2465
2466 rt2x00dev->freq_offset = rt2x00_get_field16(eeprom, EEPROM_FREQ_OFFSET);
2467
2468 /*
2469 * Read external LNA informations.
2470 */
2471 rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC, &eeprom);
2472
2473 if (rt2x00_get_field16(eeprom, EEPROM_NIC_EXTERNAL_LNA_A))
2474 __set_bit(CONFIG_EXTERNAL_LNA_A, &rt2x00dev->flags);
2475 if (rt2x00_get_field16(eeprom, EEPROM_NIC_EXTERNAL_LNA_BG))
2476 __set_bit(CONFIG_EXTERNAL_LNA_BG, &rt2x00dev->flags);
2477
e4cd2ff8 2478 /*
b34e620f 2479 * When working with a RF2529 chip without double antenna,
e4cd2ff8
ID		 2480 * the antenna settings should be gathered from the NIC
2481 * eeprom word.
2482 */
5122d898 2483 if (rt2x00_rf(rt2x00dev, RF2529) &&
e4cd2ff8 2484 !test_bit(CONFIG_DOUBLE_ANTENNA, &rt2x00dev->flags)) {
91581b62
ID		 2485 rt2x00dev->default_ant.rx =
2486 ANTENNA_A + rt2x00_get_field16(eeprom, EEPROM_NIC_RX_FIXED);
2487 rt2x00dev->default_ant.tx =
2488 ANTENNA_B - rt2x00_get_field16(eeprom, EEPROM_NIC_TX_FIXED);
e4cd2ff8
ID		 2489
2490 if (rt2x00_get_field16(eeprom, EEPROM_NIC_TX_DIVERSITY))
2491 rt2x00dev->default_ant.tx = ANTENNA_SW_DIVERSITY;
2492 if (rt2x00_get_field16(eeprom, EEPROM_NIC_ENABLE_DIVERSITY))
2493 rt2x00dev->default_ant.rx = ANTENNA_SW_DIVERSITY;
2494 }
2495
95ea3627
ID		 2496 /*
2497 * Store led settings, for correct led behaviour.
2498 * If the eeprom value is invalid,
2499 * switch to default led mode.
2500 */
771fd565 2501#ifdef CONFIG_RT2X00_LIB_LEDS
95ea3627 2502 rt2x00_eeprom_read(rt2x00dev, EEPROM_LED, &eeprom);
a9450b70
ID		 2503 value = rt2x00_get_field16(eeprom, EEPROM_LED_LED_MODE);
2504
475433be
ID		 2505 rt61pci_init_led(rt2x00dev, &rt2x00dev->led_radio, LED_TYPE_RADIO);
2506 rt61pci_init_led(rt2x00dev, &rt2x00dev->led_assoc, LED_TYPE_ASSOC);
2507 if (value == LED_MODE_SIGNAL_STRENGTH)
2508 rt61pci_init_led(rt2x00dev, &rt2x00dev->led_qual,
2509 LED_TYPE_QUALITY);
95ea3627 2510
a9450b70
ID		 2511 rt2x00_set_field16(&rt2x00dev->led_mcu_reg, MCU_LEDCS_LED_MODE, value);
2512 rt2x00_set_field16(&rt2x00dev->led_mcu_reg, MCU_LEDCS_POLARITY_GPIO_0,
95ea3627
ID		 2513 rt2x00_get_field16(eeprom,
2514 EEPROM_LED_POLARITY_GPIO_0));
a9450b70 2515 rt2x00_set_field16(&rt2x00dev->led_mcu_reg, MCU_LEDCS_POLARITY_GPIO_1,
95ea3627
ID		 2516 rt2x00_get_field16(eeprom,
2517 EEPROM_LED_POLARITY_GPIO_1));
a9450b70 2518 rt2x00_set_field16(&rt2x00dev->led_mcu_reg, MCU_LEDCS_POLARITY_GPIO_2,
95ea3627
ID		 2519 rt2x00_get_field16(eeprom,
2520 EEPROM_LED_POLARITY_GPIO_2));
a9450b70 2521 rt2x00_set_field16(&rt2x00dev->led_mcu_reg, MCU_LEDCS_POLARITY_GPIO_3,
95ea3627
ID		 2522 rt2x00_get_field16(eeprom,
2523 EEPROM_LED_POLARITY_GPIO_3));
a9450b70 2524 rt2x00_set_field16(&rt2x00dev->led_mcu_reg, MCU_LEDCS_POLARITY_GPIO_4,
95ea3627
ID		 2525 rt2x00_get_field16(eeprom,
2526 EEPROM_LED_POLARITY_GPIO_4));
a9450b70 2527 rt2x00_set_field16(&rt2x00dev->led_mcu_reg, MCU_LEDCS_POLARITY_ACT,
95ea3627 2528 rt2x00_get_field16(eeprom, EEPROM_LED_POLARITY_ACT));
a9450b70 2529 rt2x00_set_field16(&rt2x00dev->led_mcu_reg, MCU_LEDCS_POLARITY_READY_BG,
95ea3627
ID		 2530 rt2x00_get_field16(eeprom,
2531 EEPROM_LED_POLARITY_RDY_G));
a9450b70 2532 rt2x00_set_field16(&rt2x00dev->led_mcu_reg, MCU_LEDCS_POLARITY_READY_A,
95ea3627
ID		 2533 rt2x00_get_field16(eeprom,
2534 EEPROM_LED_POLARITY_RDY_A));
771fd565 2535#endif /* CONFIG_RT2X00_LIB_LEDS */
95ea3627
ID		 2536
2537 return 0;
2538}
2539
2540/*
2541 * RF value list for RF5225 & RF5325
2542 * Supports: 2.4 GHz & 5.2 GHz, rf_sequence disabled
2543 */
2544static const struct rf_channel rf_vals_noseq[] = {
2545 { 1, 0x00002ccc, 0x00004786, 0x00068455, 0x000ffa0b },
2546 { 2, 0x00002ccc, 0x00004786, 0x00068455, 0x000ffa1f },
2547 { 3, 0x00002ccc, 0x0000478a, 0x00068455, 0x000ffa0b },
2548 { 4, 0x00002ccc, 0x0000478a, 0x00068455, 0x000ffa1f },
2549 { 5, 0x00002ccc, 0x0000478e, 0x00068455, 0x000ffa0b },
2550 { 6, 0x00002ccc, 0x0000478e, 0x00068455, 0x000ffa1f },
2551 { 7, 0x00002ccc, 0x00004792, 0x00068455, 0x000ffa0b },
2552 { 8, 0x00002ccc, 0x00004792, 0x00068455, 0x000ffa1f },
2553 { 9, 0x00002ccc, 0x00004796, 0x00068455, 0x000ffa0b },
2554 { 10, 0x00002ccc, 0x00004796, 0x00068455, 0x000ffa1f },
2555 { 11, 0x00002ccc, 0x0000479a, 0x00068455, 0x000ffa0b },
2556 { 12, 0x00002ccc, 0x0000479a, 0x00068455, 0x000ffa1f },
2557 { 13, 0x00002ccc, 0x0000479e, 0x00068455, 0x000ffa0b },
2558 { 14, 0x00002ccc, 0x000047a2, 0x00068455, 0x000ffa13 },
2559
2560 /* 802.11 UNI / HyperLan 2 */
2561 { 36, 0x00002ccc, 0x0000499a, 0x0009be55, 0x000ffa23 },
2562 { 40, 0x00002ccc, 0x000049a2, 0x0009be55, 0x000ffa03 },
2563 { 44, 0x00002ccc, 0x000049a6, 0x0009be55, 0x000ffa0b },
2564 { 48, 0x00002ccc, 0x000049aa, 0x0009be55, 0x000ffa13 },
2565 { 52, 0x00002ccc, 0x000049ae, 0x0009ae55, 0x000ffa1b },
2566 { 56, 0x00002ccc, 0x000049b2, 0x0009ae55, 0x000ffa23 },
2567 { 60, 0x00002ccc, 0x000049ba, 0x0009ae55, 0x000ffa03 },
2568 { 64, 0x00002ccc, 0x000049be, 0x0009ae55, 0x000ffa0b },
2569
2570 /* 802.11 HyperLan 2 */
2571 { 100, 0x00002ccc, 0x00004a2a, 0x000bae55, 0x000ffa03 },
2572 { 104, 0x00002ccc, 0x00004a2e, 0x000bae55, 0x000ffa0b },
2573 { 108, 0x00002ccc, 0x00004a32, 0x000bae55, 0x000ffa13 },
2574 { 112, 0x00002ccc, 0x00004a36, 0x000bae55, 0x000ffa1b },
2575 { 116, 0x00002ccc, 0x00004a3a, 0x000bbe55, 0x000ffa23 },
2576 { 120, 0x00002ccc, 0x00004a82, 0x000bbe55, 0x000ffa03 },
2577 { 124, 0x00002ccc, 0x00004a86, 0x000bbe55, 0x000ffa0b },
2578 { 128, 0x00002ccc, 0x00004a8a, 0x000bbe55, 0x000ffa13 },
2579 { 132, 0x00002ccc, 0x00004a8e, 0x000bbe55, 0x000ffa1b },
2580 { 136, 0x00002ccc, 0x00004a92, 0x000bbe55, 0x000ffa23 },
2581
2582 /* 802.11 UNII */
2583 { 140, 0x00002ccc, 0x00004a9a, 0x000bbe55, 0x000ffa03 },
2584 { 149, 0x00002ccc, 0x00004aa2, 0x000bbe55, 0x000ffa1f },
2585 { 153, 0x00002ccc, 0x00004aa6, 0x000bbe55, 0x000ffa27 },
2586 { 157, 0x00002ccc, 0x00004aae, 0x000bbe55, 0x000ffa07 },
2587 { 161, 0x00002ccc, 0x00004ab2, 0x000bbe55, 0x000ffa0f },
2588 { 165, 0x00002ccc, 0x00004ab6, 0x000bbe55, 0x000ffa17 },
2589
2590 /* MMAC(Japan)J52 ch 34,38,42,46 */
2591 { 34, 0x00002ccc, 0x0000499a, 0x0009be55, 0x000ffa0b },
2592 { 38, 0x00002ccc, 0x0000499e, 0x0009be55, 0x000ffa13 },
2593 { 42, 0x00002ccc, 0x000049a2, 0x0009be55, 0x000ffa1b },
2594 { 46, 0x00002ccc, 0x000049a6, 0x0009be55, 0x000ffa23 },
2595};
2596
2597/*
2598 * RF value list for RF5225 & RF5325
2599 * Supports: 2.4 GHz & 5.2 GHz, rf_sequence enabled
2600 */
2601static const struct rf_channel rf_vals_seq[] = {
2602 { 1, 0x00002ccc, 0x00004786, 0x00068455, 0x000ffa0b },
2603 { 2, 0x00002ccc, 0x00004786, 0x00068455, 0x000ffa1f },
2604 { 3, 0x00002ccc, 0x0000478a, 0x00068455, 0x000ffa0b },
2605 { 4, 0x00002ccc, 0x0000478a, 0x00068455, 0x000ffa1f },
2606 { 5, 0x00002ccc, 0x0000478e, 0x00068455, 0x000ffa0b },
2607 { 6, 0x00002ccc, 0x0000478e, 0x00068455, 0x000ffa1f },
2608 { 7, 0x00002ccc, 0x00004792, 0x00068455, 0x000ffa0b },
2609 { 8, 0x00002ccc, 0x00004792, 0x00068455, 0x000ffa1f },
2610 { 9, 0x00002ccc, 0x00004796, 0x00068455, 0x000ffa0b },
2611 { 10, 0x00002ccc, 0x00004796, 0x00068455, 0x000ffa1f },
2612 { 11, 0x00002ccc, 0x0000479a, 0x00068455, 0x000ffa0b },
2613 { 12, 0x00002ccc, 0x0000479a, 0x00068455, 0x000ffa1f },
2614 { 13, 0x00002ccc, 0x0000479e, 0x00068455, 0x000ffa0b },
2615 { 14, 0x00002ccc, 0x000047a2, 0x00068455, 0x000ffa13 },
2616
2617 /* 802.11 UNI / HyperLan 2 */
2618 { 36, 0x00002cd4, 0x0004481a, 0x00098455, 0x000c0a03 },
2619 { 40, 0x00002cd0, 0x00044682, 0x00098455, 0x000c0a03 },
2620 { 44, 0x00002cd0, 0x00044686, 0x00098455, 0x000c0a1b },
2621 { 48, 0x00002cd0, 0x0004468e, 0x00098655, 0x000c0a0b },
2622 { 52, 0x00002cd0, 0x00044692, 0x00098855, 0x000c0a23 },
2623 { 56, 0x00002cd0, 0x0004469a, 0x00098c55, 0x000c0a13 },
2624 { 60, 0x00002cd0, 0x000446a2, 0x00098e55, 0x000c0a03 },
2625 { 64, 0x00002cd0, 0x000446a6, 0x00099255, 0x000c0a1b },
2626
2627 /* 802.11 HyperLan 2 */
2628 { 100, 0x00002cd4, 0x0004489a, 0x000b9855, 0x000c0a03 },
2629 { 104, 0x00002cd4, 0x000448a2, 0x000b9855, 0x000c0a03 },
2630 { 108, 0x00002cd4, 0x000448aa, 0x000b9855, 0x000c0a03 },
2631 { 112, 0x00002cd4, 0x000448b2, 0x000b9a55, 0x000c0a03 },
2632 { 116, 0x00002cd4, 0x000448ba, 0x000b9a55, 0x000c0a03 },
2633 { 120, 0x00002cd0, 0x00044702, 0x000b9a55, 0x000c0a03 },
2634 { 124, 0x00002cd0, 0x00044706, 0x000b9a55, 0x000c0a1b },
2635 { 128, 0x00002cd0, 0x0004470e, 0x000b9c55, 0x000c0a0b },
2636 { 132, 0x00002cd0, 0x00044712, 0x000b9c55, 0x000c0a23 },
2637 { 136, 0x00002cd0, 0x0004471a, 0x000b9e55, 0x000c0a13 },
2638
2639 /* 802.11 UNII */
2640 { 140, 0x00002cd0, 0x00044722, 0x000b9e55, 0x000c0a03 },
2641 { 149, 0x00002cd0, 0x0004472e, 0x000ba255, 0x000c0a1b },
2642 { 153, 0x00002cd0, 0x00044736, 0x000ba255, 0x000c0a0b },
2643 { 157, 0x00002cd4, 0x0004490a, 0x000ba255, 0x000c0a17 },
2644 { 161, 0x00002cd4, 0x00044912, 0x000ba255, 0x000c0a17 },
2645 { 165, 0x00002cd4, 0x0004491a, 0x000ba255, 0x000c0a17 },
2646
2647 /* MMAC(Japan)J52 ch 34,38,42,46 */
2648 { 34, 0x00002ccc, 0x0000499a, 0x0009be55, 0x000c0a0b },
2649 { 38, 0x00002ccc, 0x0000499e, 0x0009be55, 0x000c0a13 },
2650 { 42, 0x00002ccc, 0x000049a2, 0x0009be55, 0x000c0a1b },
2651 { 46, 0x00002ccc, 0x000049a6, 0x0009be55, 0x000c0a23 },
2652};
2653
8c5e7a5f 2654static int rt61pci_probe_hw_mode(struct rt2x00_dev *rt2x00dev)
95ea3627
ID		 2655{
2656 struct hw_mode_spec *spec = &rt2x00dev->spec;
8c5e7a5f
ID		 2657 struct channel_info *info;
2658 char *tx_power;
95ea3627
ID		 2659 unsigned int i;
2660
93b6bd26
GW		 2661 /*
2662 * Disable powersaving as default.
2663 */
2664 rt2x00dev->hw->wiphy->flags &= ~WIPHY_FLAG_PS_ON_BY_DEFAULT;
2665
95ea3627
ID		 2666 /*
2667 * Initialize all hw fields.
2668 */
2669 rt2x00dev->hw->flags =
566bfe5a 2670 IEEE80211_HW_HOST_BROADCAST_PS_BUFFERING |
4be8c387
JB		 2671 IEEE80211_HW_SIGNAL_DBM |
2672 IEEE80211_HW_SUPPORTS_PS |
2673 IEEE80211_HW_PS_NULLFUNC_STACK;
95ea3627 2674
14a3bf89 2675 SET_IEEE80211_DEV(rt2x00dev->hw, rt2x00dev->dev);
95ea3627
ID		 2676 SET_IEEE80211_PERM_ADDR(rt2x00dev->hw,
2677 rt2x00_eeprom_addr(rt2x00dev,
2678 EEPROM_MAC_ADDR_0));
2679
95ea3627 2680 /*
e1b4d7b7
ID		 2681 * As rt61 has a global fallback table we cannot specify
2682 * more then one tx rate per frame but since the hw will
2683 * try several rates (based on the fallback table) we should
ba3b9e5e 2684 * initialize max_report_rates to the maximum number of rates
e1b4d7b7
ID		 2685 * we are going to try. Otherwise mac80211 will truncate our
2686 * reported tx rates and the rc algortihm will end up with
2687 * incorrect data.
2688 */
ba3b9e5e
HS		 2689 rt2x00dev->hw->max_rates = 1;
2690 rt2x00dev->hw->max_report_rates = 7;
e1b4d7b7
ID		 2691 rt2x00dev->hw->max_rate_tries = 1;
2692
2693 /*
95ea3627
ID		 2694 * Initialize hw_mode information.
2695 */
31562e80
ID		 2696 spec->supported_bands = SUPPORT_BAND_2GHZ;
2697 spec->supported_rates = SUPPORT_RATE_CCK | SUPPORT_RATE_OFDM;
95ea3627
ID		 2698
2699 if (!test_bit(CONFIG_RF_SEQUENCE, &rt2x00dev->flags)) {
2700 spec->num_channels = 14;
2701 spec->channels = rf_vals_noseq;
2702 } else {
2703 spec->num_channels = 14;
2704 spec->channels = rf_vals_seq;
2705 }
2706
5122d898 2707 if (rt2x00_rf(rt2x00dev, RF5225) || rt2x00_rf(rt2x00dev, RF5325)) {
31562e80 2708 spec->supported_bands |= SUPPORT_BAND_5GHZ;
95ea3627 2709 spec->num_channels = ARRAY_SIZE(rf_vals_seq);
8c5e7a5f
ID		 2710 }
2711
2712 /*
2713 * Create channel information array
2714 */
baeb2ffa 2715 info = kcalloc(spec->num_channels, sizeof(*info), GFP_KERNEL);
8c5e7a5f
ID		 2716 if (!info)
2717 return -ENOMEM;
2718
2719 spec->channels_info = info;
95ea3627 2720
8c5e7a5f 2721 tx_power = rt2x00_eeprom_addr(rt2x00dev, EEPROM_TXPOWER_G_START);
8d1331b3
ID		 2722 for (i = 0; i < 14; i++) {
2723 info[i].max_power = MAX_TXPOWER;
2724 info[i].default_power1 = TXPOWER_FROM_DEV(tx_power[i]);
2725 }
95ea3627 2726
8c5e7a5f
ID		 2727 if (spec->num_channels > 14) {
2728 tx_power = rt2x00_eeprom_addr(rt2x00dev, EEPROM_TXPOWER_A_START);
8d1331b3
ID		 2729 for (i = 14; i < spec->num_channels; i++) {
2730 info[i].max_power = MAX_TXPOWER;
2731 info[i].default_power1 = TXPOWER_FROM_DEV(tx_power[i]);
2732 }
95ea3627 2733 }
8c5e7a5f
ID		 2734
2735 return 0;
95ea3627
ID		 2736}
2737
2738static int rt61pci_probe_hw(struct rt2x00_dev *rt2x00dev)
2739{
2740 int retval;
2741
117839bd
PR		 2742 /*
2743 * Disable power saving.
2744 */
2745 rt2x00pci_register_write(rt2x00dev, SOFT_RESET_CSR, 0x00000007);
2746
95ea3627
ID		 2747 /*
2748 * Allocate eeprom data.
2749 */
2750 retval = rt61pci_validate_eeprom(rt2x00dev);
2751 if (retval)
2752 return retval;
2753
2754 retval = rt61pci_init_eeprom(rt2x00dev);
2755 if (retval)
2756 return retval;
2757
2758 /*
2759 * Initialize hw specifications.
2760 */
8c5e7a5f
ID		 2761 retval = rt61pci_probe_hw_mode(rt2x00dev);
2762 if (retval)
2763 return retval;
95ea3627 2764
1afcfd54
IP		 2765 /*
2766 * This device has multiple filters for control frames,
2767 * but has no a separate filter for PS Poll frames.
2768 */
2769 __set_bit(DRIVER_SUPPORT_CONTROL_FILTERS, &rt2x00dev->flags);
2770
95ea3627 2771 /*
c4da0048 2772 * This device requires firmware and DMA mapped skbs.
95ea3627 2773 */
066cb637 2774 __set_bit(DRIVER_REQUIRE_FIRMWARE, &rt2x00dev->flags);
c4da0048 2775 __set_bit(DRIVER_REQUIRE_DMA, &rt2x00dev->flags);
008c4482
ID		 2776 if (!modparam_nohwcrypt)
2777 __set_bit(CONFIG_SUPPORT_HW_CRYPTO, &rt2x00dev->flags);
27df2a9c 2778 __set_bit(DRIVER_SUPPORT_LINK_TUNING, &rt2x00dev->flags);
95ea3627
ID		 2779
2780 /*
2781 * Set the rssi offset.
2782 */
2783 rt2x00dev->rssi_offset = DEFAULT_RSSI_OFFSET;
2784
2785 return 0;
2786}
2787
2788/*
2789 * IEEE80211 stack callback functions.
2790 */
2af0a570
ID		 2791static int rt61pci_conf_tx(struct ieee80211_hw *hw, u16 queue_idx,
2792 const struct ieee80211_tx_queue_params *params)
2793{
2794 struct rt2x00_dev *rt2x00dev = hw->priv;
2795 struct data_queue *queue;
2796 struct rt2x00_field32 field;
2797 int retval;
2798 u32 reg;
5e790023 2799 u32 offset;
2af0a570
ID		 2800
2801 /*
2802 * First pass the configuration through rt2x00lib, that will
2803 * update the queue settings and validate the input. After that
2804 * we are free to update the registers based on the value
2805 * in the queue parameter.
2806 */
2807 retval = rt2x00mac_conf_tx(hw, queue_idx, params);
2808 if (retval)
2809 return retval;
2810
5e790023
ID		 2811 /*
2812 * We only need to perform additional register initialization
b34e620f 2813 * for WMM queues.
5e790023
ID		 2814 */
2815 if (queue_idx >= 4)
2816 return 0;
2817
2af0a570
ID		 2818 queue = rt2x00queue_get_queue(rt2x00dev, queue_idx);
2819
2820 /* Update WMM TXOP register */
5e790023
ID		 2821 offset = AC_TXOP_CSR0 + (sizeof(u32) * (!!(queue_idx & 2)));
2822 field.bit_offset = (queue_idx & 1) * 16;
2823 field.bit_mask = 0xffff << field.bit_offset;
2824
2825 rt2x00pci_register_read(rt2x00dev, offset, &reg);
2826 rt2x00_set_field32(&reg, field, queue->txop);
2827 rt2x00pci_register_write(rt2x00dev, offset, reg);
2af0a570
ID		 2828
2829 /* Update WMM registers */
2830 field.bit_offset = queue_idx * 4;
2831 field.bit_mask = 0xf << field.bit_offset;
2832
2833 rt2x00pci_register_read(rt2x00dev, AIFSN_CSR, &reg);
2834 rt2x00_set_field32(&reg, field, queue->aifs);
2835 rt2x00pci_register_write(rt2x00dev, AIFSN_CSR, reg);
2836
2837 rt2x00pci_register_read(rt2x00dev, CWMIN_CSR, &reg);
2838 rt2x00_set_field32(&reg, field, queue->cw_min);
2839 rt2x00pci_register_write(rt2x00dev, CWMIN_CSR, reg);
2840
2841 rt2x00pci_register_read(rt2x00dev, CWMAX_CSR, &reg);
2842 rt2x00_set_field32(&reg, field, queue->cw_max);
2843 rt2x00pci_register_write(rt2x00dev, CWMAX_CSR, reg);
2844
2845 return 0;
2846}
2847
95ea3627
ID		 2848static u64 rt61pci_get_tsf(struct ieee80211_hw *hw)
2849{
2850 struct rt2x00_dev *rt2x00dev = hw->priv;
2851 u64 tsf;
2852 u32 reg;
2853
2854 rt2x00pci_register_read(rt2x00dev, TXRX_CSR13, &reg);
2855 tsf = (u64) rt2x00_get_field32(reg, TXRX_CSR13_HIGH_TSFTIMER) << 32;
2856 rt2x00pci_register_read(rt2x00dev, TXRX_CSR12, &reg);
2857 tsf |= rt2x00_get_field32(reg, TXRX_CSR12_LOW_TSFTIMER);
2858
2859 return tsf;
2860}
2861
95ea3627
ID		 2862static const struct ieee80211_ops rt61pci_mac80211_ops = {
2863 .tx = rt2x00mac_tx,
4150c572
JB		 2864 .start = rt2x00mac_start,
2865 .stop = rt2x00mac_stop,
95ea3627
ID		 2866 .add_interface = rt2x00mac_add_interface,
2867 .remove_interface = rt2x00mac_remove_interface,
2868 .config = rt2x00mac_config,
3a643d24 2869 .configure_filter = rt2x00mac_configure_filter,
61e754f4 2870 .set_key = rt2x00mac_set_key,
d8147f9d
ID		 2871 .sw_scan_start = rt2x00mac_sw_scan_start,
2872 .sw_scan_complete = rt2x00mac_sw_scan_complete,
95ea3627 2873 .get_stats = rt2x00mac_get_stats,
471b3efd 2874 .bss_info_changed = rt2x00mac_bss_info_changed,
2af0a570 2875 .conf_tx = rt61pci_conf_tx,
95ea3627 2876 .get_tsf = rt61pci_get_tsf,
e47a5cdd 2877 .rfkill_poll = rt2x00mac_rfkill_poll,
f44df18c 2878 .flush = rt2x00mac_flush,
95ea3627
ID		 2879};
2880
2881static const struct rt2x00lib_ops rt61pci_rt2x00_ops = {
2882 .irq_handler = rt61pci_interrupt,
78e256c9 2883 .irq_handler_thread = rt61pci_interrupt_thread,
95ea3627
ID		 2884 .probe_hw = rt61pci_probe_hw,
2885 .get_firmware_name = rt61pci_get_firmware_name,
0cbe0064 2886 .check_firmware = rt61pci_check_firmware,
95ea3627
ID		 2887 .load_firmware = rt61pci_load_firmware,
2888 .initialize = rt2x00pci_initialize,
2889 .uninitialize = rt2x00pci_uninitialize,
798b7adb
ID		 2890 .get_entry_state = rt61pci_get_entry_state,
2891 .clear_entry = rt61pci_clear_entry,
95ea3627 2892 .set_device_state = rt61pci_set_device_state,
95ea3627 2893 .rfkill_poll = rt61pci_rfkill_poll,
95ea3627
ID		 2894 .link_stats = rt61pci_link_stats,
2895 .reset_tuner = rt61pci_reset_tuner,
2896 .link_tuner = rt61pci_link_tuner,
dbba306f
ID		 2897 .start_queue = rt61pci_start_queue,
2898 .kick_queue = rt61pci_kick_queue,
2899 .stop_queue = rt61pci_stop_queue,
95ea3627 2900 .write_tx_desc = rt61pci_write_tx_desc,
bd88a781 2901 .write_beacon = rt61pci_write_beacon,
95ea3627 2902 .fill_rxdone = rt61pci_fill_rxdone,
61e754f4
ID		 2903 .config_shared_key = rt61pci_config_shared_key,
2904 .config_pairwise_key = rt61pci_config_pairwise_key,
3a643d24 2905 .config_filter = rt61pci_config_filter,
6bb40dd1 2906 .config_intf = rt61pci_config_intf,
72810379 2907 .config_erp = rt61pci_config_erp,
e4ea1c40 2908 .config_ant = rt61pci_config_ant,
95ea3627
ID		 2909 .config = rt61pci_config,
2910};
2911
181d6902 2912static const struct data_queue_desc rt61pci_queue_rx = {
efd2f271 2913 .entry_num = 32,
181d6902
ID		 2914 .data_size = DATA_FRAME_SIZE,
2915 .desc_size = RXD_DESC_SIZE,
b8be63ff 2916 .priv_size = sizeof(struct queue_entry_priv_pci),
181d6902
ID		 2917};
2918
2919static const struct data_queue_desc rt61pci_queue_tx = {
efd2f271 2920 .entry_num = 32,
181d6902
ID		 2921 .data_size = DATA_FRAME_SIZE,
2922 .desc_size = TXD_DESC_SIZE,
b8be63ff 2923 .priv_size = sizeof(struct queue_entry_priv_pci),
181d6902
ID		 2924};
2925
2926static const struct data_queue_desc rt61pci_queue_bcn = {
efd2f271 2927 .entry_num = 4,
78720897 2928 .data_size = 0, /* No DMA required for beacons */
181d6902 2929 .desc_size = TXINFO_SIZE,
b8be63ff 2930 .priv_size = sizeof(struct queue_entry_priv_pci),
181d6902
ID		 2931};
2932
95ea3627 2933static const struct rt2x00_ops rt61pci_ops = {
04d0362e
GW		 2934 .name = KBUILD_MODNAME,
2935 .max_sta_intf = 1,
2936 .max_ap_intf = 4,
2937 .eeprom_size = EEPROM_SIZE,
2938 .rf_size = RF_SIZE,
2939 .tx_queues = NUM_TX_QUEUES,
e6218cc4 2940 .extra_tx_headroom = 0,
04d0362e
GW		 2941 .rx = &rt61pci_queue_rx,
2942 .tx = &rt61pci_queue_tx,
2943 .bcn = &rt61pci_queue_bcn,
2944 .lib = &rt61pci_rt2x00_ops,
2945 .hw = &rt61pci_mac80211_ops,
95ea3627 2946#ifdef CONFIG_RT2X00_LIB_DEBUGFS
04d0362e 2947 .debugfs = &rt61pci_rt2x00debug,
95ea3627
ID		 2948#endif /* CONFIG_RT2X00_LIB_DEBUGFS */
2949};
2950
2951/*
2952 * RT61pci module information.
2953 */
a3aa1884 2954static DEFINE_PCI_DEVICE_TABLE(rt61pci_device_table) = {
95ea3627
ID		 2955 /* RT2561s */
2956 { PCI_DEVICE(0x1814, 0x0301), PCI_DEVICE_DATA(&rt61pci_ops) },
2957 /* RT2561 v2 */
2958 { PCI_DEVICE(0x1814, 0x0302), PCI_DEVICE_DATA(&rt61pci_ops) },
2959 /* RT2661 */
2960 { PCI_DEVICE(0x1814, 0x0401), PCI_DEVICE_DATA(&rt61pci_ops) },
2961 { 0, }
2962};
2963
2964MODULE_AUTHOR(DRV_PROJECT);
2965MODULE_VERSION(DRV_VERSION);
2966MODULE_DESCRIPTION("Ralink RT61 PCI & PCMCIA Wireless LAN driver.");
2967MODULE_SUPPORTED_DEVICE("Ralink RT2561, RT2561s & RT2661 "
2968 "PCI & PCMCIA chipset based cards");
2969MODULE_DEVICE_TABLE(pci, rt61pci_device_table);
2970MODULE_FIRMWARE(FIRMWARE_RT2561);
2971MODULE_FIRMWARE(FIRMWARE_RT2561s);
2972MODULE_FIRMWARE(FIRMWARE_RT2661);
2973MODULE_LICENSE("GPL");
2974
2975static struct pci_driver rt61pci_driver = {
2360157c 2976 .name = KBUILD_MODNAME,
95ea3627
ID		 2977 .id_table = rt61pci_device_table,
2978 .probe = rt2x00pci_probe,
2979 .remove = __devexit_p(rt2x00pci_remove),
2980 .suspend = rt2x00pci_suspend,
2981 .resume = rt2x00pci_resume,
2982};
2983
2984static int __init rt61pci_init(void)
2985{
2986 return pci_register_driver(&rt61pci_driver);
2987}
2988
2989static void __exit rt61pci_exit(void)
2990{
2991 pci_unregister_driver(&rt61pci_driver);
2992}
2993
2994module_init(rt61pci_init);
2995module_exit(rt61pci_exit);
Linux kernel - Deliverables
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