projects / deliverable / linux.git / blame
| Commit | Line | Data |
|---|---|---|
| 95ea3627 | 1 | /* |
| 9c9a0d14 | 2 | Copyright (C) 2004 - 2009 Ivo van Doorn <IvDoorn@gmail.com> |
| 95ea3627 ID |
3 | <http://rt2x00.serialmonkey.com> |
| 4 | ||
| 5 | This program is free software; you can redistribute it and/or modify | |
| 6 | it under the terms of the GNU General Public License as published by | |
| 7 | the Free Software Foundation; either version 2 of the License, or | |
| 8 | (at your option) any later version. | |
| 9 | ||
| 10 | This program is distributed in the hope that it will be useful, | |
| 11 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
| 12 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
| 13 | GNU General Public License for more details. | |
| 14 | ||
| 15 | You should have received a copy of the GNU General Public License | |
| 16 | along with this program; if not, write to the | |
| 17 | Free Software Foundation, Inc., | |
| 18 | 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. | |
| 19 | */ | |
| 20 | ||
| 21 | /* | |
| 22 | Module: rt61pci | |
| 23 | Abstract: Data structures and registers for the rt61pci module. | |
| 24 | Supported chipsets: RT2561, RT2561s, RT2661. | |
| 25 | */ | |
| 26 | ||
| 27 | #ifndef RT61PCI_H | |
| 28 | #define RT61PCI_H | |
| 29 | ||
| 49e721ec GW |
30 | /* |
| 31 | * RT chip PCI IDs. | |
| 32 | */ | |
| 33 | #define RT2561s_PCI_ID 0x0301 | |
| 34 | #define RT2561_PCI_ID 0x0302 | |
| 35 | #define RT2661_PCI_ID 0x0401 | |
| 36 | ||
| 95ea3627 ID |
37 | /* |
| 38 | * RF chip defines. | |
| 39 | */ | |
| 40 | #define RF5225 0x0001 | |
| 41 | #define RF5325 0x0002 | |
| 42 | #define RF2527 0x0003 | |
| 43 | #define RF2529 0x0004 | |
| 44 | ||
| 45 | /* | |
| 46 | * Signal information. | |
| af901ca1 | 47 | * Default offset is required for RSSI <-> dBm conversion. |
| 95ea3627 | 48 | */ |
| 95ea3627 ID |
49 | #define DEFAULT_RSSI_OFFSET 120 |
| 50 | ||
| 51 | /* | |
| 52 | * Register layout information. | |
| 53 | */ | |
| 54 | #define CSR_REG_BASE 0x3000 | |
| 55 | #define CSR_REG_SIZE 0x04b0 | |
| 56 | #define EEPROM_BASE 0x0000 | |
| 57 | #define EEPROM_SIZE 0x0100 | |
| 743b97ca | 58 | #define BBP_BASE 0x0000 |
| 95ea3627 | 59 | #define BBP_SIZE 0x0080 |
| 53bc647a ID |
60 | #define RF_BASE 0x0004 |
| 61 | #define RF_SIZE 0x0010 | |
| 95ea3627 | 62 | |
| 61448f88 GW |
63 | /* |
| 64 | * Number of TX queues. | |
| 65 | */ | |
| 66 | #define NUM_TX_QUEUES 4 | |
| 67 | ||
| 95ea3627 ID |
68 | /* |
| 69 | * PCI registers. | |
| 70 | */ | |
| 71 | ||
| 95ea3627 ID |
72 | /* |
| 73 | * HOST_CMD_CSR: For HOST to interrupt embedded processor | |
| 74 | */ | |
| 75 | #define HOST_CMD_CSR 0x0008 | |
| 76 | #define HOST_CMD_CSR_HOST_COMMAND FIELD32(0x0000007f) | |
| 77 | #define HOST_CMD_CSR_INTERRUPT_MCU FIELD32(0x00000080) | |
| 78 | ||
| 79 | /* | |
| 80 | * MCU_CNTL_CSR | |
| 81 | * SELECT_BANK: Select 8051 program bank. | |
| 82 | * RESET: Enable 8051 reset state. | |
| 83 | * READY: Ready state for 8051. | |
| 84 | */ | |
| 85 | #define MCU_CNTL_CSR 0x000c | |
| 86 | #define MCU_CNTL_CSR_SELECT_BANK FIELD32(0x00000001) | |
| 87 | #define MCU_CNTL_CSR_RESET FIELD32(0x00000002) | |
| 88 | #define MCU_CNTL_CSR_READY FIELD32(0x00000004) | |
| 89 | ||
| 90 | /* | |
| 91 | * SOFT_RESET_CSR | |
| 7d7f19cc | 92 | * FORCE_CLOCK_ON: Host force MAC clock ON |
| 95ea3627 ID |
93 | */ |
| 94 | #define SOFT_RESET_CSR 0x0010 | |
| 7d7f19cc | 95 | #define SOFT_RESET_CSR_FORCE_CLOCK_ON FIELD32(0x00000002) |
| 95ea3627 ID |
96 | |
| 97 | /* | |
| 98 | * MCU_INT_SOURCE_CSR: MCU interrupt source/mask register. | |
| 99 | */ | |
| 100 | #define MCU_INT_SOURCE_CSR 0x0014 | |
| 101 | #define MCU_INT_SOURCE_CSR_0 FIELD32(0x00000001) | |
| 102 | #define MCU_INT_SOURCE_CSR_1 FIELD32(0x00000002) | |
| 103 | #define MCU_INT_SOURCE_CSR_2 FIELD32(0x00000004) | |
| 104 | #define MCU_INT_SOURCE_CSR_3 FIELD32(0x00000008) | |
| 105 | #define MCU_INT_SOURCE_CSR_4 FIELD32(0x00000010) | |
| 106 | #define MCU_INT_SOURCE_CSR_5 FIELD32(0x00000020) | |
| 107 | #define MCU_INT_SOURCE_CSR_6 FIELD32(0x00000040) | |
| 108 | #define MCU_INT_SOURCE_CSR_7 FIELD32(0x00000080) | |
| 109 | #define MCU_INT_SOURCE_CSR_TWAKEUP FIELD32(0x00000100) | |
| 110 | #define MCU_INT_SOURCE_CSR_TBTT_EXPIRE FIELD32(0x00000200) | |
| 111 | ||
| 112 | /* | |
| 113 | * MCU_INT_MASK_CSR: MCU interrupt source/mask register. | |
| 114 | */ | |
| 115 | #define MCU_INT_MASK_CSR 0x0018 | |
| 116 | #define MCU_INT_MASK_CSR_0 FIELD32(0x00000001) | |
| 117 | #define MCU_INT_MASK_CSR_1 FIELD32(0x00000002) | |
| 118 | #define MCU_INT_MASK_CSR_2 FIELD32(0x00000004) | |
| 119 | #define MCU_INT_MASK_CSR_3 FIELD32(0x00000008) | |
| 120 | #define MCU_INT_MASK_CSR_4 FIELD32(0x00000010) | |
| 121 | #define MCU_INT_MASK_CSR_5 FIELD32(0x00000020) | |
| 122 | #define MCU_INT_MASK_CSR_6 FIELD32(0x00000040) | |
| 123 | #define MCU_INT_MASK_CSR_7 FIELD32(0x00000080) | |
| 124 | #define MCU_INT_MASK_CSR_TWAKEUP FIELD32(0x00000100) | |
| 125 | #define MCU_INT_MASK_CSR_TBTT_EXPIRE FIELD32(0x00000200) | |
| 126 | ||
| 127 | /* | |
| 128 | * PCI_USEC_CSR | |
| 129 | */ | |
| 130 | #define PCI_USEC_CSR 0x001c | |
| 131 | ||
| 132 | /* | |
| 133 | * Security key table memory. | |
| 134 | * 16 entries 32-byte for shared key table | |
| 135 | * 64 entries 32-byte for pairwise key table | |
| 136 | * 64 entries 8-byte for pairwise ta key table | |
| 137 | */ | |
| 138 | #define SHARED_KEY_TABLE_BASE 0x1000 | |
| 139 | #define PAIRWISE_KEY_TABLE_BASE 0x1200 | |
| 140 | #define PAIRWISE_TA_TABLE_BASE 0x1a00 | |
| 141 | ||
| 61e754f4 ID |
142 | #define SHARED_KEY_ENTRY(__idx) \ |
| 143 | ( SHARED_KEY_TABLE_BASE + \ | |
| 144 | ((__idx) * sizeof(struct hw_key_entry)) ) | |
| 145 | #define PAIRWISE_KEY_ENTRY(__idx) \ | |
| 146 | ( PAIRWISE_KEY_TABLE_BASE + \ | |
| 147 | ((__idx) * sizeof(struct hw_key_entry)) ) | |
| 148 | #define PAIRWISE_TA_ENTRY(__idx) \ | |
| 149 | ( PAIRWISE_TA_TABLE_BASE + \ | |
| 150 | ((__idx) * sizeof(struct hw_pairwise_ta_entry)) ) | |
| 151 | ||
| 95ea3627 ID |
152 | struct hw_key_entry { |
| 153 | u8 key[16]; | |
| 154 | u8 tx_mic[8]; | |
| 155 | u8 rx_mic[8]; | |
| ba2d3587 | 156 | } __packed; |
| 95ea3627 ID |
157 | |
| 158 | struct hw_pairwise_ta_entry { | |
| 159 | u8 address[6]; | |
| 61e754f4 ID |
160 | u8 cipher; |
| 161 | u8 reserved; | |
| ba2d3587 | 162 | } __packed; |
| 95ea3627 ID |
163 | |
| 164 | /* | |
| 165 | * Other on-chip shared memory space. | |
| 166 | */ | |
| 167 | #define HW_CIS_BASE 0x2000 | |
| 168 | #define HW_NULL_BASE 0x2b00 | |
| 169 | ||
| 170 | /* | |
| 171 | * Since NULL frame won't be that long (256 byte), | |
| 172 | * We steal 16 tail bytes to save debugging settings. | |
| 173 | */ | |
| 174 | #define HW_DEBUG_SETTING_BASE 0x2bf0 | |
| 175 | ||
| 176 | /* | |
| 177 | * On-chip BEACON frame space. | |
| 178 | */ | |
| 179 | #define HW_BEACON_BASE0 0x2c00 | |
| 180 | #define HW_BEACON_BASE1 0x2d00 | |
| 181 | #define HW_BEACON_BASE2 0x2e00 | |
| 182 | #define HW_BEACON_BASE3 0x2f00 | |
| 6bb40dd1 ID |
183 | |
| 184 | #define HW_BEACON_OFFSET(__index) \ | |
| 185 | ( HW_BEACON_BASE0 + (__index * 0x0100) ) | |
| 95ea3627 ID |
186 | |
| 187 | /* | |
| 188 | * HOST-MCU shared memory. | |
| 189 | */ | |
| 190 | ||
| 191 | /* | |
| 192 | * H2M_MAILBOX_CSR: Host-to-MCU Mailbox. | |
| 193 | */ | |
| 194 | #define H2M_MAILBOX_CSR 0x2100 | |
| 195 | #define H2M_MAILBOX_CSR_ARG0 FIELD32(0x000000ff) | |
| 196 | #define H2M_MAILBOX_CSR_ARG1 FIELD32(0x0000ff00) | |
| 197 | #define H2M_MAILBOX_CSR_CMD_TOKEN FIELD32(0x00ff0000) | |
| 198 | #define H2M_MAILBOX_CSR_OWNER FIELD32(0xff000000) | |
| 199 | ||
| 200 | /* | |
| 201 | * MCU_LEDCS: LED control for MCU Mailbox. | |
| 202 | */ | |
| 203 | #define MCU_LEDCS_LED_MODE FIELD16(0x001f) | |
| 204 | #define MCU_LEDCS_RADIO_STATUS FIELD16(0x0020) | |
| 205 | #define MCU_LEDCS_LINK_BG_STATUS FIELD16(0x0040) | |
| 206 | #define MCU_LEDCS_LINK_A_STATUS FIELD16(0x0080) | |
| 207 | #define MCU_LEDCS_POLARITY_GPIO_0 FIELD16(0x0100) | |
| 208 | #define MCU_LEDCS_POLARITY_GPIO_1 FIELD16(0x0200) | |
| 209 | #define MCU_LEDCS_POLARITY_GPIO_2 FIELD16(0x0400) | |
| 210 | #define MCU_LEDCS_POLARITY_GPIO_3 FIELD16(0x0800) | |
| 211 | #define MCU_LEDCS_POLARITY_GPIO_4 FIELD16(0x1000) | |
| 212 | #define MCU_LEDCS_POLARITY_ACT FIELD16(0x2000) | |
| 213 | #define MCU_LEDCS_POLARITY_READY_BG FIELD16(0x4000) | |
| 214 | #define MCU_LEDCS_POLARITY_READY_A FIELD16(0x8000) | |
| 215 | ||
| 216 | /* | |
| 217 | * M2H_CMD_DONE_CSR. | |
| 218 | */ | |
| 219 | #define M2H_CMD_DONE_CSR 0x2104 | |
| 220 | ||
| 221 | /* | |
| 222 | * MCU_TXOP_ARRAY_BASE. | |
| 223 | */ | |
| 224 | #define MCU_TXOP_ARRAY_BASE 0x2110 | |
| 225 | ||
| 226 | /* | |
| 227 | * MAC Control/Status Registers(CSR). | |
| 228 | * Some values are set in TU, whereas 1 TU == 1024 us. | |
| 229 | */ | |
| 230 | ||
| 231 | /* | |
| 232 | * MAC_CSR0: ASIC revision number. | |
| 233 | */ | |
| 234 | #define MAC_CSR0 0x3000 | |
| 49e721ec GW |
235 | #define MAC_CSR0_REVISION FIELD32(0x0000000f) |
| 236 | #define MAC_CSR0_CHIPSET FIELD32(0x000ffff0) | |
| 95ea3627 ID |
237 | |
| 238 | /* | |
| 239 | * MAC_CSR1: System control register. | |
| 240 | * SOFT_RESET: Software reset bit, 1: reset, 0: normal. | |
| 241 | * BBP_RESET: Hardware reset BBP. | |
| 242 | * HOST_READY: Host is ready after initialization, 1: ready. | |
| 243 | */ | |
| 244 | #define MAC_CSR1 0x3004 | |
| 245 | #define MAC_CSR1_SOFT_RESET FIELD32(0x00000001) | |
| 246 | #define MAC_CSR1_BBP_RESET FIELD32(0x00000002) | |
| 247 | #define MAC_CSR1_HOST_READY FIELD32(0x00000004) | |
| 248 | ||
| 249 | /* | |
| 250 | * MAC_CSR2: STA MAC register 0. | |
| 251 | */ | |
| 252 | #define MAC_CSR2 0x3008 | |
| 253 | #define MAC_CSR2_BYTE0 FIELD32(0x000000ff) | |
| 254 | #define MAC_CSR2_BYTE1 FIELD32(0x0000ff00) | |
| 255 | #define MAC_CSR2_BYTE2 FIELD32(0x00ff0000) | |
| 256 | #define MAC_CSR2_BYTE3 FIELD32(0xff000000) | |
| 257 | ||
| 258 | /* | |
| 259 | * MAC_CSR3: STA MAC register 1. | |
| 6bb40dd1 ID |
260 | * UNICAST_TO_ME_MASK: |
| 261 | * Used to mask off bits from byte 5 of the MAC address | |
| 262 | * to determine the UNICAST_TO_ME bit for RX frames. | |
| 263 | * The full mask is complemented by BSS_ID_MASK: | |
| 264 | * MASK = BSS_ID_MASK & UNICAST_TO_ME_MASK | |
| 95ea3627 ID |
265 | */ |
| 266 | #define MAC_CSR3 0x300c | |
| 267 | #define MAC_CSR3_BYTE4 FIELD32(0x000000ff) | |
| 268 | #define MAC_CSR3_BYTE5 FIELD32(0x0000ff00) | |
| 269 | #define MAC_CSR3_UNICAST_TO_ME_MASK FIELD32(0x00ff0000) | |
| 270 | ||
| 271 | /* | |
| 272 | * MAC_CSR4: BSSID register 0. | |
| 273 | */ | |
| 274 | #define MAC_CSR4 0x3010 | |
| 275 | #define MAC_CSR4_BYTE0 FIELD32(0x000000ff) | |
| 276 | #define MAC_CSR4_BYTE1 FIELD32(0x0000ff00) | |
| 277 | #define MAC_CSR4_BYTE2 FIELD32(0x00ff0000) | |
| 278 | #define MAC_CSR4_BYTE3 FIELD32(0xff000000) | |
| 279 | ||
| 280 | /* | |
| 281 | * MAC_CSR5: BSSID register 1. | |
| 6bb40dd1 ID |
282 | * BSS_ID_MASK: |
| 283 | * This mask is used to mask off bits 0 and 1 of byte 5 of the | |
| 284 | * BSSID. This will make sure that those bits will be ignored | |
| 285 | * when determining the MY_BSS of RX frames. | |
| 286 | * 0: 1-BSSID mode (BSS index = 0) | |
| 287 | * 1: 2-BSSID mode (BSS index: Byte5, bit 0) | |
| 288 | * 2: 2-BSSID mode (BSS index: byte5, bit 1) | |
| 289 | * 3: 4-BSSID mode (BSS index: byte5, bit 0 - 1) | |
| 95ea3627 ID |
290 | */ |
| 291 | #define MAC_CSR5 0x3014 | |
| 292 | #define MAC_CSR5_BYTE4 FIELD32(0x000000ff) | |
| 293 | #define MAC_CSR5_BYTE5 FIELD32(0x0000ff00) | |
| 294 | #define MAC_CSR5_BSS_ID_MASK FIELD32(0x00ff0000) | |
| 295 | ||
| 296 | /* | |
| 297 | * MAC_CSR6: Maximum frame length register. | |
| 298 | */ | |
| 299 | #define MAC_CSR6 0x3018 | |
| 300 | #define MAC_CSR6_MAX_FRAME_UNIT FIELD32(0x00000fff) | |
| 301 | ||
| 302 | /* | |
| 303 | * MAC_CSR7: Reserved | |
| 304 | */ | |
| 305 | #define MAC_CSR7 0x301c | |
| 306 | ||
| 307 | /* | |
| 308 | * MAC_CSR8: SIFS/EIFS register. | |
| 309 | * All units are in US. | |
| 310 | */ | |
| 311 | #define MAC_CSR8 0x3020 | |
| 312 | #define MAC_CSR8_SIFS FIELD32(0x000000ff) | |
| 313 | #define MAC_CSR8_SIFS_AFTER_RX_OFDM FIELD32(0x0000ff00) | |
| 314 | #define MAC_CSR8_EIFS FIELD32(0xffff0000) | |
| 315 | ||
| 316 | /* | |
| 317 | * MAC_CSR9: Back-Off control register. | |
| 318 | * SLOT_TIME: Slot time, default is 20us for 802.11BG. | |
| 319 | * CWMIN: Bit for Cwmin. default Cwmin is 31 (2^5 - 1). | |
| 320 | * CWMAX: Bit for Cwmax, default Cwmax is 1023 (2^10 - 1). | |
| 321 | * CW_SELECT: 1: CWmin/Cwmax select from register, 0:select from TxD. | |
| 322 | */ | |
| 323 | #define MAC_CSR9 0x3024 | |
| 324 | #define MAC_CSR9_SLOT_TIME FIELD32(0x000000ff) | |
| 325 | #define MAC_CSR9_CWMIN FIELD32(0x00000f00) | |
| 326 | #define MAC_CSR9_CWMAX FIELD32(0x0000f000) | |
| 327 | #define MAC_CSR9_CW_SELECT FIELD32(0x00010000) | |
| 328 | ||
| 329 | /* | |
| 330 | * MAC_CSR10: Power state configuration. | |
| 331 | */ | |
| 332 | #define MAC_CSR10 0x3028 | |
| 333 | ||
| 334 | /* | |
| 335 | * MAC_CSR11: Power saving transition time register. | |
| 336 | * DELAY_AFTER_TBCN: Delay after Tbcn expired in units of TU. | |
| 337 | * TBCN_BEFORE_WAKEUP: Number of beacon before wakeup. | |
| 338 | * WAKEUP_LATENCY: In unit of TU. | |
| 339 | */ | |
| 340 | #define MAC_CSR11 0x302c | |
| 341 | #define MAC_CSR11_DELAY_AFTER_TBCN FIELD32(0x000000ff) | |
| 342 | #define MAC_CSR11_TBCN_BEFORE_WAKEUP FIELD32(0x00007f00) | |
| 343 | #define MAC_CSR11_AUTOWAKE FIELD32(0x00008000) | |
| 344 | #define MAC_CSR11_WAKEUP_LATENCY FIELD32(0x000f0000) | |
| 345 | ||
| 346 | /* | |
| 347 | * MAC_CSR12: Manual power control / status register (merge CSR20 & PWRCSR1). | |
| 348 | * CURRENT_STATE: 0:sleep, 1:awake. | |
| 349 | * FORCE_WAKEUP: This has higher priority than PUT_TO_SLEEP. | |
| 350 | * BBP_CURRENT_STATE: 0: BBP sleep, 1: BBP awake. | |
| 351 | */ | |
| 352 | #define MAC_CSR12 0x3030 | |
| 353 | #define MAC_CSR12_CURRENT_STATE FIELD32(0x00000001) | |
| 354 | #define MAC_CSR12_PUT_TO_SLEEP FIELD32(0x00000002) | |
| 355 | #define MAC_CSR12_FORCE_WAKEUP FIELD32(0x00000004) | |
| 356 | #define MAC_CSR12_BBP_CURRENT_STATE FIELD32(0x00000008) | |
| 357 | ||
| 358 | /* | |
| 359 | * MAC_CSR13: GPIO. | |
| 99bdf51a GW |
360 | * MAC_CSR13_VALx: GPIO value |
| 361 | * MAC_CSR13_DIRx: GPIO direction: 0 = output; 1 = input | |
| 95ea3627 ID |
362 | */ |
| 363 | #define MAC_CSR13 0x3034 | |
| 99bdf51a GW |
364 | #define MAC_CSR13_VAL0 FIELD32(0x00000001) |
| 365 | #define MAC_CSR13_VAL1 FIELD32(0x00000002) | |
| 366 | #define MAC_CSR13_VAL2 FIELD32(0x00000004) | |
| 367 | #define MAC_CSR13_VAL3 FIELD32(0x00000008) | |
| 368 | #define MAC_CSR13_VAL4 FIELD32(0x00000010) | |
| 369 | #define MAC_CSR13_VAL5 FIELD32(0x00000020) | |
| 370 | #define MAC_CSR13_DIR0 FIELD32(0x00000100) | |
| 371 | #define MAC_CSR13_DIR1 FIELD32(0x00000200) | |
| 372 | #define MAC_CSR13_DIR2 FIELD32(0x00000400) | |
| 373 | #define MAC_CSR13_DIR3 FIELD32(0x00000800) | |
| 374 | #define MAC_CSR13_DIR4 FIELD32(0x00001000) | |
| 375 | #define MAC_CSR13_DIR5 FIELD32(0x00002000) | |
| 95ea3627 ID |
376 | |
| 377 | /* | |
| 378 | * MAC_CSR14: LED control register. | |
| 379 | * ON_PERIOD: On period, default 70ms. | |
| 380 | * OFF_PERIOD: Off period, default 30ms. | |
| 381 | * HW_LED: HW TX activity, 1: normal OFF, 0: normal ON. | |
| 382 | * SW_LED: s/w LED, 1: ON, 0: OFF. | |
| 383 | * HW_LED_POLARITY: 0: active low, 1: active high. | |
| 384 | */ | |
| 385 | #define MAC_CSR14 0x3038 | |
| 386 | #define MAC_CSR14_ON_PERIOD FIELD32(0x000000ff) | |
| 387 | #define MAC_CSR14_OFF_PERIOD FIELD32(0x0000ff00) | |
| 388 | #define MAC_CSR14_HW_LED FIELD32(0x00010000) | |
| 389 | #define MAC_CSR14_SW_LED FIELD32(0x00020000) | |
| 390 | #define MAC_CSR14_HW_LED_POLARITY FIELD32(0x00040000) | |
| 391 | #define MAC_CSR14_SW_LED2 FIELD32(0x00080000) | |
| 392 | ||
| 393 | /* | |
| 394 | * MAC_CSR15: NAV control. | |
| 395 | */ | |
| 396 | #define MAC_CSR15 0x303c | |
| 397 | ||
| 398 | /* | |
| 399 | * TXRX control registers. | |
| 400 | * Some values are set in TU, whereas 1 TU == 1024 us. | |
| 401 | */ | |
| 402 | ||
| 403 | /* | |
| 404 | * TXRX_CSR0: TX/RX configuration register. | |
| 405 | * TSF_OFFSET: Default is 24. | |
| 406 | * AUTO_TX_SEQ: 1: ASIC auto replace sequence nr in outgoing frame. | |
| 407 | * DISABLE_RX: Disable Rx engine. | |
| 408 | * DROP_CRC: Drop CRC error. | |
| 409 | * DROP_PHYSICAL: Drop physical error. | |
| 410 | * DROP_CONTROL: Drop control frame. | |
| 411 | * DROP_NOT_TO_ME: Drop not to me unicast frame. | |
| 412 | * DROP_TO_DS: Drop fram ToDs bit is true. | |
| 413 | * DROP_VERSION_ERROR: Drop version error frame. | |
| 414 | * DROP_MULTICAST: Drop multicast frames. | |
| 415 | * DROP_BORADCAST: Drop broadcast frames. | |
| 723fc7af | 416 | * DROP_ACK_CTS: Drop received ACK and CTS. |
| 95ea3627 ID |
417 | */ |
| 418 | #define TXRX_CSR0 0x3040 | |
| 419 | #define TXRX_CSR0_RX_ACK_TIMEOUT FIELD32(0x000001ff) | |
| 420 | #define TXRX_CSR0_TSF_OFFSET FIELD32(0x00007e00) | |
| 421 | #define TXRX_CSR0_AUTO_TX_SEQ FIELD32(0x00008000) | |
| 422 | #define TXRX_CSR0_DISABLE_RX FIELD32(0x00010000) | |
| 423 | #define TXRX_CSR0_DROP_CRC FIELD32(0x00020000) | |
| 424 | #define TXRX_CSR0_DROP_PHYSICAL FIELD32(0x00040000) | |
| 425 | #define TXRX_CSR0_DROP_CONTROL FIELD32(0x00080000) | |
| 426 | #define TXRX_CSR0_DROP_NOT_TO_ME FIELD32(0x00100000) | |
| 427 | #define TXRX_CSR0_DROP_TO_DS FIELD32(0x00200000) | |
| 428 | #define TXRX_CSR0_DROP_VERSION_ERROR FIELD32(0x00400000) | |
| 429 | #define TXRX_CSR0_DROP_MULTICAST FIELD32(0x00800000) | |
| e542239f | 430 | #define TXRX_CSR0_DROP_BROADCAST FIELD32(0x01000000) |
| 95ea3627 ID |
431 | #define TXRX_CSR0_DROP_ACK_CTS FIELD32(0x02000000) |
| 432 | #define TXRX_CSR0_TX_WITHOUT_WAITING FIELD32(0x04000000) | |
| 433 | ||
| 434 | /* | |
| 435 | * TXRX_CSR1 | |
| 436 | */ | |
| 437 | #define TXRX_CSR1 0x3044 | |
| 438 | #define TXRX_CSR1_BBP_ID0 FIELD32(0x0000007f) | |
| 439 | #define TXRX_CSR1_BBP_ID0_VALID FIELD32(0x00000080) | |
| 440 | #define TXRX_CSR1_BBP_ID1 FIELD32(0x00007f00) | |
| 441 | #define TXRX_CSR1_BBP_ID1_VALID FIELD32(0x00008000) | |
| 442 | #define TXRX_CSR1_BBP_ID2 FIELD32(0x007f0000) | |
| 443 | #define TXRX_CSR1_BBP_ID2_VALID FIELD32(0x00800000) | |
| 444 | #define TXRX_CSR1_BBP_ID3 FIELD32(0x7f000000) | |
| 445 | #define TXRX_CSR1_BBP_ID3_VALID FIELD32(0x80000000) | |
| 446 | ||
| 447 | /* | |
| 448 | * TXRX_CSR2 | |
| 449 | */ | |
| 450 | #define TXRX_CSR2 0x3048 | |
| 451 | #define TXRX_CSR2_BBP_ID0 FIELD32(0x0000007f) | |
| 452 | #define TXRX_CSR2_BBP_ID0_VALID FIELD32(0x00000080) | |
| 453 | #define TXRX_CSR2_BBP_ID1 FIELD32(0x00007f00) | |
| 454 | #define TXRX_CSR2_BBP_ID1_VALID FIELD32(0x00008000) | |
| 455 | #define TXRX_CSR2_BBP_ID2 FIELD32(0x007f0000) | |
| 456 | #define TXRX_CSR2_BBP_ID2_VALID FIELD32(0x00800000) | |
| 457 | #define TXRX_CSR2_BBP_ID3 FIELD32(0x7f000000) | |
| 458 | #define TXRX_CSR2_BBP_ID3_VALID FIELD32(0x80000000) | |
| 459 | ||
| 460 | /* | |
| 461 | * TXRX_CSR3 | |
| 462 | */ | |
| 463 | #define TXRX_CSR3 0x304c | |
| 464 | #define TXRX_CSR3_BBP_ID0 FIELD32(0x0000007f) | |
| 465 | #define TXRX_CSR3_BBP_ID0_VALID FIELD32(0x00000080) | |
| 466 | #define TXRX_CSR3_BBP_ID1 FIELD32(0x00007f00) | |
| 467 | #define TXRX_CSR3_BBP_ID1_VALID FIELD32(0x00008000) | |
| 468 | #define TXRX_CSR3_BBP_ID2 FIELD32(0x007f0000) | |
| 469 | #define TXRX_CSR3_BBP_ID2_VALID FIELD32(0x00800000) | |
| 470 | #define TXRX_CSR3_BBP_ID3 FIELD32(0x7f000000) | |
| 471 | #define TXRX_CSR3_BBP_ID3_VALID FIELD32(0x80000000) | |
| 472 | ||
| 473 | /* | |
| 474 | * TXRX_CSR4: Auto-Responder/Tx-retry register. | |
| 475 | * AUTORESPOND_PREAMBLE: 0:long, 1:short preamble. | |
| 476 | * OFDM_TX_RATE_DOWN: 1:enable. | |
| 477 | * OFDM_TX_RATE_STEP: 0:1-step, 1: 2-step, 2:3-step, 3:4-step. | |
| 478 | * OFDM_TX_FALLBACK_CCK: 0: Fallback to OFDM 6M only, 1: Fallback to CCK 1M,2M. | |
| 479 | */ | |
| 480 | #define TXRX_CSR4 0x3050 | |
| 481 | #define TXRX_CSR4_TX_ACK_TIMEOUT FIELD32(0x000000ff) | |
| 482 | #define TXRX_CSR4_CNTL_ACK_POLICY FIELD32(0x00000700) | |
| 483 | #define TXRX_CSR4_ACK_CTS_PSM FIELD32(0x00010000) | |
| 484 | #define TXRX_CSR4_AUTORESPOND_ENABLE FIELD32(0x00020000) | |
| 485 | #define TXRX_CSR4_AUTORESPOND_PREAMBLE FIELD32(0x00040000) | |
| 486 | #define TXRX_CSR4_OFDM_TX_RATE_DOWN FIELD32(0x00080000) | |
| 487 | #define TXRX_CSR4_OFDM_TX_RATE_STEP FIELD32(0x00300000) | |
| 488 | #define TXRX_CSR4_OFDM_TX_FALLBACK_CCK FIELD32(0x00400000) | |
| 489 | #define TXRX_CSR4_LONG_RETRY_LIMIT FIELD32(0x0f000000) | |
| 490 | #define TXRX_CSR4_SHORT_RETRY_LIMIT FIELD32(0xf0000000) | |
| 491 | ||
| 492 | /* | |
| 493 | * TXRX_CSR5 | |
| 494 | */ | |
| 495 | #define TXRX_CSR5 0x3054 | |
| 496 | ||
| 497 | /* | |
| 498 | * TXRX_CSR6: ACK/CTS payload consumed time | |
| 499 | */ | |
| 500 | #define TXRX_CSR6 0x3058 | |
| 501 | ||
| 502 | /* | |
| 503 | * TXRX_CSR7: OFDM ACK/CTS payload consumed time for 6/9/12/18 mbps. | |
| 504 | */ | |
| 505 | #define TXRX_CSR7 0x305c | |
| 506 | #define TXRX_CSR7_ACK_CTS_6MBS FIELD32(0x000000ff) | |
| 507 | #define TXRX_CSR7_ACK_CTS_9MBS FIELD32(0x0000ff00) | |
| 508 | #define TXRX_CSR7_ACK_CTS_12MBS FIELD32(0x00ff0000) | |
| 509 | #define TXRX_CSR7_ACK_CTS_18MBS FIELD32(0xff000000) | |
| 510 | ||
| 511 | /* | |
| 512 | * TXRX_CSR8: OFDM ACK/CTS payload consumed time for 24/36/48/54 mbps. | |
| 513 | */ | |
| 514 | #define TXRX_CSR8 0x3060 | |
| 515 | #define TXRX_CSR8_ACK_CTS_24MBS FIELD32(0x000000ff) | |
| 516 | #define TXRX_CSR8_ACK_CTS_36MBS FIELD32(0x0000ff00) | |
| 517 | #define TXRX_CSR8_ACK_CTS_48MBS FIELD32(0x00ff0000) | |
| 518 | #define TXRX_CSR8_ACK_CTS_54MBS FIELD32(0xff000000) | |
| 519 | ||
| 520 | /* | |
| 521 | * TXRX_CSR9: Synchronization control register. | |
| 522 | * BEACON_INTERVAL: In unit of 1/16 TU. | |
| 523 | * TSF_TICKING: Enable TSF auto counting. | |
| 524 | * TSF_SYNC: Tsf sync, 0: disable, 1: infra, 2: ad-hoc/master mode. | |
| 525 | * BEACON_GEN: Enable beacon generator. | |
| 526 | */ | |
| 527 | #define TXRX_CSR9 0x3064 | |
| 528 | #define TXRX_CSR9_BEACON_INTERVAL FIELD32(0x0000ffff) | |
| 529 | #define TXRX_CSR9_TSF_TICKING FIELD32(0x00010000) | |
| 530 | #define TXRX_CSR9_TSF_SYNC FIELD32(0x00060000) | |
| 531 | #define TXRX_CSR9_TBTT_ENABLE FIELD32(0x00080000) | |
| 532 | #define TXRX_CSR9_BEACON_GEN FIELD32(0x00100000) | |
| 533 | #define TXRX_CSR9_TIMESTAMP_COMPENSATE FIELD32(0xff000000) | |
| 534 | ||
| 535 | /* | |
| 536 | * TXRX_CSR10: BEACON alignment. | |
| 537 | */ | |
| 538 | #define TXRX_CSR10 0x3068 | |
| 539 | ||
| 540 | /* | |
| 541 | * TXRX_CSR11: AES mask. | |
| 542 | */ | |
| 543 | #define TXRX_CSR11 0x306c | |
| 544 | ||
| 545 | /* | |
| 546 | * TXRX_CSR12: TSF low 32. | |
| 547 | */ | |
| 548 | #define TXRX_CSR12 0x3070 | |
| 549 | #define TXRX_CSR12_LOW_TSFTIMER FIELD32(0xffffffff) | |
| 550 | ||
| 551 | /* | |
| 552 | * TXRX_CSR13: TSF high 32. | |
| 553 | */ | |
| 554 | #define TXRX_CSR13 0x3074 | |
| 555 | #define TXRX_CSR13_HIGH_TSFTIMER FIELD32(0xffffffff) | |
| 556 | ||
| 557 | /* | |
| 558 | * TXRX_CSR14: TBTT timer. | |
| 559 | */ | |
| 560 | #define TXRX_CSR14 0x3078 | |
| 561 | ||
| 562 | /* | |
| 563 | * TXRX_CSR15: TKIP MIC priority byte "AND" mask. | |
| 564 | */ | |
| 565 | #define TXRX_CSR15 0x307c | |
| 566 | ||
| 567 | /* | |
| 568 | * PHY control registers. | |
| 569 | * Some values are set in TU, whereas 1 TU == 1024 us. | |
| 570 | */ | |
| 571 | ||
| 572 | /* | |
| 573 | * PHY_CSR0: RF/PS control. | |
| 574 | */ | |
| 575 | #define PHY_CSR0 0x3080 | |
| 576 | #define PHY_CSR0_PA_PE_BG FIELD32(0x00010000) | |
| 577 | #define PHY_CSR0_PA_PE_A FIELD32(0x00020000) | |
| 578 | ||
| 579 | /* | |
| 580 | * PHY_CSR1 | |
| 581 | */ | |
| 582 | #define PHY_CSR1 0x3084 | |
| 583 | ||
| 584 | /* | |
| 585 | * PHY_CSR2: Pre-TX BBP control. | |
| 586 | */ | |
| 587 | #define PHY_CSR2 0x3088 | |
| 588 | ||
| 589 | /* | |
| 590 | * PHY_CSR3: BBP serial control register. | |
| 591 | * VALUE: Register value to program into BBP. | |
| 592 | * REG_NUM: Selected BBP register. | |
| 593 | * READ_CONTROL: 0: Write BBP, 1: Read BBP. | |
| 594 | * BUSY: 1: ASIC is busy execute BBP programming. | |
| 595 | */ | |
| 596 | #define PHY_CSR3 0x308c | |
| 597 | #define PHY_CSR3_VALUE FIELD32(0x000000ff) | |
| 598 | #define PHY_CSR3_REGNUM FIELD32(0x00007f00) | |
| 599 | #define PHY_CSR3_READ_CONTROL FIELD32(0x00008000) | |
| 600 | #define PHY_CSR3_BUSY FIELD32(0x00010000) | |
| 601 | ||
| 602 | /* | |
| 603 | * PHY_CSR4: RF serial control register | |
| 604 | * VALUE: Register value (include register id) serial out to RF/IF chip. | |
| 605 | * NUMBER_OF_BITS: Number of bits used in RFRegValue (I:20, RFMD:22). | |
| 606 | * IF_SELECT: 1: select IF to program, 0: select RF to program. | |
| 607 | * PLL_LD: RF PLL_LD status. | |
| 608 | * BUSY: 1: ASIC is busy execute RF programming. | |
| 609 | */ | |
| 610 | #define PHY_CSR4 0x3090 | |
| 611 | #define PHY_CSR4_VALUE FIELD32(0x00ffffff) | |
| 612 | #define PHY_CSR4_NUMBER_OF_BITS FIELD32(0x1f000000) | |
| 613 | #define PHY_CSR4_IF_SELECT FIELD32(0x20000000) | |
| 614 | #define PHY_CSR4_PLL_LD FIELD32(0x40000000) | |
| 615 | #define PHY_CSR4_BUSY FIELD32(0x80000000) | |
| 616 | ||
| 617 | /* | |
| 618 | * PHY_CSR5: RX to TX signal switch timing control. | |
| 619 | */ | |
| 620 | #define PHY_CSR5 0x3094 | |
| 621 | #define PHY_CSR5_IQ_FLIP FIELD32(0x00000004) | |
| 622 | ||
| 623 | /* | |
| 624 | * PHY_CSR6: TX to RX signal timing control. | |
| 625 | */ | |
| 626 | #define PHY_CSR6 0x3098 | |
| 627 | #define PHY_CSR6_IQ_FLIP FIELD32(0x00000004) | |
| 628 | ||
| 629 | /* | |
| 630 | * PHY_CSR7: TX DAC switching timing control. | |
| 631 | */ | |
| 632 | #define PHY_CSR7 0x309c | |
| 633 | ||
| 634 | /* | |
| 635 | * Security control register. | |
| 636 | */ | |
| 637 | ||
| 638 | /* | |
| 639 | * SEC_CSR0: Shared key table control. | |
| 640 | */ | |
| 641 | #define SEC_CSR0 0x30a0 | |
| 642 | #define SEC_CSR0_BSS0_KEY0_VALID FIELD32(0x00000001) | |
| 643 | #define SEC_CSR0_BSS0_KEY1_VALID FIELD32(0x00000002) | |
| 644 | #define SEC_CSR0_BSS0_KEY2_VALID FIELD32(0x00000004) | |
| 645 | #define SEC_CSR0_BSS0_KEY3_VALID FIELD32(0x00000008) | |
| 646 | #define SEC_CSR0_BSS1_KEY0_VALID FIELD32(0x00000010) | |
| 647 | #define SEC_CSR0_BSS1_KEY1_VALID FIELD32(0x00000020) | |
| 648 | #define SEC_CSR0_BSS1_KEY2_VALID FIELD32(0x00000040) | |
| 649 | #define SEC_CSR0_BSS1_KEY3_VALID FIELD32(0x00000080) | |
| 650 | #define SEC_CSR0_BSS2_KEY0_VALID FIELD32(0x00000100) | |
| 651 | #define SEC_CSR0_BSS2_KEY1_VALID FIELD32(0x00000200) | |
| 652 | #define SEC_CSR0_BSS2_KEY2_VALID FIELD32(0x00000400) | |
| 653 | #define SEC_CSR0_BSS2_KEY3_VALID FIELD32(0x00000800) | |
| 654 | #define SEC_CSR0_BSS3_KEY0_VALID FIELD32(0x00001000) | |
| 655 | #define SEC_CSR0_BSS3_KEY1_VALID FIELD32(0x00002000) | |
| 656 | #define SEC_CSR0_BSS3_KEY2_VALID FIELD32(0x00004000) | |
| 657 | #define SEC_CSR0_BSS3_KEY3_VALID FIELD32(0x00008000) | |
| 658 | ||
| 659 | /* | |
| 660 | * SEC_CSR1: Shared key table security mode register. | |
| 661 | */ | |
| 662 | #define SEC_CSR1 0x30a4 | |
| 663 | #define SEC_CSR1_BSS0_KEY0_CIPHER_ALG FIELD32(0x00000007) | |
| 664 | #define SEC_CSR1_BSS0_KEY1_CIPHER_ALG FIELD32(0x00000070) | |
| 665 | #define SEC_CSR1_BSS0_KEY2_CIPHER_ALG FIELD32(0x00000700) | |
| 666 | #define SEC_CSR1_BSS0_KEY3_CIPHER_ALG FIELD32(0x00007000) | |
| 667 | #define SEC_CSR1_BSS1_KEY0_CIPHER_ALG FIELD32(0x00070000) | |
| 668 | #define SEC_CSR1_BSS1_KEY1_CIPHER_ALG FIELD32(0x00700000) | |
| 669 | #define SEC_CSR1_BSS1_KEY2_CIPHER_ALG FIELD32(0x07000000) | |
| 670 | #define SEC_CSR1_BSS1_KEY3_CIPHER_ALG FIELD32(0x70000000) | |
| 671 | ||
| 672 | /* | |
| 673 | * Pairwise key table valid bitmap registers. | |
| 674 | * SEC_CSR2: pairwise key table valid bitmap 0. | |
| 675 | * SEC_CSR3: pairwise key table valid bitmap 1. | |
| 676 | */ | |
| 677 | #define SEC_CSR2 0x30a8 | |
| 678 | #define SEC_CSR3 0x30ac | |
| 679 | ||
| 680 | /* | |
| 681 | * SEC_CSR4: Pairwise key table lookup control. | |
| 682 | */ | |
| 683 | #define SEC_CSR4 0x30b0 | |
| 61e754f4 ID |
684 | #define SEC_CSR4_ENABLE_BSS0 FIELD32(0x00000001) |
| 685 | #define SEC_CSR4_ENABLE_BSS1 FIELD32(0x00000002) | |
| 686 | #define SEC_CSR4_ENABLE_BSS2 FIELD32(0x00000004) | |
| 687 | #define SEC_CSR4_ENABLE_BSS3 FIELD32(0x00000008) | |
| 95ea3627 ID |
688 | |
| 689 | /* | |
| 690 | * SEC_CSR5: shared key table security mode register. | |
| 691 | */ | |
| 692 | #define SEC_CSR5 0x30b4 | |
| 693 | #define SEC_CSR5_BSS2_KEY0_CIPHER_ALG FIELD32(0x00000007) | |
| 694 | #define SEC_CSR5_BSS2_KEY1_CIPHER_ALG FIELD32(0x00000070) | |
| 695 | #define SEC_CSR5_BSS2_KEY2_CIPHER_ALG FIELD32(0x00000700) | |
| 696 | #define SEC_CSR5_BSS2_KEY3_CIPHER_ALG FIELD32(0x00007000) | |
| 697 | #define SEC_CSR5_BSS3_KEY0_CIPHER_ALG FIELD32(0x00070000) | |
| 698 | #define SEC_CSR5_BSS3_KEY1_CIPHER_ALG FIELD32(0x00700000) | |
| 699 | #define SEC_CSR5_BSS3_KEY2_CIPHER_ALG FIELD32(0x07000000) | |
| 700 | #define SEC_CSR5_BSS3_KEY3_CIPHER_ALG FIELD32(0x70000000) | |
| 701 | ||
| 702 | /* | |
| 703 | * STA control registers. | |
| 704 | */ | |
| 705 | ||
| 706 | /* | |
| 707 | * STA_CSR0: RX PLCP error count & RX FCS error count. | |
| 708 | */ | |
| 709 | #define STA_CSR0 0x30c0 | |
| 710 | #define STA_CSR0_FCS_ERROR FIELD32(0x0000ffff) | |
| 711 | #define STA_CSR0_PLCP_ERROR FIELD32(0xffff0000) | |
| 712 | ||
| 713 | /* | |
| 714 | * STA_CSR1: RX False CCA count & RX LONG frame count. | |
| 715 | */ | |
| 716 | #define STA_CSR1 0x30c4 | |
| 717 | #define STA_CSR1_PHYSICAL_ERROR FIELD32(0x0000ffff) | |
| 718 | #define STA_CSR1_FALSE_CCA_ERROR FIELD32(0xffff0000) | |
| 719 | ||
| 720 | /* | |
| 721 | * STA_CSR2: TX Beacon count and RX FIFO overflow count. | |
| 722 | */ | |
| 723 | #define STA_CSR2 0x30c8 | |
| 724 | #define STA_CSR2_RX_FIFO_OVERFLOW_COUNT FIELD32(0x0000ffff) | |
| 725 | #define STA_CSR2_RX_OVERFLOW_COUNT FIELD32(0xffff0000) | |
| 726 | ||
| 727 | /* | |
| 728 | * STA_CSR3: TX Beacon count. | |
| 729 | */ | |
| 730 | #define STA_CSR3 0x30cc | |
| 731 | #define STA_CSR3_TX_BEACON_COUNT FIELD32(0x0000ffff) | |
| 732 | ||
| 733 | /* | |
| 734 | * STA_CSR4: TX Result status register. | |
| 735 | * VALID: 1:This register contains a valid TX result. | |
| 736 | */ | |
| 737 | #define STA_CSR4 0x30d0 | |
| 738 | #define STA_CSR4_VALID FIELD32(0x00000001) | |
| 739 | #define STA_CSR4_TX_RESULT FIELD32(0x0000000e) | |
| 740 | #define STA_CSR4_RETRY_COUNT FIELD32(0x000000f0) | |
| 741 | #define STA_CSR4_PID_SUBTYPE FIELD32(0x00001f00) | |
| 742 | #define STA_CSR4_PID_TYPE FIELD32(0x0000e000) | |
| 743 | #define STA_CSR4_TXRATE FIELD32(0x000f0000) | |
| 744 | ||
| 745 | /* | |
| 746 | * QOS control registers. | |
| 747 | */ | |
| 748 | ||
| 749 | /* | |
| 750 | * QOS_CSR0: TXOP holder MAC address register. | |
| 751 | */ | |
| 752 | #define QOS_CSR0 0x30e0 | |
| 753 | #define QOS_CSR0_BYTE0 FIELD32(0x000000ff) | |
| 754 | #define QOS_CSR0_BYTE1 FIELD32(0x0000ff00) | |
| 755 | #define QOS_CSR0_BYTE2 FIELD32(0x00ff0000) | |
| 756 | #define QOS_CSR0_BYTE3 FIELD32(0xff000000) | |
| 757 | ||
| 758 | /* | |
| 759 | * QOS_CSR1: TXOP holder MAC address register. | |
| 760 | */ | |
| 761 | #define QOS_CSR1 0x30e4 | |
| 762 | #define QOS_CSR1_BYTE4 FIELD32(0x000000ff) | |
| 763 | #define QOS_CSR1_BYTE5 FIELD32(0x0000ff00) | |
| 764 | ||
| 765 | /* | |
| 766 | * QOS_CSR2: TXOP holder timeout register. | |
| 767 | */ | |
| 768 | #define QOS_CSR2 0x30e8 | |
| 769 | ||
| 770 | /* | |
| 771 | * RX QOS-CFPOLL MAC address register. | |
| 772 | * QOS_CSR3: RX QOS-CFPOLL MAC address 0. | |
| 773 | * QOS_CSR4: RX QOS-CFPOLL MAC address 1. | |
| 774 | */ | |
| 775 | #define QOS_CSR3 0x30ec | |
| 776 | #define QOS_CSR4 0x30f0 | |
| 777 | ||
| 778 | /* | |
| 779 | * QOS_CSR5: "QosControl" field of the RX QOS-CFPOLL. | |
| 780 | */ | |
| 781 | #define QOS_CSR5 0x30f4 | |
| 782 | ||
| 783 | /* | |
| 784 | * Host DMA registers. | |
| 785 | */ | |
| 786 | ||
| 787 | /* | |
| f615e9a3 | 788 | * AC0_BASE_CSR: AC_VO base address. |
| 95ea3627 ID |
789 | */ |
| 790 | #define AC0_BASE_CSR 0x3400 | |
| 791 | #define AC0_BASE_CSR_RING_REGISTER FIELD32(0xffffffff) | |
| 792 | ||
| 793 | /* | |
| f615e9a3 | 794 | * AC1_BASE_CSR: AC_VI base address. |
| 95ea3627 ID |
795 | */ |
| 796 | #define AC1_BASE_CSR 0x3404 | |
| 797 | #define AC1_BASE_CSR_RING_REGISTER FIELD32(0xffffffff) | |
| 798 | ||
| 799 | /* | |
| f615e9a3 | 800 | * AC2_BASE_CSR: AC_BE base address. |
| 95ea3627 ID |
801 | */ |
| 802 | #define AC2_BASE_CSR 0x3408 | |
| 803 | #define AC2_BASE_CSR_RING_REGISTER FIELD32(0xffffffff) | |
| 804 | ||
| 805 | /* | |
| f615e9a3 | 806 | * AC3_BASE_CSR: AC_BK base address. |
| 95ea3627 ID |
807 | */ |
| 808 | #define AC3_BASE_CSR 0x340c | |
| 809 | #define AC3_BASE_CSR_RING_REGISTER FIELD32(0xffffffff) | |
| 810 | ||
| 811 | /* | |
| 812 | * MGMT_BASE_CSR: MGMT ring base address. | |
| 813 | */ | |
| 814 | #define MGMT_BASE_CSR 0x3410 | |
| 815 | #define MGMT_BASE_CSR_RING_REGISTER FIELD32(0xffffffff) | |
| 816 | ||
| 817 | /* | |
| f615e9a3 | 818 | * TX_RING_CSR0: TX Ring size for AC_VO, AC_VI, AC_BE, AC_BK. |
| 95ea3627 ID |
819 | */ |
| 820 | #define TX_RING_CSR0 0x3418 | |
| 821 | #define TX_RING_CSR0_AC0_RING_SIZE FIELD32(0x000000ff) | |
| 822 | #define TX_RING_CSR0_AC1_RING_SIZE FIELD32(0x0000ff00) | |
| 823 | #define TX_RING_CSR0_AC2_RING_SIZE FIELD32(0x00ff0000) | |
| 824 | #define TX_RING_CSR0_AC3_RING_SIZE FIELD32(0xff000000) | |
| 825 | ||
| 826 | /* | |
| 827 | * TX_RING_CSR1: TX Ring size for MGMT Ring, HCCA Ring | |
| 828 | * TXD_SIZE: In unit of 32-bit. | |
| 829 | */ | |
| 830 | #define TX_RING_CSR1 0x341c | |
| 831 | #define TX_RING_CSR1_MGMT_RING_SIZE FIELD32(0x000000ff) | |
| 832 | #define TX_RING_CSR1_HCCA_RING_SIZE FIELD32(0x0000ff00) | |
| 833 | #define TX_RING_CSR1_TXD_SIZE FIELD32(0x003f0000) | |
| 834 | ||
| 835 | /* | |
| 836 | * AIFSN_CSR: AIFSN for each EDCA AC. | |
| f615e9a3 ID |
837 | * AIFSN0: For AC_VO. |
| 838 | * AIFSN1: For AC_VI. | |
| 839 | * AIFSN2: For AC_BE. | |
| 840 | * AIFSN3: For AC_BK. | |
| 95ea3627 ID |
841 | */ |
| 842 | #define AIFSN_CSR 0x3420 | |
| 843 | #define AIFSN_CSR_AIFSN0 FIELD32(0x0000000f) | |
| 844 | #define AIFSN_CSR_AIFSN1 FIELD32(0x000000f0) | |
| 845 | #define AIFSN_CSR_AIFSN2 FIELD32(0x00000f00) | |
| 846 | #define AIFSN_CSR_AIFSN3 FIELD32(0x0000f000) | |
| 847 | ||
| 848 | /* | |
| 849 | * CWMIN_CSR: CWmin for each EDCA AC. | |
| f615e9a3 ID |
850 | * CWMIN0: For AC_VO. |
| 851 | * CWMIN1: For AC_VI. | |
| 852 | * CWMIN2: For AC_BE. | |
| 853 | * CWMIN3: For AC_BK. | |
| 95ea3627 ID |
854 | */ |
| 855 | #define CWMIN_CSR 0x3424 | |
| 856 | #define CWMIN_CSR_CWMIN0 FIELD32(0x0000000f) | |
| 857 | #define CWMIN_CSR_CWMIN1 FIELD32(0x000000f0) | |
| 858 | #define CWMIN_CSR_CWMIN2 FIELD32(0x00000f00) | |
| 859 | #define CWMIN_CSR_CWMIN3 FIELD32(0x0000f000) | |
| 860 | ||
| 861 | /* | |
| 862 | * CWMAX_CSR: CWmax for each EDCA AC. | |
| f615e9a3 ID |
863 | * CWMAX0: For AC_VO. |
| 864 | * CWMAX1: For AC_VI. | |
| 865 | * CWMAX2: For AC_BE. | |
| 866 | * CWMAX3: For AC_BK. | |
| 95ea3627 ID |
867 | */ |
| 868 | #define CWMAX_CSR 0x3428 | |
| 869 | #define CWMAX_CSR_CWMAX0 FIELD32(0x0000000f) | |
| 870 | #define CWMAX_CSR_CWMAX1 FIELD32(0x000000f0) | |
| 871 | #define CWMAX_CSR_CWMAX2 FIELD32(0x00000f00) | |
| 872 | #define CWMAX_CSR_CWMAX3 FIELD32(0x0000f000) | |
| 873 | ||
| 874 | /* | |
| 875 | * TX_DMA_DST_CSR: TX DMA destination | |
| 876 | * 0: TX ring0, 1: TX ring1, 2: TX ring2 3: invalid | |
| 877 | */ | |
| 878 | #define TX_DMA_DST_CSR 0x342c | |
| 879 | #define TX_DMA_DST_CSR_DEST_AC0 FIELD32(0x00000003) | |
| 880 | #define TX_DMA_DST_CSR_DEST_AC1 FIELD32(0x0000000c) | |
| 881 | #define TX_DMA_DST_CSR_DEST_AC2 FIELD32(0x00000030) | |
| 882 | #define TX_DMA_DST_CSR_DEST_AC3 FIELD32(0x000000c0) | |
| 883 | #define TX_DMA_DST_CSR_DEST_MGMT FIELD32(0x00000300) | |
| 884 | ||
| 885 | /* | |
| 886 | * TX_CNTL_CSR: KICK/Abort TX. | |
| f615e9a3 ID |
887 | * KICK_TX_AC0: For AC_VO. |
| 888 | * KICK_TX_AC1: For AC_VI. | |
| 889 | * KICK_TX_AC2: For AC_BE. | |
| 890 | * KICK_TX_AC3: For AC_BK. | |
| 891 | * ABORT_TX_AC0: For AC_VO. | |
| 892 | * ABORT_TX_AC1: For AC_VI. | |
| 893 | * ABORT_TX_AC2: For AC_BE. | |
| 894 | * ABORT_TX_AC3: For AC_BK. | |
| 95ea3627 ID |
895 | */ |
| 896 | #define TX_CNTL_CSR 0x3430 | |
| 897 | #define TX_CNTL_CSR_KICK_TX_AC0 FIELD32(0x00000001) | |
| 898 | #define TX_CNTL_CSR_KICK_TX_AC1 FIELD32(0x00000002) | |
| 899 | #define TX_CNTL_CSR_KICK_TX_AC2 FIELD32(0x00000004) | |
| 900 | #define TX_CNTL_CSR_KICK_TX_AC3 FIELD32(0x00000008) | |
| 901 | #define TX_CNTL_CSR_KICK_TX_MGMT FIELD32(0x00000010) | |
| 902 | #define TX_CNTL_CSR_ABORT_TX_AC0 FIELD32(0x00010000) | |
| 903 | #define TX_CNTL_CSR_ABORT_TX_AC1 FIELD32(0x00020000) | |
| 904 | #define TX_CNTL_CSR_ABORT_TX_AC2 FIELD32(0x00040000) | |
| 905 | #define TX_CNTL_CSR_ABORT_TX_AC3 FIELD32(0x00080000) | |
| 906 | #define TX_CNTL_CSR_ABORT_TX_MGMT FIELD32(0x00100000) | |
| 907 | ||
| 908 | /* | |
| 16938a24 | 909 | * LOAD_TX_RING_CSR: Load RX desriptor |
| 95ea3627 ID |
910 | */ |
| 911 | #define LOAD_TX_RING_CSR 0x3434 | |
| 912 | #define LOAD_TX_RING_CSR_LOAD_TXD_AC0 FIELD32(0x00000001) | |
| 913 | #define LOAD_TX_RING_CSR_LOAD_TXD_AC1 FIELD32(0x00000002) | |
| 914 | #define LOAD_TX_RING_CSR_LOAD_TXD_AC2 FIELD32(0x00000004) | |
| 915 | #define LOAD_TX_RING_CSR_LOAD_TXD_AC3 FIELD32(0x00000008) | |
| 916 | #define LOAD_TX_RING_CSR_LOAD_TXD_MGMT FIELD32(0x00000010) | |
| 917 | ||
| 918 | /* | |
| 919 | * Several read-only registers, for debugging. | |
| 920 | */ | |
| 921 | #define AC0_TXPTR_CSR 0x3438 | |
| 922 | #define AC1_TXPTR_CSR 0x343c | |
| 923 | #define AC2_TXPTR_CSR 0x3440 | |
| 924 | #define AC3_TXPTR_CSR 0x3444 | |
| 925 | #define MGMT_TXPTR_CSR 0x3448 | |
| 926 | ||
| 927 | /* | |
| 928 | * RX_BASE_CSR | |
| 929 | */ | |
| 930 | #define RX_BASE_CSR 0x3450 | |
| 931 | #define RX_BASE_CSR_RING_REGISTER FIELD32(0xffffffff) | |
| 932 | ||
| 933 | /* | |
| 934 | * RX_RING_CSR. | |
| 935 | * RXD_SIZE: In unit of 32-bit. | |
| 936 | */ | |
| 937 | #define RX_RING_CSR 0x3454 | |
| 938 | #define RX_RING_CSR_RING_SIZE FIELD32(0x000000ff) | |
| 939 | #define RX_RING_CSR_RXD_SIZE FIELD32(0x00003f00) | |
| 940 | #define RX_RING_CSR_RXD_WRITEBACK_SIZE FIELD32(0x00070000) | |
| 941 | ||
| 942 | /* | |
| 943 | * RX_CNTL_CSR | |
| 944 | */ | |
| 945 | #define RX_CNTL_CSR 0x3458 | |
| 946 | #define RX_CNTL_CSR_ENABLE_RX_DMA FIELD32(0x00000001) | |
| 947 | #define RX_CNTL_CSR_LOAD_RXD FIELD32(0x00000002) | |
| 948 | ||
| 949 | /* | |
| 950 | * RXPTR_CSR: Read-only, for debugging. | |
| 951 | */ | |
| 952 | #define RXPTR_CSR 0x345c | |
| 953 | ||
| 954 | /* | |
| 955 | * PCI_CFG_CSR | |
| 956 | */ | |
| 957 | #define PCI_CFG_CSR 0x3460 | |
| 958 | ||
| 959 | /* | |
| 960 | * BUF_FORMAT_CSR | |
| 961 | */ | |
| 962 | #define BUF_FORMAT_CSR 0x3464 | |
| 963 | ||
| 964 | /* | |
| 965 | * INT_SOURCE_CSR: Interrupt source register. | |
| 966 | * Write one to clear corresponding bit. | |
| 967 | */ | |
| 968 | #define INT_SOURCE_CSR 0x3468 | |
| 969 | #define INT_SOURCE_CSR_TXDONE FIELD32(0x00000001) | |
| 970 | #define INT_SOURCE_CSR_RXDONE FIELD32(0x00000002) | |
| 971 | #define INT_SOURCE_CSR_BEACON_DONE FIELD32(0x00000004) | |
| 972 | #define INT_SOURCE_CSR_TX_ABORT_DONE FIELD32(0x00000010) | |
| 973 | #define INT_SOURCE_CSR_AC0_DMA_DONE FIELD32(0x00010000) | |
| 974 | #define INT_SOURCE_CSR_AC1_DMA_DONE FIELD32(0x00020000) | |
| 975 | #define INT_SOURCE_CSR_AC2_DMA_DONE FIELD32(0x00040000) | |
| 976 | #define INT_SOURCE_CSR_AC3_DMA_DONE FIELD32(0x00080000) | |
| 977 | #define INT_SOURCE_CSR_MGMT_DMA_DONE FIELD32(0x00100000) | |
| 978 | #define INT_SOURCE_CSR_HCCA_DMA_DONE FIELD32(0x00200000) | |
| 979 | ||
| 980 | /* | |
| 981 | * INT_MASK_CSR: Interrupt MASK register. 1: the interrupt is mask OFF. | |
| 982 | * MITIGATION_PERIOD: Interrupt mitigation in unit of 32 PCI clock. | |
| 983 | */ | |
| 984 | #define INT_MASK_CSR 0x346c | |
| 985 | #define INT_MASK_CSR_TXDONE FIELD32(0x00000001) | |
| 986 | #define INT_MASK_CSR_RXDONE FIELD32(0x00000002) | |
| 987 | #define INT_MASK_CSR_BEACON_DONE FIELD32(0x00000004) | |
| 988 | #define INT_MASK_CSR_TX_ABORT_DONE FIELD32(0x00000010) | |
| 989 | #define INT_MASK_CSR_ENABLE_MITIGATION FIELD32(0x00000080) | |
| 990 | #define INT_MASK_CSR_MITIGATION_PERIOD FIELD32(0x0000ff00) | |
| 991 | #define INT_MASK_CSR_AC0_DMA_DONE FIELD32(0x00010000) | |
| 992 | #define INT_MASK_CSR_AC1_DMA_DONE FIELD32(0x00020000) | |
| 993 | #define INT_MASK_CSR_AC2_DMA_DONE FIELD32(0x00040000) | |
| 994 | #define INT_MASK_CSR_AC3_DMA_DONE FIELD32(0x00080000) | |
| 995 | #define INT_MASK_CSR_MGMT_DMA_DONE FIELD32(0x00100000) | |
| 996 | #define INT_MASK_CSR_HCCA_DMA_DONE FIELD32(0x00200000) | |
| 997 | ||
| 998 | /* | |
| 999 | * E2PROM_CSR: EEPROM control register. | |
| 1000 | * RELOAD: Write 1 to reload eeprom content. | |
| 1001 | * TYPE_93C46: 1: 93c46, 0:93c66. | |
| 1002 | * LOAD_STATUS: 1:loading, 0:done. | |
| 1003 | */ | |
| 1004 | #define E2PROM_CSR 0x3470 | |
| 1005 | #define E2PROM_CSR_RELOAD FIELD32(0x00000001) | |
| 1006 | #define E2PROM_CSR_DATA_CLOCK FIELD32(0x00000002) | |
| 1007 | #define E2PROM_CSR_CHIP_SELECT FIELD32(0x00000004) | |
| 1008 | #define E2PROM_CSR_DATA_IN FIELD32(0x00000008) | |
| 1009 | #define E2PROM_CSR_DATA_OUT FIELD32(0x00000010) | |
| 1010 | #define E2PROM_CSR_TYPE_93C46 FIELD32(0x00000020) | |
| 1011 | #define E2PROM_CSR_LOAD_STATUS FIELD32(0x00000040) | |
| 1012 | ||
| 1013 | /* | |
| f615e9a3 ID |
1014 | * AC_TXOP_CSR0: AC_VO/AC_VI TXOP register. |
| 1015 | * AC0_TX_OP: For AC_VO, in unit of 32us. | |
| 1016 | * AC1_TX_OP: For AC_VI, in unit of 32us. | |
| 95ea3627 ID |
1017 | */ |
| 1018 | #define AC_TXOP_CSR0 0x3474 | |
| 1019 | #define AC_TXOP_CSR0_AC0_TX_OP FIELD32(0x0000ffff) | |
| 1020 | #define AC_TXOP_CSR0_AC1_TX_OP FIELD32(0xffff0000) | |
| 1021 | ||
| 1022 | /* | |
| f615e9a3 ID |
1023 | * AC_TXOP_CSR1: AC_BE/AC_BK TXOP register. |
| 1024 | * AC2_TX_OP: For AC_BE, in unit of 32us. | |
| 1025 | * AC3_TX_OP: For AC_BK, in unit of 32us. | |
| 95ea3627 ID |
1026 | */ |
| 1027 | #define AC_TXOP_CSR1 0x3478 | |
| 1028 | #define AC_TXOP_CSR1_AC2_TX_OP FIELD32(0x0000ffff) | |
| 1029 | #define AC_TXOP_CSR1_AC3_TX_OP FIELD32(0xffff0000) | |
| 1030 | ||
| 1031 | /* | |
| 1032 | * DMA_STATUS_CSR | |
| 1033 | */ | |
| 1034 | #define DMA_STATUS_CSR 0x3480 | |
| 1035 | ||
| 1036 | /* | |
| 1037 | * TEST_MODE_CSR | |
| 1038 | */ | |
| 1039 | #define TEST_MODE_CSR 0x3484 | |
| 1040 | ||
| 1041 | /* | |
| 1042 | * UART0_TX_CSR | |
| 1043 | */ | |
| 1044 | #define UART0_TX_CSR 0x3488 | |
| 1045 | ||
| 1046 | /* | |
| 1047 | * UART0_RX_CSR | |
| 1048 | */ | |
| 1049 | #define UART0_RX_CSR 0x348c | |
| 1050 | ||
| 1051 | /* | |
| 1052 | * UART0_FRAME_CSR | |
| 1053 | */ | |
| 1054 | #define UART0_FRAME_CSR 0x3490 | |
| 1055 | ||
| 1056 | /* | |
| 1057 | * UART0_BUFFER_CSR | |
| 1058 | */ | |
| 1059 | #define UART0_BUFFER_CSR 0x3494 | |
| 1060 | ||
| 1061 | /* | |
| 1062 | * IO_CNTL_CSR | |
| 7d7f19cc | 1063 | * RF_PS: Set RF interface value to power save |
| 95ea3627 ID |
1064 | */ |
| 1065 | #define IO_CNTL_CSR 0x3498 | |
| 7d7f19cc | 1066 | #define IO_CNTL_CSR_RF_PS FIELD32(0x00000004) |
| 95ea3627 ID |
1067 | |
| 1068 | /* | |
| 1069 | * UART_INT_SOURCE_CSR | |
| 1070 | */ | |
| 1071 | #define UART_INT_SOURCE_CSR 0x34a8 | |
| 1072 | ||
| 1073 | /* | |
| 1074 | * UART_INT_MASK_CSR | |
| 1075 | */ | |
| 1076 | #define UART_INT_MASK_CSR 0x34ac | |
| 1077 | ||
| 1078 | /* | |
| 1079 | * PBF_QUEUE_CSR | |
| 1080 | */ | |
| 1081 | #define PBF_QUEUE_CSR 0x34b0 | |
| 1082 | ||
| 1083 | /* | |
| 1084 | * Firmware DMA registers. | |
| 1085 | * Firmware DMA registers are dedicated for MCU usage | |
| 1086 | * and should not be touched by host driver. | |
| 1087 | * Therefore we skip the definition of these registers. | |
| 1088 | */ | |
| 1089 | #define FW_TX_BASE_CSR 0x34c0 | |
| 1090 | #define FW_TX_START_CSR 0x34c4 | |
| 1091 | #define FW_TX_LAST_CSR 0x34c8 | |
| 1092 | #define FW_MODE_CNTL_CSR 0x34cc | |
| 1093 | #define FW_TXPTR_CSR 0x34d0 | |
| 1094 | ||
| 1095 | /* | |
| 1096 | * 8051 firmware image. | |
| 1097 | */ | |
| 1098 | #define FIRMWARE_RT2561 "rt2561.bin" | |
| 1099 | #define FIRMWARE_RT2561s "rt2561s.bin" | |
| 1100 | #define FIRMWARE_RT2661 "rt2661.bin" | |
| 1101 | #define FIRMWARE_IMAGE_BASE 0x4000 | |
| 1102 | ||
| 1103 | /* | |
| 1104 | * BBP registers. | |
| 1105 | * The wordsize of the BBP is 8 bits. | |
| 1106 | */ | |
| 1107 | ||
| 1108 | /* | |
| 1109 | * R2 | |
| 1110 | */ | |
| 1111 | #define BBP_R2_BG_MODE FIELD8(0x20) | |
| 1112 | ||
| 1113 | /* | |
| 1114 | * R3 | |
| 1115 | */ | |
| 1116 | #define BBP_R3_SMART_MODE FIELD8(0x01) | |
| 1117 | ||
| 1118 | /* | |
| 1119 | * R4: RX antenna control | |
| 1120 | * FRAME_END: 1 - DPDT, 0 - SPDT (Only valid for 802.11G, RF2527 & RF2529) | |
| 1121 | */ | |
| acaa410d MN |
1122 | |
| 1123 | /* | |
| 1124 | * ANTENNA_CONTROL semantics (guessed): | |
| 1125 | * 0x1: Software controlled antenna switching (fixed or SW diversity) | |
| 1126 | * 0x2: Hardware diversity. | |
| 1127 | */ | |
| 1128 | #define BBP_R4_RX_ANTENNA_CONTROL FIELD8(0x03) | |
| 95ea3627 ID |
1129 | #define BBP_R4_RX_FRAME_END FIELD8(0x20) |
| 1130 | ||
| 1131 | /* | |
| 1132 | * R77 | |
| 1133 | */ | |
| acaa410d | 1134 | #define BBP_R77_RX_ANTENNA FIELD8(0x03) |
| 95ea3627 ID |
1135 | |
| 1136 | /* | |
| 1137 | * RF registers | |
| 1138 | */ | |
| 1139 | ||
| 1140 | /* | |
| 1141 | * RF 3 | |
| 1142 | */ | |
| 1143 | #define RF3_TXPOWER FIELD32(0x00003e00) | |
| 1144 | ||
| 1145 | /* | |
| 1146 | * RF 4 | |
| 1147 | */ | |
| 1148 | #define RF4_FREQ_OFFSET FIELD32(0x0003f000) | |
| 1149 | ||
| 1150 | /* | |
| 1151 | * EEPROM content. | |
| 1152 | * The wordsize of the EEPROM is 16 bits. | |
| 1153 | */ | |
| 1154 | ||
| 1155 | /* | |
| 1156 | * HW MAC address. | |
| 1157 | */ | |
| 1158 | #define EEPROM_MAC_ADDR_0 0x0002 | |
| 1159 | #define EEPROM_MAC_ADDR_BYTE0 FIELD16(0x00ff) | |
| 1160 | #define EEPROM_MAC_ADDR_BYTE1 FIELD16(0xff00) | |
| ce359f90 | 1161 | #define EEPROM_MAC_ADDR1 0x0003 |
| 95ea3627 ID |
1162 | #define EEPROM_MAC_ADDR_BYTE2 FIELD16(0x00ff) |
| 1163 | #define EEPROM_MAC_ADDR_BYTE3 FIELD16(0xff00) | |
| ce359f90 | 1164 | #define EEPROM_MAC_ADDR_2 0x0004 |
| 95ea3627 ID |
1165 | #define EEPROM_MAC_ADDR_BYTE4 FIELD16(0x00ff) |
| 1166 | #define EEPROM_MAC_ADDR_BYTE5 FIELD16(0xff00) | |
| 1167 | ||
| 1168 | /* | |
| 1169 | * EEPROM antenna. | |
| 1170 | * ANTENNA_NUM: Number of antenna's. | |
| 1171 | * TX_DEFAULT: Default antenna 0: diversity, 1: A, 2: B. | |
| 1172 | * RX_DEFAULT: Default antenna 0: diversity, 1: A, 2: B. | |
| 1173 | * FRAME_TYPE: 0: DPDT , 1: SPDT , noted this bit is valid for g only. | |
| 1174 | * DYN_TXAGC: Dynamic TX AGC control. | |
| 1175 | * HARDWARE_RADIO: 1: Hardware controlled radio. Read GPIO0. | |
| 1176 | * RF_TYPE: Rf_type of this adapter. | |
| 1177 | */ | |
| 1178 | #define EEPROM_ANTENNA 0x0010 | |
| 1179 | #define EEPROM_ANTENNA_NUM FIELD16(0x0003) | |
| 1180 | #define EEPROM_ANTENNA_TX_DEFAULT FIELD16(0x000c) | |
| 1181 | #define EEPROM_ANTENNA_RX_DEFAULT FIELD16(0x0030) | |
| 1182 | #define EEPROM_ANTENNA_FRAME_TYPE FIELD16(0x0040) | |
| 1183 | #define EEPROM_ANTENNA_DYN_TXAGC FIELD16(0x0200) | |
| 1184 | #define EEPROM_ANTENNA_HARDWARE_RADIO FIELD16(0x0400) | |
| 1185 | #define EEPROM_ANTENNA_RF_TYPE FIELD16(0xf800) | |
| 1186 | ||
| 1187 | /* | |
| 1188 | * EEPROM NIC config. | |
| 1189 | * ENABLE_DIVERSITY: 1:enable, 0:disable. | |
| 1190 | * EXTERNAL_LNA_BG: External LNA enable for 2.4G. | |
| 1191 | * CARDBUS_ACCEL: 0:enable, 1:disable. | |
| 1192 | * EXTERNAL_LNA_A: External LNA enable for 5G. | |
| 1193 | */ | |
| 1194 | #define EEPROM_NIC 0x0011 | |
| 1195 | #define EEPROM_NIC_ENABLE_DIVERSITY FIELD16(0x0001) | |
| 1196 | #define EEPROM_NIC_TX_DIVERSITY FIELD16(0x0002) | |
| 91581b62 ID |
1197 | #define EEPROM_NIC_RX_FIXED FIELD16(0x0004) |
| 1198 | #define EEPROM_NIC_TX_FIXED FIELD16(0x0008) | |
| 95ea3627 ID |
1199 | #define EEPROM_NIC_EXTERNAL_LNA_BG FIELD16(0x0010) |
| 1200 | #define EEPROM_NIC_CARDBUS_ACCEL FIELD16(0x0020) | |
| 1201 | #define EEPROM_NIC_EXTERNAL_LNA_A FIELD16(0x0040) | |
| 1202 | ||
| 1203 | /* | |
| 1204 | * EEPROM geography. | |
| 1205 | * GEO_A: Default geographical setting for 5GHz band | |
| 1206 | * GEO: Default geographical setting. | |
| 1207 | */ | |
| 1208 | #define EEPROM_GEOGRAPHY 0x0012 | |
| 1209 | #define EEPROM_GEOGRAPHY_GEO_A FIELD16(0x00ff) | |
| 1210 | #define EEPROM_GEOGRAPHY_GEO FIELD16(0xff00) | |
| 1211 | ||
| 1212 | /* | |
| 1213 | * EEPROM BBP. | |
| 1214 | */ | |
| 1215 | #define EEPROM_BBP_START 0x0013 | |
| 1216 | #define EEPROM_BBP_SIZE 16 | |
| 1217 | #define EEPROM_BBP_VALUE FIELD16(0x00ff) | |
| 1218 | #define EEPROM_BBP_REG_ID FIELD16(0xff00) | |
| 1219 | ||
| 1220 | /* | |
| 1221 | * EEPROM TXPOWER 802.11G | |
| 1222 | */ | |
| 1223 | #define EEPROM_TXPOWER_G_START 0x0023 | |
| 1224 | #define EEPROM_TXPOWER_G_SIZE 7 | |
| 1225 | #define EEPROM_TXPOWER_G_1 FIELD16(0x00ff) | |
| 1226 | #define EEPROM_TXPOWER_G_2 FIELD16(0xff00) | |
| 1227 | ||
| 1228 | /* | |
| 1229 | * EEPROM Frequency | |
| 1230 | */ | |
| 1231 | #define EEPROM_FREQ 0x002f | |
| 1232 | #define EEPROM_FREQ_OFFSET FIELD16(0x00ff) | |
| 1233 | #define EEPROM_FREQ_SEQ_MASK FIELD16(0xff00) | |
| 1234 | #define EEPROM_FREQ_SEQ FIELD16(0x0300) | |
| 1235 | ||
| 1236 | /* | |
| 1237 | * EEPROM LED. | |
| 1238 | * POLARITY_RDY_G: Polarity RDY_G setting. | |
| 1239 | * POLARITY_RDY_A: Polarity RDY_A setting. | |
| 1240 | * POLARITY_ACT: Polarity ACT setting. | |
| 1241 | * POLARITY_GPIO_0: Polarity GPIO0 setting. | |
| 1242 | * POLARITY_GPIO_1: Polarity GPIO1 setting. | |
| 1243 | * POLARITY_GPIO_2: Polarity GPIO2 setting. | |
| 1244 | * POLARITY_GPIO_3: Polarity GPIO3 setting. | |
| 1245 | * POLARITY_GPIO_4: Polarity GPIO4 setting. | |
| 1246 | * LED_MODE: Led mode. | |
| 1247 | */ | |
| 1248 | #define EEPROM_LED 0x0030 | |
| 1249 | #define EEPROM_LED_POLARITY_RDY_G FIELD16(0x0001) | |
| 1250 | #define EEPROM_LED_POLARITY_RDY_A FIELD16(0x0002) | |
| 1251 | #define EEPROM_LED_POLARITY_ACT FIELD16(0x0004) | |
| 1252 | #define EEPROM_LED_POLARITY_GPIO_0 FIELD16(0x0008) | |
| 1253 | #define EEPROM_LED_POLARITY_GPIO_1 FIELD16(0x0010) | |
| 1254 | #define EEPROM_LED_POLARITY_GPIO_2 FIELD16(0x0020) | |
| 1255 | #define EEPROM_LED_POLARITY_GPIO_3 FIELD16(0x0040) | |
| 1256 | #define EEPROM_LED_POLARITY_GPIO_4 FIELD16(0x0080) | |
| 1257 | #define EEPROM_LED_LED_MODE FIELD16(0x1f00) | |
| 1258 | ||
| 1259 | /* | |
| 1260 | * EEPROM TXPOWER 802.11A | |
| 1261 | */ | |
| 1262 | #define EEPROM_TXPOWER_A_START 0x0031 | |
| 1263 | #define EEPROM_TXPOWER_A_SIZE 12 | |
| 1264 | #define EEPROM_TXPOWER_A_1 FIELD16(0x00ff) | |
| 1265 | #define EEPROM_TXPOWER_A_2 FIELD16(0xff00) | |
| 1266 | ||
| 1267 | /* | |
| 1268 | * EEPROM RSSI offset 802.11BG | |
| 1269 | */ | |
| 1270 | #define EEPROM_RSSI_OFFSET_BG 0x004d | |
| 1271 | #define EEPROM_RSSI_OFFSET_BG_1 FIELD16(0x00ff) | |
| 1272 | #define EEPROM_RSSI_OFFSET_BG_2 FIELD16(0xff00) | |
| 1273 | ||
| 1274 | /* | |
| 1275 | * EEPROM RSSI offset 802.11A | |
| 1276 | */ | |
| 1277 | #define EEPROM_RSSI_OFFSET_A 0x004e | |
| 1278 | #define EEPROM_RSSI_OFFSET_A_1 FIELD16(0x00ff) | |
| 1279 | #define EEPROM_RSSI_OFFSET_A_2 FIELD16(0xff00) | |
| 1280 | ||
| 1281 | /* | |
| 1282 | * MCU mailbox commands. | |
| 1283 | */ | |
| 1284 | #define MCU_SLEEP 0x30 | |
| 1285 | #define MCU_WAKEUP 0x31 | |
| 1286 | #define MCU_LED 0x50 | |
| 1287 | #define MCU_LED_STRENGTH 0x52 | |
| 1288 | ||
| 1289 | /* | |
| 1290 | * DMA descriptor defines. | |
| 1291 | */ | |
| 4bd7c452 | 1292 | #define TXD_DESC_SIZE ( 16 * sizeof(__le32) ) |
| 181d6902 | 1293 | #define TXINFO_SIZE ( 6 * sizeof(__le32) ) |
| 4bd7c452 | 1294 | #define RXD_DESC_SIZE ( 16 * sizeof(__le32) ) |
| 95ea3627 ID |
1295 | |
| 1296 | /* | |
| 1297 | * TX descriptor format for TX, PRIO and Beacon Ring. | |
| 1298 | */ | |
| 1299 | ||
| 1300 | /* | |
| 1301 | * Word0 | |
| 1302 | * TKIP_MIC: ASIC appends TKIP MIC if TKIP is used. | |
| 1303 | * KEY_TABLE: Use per-client pairwise KEY table. | |
| 1304 | * KEY_INDEX: | |
| 1305 | * Key index (0~31) to the pairwise KEY table. | |
| 1306 | * 0~3 to shared KEY table 0 (BSS0). | |
| 1307 | * 4~7 to shared KEY table 1 (BSS1). | |
| 1308 | * 8~11 to shared KEY table 2 (BSS2). | |
| 1309 | * 12~15 to shared KEY table 3 (BSS3). | |
| 1310 | * BURST: Next frame belongs to same "burst" event. | |
| 1311 | */ | |
| 1312 | #define TXD_W0_OWNER_NIC FIELD32(0x00000001) | |
| 1313 | #define TXD_W0_VALID FIELD32(0x00000002) | |
| 1314 | #define TXD_W0_MORE_FRAG FIELD32(0x00000004) | |
| 1315 | #define TXD_W0_ACK FIELD32(0x00000008) | |
| 1316 | #define TXD_W0_TIMESTAMP FIELD32(0x00000010) | |
| 1317 | #define TXD_W0_OFDM FIELD32(0x00000020) | |
| 1318 | #define TXD_W0_IFS FIELD32(0x00000040) | |
| 1319 | #define TXD_W0_RETRY_MODE FIELD32(0x00000080) | |
| 1320 | #define TXD_W0_TKIP_MIC FIELD32(0x00000100) | |
| 1321 | #define TXD_W0_KEY_TABLE FIELD32(0x00000200) | |
| 1322 | #define TXD_W0_KEY_INDEX FIELD32(0x0000fc00) | |
| 1323 | #define TXD_W0_DATABYTE_COUNT FIELD32(0x0fff0000) | |
| 1324 | #define TXD_W0_BURST FIELD32(0x10000000) | |
| 1325 | #define TXD_W0_CIPHER_ALG FIELD32(0xe0000000) | |
| 1326 | ||
| 1327 | /* | |
| 1328 | * Word1 | |
| 1329 | * HOST_Q_ID: EDCA/HCCA queue ID. | |
| 1330 | * HW_SEQUENCE: MAC overwrites the frame sequence number. | |
| 1331 | * BUFFER_COUNT: Number of buffers in this TXD. | |
| 1332 | */ | |
| 1333 | #define TXD_W1_HOST_Q_ID FIELD32(0x0000000f) | |
| 1334 | #define TXD_W1_AIFSN FIELD32(0x000000f0) | |
| 1335 | #define TXD_W1_CWMIN FIELD32(0x00000f00) | |
| 1336 | #define TXD_W1_CWMAX FIELD32(0x0000f000) | |
| 1337 | #define TXD_W1_IV_OFFSET FIELD32(0x003f0000) | |
| 1338 | #define TXD_W1_PIGGY_BACK FIELD32(0x01000000) | |
| 1339 | #define TXD_W1_HW_SEQUENCE FIELD32(0x10000000) | |
| 1340 | #define TXD_W1_BUFFER_COUNT FIELD32(0xe0000000) | |
| 1341 | ||
| 1342 | /* | |
| 1343 | * Word2: PLCP information | |
| 1344 | */ | |
| 1345 | #define TXD_W2_PLCP_SIGNAL FIELD32(0x000000ff) | |
| 1346 | #define TXD_W2_PLCP_SERVICE FIELD32(0x0000ff00) | |
| 1347 | #define TXD_W2_PLCP_LENGTH_LOW FIELD32(0x00ff0000) | |
| 1348 | #define TXD_W2_PLCP_LENGTH_HIGH FIELD32(0xff000000) | |
| 1349 | ||
| 1350 | /* | |
| 1351 | * Word3 | |
| 1352 | */ | |
| 1353 | #define TXD_W3_IV FIELD32(0xffffffff) | |
| 1354 | ||
| 1355 | /* | |
| 1356 | * Word4 | |
| 1357 | */ | |
| 1358 | #define TXD_W4_EIV FIELD32(0xffffffff) | |
| 1359 | ||
| 1360 | /* | |
| 1361 | * Word5 | |
| 1362 | * FRAME_OFFSET: Frame start offset inside ASIC TXFIFO (after TXINFO field). | |
| 1363 | * TXD_W5_PID_SUBTYPE: Driver assigned packet ID index for txdone handler. | |
| 1364 | * TXD_W5_PID_TYPE: Driver assigned packet ID type for txdone handler. | |
| 1365 | * WAITING_DMA_DONE_INT: TXD been filled with data | |
| 1366 | * and waiting for TxDoneISR housekeeping. | |
| 1367 | */ | |
| 1368 | #define TXD_W5_FRAME_OFFSET FIELD32(0x000000ff) | |
| 1369 | #define TXD_W5_PID_SUBTYPE FIELD32(0x00001f00) | |
| 1370 | #define TXD_W5_PID_TYPE FIELD32(0x0000e000) | |
| 1371 | #define TXD_W5_TX_POWER FIELD32(0x00ff0000) | |
| 1372 | #define TXD_W5_WAITING_DMA_DONE_INT FIELD32(0x01000000) | |
| 1373 | ||
| 1374 | /* | |
| 1375 | * the above 24-byte is called TXINFO and will be DMAed to MAC block | |
| 1376 | * through TXFIFO. MAC block use this TXINFO to control the transmission | |
| 1377 | * behavior of this frame. | |
| 1378 | * The following fields are not used by MAC block. | |
| 1379 | * They are used by DMA block and HOST driver only. | |
| 1380 | * Once a frame has been DMA to ASIC, all the following fields are useless | |
| 1381 | * to ASIC. | |
| 1382 | */ | |
| 1383 | ||
| 1384 | /* | |
| 1385 | * Word6-10: Buffer physical address | |
| 1386 | */ | |
| 1387 | #define TXD_W6_BUFFER_PHYSICAL_ADDRESS FIELD32(0xffffffff) | |
| 1388 | #define TXD_W7_BUFFER_PHYSICAL_ADDRESS FIELD32(0xffffffff) | |
| 1389 | #define TXD_W8_BUFFER_PHYSICAL_ADDRESS FIELD32(0xffffffff) | |
| 1390 | #define TXD_W9_BUFFER_PHYSICAL_ADDRESS FIELD32(0xffffffff) | |
| 1391 | #define TXD_W10_BUFFER_PHYSICAL_ADDRESS FIELD32(0xffffffff) | |
| 1392 | ||
| 1393 | /* | |
| 1394 | * Word11-13: Buffer length | |
| 1395 | */ | |
| 1396 | #define TXD_W11_BUFFER_LENGTH0 FIELD32(0x00000fff) | |
| 1397 | #define TXD_W11_BUFFER_LENGTH1 FIELD32(0x0fff0000) | |
| 1398 | #define TXD_W12_BUFFER_LENGTH2 FIELD32(0x00000fff) | |
| 1399 | #define TXD_W12_BUFFER_LENGTH3 FIELD32(0x0fff0000) | |
| 1400 | #define TXD_W13_BUFFER_LENGTH4 FIELD32(0x00000fff) | |
| 1401 | ||
| 1402 | /* | |
| 1403 | * Word14 | |
| 1404 | */ | |
| 1405 | #define TXD_W14_SK_BUFFER FIELD32(0xffffffff) | |
| 1406 | ||
| 1407 | /* | |
| 1408 | * Word15 | |
| 1409 | */ | |
| 1410 | #define TXD_W15_NEXT_SK_BUFFER FIELD32(0xffffffff) | |
| 1411 | ||
| 1412 | /* | |
| 1413 | * RX descriptor format for RX Ring. | |
| 1414 | */ | |
| 1415 | ||
| 1416 | /* | |
| 1417 | * Word0 | |
| 1418 | * CIPHER_ERROR: 1:ICV error, 2:MIC error, 3:invalid key. | |
| 1419 | * KEY_INDEX: Decryption key actually used. | |
| 1420 | */ | |
| 1421 | #define RXD_W0_OWNER_NIC FIELD32(0x00000001) | |
| 1422 | #define RXD_W0_DROP FIELD32(0x00000002) | |
| 1423 | #define RXD_W0_UNICAST_TO_ME FIELD32(0x00000004) | |
| 1424 | #define RXD_W0_MULTICAST FIELD32(0x00000008) | |
| 1425 | #define RXD_W0_BROADCAST FIELD32(0x00000010) | |
| 1426 | #define RXD_W0_MY_BSS FIELD32(0x00000020) | |
| 1427 | #define RXD_W0_CRC_ERROR FIELD32(0x00000040) | |
| 1428 | #define RXD_W0_OFDM FIELD32(0x00000080) | |
| 1429 | #define RXD_W0_CIPHER_ERROR FIELD32(0x00000300) | |
| 1430 | #define RXD_W0_KEY_INDEX FIELD32(0x0000fc00) | |
| 1431 | #define RXD_W0_DATABYTE_COUNT FIELD32(0x0fff0000) | |
| 1432 | #define RXD_W0_CIPHER_ALG FIELD32(0xe0000000) | |
| 1433 | ||
| 1434 | /* | |
| 1435 | * Word1 | |
| 1436 | * SIGNAL: RX raw data rate reported by BBP. | |
| 1437 | */ | |
| 1438 | #define RXD_W1_SIGNAL FIELD32(0x000000ff) | |
| 1439 | #define RXD_W1_RSSI_AGC FIELD32(0x00001f00) | |
| 1440 | #define RXD_W1_RSSI_LNA FIELD32(0x00006000) | |
| 1441 | #define RXD_W1_FRAME_OFFSET FIELD32(0x7f000000) | |
| 1442 | ||
| 1443 | /* | |
| 1444 | * Word2 | |
| 1445 | * IV: Received IV of originally encrypted. | |
| 1446 | */ | |
| 1447 | #define RXD_W2_IV FIELD32(0xffffffff) | |
| 1448 | ||
| 1449 | /* | |
| 1450 | * Word3 | |
| 1451 | * EIV: Received EIV of originally encrypted. | |
| 1452 | */ | |
| 1453 | #define RXD_W3_EIV FIELD32(0xffffffff) | |
| 1454 | ||
| 1455 | /* | |
| 1456 | * Word4 | |
| 61e754f4 ID |
1457 | * ICV: Received ICV of originally encrypted. |
| 1458 | * NOTE: This is a guess, the official definition is "reserved" | |
| 95ea3627 | 1459 | */ |
| 61e754f4 | 1460 | #define RXD_W4_ICV FIELD32(0xffffffff) |
| 95ea3627 ID |
1461 | |
| 1462 | /* | |
| 1463 | * the above 20-byte is called RXINFO and will be DMAed to MAC RX block | |
| 1464 | * and passed to the HOST driver. | |
| 1465 | * The following fields are for DMA block and HOST usage only. | |
| 1466 | * Can't be touched by ASIC MAC block. | |
| 1467 | */ | |
| 1468 | ||
| 1469 | /* | |
| 1470 | * Word5 | |
| 1471 | */ | |
| 1472 | #define RXD_W5_BUFFER_PHYSICAL_ADDRESS FIELD32(0xffffffff) | |
| 1473 | ||
| 1474 | /* | |
| 1475 | * Word6-15: Reserved | |
| 1476 | */ | |
| 1477 | #define RXD_W6_RESERVED FIELD32(0xffffffff) | |
| 1478 | #define RXD_W7_RESERVED FIELD32(0xffffffff) | |
| 1479 | #define RXD_W8_RESERVED FIELD32(0xffffffff) | |
| 1480 | #define RXD_W9_RESERVED FIELD32(0xffffffff) | |
| 1481 | #define RXD_W10_RESERVED FIELD32(0xffffffff) | |
| 1482 | #define RXD_W11_RESERVED FIELD32(0xffffffff) | |
| 1483 | #define RXD_W12_RESERVED FIELD32(0xffffffff) | |
| 1484 | #define RXD_W13_RESERVED FIELD32(0xffffffff) | |
| 1485 | #define RXD_W14_RESERVED FIELD32(0xffffffff) | |
| 1486 | #define RXD_W15_RESERVED FIELD32(0xffffffff) | |
| 1487 | ||
| 1488 | /* | |
| 49513481 | 1489 | * Macros for converting txpower from EEPROM to mac80211 value |
| de99ff82 | 1490 | * and from mac80211 value to register value. |
| 95ea3627 ID |
1491 | */ |
| 1492 | #define MIN_TXPOWER 0 | |
| 1493 | #define MAX_TXPOWER 31 | |
| 1494 | #define DEFAULT_TXPOWER 24 | |
| 1495 | ||
| 8c5e7a5f ID |
1496 | #define TXPOWER_FROM_DEV(__txpower) \ |
| 1497 | (((u8)(__txpower)) > MAX_TXPOWER) ? DEFAULT_TXPOWER : (__txpower) | |
| 1498 | ||
| 1499 | #define TXPOWER_TO_DEV(__txpower) \ | |
| 1500 | clamp_t(char, __txpower, MIN_TXPOWER, MAX_TXPOWER) | |
| 95ea3627 ID |
1501 | |
| 1502 | #endif /* RT61PCI_H */ |