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ath9k: correct warning about unintialized variable 'tid'
[deliverable/linux.git] / drivers / net / wireless / rt2x00 / rt61pci.h
CommitLineData
95ea3627 1/*
811aa9ca 2 Copyright (C) 2004 - 2008 rt2x00 SourceForge Project
95ea3627
ID		 3 <http://rt2x00.serialmonkey.com>
4
5 This program is free software; you can redistribute it and/or modify
6 it under the terms of the GNU General Public License as published by
7 the Free Software Foundation; either version 2 of the License, or
8 (at your option) any later version.
9
10 This program is distributed in the hope that it will be useful,
11 but WITHOUT ANY WARRANTY; without even the implied warranty of
12 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 GNU General Public License for more details.
14
15 You should have received a copy of the GNU General Public License
16 along with this program; if not, write to the
17 Free Software Foundation, Inc.,
18 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
19 */
20
21/*
22 Module: rt61pci
23 Abstract: Data structures and registers for the rt61pci module.
24 Supported chipsets: RT2561, RT2561s, RT2661.
25 */
26
27#ifndef RT61PCI_H
28#define RT61PCI_H
29
30/*
31 * RF chip defines.
32 */
33#define RF5225 0x0001
34#define RF5325 0x0002
35#define RF2527 0x0003
36#define RF2529 0x0004
37
38/*
39 * Signal information.
40 * Defaul offset is required for RSSI <-> dBm conversion.
41 */
95ea3627
ID		 42#define DEFAULT_RSSI_OFFSET 120
43
44/*
45 * Register layout information.
46 */
47#define CSR_REG_BASE 0x3000
48#define CSR_REG_SIZE 0x04b0
49#define EEPROM_BASE 0x0000
50#define EEPROM_SIZE 0x0100
51#define BBP_SIZE 0x0080
52#define RF_SIZE 0x0014
53
61448f88
GW		 54/*
55 * Number of TX queues.
56 */
57#define NUM_TX_QUEUES 4
58
95ea3627
ID		 59/*
60 * PCI registers.
61 */
62
63/*
64 * PCI Configuration Header
65 */
66#define PCI_CONFIG_HEADER_VENDOR 0x0000
67#define PCI_CONFIG_HEADER_DEVICE 0x0002
68
69/*
70 * HOST_CMD_CSR: For HOST to interrupt embedded processor
71 */
72#define HOST_CMD_CSR 0x0008
73#define HOST_CMD_CSR_HOST_COMMAND FIELD32(0x0000007f)
74#define HOST_CMD_CSR_INTERRUPT_MCU FIELD32(0x00000080)
75
76/*
77 * MCU_CNTL_CSR
78 * SELECT_BANK: Select 8051 program bank.
79 * RESET: Enable 8051 reset state.
80 * READY: Ready state for 8051.
81 */
82#define MCU_CNTL_CSR 0x000c
83#define MCU_CNTL_CSR_SELECT_BANK FIELD32(0x00000001)
84#define MCU_CNTL_CSR_RESET FIELD32(0x00000002)
85#define MCU_CNTL_CSR_READY FIELD32(0x00000004)
86
87/*
88 * SOFT_RESET_CSR
89 */
90#define SOFT_RESET_CSR 0x0010
91
92/*
93 * MCU_INT_SOURCE_CSR: MCU interrupt source/mask register.
94 */
95#define MCU_INT_SOURCE_CSR 0x0014
96#define MCU_INT_SOURCE_CSR_0 FIELD32(0x00000001)
97#define MCU_INT_SOURCE_CSR_1 FIELD32(0x00000002)
98#define MCU_INT_SOURCE_CSR_2 FIELD32(0x00000004)
99#define MCU_INT_SOURCE_CSR_3 FIELD32(0x00000008)
100#define MCU_INT_SOURCE_CSR_4 FIELD32(0x00000010)
101#define MCU_INT_SOURCE_CSR_5 FIELD32(0x00000020)
102#define MCU_INT_SOURCE_CSR_6 FIELD32(0x00000040)
103#define MCU_INT_SOURCE_CSR_7 FIELD32(0x00000080)
104#define MCU_INT_SOURCE_CSR_TWAKEUP FIELD32(0x00000100)
105#define MCU_INT_SOURCE_CSR_TBTT_EXPIRE FIELD32(0x00000200)
106
107/*
108 * MCU_INT_MASK_CSR: MCU interrupt source/mask register.
109 */
110#define MCU_INT_MASK_CSR 0x0018
111#define MCU_INT_MASK_CSR_0 FIELD32(0x00000001)
112#define MCU_INT_MASK_CSR_1 FIELD32(0x00000002)
113#define MCU_INT_MASK_CSR_2 FIELD32(0x00000004)
114#define MCU_INT_MASK_CSR_3 FIELD32(0x00000008)
115#define MCU_INT_MASK_CSR_4 FIELD32(0x00000010)
116#define MCU_INT_MASK_CSR_5 FIELD32(0x00000020)
117#define MCU_INT_MASK_CSR_6 FIELD32(0x00000040)
118#define MCU_INT_MASK_CSR_7 FIELD32(0x00000080)
119#define MCU_INT_MASK_CSR_TWAKEUP FIELD32(0x00000100)
120#define MCU_INT_MASK_CSR_TBTT_EXPIRE FIELD32(0x00000200)
121
122/*
123 * PCI_USEC_CSR
124 */
125#define PCI_USEC_CSR 0x001c
126
127/*
128 * Security key table memory.
129 * 16 entries 32-byte for shared key table
130 * 64 entries 32-byte for pairwise key table
131 * 64 entries 8-byte for pairwise ta key table
132 */
133#define SHARED_KEY_TABLE_BASE 0x1000
134#define PAIRWISE_KEY_TABLE_BASE 0x1200
135#define PAIRWISE_TA_TABLE_BASE 0x1a00
136
61e754f4
ID		 137#define SHARED_KEY_ENTRY(__idx) \
138 ( SHARED_KEY_TABLE_BASE + \
139 ((__idx) * sizeof(struct hw_key_entry)) )
140#define PAIRWISE_KEY_ENTRY(__idx) \
141 ( PAIRWISE_KEY_TABLE_BASE + \
142 ((__idx) * sizeof(struct hw_key_entry)) )
143#define PAIRWISE_TA_ENTRY(__idx) \
144 ( PAIRWISE_TA_TABLE_BASE + \
145 ((__idx) * sizeof(struct hw_pairwise_ta_entry)) )
146
95ea3627
ID		 147struct hw_key_entry {
148 u8 key[16];
149 u8 tx_mic[8];
150 u8 rx_mic[8];
151} __attribute__ ((packed));
152
153struct hw_pairwise_ta_entry {
154 u8 address[6];
61e754f4
ID		 155 u8 cipher;
156 u8 reserved;
95ea3627
ID		 157} __attribute__ ((packed));
158
159/*
160 * Other on-chip shared memory space.
161 */
162#define HW_CIS_BASE 0x2000
163#define HW_NULL_BASE 0x2b00
164
165/*
166 * Since NULL frame won't be that long (256 byte),
167 * We steal 16 tail bytes to save debugging settings.
168 */
169#define HW_DEBUG_SETTING_BASE 0x2bf0
170
171/*
172 * On-chip BEACON frame space.
173 */
174#define HW_BEACON_BASE0 0x2c00
175#define HW_BEACON_BASE1 0x2d00
176#define HW_BEACON_BASE2 0x2e00
177#define HW_BEACON_BASE3 0x2f00
6bb40dd1
ID		 178
179#define HW_BEACON_OFFSET(__index) \
180 ( HW_BEACON_BASE0 + (__index * 0x0100) )
95ea3627
ID		 181
182/*
183 * HOST-MCU shared memory.
184 */
185
186/*
187 * H2M_MAILBOX_CSR: Host-to-MCU Mailbox.
188 */
189#define H2M_MAILBOX_CSR 0x2100
190#define H2M_MAILBOX_CSR_ARG0 FIELD32(0x000000ff)
191#define H2M_MAILBOX_CSR_ARG1 FIELD32(0x0000ff00)
192#define H2M_MAILBOX_CSR_CMD_TOKEN FIELD32(0x00ff0000)
193#define H2M_MAILBOX_CSR_OWNER FIELD32(0xff000000)
194
195/*
196 * MCU_LEDCS: LED control for MCU Mailbox.
197 */
198#define MCU_LEDCS_LED_MODE FIELD16(0x001f)
199#define MCU_LEDCS_RADIO_STATUS FIELD16(0x0020)
200#define MCU_LEDCS_LINK_BG_STATUS FIELD16(0x0040)
201#define MCU_LEDCS_LINK_A_STATUS FIELD16(0x0080)
202#define MCU_LEDCS_POLARITY_GPIO_0 FIELD16(0x0100)
203#define MCU_LEDCS_POLARITY_GPIO_1 FIELD16(0x0200)
204#define MCU_LEDCS_POLARITY_GPIO_2 FIELD16(0x0400)
205#define MCU_LEDCS_POLARITY_GPIO_3 FIELD16(0x0800)
206#define MCU_LEDCS_POLARITY_GPIO_4 FIELD16(0x1000)
207#define MCU_LEDCS_POLARITY_ACT FIELD16(0x2000)
208#define MCU_LEDCS_POLARITY_READY_BG FIELD16(0x4000)
209#define MCU_LEDCS_POLARITY_READY_A FIELD16(0x8000)
210
211/*
212 * M2H_CMD_DONE_CSR.
213 */
214#define M2H_CMD_DONE_CSR 0x2104
215
216/*
217 * MCU_TXOP_ARRAY_BASE.
218 */
219#define MCU_TXOP_ARRAY_BASE 0x2110
220
221/*
222 * MAC Control/Status Registers(CSR).
223 * Some values are set in TU, whereas 1 TU == 1024 us.
224 */
225
226/*
227 * MAC_CSR0: ASIC revision number.
228 */
229#define MAC_CSR0 0x3000
230
231/*
232 * MAC_CSR1: System control register.
233 * SOFT_RESET: Software reset bit, 1: reset, 0: normal.
234 * BBP_RESET: Hardware reset BBP.
235 * HOST_READY: Host is ready after initialization, 1: ready.
236 */
237#define MAC_CSR1 0x3004
238#define MAC_CSR1_SOFT_RESET FIELD32(0x00000001)
239#define MAC_CSR1_BBP_RESET FIELD32(0x00000002)
240#define MAC_CSR1_HOST_READY FIELD32(0x00000004)
241
242/*
243 * MAC_CSR2: STA MAC register 0.
244 */
245#define MAC_CSR2 0x3008
246#define MAC_CSR2_BYTE0 FIELD32(0x000000ff)
247#define MAC_CSR2_BYTE1 FIELD32(0x0000ff00)
248#define MAC_CSR2_BYTE2 FIELD32(0x00ff0000)
249#define MAC_CSR2_BYTE3 FIELD32(0xff000000)
250
251/*
252 * MAC_CSR3: STA MAC register 1.
6bb40dd1
ID		 253 * UNICAST_TO_ME_MASK:
254 * Used to mask off bits from byte 5 of the MAC address
255 * to determine the UNICAST_TO_ME bit for RX frames.
256 * The full mask is complemented by BSS_ID_MASK:
257 * MASK = BSS_ID_MASK & UNICAST_TO_ME_MASK
95ea3627
ID		 258 */
259#define MAC_CSR3 0x300c
260#define MAC_CSR3_BYTE4 FIELD32(0x000000ff)
261#define MAC_CSR3_BYTE5 FIELD32(0x0000ff00)
262#define MAC_CSR3_UNICAST_TO_ME_MASK FIELD32(0x00ff0000)
263
264/*
265 * MAC_CSR4: BSSID register 0.
266 */
267#define MAC_CSR4 0x3010
268#define MAC_CSR4_BYTE0 FIELD32(0x000000ff)
269#define MAC_CSR4_BYTE1 FIELD32(0x0000ff00)
270#define MAC_CSR4_BYTE2 FIELD32(0x00ff0000)
271#define MAC_CSR4_BYTE3 FIELD32(0xff000000)
272
273/*
274 * MAC_CSR5: BSSID register 1.
6bb40dd1
ID		 275 * BSS_ID_MASK:
276 * This mask is used to mask off bits 0 and 1 of byte 5 of the
277 * BSSID. This will make sure that those bits will be ignored
278 * when determining the MY_BSS of RX frames.
279 * 0: 1-BSSID mode (BSS index = 0)
280 * 1: 2-BSSID mode (BSS index: Byte5, bit 0)
281 * 2: 2-BSSID mode (BSS index: byte5, bit 1)
282 * 3: 4-BSSID mode (BSS index: byte5, bit 0 - 1)
95ea3627
ID		 283 */
284#define MAC_CSR5 0x3014
285#define MAC_CSR5_BYTE4 FIELD32(0x000000ff)
286#define MAC_CSR5_BYTE5 FIELD32(0x0000ff00)
287#define MAC_CSR5_BSS_ID_MASK FIELD32(0x00ff0000)
288
289/*
290 * MAC_CSR6: Maximum frame length register.
291 */
292#define MAC_CSR6 0x3018
293#define MAC_CSR6_MAX_FRAME_UNIT FIELD32(0x00000fff)
294
295/*
296 * MAC_CSR7: Reserved
297 */
298#define MAC_CSR7 0x301c
299
300/*
301 * MAC_CSR8: SIFS/EIFS register.
302 * All units are in US.
303 */
304#define MAC_CSR8 0x3020
305#define MAC_CSR8_SIFS FIELD32(0x000000ff)
306#define MAC_CSR8_SIFS_AFTER_RX_OFDM FIELD32(0x0000ff00)
307#define MAC_CSR8_EIFS FIELD32(0xffff0000)
308
309/*
310 * MAC_CSR9: Back-Off control register.
311 * SLOT_TIME: Slot time, default is 20us for 802.11BG.
312 * CWMIN: Bit for Cwmin. default Cwmin is 31 (2^5 - 1).
313 * CWMAX: Bit for Cwmax, default Cwmax is 1023 (2^10 - 1).
314 * CW_SELECT: 1: CWmin/Cwmax select from register, 0:select from TxD.
315 */
316#define MAC_CSR9 0x3024
317#define MAC_CSR9_SLOT_TIME FIELD32(0x000000ff)
318#define MAC_CSR9_CWMIN FIELD32(0x00000f00)
319#define MAC_CSR9_CWMAX FIELD32(0x0000f000)
320#define MAC_CSR9_CW_SELECT FIELD32(0x00010000)
321
322/*
323 * MAC_CSR10: Power state configuration.
324 */
325#define MAC_CSR10 0x3028
326
327/*
328 * MAC_CSR11: Power saving transition time register.
329 * DELAY_AFTER_TBCN: Delay after Tbcn expired in units of TU.
330 * TBCN_BEFORE_WAKEUP: Number of beacon before wakeup.
331 * WAKEUP_LATENCY: In unit of TU.
332 */
333#define MAC_CSR11 0x302c
334#define MAC_CSR11_DELAY_AFTER_TBCN FIELD32(0x000000ff)
335#define MAC_CSR11_TBCN_BEFORE_WAKEUP FIELD32(0x00007f00)
336#define MAC_CSR11_AUTOWAKE FIELD32(0x00008000)
337#define MAC_CSR11_WAKEUP_LATENCY FIELD32(0x000f0000)
338
339/*
340 * MAC_CSR12: Manual power control / status register (merge CSR20 & PWRCSR1).
341 * CURRENT_STATE: 0:sleep, 1:awake.
342 * FORCE_WAKEUP: This has higher priority than PUT_TO_SLEEP.
343 * BBP_CURRENT_STATE: 0: BBP sleep, 1: BBP awake.
344 */
345#define MAC_CSR12 0x3030
346#define MAC_CSR12_CURRENT_STATE FIELD32(0x00000001)
347#define MAC_CSR12_PUT_TO_SLEEP FIELD32(0x00000002)
348#define MAC_CSR12_FORCE_WAKEUP FIELD32(0x00000004)
349#define MAC_CSR12_BBP_CURRENT_STATE FIELD32(0x00000008)
350
351/*
352 * MAC_CSR13: GPIO.
353 */
354#define MAC_CSR13 0x3034
355#define MAC_CSR13_BIT0 FIELD32(0x00000001)
356#define MAC_CSR13_BIT1 FIELD32(0x00000002)
357#define MAC_CSR13_BIT2 FIELD32(0x00000004)
358#define MAC_CSR13_BIT3 FIELD32(0x00000008)
359#define MAC_CSR13_BIT4 FIELD32(0x00000010)
360#define MAC_CSR13_BIT5 FIELD32(0x00000020)
361#define MAC_CSR13_BIT6 FIELD32(0x00000040)
362#define MAC_CSR13_BIT7 FIELD32(0x00000080)
363#define MAC_CSR13_BIT8 FIELD32(0x00000100)
364#define MAC_CSR13_BIT9 FIELD32(0x00000200)
365#define MAC_CSR13_BIT10 FIELD32(0x00000400)
366#define MAC_CSR13_BIT11 FIELD32(0x00000800)
367#define MAC_CSR13_BIT12 FIELD32(0x00001000)
368
369/*
370 * MAC_CSR14: LED control register.
371 * ON_PERIOD: On period, default 70ms.
372 * OFF_PERIOD: Off period, default 30ms.
373 * HW_LED: HW TX activity, 1: normal OFF, 0: normal ON.
374 * SW_LED: s/w LED, 1: ON, 0: OFF.
375 * HW_LED_POLARITY: 0: active low, 1: active high.
376 */
377#define MAC_CSR14 0x3038
378#define MAC_CSR14_ON_PERIOD FIELD32(0x000000ff)
379#define MAC_CSR14_OFF_PERIOD FIELD32(0x0000ff00)
380#define MAC_CSR14_HW_LED FIELD32(0x00010000)
381#define MAC_CSR14_SW_LED FIELD32(0x00020000)
382#define MAC_CSR14_HW_LED_POLARITY FIELD32(0x00040000)
383#define MAC_CSR14_SW_LED2 FIELD32(0x00080000)
384
385/*
386 * MAC_CSR15: NAV control.
387 */
388#define MAC_CSR15 0x303c
389
390/*
391 * TXRX control registers.
392 * Some values are set in TU, whereas 1 TU == 1024 us.
393 */
394
395/*
396 * TXRX_CSR0: TX/RX configuration register.
397 * TSF_OFFSET: Default is 24.
398 * AUTO_TX_SEQ: 1: ASIC auto replace sequence nr in outgoing frame.
399 * DISABLE_RX: Disable Rx engine.
400 * DROP_CRC: Drop CRC error.
401 * DROP_PHYSICAL: Drop physical error.
402 * DROP_CONTROL: Drop control frame.
403 * DROP_NOT_TO_ME: Drop not to me unicast frame.
404 * DROP_TO_DS: Drop fram ToDs bit is true.
405 * DROP_VERSION_ERROR: Drop version error frame.
406 * DROP_MULTICAST: Drop multicast frames.
407 * DROP_BORADCAST: Drop broadcast frames.
408 * ROP_ACK_CTS: Drop received ACK and CTS.
409 */
410#define TXRX_CSR0 0x3040
411#define TXRX_CSR0_RX_ACK_TIMEOUT FIELD32(0x000001ff)
412#define TXRX_CSR0_TSF_OFFSET FIELD32(0x00007e00)
413#define TXRX_CSR0_AUTO_TX_SEQ FIELD32(0x00008000)
414#define TXRX_CSR0_DISABLE_RX FIELD32(0x00010000)
415#define TXRX_CSR0_DROP_CRC FIELD32(0x00020000)
416#define TXRX_CSR0_DROP_PHYSICAL FIELD32(0x00040000)
417#define TXRX_CSR0_DROP_CONTROL FIELD32(0x00080000)
418#define TXRX_CSR0_DROP_NOT_TO_ME FIELD32(0x00100000)
419#define TXRX_CSR0_DROP_TO_DS FIELD32(0x00200000)
420#define TXRX_CSR0_DROP_VERSION_ERROR FIELD32(0x00400000)
421#define TXRX_CSR0_DROP_MULTICAST FIELD32(0x00800000)
e542239f 422#define TXRX_CSR0_DROP_BROADCAST FIELD32(0x01000000)
95ea3627
ID		 423#define TXRX_CSR0_DROP_ACK_CTS FIELD32(0x02000000)
424#define TXRX_CSR0_TX_WITHOUT_WAITING FIELD32(0x04000000)
425
426/*
427 * TXRX_CSR1
428 */
429#define TXRX_CSR1 0x3044
430#define TXRX_CSR1_BBP_ID0 FIELD32(0x0000007f)
431#define TXRX_CSR1_BBP_ID0_VALID FIELD32(0x00000080)
432#define TXRX_CSR1_BBP_ID1 FIELD32(0x00007f00)
433#define TXRX_CSR1_BBP_ID1_VALID FIELD32(0x00008000)
434#define TXRX_CSR1_BBP_ID2 FIELD32(0x007f0000)
435#define TXRX_CSR1_BBP_ID2_VALID FIELD32(0x00800000)
436#define TXRX_CSR1_BBP_ID3 FIELD32(0x7f000000)
437#define TXRX_CSR1_BBP_ID3_VALID FIELD32(0x80000000)
438
439/*
440 * TXRX_CSR2
441 */
442#define TXRX_CSR2 0x3048
443#define TXRX_CSR2_BBP_ID0 FIELD32(0x0000007f)
444#define TXRX_CSR2_BBP_ID0_VALID FIELD32(0x00000080)
445#define TXRX_CSR2_BBP_ID1 FIELD32(0x00007f00)
446#define TXRX_CSR2_BBP_ID1_VALID FIELD32(0x00008000)
447#define TXRX_CSR2_BBP_ID2 FIELD32(0x007f0000)
448#define TXRX_CSR2_BBP_ID2_VALID FIELD32(0x00800000)
449#define TXRX_CSR2_BBP_ID3 FIELD32(0x7f000000)
450#define TXRX_CSR2_BBP_ID3_VALID FIELD32(0x80000000)
451
452/*
453 * TXRX_CSR3
454 */
455#define TXRX_CSR3 0x304c
456#define TXRX_CSR3_BBP_ID0 FIELD32(0x0000007f)
457#define TXRX_CSR3_BBP_ID0_VALID FIELD32(0x00000080)
458#define TXRX_CSR3_BBP_ID1 FIELD32(0x00007f00)
459#define TXRX_CSR3_BBP_ID1_VALID FIELD32(0x00008000)
460#define TXRX_CSR3_BBP_ID2 FIELD32(0x007f0000)
461#define TXRX_CSR3_BBP_ID2_VALID FIELD32(0x00800000)
462#define TXRX_CSR3_BBP_ID3 FIELD32(0x7f000000)
463#define TXRX_CSR3_BBP_ID3_VALID FIELD32(0x80000000)
464
465/*
466 * TXRX_CSR4: Auto-Responder/Tx-retry register.
467 * AUTORESPOND_PREAMBLE: 0:long, 1:short preamble.
468 * OFDM_TX_RATE_DOWN: 1:enable.
469 * OFDM_TX_RATE_STEP: 0:1-step, 1: 2-step, 2:3-step, 3:4-step.
470 * OFDM_TX_FALLBACK_CCK: 0: Fallback to OFDM 6M only, 1: Fallback to CCK 1M,2M.
471 */
472#define TXRX_CSR4 0x3050
473#define TXRX_CSR4_TX_ACK_TIMEOUT FIELD32(0x000000ff)
474#define TXRX_CSR4_CNTL_ACK_POLICY FIELD32(0x00000700)
475#define TXRX_CSR4_ACK_CTS_PSM FIELD32(0x00010000)
476#define TXRX_CSR4_AUTORESPOND_ENABLE FIELD32(0x00020000)
477#define TXRX_CSR4_AUTORESPOND_PREAMBLE FIELD32(0x00040000)
478#define TXRX_CSR4_OFDM_TX_RATE_DOWN FIELD32(0x00080000)
479#define TXRX_CSR4_OFDM_TX_RATE_STEP FIELD32(0x00300000)
480#define TXRX_CSR4_OFDM_TX_FALLBACK_CCK FIELD32(0x00400000)
481#define TXRX_CSR4_LONG_RETRY_LIMIT FIELD32(0x0f000000)
482#define TXRX_CSR4_SHORT_RETRY_LIMIT FIELD32(0xf0000000)
483
484/*
485 * TXRX_CSR5
486 */
487#define TXRX_CSR5 0x3054
488
489/*
490 * TXRX_CSR6: ACK/CTS payload consumed time
491 */
492#define TXRX_CSR6 0x3058
493
494/*
495 * TXRX_CSR7: OFDM ACK/CTS payload consumed time for 6/9/12/18 mbps.
496 */
497#define TXRX_CSR7 0x305c
498#define TXRX_CSR7_ACK_CTS_6MBS FIELD32(0x000000ff)
499#define TXRX_CSR7_ACK_CTS_9MBS FIELD32(0x0000ff00)
500#define TXRX_CSR7_ACK_CTS_12MBS FIELD32(0x00ff0000)
501#define TXRX_CSR7_ACK_CTS_18MBS FIELD32(0xff000000)
502
503/*
504 * TXRX_CSR8: OFDM ACK/CTS payload consumed time for 24/36/48/54 mbps.
505 */
506#define TXRX_CSR8 0x3060
507#define TXRX_CSR8_ACK_CTS_24MBS FIELD32(0x000000ff)
508#define TXRX_CSR8_ACK_CTS_36MBS FIELD32(0x0000ff00)
509#define TXRX_CSR8_ACK_CTS_48MBS FIELD32(0x00ff0000)
510#define TXRX_CSR8_ACK_CTS_54MBS FIELD32(0xff000000)
511
512/*
513 * TXRX_CSR9: Synchronization control register.
514 * BEACON_INTERVAL: In unit of 1/16 TU.
515 * TSF_TICKING: Enable TSF auto counting.
516 * TSF_SYNC: Tsf sync, 0: disable, 1: infra, 2: ad-hoc/master mode.
517 * BEACON_GEN: Enable beacon generator.
518 */
519#define TXRX_CSR9 0x3064
520#define TXRX_CSR9_BEACON_INTERVAL FIELD32(0x0000ffff)
521#define TXRX_CSR9_TSF_TICKING FIELD32(0x00010000)
522#define TXRX_CSR9_TSF_SYNC FIELD32(0x00060000)
523#define TXRX_CSR9_TBTT_ENABLE FIELD32(0x00080000)
524#define TXRX_CSR9_BEACON_GEN FIELD32(0x00100000)
525#define TXRX_CSR9_TIMESTAMP_COMPENSATE FIELD32(0xff000000)
526
527/*
528 * TXRX_CSR10: BEACON alignment.
529 */
530#define TXRX_CSR10 0x3068
531
532/*
533 * TXRX_CSR11: AES mask.
534 */
535#define TXRX_CSR11 0x306c
536
537/*
538 * TXRX_CSR12: TSF low 32.
539 */
540#define TXRX_CSR12 0x3070
541#define TXRX_CSR12_LOW_TSFTIMER FIELD32(0xffffffff)
542
543/*
544 * TXRX_CSR13: TSF high 32.
545 */
546#define TXRX_CSR13 0x3074
547#define TXRX_CSR13_HIGH_TSFTIMER FIELD32(0xffffffff)
548
549/*
550 * TXRX_CSR14: TBTT timer.
551 */
552#define TXRX_CSR14 0x3078
553
554/*
555 * TXRX_CSR15: TKIP MIC priority byte "AND" mask.
556 */
557#define TXRX_CSR15 0x307c
558
559/*
560 * PHY control registers.
561 * Some values are set in TU, whereas 1 TU == 1024 us.
562 */
563
564/*
565 * PHY_CSR0: RF/PS control.
566 */
567#define PHY_CSR0 0x3080
568#define PHY_CSR0_PA_PE_BG FIELD32(0x00010000)
569#define PHY_CSR0_PA_PE_A FIELD32(0x00020000)
570
571/*
572 * PHY_CSR1
573 */
574#define PHY_CSR1 0x3084
575
576/*
577 * PHY_CSR2: Pre-TX BBP control.
578 */
579#define PHY_CSR2 0x3088
580
581/*
582 * PHY_CSR3: BBP serial control register.
583 * VALUE: Register value to program into BBP.
584 * REG_NUM: Selected BBP register.
585 * READ_CONTROL: 0: Write BBP, 1: Read BBP.
586 * BUSY: 1: ASIC is busy execute BBP programming.
587 */
588#define PHY_CSR3 0x308c
589#define PHY_CSR3_VALUE FIELD32(0x000000ff)
590#define PHY_CSR3_REGNUM FIELD32(0x00007f00)
591#define PHY_CSR3_READ_CONTROL FIELD32(0x00008000)
592#define PHY_CSR3_BUSY FIELD32(0x00010000)
593
594/*
595 * PHY_CSR4: RF serial control register
596 * VALUE: Register value (include register id) serial out to RF/IF chip.
597 * NUMBER_OF_BITS: Number of bits used in RFRegValue (I:20, RFMD:22).
598 * IF_SELECT: 1: select IF to program, 0: select RF to program.
599 * PLL_LD: RF PLL_LD status.
600 * BUSY: 1: ASIC is busy execute RF programming.
601 */
602#define PHY_CSR4 0x3090
603#define PHY_CSR4_VALUE FIELD32(0x00ffffff)
604#define PHY_CSR4_NUMBER_OF_BITS FIELD32(0x1f000000)
605#define PHY_CSR4_IF_SELECT FIELD32(0x20000000)
606#define PHY_CSR4_PLL_LD FIELD32(0x40000000)
607#define PHY_CSR4_BUSY FIELD32(0x80000000)
608
609/*
610 * PHY_CSR5: RX to TX signal switch timing control.
611 */
612#define PHY_CSR5 0x3094
613#define PHY_CSR5_IQ_FLIP FIELD32(0x00000004)
614
615/*
616 * PHY_CSR6: TX to RX signal timing control.
617 */
618#define PHY_CSR6 0x3098
619#define PHY_CSR6_IQ_FLIP FIELD32(0x00000004)
620
621/*
622 * PHY_CSR7: TX DAC switching timing control.
623 */
624#define PHY_CSR7 0x309c
625
626/*
627 * Security control register.
628 */
629
630/*
631 * SEC_CSR0: Shared key table control.
632 */
633#define SEC_CSR0 0x30a0
634#define SEC_CSR0_BSS0_KEY0_VALID FIELD32(0x00000001)
635#define SEC_CSR0_BSS0_KEY1_VALID FIELD32(0x00000002)
636#define SEC_CSR0_BSS0_KEY2_VALID FIELD32(0x00000004)
637#define SEC_CSR0_BSS0_KEY3_VALID FIELD32(0x00000008)
638#define SEC_CSR0_BSS1_KEY0_VALID FIELD32(0x00000010)
639#define SEC_CSR0_BSS1_KEY1_VALID FIELD32(0x00000020)
640#define SEC_CSR0_BSS1_KEY2_VALID FIELD32(0x00000040)
641#define SEC_CSR0_BSS1_KEY3_VALID FIELD32(0x00000080)
642#define SEC_CSR0_BSS2_KEY0_VALID FIELD32(0x00000100)
643#define SEC_CSR0_BSS2_KEY1_VALID FIELD32(0x00000200)
644#define SEC_CSR0_BSS2_KEY2_VALID FIELD32(0x00000400)
645#define SEC_CSR0_BSS2_KEY3_VALID FIELD32(0x00000800)
646#define SEC_CSR0_BSS3_KEY0_VALID FIELD32(0x00001000)
647#define SEC_CSR0_BSS3_KEY1_VALID FIELD32(0x00002000)
648#define SEC_CSR0_BSS3_KEY2_VALID FIELD32(0x00004000)
649#define SEC_CSR0_BSS3_KEY3_VALID FIELD32(0x00008000)
650
651/*
652 * SEC_CSR1: Shared key table security mode register.
653 */
654#define SEC_CSR1 0x30a4
655#define SEC_CSR1_BSS0_KEY0_CIPHER_ALG FIELD32(0x00000007)
656#define SEC_CSR1_BSS0_KEY1_CIPHER_ALG FIELD32(0x00000070)
657#define SEC_CSR1_BSS0_KEY2_CIPHER_ALG FIELD32(0x00000700)
658#define SEC_CSR1_BSS0_KEY3_CIPHER_ALG FIELD32(0x00007000)
659#define SEC_CSR1_BSS1_KEY0_CIPHER_ALG FIELD32(0x00070000)
660#define SEC_CSR1_BSS1_KEY1_CIPHER_ALG FIELD32(0x00700000)
661#define SEC_CSR1_BSS1_KEY2_CIPHER_ALG FIELD32(0x07000000)
662#define SEC_CSR1_BSS1_KEY3_CIPHER_ALG FIELD32(0x70000000)
663
664/*
665 * Pairwise key table valid bitmap registers.
666 * SEC_CSR2: pairwise key table valid bitmap 0.
667 * SEC_CSR3: pairwise key table valid bitmap 1.
668 */
669#define SEC_CSR2 0x30a8
670#define SEC_CSR3 0x30ac
671
672/*
673 * SEC_CSR4: Pairwise key table lookup control.
674 */
675#define SEC_CSR4 0x30b0
61e754f4
ID		 676#define SEC_CSR4_ENABLE_BSS0 FIELD32(0x00000001)
677#define SEC_CSR4_ENABLE_BSS1 FIELD32(0x00000002)
678#define SEC_CSR4_ENABLE_BSS2 FIELD32(0x00000004)
679#define SEC_CSR4_ENABLE_BSS3 FIELD32(0x00000008)
95ea3627
ID		 680
681/*
682 * SEC_CSR5: shared key table security mode register.
683 */
684#define SEC_CSR5 0x30b4
685#define SEC_CSR5_BSS2_KEY0_CIPHER_ALG FIELD32(0x00000007)
686#define SEC_CSR5_BSS2_KEY1_CIPHER_ALG FIELD32(0x00000070)
687#define SEC_CSR5_BSS2_KEY2_CIPHER_ALG FIELD32(0x00000700)
688#define SEC_CSR5_BSS2_KEY3_CIPHER_ALG FIELD32(0x00007000)
689#define SEC_CSR5_BSS3_KEY0_CIPHER_ALG FIELD32(0x00070000)
690#define SEC_CSR5_BSS3_KEY1_CIPHER_ALG FIELD32(0x00700000)
691#define SEC_CSR5_BSS3_KEY2_CIPHER_ALG FIELD32(0x07000000)
692#define SEC_CSR5_BSS3_KEY3_CIPHER_ALG FIELD32(0x70000000)
693
694/*
695 * STA control registers.
696 */
697
698/*
699 * STA_CSR0: RX PLCP error count & RX FCS error count.
700 */
701#define STA_CSR0 0x30c0
702#define STA_CSR0_FCS_ERROR FIELD32(0x0000ffff)
703#define STA_CSR0_PLCP_ERROR FIELD32(0xffff0000)
704
705/*
706 * STA_CSR1: RX False CCA count & RX LONG frame count.
707 */
708#define STA_CSR1 0x30c4
709#define STA_CSR1_PHYSICAL_ERROR FIELD32(0x0000ffff)
710#define STA_CSR1_FALSE_CCA_ERROR FIELD32(0xffff0000)
711
712/*
713 * STA_CSR2: TX Beacon count and RX FIFO overflow count.
714 */
715#define STA_CSR2 0x30c8
716#define STA_CSR2_RX_FIFO_OVERFLOW_COUNT FIELD32(0x0000ffff)
717#define STA_CSR2_RX_OVERFLOW_COUNT FIELD32(0xffff0000)
718
719/*
720 * STA_CSR3: TX Beacon count.
721 */
722#define STA_CSR3 0x30cc
723#define STA_CSR3_TX_BEACON_COUNT FIELD32(0x0000ffff)
724
725/*
726 * STA_CSR4: TX Result status register.
727 * VALID: 1:This register contains a valid TX result.
728 */
729#define STA_CSR4 0x30d0
730#define STA_CSR4_VALID FIELD32(0x00000001)
731#define STA_CSR4_TX_RESULT FIELD32(0x0000000e)
732#define STA_CSR4_RETRY_COUNT FIELD32(0x000000f0)
733#define STA_CSR4_PID_SUBTYPE FIELD32(0x00001f00)
734#define STA_CSR4_PID_TYPE FIELD32(0x0000e000)
735#define STA_CSR4_TXRATE FIELD32(0x000f0000)
736
737/*
738 * QOS control registers.
739 */
740
741/*
742 * QOS_CSR0: TXOP holder MAC address register.
743 */
744#define QOS_CSR0 0x30e0
745#define QOS_CSR0_BYTE0 FIELD32(0x000000ff)
746#define QOS_CSR0_BYTE1 FIELD32(0x0000ff00)
747#define QOS_CSR0_BYTE2 FIELD32(0x00ff0000)
748#define QOS_CSR0_BYTE3 FIELD32(0xff000000)
749
750/*
751 * QOS_CSR1: TXOP holder MAC address register.
752 */
753#define QOS_CSR1 0x30e4
754#define QOS_CSR1_BYTE4 FIELD32(0x000000ff)
755#define QOS_CSR1_BYTE5 FIELD32(0x0000ff00)
756
757/*
758 * QOS_CSR2: TXOP holder timeout register.
759 */
760#define QOS_CSR2 0x30e8
761
762/*
763 * RX QOS-CFPOLL MAC address register.
764 * QOS_CSR3: RX QOS-CFPOLL MAC address 0.
765 * QOS_CSR4: RX QOS-CFPOLL MAC address 1.
766 */
767#define QOS_CSR3 0x30ec
768#define QOS_CSR4 0x30f0
769
770/*
771 * QOS_CSR5: "QosControl" field of the RX QOS-CFPOLL.
772 */
773#define QOS_CSR5 0x30f4
774
775/*
776 * Host DMA registers.
777 */
778
779/*
780 * AC0_BASE_CSR: AC_BK base address.
781 */
782#define AC0_BASE_CSR 0x3400
783#define AC0_BASE_CSR_RING_REGISTER FIELD32(0xffffffff)
784
785/*
786 * AC1_BASE_CSR: AC_BE base address.
787 */
788#define AC1_BASE_CSR 0x3404
789#define AC1_BASE_CSR_RING_REGISTER FIELD32(0xffffffff)
790
791/*
792 * AC2_BASE_CSR: AC_VI base address.
793 */
794#define AC2_BASE_CSR 0x3408
795#define AC2_BASE_CSR_RING_REGISTER FIELD32(0xffffffff)
796
797/*
798 * AC3_BASE_CSR: AC_VO base address.
799 */
800#define AC3_BASE_CSR 0x340c
801#define AC3_BASE_CSR_RING_REGISTER FIELD32(0xffffffff)
802
803/*
804 * MGMT_BASE_CSR: MGMT ring base address.
805 */
806#define MGMT_BASE_CSR 0x3410
807#define MGMT_BASE_CSR_RING_REGISTER FIELD32(0xffffffff)
808
809/*
810 * TX_RING_CSR0: TX Ring size for AC_BK, AC_BE, AC_VI, AC_VO.
811 */
812#define TX_RING_CSR0 0x3418
813#define TX_RING_CSR0_AC0_RING_SIZE FIELD32(0x000000ff)
814#define TX_RING_CSR0_AC1_RING_SIZE FIELD32(0x0000ff00)
815#define TX_RING_CSR0_AC2_RING_SIZE FIELD32(0x00ff0000)
816#define TX_RING_CSR0_AC3_RING_SIZE FIELD32(0xff000000)
817
818/*
819 * TX_RING_CSR1: TX Ring size for MGMT Ring, HCCA Ring
820 * TXD_SIZE: In unit of 32-bit.
821 */
822#define TX_RING_CSR1 0x341c
823#define TX_RING_CSR1_MGMT_RING_SIZE FIELD32(0x000000ff)
824#define TX_RING_CSR1_HCCA_RING_SIZE FIELD32(0x0000ff00)
825#define TX_RING_CSR1_TXD_SIZE FIELD32(0x003f0000)
826
827/*
828 * AIFSN_CSR: AIFSN for each EDCA AC.
829 * AIFSN0: For AC_BK.
830 * AIFSN1: For AC_BE.
831 * AIFSN2: For AC_VI.
832 * AIFSN3: For AC_VO.
833 */
834#define AIFSN_CSR 0x3420
835#define AIFSN_CSR_AIFSN0 FIELD32(0x0000000f)
836#define AIFSN_CSR_AIFSN1 FIELD32(0x000000f0)
837#define AIFSN_CSR_AIFSN2 FIELD32(0x00000f00)
838#define AIFSN_CSR_AIFSN3 FIELD32(0x0000f000)
839
840/*
841 * CWMIN_CSR: CWmin for each EDCA AC.
842 * CWMIN0: For AC_BK.
843 * CWMIN1: For AC_BE.
844 * CWMIN2: For AC_VI.
845 * CWMIN3: For AC_VO.
846 */
847#define CWMIN_CSR 0x3424
848#define CWMIN_CSR_CWMIN0 FIELD32(0x0000000f)
849#define CWMIN_CSR_CWMIN1 FIELD32(0x000000f0)
850#define CWMIN_CSR_CWMIN2 FIELD32(0x00000f00)
851#define CWMIN_CSR_CWMIN3 FIELD32(0x0000f000)
852
853/*
854 * CWMAX_CSR: CWmax for each EDCA AC.
855 * CWMAX0: For AC_BK.
856 * CWMAX1: For AC_BE.
857 * CWMAX2: For AC_VI.
858 * CWMAX3: For AC_VO.
859 */
860#define CWMAX_CSR 0x3428
861#define CWMAX_CSR_CWMAX0 FIELD32(0x0000000f)
862#define CWMAX_CSR_CWMAX1 FIELD32(0x000000f0)
863#define CWMAX_CSR_CWMAX2 FIELD32(0x00000f00)
864#define CWMAX_CSR_CWMAX3 FIELD32(0x0000f000)
865
866/*
867 * TX_DMA_DST_CSR: TX DMA destination
868 * 0: TX ring0, 1: TX ring1, 2: TX ring2 3: invalid
869 */
870#define TX_DMA_DST_CSR 0x342c
871#define TX_DMA_DST_CSR_DEST_AC0 FIELD32(0x00000003)
872#define TX_DMA_DST_CSR_DEST_AC1 FIELD32(0x0000000c)
873#define TX_DMA_DST_CSR_DEST_AC2 FIELD32(0x00000030)
874#define TX_DMA_DST_CSR_DEST_AC3 FIELD32(0x000000c0)
875#define TX_DMA_DST_CSR_DEST_MGMT FIELD32(0x00000300)
876
877/*
878 * TX_CNTL_CSR: KICK/Abort TX.
879 * KICK_TX_AC0: For AC_BK.
880 * KICK_TX_AC1: For AC_BE.
881 * KICK_TX_AC2: For AC_VI.
882 * KICK_TX_AC3: For AC_VO.
883 * ABORT_TX_AC0: For AC_BK.
884 * ABORT_TX_AC1: For AC_BE.
885 * ABORT_TX_AC2: For AC_VI.
886 * ABORT_TX_AC3: For AC_VO.
887 */
888#define TX_CNTL_CSR 0x3430
889#define TX_CNTL_CSR_KICK_TX_AC0 FIELD32(0x00000001)
890#define TX_CNTL_CSR_KICK_TX_AC1 FIELD32(0x00000002)
891#define TX_CNTL_CSR_KICK_TX_AC2 FIELD32(0x00000004)
892#define TX_CNTL_CSR_KICK_TX_AC3 FIELD32(0x00000008)
893#define TX_CNTL_CSR_KICK_TX_MGMT FIELD32(0x00000010)
894#define TX_CNTL_CSR_ABORT_TX_AC0 FIELD32(0x00010000)
895#define TX_CNTL_CSR_ABORT_TX_AC1 FIELD32(0x00020000)
896#define TX_CNTL_CSR_ABORT_TX_AC2 FIELD32(0x00040000)
897#define TX_CNTL_CSR_ABORT_TX_AC3 FIELD32(0x00080000)
898#define TX_CNTL_CSR_ABORT_TX_MGMT FIELD32(0x00100000)
899
900/*
16938a24 901 * LOAD_TX_RING_CSR: Load RX desriptor
95ea3627
ID		 902 */
903#define LOAD_TX_RING_CSR 0x3434
904#define LOAD_TX_RING_CSR_LOAD_TXD_AC0 FIELD32(0x00000001)
905#define LOAD_TX_RING_CSR_LOAD_TXD_AC1 FIELD32(0x00000002)
906#define LOAD_TX_RING_CSR_LOAD_TXD_AC2 FIELD32(0x00000004)
907#define LOAD_TX_RING_CSR_LOAD_TXD_AC3 FIELD32(0x00000008)
908#define LOAD_TX_RING_CSR_LOAD_TXD_MGMT FIELD32(0x00000010)
909
910/*
911 * Several read-only registers, for debugging.
912 */
913#define AC0_TXPTR_CSR 0x3438
914#define AC1_TXPTR_CSR 0x343c
915#define AC2_TXPTR_CSR 0x3440
916#define AC3_TXPTR_CSR 0x3444
917#define MGMT_TXPTR_CSR 0x3448
918
919/*
920 * RX_BASE_CSR
921 */
922#define RX_BASE_CSR 0x3450
923#define RX_BASE_CSR_RING_REGISTER FIELD32(0xffffffff)
924
925/*
926 * RX_RING_CSR.
927 * RXD_SIZE: In unit of 32-bit.
928 */
929#define RX_RING_CSR 0x3454
930#define RX_RING_CSR_RING_SIZE FIELD32(0x000000ff)
931#define RX_RING_CSR_RXD_SIZE FIELD32(0x00003f00)
932#define RX_RING_CSR_RXD_WRITEBACK_SIZE FIELD32(0x00070000)
933
934/*
935 * RX_CNTL_CSR
936 */
937#define RX_CNTL_CSR 0x3458
938#define RX_CNTL_CSR_ENABLE_RX_DMA FIELD32(0x00000001)
939#define RX_CNTL_CSR_LOAD_RXD FIELD32(0x00000002)
940
941/*
942 * RXPTR_CSR: Read-only, for debugging.
943 */
944#define RXPTR_CSR 0x345c
945
946/*
947 * PCI_CFG_CSR
948 */
949#define PCI_CFG_CSR 0x3460
950
951/*
952 * BUF_FORMAT_CSR
953 */
954#define BUF_FORMAT_CSR 0x3464
955
956/*
957 * INT_SOURCE_CSR: Interrupt source register.
958 * Write one to clear corresponding bit.
959 */
960#define INT_SOURCE_CSR 0x3468
961#define INT_SOURCE_CSR_TXDONE FIELD32(0x00000001)
962#define INT_SOURCE_CSR_RXDONE FIELD32(0x00000002)
963#define INT_SOURCE_CSR_BEACON_DONE FIELD32(0x00000004)
964#define INT_SOURCE_CSR_TX_ABORT_DONE FIELD32(0x00000010)
965#define INT_SOURCE_CSR_AC0_DMA_DONE FIELD32(0x00010000)
966#define INT_SOURCE_CSR_AC1_DMA_DONE FIELD32(0x00020000)
967#define INT_SOURCE_CSR_AC2_DMA_DONE FIELD32(0x00040000)
968#define INT_SOURCE_CSR_AC3_DMA_DONE FIELD32(0x00080000)
969#define INT_SOURCE_CSR_MGMT_DMA_DONE FIELD32(0x00100000)
970#define INT_SOURCE_CSR_HCCA_DMA_DONE FIELD32(0x00200000)
971
972/*
973 * INT_MASK_CSR: Interrupt MASK register. 1: the interrupt is mask OFF.
974 * MITIGATION_PERIOD: Interrupt mitigation in unit of 32 PCI clock.
975 */
976#define INT_MASK_CSR 0x346c
977#define INT_MASK_CSR_TXDONE FIELD32(0x00000001)
978#define INT_MASK_CSR_RXDONE FIELD32(0x00000002)
979#define INT_MASK_CSR_BEACON_DONE FIELD32(0x00000004)
980#define INT_MASK_CSR_TX_ABORT_DONE FIELD32(0x00000010)
981#define INT_MASK_CSR_ENABLE_MITIGATION FIELD32(0x00000080)
982#define INT_MASK_CSR_MITIGATION_PERIOD FIELD32(0x0000ff00)
983#define INT_MASK_CSR_AC0_DMA_DONE FIELD32(0x00010000)
984#define INT_MASK_CSR_AC1_DMA_DONE FIELD32(0x00020000)
985#define INT_MASK_CSR_AC2_DMA_DONE FIELD32(0x00040000)
986#define INT_MASK_CSR_AC3_DMA_DONE FIELD32(0x00080000)
987#define INT_MASK_CSR_MGMT_DMA_DONE FIELD32(0x00100000)
988#define INT_MASK_CSR_HCCA_DMA_DONE FIELD32(0x00200000)
989
990/*
991 * E2PROM_CSR: EEPROM control register.
992 * RELOAD: Write 1 to reload eeprom content.
993 * TYPE_93C46: 1: 93c46, 0:93c66.
994 * LOAD_STATUS: 1:loading, 0:done.
995 */
996#define E2PROM_CSR 0x3470
997#define E2PROM_CSR_RELOAD FIELD32(0x00000001)
998#define E2PROM_CSR_DATA_CLOCK FIELD32(0x00000002)
999#define E2PROM_CSR_CHIP_SELECT FIELD32(0x00000004)
1000#define E2PROM_CSR_DATA_IN FIELD32(0x00000008)
1001#define E2PROM_CSR_DATA_OUT FIELD32(0x00000010)
1002#define E2PROM_CSR_TYPE_93C46 FIELD32(0x00000020)
1003#define E2PROM_CSR_LOAD_STATUS FIELD32(0x00000040)
1004
1005/*
1006 * AC_TXOP_CSR0: AC_BK/AC_BE TXOP register.
1007 * AC0_TX_OP: For AC_BK, in unit of 32us.
1008 * AC1_TX_OP: For AC_BE, in unit of 32us.
1009 */
1010#define AC_TXOP_CSR0 0x3474
1011#define AC_TXOP_CSR0_AC0_TX_OP FIELD32(0x0000ffff)
1012#define AC_TXOP_CSR0_AC1_TX_OP FIELD32(0xffff0000)
1013
1014/*
1015 * AC_TXOP_CSR1: AC_VO/AC_VI TXOP register.
1016 * AC2_TX_OP: For AC_VI, in unit of 32us.
1017 * AC3_TX_OP: For AC_VO, in unit of 32us.
1018 */
1019#define AC_TXOP_CSR1 0x3478
1020#define AC_TXOP_CSR1_AC2_TX_OP FIELD32(0x0000ffff)
1021#define AC_TXOP_CSR1_AC3_TX_OP FIELD32(0xffff0000)
1022
1023/*
1024 * DMA_STATUS_CSR
1025 */
1026#define DMA_STATUS_CSR 0x3480
1027
1028/*
1029 * TEST_MODE_CSR
1030 */
1031#define TEST_MODE_CSR 0x3484
1032
1033/*
1034 * UART0_TX_CSR
1035 */
1036#define UART0_TX_CSR 0x3488
1037
1038/*
1039 * UART0_RX_CSR
1040 */
1041#define UART0_RX_CSR 0x348c
1042
1043/*
1044 * UART0_FRAME_CSR
1045 */
1046#define UART0_FRAME_CSR 0x3490
1047
1048/*
1049 * UART0_BUFFER_CSR
1050 */
1051#define UART0_BUFFER_CSR 0x3494
1052
1053/*
1054 * IO_CNTL_CSR
1055 */
1056#define IO_CNTL_CSR 0x3498
1057
1058/*
1059 * UART_INT_SOURCE_CSR
1060 */
1061#define UART_INT_SOURCE_CSR 0x34a8
1062
1063/*
1064 * UART_INT_MASK_CSR
1065 */
1066#define UART_INT_MASK_CSR 0x34ac
1067
1068/*
1069 * PBF_QUEUE_CSR
1070 */
1071#define PBF_QUEUE_CSR 0x34b0
1072
1073/*
1074 * Firmware DMA registers.
1075 * Firmware DMA registers are dedicated for MCU usage
1076 * and should not be touched by host driver.
1077 * Therefore we skip the definition of these registers.
1078 */
1079#define FW_TX_BASE_CSR 0x34c0
1080#define FW_TX_START_CSR 0x34c4
1081#define FW_TX_LAST_CSR 0x34c8
1082#define FW_MODE_CNTL_CSR 0x34cc
1083#define FW_TXPTR_CSR 0x34d0
1084
1085/*
1086 * 8051 firmware image.
1087 */
1088#define FIRMWARE_RT2561 "rt2561.bin"
1089#define FIRMWARE_RT2561s "rt2561s.bin"
1090#define FIRMWARE_RT2661 "rt2661.bin"
1091#define FIRMWARE_IMAGE_BASE 0x4000
1092
1093/*
1094 * BBP registers.
1095 * The wordsize of the BBP is 8 bits.
1096 */
1097
1098/*
1099 * R2
1100 */
1101#define BBP_R2_BG_MODE FIELD8(0x20)
1102
1103/*
1104 * R3
1105 */
1106#define BBP_R3_SMART_MODE FIELD8(0x01)
1107
1108/*
1109 * R4: RX antenna control
1110 * FRAME_END: 1 - DPDT, 0 - SPDT (Only valid for 802.11G, RF2527 & RF2529)
1111 */
acaa410d
MN		 1112
1113/*
1114 * ANTENNA_CONTROL semantics (guessed):
1115 * 0x1: Software controlled antenna switching (fixed or SW diversity)
1116 * 0x2: Hardware diversity.
1117 */
1118#define BBP_R4_RX_ANTENNA_CONTROL FIELD8(0x03)
95ea3627
ID		 1119#define BBP_R4_RX_FRAME_END FIELD8(0x20)
1120
1121/*
1122 * R77
1123 */
acaa410d 1124#define BBP_R77_RX_ANTENNA FIELD8(0x03)
95ea3627
ID		 1125
1126/*
1127 * RF registers
1128 */
1129
1130/*
1131 * RF 3
1132 */
1133#define RF3_TXPOWER FIELD32(0x00003e00)
1134
1135/*
1136 * RF 4
1137 */
1138#define RF4_FREQ_OFFSET FIELD32(0x0003f000)
1139
1140/*
1141 * EEPROM content.
1142 * The wordsize of the EEPROM is 16 bits.
1143 */
1144
1145/*
1146 * HW MAC address.
1147 */
1148#define EEPROM_MAC_ADDR_0 0x0002
1149#define EEPROM_MAC_ADDR_BYTE0 FIELD16(0x00ff)
1150#define EEPROM_MAC_ADDR_BYTE1 FIELD16(0xff00)
ce359f90 1151#define EEPROM_MAC_ADDR1 0x0003
95ea3627
ID		 1152#define EEPROM_MAC_ADDR_BYTE2 FIELD16(0x00ff)
1153#define EEPROM_MAC_ADDR_BYTE3 FIELD16(0xff00)
ce359f90 1154#define EEPROM_MAC_ADDR_2 0x0004
95ea3627
ID		 1155#define EEPROM_MAC_ADDR_BYTE4 FIELD16(0x00ff)
1156#define EEPROM_MAC_ADDR_BYTE5 FIELD16(0xff00)
1157
1158/*
1159 * EEPROM antenna.
1160 * ANTENNA_NUM: Number of antenna's.
1161 * TX_DEFAULT: Default antenna 0: diversity, 1: A, 2: B.
1162 * RX_DEFAULT: Default antenna 0: diversity, 1: A, 2: B.
1163 * FRAME_TYPE: 0: DPDT , 1: SPDT , noted this bit is valid for g only.
1164 * DYN_TXAGC: Dynamic TX AGC control.
1165 * HARDWARE_RADIO: 1: Hardware controlled radio. Read GPIO0.
1166 * RF_TYPE: Rf_type of this adapter.
1167 */
1168#define EEPROM_ANTENNA 0x0010
1169#define EEPROM_ANTENNA_NUM FIELD16(0x0003)
1170#define EEPROM_ANTENNA_TX_DEFAULT FIELD16(0x000c)
1171#define EEPROM_ANTENNA_RX_DEFAULT FIELD16(0x0030)
1172#define EEPROM_ANTENNA_FRAME_TYPE FIELD16(0x0040)
1173#define EEPROM_ANTENNA_DYN_TXAGC FIELD16(0x0200)
1174#define EEPROM_ANTENNA_HARDWARE_RADIO FIELD16(0x0400)
1175#define EEPROM_ANTENNA_RF_TYPE FIELD16(0xf800)
1176
1177/*
1178 * EEPROM NIC config.
1179 * ENABLE_DIVERSITY: 1:enable, 0:disable.
1180 * EXTERNAL_LNA_BG: External LNA enable for 2.4G.
1181 * CARDBUS_ACCEL: 0:enable, 1:disable.
1182 * EXTERNAL_LNA_A: External LNA enable for 5G.
1183 */
1184#define EEPROM_NIC 0x0011
1185#define EEPROM_NIC_ENABLE_DIVERSITY FIELD16(0x0001)
1186#define EEPROM_NIC_TX_DIVERSITY FIELD16(0x0002)
1187#define EEPROM_NIC_TX_RX_FIXED FIELD16(0x000c)
1188#define EEPROM_NIC_EXTERNAL_LNA_BG FIELD16(0x0010)
1189#define EEPROM_NIC_CARDBUS_ACCEL FIELD16(0x0020)
1190#define EEPROM_NIC_EXTERNAL_LNA_A FIELD16(0x0040)
1191
1192/*
1193 * EEPROM geography.
1194 * GEO_A: Default geographical setting for 5GHz band
1195 * GEO: Default geographical setting.
1196 */
1197#define EEPROM_GEOGRAPHY 0x0012
1198#define EEPROM_GEOGRAPHY_GEO_A FIELD16(0x00ff)
1199#define EEPROM_GEOGRAPHY_GEO FIELD16(0xff00)
1200
1201/*
1202 * EEPROM BBP.
1203 */
1204#define EEPROM_BBP_START 0x0013
1205#define EEPROM_BBP_SIZE 16
1206#define EEPROM_BBP_VALUE FIELD16(0x00ff)
1207#define EEPROM_BBP_REG_ID FIELD16(0xff00)
1208
1209/*
1210 * EEPROM TXPOWER 802.11G
1211 */
1212#define EEPROM_TXPOWER_G_START 0x0023
1213#define EEPROM_TXPOWER_G_SIZE 7
1214#define EEPROM_TXPOWER_G_1 FIELD16(0x00ff)
1215#define EEPROM_TXPOWER_G_2 FIELD16(0xff00)
1216
1217/*
1218 * EEPROM Frequency
1219 */
1220#define EEPROM_FREQ 0x002f
1221#define EEPROM_FREQ_OFFSET FIELD16(0x00ff)
1222#define EEPROM_FREQ_SEQ_MASK FIELD16(0xff00)
1223#define EEPROM_FREQ_SEQ FIELD16(0x0300)
1224
1225/*
1226 * EEPROM LED.
1227 * POLARITY_RDY_G: Polarity RDY_G setting.
1228 * POLARITY_RDY_A: Polarity RDY_A setting.
1229 * POLARITY_ACT: Polarity ACT setting.
1230 * POLARITY_GPIO_0: Polarity GPIO0 setting.
1231 * POLARITY_GPIO_1: Polarity GPIO1 setting.
1232 * POLARITY_GPIO_2: Polarity GPIO2 setting.
1233 * POLARITY_GPIO_3: Polarity GPIO3 setting.
1234 * POLARITY_GPIO_4: Polarity GPIO4 setting.
1235 * LED_MODE: Led mode.
1236 */
1237#define EEPROM_LED 0x0030
1238#define EEPROM_LED_POLARITY_RDY_G FIELD16(0x0001)
1239#define EEPROM_LED_POLARITY_RDY_A FIELD16(0x0002)
1240#define EEPROM_LED_POLARITY_ACT FIELD16(0x0004)
1241#define EEPROM_LED_POLARITY_GPIO_0 FIELD16(0x0008)
1242#define EEPROM_LED_POLARITY_GPIO_1 FIELD16(0x0010)
1243#define EEPROM_LED_POLARITY_GPIO_2 FIELD16(0x0020)
1244#define EEPROM_LED_POLARITY_GPIO_3 FIELD16(0x0040)
1245#define EEPROM_LED_POLARITY_GPIO_4 FIELD16(0x0080)
1246#define EEPROM_LED_LED_MODE FIELD16(0x1f00)
1247
1248/*
1249 * EEPROM TXPOWER 802.11A
1250 */
1251#define EEPROM_TXPOWER_A_START 0x0031
1252#define EEPROM_TXPOWER_A_SIZE 12
1253#define EEPROM_TXPOWER_A_1 FIELD16(0x00ff)
1254#define EEPROM_TXPOWER_A_2 FIELD16(0xff00)
1255
1256/*
1257 * EEPROM RSSI offset 802.11BG
1258 */
1259#define EEPROM_RSSI_OFFSET_BG 0x004d
1260#define EEPROM_RSSI_OFFSET_BG_1 FIELD16(0x00ff)
1261#define EEPROM_RSSI_OFFSET_BG_2 FIELD16(0xff00)
1262
1263/*
1264 * EEPROM RSSI offset 802.11A
1265 */
1266#define EEPROM_RSSI_OFFSET_A 0x004e
1267#define EEPROM_RSSI_OFFSET_A_1 FIELD16(0x00ff)
1268#define EEPROM_RSSI_OFFSET_A_2 FIELD16(0xff00)
1269
1270/*
1271 * MCU mailbox commands.
1272 */
1273#define MCU_SLEEP 0x30
1274#define MCU_WAKEUP 0x31
1275#define MCU_LED 0x50
1276#define MCU_LED_STRENGTH 0x52
1277
1278/*
1279 * DMA descriptor defines.
1280 */
4bd7c452 1281#define TXD_DESC_SIZE ( 16 * sizeof(__le32) )
181d6902 1282#define TXINFO_SIZE ( 6 * sizeof(__le32) )
4bd7c452 1283#define RXD_DESC_SIZE ( 16 * sizeof(__le32) )
95ea3627
ID		 1284
1285/*
1286 * TX descriptor format for TX, PRIO and Beacon Ring.
1287 */
1288
1289/*
1290 * Word0
1291 * TKIP_MIC: ASIC appends TKIP MIC if TKIP is used.
1292 * KEY_TABLE: Use per-client pairwise KEY table.
1293 * KEY_INDEX:
1294 * Key index (0~31) to the pairwise KEY table.
1295 * 0~3 to shared KEY table 0 (BSS0).
1296 * 4~7 to shared KEY table 1 (BSS1).
1297 * 8~11 to shared KEY table 2 (BSS2).
1298 * 12~15 to shared KEY table 3 (BSS3).
1299 * BURST: Next frame belongs to same "burst" event.
1300 */
1301#define TXD_W0_OWNER_NIC FIELD32(0x00000001)
1302#define TXD_W0_VALID FIELD32(0x00000002)
1303#define TXD_W0_MORE_FRAG FIELD32(0x00000004)
1304#define TXD_W0_ACK FIELD32(0x00000008)
1305#define TXD_W0_TIMESTAMP FIELD32(0x00000010)
1306#define TXD_W0_OFDM FIELD32(0x00000020)
1307#define TXD_W0_IFS FIELD32(0x00000040)
1308#define TXD_W0_RETRY_MODE FIELD32(0x00000080)
1309#define TXD_W0_TKIP_MIC FIELD32(0x00000100)
1310#define TXD_W0_KEY_TABLE FIELD32(0x00000200)
1311#define TXD_W0_KEY_INDEX FIELD32(0x0000fc00)
1312#define TXD_W0_DATABYTE_COUNT FIELD32(0x0fff0000)
1313#define TXD_W0_BURST FIELD32(0x10000000)
1314#define TXD_W0_CIPHER_ALG FIELD32(0xe0000000)
1315
1316/*
1317 * Word1
1318 * HOST_Q_ID: EDCA/HCCA queue ID.
1319 * HW_SEQUENCE: MAC overwrites the frame sequence number.
1320 * BUFFER_COUNT: Number of buffers in this TXD.
1321 */
1322#define TXD_W1_HOST_Q_ID FIELD32(0x0000000f)
1323#define TXD_W1_AIFSN FIELD32(0x000000f0)
1324#define TXD_W1_CWMIN FIELD32(0x00000f00)
1325#define TXD_W1_CWMAX FIELD32(0x0000f000)
1326#define TXD_W1_IV_OFFSET FIELD32(0x003f0000)
1327#define TXD_W1_PIGGY_BACK FIELD32(0x01000000)
1328#define TXD_W1_HW_SEQUENCE FIELD32(0x10000000)
1329#define TXD_W1_BUFFER_COUNT FIELD32(0xe0000000)
1330
1331/*
1332 * Word2: PLCP information
1333 */
1334#define TXD_W2_PLCP_SIGNAL FIELD32(0x000000ff)
1335#define TXD_W2_PLCP_SERVICE FIELD32(0x0000ff00)
1336#define TXD_W2_PLCP_LENGTH_LOW FIELD32(0x00ff0000)
1337#define TXD_W2_PLCP_LENGTH_HIGH FIELD32(0xff000000)
1338
1339/*
1340 * Word3
1341 */
1342#define TXD_W3_IV FIELD32(0xffffffff)
1343
1344/*
1345 * Word4
1346 */
1347#define TXD_W4_EIV FIELD32(0xffffffff)
1348
1349/*
1350 * Word5
1351 * FRAME_OFFSET: Frame start offset inside ASIC TXFIFO (after TXINFO field).
1352 * TXD_W5_PID_SUBTYPE: Driver assigned packet ID index for txdone handler.
1353 * TXD_W5_PID_TYPE: Driver assigned packet ID type for txdone handler.
1354 * WAITING_DMA_DONE_INT: TXD been filled with data
1355 * and waiting for TxDoneISR housekeeping.
1356 */
1357#define TXD_W5_FRAME_OFFSET FIELD32(0x000000ff)
1358#define TXD_W5_PID_SUBTYPE FIELD32(0x00001f00)
1359#define TXD_W5_PID_TYPE FIELD32(0x0000e000)
1360#define TXD_W5_TX_POWER FIELD32(0x00ff0000)
1361#define TXD_W5_WAITING_DMA_DONE_INT FIELD32(0x01000000)
1362
1363/*
1364 * the above 24-byte is called TXINFO and will be DMAed to MAC block
1365 * through TXFIFO. MAC block use this TXINFO to control the transmission
1366 * behavior of this frame.
1367 * The following fields are not used by MAC block.
1368 * They are used by DMA block and HOST driver only.
1369 * Once a frame has been DMA to ASIC, all the following fields are useless
1370 * to ASIC.
1371 */
1372
1373/*
1374 * Word6-10: Buffer physical address
1375 */
1376#define TXD_W6_BUFFER_PHYSICAL_ADDRESS FIELD32(0xffffffff)
1377#define TXD_W7_BUFFER_PHYSICAL_ADDRESS FIELD32(0xffffffff)
1378#define TXD_W8_BUFFER_PHYSICAL_ADDRESS FIELD32(0xffffffff)
1379#define TXD_W9_BUFFER_PHYSICAL_ADDRESS FIELD32(0xffffffff)
1380#define TXD_W10_BUFFER_PHYSICAL_ADDRESS FIELD32(0xffffffff)
1381
1382/*
1383 * Word11-13: Buffer length
1384 */
1385#define TXD_W11_BUFFER_LENGTH0 FIELD32(0x00000fff)
1386#define TXD_W11_BUFFER_LENGTH1 FIELD32(0x0fff0000)
1387#define TXD_W12_BUFFER_LENGTH2 FIELD32(0x00000fff)
1388#define TXD_W12_BUFFER_LENGTH3 FIELD32(0x0fff0000)
1389#define TXD_W13_BUFFER_LENGTH4 FIELD32(0x00000fff)
1390
1391/*
1392 * Word14
1393 */
1394#define TXD_W14_SK_BUFFER FIELD32(0xffffffff)
1395
1396/*
1397 * Word15
1398 */
1399#define TXD_W15_NEXT_SK_BUFFER FIELD32(0xffffffff)
1400
1401/*
1402 * RX descriptor format for RX Ring.
1403 */
1404
1405/*
1406 * Word0
1407 * CIPHER_ERROR: 1:ICV error, 2:MIC error, 3:invalid key.
1408 * KEY_INDEX: Decryption key actually used.
1409 */
1410#define RXD_W0_OWNER_NIC FIELD32(0x00000001)
1411#define RXD_W0_DROP FIELD32(0x00000002)
1412#define RXD_W0_UNICAST_TO_ME FIELD32(0x00000004)
1413#define RXD_W0_MULTICAST FIELD32(0x00000008)
1414#define RXD_W0_BROADCAST FIELD32(0x00000010)
1415#define RXD_W0_MY_BSS FIELD32(0x00000020)
1416#define RXD_W0_CRC_ERROR FIELD32(0x00000040)
1417#define RXD_W0_OFDM FIELD32(0x00000080)
1418#define RXD_W0_CIPHER_ERROR FIELD32(0x00000300)
1419#define RXD_W0_KEY_INDEX FIELD32(0x0000fc00)
1420#define RXD_W0_DATABYTE_COUNT FIELD32(0x0fff0000)
1421#define RXD_W0_CIPHER_ALG FIELD32(0xe0000000)
1422
1423/*
1424 * Word1
1425 * SIGNAL: RX raw data rate reported by BBP.
1426 */
1427#define RXD_W1_SIGNAL FIELD32(0x000000ff)
1428#define RXD_W1_RSSI_AGC FIELD32(0x00001f00)
1429#define RXD_W1_RSSI_LNA FIELD32(0x00006000)
1430#define RXD_W1_FRAME_OFFSET FIELD32(0x7f000000)
1431
1432/*
1433 * Word2
1434 * IV: Received IV of originally encrypted.
1435 */
1436#define RXD_W2_IV FIELD32(0xffffffff)
1437
1438/*
1439 * Word3
1440 * EIV: Received EIV of originally encrypted.
1441 */
1442#define RXD_W3_EIV FIELD32(0xffffffff)
1443
1444/*
1445 * Word4
61e754f4
ID		 1446 * ICV: Received ICV of originally encrypted.
1447 * NOTE: This is a guess, the official definition is "reserved"
95ea3627 1448 */
61e754f4 1449#define RXD_W4_ICV FIELD32(0xffffffff)
95ea3627
ID		 1450
1451/*
1452 * the above 20-byte is called RXINFO and will be DMAed to MAC RX block
1453 * and passed to the HOST driver.
1454 * The following fields are for DMA block and HOST usage only.
1455 * Can't be touched by ASIC MAC block.
1456 */
1457
1458/*
1459 * Word5
1460 */
1461#define RXD_W5_BUFFER_PHYSICAL_ADDRESS FIELD32(0xffffffff)
1462
1463/*
1464 * Word6-15: Reserved
1465 */
1466#define RXD_W6_RESERVED FIELD32(0xffffffff)
1467#define RXD_W7_RESERVED FIELD32(0xffffffff)
1468#define RXD_W8_RESERVED FIELD32(0xffffffff)
1469#define RXD_W9_RESERVED FIELD32(0xffffffff)
1470#define RXD_W10_RESERVED FIELD32(0xffffffff)
1471#define RXD_W11_RESERVED FIELD32(0xffffffff)
1472#define RXD_W12_RESERVED FIELD32(0xffffffff)
1473#define RXD_W13_RESERVED FIELD32(0xffffffff)
1474#define RXD_W14_RESERVED FIELD32(0xffffffff)
1475#define RXD_W15_RESERVED FIELD32(0xffffffff)
1476
1477/*
de99ff82
ID		 1478 * Macro's for converting txpower from EEPROM to mac80211 value
1479 * and from mac80211 value to register value.
95ea3627
ID		 1480 */
1481#define MIN_TXPOWER 0
1482#define MAX_TXPOWER 31
1483#define DEFAULT_TXPOWER 24
1484
8c5e7a5f
ID		 1485#define TXPOWER_FROM_DEV(__txpower) \
1486 (((u8)(__txpower)) > MAX_TXPOWER) ? DEFAULT_TXPOWER : (__txpower)
1487
1488#define TXPOWER_TO_DEV(__txpower) \
1489 clamp_t(char, __txpower, MIN_TXPOWER, MAX_TXPOWER)
95ea3627
ID		 1490
1491#endif /* RT61PCI_H */
Linux kernel - Deliverables
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