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rt2x00: Fix vgc_level_reg handling
[deliverable/linux.git] / drivers / net / wireless / rt2x00 / rt73usb.c
CommitLineData
95ea3627 1/*
9c9a0d14 2 Copyright (C) 2004 - 2009 Ivo van Doorn <IvDoorn@gmail.com>
95ea3627
ID		 3 <http://rt2x00.serialmonkey.com>
4
5 This program is free software; you can redistribute it and/or modify
6 it under the terms of the GNU General Public License as published by
7 the Free Software Foundation; either version 2 of the License, or
8 (at your option) any later version.
9
10 This program is distributed in the hope that it will be useful,
11 but WITHOUT ANY WARRANTY; without even the implied warranty of
12 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 GNU General Public License for more details.
14
15 You should have received a copy of the GNU General Public License
16 along with this program; if not, write to the
17 Free Software Foundation, Inc.,
18 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
19 */
20
21/*
22 Module: rt73usb
23 Abstract: rt73usb device specific routines.
24 Supported chipsets: rt2571W & rt2671.
25 */
26
a7f3a06c 27#include <linux/crc-itu-t.h>
95ea3627
ID		 28#include <linux/delay.h>
29#include <linux/etherdevice.h>
30#include <linux/init.h>
31#include <linux/kernel.h>
32#include <linux/module.h>
5a0e3ad6 33#include <linux/slab.h>
95ea3627
ID		 34#include <linux/usb.h>
35
36#include "rt2x00.h"
37#include "rt2x00usb.h"
38#include "rt73usb.h"
39
008c4482
ID		 40/*
41 * Allow hardware encryption to be disabled.
42 */
43static int modparam_nohwcrypt = 0;
44module_param_named(nohwcrypt, modparam_nohwcrypt, bool, S_IRUGO);
45MODULE_PARM_DESC(nohwcrypt, "Disable hardware encryption.");
46
95ea3627
ID		 47/*
48 * Register access.
49 * All access to the CSR registers will go through the methods
0f829b1d 50 * rt2x00usb_register_read and rt2x00usb_register_write.
95ea3627
ID		 51 * BBP and RF register require indirect register access,
52 * and use the CSR registers BBPCSR and RFCSR to achieve this.
53 * These indirect registers work with busy bits,
54 * and we will try maximal REGISTER_BUSY_COUNT times to access
55 * the register while taking a REGISTER_BUSY_DELAY us delay
56 * between each attampt. When the busy bit is still set at that time,
57 * the access attempt is considered to have failed,
58 * and we will print an error.
8ff48a8b 59 * The _lock versions must be used if you already hold the csr_mutex
95ea3627 60 */
c9c3b1a5 61#define WAIT_FOR_BBP(__dev, __reg) \
0f829b1d 62 rt2x00usb_regbusy_read((__dev), PHY_CSR3, PHY_CSR3_BUSY, (__reg))
c9c3b1a5 63#define WAIT_FOR_RF(__dev, __reg) \
0f829b1d 64 rt2x00usb_regbusy_read((__dev), PHY_CSR4, PHY_CSR4_BUSY, (__reg))
c9c3b1a5 65
0e14f6d3 66static void rt73usb_bbp_write(struct rt2x00_dev *rt2x00dev,
95ea3627
ID		 67 const unsigned int word, const u8 value)
68{
69 u32 reg;
70
8ff48a8b 71 mutex_lock(&rt2x00dev->csr_mutex);
3d82346c 72
95ea3627 73 /*
c9c3b1a5
ID		 74 * Wait until the BBP becomes available, afterwards we
75 * can safely write the new data into the register.
95ea3627 76 */
c9c3b1a5
ID		 77 if (WAIT_FOR_BBP(rt2x00dev, &reg)) {
78 reg = 0;
79 rt2x00_set_field32(&reg, PHY_CSR3_VALUE, value);
80 rt2x00_set_field32(&reg, PHY_CSR3_REGNUM, word);
81 rt2x00_set_field32(&reg, PHY_CSR3_BUSY, 1);
82 rt2x00_set_field32(&reg, PHY_CSR3_READ_CONTROL, 0);
83
0f829b1d 84 rt2x00usb_register_write_lock(rt2x00dev, PHY_CSR3, reg);
c9c3b1a5 85 }
99ade259 86
8ff48a8b 87 mutex_unlock(&rt2x00dev->csr_mutex);
95ea3627
ID		 88}
89
0e14f6d3 90static void rt73usb_bbp_read(struct rt2x00_dev *rt2x00dev,
95ea3627
ID		 91 const unsigned int word, u8 *value)
92{
93 u32 reg;
94
8ff48a8b 95 mutex_lock(&rt2x00dev->csr_mutex);
3d82346c 96
95ea3627 97 /*
c9c3b1a5
ID		 98 * Wait until the BBP becomes available, afterwards we
99 * can safely write the read request into the register.
100 * After the data has been written, we wait until hardware
101 * returns the correct value, if at any time the register
102 * doesn't become available in time, reg will be 0xffffffff
103 * which means we return 0xff to the caller.
95ea3627 104 */
c9c3b1a5
ID		 105 if (WAIT_FOR_BBP(rt2x00dev, &reg)) {
106 reg = 0;
107 rt2x00_set_field32(&reg, PHY_CSR3_REGNUM, word);
108 rt2x00_set_field32(&reg, PHY_CSR3_BUSY, 1);
109 rt2x00_set_field32(&reg, PHY_CSR3_READ_CONTROL, 1);
95ea3627 110
0f829b1d 111 rt2x00usb_register_write_lock(rt2x00dev, PHY_CSR3, reg);
95ea3627 112
c9c3b1a5
ID		 113 WAIT_FOR_BBP(rt2x00dev, &reg);
114 }
95ea3627
ID		 115
116 *value = rt2x00_get_field32(reg, PHY_CSR3_VALUE);
99ade259 117
8ff48a8b 118 mutex_unlock(&rt2x00dev->csr_mutex);
95ea3627
ID		 119}
120
0e14f6d3 121static void rt73usb_rf_write(struct rt2x00_dev *rt2x00dev,
95ea3627
ID		 122 const unsigned int word, const u32 value)
123{
124 u32 reg;
95ea3627 125
8ff48a8b 126 mutex_lock(&rt2x00dev->csr_mutex);
3d82346c 127
4f5af6eb 128 /*
c9c3b1a5
ID		 129 * Wait until the RF becomes available, afterwards we
130 * can safely write the new data into the register.
4f5af6eb 131 */
c9c3b1a5
ID		 132 if (WAIT_FOR_RF(rt2x00dev, &reg)) {
133 reg = 0;
134 rt2x00_set_field32(&reg, PHY_CSR4_VALUE, value);
135 /*
136 * RF5225 and RF2527 contain 21 bits per RF register value,
137 * all others contain 20 bits.
138 */
139 rt2x00_set_field32(&reg, PHY_CSR4_NUMBER_OF_BITS,
5122d898
GW		 140 20 + (rt2x00_rf(rt2x00dev, RF5225) ||
141 rt2x00_rf(rt2x00dev, RF2527)));
c9c3b1a5
ID		 142 rt2x00_set_field32(&reg, PHY_CSR4_IF_SELECT, 0);
143 rt2x00_set_field32(&reg, PHY_CSR4_BUSY, 1);
144
0f829b1d 145 rt2x00usb_register_write_lock(rt2x00dev, PHY_CSR4, reg);
c9c3b1a5
ID		 146 rt2x00_rf_write(rt2x00dev, word, value);
147 }
8ff48a8b
ID		 148
149 mutex_unlock(&rt2x00dev->csr_mutex);
95ea3627
ID		 150}
151
152#ifdef CONFIG_RT2X00_LIB_DEBUGFS
95ea3627
ID		 153static const struct rt2x00debug rt73usb_rt2x00debug = {
154 .owner = THIS_MODULE,
155 .csr = {
0f829b1d
ID		 156 .read = rt2x00usb_register_read,
157 .write = rt2x00usb_register_write,
743b97ca
ID		 158 .flags = RT2X00DEBUGFS_OFFSET,
159 .word_base = CSR_REG_BASE,
95ea3627
ID		 160 .word_size = sizeof(u32),
161 .word_count = CSR_REG_SIZE / sizeof(u32),
162 },
163 .eeprom = {
164 .read = rt2x00_eeprom_read,
165 .write = rt2x00_eeprom_write,
743b97ca 166 .word_base = EEPROM_BASE,
95ea3627
ID		 167 .word_size = sizeof(u16),
168 .word_count = EEPROM_SIZE / sizeof(u16),
169 },
170 .bbp = {
171 .read = rt73usb_bbp_read,
172 .write = rt73usb_bbp_write,
743b97ca 173 .word_base = BBP_BASE,
95ea3627
ID		 174 .word_size = sizeof(u8),
175 .word_count = BBP_SIZE / sizeof(u8),
176 },
177 .rf = {
178 .read = rt2x00_rf_read,
179 .write = rt73usb_rf_write,
743b97ca 180 .word_base = RF_BASE,
95ea3627
ID		 181 .word_size = sizeof(u32),
182 .word_count = RF_SIZE / sizeof(u32),
183 },
184};
185#endif /* CONFIG_RT2X00_LIB_DEBUGFS */
186
7396faf4
ID		 187static int rt73usb_rfkill_poll(struct rt2x00_dev *rt2x00dev)
188{
189 u32 reg;
190
191 rt2x00usb_register_read(rt2x00dev, MAC_CSR13, &reg);
192 return rt2x00_get_field32(reg, MAC_CSR13_BIT7);
193}
7396faf4 194
771fd565 195#ifdef CONFIG_RT2X00_LIB_LEDS
a2e1d52a 196static void rt73usb_brightness_set(struct led_classdev *led_cdev,
a9450b70
ID		 197 enum led_brightness brightness)
198{
199 struct rt2x00_led *led =
200 container_of(led_cdev, struct rt2x00_led, led_dev);
201 unsigned int enabled = brightness != LED_OFF;
202 unsigned int a_mode =
203 (enabled && led->rt2x00dev->curr_band == IEEE80211_BAND_5GHZ);
204 unsigned int bg_mode =
205 (enabled && led->rt2x00dev->curr_band == IEEE80211_BAND_2GHZ);
206
207 if (led->type == LED_TYPE_RADIO) {
208 rt2x00_set_field16(&led->rt2x00dev->led_mcu_reg,
209 MCU_LEDCS_RADIO_STATUS, enabled);
210
47b10cd1
ID		 211 rt2x00usb_vendor_request_sw(led->rt2x00dev, USB_LED_CONTROL,
212 0, led->rt2x00dev->led_mcu_reg,
213 REGISTER_TIMEOUT);
a9450b70
ID		 214 } else if (led->type == LED_TYPE_ASSOC) {
215 rt2x00_set_field16(&led->rt2x00dev->led_mcu_reg,
216 MCU_LEDCS_LINK_BG_STATUS, bg_mode);
217 rt2x00_set_field16(&led->rt2x00dev->led_mcu_reg,
218 MCU_LEDCS_LINK_A_STATUS, a_mode);
219
47b10cd1
ID		 220 rt2x00usb_vendor_request_sw(led->rt2x00dev, USB_LED_CONTROL,
221 0, led->rt2x00dev->led_mcu_reg,
222 REGISTER_TIMEOUT);
a9450b70
ID		 223 } else if (led->type == LED_TYPE_QUALITY) {
224 /*
225 * The brightness is divided into 6 levels (0 - 5),
226 * this means we need to convert the brightness
227 * argument into the matching level within that range.
228 */
47b10cd1
ID		 229 rt2x00usb_vendor_request_sw(led->rt2x00dev, USB_LED_CONTROL,
230 brightness / (LED_FULL / 6),
231 led->rt2x00dev->led_mcu_reg,
232 REGISTER_TIMEOUT);
a9450b70
ID		 233 }
234}
a2e1d52a
ID		 235
236static int rt73usb_blink_set(struct led_classdev *led_cdev,
237 unsigned long *delay_on,
238 unsigned long *delay_off)
239{
240 struct rt2x00_led *led =
241 container_of(led_cdev, struct rt2x00_led, led_dev);
242 u32 reg;
243
0f829b1d 244 rt2x00usb_register_read(led->rt2x00dev, MAC_CSR14, &reg);
a2e1d52a
ID		 245 rt2x00_set_field32(&reg, MAC_CSR14_ON_PERIOD, *delay_on);
246 rt2x00_set_field32(&reg, MAC_CSR14_OFF_PERIOD, *delay_off);
0f829b1d 247 rt2x00usb_register_write(led->rt2x00dev, MAC_CSR14, reg);
a2e1d52a
ID		 248
249 return 0;
250}
475433be
ID		 251
252static void rt73usb_init_led(struct rt2x00_dev *rt2x00dev,
253 struct rt2x00_led *led,
254 enum led_type type)
255{
256 led->rt2x00dev = rt2x00dev;
257 led->type = type;
258 led->led_dev.brightness_set = rt73usb_brightness_set;
259 led->led_dev.blink_set = rt73usb_blink_set;
260 led->flags = LED_INITIALIZED;
261}
771fd565 262#endif /* CONFIG_RT2X00_LIB_LEDS */
a9450b70 263
95ea3627
ID		 264/*
265 * Configuration handlers.
266 */
906c110f
ID		 267static int rt73usb_config_shared_key(struct rt2x00_dev *rt2x00dev,
268 struct rt2x00lib_crypto *crypto,
269 struct ieee80211_key_conf *key)
270{
271 struct hw_key_entry key_entry;
272 struct rt2x00_field32 field;
906c110f
ID		 273 u32 mask;
274 u32 reg;
275
276 if (crypto->cmd == SET_KEY) {
277 /*
278 * rt2x00lib can't determine the correct free
279 * key_idx for shared keys. We have 1 register
280 * with key valid bits. The goal is simple, read
281 * the register, if that is full we have no slots
282 * left.
283 * Note that each BSS is allowed to have up to 4
284 * shared keys, so put a mask over the allowed
285 * entries.
286 */
287 mask = (0xf << crypto->bssidx);
288
0f829b1d 289 rt2x00usb_register_read(rt2x00dev, SEC_CSR0, &reg);
906c110f
ID		 290 reg &= mask;
291
292 if (reg && reg == mask)
293 return -ENOSPC;
294
acaf908d 295 key->hw_key_idx += reg ? ffz(reg) : 0;
906c110f
ID		 296
297 /*
298 * Upload key to hardware
299 */
300 memcpy(key_entry.key, crypto->key,
301 sizeof(key_entry.key));
302 memcpy(key_entry.tx_mic, crypto->tx_mic,
303 sizeof(key_entry.tx_mic));
304 memcpy(key_entry.rx_mic, crypto->rx_mic,
305 sizeof(key_entry.rx_mic));
306
307 reg = SHARED_KEY_ENTRY(key->hw_key_idx);
96b61baf
GW		 308 rt2x00usb_register_multiwrite(rt2x00dev, reg,
309 &key_entry, sizeof(key_entry));
906c110f
ID		 310
311 /*
312 * The cipher types are stored over 2 registers.
313 * bssidx 0 and 1 keys are stored in SEC_CSR1 and
314 * bssidx 1 and 2 keys are stored in SEC_CSR5.
315 * Using the correct defines correctly will cause overhead,
316 * so just calculate the correct offset.
317 */
318 if (key->hw_key_idx < 8) {
319 field.bit_offset = (3 * key->hw_key_idx);
320 field.bit_mask = 0x7 << field.bit_offset;
321
0f829b1d 322 rt2x00usb_register_read(rt2x00dev, SEC_CSR1, &reg);
906c110f 323 rt2x00_set_field32(&reg, field, crypto->cipher);
0f829b1d 324 rt2x00usb_register_write(rt2x00dev, SEC_CSR1, reg);
906c110f
ID		 325 } else {
326 field.bit_offset = (3 * (key->hw_key_idx - 8));
327 field.bit_mask = 0x7 << field.bit_offset;
328
0f829b1d 329 rt2x00usb_register_read(rt2x00dev, SEC_CSR5, &reg);
906c110f 330 rt2x00_set_field32(&reg, field, crypto->cipher);
0f829b1d 331 rt2x00usb_register_write(rt2x00dev, SEC_CSR5, reg);
906c110f
ID		 332 }
333
334 /*
335 * The driver does not support the IV/EIV generation
336 * in hardware. However it doesn't support the IV/EIV
337 * inside the ieee80211 frame either, but requires it
3ad2f3fb 338 * to be provided separately for the descriptor.
906c110f
ID		 339 * rt2x00lib will cut the IV/EIV data out of all frames
340 * given to us by mac80211, but we must tell mac80211
341 * to generate the IV/EIV data.
342 */
343 key->flags |= IEEE80211_KEY_FLAG_GENERATE_IV;
344 }
345
346 /*
347 * SEC_CSR0 contains only single-bit fields to indicate
348 * a particular key is valid. Because using the FIELD32()
349 * defines directly will cause a lot of overhead we use
350 * a calculation to determine the correct bit directly.
351 */
352 mask = 1 << key->hw_key_idx;
353
0f829b1d 354 rt2x00usb_register_read(rt2x00dev, SEC_CSR0, &reg);
906c110f
ID		 355 if (crypto->cmd == SET_KEY)
356 reg |= mask;
357 else if (crypto->cmd == DISABLE_KEY)
358 reg &= ~mask;
0f829b1d 359 rt2x00usb_register_write(rt2x00dev, SEC_CSR0, reg);
906c110f
ID		 360
361 return 0;
362}
363
364static int rt73usb_config_pairwise_key(struct rt2x00_dev *rt2x00dev,
365 struct rt2x00lib_crypto *crypto,
366 struct ieee80211_key_conf *key)
367{
368 struct hw_pairwise_ta_entry addr_entry;
369 struct hw_key_entry key_entry;
906c110f
ID		 370 u32 mask;
371 u32 reg;
372
373 if (crypto->cmd == SET_KEY) {
374 /*
375 * rt2x00lib can't determine the correct free
376 * key_idx for pairwise keys. We have 2 registers
377 * with key valid bits. The goal is simple, read
378 * the first register, if that is full move to
379 * the next register.
380 * When both registers are full, we drop the key,
381 * otherwise we use the first invalid entry.
382 */
0f829b1d 383 rt2x00usb_register_read(rt2x00dev, SEC_CSR2, &reg);
906c110f
ID		 384 if (reg && reg == ~0) {
385 key->hw_key_idx = 32;
0f829b1d 386 rt2x00usb_register_read(rt2x00dev, SEC_CSR3, &reg);
906c110f
ID		 387 if (reg && reg == ~0)
388 return -ENOSPC;
389 }
390
acaf908d 391 key->hw_key_idx += reg ? ffz(reg) : 0;
906c110f
ID		 392
393 /*
394 * Upload key to hardware
395 */
396 memcpy(key_entry.key, crypto->key,
397 sizeof(key_entry.key));
398 memcpy(key_entry.tx_mic, crypto->tx_mic,
399 sizeof(key_entry.tx_mic));
400 memcpy(key_entry.rx_mic, crypto->rx_mic,
401 sizeof(key_entry.rx_mic));
402
403 reg = PAIRWISE_KEY_ENTRY(key->hw_key_idx);
96b61baf
GW		 404 rt2x00usb_register_multiwrite(rt2x00dev, reg,
405 &key_entry, sizeof(key_entry));
906c110f
ID		 406
407 /*
408 * Send the address and cipher type to the hardware register.
906c110f
ID		 409 */
410 memset(&addr_entry, 0, sizeof(addr_entry));
411 memcpy(&addr_entry, crypto->address, ETH_ALEN);
412 addr_entry.cipher = crypto->cipher;
413
414 reg = PAIRWISE_TA_ENTRY(key->hw_key_idx);
0f829b1d 415 rt2x00usb_register_multiwrite(rt2x00dev, reg,
906c110f
ID		 416 &addr_entry, sizeof(addr_entry));
417
418 /*
419 * Enable pairwise lookup table for given BSS idx,
420 * without this received frames will not be decrypted
421 * by the hardware.
422 */
0f829b1d 423 rt2x00usb_register_read(rt2x00dev, SEC_CSR4, &reg);
906c110f 424 reg |= (1 << crypto->bssidx);
0f829b1d 425 rt2x00usb_register_write(rt2x00dev, SEC_CSR4, reg);
906c110f
ID		 426
427 /*
428 * The driver does not support the IV/EIV generation
429 * in hardware. However it doesn't support the IV/EIV
430 * inside the ieee80211 frame either, but requires it
3ad2f3fb 431 * to be provided separately for the descriptor.
906c110f
ID		 432 * rt2x00lib will cut the IV/EIV data out of all frames
433 * given to us by mac80211, but we must tell mac80211
434 * to generate the IV/EIV data.
435 */
436 key->flags |= IEEE80211_KEY_FLAG_GENERATE_IV;
437 }
438
439 /*
440 * SEC_CSR2 and SEC_CSR3 contain only single-bit fields to indicate
441 * a particular key is valid. Because using the FIELD32()
442 * defines directly will cause a lot of overhead we use
443 * a calculation to determine the correct bit directly.
444 */
445 if (key->hw_key_idx < 32) {
446 mask = 1 << key->hw_key_idx;
447
0f829b1d 448 rt2x00usb_register_read(rt2x00dev, SEC_CSR2, &reg);
906c110f
ID		 449 if (crypto->cmd == SET_KEY)
450 reg |= mask;
451 else if (crypto->cmd == DISABLE_KEY)
452 reg &= ~mask;
0f829b1d 453 rt2x00usb_register_write(rt2x00dev, SEC_CSR2, reg);
906c110f
ID		 454 } else {
455 mask = 1 << (key->hw_key_idx - 32);
456
0f829b1d 457 rt2x00usb_register_read(rt2x00dev, SEC_CSR3, &reg);
906c110f
ID		 458 if (crypto->cmd == SET_KEY)
459 reg |= mask;
460 else if (crypto->cmd == DISABLE_KEY)
461 reg &= ~mask;
0f829b1d 462 rt2x00usb_register_write(rt2x00dev, SEC_CSR3, reg);
906c110f
ID		 463 }
464
465 return 0;
466}
467
3a643d24
ID		 468static void rt73usb_config_filter(struct rt2x00_dev *rt2x00dev,
469 const unsigned int filter_flags)
470{
471 u32 reg;
472
473 /*
474 * Start configuration steps.
475 * Note that the version error will always be dropped
476 * and broadcast frames will always be accepted since
477 * there is no filter for it at this time.
478 */
0f829b1d 479 rt2x00usb_register_read(rt2x00dev, TXRX_CSR0, &reg);
3a643d24
ID		 480 rt2x00_set_field32(&reg, TXRX_CSR0_DROP_CRC,
481 !(filter_flags & FIF_FCSFAIL));
482 rt2x00_set_field32(&reg, TXRX_CSR0_DROP_PHYSICAL,
483 !(filter_flags & FIF_PLCPFAIL));
484 rt2x00_set_field32(&reg, TXRX_CSR0_DROP_CONTROL,
1afcfd54 485 !(filter_flags & (FIF_CONTROL | FIF_PSPOLL)));
3a643d24
ID		 486 rt2x00_set_field32(&reg, TXRX_CSR0_DROP_NOT_TO_ME,
487 !(filter_flags & FIF_PROMISC_IN_BSS));
488 rt2x00_set_field32(&reg, TXRX_CSR0_DROP_TO_DS,
e0b005fa
ID		 489 !(filter_flags & FIF_PROMISC_IN_BSS) &&
490 !rt2x00dev->intf_ap_count);
3a643d24
ID		 491 rt2x00_set_field32(&reg, TXRX_CSR0_DROP_VERSION_ERROR, 1);
492 rt2x00_set_field32(&reg, TXRX_CSR0_DROP_MULTICAST,
493 !(filter_flags & FIF_ALLMULTI));
494 rt2x00_set_field32(&reg, TXRX_CSR0_DROP_BROADCAST, 0);
495 rt2x00_set_field32(&reg, TXRX_CSR0_DROP_ACK_CTS,
496 !(filter_flags & FIF_CONTROL));
0f829b1d 497 rt2x00usb_register_write(rt2x00dev, TXRX_CSR0, reg);
3a643d24
ID		 498}
499
6bb40dd1
ID		 500static void rt73usb_config_intf(struct rt2x00_dev *rt2x00dev,
501 struct rt2x00_intf *intf,
502 struct rt2x00intf_conf *conf,
503 const unsigned int flags)
95ea3627 504{
6bb40dd1
ID		 505 unsigned int beacon_base;
506 u32 reg;
95ea3627 507
6bb40dd1
ID		 508 if (flags & CONFIG_UPDATE_TYPE) {
509 /*
510 * Clear current synchronisation setup.
511 * For the Beacon base registers we only need to clear
512 * the first byte since that byte contains the VALID and OWNER
513 * bits which (when set to 0) will invalidate the entire beacon.
514 */
515 beacon_base = HW_BEACON_OFFSET(intf->beacon->entry_idx);
0f829b1d 516 rt2x00usb_register_write(rt2x00dev, beacon_base, 0);
95ea3627 517
6bb40dd1
ID		 518 /*
519 * Enable synchronisation.
520 */
0f829b1d 521 rt2x00usb_register_read(rt2x00dev, TXRX_CSR9, &reg);
fd3c91c5 522 rt2x00_set_field32(&reg, TXRX_CSR9_TSF_TICKING, 1);
6bb40dd1 523 rt2x00_set_field32(&reg, TXRX_CSR9_TSF_SYNC, conf->sync);
fd3c91c5 524 rt2x00_set_field32(&reg, TXRX_CSR9_TBTT_ENABLE, 1);
0f829b1d 525 rt2x00usb_register_write(rt2x00dev, TXRX_CSR9, reg);
6bb40dd1 526 }
95ea3627 527
6bb40dd1
ID		 528 if (flags & CONFIG_UPDATE_MAC) {
529 reg = le32_to_cpu(conf->mac[1]);
530 rt2x00_set_field32(&reg, MAC_CSR3_UNICAST_TO_ME_MASK, 0xff);
531 conf->mac[1] = cpu_to_le32(reg);
95ea3627 532
0f829b1d 533 rt2x00usb_register_multiwrite(rt2x00dev, MAC_CSR2,
6bb40dd1
ID		 534 conf->mac, sizeof(conf->mac));
535 }
95ea3627 536
6bb40dd1
ID		 537 if (flags & CONFIG_UPDATE_BSSID) {
538 reg = le32_to_cpu(conf->bssid[1]);
539 rt2x00_set_field32(&reg, MAC_CSR5_BSS_ID_MASK, 3);
540 conf->bssid[1] = cpu_to_le32(reg);
95ea3627 541
0f829b1d 542 rt2x00usb_register_multiwrite(rt2x00dev, MAC_CSR4,
6bb40dd1
ID		 543 conf->bssid, sizeof(conf->bssid));
544 }
95ea3627
ID		 545}
546
3a643d24
ID		 547static void rt73usb_config_erp(struct rt2x00_dev *rt2x00dev,
548 struct rt2x00lib_erp *erp)
95ea3627 549{
95ea3627 550 u32 reg;
95ea3627 551
0f829b1d 552 rt2x00usb_register_read(rt2x00dev, TXRX_CSR0, &reg);
4789666e 553 rt2x00_set_field32(&reg, TXRX_CSR0_RX_ACK_TIMEOUT, 0x32);
8a566afe 554 rt2x00_set_field32(&reg, TXRX_CSR0_TSF_OFFSET, IEEE80211_HEADER);
0f829b1d 555 rt2x00usb_register_write(rt2x00dev, TXRX_CSR0, reg);
95ea3627 556
0f829b1d 557 rt2x00usb_register_read(rt2x00dev, TXRX_CSR4, &reg);
8a566afe 558 rt2x00_set_field32(&reg, TXRX_CSR4_AUTORESPOND_ENABLE, 1);
4f5af6eb 559 rt2x00_set_field32(&reg, TXRX_CSR4_AUTORESPOND_PREAMBLE,
72810379 560 !!erp->short_preamble);
0f829b1d 561 rt2x00usb_register_write(rt2x00dev, TXRX_CSR4, reg);
95ea3627 562
0f829b1d 563 rt2x00usb_register_write(rt2x00dev, TXRX_CSR5, erp->basic_rates);
95ea3627 564
8a566afe
ID		 565 rt2x00usb_register_read(rt2x00dev, TXRX_CSR9, &reg);
566 rt2x00_set_field32(&reg, TXRX_CSR9_BEACON_INTERVAL,
567 erp->beacon_int * 16);
568 rt2x00usb_register_write(rt2x00dev, TXRX_CSR9, reg);
569
0f829b1d 570 rt2x00usb_register_read(rt2x00dev, MAC_CSR9, &reg);
e4ea1c40 571 rt2x00_set_field32(&reg, MAC_CSR9_SLOT_TIME, erp->slot_time);
0f829b1d 572 rt2x00usb_register_write(rt2x00dev, MAC_CSR9, reg);
95ea3627 573
0f829b1d 574 rt2x00usb_register_read(rt2x00dev, MAC_CSR8, &reg);
e4ea1c40
ID		 575 rt2x00_set_field32(&reg, MAC_CSR8_SIFS, erp->sifs);
576 rt2x00_set_field32(&reg, MAC_CSR8_SIFS_AFTER_RX_OFDM, 3);
577 rt2x00_set_field32(&reg, MAC_CSR8_EIFS, erp->eifs);
0f829b1d 578 rt2x00usb_register_write(rt2x00dev, MAC_CSR8, reg);
95ea3627
ID		 579}
580
581static void rt73usb_config_antenna_5x(struct rt2x00_dev *rt2x00dev,
addc81bd 582 struct antenna_setup *ant)
95ea3627
ID		 583{
584 u8 r3;
585 u8 r4;
586 u8 r77;
2676c94d 587 u8 temp;
95ea3627
ID		 588
589 rt73usb_bbp_read(rt2x00dev, 3, &r3);
590 rt73usb_bbp_read(rt2x00dev, 4, &r4);
591 rt73usb_bbp_read(rt2x00dev, 77, &r77);
592
593 rt2x00_set_field8(&r3, BBP_R3_SMART_MODE, 0);
594
e4cd2ff8
ID		 595 /*
596 * Configure the RX antenna.
597 */
addc81bd 598 switch (ant->rx) {
95ea3627 599 case ANTENNA_HW_DIVERSITY:
2676c94d
MN		 600 rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA_CONTROL, 2);
601 temp = !test_bit(CONFIG_FRAME_TYPE, &rt2x00dev->flags)
8318d78a 602 && (rt2x00dev->curr_band != IEEE80211_BAND_5GHZ);
2676c94d 603 rt2x00_set_field8(&r4, BBP_R4_RX_FRAME_END, temp);
95ea3627
ID		 604 break;
605 case ANTENNA_A:
2676c94d 606 rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA_CONTROL, 1);
95ea3627 607 rt2x00_set_field8(&r4, BBP_R4_RX_FRAME_END, 0);
8318d78a 608 if (rt2x00dev->curr_band == IEEE80211_BAND_5GHZ)
2676c94d
MN		 609 rt2x00_set_field8(&r77, BBP_R77_RX_ANTENNA, 0);
610 else
611 rt2x00_set_field8(&r77, BBP_R77_RX_ANTENNA, 3);
95ea3627
ID		 612 break;
613 case ANTENNA_B:
a4fe07d9 614 default:
2676c94d 615 rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA_CONTROL, 1);
95ea3627 616 rt2x00_set_field8(&r4, BBP_R4_RX_FRAME_END, 0);
8318d78a 617 if (rt2x00dev->curr_band == IEEE80211_BAND_5GHZ)
2676c94d
MN		 618 rt2x00_set_field8(&r77, BBP_R77_RX_ANTENNA, 3);
619 else
620 rt2x00_set_field8(&r77, BBP_R77_RX_ANTENNA, 0);
95ea3627
ID		 621 break;
622 }
623
624 rt73usb_bbp_write(rt2x00dev, 77, r77);
625 rt73usb_bbp_write(rt2x00dev, 3, r3);
626 rt73usb_bbp_write(rt2x00dev, 4, r4);
627}
628
629static void rt73usb_config_antenna_2x(struct rt2x00_dev *rt2x00dev,
addc81bd 630 struct antenna_setup *ant)
95ea3627
ID		 631{
632 u8 r3;
633 u8 r4;
634 u8 r77;
635
636 rt73usb_bbp_read(rt2x00dev, 3, &r3);
637 rt73usb_bbp_read(rt2x00dev, 4, &r4);
638 rt73usb_bbp_read(rt2x00dev, 77, &r77);
639
640 rt2x00_set_field8(&r3, BBP_R3_SMART_MODE, 0);
641 rt2x00_set_field8(&r4, BBP_R4_RX_FRAME_END,
642 !test_bit(CONFIG_FRAME_TYPE, &rt2x00dev->flags));
643
e4cd2ff8
ID		 644 /*
645 * Configure the RX antenna.
646 */
addc81bd 647 switch (ant->rx) {
95ea3627 648 case ANTENNA_HW_DIVERSITY:
2676c94d 649 rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA_CONTROL, 2);
95ea3627
ID		 650 break;
651 case ANTENNA_A:
2676c94d
MN		 652 rt2x00_set_field8(&r77, BBP_R77_RX_ANTENNA, 3);
653 rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA_CONTROL, 1);
95ea3627
ID		 654 break;
655 case ANTENNA_B:
a4fe07d9 656 default:
2676c94d
MN		 657 rt2x00_set_field8(&r77, BBP_R77_RX_ANTENNA, 0);
658 rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA_CONTROL, 1);
95ea3627
ID		 659 break;
660 }
661
662 rt73usb_bbp_write(rt2x00dev, 77, r77);
663 rt73usb_bbp_write(rt2x00dev, 3, r3);
664 rt73usb_bbp_write(rt2x00dev, 4, r4);
665}
666
667struct antenna_sel {
668 u8 word;
669 /*
670 * value[0] -> non-LNA
671 * value[1] -> LNA
672 */
673 u8 value[2];
674};
675
676static const struct antenna_sel antenna_sel_a[] = {
677 { 96, { 0x58, 0x78 } },
678 { 104, { 0x38, 0x48 } },
679 { 75, { 0xfe, 0x80 } },
680 { 86, { 0xfe, 0x80 } },
681 { 88, { 0xfe, 0x80 } },
682 { 35, { 0x60, 0x60 } },
683 { 97, { 0x58, 0x58 } },
684 { 98, { 0x58, 0x58 } },
685};
686
687static const struct antenna_sel antenna_sel_bg[] = {
688 { 96, { 0x48, 0x68 } },
689 { 104, { 0x2c, 0x3c } },
690 { 75, { 0xfe, 0x80 } },
691 { 86, { 0xfe, 0x80 } },
692 { 88, { 0xfe, 0x80 } },
693 { 35, { 0x50, 0x50 } },
694 { 97, { 0x48, 0x48 } },
695 { 98, { 0x48, 0x48 } },
696};
697
e4ea1c40
ID		 698static void rt73usb_config_ant(struct rt2x00_dev *rt2x00dev,
699 struct antenna_setup *ant)
95ea3627
ID		 700{
701 const struct antenna_sel *sel;
702 unsigned int lna;
703 unsigned int i;
704 u32 reg;
705
a4fe07d9
ID		 706 /*
707 * We should never come here because rt2x00lib is supposed
708 * to catch this and send us the correct antenna explicitely.
709 */
710 BUG_ON(ant->rx == ANTENNA_SW_DIVERSITY ||
711 ant->tx == ANTENNA_SW_DIVERSITY);
712
8318d78a 713 if (rt2x00dev->curr_band == IEEE80211_BAND_5GHZ) {
95ea3627
ID		 714 sel = antenna_sel_a;
715 lna = test_bit(CONFIG_EXTERNAL_LNA_A, &rt2x00dev->flags);
95ea3627
ID		 716 } else {
717 sel = antenna_sel_bg;
718 lna = test_bit(CONFIG_EXTERNAL_LNA_BG, &rt2x00dev->flags);
95ea3627
ID		 719 }
720
2676c94d
MN		 721 for (i = 0; i < ARRAY_SIZE(antenna_sel_a); i++)
722 rt73usb_bbp_write(rt2x00dev, sel[i].word, sel[i].value[lna]);
723
0f829b1d 724 rt2x00usb_register_read(rt2x00dev, PHY_CSR0, &reg);
2676c94d 725
ddc827f9 726 rt2x00_set_field32(&reg, PHY_CSR0_PA_PE_BG,
8318d78a 727 (rt2x00dev->curr_band == IEEE80211_BAND_2GHZ));
ddc827f9 728 rt2x00_set_field32(&reg, PHY_CSR0_PA_PE_A,
8318d78a 729 (rt2x00dev->curr_band == IEEE80211_BAND_5GHZ));
ddc827f9 730
0f829b1d 731 rt2x00usb_register_write(rt2x00dev, PHY_CSR0, reg);
95ea3627 732
5122d898 733 if (rt2x00_rf(rt2x00dev, RF5226) || rt2x00_rf(rt2x00dev, RF5225))
addc81bd 734 rt73usb_config_antenna_5x(rt2x00dev, ant);
5122d898 735 else if (rt2x00_rf(rt2x00dev, RF2528) || rt2x00_rf(rt2x00dev, RF2527))
addc81bd 736 rt73usb_config_antenna_2x(rt2x00dev, ant);
95ea3627
ID		 737}
738
e4ea1c40 739static void rt73usb_config_lna_gain(struct rt2x00_dev *rt2x00dev,
5c58ee51 740 struct rt2x00lib_conf *libconf)
e4ea1c40
ID		 741{
742 u16 eeprom;
743 short lna_gain = 0;
744
745 if (libconf->conf->channel->band == IEEE80211_BAND_2GHZ) {
746 if (test_bit(CONFIG_EXTERNAL_LNA_BG, &rt2x00dev->flags))
747 lna_gain += 14;
748
749 rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_OFFSET_BG, &eeprom);
750 lna_gain -= rt2x00_get_field16(eeprom, EEPROM_RSSI_OFFSET_BG_1);
751 } else {
752 rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_OFFSET_A, &eeprom);
753 lna_gain -= rt2x00_get_field16(eeprom, EEPROM_RSSI_OFFSET_A_1);
754 }
755
756 rt2x00dev->lna_gain = lna_gain;
757}
758
759static void rt73usb_config_channel(struct rt2x00_dev *rt2x00dev,
760 struct rf_channel *rf, const int txpower)
761{
762 u8 r3;
763 u8 r94;
764 u8 smart;
765
766 rt2x00_set_field32(&rf->rf3, RF3_TXPOWER, TXPOWER_TO_DEV(txpower));
767 rt2x00_set_field32(&rf->rf4, RF4_FREQ_OFFSET, rt2x00dev->freq_offset);
768
5122d898 769 smart = !(rt2x00_rf(rt2x00dev, RF5225) || rt2x00_rf(rt2x00dev, RF2527));
e4ea1c40
ID		 770
771 rt73usb_bbp_read(rt2x00dev, 3, &r3);
772 rt2x00_set_field8(&r3, BBP_R3_SMART_MODE, smart);
773 rt73usb_bbp_write(rt2x00dev, 3, r3);
774
775 r94 = 6;
776 if (txpower > MAX_TXPOWER && txpower <= (MAX_TXPOWER + r94))
777 r94 += txpower - MAX_TXPOWER;
778 else if (txpower < MIN_TXPOWER && txpower >= (MIN_TXPOWER - r94))
779 r94 += txpower;
780 rt73usb_bbp_write(rt2x00dev, 94, r94);
781
782 rt73usb_rf_write(rt2x00dev, 1, rf->rf1);
783 rt73usb_rf_write(rt2x00dev, 2, rf->rf2);
784 rt73usb_rf_write(rt2x00dev, 3, rf->rf3 & ~0x00000004);
785 rt73usb_rf_write(rt2x00dev, 4, rf->rf4);
786
787 rt73usb_rf_write(rt2x00dev, 1, rf->rf1);
788 rt73usb_rf_write(rt2x00dev, 2, rf->rf2);
789 rt73usb_rf_write(rt2x00dev, 3, rf->rf3 | 0x00000004);
790 rt73usb_rf_write(rt2x00dev, 4, rf->rf4);
791
792 rt73usb_rf_write(rt2x00dev, 1, rf->rf1);
793 rt73usb_rf_write(rt2x00dev, 2, rf->rf2);
794 rt73usb_rf_write(rt2x00dev, 3, rf->rf3 & ~0x00000004);
795 rt73usb_rf_write(rt2x00dev, 4, rf->rf4);
796
797 udelay(10);
798}
799
800static void rt73usb_config_txpower(struct rt2x00_dev *rt2x00dev,
801 const int txpower)
802{
803 struct rf_channel rf;
804
805 rt2x00_rf_read(rt2x00dev, 1, &rf.rf1);
806 rt2x00_rf_read(rt2x00dev, 2, &rf.rf2);
807 rt2x00_rf_read(rt2x00dev, 3, &rf.rf3);
808 rt2x00_rf_read(rt2x00dev, 4, &rf.rf4);
809
810 rt73usb_config_channel(rt2x00dev, &rf, txpower);
811}
812
813static void rt73usb_config_retry_limit(struct rt2x00_dev *rt2x00dev,
814 struct rt2x00lib_conf *libconf)
95ea3627
ID		 815{
816 u32 reg;
817
0f829b1d 818 rt2x00usb_register_read(rt2x00dev, TXRX_CSR4, &reg);
e1b4d7b7
ID		 819 rt2x00_set_field32(&reg, TXRX_CSR4_OFDM_TX_RATE_DOWN, 1);
820 rt2x00_set_field32(&reg, TXRX_CSR4_OFDM_TX_RATE_STEP, 0);
821 rt2x00_set_field32(&reg, TXRX_CSR4_OFDM_TX_FALLBACK_CCK, 0);
e4ea1c40
ID		 822 rt2x00_set_field32(&reg, TXRX_CSR4_LONG_RETRY_LIMIT,
823 libconf->conf->long_frame_max_tx_count);
824 rt2x00_set_field32(&reg, TXRX_CSR4_SHORT_RETRY_LIMIT,
825 libconf->conf->short_frame_max_tx_count);
0f829b1d 826 rt2x00usb_register_write(rt2x00dev, TXRX_CSR4, reg);
e4ea1c40 827}
95ea3627 828
7d7f19cc
ID		 829static void rt73usb_config_ps(struct rt2x00_dev *rt2x00dev,
830 struct rt2x00lib_conf *libconf)
831{
832 enum dev_state state =
833 (libconf->conf->flags & IEEE80211_CONF_PS) ?
834 STATE_SLEEP : STATE_AWAKE;
835 u32 reg;
836
837 if (state == STATE_SLEEP) {
838 rt2x00usb_register_read(rt2x00dev, MAC_CSR11, &reg);
839 rt2x00_set_field32(&reg, MAC_CSR11_DELAY_AFTER_TBCN,
6b347bff 840 rt2x00dev->beacon_int - 10);
7d7f19cc
ID		 841 rt2x00_set_field32(&reg, MAC_CSR11_TBCN_BEFORE_WAKEUP,
842 libconf->conf->listen_interval - 1);
843 rt2x00_set_field32(&reg, MAC_CSR11_WAKEUP_LATENCY, 5);
844
845 /* We must first disable autowake before it can be enabled */
846 rt2x00_set_field32(&reg, MAC_CSR11_AUTOWAKE, 0);
847 rt2x00usb_register_write(rt2x00dev, MAC_CSR11, reg);
848
849 rt2x00_set_field32(&reg, MAC_CSR11_AUTOWAKE, 1);
850 rt2x00usb_register_write(rt2x00dev, MAC_CSR11, reg);
851
852 rt2x00usb_vendor_request_sw(rt2x00dev, USB_DEVICE_MODE, 0,
853 USB_MODE_SLEEP, REGISTER_TIMEOUT);
854 } else {
7d7f19cc
ID		 855 rt2x00usb_register_read(rt2x00dev, MAC_CSR11, &reg);
856 rt2x00_set_field32(&reg, MAC_CSR11_DELAY_AFTER_TBCN, 0);
857 rt2x00_set_field32(&reg, MAC_CSR11_TBCN_BEFORE_WAKEUP, 0);
858 rt2x00_set_field32(&reg, MAC_CSR11_AUTOWAKE, 0);
859 rt2x00_set_field32(&reg, MAC_CSR11_WAKEUP_LATENCY, 0);
860 rt2x00usb_register_write(rt2x00dev, MAC_CSR11, reg);
5731858d
GW		 861
862 rt2x00usb_vendor_request_sw(rt2x00dev, USB_DEVICE_MODE, 0,
863 USB_MODE_WAKEUP, REGISTER_TIMEOUT);
7d7f19cc
ID		 864 }
865}
866
95ea3627 867static void rt73usb_config(struct rt2x00_dev *rt2x00dev,
6bb40dd1
ID		 868 struct rt2x00lib_conf *libconf,
869 const unsigned int flags)
95ea3627 870{
ba2ab471
ID		 871 /* Always recalculate LNA gain before changing configuration */
872 rt73usb_config_lna_gain(rt2x00dev, libconf);
873
e4ea1c40 874 if (flags & IEEE80211_CONF_CHANGE_CHANNEL)
5c58ee51
ID		 875 rt73usb_config_channel(rt2x00dev, &libconf->rf,
876 libconf->conf->power_level);
e4ea1c40
ID		 877 if ((flags & IEEE80211_CONF_CHANGE_POWER) &&
878 !(flags & IEEE80211_CONF_CHANGE_CHANNEL))
5c58ee51 879 rt73usb_config_txpower(rt2x00dev, libconf->conf->power_level);
e4ea1c40
ID		 880 if (flags & IEEE80211_CONF_CHANGE_RETRY_LIMITS)
881 rt73usb_config_retry_limit(rt2x00dev, libconf);
7d7f19cc
ID		 882 if (flags & IEEE80211_CONF_CHANGE_PS)
883 rt73usb_config_ps(rt2x00dev, libconf);
95ea3627
ID		 884}
885
95ea3627
ID		 886/*
887 * Link tuning
888 */
ebcf26da
ID		 889static void rt73usb_link_stats(struct rt2x00_dev *rt2x00dev,
890 struct link_qual *qual)
95ea3627
ID		 891{
892 u32 reg;
893
894 /*
895 * Update FCS error count from register.
896 */
0f829b1d 897 rt2x00usb_register_read(rt2x00dev, STA_CSR0, &reg);
ebcf26da 898 qual->rx_failed = rt2x00_get_field32(reg, STA_CSR0_FCS_ERROR);
95ea3627
ID		 899
900 /*
901 * Update False CCA count from register.
902 */
0f829b1d 903 rt2x00usb_register_read(rt2x00dev, STA_CSR1, &reg);
ebcf26da 904 qual->false_cca = rt2x00_get_field32(reg, STA_CSR1_FALSE_CCA_ERROR);
95ea3627
ID		 905}
906
5352ff65
ID		 907static inline void rt73usb_set_vgc(struct rt2x00_dev *rt2x00dev,
908 struct link_qual *qual, u8 vgc_level)
eb20b4e8 909{
5352ff65 910 if (qual->vgc_level != vgc_level) {
eb20b4e8 911 rt73usb_bbp_write(rt2x00dev, 17, vgc_level);
5352ff65
ID		 912 qual->vgc_level = vgc_level;
913 qual->vgc_level_reg = vgc_level;
eb20b4e8
ID		 914 }
915}
916
5352ff65
ID		 917static void rt73usb_reset_tuner(struct rt2x00_dev *rt2x00dev,
918 struct link_qual *qual)
95ea3627 919{
5352ff65 920 rt73usb_set_vgc(rt2x00dev, qual, 0x20);
95ea3627
ID		 921}
922
5352ff65
ID		 923static void rt73usb_link_tuner(struct rt2x00_dev *rt2x00dev,
924 struct link_qual *qual, const u32 count)
95ea3627 925{
95ea3627
ID		 926 u8 up_bound;
927 u8 low_bound;
928
95ea3627
ID		 929 /*
930 * Determine r17 bounds.
931 */
8318d78a 932 if (rt2x00dev->rx_status.band == IEEE80211_BAND_5GHZ) {
95ea3627
ID		 933 low_bound = 0x28;
934 up_bound = 0x48;
935
936 if (test_bit(CONFIG_EXTERNAL_LNA_A, &rt2x00dev->flags)) {
937 low_bound += 0x10;
938 up_bound += 0x10;
939 }
940 } else {
5352ff65 941 if (qual->rssi > -82) {
95ea3627
ID		 942 low_bound = 0x1c;
943 up_bound = 0x40;
5352ff65 944 } else if (qual->rssi > -84) {
95ea3627
ID		 945 low_bound = 0x1c;
946 up_bound = 0x20;
947 } else {
948 low_bound = 0x1c;
949 up_bound = 0x1c;
950 }
951
952 if (test_bit(CONFIG_EXTERNAL_LNA_BG, &rt2x00dev->flags)) {
953 low_bound += 0x14;
954 up_bound += 0x10;
955 }
956 }
957
6bb40dd1
ID		 958 /*
959 * If we are not associated, we should go straight to the
960 * dynamic CCA tuning.
961 */
962 if (!rt2x00dev->intf_associated)
963 goto dynamic_cca_tune;
964
95ea3627
ID		 965 /*
966 * Special big-R17 for very short distance
967 */
5352ff65
ID		 968 if (qual->rssi > -35) {
969 rt73usb_set_vgc(rt2x00dev, qual, 0x60);
95ea3627
ID		 970 return;
971 }
972
973 /*
974 * Special big-R17 for short distance
975 */
5352ff65
ID		 976 if (qual->rssi >= -58) {
977 rt73usb_set_vgc(rt2x00dev, qual, up_bound);
95ea3627
ID		 978 return;
979 }
980
981 /*
982 * Special big-R17 for middle-short distance
983 */
5352ff65
ID		 984 if (qual->rssi >= -66) {
985 rt73usb_set_vgc(rt2x00dev, qual, low_bound + 0x10);
95ea3627
ID		 986 return;
987 }
988
989 /*
990 * Special mid-R17 for middle distance
991 */
5352ff65
ID		 992 if (qual->rssi >= -74) {
993 rt73usb_set_vgc(rt2x00dev, qual, low_bound + 0x08);
95ea3627
ID		 994 return;
995 }
996
997 /*
998 * Special case: Change up_bound based on the rssi.
999 * Lower up_bound when rssi is weaker then -74 dBm.
1000 */
5352ff65 1001 up_bound -= 2 * (-74 - qual->rssi);
95ea3627
ID		 1002 if (low_bound > up_bound)
1003 up_bound = low_bound;
1004
5352ff65
ID		 1005 if (qual->vgc_level > up_bound) {
1006 rt73usb_set_vgc(rt2x00dev, qual, up_bound);
95ea3627
ID		 1007 return;
1008 }
1009
6bb40dd1
ID		 1010dynamic_cca_tune:
1011
95ea3627
ID		 1012 /*
1013 * r17 does not yet exceed upper limit, continue and base
1014 * the r17 tuning on the false CCA count.
1015 */
5352ff65
ID		 1016 if ((qual->false_cca > 512) && (qual->vgc_level < up_bound))
1017 rt73usb_set_vgc(rt2x00dev, qual,
1018 min_t(u8, qual->vgc_level + 4, up_bound));
1019 else if ((qual->false_cca < 100) && (qual->vgc_level > low_bound))
1020 rt73usb_set_vgc(rt2x00dev, qual,
1021 max_t(u8, qual->vgc_level - 4, low_bound));
95ea3627
ID		 1022}
1023
1024/*
a7f3a06c 1025 * Firmware functions
95ea3627
ID		 1026 */
1027static char *rt73usb_get_firmware_name(struct rt2x00_dev *rt2x00dev)
1028{
1029 return FIRMWARE_RT2571;
1030}
1031
0cbe0064
ID		 1032static int rt73usb_check_firmware(struct rt2x00_dev *rt2x00dev,
1033 const u8 *data, const size_t len)
a7f3a06c 1034{
0cbe0064 1035 u16 fw_crc;
a7f3a06c
ID		 1036 u16 crc;
1037
1038 /*
0cbe0064
ID		 1039 * Only support 2kb firmware files.
1040 */
1041 if (len != 2048)
1042 return FW_BAD_LENGTH;
1043
1044 /*
a7f3a06c
ID		 1045 * The last 2 bytes in the firmware array are the crc checksum itself,
1046 * this means that we should never pass those 2 bytes to the crc
1047 * algorithm.
1048 */
0cbe0064
ID		 1049 fw_crc = (data[len - 2] << 8 | data[len - 1]);
1050
1051 /*
1052 * Use the crc itu-t algorithm.
1053 */
a7f3a06c
ID		 1054 crc = crc_itu_t(0, data, len - 2);
1055 crc = crc_itu_t_byte(crc, 0);
1056 crc = crc_itu_t_byte(crc, 0);
1057
0cbe0064 1058 return (fw_crc == crc) ? FW_OK : FW_BAD_CRC;
a7f3a06c
ID		 1059}
1060
0cbe0064
ID		 1061static int rt73usb_load_firmware(struct rt2x00_dev *rt2x00dev,
1062 const u8 *data, const size_t len)
95ea3627
ID		 1063{
1064 unsigned int i;
1065 int status;
1066 u32 reg;
95ea3627
ID		 1067
1068 /*
1069 * Wait for stable hardware.
1070 */
1071 for (i = 0; i < 100; i++) {
0f829b1d 1072 rt2x00usb_register_read(rt2x00dev, MAC_CSR0, &reg);
95ea3627
ID		 1073 if (reg)
1074 break;
1075 msleep(1);
1076 }
1077
1078 if (!reg) {
1079 ERROR(rt2x00dev, "Unstable hardware.\n");
1080 return -EBUSY;
1081 }
1082
1083 /*
1084 * Write firmware to device.
95ea3627 1085 */
96b61baf 1086 rt2x00usb_register_multiwrite(rt2x00dev, FIRMWARE_IMAGE_BASE, data, len);
95ea3627
ID		 1087
1088 /*
1089 * Send firmware request to device to load firmware,
1090 * we need to specify a long timeout time.
1091 */
1092 status = rt2x00usb_vendor_request_sw(rt2x00dev, USB_DEVICE_MODE,
3b640f21 1093 0, USB_MODE_FIRMWARE,
95ea3627
ID		 1094 REGISTER_TIMEOUT_FIRMWARE);
1095 if (status < 0) {
1096 ERROR(rt2x00dev, "Failed to write Firmware to device.\n");
1097 return status;
1098 }
1099
95ea3627
ID		 1100 return 0;
1101}
1102
a7f3a06c
ID		 1103/*
1104 * Initialization functions.
1105 */
95ea3627
ID		 1106static int rt73usb_init_registers(struct rt2x00_dev *rt2x00dev)
1107{
1108 u32 reg;
1109
0f829b1d 1110 rt2x00usb_register_read(rt2x00dev, TXRX_CSR0, &reg);
95ea3627
ID		 1111 rt2x00_set_field32(&reg, TXRX_CSR0_AUTO_TX_SEQ, 1);
1112 rt2x00_set_field32(&reg, TXRX_CSR0_DISABLE_RX, 0);
1113 rt2x00_set_field32(&reg, TXRX_CSR0_TX_WITHOUT_WAITING, 0);
0f829b1d 1114 rt2x00usb_register_write(rt2x00dev, TXRX_CSR0, reg);
95ea3627 1115
0f829b1d 1116 rt2x00usb_register_read(rt2x00dev, TXRX_CSR1, &reg);
95ea3627
ID		 1117 rt2x00_set_field32(&reg, TXRX_CSR1_BBP_ID0, 47); /* CCK Signal */
1118 rt2x00_set_field32(&reg, TXRX_CSR1_BBP_ID0_VALID, 1);
1119 rt2x00_set_field32(&reg, TXRX_CSR1_BBP_ID1, 30); /* Rssi */
1120 rt2x00_set_field32(&reg, TXRX_CSR1_BBP_ID1_VALID, 1);
1121 rt2x00_set_field32(&reg, TXRX_CSR1_BBP_ID2, 42); /* OFDM Rate */
1122 rt2x00_set_field32(&reg, TXRX_CSR1_BBP_ID2_VALID, 1);
1123 rt2x00_set_field32(&reg, TXRX_CSR1_BBP_ID3, 30); /* Rssi */
1124 rt2x00_set_field32(&reg, TXRX_CSR1_BBP_ID3_VALID, 1);
0f829b1d 1125 rt2x00usb_register_write(rt2x00dev, TXRX_CSR1, reg);
95ea3627
ID		 1126
1127 /*
1128 * CCK TXD BBP registers
1129 */
0f829b1d 1130 rt2x00usb_register_read(rt2x00dev, TXRX_CSR2, &reg);
95ea3627
ID		 1131 rt2x00_set_field32(&reg, TXRX_CSR2_BBP_ID0, 13);
1132 rt2x00_set_field32(&reg, TXRX_CSR2_BBP_ID0_VALID, 1);
1133 rt2x00_set_field32(&reg, TXRX_CSR2_BBP_ID1, 12);
1134 rt2x00_set_field32(&reg, TXRX_CSR2_BBP_ID1_VALID, 1);
1135 rt2x00_set_field32(&reg, TXRX_CSR2_BBP_ID2, 11);
1136 rt2x00_set_field32(&reg, TXRX_CSR2_BBP_ID2_VALID, 1);
1137 rt2x00_set_field32(&reg, TXRX_CSR2_BBP_ID3, 10);
1138 rt2x00_set_field32(&reg, TXRX_CSR2_BBP_ID3_VALID, 1);
0f829b1d 1139 rt2x00usb_register_write(rt2x00dev, TXRX_CSR2, reg);
95ea3627
ID		 1140
1141 /*
1142 * OFDM TXD BBP registers
1143 */
0f829b1d 1144 rt2x00usb_register_read(rt2x00dev, TXRX_CSR3, &reg);
95ea3627
ID		 1145 rt2x00_set_field32(&reg, TXRX_CSR3_BBP_ID0, 7);
1146 rt2x00_set_field32(&reg, TXRX_CSR3_BBP_ID0_VALID, 1);
1147 rt2x00_set_field32(&reg, TXRX_CSR3_BBP_ID1, 6);
1148 rt2x00_set_field32(&reg, TXRX_CSR3_BBP_ID1_VALID, 1);
1149 rt2x00_set_field32(&reg, TXRX_CSR3_BBP_ID2, 5);
1150 rt2x00_set_field32(&reg, TXRX_CSR3_BBP_ID2_VALID, 1);
0f829b1d 1151 rt2x00usb_register_write(rt2x00dev, TXRX_CSR3, reg);
95ea3627 1152
0f829b1d 1153 rt2x00usb_register_read(rt2x00dev, TXRX_CSR7, &reg);
95ea3627
ID		 1154 rt2x00_set_field32(&reg, TXRX_CSR7_ACK_CTS_6MBS, 59);
1155 rt2x00_set_field32(&reg, TXRX_CSR7_ACK_CTS_9MBS, 53);
1156 rt2x00_set_field32(&reg, TXRX_CSR7_ACK_CTS_12MBS, 49);
1157 rt2x00_set_field32(&reg, TXRX_CSR7_ACK_CTS_18MBS, 46);
0f829b1d 1158 rt2x00usb_register_write(rt2x00dev, TXRX_CSR7, reg);
95ea3627 1159
0f829b1d 1160 rt2x00usb_register_read(rt2x00dev, TXRX_CSR8, &reg);
95ea3627
ID		 1161 rt2x00_set_field32(&reg, TXRX_CSR8_ACK_CTS_24MBS, 44);
1162 rt2x00_set_field32(&reg, TXRX_CSR8_ACK_CTS_36MBS, 42);
1163 rt2x00_set_field32(&reg, TXRX_CSR8_ACK_CTS_48MBS, 42);
1164 rt2x00_set_field32(&reg, TXRX_CSR8_ACK_CTS_54MBS, 42);
0f829b1d 1165 rt2x00usb_register_write(rt2x00dev, TXRX_CSR8, reg);
95ea3627 1166
0f829b1d 1167 rt2x00usb_register_read(rt2x00dev, TXRX_CSR9, &reg);
1f909162
ID		 1168 rt2x00_set_field32(&reg, TXRX_CSR9_BEACON_INTERVAL, 0);
1169 rt2x00_set_field32(&reg, TXRX_CSR9_TSF_TICKING, 0);
1170 rt2x00_set_field32(&reg, TXRX_CSR9_TSF_SYNC, 0);
1171 rt2x00_set_field32(&reg, TXRX_CSR9_TBTT_ENABLE, 0);
1172 rt2x00_set_field32(&reg, TXRX_CSR9_BEACON_GEN, 0);
1173 rt2x00_set_field32(&reg, TXRX_CSR9_TIMESTAMP_COMPENSATE, 0);
0f829b1d 1174 rt2x00usb_register_write(rt2x00dev, TXRX_CSR9, reg);
1f909162 1175
0f829b1d 1176 rt2x00usb_register_write(rt2x00dev, TXRX_CSR15, 0x0000000f);
95ea3627 1177
0f829b1d 1178 rt2x00usb_register_read(rt2x00dev, MAC_CSR6, &reg);
95ea3627 1179 rt2x00_set_field32(&reg, MAC_CSR6_MAX_FRAME_UNIT, 0xfff);
0f829b1d 1180 rt2x00usb_register_write(rt2x00dev, MAC_CSR6, reg);
95ea3627 1181
0f829b1d 1182 rt2x00usb_register_write(rt2x00dev, MAC_CSR10, 0x00000718);
95ea3627
ID		 1183
1184 if (rt2x00dev->ops->lib->set_device_state(rt2x00dev, STATE_AWAKE))
1185 return -EBUSY;
1186
0f829b1d 1187 rt2x00usb_register_write(rt2x00dev, MAC_CSR13, 0x00007f00);
95ea3627
ID		 1188
1189 /*
1190 * Invalidate all Shared Keys (SEC_CSR0),
1191 * and clear the Shared key Cipher algorithms (SEC_CSR1 & SEC_CSR5)
1192 */
0f829b1d
ID		 1193 rt2x00usb_register_write(rt2x00dev, SEC_CSR0, 0x00000000);
1194 rt2x00usb_register_write(rt2x00dev, SEC_CSR1, 0x00000000);
1195 rt2x00usb_register_write(rt2x00dev, SEC_CSR5, 0x00000000);
95ea3627
ID		 1196
1197 reg = 0x000023b0;
5122d898 1198 if (rt2x00_rf(rt2x00dev, RF5225) || rt2x00_rf(rt2x00dev, RF2527))
95ea3627 1199 rt2x00_set_field32(&reg, PHY_CSR1_RF_RPI, 1);
0f829b1d 1200 rt2x00usb_register_write(rt2x00dev, PHY_CSR1, reg);
95ea3627 1201
0f829b1d
ID		 1202 rt2x00usb_register_write(rt2x00dev, PHY_CSR5, 0x00040a06);
1203 rt2x00usb_register_write(rt2x00dev, PHY_CSR6, 0x00080606);
1204 rt2x00usb_register_write(rt2x00dev, PHY_CSR7, 0x00000408);
95ea3627 1205
0f829b1d 1206 rt2x00usb_register_read(rt2x00dev, MAC_CSR9, &reg);
95ea3627 1207 rt2x00_set_field32(&reg, MAC_CSR9_CW_SELECT, 0);
0f829b1d 1208 rt2x00usb_register_write(rt2x00dev, MAC_CSR9, reg);
95ea3627 1209
6bb40dd1
ID		 1210 /*
1211 * Clear all beacons
1212 * For the Beacon base registers we only need to clear
1213 * the first byte since that byte contains the VALID and OWNER
1214 * bits which (when set to 0) will invalidate the entire beacon.
1215 */
0f829b1d
ID		 1216 rt2x00usb_register_write(rt2x00dev, HW_BEACON_BASE0, 0);
1217 rt2x00usb_register_write(rt2x00dev, HW_BEACON_BASE1, 0);
1218 rt2x00usb_register_write(rt2x00dev, HW_BEACON_BASE2, 0);
1219 rt2x00usb_register_write(rt2x00dev, HW_BEACON_BASE3, 0);
6bb40dd1 1220
95ea3627
ID		 1221 /*
1222 * We must clear the error counters.
1223 * These registers are cleared on read,
1224 * so we may pass a useless variable to store the value.
1225 */
0f829b1d
ID		 1226 rt2x00usb_register_read(rt2x00dev, STA_CSR0, &reg);
1227 rt2x00usb_register_read(rt2x00dev, STA_CSR1, &reg);
1228 rt2x00usb_register_read(rt2x00dev, STA_CSR2, &reg);
95ea3627
ID		 1229
1230 /*
1231 * Reset MAC and BBP registers.
1232 */
0f829b1d 1233 rt2x00usb_register_read(rt2x00dev, MAC_CSR1, &reg);
95ea3627
ID		 1234 rt2x00_set_field32(&reg, MAC_CSR1_SOFT_RESET, 1);
1235 rt2x00_set_field32(&reg, MAC_CSR1_BBP_RESET, 1);
0f829b1d 1236 rt2x00usb_register_write(rt2x00dev, MAC_CSR1, reg);
95ea3627 1237
0f829b1d 1238 rt2x00usb_register_read(rt2x00dev, MAC_CSR1, &reg);
95ea3627
ID		 1239 rt2x00_set_field32(&reg, MAC_CSR1_SOFT_RESET, 0);
1240 rt2x00_set_field32(&reg, MAC_CSR1_BBP_RESET, 0);
0f829b1d 1241 rt2x00usb_register_write(rt2x00dev, MAC_CSR1, reg);
95ea3627 1242
0f829b1d 1243 rt2x00usb_register_read(rt2x00dev, MAC_CSR1, &reg);
95ea3627 1244 rt2x00_set_field32(&reg, MAC_CSR1_HOST_READY, 1);
0f829b1d 1245 rt2x00usb_register_write(rt2x00dev, MAC_CSR1, reg);
95ea3627
ID		 1246
1247 return 0;
1248}
1249
2b08da3f 1250static int rt73usb_wait_bbp_ready(struct rt2x00_dev *rt2x00dev)
95ea3627
ID		 1251{
1252 unsigned int i;
95ea3627
ID		 1253 u8 value;
1254
1255 for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
1256 rt73usb_bbp_read(rt2x00dev, 0, &value);
1257 if ((value != 0xff) && (value != 0x00))
2b08da3f 1258 return 0;
95ea3627
ID		 1259 udelay(REGISTER_BUSY_DELAY);
1260 }
1261
1262 ERROR(rt2x00dev, "BBP register access failed, aborting.\n");
1263 return -EACCES;
2b08da3f
ID		 1264}
1265
1266static int rt73usb_init_bbp(struct rt2x00_dev *rt2x00dev)
1267{
1268 unsigned int i;
1269 u16 eeprom;
1270 u8 reg_id;
1271 u8 value;
1272
1273 if (unlikely(rt73usb_wait_bbp_ready(rt2x00dev)))
1274 return -EACCES;
95ea3627 1275
95ea3627
ID		 1276 rt73usb_bbp_write(rt2x00dev, 3, 0x80);
1277 rt73usb_bbp_write(rt2x00dev, 15, 0x30);
1278 rt73usb_bbp_write(rt2x00dev, 21, 0xc8);
1279 rt73usb_bbp_write(rt2x00dev, 22, 0x38);
1280 rt73usb_bbp_write(rt2x00dev, 23, 0x06);
1281 rt73usb_bbp_write(rt2x00dev, 24, 0xfe);
1282 rt73usb_bbp_write(rt2x00dev, 25, 0x0a);
1283 rt73usb_bbp_write(rt2x00dev, 26, 0x0d);
1284 rt73usb_bbp_write(rt2x00dev, 32, 0x0b);
1285 rt73usb_bbp_write(rt2x00dev, 34, 0x12);
1286 rt73usb_bbp_write(rt2x00dev, 37, 0x07);
1287 rt73usb_bbp_write(rt2x00dev, 39, 0xf8);
1288 rt73usb_bbp_write(rt2x00dev, 41, 0x60);
1289 rt73usb_bbp_write(rt2x00dev, 53, 0x10);
1290 rt73usb_bbp_write(rt2x00dev, 54, 0x18);
1291 rt73usb_bbp_write(rt2x00dev, 60, 0x10);
1292 rt73usb_bbp_write(rt2x00dev, 61, 0x04);
1293 rt73usb_bbp_write(rt2x00dev, 62, 0x04);
1294 rt73usb_bbp_write(rt2x00dev, 75, 0xfe);
1295 rt73usb_bbp_write(rt2x00dev, 86, 0xfe);
1296 rt73usb_bbp_write(rt2x00dev, 88, 0xfe);
1297 rt73usb_bbp_write(rt2x00dev, 90, 0x0f);
1298 rt73usb_bbp_write(rt2x00dev, 99, 0x00);
1299 rt73usb_bbp_write(rt2x00dev, 102, 0x16);
1300 rt73usb_bbp_write(rt2x00dev, 107, 0x04);
1301
95ea3627
ID		 1302 for (i = 0; i < EEPROM_BBP_SIZE; i++) {
1303 rt2x00_eeprom_read(rt2x00dev, EEPROM_BBP_START + i, &eeprom);
1304
1305 if (eeprom != 0xffff && eeprom != 0x0000) {
1306 reg_id = rt2x00_get_field16(eeprom, EEPROM_BBP_REG_ID);
1307 value = rt2x00_get_field16(eeprom, EEPROM_BBP_VALUE);
95ea3627
ID		 1308 rt73usb_bbp_write(rt2x00dev, reg_id, value);
1309 }
1310 }
95ea3627
ID		 1311
1312 return 0;
1313}
1314
1315/*
1316 * Device state switch handlers.
1317 */
1318static void rt73usb_toggle_rx(struct rt2x00_dev *rt2x00dev,
1319 enum dev_state state)
1320{
1321 u32 reg;
1322
0f829b1d 1323 rt2x00usb_register_read(rt2x00dev, TXRX_CSR0, &reg);
95ea3627 1324 rt2x00_set_field32(&reg, TXRX_CSR0_DISABLE_RX,
2b08da3f
ID		 1325 (state == STATE_RADIO_RX_OFF) ||
1326 (state == STATE_RADIO_RX_OFF_LINK));
0f829b1d 1327 rt2x00usb_register_write(rt2x00dev, TXRX_CSR0, reg);
95ea3627
ID		 1328}
1329
1330static int rt73usb_enable_radio(struct rt2x00_dev *rt2x00dev)
1331{
1332 /*
1333 * Initialize all registers.
1334 */
2b08da3f
ID		 1335 if (unlikely(rt73usb_init_registers(rt2x00dev) ||
1336 rt73usb_init_bbp(rt2x00dev)))
95ea3627 1337 return -EIO;
95ea3627 1338
95ea3627
ID		 1339 return 0;
1340}
1341
1342static void rt73usb_disable_radio(struct rt2x00_dev *rt2x00dev)
1343{
0f829b1d 1344 rt2x00usb_register_write(rt2x00dev, MAC_CSR10, 0x00001818);
95ea3627
ID		 1345
1346 /*
1347 * Disable synchronisation.
1348 */
0f829b1d 1349 rt2x00usb_register_write(rt2x00dev, TXRX_CSR9, 0);
95ea3627
ID		 1350
1351 rt2x00usb_disable_radio(rt2x00dev);
1352}
1353
1354static int rt73usb_set_state(struct rt2x00_dev *rt2x00dev, enum dev_state state)
1355{
9655a6ec 1356 u32 reg, reg2;
95ea3627
ID		 1357 unsigned int i;
1358 char put_to_sleep;
95ea3627
ID		 1359
1360 put_to_sleep = (state != STATE_AWAKE);
1361
0f829b1d 1362 rt2x00usb_register_read(rt2x00dev, MAC_CSR12, &reg);
95ea3627
ID		 1363 rt2x00_set_field32(&reg, MAC_CSR12_FORCE_WAKEUP, !put_to_sleep);
1364 rt2x00_set_field32(&reg, MAC_CSR12_PUT_TO_SLEEP, put_to_sleep);
0f829b1d 1365 rt2x00usb_register_write(rt2x00dev, MAC_CSR12, reg);
95ea3627
ID		 1366
1367 /*
1368 * Device is not guaranteed to be in the requested state yet.
1369 * We must wait until the register indicates that the
1370 * device has entered the correct state.
1371 */
1372 for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
9655a6ec
GW		 1373 rt2x00usb_register_read(rt2x00dev, MAC_CSR12, &reg2);
1374 state = rt2x00_get_field32(reg2, MAC_CSR12_BBP_CURRENT_STATE);
2b08da3f 1375 if (state == !put_to_sleep)
95ea3627 1376 return 0;
9655a6ec 1377 rt2x00usb_register_write(rt2x00dev, MAC_CSR12, reg);
95ea3627
ID		 1378 msleep(10);
1379 }
1380
95ea3627
ID		 1381 return -EBUSY;
1382}
1383
1384static int rt73usb_set_device_state(struct rt2x00_dev *rt2x00dev,
1385 enum dev_state state)
1386{
1387 int retval = 0;
1388
1389 switch (state) {
1390 case STATE_RADIO_ON:
1391 retval = rt73usb_enable_radio(rt2x00dev);
1392 break;
1393 case STATE_RADIO_OFF:
1394 rt73usb_disable_radio(rt2x00dev);
1395 break;
1396 case STATE_RADIO_RX_ON:
61667d8d 1397 case STATE_RADIO_RX_ON_LINK:
95ea3627 1398 case STATE_RADIO_RX_OFF:
61667d8d 1399 case STATE_RADIO_RX_OFF_LINK:
2b08da3f
ID		 1400 rt73usb_toggle_rx(rt2x00dev, state);
1401 break;
1402 case STATE_RADIO_IRQ_ON:
1403 case STATE_RADIO_IRQ_OFF:
1404 /* No support, but no error either */
95ea3627
ID		 1405 break;
1406 case STATE_DEEP_SLEEP:
1407 case STATE_SLEEP:
1408 case STATE_STANDBY:
1409 case STATE_AWAKE:
1410 retval = rt73usb_set_state(rt2x00dev, state);
1411 break;
1412 default:
1413 retval = -ENOTSUPP;
1414 break;
1415 }
1416
2b08da3f
ID		 1417 if (unlikely(retval))
1418 ERROR(rt2x00dev, "Device failed to enter state %d (%d).\n",
1419 state, retval);
1420
95ea3627
ID		 1421 return retval;
1422}
1423
1424/*
1425 * TX descriptor initialization
1426 */
1427static void rt73usb_write_tx_desc(struct rt2x00_dev *rt2x00dev,
906c110f
ID		 1428 struct sk_buff *skb,
1429 struct txentry_desc *txdesc)
95ea3627 1430{
181d6902 1431 struct skb_frame_desc *skbdesc = get_skb_frame_desc(skb);
0b8004aa 1432 __le32 *txd = (__le32 *) skb->data;
95ea3627
ID		 1433 u32 word;
1434
1435 /*
1436 * Start writing the descriptor words.
1437 */
e01f1ec3
GW		 1438 rt2x00_desc_read(txd, 0, &word);
1439 rt2x00_set_field32(&word, TXD_W0_BURST,
1440 test_bit(ENTRY_TXD_BURST, &txdesc->flags));
1441 rt2x00_set_field32(&word, TXD_W0_VALID, 1);
1442 rt2x00_set_field32(&word, TXD_W0_MORE_FRAG,
1443 test_bit(ENTRY_TXD_MORE_FRAG, &txdesc->flags));
1444 rt2x00_set_field32(&word, TXD_W0_ACK,
1445 test_bit(ENTRY_TXD_ACK, &txdesc->flags));
1446 rt2x00_set_field32(&word, TXD_W0_TIMESTAMP,
1447 test_bit(ENTRY_TXD_REQ_TIMESTAMP, &txdesc->flags));
1448 rt2x00_set_field32(&word, TXD_W0_OFDM,
1449 (txdesc->rate_mode == RATE_MODE_OFDM));
1450 rt2x00_set_field32(&word, TXD_W0_IFS, txdesc->ifs);
1451 rt2x00_set_field32(&word, TXD_W0_RETRY_MODE,
1452 test_bit(ENTRY_TXD_RETRY_MODE, &txdesc->flags));
1453 rt2x00_set_field32(&word, TXD_W0_TKIP_MIC,
1454 test_bit(ENTRY_TXD_ENCRYPT_MMIC, &txdesc->flags));
1455 rt2x00_set_field32(&word, TXD_W0_KEY_TABLE,
1456 test_bit(ENTRY_TXD_ENCRYPT_PAIRWISE, &txdesc->flags));
1457 rt2x00_set_field32(&word, TXD_W0_KEY_INDEX, txdesc->key_idx);
1458 rt2x00_set_field32(&word, TXD_W0_DATABYTE_COUNT, txdesc->length);
1459 rt2x00_set_field32(&word, TXD_W0_BURST2,
1460 test_bit(ENTRY_TXD_BURST, &txdesc->flags));
1461 rt2x00_set_field32(&word, TXD_W0_CIPHER_ALG, txdesc->cipher);
1462 rt2x00_desc_write(txd, 0, word);
1463
95ea3627 1464 rt2x00_desc_read(txd, 1, &word);
181d6902
ID		 1465 rt2x00_set_field32(&word, TXD_W1_HOST_Q_ID, txdesc->queue);
1466 rt2x00_set_field32(&word, TXD_W1_AIFSN, txdesc->aifs);
1467 rt2x00_set_field32(&word, TXD_W1_CWMIN, txdesc->cw_min);
1468 rt2x00_set_field32(&word, TXD_W1_CWMAX, txdesc->cw_max);
906c110f 1469 rt2x00_set_field32(&word, TXD_W1_IV_OFFSET, txdesc->iv_offset);
5adf6d63
ID		 1470 rt2x00_set_field32(&word, TXD_W1_HW_SEQUENCE,
1471 test_bit(ENTRY_TXD_GENERATE_SEQ, &txdesc->flags));
95ea3627
ID		 1472 rt2x00_desc_write(txd, 1, word);
1473
1474 rt2x00_desc_read(txd, 2, &word);
181d6902
ID		 1475 rt2x00_set_field32(&word, TXD_W2_PLCP_SIGNAL, txdesc->signal);
1476 rt2x00_set_field32(&word, TXD_W2_PLCP_SERVICE, txdesc->service);
1477 rt2x00_set_field32(&word, TXD_W2_PLCP_LENGTH_LOW, txdesc->length_low);
1478 rt2x00_set_field32(&word, TXD_W2_PLCP_LENGTH_HIGH, txdesc->length_high);
95ea3627
ID		 1479 rt2x00_desc_write(txd, 2, word);
1480
906c110f 1481 if (test_bit(ENTRY_TXD_ENCRYPT, &txdesc->flags)) {
1ce9cdac
ID		 1482 _rt2x00_desc_write(txd, 3, skbdesc->iv[0]);
1483 _rt2x00_desc_write(txd, 4, skbdesc->iv[1]);
906c110f
ID		 1484 }
1485
95ea3627
ID		 1486 rt2x00_desc_read(txd, 5, &word);
1487 rt2x00_set_field32(&word, TXD_W5_TX_POWER,
ac1aa7e4 1488 TXPOWER_TO_DEV(rt2x00dev->tx_power));
95ea3627
ID		 1489 rt2x00_set_field32(&word, TXD_W5_WAITING_DMA_DONE_INT, 1);
1490 rt2x00_desc_write(txd, 5, word);
1491
85b7a8b3
GW		 1492 /*
1493 * Register descriptor details in skb frame descriptor.
1494 */
0b8004aa 1495 skbdesc->flags |= SKBDESC_DESC_IN_SKB;
85b7a8b3
GW		 1496 skbdesc->desc = txd;
1497 skbdesc->desc_len = TXD_DESC_SIZE;
95ea3627
ID		 1498}
1499
bd88a781
ID		 1500/*
1501 * TX data initialization
1502 */
f224f4ef
GW		 1503static void rt73usb_write_beacon(struct queue_entry *entry,
1504 struct txentry_desc *txdesc)
bd88a781
ID		 1505{
1506 struct rt2x00_dev *rt2x00dev = entry->queue->rt2x00dev;
bd88a781
ID		 1507 unsigned int beacon_base;
1508 u32 reg;
1509
bd88a781
ID		 1510 /*
1511 * Disable beaconing while we are reloading the beacon data,
1512 * otherwise we might be sending out invalid data.
1513 */
0f829b1d 1514 rt2x00usb_register_read(rt2x00dev, TXRX_CSR9, &reg);
bd88a781 1515 rt2x00_set_field32(&reg, TXRX_CSR9_BEACON_GEN, 0);
0f829b1d 1516 rt2x00usb_register_write(rt2x00dev, TXRX_CSR9, reg);
bd88a781 1517
0b8004aa
GW		 1518 /*
1519 * Add space for the descriptor in front of the skb.
1520 */
1521 skb_push(entry->skb, TXD_DESC_SIZE);
1522 memset(entry->skb->data, 0, TXD_DESC_SIZE);
1523
5c3b685c
GW		 1524 /*
1525 * Write the TX descriptor for the beacon.
1526 */
1527 rt73usb_write_tx_desc(rt2x00dev, entry->skb, txdesc);
1528
1529 /*
1530 * Dump beacon to userspace through debugfs.
1531 */
1532 rt2x00debug_dump_frame(rt2x00dev, DUMP_FRAME_BEACON, entry->skb);
1533
bd88a781
ID		 1534 /*
1535 * Write entire beacon with descriptor to register.
1536 */
1537 beacon_base = HW_BEACON_OFFSET(entry->entry_idx);
96b61baf
GW		 1538 rt2x00usb_register_multiwrite(rt2x00dev, beacon_base,
1539 entry->skb->data, entry->skb->len);
bd88a781 1540
d61cb266
GW		 1541 /*
1542 * Enable beaconing again.
1543 *
1544 * For Wi-Fi faily generated beacons between participating stations.
1545 * Set TBTT phase adaptive adjustment step to 8us (default 16us)
1546 */
1547 rt2x00usb_register_write(rt2x00dev, TXRX_CSR10, 0x00001008);
1548
1549 rt2x00_set_field32(&reg, TXRX_CSR9_TSF_TICKING, 1);
1550 rt2x00_set_field32(&reg, TXRX_CSR9_TBTT_ENABLE, 1);
1551 rt2x00_set_field32(&reg, TXRX_CSR9_BEACON_GEN, 1);
1552 rt2x00usb_register_write(rt2x00dev, TXRX_CSR9, reg);
1553
bd88a781
ID		 1554 /*
1555 * Clean up the beacon skb.
1556 */
1557 dev_kfree_skb(entry->skb);
1558 entry->skb = NULL;
1559}
1560
f1ca2167 1561static int rt73usb_get_tx_data_len(struct queue_entry *entry)
dd9fa2d2
ID		 1562{
1563 int length;
1564
1565 /*
1566 * The length _must_ be a multiple of 4,
1567 * but it must _not_ be a multiple of the USB packet size.
1568 */
f1ca2167
ID		 1569 length = roundup(entry->skb->len, 4);
1570 length += (4 * !(length % entry->queue->usb_maxpacket));
dd9fa2d2
ID		 1571
1572 return length;
1573}
1574
95ea3627
ID		 1575/*
1576 * RX control handlers
1577 */
1578static int rt73usb_agc_to_rssi(struct rt2x00_dev *rt2x00dev, int rxd_w1)
1579{
ba2ab471 1580 u8 offset = rt2x00dev->lna_gain;
95ea3627
ID		 1581 u8 lna;
1582
1583 lna = rt2x00_get_field32(rxd_w1, RXD_W1_RSSI_LNA);
1584 switch (lna) {
1585 case 3:
ba2ab471 1586 offset += 90;
95ea3627
ID		 1587 break;
1588 case 2:
ba2ab471 1589 offset += 74;
95ea3627
ID		 1590 break;
1591 case 1:
ba2ab471 1592 offset += 64;
95ea3627
ID		 1593 break;
1594 default:
1595 return 0;
1596 }
1597
8318d78a 1598 if (rt2x00dev->rx_status.band == IEEE80211_BAND_5GHZ) {
95ea3627
ID		 1599 if (test_bit(CONFIG_EXTERNAL_LNA_A, &rt2x00dev->flags)) {
1600 if (lna == 3 || lna == 2)
1601 offset += 10;
1602 } else {
1603 if (lna == 3)
1604 offset += 6;
1605 else if (lna == 2)
1606 offset += 8;
1607 }
95ea3627
ID		 1608 }
1609
1610 return rt2x00_get_field32(rxd_w1, RXD_W1_RSSI_AGC) * 2 - offset;
1611}
1612
181d6902 1613static void rt73usb_fill_rxdone(struct queue_entry *entry,
55887511 1614 struct rxdone_entry_desc *rxdesc)
95ea3627 1615{
906c110f 1616 struct rt2x00_dev *rt2x00dev = entry->queue->rt2x00dev;
181d6902 1617 struct skb_frame_desc *skbdesc = get_skb_frame_desc(entry->skb);
4bd7c452 1618 __le32 *rxd = (__le32 *)entry->skb->data;
95ea3627
ID		 1619 u32 word0;
1620 u32 word1;
1621
f855c10b 1622 /*
a26cbc65
GW		 1623 * Copy descriptor to the skbdesc->desc buffer, making it safe from moving of
1624 * frame data in rt2x00usb.
f855c10b 1625 */
a26cbc65 1626 memcpy(skbdesc->desc, rxd, skbdesc->desc_len);
70a96109 1627 rxd = (__le32 *)skbdesc->desc;
f855c10b
ID		 1628
1629 /*
70a96109 1630 * It is now safe to read the descriptor on all architectures.
f855c10b 1631 */
95ea3627
ID		 1632 rt2x00_desc_read(rxd, 0, &word0);
1633 rt2x00_desc_read(rxd, 1, &word1);
1634
4150c572 1635 if (rt2x00_get_field32(word0, RXD_W0_CRC_ERROR))
181d6902 1636 rxdesc->flags |= RX_FLAG_FAILED_FCS_CRC;
95ea3627 1637
78b8f3b0
GW		 1638 rxdesc->cipher = rt2x00_get_field32(word0, RXD_W0_CIPHER_ALG);
1639 rxdesc->cipher_status = rt2x00_get_field32(word0, RXD_W0_CIPHER_ERROR);
906c110f
ID		 1640
1641 if (rxdesc->cipher != CIPHER_NONE) {
1ce9cdac
ID		 1642 _rt2x00_desc_read(rxd, 2, &rxdesc->iv[0]);
1643 _rt2x00_desc_read(rxd, 3, &rxdesc->iv[1]);
74415edb
ID		 1644 rxdesc->dev_flags |= RXDONE_CRYPTO_IV;
1645
906c110f 1646 _rt2x00_desc_read(rxd, 4, &rxdesc->icv);
74415edb 1647 rxdesc->dev_flags |= RXDONE_CRYPTO_ICV;
906c110f
ID		 1648
1649 /*
1650 * Hardware has stripped IV/EIV data from 802.11 frame during
3ad2f3fb 1651 * decryption. It has provided the data separately but rt2x00lib
906c110f
ID		 1652 * should decide if it should be reinserted.
1653 */
1654 rxdesc->flags |= RX_FLAG_IV_STRIPPED;
1655
1656 /*
1657 * FIXME: Legacy driver indicates that the frame does
1658 * contain the Michael Mic. Unfortunately, in rt2x00
1659 * the MIC seems to be missing completely...
1660 */
1661 rxdesc->flags |= RX_FLAG_MMIC_STRIPPED;
1662
1663 if (rxdesc->cipher_status == RX_CRYPTO_SUCCESS)
1664 rxdesc->flags |= RX_FLAG_DECRYPTED;
1665 else if (rxdesc->cipher_status == RX_CRYPTO_FAIL_MIC)
1666 rxdesc->flags |= RX_FLAG_MMIC_ERROR;
1667 }
1668
95ea3627
ID		 1669 /*
1670 * Obtain the status about this packet.
89993890
ID		 1671 * When frame was received with an OFDM bitrate,
1672 * the signal is the PLCP value. If it was received with
1673 * a CCK bitrate the signal is the rate in 100kbit/s.
95ea3627 1674 */
181d6902 1675 rxdesc->signal = rt2x00_get_field32(word1, RXD_W1_SIGNAL);
906c110f 1676 rxdesc->rssi = rt73usb_agc_to_rssi(rt2x00dev, word1);
181d6902 1677 rxdesc->size = rt2x00_get_field32(word0, RXD_W0_DATABYTE_COUNT);
19d30e02 1678
19d30e02
ID		 1679 if (rt2x00_get_field32(word0, RXD_W0_OFDM))
1680 rxdesc->dev_flags |= RXDONE_SIGNAL_PLCP;
6c6aa3c0
ID		 1681 else
1682 rxdesc->dev_flags |= RXDONE_SIGNAL_BITRATE;
19d30e02
ID		 1683 if (rt2x00_get_field32(word0, RXD_W0_MY_BSS))
1684 rxdesc->dev_flags |= RXDONE_MY_BSS;
181d6902 1685
2ae23854 1686 /*
70a96109 1687 * Set skb pointers, and update frame information.
2ae23854 1688 */
70a96109 1689 skb_pull(entry->skb, entry->queue->desc_size);
2ae23854 1690 skb_trim(entry->skb, rxdesc->size);
95ea3627
ID		 1691}
1692
1693/*
1694 * Device probe functions.
1695 */
1696static int rt73usb_validate_eeprom(struct rt2x00_dev *rt2x00dev)
1697{
1698 u16 word;
1699 u8 *mac;
1700 s8 value;
1701
1702 rt2x00usb_eeprom_read(rt2x00dev, rt2x00dev->eeprom, EEPROM_SIZE);
1703
1704 /*
1705 * Start validation of the data that has been read.
1706 */
1707 mac = rt2x00_eeprom_addr(rt2x00dev, EEPROM_MAC_ADDR_0);
1708 if (!is_valid_ether_addr(mac)) {
1709 random_ether_addr(mac);
e174961c 1710 EEPROM(rt2x00dev, "MAC: %pM\n", mac);
95ea3627
ID		 1711 }
1712
1713 rt2x00_eeprom_read(rt2x00dev, EEPROM_ANTENNA, &word);
1714 if (word == 0xffff) {
1715 rt2x00_set_field16(&word, EEPROM_ANTENNA_NUM, 2);
362f3b6b
ID		 1716 rt2x00_set_field16(&word, EEPROM_ANTENNA_TX_DEFAULT,
1717 ANTENNA_B);
1718 rt2x00_set_field16(&word, EEPROM_ANTENNA_RX_DEFAULT,
1719 ANTENNA_B);
95ea3627
ID		 1720 rt2x00_set_field16(&word, EEPROM_ANTENNA_FRAME_TYPE, 0);
1721 rt2x00_set_field16(&word, EEPROM_ANTENNA_DYN_TXAGC, 0);
1722 rt2x00_set_field16(&word, EEPROM_ANTENNA_HARDWARE_RADIO, 0);
1723 rt2x00_set_field16(&word, EEPROM_ANTENNA_RF_TYPE, RF5226);
1724 rt2x00_eeprom_write(rt2x00dev, EEPROM_ANTENNA, word);
1725 EEPROM(rt2x00dev, "Antenna: 0x%04x\n", word);
1726 }
1727
1728 rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC, &word);
1729 if (word == 0xffff) {
1730 rt2x00_set_field16(&word, EEPROM_NIC_EXTERNAL_LNA, 0);
1731 rt2x00_eeprom_write(rt2x00dev, EEPROM_NIC, word);
1732 EEPROM(rt2x00dev, "NIC: 0x%04x\n", word);
1733 }
1734
1735 rt2x00_eeprom_read(rt2x00dev, EEPROM_LED, &word);
1736 if (word == 0xffff) {
1737 rt2x00_set_field16(&word, EEPROM_LED_POLARITY_RDY_G, 0);
1738 rt2x00_set_field16(&word, EEPROM_LED_POLARITY_RDY_A, 0);
1739 rt2x00_set_field16(&word, EEPROM_LED_POLARITY_ACT, 0);
1740 rt2x00_set_field16(&word, EEPROM_LED_POLARITY_GPIO_0, 0);
1741 rt2x00_set_field16(&word, EEPROM_LED_POLARITY_GPIO_1, 0);
1742 rt2x00_set_field16(&word, EEPROM_LED_POLARITY_GPIO_2, 0);
1743 rt2x00_set_field16(&word, EEPROM_LED_POLARITY_GPIO_3, 0);
1744 rt2x00_set_field16(&word, EEPROM_LED_POLARITY_GPIO_4, 0);
1745 rt2x00_set_field16(&word, EEPROM_LED_LED_MODE,
1746 LED_MODE_DEFAULT);
1747 rt2x00_eeprom_write(rt2x00dev, EEPROM_LED, word);
1748 EEPROM(rt2x00dev, "Led: 0x%04x\n", word);
1749 }
1750
1751 rt2x00_eeprom_read(rt2x00dev, EEPROM_FREQ, &word);
1752 if (word == 0xffff) {
1753 rt2x00_set_field16(&word, EEPROM_FREQ_OFFSET, 0);
1754 rt2x00_set_field16(&word, EEPROM_FREQ_SEQ, 0);
1755 rt2x00_eeprom_write(rt2x00dev, EEPROM_FREQ, word);
1756 EEPROM(rt2x00dev, "Freq: 0x%04x\n", word);
1757 }
1758
1759 rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_OFFSET_BG, &word);
1760 if (word == 0xffff) {
1761 rt2x00_set_field16(&word, EEPROM_RSSI_OFFSET_BG_1, 0);
1762 rt2x00_set_field16(&word, EEPROM_RSSI_OFFSET_BG_2, 0);
1763 rt2x00_eeprom_write(rt2x00dev, EEPROM_RSSI_OFFSET_BG, word);
1764 EEPROM(rt2x00dev, "RSSI OFFSET BG: 0x%04x\n", word);
1765 } else {
1766 value = rt2x00_get_field16(word, EEPROM_RSSI_OFFSET_BG_1);
1767 if (value < -10 || value > 10)
1768 rt2x00_set_field16(&word, EEPROM_RSSI_OFFSET_BG_1, 0);
1769 value = rt2x00_get_field16(word, EEPROM_RSSI_OFFSET_BG_2);
1770 if (value < -10 || value > 10)
1771 rt2x00_set_field16(&word, EEPROM_RSSI_OFFSET_BG_2, 0);
1772 rt2x00_eeprom_write(rt2x00dev, EEPROM_RSSI_OFFSET_BG, word);
1773 }
1774
1775 rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_OFFSET_A, &word);
1776 if (word == 0xffff) {
1777 rt2x00_set_field16(&word, EEPROM_RSSI_OFFSET_A_1, 0);
1778 rt2x00_set_field16(&word, EEPROM_RSSI_OFFSET_A_2, 0);
1779 rt2x00_eeprom_write(rt2x00dev, EEPROM_RSSI_OFFSET_A, word);
417f412f 1780 EEPROM(rt2x00dev, "RSSI OFFSET A: 0x%04x\n", word);
95ea3627
ID		 1781 } else {
1782 value = rt2x00_get_field16(word, EEPROM_RSSI_OFFSET_A_1);
1783 if (value < -10 || value > 10)
1784 rt2x00_set_field16(&word, EEPROM_RSSI_OFFSET_A_1, 0);
1785 value = rt2x00_get_field16(word, EEPROM_RSSI_OFFSET_A_2);
1786 if (value < -10 || value > 10)
1787 rt2x00_set_field16(&word, EEPROM_RSSI_OFFSET_A_2, 0);
1788 rt2x00_eeprom_write(rt2x00dev, EEPROM_RSSI_OFFSET_A, word);
1789 }
1790
1791 return 0;
1792}
1793
1794static int rt73usb_init_eeprom(struct rt2x00_dev *rt2x00dev)
1795{
1796 u32 reg;
1797 u16 value;
1798 u16 eeprom;
1799
1800 /*
1801 * Read EEPROM word for configuration.
1802 */
1803 rt2x00_eeprom_read(rt2x00dev, EEPROM_ANTENNA, &eeprom);
1804
1805 /*
1806 * Identify RF chipset.
1807 */
1808 value = rt2x00_get_field16(eeprom, EEPROM_ANTENNA_RF_TYPE);
0f829b1d 1809 rt2x00usb_register_read(rt2x00dev, MAC_CSR0, &reg);
49e721ec
GW		 1810 rt2x00_set_chip(rt2x00dev, rt2x00_get_field32(reg, MAC_CSR0_CHIPSET),
1811 value, rt2x00_get_field32(reg, MAC_CSR0_REVISION));
95ea3627 1812
49e721ec 1813 if (!rt2x00_rt(rt2x00dev, RT2573) || (rt2x00_rev(rt2x00dev) == 0)) {
95ea3627
ID		 1814 ERROR(rt2x00dev, "Invalid RT chipset detected.\n");
1815 return -ENODEV;
1816 }
1817
5122d898
GW		 1818 if (!rt2x00_rf(rt2x00dev, RF5226) &&
1819 !rt2x00_rf(rt2x00dev, RF2528) &&
1820 !rt2x00_rf(rt2x00dev, RF5225) &&
1821 !rt2x00_rf(rt2x00dev, RF2527)) {
95ea3627
ID		 1822 ERROR(rt2x00dev, "Invalid RF chipset detected.\n");
1823 return -ENODEV;
1824 }
1825
1826 /*
1827 * Identify default antenna configuration.
1828 */
addc81bd 1829 rt2x00dev->default_ant.tx =
95ea3627 1830 rt2x00_get_field16(eeprom, EEPROM_ANTENNA_TX_DEFAULT);
addc81bd 1831 rt2x00dev->default_ant.rx =
95ea3627
ID		 1832 rt2x00_get_field16(eeprom, EEPROM_ANTENNA_RX_DEFAULT);
1833
1834 /*
1835 * Read the Frame type.
1836 */
1837 if (rt2x00_get_field16(eeprom, EEPROM_ANTENNA_FRAME_TYPE))
1838 __set_bit(CONFIG_FRAME_TYPE, &rt2x00dev->flags);
1839
7396faf4
ID		 1840 /*
1841 * Detect if this device has an hardware controlled radio.
1842 */
7396faf4
ID		 1843 if (rt2x00_get_field16(eeprom, EEPROM_ANTENNA_HARDWARE_RADIO))
1844 __set_bit(CONFIG_SUPPORT_HW_BUTTON, &rt2x00dev->flags);
7396faf4 1845
95ea3627
ID		 1846 /*
1847 * Read frequency offset.
1848 */
1849 rt2x00_eeprom_read(rt2x00dev, EEPROM_FREQ, &eeprom);
1850 rt2x00dev->freq_offset = rt2x00_get_field16(eeprom, EEPROM_FREQ_OFFSET);
1851
1852 /*
1853 * Read external LNA informations.
1854 */
1855 rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC, &eeprom);
1856
1857 if (rt2x00_get_field16(eeprom, EEPROM_NIC_EXTERNAL_LNA)) {
1858 __set_bit(CONFIG_EXTERNAL_LNA_A, &rt2x00dev->flags);
1859 __set_bit(CONFIG_EXTERNAL_LNA_BG, &rt2x00dev->flags);
1860 }
1861
1862 /*
1863 * Store led settings, for correct led behaviour.
1864 */
771fd565 1865#ifdef CONFIG_RT2X00_LIB_LEDS
95ea3627
ID		 1866 rt2x00_eeprom_read(rt2x00dev, EEPROM_LED, &eeprom);
1867
475433be
ID		 1868 rt73usb_init_led(rt2x00dev, &rt2x00dev->led_radio, LED_TYPE_RADIO);
1869 rt73usb_init_led(rt2x00dev, &rt2x00dev->led_assoc, LED_TYPE_ASSOC);
1870 if (value == LED_MODE_SIGNAL_STRENGTH)
1871 rt73usb_init_led(rt2x00dev, &rt2x00dev->led_qual,
1872 LED_TYPE_QUALITY);
a9450b70
ID		 1873
1874 rt2x00_set_field16(&rt2x00dev->led_mcu_reg, MCU_LEDCS_LED_MODE, value);
1875 rt2x00_set_field16(&rt2x00dev->led_mcu_reg, MCU_LEDCS_POLARITY_GPIO_0,
95ea3627
ID		 1876 rt2x00_get_field16(eeprom,
1877 EEPROM_LED_POLARITY_GPIO_0));
a9450b70 1878 rt2x00_set_field16(&rt2x00dev->led_mcu_reg, MCU_LEDCS_POLARITY_GPIO_1,
95ea3627
ID		 1879 rt2x00_get_field16(eeprom,
1880 EEPROM_LED_POLARITY_GPIO_1));
a9450b70 1881 rt2x00_set_field16(&rt2x00dev->led_mcu_reg, MCU_LEDCS_POLARITY_GPIO_2,
95ea3627
ID		 1882 rt2x00_get_field16(eeprom,
1883 EEPROM_LED_POLARITY_GPIO_2));
a9450b70 1884 rt2x00_set_field16(&rt2x00dev->led_mcu_reg, MCU_LEDCS_POLARITY_GPIO_3,
95ea3627
ID		 1885 rt2x00_get_field16(eeprom,
1886 EEPROM_LED_POLARITY_GPIO_3));
a9450b70 1887 rt2x00_set_field16(&rt2x00dev->led_mcu_reg, MCU_LEDCS_POLARITY_GPIO_4,
95ea3627
ID		 1888 rt2x00_get_field16(eeprom,
1889 EEPROM_LED_POLARITY_GPIO_4));
a9450b70 1890 rt2x00_set_field16(&rt2x00dev->led_mcu_reg, MCU_LEDCS_POLARITY_ACT,
95ea3627 1891 rt2x00_get_field16(eeprom, EEPROM_LED_POLARITY_ACT));
a9450b70 1892 rt2x00_set_field16(&rt2x00dev->led_mcu_reg, MCU_LEDCS_POLARITY_READY_BG,
95ea3627
ID		 1893 rt2x00_get_field16(eeprom,
1894 EEPROM_LED_POLARITY_RDY_G));
a9450b70 1895 rt2x00_set_field16(&rt2x00dev->led_mcu_reg, MCU_LEDCS_POLARITY_READY_A,
95ea3627
ID		 1896 rt2x00_get_field16(eeprom,
1897 EEPROM_LED_POLARITY_RDY_A));
771fd565 1898#endif /* CONFIG_RT2X00_LIB_LEDS */
95ea3627
ID		 1899
1900 return 0;
1901}
1902
1903/*
1904 * RF value list for RF2528
1905 * Supports: 2.4 GHz
1906 */
1907static const struct rf_channel rf_vals_bg_2528[] = {
1908 { 1, 0x00002c0c, 0x00000786, 0x00068255, 0x000fea0b },
1909 { 2, 0x00002c0c, 0x00000786, 0x00068255, 0x000fea1f },
1910 { 3, 0x00002c0c, 0x0000078a, 0x00068255, 0x000fea0b },
1911 { 4, 0x00002c0c, 0x0000078a, 0x00068255, 0x000fea1f },
1912 { 5, 0x00002c0c, 0x0000078e, 0x00068255, 0x000fea0b },
1913 { 6, 0x00002c0c, 0x0000078e, 0x00068255, 0x000fea1f },
1914 { 7, 0x00002c0c, 0x00000792, 0x00068255, 0x000fea0b },
1915 { 8, 0x00002c0c, 0x00000792, 0x00068255, 0x000fea1f },
1916 { 9, 0x00002c0c, 0x00000796, 0x00068255, 0x000fea0b },
1917 { 10, 0x00002c0c, 0x00000796, 0x00068255, 0x000fea1f },
1918 { 11, 0x00002c0c, 0x0000079a, 0x00068255, 0x000fea0b },
1919 { 12, 0x00002c0c, 0x0000079a, 0x00068255, 0x000fea1f },
1920 { 13, 0x00002c0c, 0x0000079e, 0x00068255, 0x000fea0b },
1921 { 14, 0x00002c0c, 0x000007a2, 0x00068255, 0x000fea13 },
1922};
1923
1924/*
1925 * RF value list for RF5226
1926 * Supports: 2.4 GHz & 5.2 GHz
1927 */
1928static const struct rf_channel rf_vals_5226[] = {
1929 { 1, 0x00002c0c, 0x00000786, 0x00068255, 0x000fea0b },
1930 { 2, 0x00002c0c, 0x00000786, 0x00068255, 0x000fea1f },
1931 { 3, 0x00002c0c, 0x0000078a, 0x00068255, 0x000fea0b },
1932 { 4, 0x00002c0c, 0x0000078a, 0x00068255, 0x000fea1f },
1933 { 5, 0x00002c0c, 0x0000078e, 0x00068255, 0x000fea0b },
1934 { 6, 0x00002c0c, 0x0000078e, 0x00068255, 0x000fea1f },
1935 { 7, 0x00002c0c, 0x00000792, 0x00068255, 0x000fea0b },
1936 { 8, 0x00002c0c, 0x00000792, 0x00068255, 0x000fea1f },
1937 { 9, 0x00002c0c, 0x00000796, 0x00068255, 0x000fea0b },
1938 { 10, 0x00002c0c, 0x00000796, 0x00068255, 0x000fea1f },
1939 { 11, 0x00002c0c, 0x0000079a, 0x00068255, 0x000fea0b },
1940 { 12, 0x00002c0c, 0x0000079a, 0x00068255, 0x000fea1f },
1941 { 13, 0x00002c0c, 0x0000079e, 0x00068255, 0x000fea0b },
1942 { 14, 0x00002c0c, 0x000007a2, 0x00068255, 0x000fea13 },
1943
1944 /* 802.11 UNI / HyperLan 2 */
1945 { 36, 0x00002c0c, 0x0000099a, 0x00098255, 0x000fea23 },
1946 { 40, 0x00002c0c, 0x000009a2, 0x00098255, 0x000fea03 },
1947 { 44, 0x00002c0c, 0x000009a6, 0x00098255, 0x000fea0b },
1948 { 48, 0x00002c0c, 0x000009aa, 0x00098255, 0x000fea13 },
1949 { 52, 0x00002c0c, 0x000009ae, 0x00098255, 0x000fea1b },
1950 { 56, 0x00002c0c, 0x000009b2, 0x00098255, 0x000fea23 },
1951 { 60, 0x00002c0c, 0x000009ba, 0x00098255, 0x000fea03 },
1952 { 64, 0x00002c0c, 0x000009be, 0x00098255, 0x000fea0b },
1953
1954 /* 802.11 HyperLan 2 */
1955 { 100, 0x00002c0c, 0x00000a2a, 0x000b8255, 0x000fea03 },
1956 { 104, 0x00002c0c, 0x00000a2e, 0x000b8255, 0x000fea0b },
1957 { 108, 0x00002c0c, 0x00000a32, 0x000b8255, 0x000fea13 },
1958 { 112, 0x00002c0c, 0x00000a36, 0x000b8255, 0x000fea1b },
1959 { 116, 0x00002c0c, 0x00000a3a, 0x000b8255, 0x000fea23 },
1960 { 120, 0x00002c0c, 0x00000a82, 0x000b8255, 0x000fea03 },
1961 { 124, 0x00002c0c, 0x00000a86, 0x000b8255, 0x000fea0b },
1962 { 128, 0x00002c0c, 0x00000a8a, 0x000b8255, 0x000fea13 },
1963 { 132, 0x00002c0c, 0x00000a8e, 0x000b8255, 0x000fea1b },
1964 { 136, 0x00002c0c, 0x00000a92, 0x000b8255, 0x000fea23 },
1965
1966 /* 802.11 UNII */
1967 { 140, 0x00002c0c, 0x00000a9a, 0x000b8255, 0x000fea03 },
1968 { 149, 0x00002c0c, 0x00000aa2, 0x000b8255, 0x000fea1f },
1969 { 153, 0x00002c0c, 0x00000aa6, 0x000b8255, 0x000fea27 },
1970 { 157, 0x00002c0c, 0x00000aae, 0x000b8255, 0x000fea07 },
1971 { 161, 0x00002c0c, 0x00000ab2, 0x000b8255, 0x000fea0f },
1972 { 165, 0x00002c0c, 0x00000ab6, 0x000b8255, 0x000fea17 },
1973
1974 /* MMAC(Japan)J52 ch 34,38,42,46 */
1975 { 34, 0x00002c0c, 0x0008099a, 0x000da255, 0x000d3a0b },
1976 { 38, 0x00002c0c, 0x0008099e, 0x000da255, 0x000d3a13 },
1977 { 42, 0x00002c0c, 0x000809a2, 0x000da255, 0x000d3a1b },
1978 { 46, 0x00002c0c, 0x000809a6, 0x000da255, 0x000d3a23 },
1979};
1980
1981/*
1982 * RF value list for RF5225 & RF2527
1983 * Supports: 2.4 GHz & 5.2 GHz
1984 */
1985static const struct rf_channel rf_vals_5225_2527[] = {
1986 { 1, 0x00002ccc, 0x00004786, 0x00068455, 0x000ffa0b },
1987 { 2, 0x00002ccc, 0x00004786, 0x00068455, 0x000ffa1f },
1988 { 3, 0x00002ccc, 0x0000478a, 0x00068455, 0x000ffa0b },
1989 { 4, 0x00002ccc, 0x0000478a, 0x00068455, 0x000ffa1f },
1990 { 5, 0x00002ccc, 0x0000478e, 0x00068455, 0x000ffa0b },
1991 { 6, 0x00002ccc, 0x0000478e, 0x00068455, 0x000ffa1f },
1992 { 7, 0x00002ccc, 0x00004792, 0x00068455, 0x000ffa0b },
1993 { 8, 0x00002ccc, 0x00004792, 0x00068455, 0x000ffa1f },
1994 { 9, 0x00002ccc, 0x00004796, 0x00068455, 0x000ffa0b },
1995 { 10, 0x00002ccc, 0x00004796, 0x00068455, 0x000ffa1f },
1996 { 11, 0x00002ccc, 0x0000479a, 0x00068455, 0x000ffa0b },
1997 { 12, 0x00002ccc, 0x0000479a, 0x00068455, 0x000ffa1f },
1998 { 13, 0x00002ccc, 0x0000479e, 0x00068455, 0x000ffa0b },
1999 { 14, 0x00002ccc, 0x000047a2, 0x00068455, 0x000ffa13 },
2000
2001 /* 802.11 UNI / HyperLan 2 */
2002 { 36, 0x00002ccc, 0x0000499a, 0x0009be55, 0x000ffa23 },
2003 { 40, 0x00002ccc, 0x000049a2, 0x0009be55, 0x000ffa03 },
2004 { 44, 0x00002ccc, 0x000049a6, 0x0009be55, 0x000ffa0b },
2005 { 48, 0x00002ccc, 0x000049aa, 0x0009be55, 0x000ffa13 },
2006 { 52, 0x00002ccc, 0x000049ae, 0x0009ae55, 0x000ffa1b },
2007 { 56, 0x00002ccc, 0x000049b2, 0x0009ae55, 0x000ffa23 },
2008 { 60, 0x00002ccc, 0x000049ba, 0x0009ae55, 0x000ffa03 },
2009 { 64, 0x00002ccc, 0x000049be, 0x0009ae55, 0x000ffa0b },
2010
2011 /* 802.11 HyperLan 2 */
2012 { 100, 0x00002ccc, 0x00004a2a, 0x000bae55, 0x000ffa03 },
2013 { 104, 0x00002ccc, 0x00004a2e, 0x000bae55, 0x000ffa0b },
2014 { 108, 0x00002ccc, 0x00004a32, 0x000bae55, 0x000ffa13 },
2015 { 112, 0x00002ccc, 0x00004a36, 0x000bae55, 0x000ffa1b },
2016 { 116, 0x00002ccc, 0x00004a3a, 0x000bbe55, 0x000ffa23 },
2017 { 120, 0x00002ccc, 0x00004a82, 0x000bbe55, 0x000ffa03 },
2018 { 124, 0x00002ccc, 0x00004a86, 0x000bbe55, 0x000ffa0b },
2019 { 128, 0x00002ccc, 0x00004a8a, 0x000bbe55, 0x000ffa13 },
2020 { 132, 0x00002ccc, 0x00004a8e, 0x000bbe55, 0x000ffa1b },
2021 { 136, 0x00002ccc, 0x00004a92, 0x000bbe55, 0x000ffa23 },
2022
2023 /* 802.11 UNII */
2024 { 140, 0x00002ccc, 0x00004a9a, 0x000bbe55, 0x000ffa03 },
2025 { 149, 0x00002ccc, 0x00004aa2, 0x000bbe55, 0x000ffa1f },
2026 { 153, 0x00002ccc, 0x00004aa6, 0x000bbe55, 0x000ffa27 },
2027 { 157, 0x00002ccc, 0x00004aae, 0x000bbe55, 0x000ffa07 },
2028 { 161, 0x00002ccc, 0x00004ab2, 0x000bbe55, 0x000ffa0f },
2029 { 165, 0x00002ccc, 0x00004ab6, 0x000bbe55, 0x000ffa17 },
2030
2031 /* MMAC(Japan)J52 ch 34,38,42,46 */
2032 { 34, 0x00002ccc, 0x0000499a, 0x0009be55, 0x000ffa0b },
2033 { 38, 0x00002ccc, 0x0000499e, 0x0009be55, 0x000ffa13 },
2034 { 42, 0x00002ccc, 0x000049a2, 0x0009be55, 0x000ffa1b },
2035 { 46, 0x00002ccc, 0x000049a6, 0x0009be55, 0x000ffa23 },
2036};
2037
2038
8c5e7a5f 2039static int rt73usb_probe_hw_mode(struct rt2x00_dev *rt2x00dev)
95ea3627
ID		 2040{
2041 struct hw_mode_spec *spec = &rt2x00dev->spec;
8c5e7a5f
ID		 2042 struct channel_info *info;
2043 char *tx_power;
95ea3627
ID		 2044 unsigned int i;
2045
2046 /*
2047 * Initialize all hw fields.
2048 */
2049 rt2x00dev->hw->flags =
566bfe5a 2050 IEEE80211_HW_HOST_BROADCAST_PS_BUFFERING |
4be8c387
JB		 2051 IEEE80211_HW_SIGNAL_DBM |
2052 IEEE80211_HW_SUPPORTS_PS |
2053 IEEE80211_HW_PS_NULLFUNC_STACK;
95ea3627 2054
14a3bf89 2055 SET_IEEE80211_DEV(rt2x00dev->hw, rt2x00dev->dev);
95ea3627
ID		 2056 SET_IEEE80211_PERM_ADDR(rt2x00dev->hw,
2057 rt2x00_eeprom_addr(rt2x00dev,
2058 EEPROM_MAC_ADDR_0));
2059
95ea3627
ID		 2060 /*
2061 * Initialize hw_mode information.
2062 */
31562e80
ID		 2063 spec->supported_bands = SUPPORT_BAND_2GHZ;
2064 spec->supported_rates = SUPPORT_RATE_CCK | SUPPORT_RATE_OFDM;
95ea3627 2065
5122d898 2066 if (rt2x00_rf(rt2x00dev, RF2528)) {
95ea3627
ID		 2067 spec->num_channels = ARRAY_SIZE(rf_vals_bg_2528);
2068 spec->channels = rf_vals_bg_2528;
5122d898 2069 } else if (rt2x00_rf(rt2x00dev, RF5226)) {
31562e80 2070 spec->supported_bands |= SUPPORT_BAND_5GHZ;
95ea3627
ID		 2071 spec->num_channels = ARRAY_SIZE(rf_vals_5226);
2072 spec->channels = rf_vals_5226;
5122d898 2073 } else if (rt2x00_rf(rt2x00dev, RF2527)) {
95ea3627
ID		 2074 spec->num_channels = 14;
2075 spec->channels = rf_vals_5225_2527;
5122d898 2076 } else if (rt2x00_rf(rt2x00dev, RF5225)) {
31562e80 2077 spec->supported_bands |= SUPPORT_BAND_5GHZ;
95ea3627
ID		 2078 spec->num_channels = ARRAY_SIZE(rf_vals_5225_2527);
2079 spec->channels = rf_vals_5225_2527;
2080 }
2081
8c5e7a5f
ID		 2082 /*
2083 * Create channel information array
2084 */
2085 info = kzalloc(spec->num_channels * sizeof(*info), GFP_KERNEL);
2086 if (!info)
2087 return -ENOMEM;
95ea3627 2088
8c5e7a5f
ID		 2089 spec->channels_info = info;
2090
2091 tx_power = rt2x00_eeprom_addr(rt2x00dev, EEPROM_TXPOWER_G_START);
2092 for (i = 0; i < 14; i++)
2093 info[i].tx_power1 = TXPOWER_FROM_DEV(tx_power[i]);
2094
2095 if (spec->num_channels > 14) {
2096 tx_power = rt2x00_eeprom_addr(rt2x00dev, EEPROM_TXPOWER_A_START);
2097 for (i = 14; i < spec->num_channels; i++)
2098 info[i].tx_power1 = TXPOWER_FROM_DEV(tx_power[i]);
95ea3627 2099 }
8c5e7a5f
ID		 2100
2101 return 0;
95ea3627
ID		 2102}
2103
2104static int rt73usb_probe_hw(struct rt2x00_dev *rt2x00dev)
2105{
2106 int retval;
2107
2108 /*
2109 * Allocate eeprom data.
2110 */
2111 retval = rt73usb_validate_eeprom(rt2x00dev);
2112 if (retval)
2113 return retval;
2114
2115 retval = rt73usb_init_eeprom(rt2x00dev);
2116 if (retval)
2117 return retval;
2118
2119 /*
2120 * Initialize hw specifications.
2121 */
8c5e7a5f
ID		 2122 retval = rt73usb_probe_hw_mode(rt2x00dev);
2123 if (retval)
2124 return retval;
95ea3627 2125
1afcfd54
IP		 2126 /*
2127 * This device has multiple filters for control frames,
2128 * but has no a separate filter for PS Poll frames.
2129 */
2130 __set_bit(DRIVER_SUPPORT_CONTROL_FILTERS, &rt2x00dev->flags);
2131
95ea3627 2132 /*
9404ef34 2133 * This device requires firmware.
95ea3627 2134 */
066cb637 2135 __set_bit(DRIVER_REQUIRE_FIRMWARE, &rt2x00dev->flags);
008c4482
ID		 2136 if (!modparam_nohwcrypt)
2137 __set_bit(CONFIG_SUPPORT_HW_CRYPTO, &rt2x00dev->flags);
27df2a9c 2138 __set_bit(DRIVER_SUPPORT_LINK_TUNING, &rt2x00dev->flags);
95ea3627
ID		 2139
2140 /*
2141 * Set the rssi offset.
2142 */
2143 rt2x00dev->rssi_offset = DEFAULT_RSSI_OFFSET;
2144
2145 return 0;
2146}
2147
2148/*
2149 * IEEE80211 stack callback functions.
2150 */
2af0a570
ID		 2151static int rt73usb_conf_tx(struct ieee80211_hw *hw, u16 queue_idx,
2152 const struct ieee80211_tx_queue_params *params)
2153{
2154 struct rt2x00_dev *rt2x00dev = hw->priv;
2155 struct data_queue *queue;
2156 struct rt2x00_field32 field;
2157 int retval;
2158 u32 reg;
5e790023 2159 u32 offset;
2af0a570
ID		 2160
2161 /*
2162 * First pass the configuration through rt2x00lib, that will
2163 * update the queue settings and validate the input. After that
2164 * we are free to update the registers based on the value
2165 * in the queue parameter.
2166 */
2167 retval = rt2x00mac_conf_tx(hw, queue_idx, params);
2168 if (retval)
2169 return retval;
2170
5e790023
ID		 2171 /*
2172 * We only need to perform additional register initialization
2173 * for WMM queues/
2174 */
2175 if (queue_idx >= 4)
2176 return 0;
2177
2af0a570
ID		 2178 queue = rt2x00queue_get_queue(rt2x00dev, queue_idx);
2179
2180 /* Update WMM TXOP register */
5e790023
ID		 2181 offset = AC_TXOP_CSR0 + (sizeof(u32) * (!!(queue_idx & 2)));
2182 field.bit_offset = (queue_idx & 1) * 16;
2183 field.bit_mask = 0xffff << field.bit_offset;
2184
2185 rt2x00usb_register_read(rt2x00dev, offset, &reg);
2186 rt2x00_set_field32(&reg, field, queue->txop);
2187 rt2x00usb_register_write(rt2x00dev, offset, reg);
2af0a570
ID		 2188
2189 /* Update WMM registers */
2190 field.bit_offset = queue_idx * 4;
2191 field.bit_mask = 0xf << field.bit_offset;
2192
0f829b1d 2193 rt2x00usb_register_read(rt2x00dev, AIFSN_CSR, &reg);
2af0a570 2194 rt2x00_set_field32(&reg, field, queue->aifs);
0f829b1d 2195 rt2x00usb_register_write(rt2x00dev, AIFSN_CSR, reg);
2af0a570 2196
0f829b1d 2197 rt2x00usb_register_read(rt2x00dev, CWMIN_CSR, &reg);
2af0a570 2198 rt2x00_set_field32(&reg, field, queue->cw_min);
0f829b1d 2199 rt2x00usb_register_write(rt2x00dev, CWMIN_CSR, reg);
2af0a570 2200
0f829b1d 2201 rt2x00usb_register_read(rt2x00dev, CWMAX_CSR, &reg);
2af0a570 2202 rt2x00_set_field32(&reg, field, queue->cw_max);
0f829b1d 2203 rt2x00usb_register_write(rt2x00dev, CWMAX_CSR, reg);
2af0a570
ID		 2204
2205 return 0;
2206}
2207
95ea3627
ID		 2208static u64 rt73usb_get_tsf(struct ieee80211_hw *hw)
2209{
2210 struct rt2x00_dev *rt2x00dev = hw->priv;
2211 u64 tsf;
2212 u32 reg;
2213
0f829b1d 2214 rt2x00usb_register_read(rt2x00dev, TXRX_CSR13, &reg);
95ea3627 2215 tsf = (u64) rt2x00_get_field32(reg, TXRX_CSR13_HIGH_TSFTIMER) << 32;
0f829b1d 2216 rt2x00usb_register_read(rt2x00dev, TXRX_CSR12, &reg);
95ea3627
ID		 2217 tsf |= rt2x00_get_field32(reg, TXRX_CSR12_LOW_TSFTIMER);
2218
2219 return tsf;
2220}
95ea3627 2221
95ea3627
ID		 2222static const struct ieee80211_ops rt73usb_mac80211_ops = {
2223 .tx = rt2x00mac_tx,
4150c572
JB		 2224 .start = rt2x00mac_start,
2225 .stop = rt2x00mac_stop,
95ea3627
ID		 2226 .add_interface = rt2x00mac_add_interface,
2227 .remove_interface = rt2x00mac_remove_interface,
2228 .config = rt2x00mac_config,
3a643d24 2229 .configure_filter = rt2x00mac_configure_filter,
930c06f2 2230 .set_tim = rt2x00mac_set_tim,
906c110f 2231 .set_key = rt2x00mac_set_key,
d8147f9d
ID		 2232 .sw_scan_start = rt2x00mac_sw_scan_start,
2233 .sw_scan_complete = rt2x00mac_sw_scan_complete,
95ea3627 2234 .get_stats = rt2x00mac_get_stats,
471b3efd 2235 .bss_info_changed = rt2x00mac_bss_info_changed,
2af0a570 2236 .conf_tx = rt73usb_conf_tx,
95ea3627 2237 .get_tsf = rt73usb_get_tsf,
e47a5cdd 2238 .rfkill_poll = rt2x00mac_rfkill_poll,
95ea3627
ID		 2239};
2240
2241static const struct rt2x00lib_ops rt73usb_rt2x00_ops = {
2242 .probe_hw = rt73usb_probe_hw,
2243 .get_firmware_name = rt73usb_get_firmware_name,
0cbe0064 2244 .check_firmware = rt73usb_check_firmware,
95ea3627
ID		 2245 .load_firmware = rt73usb_load_firmware,
2246 .initialize = rt2x00usb_initialize,
2247 .uninitialize = rt2x00usb_uninitialize,
798b7adb 2248 .clear_entry = rt2x00usb_clear_entry,
95ea3627 2249 .set_device_state = rt73usb_set_device_state,
7396faf4 2250 .rfkill_poll = rt73usb_rfkill_poll,
95ea3627
ID		 2251 .link_stats = rt73usb_link_stats,
2252 .reset_tuner = rt73usb_reset_tuner,
2253 .link_tuner = rt73usb_link_tuner,
2254 .write_tx_desc = rt73usb_write_tx_desc,
bd88a781 2255 .write_beacon = rt73usb_write_beacon,
dd9fa2d2 2256 .get_tx_data_len = rt73usb_get_tx_data_len,
d61cb266 2257 .kick_tx_queue = rt2x00usb_kick_tx_queue,
a2c9b652 2258 .kill_tx_queue = rt2x00usb_kill_tx_queue,
95ea3627 2259 .fill_rxdone = rt73usb_fill_rxdone,
906c110f
ID		 2260 .config_shared_key = rt73usb_config_shared_key,
2261 .config_pairwise_key = rt73usb_config_pairwise_key,
3a643d24 2262 .config_filter = rt73usb_config_filter,
6bb40dd1 2263 .config_intf = rt73usb_config_intf,
72810379 2264 .config_erp = rt73usb_config_erp,
e4ea1c40 2265 .config_ant = rt73usb_config_ant,
95ea3627
ID		 2266 .config = rt73usb_config,
2267};
2268
181d6902
ID		 2269static const struct data_queue_desc rt73usb_queue_rx = {
2270 .entry_num = RX_ENTRIES,
2271 .data_size = DATA_FRAME_SIZE,
2272 .desc_size = RXD_DESC_SIZE,
b8be63ff 2273 .priv_size = sizeof(struct queue_entry_priv_usb),
181d6902
ID		 2274};
2275
2276static const struct data_queue_desc rt73usb_queue_tx = {
2277 .entry_num = TX_ENTRIES,
2278 .data_size = DATA_FRAME_SIZE,
2279 .desc_size = TXD_DESC_SIZE,
b8be63ff 2280 .priv_size = sizeof(struct queue_entry_priv_usb),
181d6902
ID		 2281};
2282
2283static const struct data_queue_desc rt73usb_queue_bcn = {
6bb40dd1 2284 .entry_num = 4 * BEACON_ENTRIES,
181d6902
ID		 2285 .data_size = MGMT_FRAME_SIZE,
2286 .desc_size = TXINFO_SIZE,
b8be63ff 2287 .priv_size = sizeof(struct queue_entry_priv_usb),
181d6902
ID		 2288};
2289
95ea3627 2290static const struct rt2x00_ops rt73usb_ops = {
04d0362e
GW		 2291 .name = KBUILD_MODNAME,
2292 .max_sta_intf = 1,
2293 .max_ap_intf = 4,
2294 .eeprom_size = EEPROM_SIZE,
2295 .rf_size = RF_SIZE,
2296 .tx_queues = NUM_TX_QUEUES,
e6218cc4 2297 .extra_tx_headroom = TXD_DESC_SIZE,
04d0362e
GW		 2298 .rx = &rt73usb_queue_rx,
2299 .tx = &rt73usb_queue_tx,
2300 .bcn = &rt73usb_queue_bcn,
2301 .lib = &rt73usb_rt2x00_ops,
2302 .hw = &rt73usb_mac80211_ops,
95ea3627 2303#ifdef CONFIG_RT2X00_LIB_DEBUGFS
04d0362e 2304 .debugfs = &rt73usb_rt2x00debug,
95ea3627
ID		 2305#endif /* CONFIG_RT2X00_LIB_DEBUGFS */
2306};
2307
2308/*
2309 * rt73usb module information.
2310 */
2311static struct usb_device_id rt73usb_device_table[] = {
2312 /* AboCom */
ef4bb70d
XVP		 2313 { USB_DEVICE(0x07b8, 0xb21b), USB_DEVICE_DATA(&rt73usb_ops) },
2314 { USB_DEVICE(0x07b8, 0xb21c), USB_DEVICE_DATA(&rt73usb_ops) },
95ea3627 2315 { USB_DEVICE(0x07b8, 0xb21d), USB_DEVICE_DATA(&rt73usb_ops) },
ef4bb70d
XVP		 2316 { USB_DEVICE(0x07b8, 0xb21e), USB_DEVICE_DATA(&rt73usb_ops) },
2317 { USB_DEVICE(0x07b8, 0xb21f), USB_DEVICE_DATA(&rt73usb_ops) },
2318 /* AL */
2319 { USB_DEVICE(0x14b2, 0x3c10), USB_DEVICE_DATA(&rt73usb_ops) },
144d9ad9
ID		 2320 /* Amigo */
2321 { USB_DEVICE(0x148f, 0x9021), USB_DEVICE_DATA(&rt73usb_ops) },
2322 { USB_DEVICE(0x0eb0, 0x9021), USB_DEVICE_DATA(&rt73usb_ops) },
ef4bb70d
XVP		 2323 /* AMIT */
2324 { USB_DEVICE(0x18c5, 0x0002), USB_DEVICE_DATA(&rt73usb_ops) },
95ea3627
ID		 2325 /* Askey */
2326 { USB_DEVICE(0x1690, 0x0722), USB_DEVICE_DATA(&rt73usb_ops) },
2327 /* ASUS */
2328 { USB_DEVICE(0x0b05, 0x1723), USB_DEVICE_DATA(&rt73usb_ops) },
2329 { USB_DEVICE(0x0b05, 0x1724), USB_DEVICE_DATA(&rt73usb_ops) },
2330 /* Belkin */
2331 { USB_DEVICE(0x050d, 0x7050), USB_DEVICE_DATA(&rt73usb_ops) },
2332 { USB_DEVICE(0x050d, 0x705a), USB_DEVICE_DATA(&rt73usb_ops) },
2333 { USB_DEVICE(0x050d, 0x905b), USB_DEVICE_DATA(&rt73usb_ops) },
1f06862e 2334 { USB_DEVICE(0x050d, 0x905c), USB_DEVICE_DATA(&rt73usb_ops) },
95ea3627
ID		 2335 /* Billionton */
2336 { USB_DEVICE(0x1631, 0xc019), USB_DEVICE_DATA(&rt73usb_ops) },
ef4bb70d 2337 { USB_DEVICE(0x08dd, 0x0120), USB_DEVICE_DATA(&rt73usb_ops) },
95ea3627 2338 /* Buffalo */
964d6ad9 2339 { USB_DEVICE(0x0411, 0x00d8), USB_DEVICE_DATA(&rt73usb_ops) },
050e8a47 2340 { USB_DEVICE(0x0411, 0x00d9), USB_DEVICE_DATA(&rt73usb_ops) },
95ea3627 2341 { USB_DEVICE(0x0411, 0x00f4), USB_DEVICE_DATA(&rt73usb_ops) },
6aabd4c4
ID		 2342 { USB_DEVICE(0x0411, 0x0116), USB_DEVICE_DATA(&rt73usb_ops) },
2343 { USB_DEVICE(0x0411, 0x0119), USB_DEVICE_DATA(&rt73usb_ops) },
51b2853f
BP		 2344 /* CEIVA */
2345 { USB_DEVICE(0x178d, 0x02be), USB_DEVICE_DATA(&rt73usb_ops) },
95ea3627
ID		 2346 /* CNet */
2347 { USB_DEVICE(0x1371, 0x9022), USB_DEVICE_DATA(&rt73usb_ops) },
2348 { USB_DEVICE(0x1371, 0x9032), USB_DEVICE_DATA(&rt73usb_ops) },
2349 /* Conceptronic */
2350 { USB_DEVICE(0x14b2, 0x3c22), USB_DEVICE_DATA(&rt73usb_ops) },
0a74892b
MM		 2351 /* Corega */
2352 { USB_DEVICE(0x07aa, 0x002e), USB_DEVICE_DATA(&rt73usb_ops) },
95ea3627
ID		 2353 /* D-Link */
2354 { USB_DEVICE(0x07d1, 0x3c03), USB_DEVICE_DATA(&rt73usb_ops) },
2355 { USB_DEVICE(0x07d1, 0x3c04), USB_DEVICE_DATA(&rt73usb_ops) },
cb62eccd 2356 { USB_DEVICE(0x07d1, 0x3c06), USB_DEVICE_DATA(&rt73usb_ops) },
445815d7 2357 { USB_DEVICE(0x07d1, 0x3c07), USB_DEVICE_DATA(&rt73usb_ops) },
ef4bb70d
XVP		 2358 /* Edimax */
2359 { USB_DEVICE(0x7392, 0x7318), USB_DEVICE_DATA(&rt73usb_ops) },
2360 { USB_DEVICE(0x7392, 0x7618), USB_DEVICE_DATA(&rt73usb_ops) },
2361 /* EnGenius */
2362 { USB_DEVICE(0x1740, 0x3701), USB_DEVICE_DATA(&rt73usb_ops) },
95ea3627
ID		 2363 /* Gemtek */
2364 { USB_DEVICE(0x15a9, 0x0004), USB_DEVICE_DATA(&rt73usb_ops) },
2365 /* Gigabyte */
2366 { USB_DEVICE(0x1044, 0x8008), USB_DEVICE_DATA(&rt73usb_ops) },
2367 { USB_DEVICE(0x1044, 0x800a), USB_DEVICE_DATA(&rt73usb_ops) },
2368 /* Huawei-3Com */
2369 { USB_DEVICE(0x1472, 0x0009), USB_DEVICE_DATA(&rt73usb_ops) },
2370 /* Hercules */
78bd6bbf 2371 { USB_DEVICE(0x06f8, 0xe002), USB_DEVICE_DATA(&rt73usb_ops) },
95ea3627
ID		 2372 { USB_DEVICE(0x06f8, 0xe010), USB_DEVICE_DATA(&rt73usb_ops) },
2373 { USB_DEVICE(0x06f8, 0xe020), USB_DEVICE_DATA(&rt73usb_ops) },
2374 /* Linksys */
2375 { USB_DEVICE(0x13b1, 0x0020), USB_DEVICE_DATA(&rt73usb_ops) },
2376 { USB_DEVICE(0x13b1, 0x0023), USB_DEVICE_DATA(&rt73usb_ops) },
3be36ae2 2377 { USB_DEVICE(0x13b1, 0x0028), USB_DEVICE_DATA(&rt73usb_ops) },
95ea3627 2378 /* MSI */
22720645 2379 { USB_DEVICE(0x0db0, 0x4600), USB_DEVICE_DATA(&rt73usb_ops) },
95ea3627
ID		 2380 { USB_DEVICE(0x0db0, 0x6877), USB_DEVICE_DATA(&rt73usb_ops) },
2381 { USB_DEVICE(0x0db0, 0x6874), USB_DEVICE_DATA(&rt73usb_ops) },
2382 { USB_DEVICE(0x0db0, 0xa861), USB_DEVICE_DATA(&rt73usb_ops) },
2383 { USB_DEVICE(0x0db0, 0xa874), USB_DEVICE_DATA(&rt73usb_ops) },
22720645
XVP		 2384 /* Ovislink */
2385 { USB_DEVICE(0x1b75, 0x7318), USB_DEVICE_DATA(&rt73usb_ops) },
95ea3627 2386 /* Ralink */
144d9ad9 2387 { USB_DEVICE(0x04bb, 0x093d), USB_DEVICE_DATA(&rt73usb_ops) },
95ea3627
ID		 2388 { USB_DEVICE(0x148f, 0x2573), USB_DEVICE_DATA(&rt73usb_ops) },
2389 { USB_DEVICE(0x148f, 0x2671), USB_DEVICE_DATA(&rt73usb_ops) },
2390 /* Qcom */
2391 { USB_DEVICE(0x18e8, 0x6196), USB_DEVICE_DATA(&rt73usb_ops) },
2392 { USB_DEVICE(0x18e8, 0x6229), USB_DEVICE_DATA(&rt73usb_ops) },
2393 { USB_DEVICE(0x18e8, 0x6238), USB_DEVICE_DATA(&rt73usb_ops) },
ef4bb70d
XVP		 2394 /* Samsung */
2395 { USB_DEVICE(0x04e8, 0x4471), USB_DEVICE_DATA(&rt73usb_ops) },
95ea3627
ID		 2396 /* Senao */
2397 { USB_DEVICE(0x1740, 0x7100), USB_DEVICE_DATA(&rt73usb_ops) },
2398 /* Sitecom */
ef4bb70d
XVP		 2399 { USB_DEVICE(0x0df6, 0x0024), USB_DEVICE_DATA(&rt73usb_ops) },
2400 { USB_DEVICE(0x0df6, 0x0027), USB_DEVICE_DATA(&rt73usb_ops) },
2401 { USB_DEVICE(0x0df6, 0x002f), USB_DEVICE_DATA(&rt73usb_ops) },
95ea3627 2402 { USB_DEVICE(0x0df6, 0x90ac), USB_DEVICE_DATA(&rt73usb_ops) },
ef4bb70d 2403 { USB_DEVICE(0x0df6, 0x9712), USB_DEVICE_DATA(&rt73usb_ops) },
95ea3627
ID		 2404 /* Surecom */
2405 { USB_DEVICE(0x0769, 0x31f3), USB_DEVICE_DATA(&rt73usb_ops) },
14344b81
ID		 2406 /* Tilgin */
2407 { USB_DEVICE(0x6933, 0x5001), USB_DEVICE_DATA(&rt73usb_ops) },
ef4bb70d
XVP		 2408 /* Philips */
2409 { USB_DEVICE(0x0471, 0x200a), USB_DEVICE_DATA(&rt73usb_ops) },
95ea3627
ID		 2410 /* Planex */
2411 { USB_DEVICE(0x2019, 0xab01), USB_DEVICE_DATA(&rt73usb_ops) },
2412 { USB_DEVICE(0x2019, 0xab50), USB_DEVICE_DATA(&rt73usb_ops) },
22720645
XVP		 2413 /* WideTell */
2414 { USB_DEVICE(0x7167, 0x3840), USB_DEVICE_DATA(&rt73usb_ops) },
ef4bb70d
XVP		 2415 /* Zcom */
2416 { USB_DEVICE(0x0cde, 0x001c), USB_DEVICE_DATA(&rt73usb_ops) },
144d9ad9
ID		 2417 /* ZyXEL */
2418 { USB_DEVICE(0x0586, 0x3415), USB_DEVICE_DATA(&rt73usb_ops) },
95ea3627
ID		 2419 { 0, }
2420};
2421
2422MODULE_AUTHOR(DRV_PROJECT);
2423MODULE_VERSION(DRV_VERSION);
2424MODULE_DESCRIPTION("Ralink RT73 USB Wireless LAN driver.");
2425MODULE_SUPPORTED_DEVICE("Ralink RT2571W & RT2671 USB chipset based cards");
2426MODULE_DEVICE_TABLE(usb, rt73usb_device_table);
2427MODULE_FIRMWARE(FIRMWARE_RT2571);
2428MODULE_LICENSE("GPL");
2429
2430static struct usb_driver rt73usb_driver = {
2360157c 2431 .name = KBUILD_MODNAME,
95ea3627
ID		 2432 .id_table = rt73usb_device_table,
2433 .probe = rt2x00usb_probe,
2434 .disconnect = rt2x00usb_disconnect,
2435 .suspend = rt2x00usb_suspend,
2436 .resume = rt2x00usb_resume,
2437};
2438
2439static int __init rt73usb_init(void)
2440{
2441 return usb_register(&rt73usb_driver);
2442}
2443
2444static void __exit rt73usb_exit(void)
2445{
2446 usb_deregister(&rt73usb_driver);
2447}
2448
2449module_init(rt73usb_init);
2450module_exit(rt73usb_exit);
Linux kernel - Deliverables
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