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95ea3627 | 1 | /* |
9c9a0d14 | 2 | Copyright (C) 2004 - 2009 Ivo van Doorn <IvDoorn@gmail.com> |
95ea3627 ID |
3 | <http://rt2x00.serialmonkey.com> |
4 | ||
5 | This program is free software; you can redistribute it and/or modify | |
6 | it under the terms of the GNU General Public License as published by | |
7 | the Free Software Foundation; either version 2 of the License, or | |
8 | (at your option) any later version. | |
9 | ||
10 | This program is distributed in the hope that it will be useful, | |
11 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
12 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
13 | GNU General Public License for more details. | |
14 | ||
15 | You should have received a copy of the GNU General Public License | |
16 | along with this program; if not, write to the | |
17 | Free Software Foundation, Inc., | |
18 | 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. | |
19 | */ | |
20 | ||
21 | /* | |
22 | Module: rt73usb | |
23 | Abstract: rt73usb device specific routines. | |
24 | Supported chipsets: rt2571W & rt2671. | |
25 | */ | |
26 | ||
a7f3a06c | 27 | #include <linux/crc-itu-t.h> |
95ea3627 ID |
28 | #include <linux/delay.h> |
29 | #include <linux/etherdevice.h> | |
30 | #include <linux/init.h> | |
31 | #include <linux/kernel.h> | |
32 | #include <linux/module.h> | |
5a0e3ad6 | 33 | #include <linux/slab.h> |
95ea3627 ID |
34 | #include <linux/usb.h> |
35 | ||
36 | #include "rt2x00.h" | |
37 | #include "rt2x00usb.h" | |
38 | #include "rt73usb.h" | |
39 | ||
008c4482 ID |
40 | /* |
41 | * Allow hardware encryption to be disabled. | |
42 | */ | |
821cde63 | 43 | static int modparam_nohwcrypt; |
008c4482 ID |
44 | module_param_named(nohwcrypt, modparam_nohwcrypt, bool, S_IRUGO); |
45 | MODULE_PARM_DESC(nohwcrypt, "Disable hardware encryption."); | |
46 | ||
95ea3627 ID |
47 | /* |
48 | * Register access. | |
49 | * All access to the CSR registers will go through the methods | |
0f829b1d | 50 | * rt2x00usb_register_read and rt2x00usb_register_write. |
95ea3627 ID |
51 | * BBP and RF register require indirect register access, |
52 | * and use the CSR registers BBPCSR and RFCSR to achieve this. | |
53 | * These indirect registers work with busy bits, | |
54 | * and we will try maximal REGISTER_BUSY_COUNT times to access | |
55 | * the register while taking a REGISTER_BUSY_DELAY us delay | |
56 | * between each attampt. When the busy bit is still set at that time, | |
57 | * the access attempt is considered to have failed, | |
58 | * and we will print an error. | |
8ff48a8b | 59 | * The _lock versions must be used if you already hold the csr_mutex |
95ea3627 | 60 | */ |
c9c3b1a5 | 61 | #define WAIT_FOR_BBP(__dev, __reg) \ |
0f829b1d | 62 | rt2x00usb_regbusy_read((__dev), PHY_CSR3, PHY_CSR3_BUSY, (__reg)) |
c9c3b1a5 | 63 | #define WAIT_FOR_RF(__dev, __reg) \ |
0f829b1d | 64 | rt2x00usb_regbusy_read((__dev), PHY_CSR4, PHY_CSR4_BUSY, (__reg)) |
c9c3b1a5 | 65 | |
0e14f6d3 | 66 | static void rt73usb_bbp_write(struct rt2x00_dev *rt2x00dev, |
95ea3627 ID |
67 | const unsigned int word, const u8 value) |
68 | { | |
69 | u32 reg; | |
70 | ||
8ff48a8b | 71 | mutex_lock(&rt2x00dev->csr_mutex); |
3d82346c | 72 | |
95ea3627 | 73 | /* |
c9c3b1a5 ID |
74 | * Wait until the BBP becomes available, afterwards we |
75 | * can safely write the new data into the register. | |
95ea3627 | 76 | */ |
c9c3b1a5 ID |
77 | if (WAIT_FOR_BBP(rt2x00dev, ®)) { |
78 | reg = 0; | |
79 | rt2x00_set_field32(®, PHY_CSR3_VALUE, value); | |
80 | rt2x00_set_field32(®, PHY_CSR3_REGNUM, word); | |
81 | rt2x00_set_field32(®, PHY_CSR3_BUSY, 1); | |
82 | rt2x00_set_field32(®, PHY_CSR3_READ_CONTROL, 0); | |
83 | ||
0f829b1d | 84 | rt2x00usb_register_write_lock(rt2x00dev, PHY_CSR3, reg); |
c9c3b1a5 | 85 | } |
99ade259 | 86 | |
8ff48a8b | 87 | mutex_unlock(&rt2x00dev->csr_mutex); |
95ea3627 ID |
88 | } |
89 | ||
0e14f6d3 | 90 | static void rt73usb_bbp_read(struct rt2x00_dev *rt2x00dev, |
95ea3627 ID |
91 | const unsigned int word, u8 *value) |
92 | { | |
93 | u32 reg; | |
94 | ||
8ff48a8b | 95 | mutex_lock(&rt2x00dev->csr_mutex); |
3d82346c | 96 | |
95ea3627 | 97 | /* |
c9c3b1a5 ID |
98 | * Wait until the BBP becomes available, afterwards we |
99 | * can safely write the read request into the register. | |
100 | * After the data has been written, we wait until hardware | |
101 | * returns the correct value, if at any time the register | |
102 | * doesn't become available in time, reg will be 0xffffffff | |
103 | * which means we return 0xff to the caller. | |
95ea3627 | 104 | */ |
c9c3b1a5 ID |
105 | if (WAIT_FOR_BBP(rt2x00dev, ®)) { |
106 | reg = 0; | |
107 | rt2x00_set_field32(®, PHY_CSR3_REGNUM, word); | |
108 | rt2x00_set_field32(®, PHY_CSR3_BUSY, 1); | |
109 | rt2x00_set_field32(®, PHY_CSR3_READ_CONTROL, 1); | |
95ea3627 | 110 | |
0f829b1d | 111 | rt2x00usb_register_write_lock(rt2x00dev, PHY_CSR3, reg); |
95ea3627 | 112 | |
c9c3b1a5 ID |
113 | WAIT_FOR_BBP(rt2x00dev, ®); |
114 | } | |
95ea3627 ID |
115 | |
116 | *value = rt2x00_get_field32(reg, PHY_CSR3_VALUE); | |
99ade259 | 117 | |
8ff48a8b | 118 | mutex_unlock(&rt2x00dev->csr_mutex); |
95ea3627 ID |
119 | } |
120 | ||
0e14f6d3 | 121 | static void rt73usb_rf_write(struct rt2x00_dev *rt2x00dev, |
95ea3627 ID |
122 | const unsigned int word, const u32 value) |
123 | { | |
124 | u32 reg; | |
95ea3627 | 125 | |
8ff48a8b | 126 | mutex_lock(&rt2x00dev->csr_mutex); |
3d82346c | 127 | |
4f5af6eb | 128 | /* |
c9c3b1a5 ID |
129 | * Wait until the RF becomes available, afterwards we |
130 | * can safely write the new data into the register. | |
4f5af6eb | 131 | */ |
c9c3b1a5 ID |
132 | if (WAIT_FOR_RF(rt2x00dev, ®)) { |
133 | reg = 0; | |
134 | rt2x00_set_field32(®, PHY_CSR4_VALUE, value); | |
135 | /* | |
136 | * RF5225 and RF2527 contain 21 bits per RF register value, | |
137 | * all others contain 20 bits. | |
138 | */ | |
139 | rt2x00_set_field32(®, PHY_CSR4_NUMBER_OF_BITS, | |
5122d898 GW |
140 | 20 + (rt2x00_rf(rt2x00dev, RF5225) || |
141 | rt2x00_rf(rt2x00dev, RF2527))); | |
c9c3b1a5 ID |
142 | rt2x00_set_field32(®, PHY_CSR4_IF_SELECT, 0); |
143 | rt2x00_set_field32(®, PHY_CSR4_BUSY, 1); | |
144 | ||
0f829b1d | 145 | rt2x00usb_register_write_lock(rt2x00dev, PHY_CSR4, reg); |
c9c3b1a5 ID |
146 | rt2x00_rf_write(rt2x00dev, word, value); |
147 | } | |
8ff48a8b ID |
148 | |
149 | mutex_unlock(&rt2x00dev->csr_mutex); | |
95ea3627 ID |
150 | } |
151 | ||
152 | #ifdef CONFIG_RT2X00_LIB_DEBUGFS | |
95ea3627 ID |
153 | static const struct rt2x00debug rt73usb_rt2x00debug = { |
154 | .owner = THIS_MODULE, | |
155 | .csr = { | |
0f829b1d ID |
156 | .read = rt2x00usb_register_read, |
157 | .write = rt2x00usb_register_write, | |
743b97ca ID |
158 | .flags = RT2X00DEBUGFS_OFFSET, |
159 | .word_base = CSR_REG_BASE, | |
95ea3627 ID |
160 | .word_size = sizeof(u32), |
161 | .word_count = CSR_REG_SIZE / sizeof(u32), | |
162 | }, | |
163 | .eeprom = { | |
164 | .read = rt2x00_eeprom_read, | |
165 | .write = rt2x00_eeprom_write, | |
743b97ca | 166 | .word_base = EEPROM_BASE, |
95ea3627 ID |
167 | .word_size = sizeof(u16), |
168 | .word_count = EEPROM_SIZE / sizeof(u16), | |
169 | }, | |
170 | .bbp = { | |
171 | .read = rt73usb_bbp_read, | |
172 | .write = rt73usb_bbp_write, | |
743b97ca | 173 | .word_base = BBP_BASE, |
95ea3627 ID |
174 | .word_size = sizeof(u8), |
175 | .word_count = BBP_SIZE / sizeof(u8), | |
176 | }, | |
177 | .rf = { | |
178 | .read = rt2x00_rf_read, | |
179 | .write = rt73usb_rf_write, | |
743b97ca | 180 | .word_base = RF_BASE, |
95ea3627 ID |
181 | .word_size = sizeof(u32), |
182 | .word_count = RF_SIZE / sizeof(u32), | |
183 | }, | |
184 | }; | |
185 | #endif /* CONFIG_RT2X00_LIB_DEBUGFS */ | |
186 | ||
7396faf4 ID |
187 | static int rt73usb_rfkill_poll(struct rt2x00_dev *rt2x00dev) |
188 | { | |
189 | u32 reg; | |
190 | ||
191 | rt2x00usb_register_read(rt2x00dev, MAC_CSR13, ®); | |
192 | return rt2x00_get_field32(reg, MAC_CSR13_BIT7); | |
193 | } | |
7396faf4 | 194 | |
771fd565 | 195 | #ifdef CONFIG_RT2X00_LIB_LEDS |
a2e1d52a | 196 | static void rt73usb_brightness_set(struct led_classdev *led_cdev, |
a9450b70 ID |
197 | enum led_brightness brightness) |
198 | { | |
199 | struct rt2x00_led *led = | |
200 | container_of(led_cdev, struct rt2x00_led, led_dev); | |
201 | unsigned int enabled = brightness != LED_OFF; | |
202 | unsigned int a_mode = | |
203 | (enabled && led->rt2x00dev->curr_band == IEEE80211_BAND_5GHZ); | |
204 | unsigned int bg_mode = | |
205 | (enabled && led->rt2x00dev->curr_band == IEEE80211_BAND_2GHZ); | |
206 | ||
207 | if (led->type == LED_TYPE_RADIO) { | |
208 | rt2x00_set_field16(&led->rt2x00dev->led_mcu_reg, | |
209 | MCU_LEDCS_RADIO_STATUS, enabled); | |
210 | ||
47b10cd1 ID |
211 | rt2x00usb_vendor_request_sw(led->rt2x00dev, USB_LED_CONTROL, |
212 | 0, led->rt2x00dev->led_mcu_reg, | |
213 | REGISTER_TIMEOUT); | |
a9450b70 ID |
214 | } else if (led->type == LED_TYPE_ASSOC) { |
215 | rt2x00_set_field16(&led->rt2x00dev->led_mcu_reg, | |
216 | MCU_LEDCS_LINK_BG_STATUS, bg_mode); | |
217 | rt2x00_set_field16(&led->rt2x00dev->led_mcu_reg, | |
218 | MCU_LEDCS_LINK_A_STATUS, a_mode); | |
219 | ||
47b10cd1 ID |
220 | rt2x00usb_vendor_request_sw(led->rt2x00dev, USB_LED_CONTROL, |
221 | 0, led->rt2x00dev->led_mcu_reg, | |
222 | REGISTER_TIMEOUT); | |
a9450b70 ID |
223 | } else if (led->type == LED_TYPE_QUALITY) { |
224 | /* | |
225 | * The brightness is divided into 6 levels (0 - 5), | |
226 | * this means we need to convert the brightness | |
227 | * argument into the matching level within that range. | |
228 | */ | |
47b10cd1 ID |
229 | rt2x00usb_vendor_request_sw(led->rt2x00dev, USB_LED_CONTROL, |
230 | brightness / (LED_FULL / 6), | |
231 | led->rt2x00dev->led_mcu_reg, | |
232 | REGISTER_TIMEOUT); | |
a9450b70 ID |
233 | } |
234 | } | |
a2e1d52a ID |
235 | |
236 | static int rt73usb_blink_set(struct led_classdev *led_cdev, | |
237 | unsigned long *delay_on, | |
238 | unsigned long *delay_off) | |
239 | { | |
240 | struct rt2x00_led *led = | |
241 | container_of(led_cdev, struct rt2x00_led, led_dev); | |
242 | u32 reg; | |
243 | ||
0f829b1d | 244 | rt2x00usb_register_read(led->rt2x00dev, MAC_CSR14, ®); |
a2e1d52a ID |
245 | rt2x00_set_field32(®, MAC_CSR14_ON_PERIOD, *delay_on); |
246 | rt2x00_set_field32(®, MAC_CSR14_OFF_PERIOD, *delay_off); | |
0f829b1d | 247 | rt2x00usb_register_write(led->rt2x00dev, MAC_CSR14, reg); |
a2e1d52a ID |
248 | |
249 | return 0; | |
250 | } | |
475433be ID |
251 | |
252 | static void rt73usb_init_led(struct rt2x00_dev *rt2x00dev, | |
253 | struct rt2x00_led *led, | |
254 | enum led_type type) | |
255 | { | |
256 | led->rt2x00dev = rt2x00dev; | |
257 | led->type = type; | |
258 | led->led_dev.brightness_set = rt73usb_brightness_set; | |
259 | led->led_dev.blink_set = rt73usb_blink_set; | |
260 | led->flags = LED_INITIALIZED; | |
261 | } | |
771fd565 | 262 | #endif /* CONFIG_RT2X00_LIB_LEDS */ |
a9450b70 | 263 | |
95ea3627 ID |
264 | /* |
265 | * Configuration handlers. | |
266 | */ | |
906c110f ID |
267 | static int rt73usb_config_shared_key(struct rt2x00_dev *rt2x00dev, |
268 | struct rt2x00lib_crypto *crypto, | |
269 | struct ieee80211_key_conf *key) | |
270 | { | |
271 | struct hw_key_entry key_entry; | |
272 | struct rt2x00_field32 field; | |
906c110f ID |
273 | u32 mask; |
274 | u32 reg; | |
275 | ||
276 | if (crypto->cmd == SET_KEY) { | |
277 | /* | |
278 | * rt2x00lib can't determine the correct free | |
279 | * key_idx for shared keys. We have 1 register | |
280 | * with key valid bits. The goal is simple, read | |
281 | * the register, if that is full we have no slots | |
282 | * left. | |
283 | * Note that each BSS is allowed to have up to 4 | |
284 | * shared keys, so put a mask over the allowed | |
285 | * entries. | |
286 | */ | |
287 | mask = (0xf << crypto->bssidx); | |
288 | ||
0f829b1d | 289 | rt2x00usb_register_read(rt2x00dev, SEC_CSR0, ®); |
906c110f ID |
290 | reg &= mask; |
291 | ||
292 | if (reg && reg == mask) | |
293 | return -ENOSPC; | |
294 | ||
acaf908d | 295 | key->hw_key_idx += reg ? ffz(reg) : 0; |
906c110f ID |
296 | |
297 | /* | |
298 | * Upload key to hardware | |
299 | */ | |
300 | memcpy(key_entry.key, crypto->key, | |
301 | sizeof(key_entry.key)); | |
302 | memcpy(key_entry.tx_mic, crypto->tx_mic, | |
303 | sizeof(key_entry.tx_mic)); | |
304 | memcpy(key_entry.rx_mic, crypto->rx_mic, | |
305 | sizeof(key_entry.rx_mic)); | |
306 | ||
307 | reg = SHARED_KEY_ENTRY(key->hw_key_idx); | |
96b61baf GW |
308 | rt2x00usb_register_multiwrite(rt2x00dev, reg, |
309 | &key_entry, sizeof(key_entry)); | |
906c110f ID |
310 | |
311 | /* | |
312 | * The cipher types are stored over 2 registers. | |
313 | * bssidx 0 and 1 keys are stored in SEC_CSR1 and | |
314 | * bssidx 1 and 2 keys are stored in SEC_CSR5. | |
315 | * Using the correct defines correctly will cause overhead, | |
316 | * so just calculate the correct offset. | |
317 | */ | |
318 | if (key->hw_key_idx < 8) { | |
319 | field.bit_offset = (3 * key->hw_key_idx); | |
320 | field.bit_mask = 0x7 << field.bit_offset; | |
321 | ||
0f829b1d | 322 | rt2x00usb_register_read(rt2x00dev, SEC_CSR1, ®); |
906c110f | 323 | rt2x00_set_field32(®, field, crypto->cipher); |
0f829b1d | 324 | rt2x00usb_register_write(rt2x00dev, SEC_CSR1, reg); |
906c110f ID |
325 | } else { |
326 | field.bit_offset = (3 * (key->hw_key_idx - 8)); | |
327 | field.bit_mask = 0x7 << field.bit_offset; | |
328 | ||
0f829b1d | 329 | rt2x00usb_register_read(rt2x00dev, SEC_CSR5, ®); |
906c110f | 330 | rt2x00_set_field32(®, field, crypto->cipher); |
0f829b1d | 331 | rt2x00usb_register_write(rt2x00dev, SEC_CSR5, reg); |
906c110f ID |
332 | } |
333 | ||
334 | /* | |
335 | * The driver does not support the IV/EIV generation | |
336 | * in hardware. However it doesn't support the IV/EIV | |
337 | * inside the ieee80211 frame either, but requires it | |
3ad2f3fb | 338 | * to be provided separately for the descriptor. |
906c110f ID |
339 | * rt2x00lib will cut the IV/EIV data out of all frames |
340 | * given to us by mac80211, but we must tell mac80211 | |
341 | * to generate the IV/EIV data. | |
342 | */ | |
343 | key->flags |= IEEE80211_KEY_FLAG_GENERATE_IV; | |
344 | } | |
345 | ||
346 | /* | |
347 | * SEC_CSR0 contains only single-bit fields to indicate | |
348 | * a particular key is valid. Because using the FIELD32() | |
349 | * defines directly will cause a lot of overhead we use | |
350 | * a calculation to determine the correct bit directly. | |
351 | */ | |
352 | mask = 1 << key->hw_key_idx; | |
353 | ||
0f829b1d | 354 | rt2x00usb_register_read(rt2x00dev, SEC_CSR0, ®); |
906c110f ID |
355 | if (crypto->cmd == SET_KEY) |
356 | reg |= mask; | |
357 | else if (crypto->cmd == DISABLE_KEY) | |
358 | reg &= ~mask; | |
0f829b1d | 359 | rt2x00usb_register_write(rt2x00dev, SEC_CSR0, reg); |
906c110f ID |
360 | |
361 | return 0; | |
362 | } | |
363 | ||
364 | static int rt73usb_config_pairwise_key(struct rt2x00_dev *rt2x00dev, | |
365 | struct rt2x00lib_crypto *crypto, | |
366 | struct ieee80211_key_conf *key) | |
367 | { | |
368 | struct hw_pairwise_ta_entry addr_entry; | |
369 | struct hw_key_entry key_entry; | |
906c110f ID |
370 | u32 mask; |
371 | u32 reg; | |
372 | ||
373 | if (crypto->cmd == SET_KEY) { | |
374 | /* | |
375 | * rt2x00lib can't determine the correct free | |
376 | * key_idx for pairwise keys. We have 2 registers | |
377 | * with key valid bits. The goal is simple, read | |
378 | * the first register, if that is full move to | |
379 | * the next register. | |
380 | * When both registers are full, we drop the key, | |
381 | * otherwise we use the first invalid entry. | |
382 | */ | |
0f829b1d | 383 | rt2x00usb_register_read(rt2x00dev, SEC_CSR2, ®); |
906c110f ID |
384 | if (reg && reg == ~0) { |
385 | key->hw_key_idx = 32; | |
0f829b1d | 386 | rt2x00usb_register_read(rt2x00dev, SEC_CSR3, ®); |
906c110f ID |
387 | if (reg && reg == ~0) |
388 | return -ENOSPC; | |
389 | } | |
390 | ||
acaf908d | 391 | key->hw_key_idx += reg ? ffz(reg) : 0; |
906c110f ID |
392 | |
393 | /* | |
394 | * Upload key to hardware | |
395 | */ | |
396 | memcpy(key_entry.key, crypto->key, | |
397 | sizeof(key_entry.key)); | |
398 | memcpy(key_entry.tx_mic, crypto->tx_mic, | |
399 | sizeof(key_entry.tx_mic)); | |
400 | memcpy(key_entry.rx_mic, crypto->rx_mic, | |
401 | sizeof(key_entry.rx_mic)); | |
402 | ||
403 | reg = PAIRWISE_KEY_ENTRY(key->hw_key_idx); | |
96b61baf GW |
404 | rt2x00usb_register_multiwrite(rt2x00dev, reg, |
405 | &key_entry, sizeof(key_entry)); | |
906c110f ID |
406 | |
407 | /* | |
408 | * Send the address and cipher type to the hardware register. | |
906c110f ID |
409 | */ |
410 | memset(&addr_entry, 0, sizeof(addr_entry)); | |
411 | memcpy(&addr_entry, crypto->address, ETH_ALEN); | |
412 | addr_entry.cipher = crypto->cipher; | |
413 | ||
414 | reg = PAIRWISE_TA_ENTRY(key->hw_key_idx); | |
0f829b1d | 415 | rt2x00usb_register_multiwrite(rt2x00dev, reg, |
906c110f ID |
416 | &addr_entry, sizeof(addr_entry)); |
417 | ||
418 | /* | |
419 | * Enable pairwise lookup table for given BSS idx, | |
420 | * without this received frames will not be decrypted | |
421 | * by the hardware. | |
422 | */ | |
0f829b1d | 423 | rt2x00usb_register_read(rt2x00dev, SEC_CSR4, ®); |
906c110f | 424 | reg |= (1 << crypto->bssidx); |
0f829b1d | 425 | rt2x00usb_register_write(rt2x00dev, SEC_CSR4, reg); |
906c110f ID |
426 | |
427 | /* | |
428 | * The driver does not support the IV/EIV generation | |
429 | * in hardware. However it doesn't support the IV/EIV | |
430 | * inside the ieee80211 frame either, but requires it | |
3ad2f3fb | 431 | * to be provided separately for the descriptor. |
906c110f ID |
432 | * rt2x00lib will cut the IV/EIV data out of all frames |
433 | * given to us by mac80211, but we must tell mac80211 | |
434 | * to generate the IV/EIV data. | |
435 | */ | |
436 | key->flags |= IEEE80211_KEY_FLAG_GENERATE_IV; | |
437 | } | |
438 | ||
439 | /* | |
440 | * SEC_CSR2 and SEC_CSR3 contain only single-bit fields to indicate | |
441 | * a particular key is valid. Because using the FIELD32() | |
442 | * defines directly will cause a lot of overhead we use | |
443 | * a calculation to determine the correct bit directly. | |
444 | */ | |
445 | if (key->hw_key_idx < 32) { | |
446 | mask = 1 << key->hw_key_idx; | |
447 | ||
0f829b1d | 448 | rt2x00usb_register_read(rt2x00dev, SEC_CSR2, ®); |
906c110f ID |
449 | if (crypto->cmd == SET_KEY) |
450 | reg |= mask; | |
451 | else if (crypto->cmd == DISABLE_KEY) | |
452 | reg &= ~mask; | |
0f829b1d | 453 | rt2x00usb_register_write(rt2x00dev, SEC_CSR2, reg); |
906c110f ID |
454 | } else { |
455 | mask = 1 << (key->hw_key_idx - 32); | |
456 | ||
0f829b1d | 457 | rt2x00usb_register_read(rt2x00dev, SEC_CSR3, ®); |
906c110f ID |
458 | if (crypto->cmd == SET_KEY) |
459 | reg |= mask; | |
460 | else if (crypto->cmd == DISABLE_KEY) | |
461 | reg &= ~mask; | |
0f829b1d | 462 | rt2x00usb_register_write(rt2x00dev, SEC_CSR3, reg); |
906c110f ID |
463 | } |
464 | ||
465 | return 0; | |
466 | } | |
467 | ||
3a643d24 ID |
468 | static void rt73usb_config_filter(struct rt2x00_dev *rt2x00dev, |
469 | const unsigned int filter_flags) | |
470 | { | |
471 | u32 reg; | |
472 | ||
473 | /* | |
474 | * Start configuration steps. | |
475 | * Note that the version error will always be dropped | |
476 | * and broadcast frames will always be accepted since | |
477 | * there is no filter for it at this time. | |
478 | */ | |
0f829b1d | 479 | rt2x00usb_register_read(rt2x00dev, TXRX_CSR0, ®); |
3a643d24 ID |
480 | rt2x00_set_field32(®, TXRX_CSR0_DROP_CRC, |
481 | !(filter_flags & FIF_FCSFAIL)); | |
482 | rt2x00_set_field32(®, TXRX_CSR0_DROP_PHYSICAL, | |
483 | !(filter_flags & FIF_PLCPFAIL)); | |
484 | rt2x00_set_field32(®, TXRX_CSR0_DROP_CONTROL, | |
1afcfd54 | 485 | !(filter_flags & (FIF_CONTROL | FIF_PSPOLL))); |
3a643d24 ID |
486 | rt2x00_set_field32(®, TXRX_CSR0_DROP_NOT_TO_ME, |
487 | !(filter_flags & FIF_PROMISC_IN_BSS)); | |
488 | rt2x00_set_field32(®, TXRX_CSR0_DROP_TO_DS, | |
e0b005fa ID |
489 | !(filter_flags & FIF_PROMISC_IN_BSS) && |
490 | !rt2x00dev->intf_ap_count); | |
3a643d24 ID |
491 | rt2x00_set_field32(®, TXRX_CSR0_DROP_VERSION_ERROR, 1); |
492 | rt2x00_set_field32(®, TXRX_CSR0_DROP_MULTICAST, | |
493 | !(filter_flags & FIF_ALLMULTI)); | |
494 | rt2x00_set_field32(®, TXRX_CSR0_DROP_BROADCAST, 0); | |
495 | rt2x00_set_field32(®, TXRX_CSR0_DROP_ACK_CTS, | |
496 | !(filter_flags & FIF_CONTROL)); | |
0f829b1d | 497 | rt2x00usb_register_write(rt2x00dev, TXRX_CSR0, reg); |
3a643d24 ID |
498 | } |
499 | ||
6bb40dd1 ID |
500 | static void rt73usb_config_intf(struct rt2x00_dev *rt2x00dev, |
501 | struct rt2x00_intf *intf, | |
502 | struct rt2x00intf_conf *conf, | |
503 | const unsigned int flags) | |
95ea3627 | 504 | { |
6bb40dd1 ID |
505 | unsigned int beacon_base; |
506 | u32 reg; | |
95ea3627 | 507 | |
6bb40dd1 ID |
508 | if (flags & CONFIG_UPDATE_TYPE) { |
509 | /* | |
510 | * Clear current synchronisation setup. | |
511 | * For the Beacon base registers we only need to clear | |
512 | * the first byte since that byte contains the VALID and OWNER | |
513 | * bits which (when set to 0) will invalidate the entire beacon. | |
514 | */ | |
515 | beacon_base = HW_BEACON_OFFSET(intf->beacon->entry_idx); | |
0f829b1d | 516 | rt2x00usb_register_write(rt2x00dev, beacon_base, 0); |
95ea3627 | 517 | |
6bb40dd1 ID |
518 | /* |
519 | * Enable synchronisation. | |
520 | */ | |
0f829b1d | 521 | rt2x00usb_register_read(rt2x00dev, TXRX_CSR9, ®); |
fd3c91c5 | 522 | rt2x00_set_field32(®, TXRX_CSR9_TSF_TICKING, 1); |
6bb40dd1 | 523 | rt2x00_set_field32(®, TXRX_CSR9_TSF_SYNC, conf->sync); |
fd3c91c5 | 524 | rt2x00_set_field32(®, TXRX_CSR9_TBTT_ENABLE, 1); |
0f829b1d | 525 | rt2x00usb_register_write(rt2x00dev, TXRX_CSR9, reg); |
6bb40dd1 | 526 | } |
95ea3627 | 527 | |
6bb40dd1 ID |
528 | if (flags & CONFIG_UPDATE_MAC) { |
529 | reg = le32_to_cpu(conf->mac[1]); | |
530 | rt2x00_set_field32(®, MAC_CSR3_UNICAST_TO_ME_MASK, 0xff); | |
531 | conf->mac[1] = cpu_to_le32(reg); | |
95ea3627 | 532 | |
0f829b1d | 533 | rt2x00usb_register_multiwrite(rt2x00dev, MAC_CSR2, |
6bb40dd1 ID |
534 | conf->mac, sizeof(conf->mac)); |
535 | } | |
95ea3627 | 536 | |
6bb40dd1 ID |
537 | if (flags & CONFIG_UPDATE_BSSID) { |
538 | reg = le32_to_cpu(conf->bssid[1]); | |
539 | rt2x00_set_field32(®, MAC_CSR5_BSS_ID_MASK, 3); | |
540 | conf->bssid[1] = cpu_to_le32(reg); | |
95ea3627 | 541 | |
0f829b1d | 542 | rt2x00usb_register_multiwrite(rt2x00dev, MAC_CSR4, |
6bb40dd1 ID |
543 | conf->bssid, sizeof(conf->bssid)); |
544 | } | |
95ea3627 ID |
545 | } |
546 | ||
3a643d24 | 547 | static void rt73usb_config_erp(struct rt2x00_dev *rt2x00dev, |
02044643 HS |
548 | struct rt2x00lib_erp *erp, |
549 | u32 changed) | |
95ea3627 | 550 | { |
95ea3627 | 551 | u32 reg; |
95ea3627 | 552 | |
0f829b1d | 553 | rt2x00usb_register_read(rt2x00dev, TXRX_CSR0, ®); |
4789666e | 554 | rt2x00_set_field32(®, TXRX_CSR0_RX_ACK_TIMEOUT, 0x32); |
8a566afe | 555 | rt2x00_set_field32(®, TXRX_CSR0_TSF_OFFSET, IEEE80211_HEADER); |
0f829b1d | 556 | rt2x00usb_register_write(rt2x00dev, TXRX_CSR0, reg); |
95ea3627 | 557 | |
02044643 HS |
558 | if (changed & BSS_CHANGED_ERP_PREAMBLE) { |
559 | rt2x00usb_register_read(rt2x00dev, TXRX_CSR4, ®); | |
560 | rt2x00_set_field32(®, TXRX_CSR4_AUTORESPOND_ENABLE, 1); | |
561 | rt2x00_set_field32(®, TXRX_CSR4_AUTORESPOND_PREAMBLE, | |
562 | !!erp->short_preamble); | |
563 | rt2x00usb_register_write(rt2x00dev, TXRX_CSR4, reg); | |
564 | } | |
95ea3627 | 565 | |
02044643 HS |
566 | if (changed & BSS_CHANGED_BASIC_RATES) |
567 | rt2x00usb_register_write(rt2x00dev, TXRX_CSR5, | |
568 | erp->basic_rates); | |
95ea3627 | 569 | |
02044643 HS |
570 | if (changed & BSS_CHANGED_BEACON_INT) { |
571 | rt2x00usb_register_read(rt2x00dev, TXRX_CSR9, ®); | |
572 | rt2x00_set_field32(®, TXRX_CSR9_BEACON_INTERVAL, | |
573 | erp->beacon_int * 16); | |
574 | rt2x00usb_register_write(rt2x00dev, TXRX_CSR9, reg); | |
575 | } | |
8a566afe | 576 | |
02044643 HS |
577 | if (changed & BSS_CHANGED_ERP_SLOT) { |
578 | rt2x00usb_register_read(rt2x00dev, MAC_CSR9, ®); | |
579 | rt2x00_set_field32(®, MAC_CSR9_SLOT_TIME, erp->slot_time); | |
580 | rt2x00usb_register_write(rt2x00dev, MAC_CSR9, reg); | |
95ea3627 | 581 | |
02044643 HS |
582 | rt2x00usb_register_read(rt2x00dev, MAC_CSR8, ®); |
583 | rt2x00_set_field32(®, MAC_CSR8_SIFS, erp->sifs); | |
584 | rt2x00_set_field32(®, MAC_CSR8_SIFS_AFTER_RX_OFDM, 3); | |
585 | rt2x00_set_field32(®, MAC_CSR8_EIFS, erp->eifs); | |
586 | rt2x00usb_register_write(rt2x00dev, MAC_CSR8, reg); | |
587 | } | |
95ea3627 ID |
588 | } |
589 | ||
590 | static void rt73usb_config_antenna_5x(struct rt2x00_dev *rt2x00dev, | |
addc81bd | 591 | struct antenna_setup *ant) |
95ea3627 ID |
592 | { |
593 | u8 r3; | |
594 | u8 r4; | |
595 | u8 r77; | |
2676c94d | 596 | u8 temp; |
95ea3627 ID |
597 | |
598 | rt73usb_bbp_read(rt2x00dev, 3, &r3); | |
599 | rt73usb_bbp_read(rt2x00dev, 4, &r4); | |
600 | rt73usb_bbp_read(rt2x00dev, 77, &r77); | |
601 | ||
602 | rt2x00_set_field8(&r3, BBP_R3_SMART_MODE, 0); | |
603 | ||
e4cd2ff8 ID |
604 | /* |
605 | * Configure the RX antenna. | |
606 | */ | |
addc81bd | 607 | switch (ant->rx) { |
95ea3627 | 608 | case ANTENNA_HW_DIVERSITY: |
2676c94d MN |
609 | rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA_CONTROL, 2); |
610 | temp = !test_bit(CONFIG_FRAME_TYPE, &rt2x00dev->flags) | |
8318d78a | 611 | && (rt2x00dev->curr_band != IEEE80211_BAND_5GHZ); |
2676c94d | 612 | rt2x00_set_field8(&r4, BBP_R4_RX_FRAME_END, temp); |
95ea3627 ID |
613 | break; |
614 | case ANTENNA_A: | |
2676c94d | 615 | rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA_CONTROL, 1); |
95ea3627 | 616 | rt2x00_set_field8(&r4, BBP_R4_RX_FRAME_END, 0); |
8318d78a | 617 | if (rt2x00dev->curr_band == IEEE80211_BAND_5GHZ) |
2676c94d MN |
618 | rt2x00_set_field8(&r77, BBP_R77_RX_ANTENNA, 0); |
619 | else | |
620 | rt2x00_set_field8(&r77, BBP_R77_RX_ANTENNA, 3); | |
95ea3627 ID |
621 | break; |
622 | case ANTENNA_B: | |
a4fe07d9 | 623 | default: |
2676c94d | 624 | rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA_CONTROL, 1); |
95ea3627 | 625 | rt2x00_set_field8(&r4, BBP_R4_RX_FRAME_END, 0); |
8318d78a | 626 | if (rt2x00dev->curr_band == IEEE80211_BAND_5GHZ) |
2676c94d MN |
627 | rt2x00_set_field8(&r77, BBP_R77_RX_ANTENNA, 3); |
628 | else | |
629 | rt2x00_set_field8(&r77, BBP_R77_RX_ANTENNA, 0); | |
95ea3627 ID |
630 | break; |
631 | } | |
632 | ||
633 | rt73usb_bbp_write(rt2x00dev, 77, r77); | |
634 | rt73usb_bbp_write(rt2x00dev, 3, r3); | |
635 | rt73usb_bbp_write(rt2x00dev, 4, r4); | |
636 | } | |
637 | ||
638 | static void rt73usb_config_antenna_2x(struct rt2x00_dev *rt2x00dev, | |
addc81bd | 639 | struct antenna_setup *ant) |
95ea3627 ID |
640 | { |
641 | u8 r3; | |
642 | u8 r4; | |
643 | u8 r77; | |
644 | ||
645 | rt73usb_bbp_read(rt2x00dev, 3, &r3); | |
646 | rt73usb_bbp_read(rt2x00dev, 4, &r4); | |
647 | rt73usb_bbp_read(rt2x00dev, 77, &r77); | |
648 | ||
649 | rt2x00_set_field8(&r3, BBP_R3_SMART_MODE, 0); | |
650 | rt2x00_set_field8(&r4, BBP_R4_RX_FRAME_END, | |
651 | !test_bit(CONFIG_FRAME_TYPE, &rt2x00dev->flags)); | |
652 | ||
e4cd2ff8 ID |
653 | /* |
654 | * Configure the RX antenna. | |
655 | */ | |
addc81bd | 656 | switch (ant->rx) { |
95ea3627 | 657 | case ANTENNA_HW_DIVERSITY: |
2676c94d | 658 | rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA_CONTROL, 2); |
95ea3627 ID |
659 | break; |
660 | case ANTENNA_A: | |
2676c94d MN |
661 | rt2x00_set_field8(&r77, BBP_R77_RX_ANTENNA, 3); |
662 | rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA_CONTROL, 1); | |
95ea3627 ID |
663 | break; |
664 | case ANTENNA_B: | |
a4fe07d9 | 665 | default: |
2676c94d MN |
666 | rt2x00_set_field8(&r77, BBP_R77_RX_ANTENNA, 0); |
667 | rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA_CONTROL, 1); | |
95ea3627 ID |
668 | break; |
669 | } | |
670 | ||
671 | rt73usb_bbp_write(rt2x00dev, 77, r77); | |
672 | rt73usb_bbp_write(rt2x00dev, 3, r3); | |
673 | rt73usb_bbp_write(rt2x00dev, 4, r4); | |
674 | } | |
675 | ||
676 | struct antenna_sel { | |
677 | u8 word; | |
678 | /* | |
679 | * value[0] -> non-LNA | |
680 | * value[1] -> LNA | |
681 | */ | |
682 | u8 value[2]; | |
683 | }; | |
684 | ||
685 | static const struct antenna_sel antenna_sel_a[] = { | |
686 | { 96, { 0x58, 0x78 } }, | |
687 | { 104, { 0x38, 0x48 } }, | |
688 | { 75, { 0xfe, 0x80 } }, | |
689 | { 86, { 0xfe, 0x80 } }, | |
690 | { 88, { 0xfe, 0x80 } }, | |
691 | { 35, { 0x60, 0x60 } }, | |
692 | { 97, { 0x58, 0x58 } }, | |
693 | { 98, { 0x58, 0x58 } }, | |
694 | }; | |
695 | ||
696 | static const struct antenna_sel antenna_sel_bg[] = { | |
697 | { 96, { 0x48, 0x68 } }, | |
698 | { 104, { 0x2c, 0x3c } }, | |
699 | { 75, { 0xfe, 0x80 } }, | |
700 | { 86, { 0xfe, 0x80 } }, | |
701 | { 88, { 0xfe, 0x80 } }, | |
702 | { 35, { 0x50, 0x50 } }, | |
703 | { 97, { 0x48, 0x48 } }, | |
704 | { 98, { 0x48, 0x48 } }, | |
705 | }; | |
706 | ||
e4ea1c40 ID |
707 | static void rt73usb_config_ant(struct rt2x00_dev *rt2x00dev, |
708 | struct antenna_setup *ant) | |
95ea3627 ID |
709 | { |
710 | const struct antenna_sel *sel; | |
711 | unsigned int lna; | |
712 | unsigned int i; | |
713 | u32 reg; | |
714 | ||
a4fe07d9 ID |
715 | /* |
716 | * We should never come here because rt2x00lib is supposed | |
717 | * to catch this and send us the correct antenna explicitely. | |
718 | */ | |
719 | BUG_ON(ant->rx == ANTENNA_SW_DIVERSITY || | |
720 | ant->tx == ANTENNA_SW_DIVERSITY); | |
721 | ||
8318d78a | 722 | if (rt2x00dev->curr_band == IEEE80211_BAND_5GHZ) { |
95ea3627 ID |
723 | sel = antenna_sel_a; |
724 | lna = test_bit(CONFIG_EXTERNAL_LNA_A, &rt2x00dev->flags); | |
95ea3627 ID |
725 | } else { |
726 | sel = antenna_sel_bg; | |
727 | lna = test_bit(CONFIG_EXTERNAL_LNA_BG, &rt2x00dev->flags); | |
95ea3627 ID |
728 | } |
729 | ||
2676c94d MN |
730 | for (i = 0; i < ARRAY_SIZE(antenna_sel_a); i++) |
731 | rt73usb_bbp_write(rt2x00dev, sel[i].word, sel[i].value[lna]); | |
732 | ||
0f829b1d | 733 | rt2x00usb_register_read(rt2x00dev, PHY_CSR0, ®); |
2676c94d | 734 | |
ddc827f9 | 735 | rt2x00_set_field32(®, PHY_CSR0_PA_PE_BG, |
8318d78a | 736 | (rt2x00dev->curr_band == IEEE80211_BAND_2GHZ)); |
ddc827f9 | 737 | rt2x00_set_field32(®, PHY_CSR0_PA_PE_A, |
8318d78a | 738 | (rt2x00dev->curr_band == IEEE80211_BAND_5GHZ)); |
ddc827f9 | 739 | |
0f829b1d | 740 | rt2x00usb_register_write(rt2x00dev, PHY_CSR0, reg); |
95ea3627 | 741 | |
5122d898 | 742 | if (rt2x00_rf(rt2x00dev, RF5226) || rt2x00_rf(rt2x00dev, RF5225)) |
addc81bd | 743 | rt73usb_config_antenna_5x(rt2x00dev, ant); |
5122d898 | 744 | else if (rt2x00_rf(rt2x00dev, RF2528) || rt2x00_rf(rt2x00dev, RF2527)) |
addc81bd | 745 | rt73usb_config_antenna_2x(rt2x00dev, ant); |
95ea3627 ID |
746 | } |
747 | ||
e4ea1c40 | 748 | static void rt73usb_config_lna_gain(struct rt2x00_dev *rt2x00dev, |
5c58ee51 | 749 | struct rt2x00lib_conf *libconf) |
e4ea1c40 ID |
750 | { |
751 | u16 eeprom; | |
752 | short lna_gain = 0; | |
753 | ||
754 | if (libconf->conf->channel->band == IEEE80211_BAND_2GHZ) { | |
755 | if (test_bit(CONFIG_EXTERNAL_LNA_BG, &rt2x00dev->flags)) | |
756 | lna_gain += 14; | |
757 | ||
758 | rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_OFFSET_BG, &eeprom); | |
759 | lna_gain -= rt2x00_get_field16(eeprom, EEPROM_RSSI_OFFSET_BG_1); | |
760 | } else { | |
761 | rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_OFFSET_A, &eeprom); | |
762 | lna_gain -= rt2x00_get_field16(eeprom, EEPROM_RSSI_OFFSET_A_1); | |
763 | } | |
764 | ||
765 | rt2x00dev->lna_gain = lna_gain; | |
766 | } | |
767 | ||
768 | static void rt73usb_config_channel(struct rt2x00_dev *rt2x00dev, | |
769 | struct rf_channel *rf, const int txpower) | |
770 | { | |
771 | u8 r3; | |
772 | u8 r94; | |
773 | u8 smart; | |
774 | ||
775 | rt2x00_set_field32(&rf->rf3, RF3_TXPOWER, TXPOWER_TO_DEV(txpower)); | |
776 | rt2x00_set_field32(&rf->rf4, RF4_FREQ_OFFSET, rt2x00dev->freq_offset); | |
777 | ||
5122d898 | 778 | smart = !(rt2x00_rf(rt2x00dev, RF5225) || rt2x00_rf(rt2x00dev, RF2527)); |
e4ea1c40 ID |
779 | |
780 | rt73usb_bbp_read(rt2x00dev, 3, &r3); | |
781 | rt2x00_set_field8(&r3, BBP_R3_SMART_MODE, smart); | |
782 | rt73usb_bbp_write(rt2x00dev, 3, r3); | |
783 | ||
784 | r94 = 6; | |
785 | if (txpower > MAX_TXPOWER && txpower <= (MAX_TXPOWER + r94)) | |
786 | r94 += txpower - MAX_TXPOWER; | |
787 | else if (txpower < MIN_TXPOWER && txpower >= (MIN_TXPOWER - r94)) | |
788 | r94 += txpower; | |
789 | rt73usb_bbp_write(rt2x00dev, 94, r94); | |
790 | ||
791 | rt73usb_rf_write(rt2x00dev, 1, rf->rf1); | |
792 | rt73usb_rf_write(rt2x00dev, 2, rf->rf2); | |
793 | rt73usb_rf_write(rt2x00dev, 3, rf->rf3 & ~0x00000004); | |
794 | rt73usb_rf_write(rt2x00dev, 4, rf->rf4); | |
795 | ||
796 | rt73usb_rf_write(rt2x00dev, 1, rf->rf1); | |
797 | rt73usb_rf_write(rt2x00dev, 2, rf->rf2); | |
798 | rt73usb_rf_write(rt2x00dev, 3, rf->rf3 | 0x00000004); | |
799 | rt73usb_rf_write(rt2x00dev, 4, rf->rf4); | |
800 | ||
801 | rt73usb_rf_write(rt2x00dev, 1, rf->rf1); | |
802 | rt73usb_rf_write(rt2x00dev, 2, rf->rf2); | |
803 | rt73usb_rf_write(rt2x00dev, 3, rf->rf3 & ~0x00000004); | |
804 | rt73usb_rf_write(rt2x00dev, 4, rf->rf4); | |
805 | ||
806 | udelay(10); | |
807 | } | |
808 | ||
809 | static void rt73usb_config_txpower(struct rt2x00_dev *rt2x00dev, | |
810 | const int txpower) | |
811 | { | |
812 | struct rf_channel rf; | |
813 | ||
814 | rt2x00_rf_read(rt2x00dev, 1, &rf.rf1); | |
815 | rt2x00_rf_read(rt2x00dev, 2, &rf.rf2); | |
816 | rt2x00_rf_read(rt2x00dev, 3, &rf.rf3); | |
817 | rt2x00_rf_read(rt2x00dev, 4, &rf.rf4); | |
818 | ||
819 | rt73usb_config_channel(rt2x00dev, &rf, txpower); | |
820 | } | |
821 | ||
822 | static void rt73usb_config_retry_limit(struct rt2x00_dev *rt2x00dev, | |
823 | struct rt2x00lib_conf *libconf) | |
95ea3627 ID |
824 | { |
825 | u32 reg; | |
826 | ||
0f829b1d | 827 | rt2x00usb_register_read(rt2x00dev, TXRX_CSR4, ®); |
e1b4d7b7 ID |
828 | rt2x00_set_field32(®, TXRX_CSR4_OFDM_TX_RATE_DOWN, 1); |
829 | rt2x00_set_field32(®, TXRX_CSR4_OFDM_TX_RATE_STEP, 0); | |
830 | rt2x00_set_field32(®, TXRX_CSR4_OFDM_TX_FALLBACK_CCK, 0); | |
e4ea1c40 ID |
831 | rt2x00_set_field32(®, TXRX_CSR4_LONG_RETRY_LIMIT, |
832 | libconf->conf->long_frame_max_tx_count); | |
833 | rt2x00_set_field32(®, TXRX_CSR4_SHORT_RETRY_LIMIT, | |
834 | libconf->conf->short_frame_max_tx_count); | |
0f829b1d | 835 | rt2x00usb_register_write(rt2x00dev, TXRX_CSR4, reg); |
e4ea1c40 | 836 | } |
95ea3627 | 837 | |
7d7f19cc ID |
838 | static void rt73usb_config_ps(struct rt2x00_dev *rt2x00dev, |
839 | struct rt2x00lib_conf *libconf) | |
840 | { | |
841 | enum dev_state state = | |
842 | (libconf->conf->flags & IEEE80211_CONF_PS) ? | |
843 | STATE_SLEEP : STATE_AWAKE; | |
844 | u32 reg; | |
845 | ||
846 | if (state == STATE_SLEEP) { | |
847 | rt2x00usb_register_read(rt2x00dev, MAC_CSR11, ®); | |
848 | rt2x00_set_field32(®, MAC_CSR11_DELAY_AFTER_TBCN, | |
6b347bff | 849 | rt2x00dev->beacon_int - 10); |
7d7f19cc ID |
850 | rt2x00_set_field32(®, MAC_CSR11_TBCN_BEFORE_WAKEUP, |
851 | libconf->conf->listen_interval - 1); | |
852 | rt2x00_set_field32(®, MAC_CSR11_WAKEUP_LATENCY, 5); | |
853 | ||
854 | /* We must first disable autowake before it can be enabled */ | |
855 | rt2x00_set_field32(®, MAC_CSR11_AUTOWAKE, 0); | |
856 | rt2x00usb_register_write(rt2x00dev, MAC_CSR11, reg); | |
857 | ||
858 | rt2x00_set_field32(®, MAC_CSR11_AUTOWAKE, 1); | |
859 | rt2x00usb_register_write(rt2x00dev, MAC_CSR11, reg); | |
860 | ||
861 | rt2x00usb_vendor_request_sw(rt2x00dev, USB_DEVICE_MODE, 0, | |
862 | USB_MODE_SLEEP, REGISTER_TIMEOUT); | |
863 | } else { | |
7d7f19cc ID |
864 | rt2x00usb_register_read(rt2x00dev, MAC_CSR11, ®); |
865 | rt2x00_set_field32(®, MAC_CSR11_DELAY_AFTER_TBCN, 0); | |
866 | rt2x00_set_field32(®, MAC_CSR11_TBCN_BEFORE_WAKEUP, 0); | |
867 | rt2x00_set_field32(®, MAC_CSR11_AUTOWAKE, 0); | |
868 | rt2x00_set_field32(®, MAC_CSR11_WAKEUP_LATENCY, 0); | |
869 | rt2x00usb_register_write(rt2x00dev, MAC_CSR11, reg); | |
5731858d GW |
870 | |
871 | rt2x00usb_vendor_request_sw(rt2x00dev, USB_DEVICE_MODE, 0, | |
872 | USB_MODE_WAKEUP, REGISTER_TIMEOUT); | |
7d7f19cc ID |
873 | } |
874 | } | |
875 | ||
95ea3627 | 876 | static void rt73usb_config(struct rt2x00_dev *rt2x00dev, |
6bb40dd1 ID |
877 | struct rt2x00lib_conf *libconf, |
878 | const unsigned int flags) | |
95ea3627 | 879 | { |
ba2ab471 ID |
880 | /* Always recalculate LNA gain before changing configuration */ |
881 | rt73usb_config_lna_gain(rt2x00dev, libconf); | |
882 | ||
e4ea1c40 | 883 | if (flags & IEEE80211_CONF_CHANGE_CHANNEL) |
5c58ee51 ID |
884 | rt73usb_config_channel(rt2x00dev, &libconf->rf, |
885 | libconf->conf->power_level); | |
e4ea1c40 ID |
886 | if ((flags & IEEE80211_CONF_CHANGE_POWER) && |
887 | !(flags & IEEE80211_CONF_CHANGE_CHANNEL)) | |
5c58ee51 | 888 | rt73usb_config_txpower(rt2x00dev, libconf->conf->power_level); |
e4ea1c40 ID |
889 | if (flags & IEEE80211_CONF_CHANGE_RETRY_LIMITS) |
890 | rt73usb_config_retry_limit(rt2x00dev, libconf); | |
7d7f19cc ID |
891 | if (flags & IEEE80211_CONF_CHANGE_PS) |
892 | rt73usb_config_ps(rt2x00dev, libconf); | |
95ea3627 ID |
893 | } |
894 | ||
95ea3627 ID |
895 | /* |
896 | * Link tuning | |
897 | */ | |
ebcf26da ID |
898 | static void rt73usb_link_stats(struct rt2x00_dev *rt2x00dev, |
899 | struct link_qual *qual) | |
95ea3627 ID |
900 | { |
901 | u32 reg; | |
902 | ||
903 | /* | |
904 | * Update FCS error count from register. | |
905 | */ | |
0f829b1d | 906 | rt2x00usb_register_read(rt2x00dev, STA_CSR0, ®); |
ebcf26da | 907 | qual->rx_failed = rt2x00_get_field32(reg, STA_CSR0_FCS_ERROR); |
95ea3627 ID |
908 | |
909 | /* | |
910 | * Update False CCA count from register. | |
911 | */ | |
0f829b1d | 912 | rt2x00usb_register_read(rt2x00dev, STA_CSR1, ®); |
ebcf26da | 913 | qual->false_cca = rt2x00_get_field32(reg, STA_CSR1_FALSE_CCA_ERROR); |
95ea3627 ID |
914 | } |
915 | ||
5352ff65 ID |
916 | static inline void rt73usb_set_vgc(struct rt2x00_dev *rt2x00dev, |
917 | struct link_qual *qual, u8 vgc_level) | |
eb20b4e8 | 918 | { |
5352ff65 | 919 | if (qual->vgc_level != vgc_level) { |
eb20b4e8 | 920 | rt73usb_bbp_write(rt2x00dev, 17, vgc_level); |
5352ff65 ID |
921 | qual->vgc_level = vgc_level; |
922 | qual->vgc_level_reg = vgc_level; | |
eb20b4e8 ID |
923 | } |
924 | } | |
925 | ||
5352ff65 ID |
926 | static void rt73usb_reset_tuner(struct rt2x00_dev *rt2x00dev, |
927 | struct link_qual *qual) | |
95ea3627 | 928 | { |
5352ff65 | 929 | rt73usb_set_vgc(rt2x00dev, qual, 0x20); |
95ea3627 ID |
930 | } |
931 | ||
5352ff65 ID |
932 | static void rt73usb_link_tuner(struct rt2x00_dev *rt2x00dev, |
933 | struct link_qual *qual, const u32 count) | |
95ea3627 | 934 | { |
95ea3627 ID |
935 | u8 up_bound; |
936 | u8 low_bound; | |
937 | ||
95ea3627 ID |
938 | /* |
939 | * Determine r17 bounds. | |
940 | */ | |
e5ef5bad | 941 | if (rt2x00dev->curr_band == IEEE80211_BAND_5GHZ) { |
95ea3627 ID |
942 | low_bound = 0x28; |
943 | up_bound = 0x48; | |
944 | ||
945 | if (test_bit(CONFIG_EXTERNAL_LNA_A, &rt2x00dev->flags)) { | |
946 | low_bound += 0x10; | |
947 | up_bound += 0x10; | |
948 | } | |
949 | } else { | |
5352ff65 | 950 | if (qual->rssi > -82) { |
95ea3627 ID |
951 | low_bound = 0x1c; |
952 | up_bound = 0x40; | |
5352ff65 | 953 | } else if (qual->rssi > -84) { |
95ea3627 ID |
954 | low_bound = 0x1c; |
955 | up_bound = 0x20; | |
956 | } else { | |
957 | low_bound = 0x1c; | |
958 | up_bound = 0x1c; | |
959 | } | |
960 | ||
961 | if (test_bit(CONFIG_EXTERNAL_LNA_BG, &rt2x00dev->flags)) { | |
962 | low_bound += 0x14; | |
963 | up_bound += 0x10; | |
964 | } | |
965 | } | |
966 | ||
6bb40dd1 ID |
967 | /* |
968 | * If we are not associated, we should go straight to the | |
969 | * dynamic CCA tuning. | |
970 | */ | |
971 | if (!rt2x00dev->intf_associated) | |
972 | goto dynamic_cca_tune; | |
973 | ||
95ea3627 ID |
974 | /* |
975 | * Special big-R17 for very short distance | |
976 | */ | |
5352ff65 ID |
977 | if (qual->rssi > -35) { |
978 | rt73usb_set_vgc(rt2x00dev, qual, 0x60); | |
95ea3627 ID |
979 | return; |
980 | } | |
981 | ||
982 | /* | |
983 | * Special big-R17 for short distance | |
984 | */ | |
5352ff65 ID |
985 | if (qual->rssi >= -58) { |
986 | rt73usb_set_vgc(rt2x00dev, qual, up_bound); | |
95ea3627 ID |
987 | return; |
988 | } | |
989 | ||
990 | /* | |
991 | * Special big-R17 for middle-short distance | |
992 | */ | |
5352ff65 ID |
993 | if (qual->rssi >= -66) { |
994 | rt73usb_set_vgc(rt2x00dev, qual, low_bound + 0x10); | |
95ea3627 ID |
995 | return; |
996 | } | |
997 | ||
998 | /* | |
999 | * Special mid-R17 for middle distance | |
1000 | */ | |
5352ff65 ID |
1001 | if (qual->rssi >= -74) { |
1002 | rt73usb_set_vgc(rt2x00dev, qual, low_bound + 0x08); | |
95ea3627 ID |
1003 | return; |
1004 | } | |
1005 | ||
1006 | /* | |
1007 | * Special case: Change up_bound based on the rssi. | |
1008 | * Lower up_bound when rssi is weaker then -74 dBm. | |
1009 | */ | |
5352ff65 | 1010 | up_bound -= 2 * (-74 - qual->rssi); |
95ea3627 ID |
1011 | if (low_bound > up_bound) |
1012 | up_bound = low_bound; | |
1013 | ||
5352ff65 ID |
1014 | if (qual->vgc_level > up_bound) { |
1015 | rt73usb_set_vgc(rt2x00dev, qual, up_bound); | |
95ea3627 ID |
1016 | return; |
1017 | } | |
1018 | ||
6bb40dd1 ID |
1019 | dynamic_cca_tune: |
1020 | ||
95ea3627 ID |
1021 | /* |
1022 | * r17 does not yet exceed upper limit, continue and base | |
1023 | * the r17 tuning on the false CCA count. | |
1024 | */ | |
5352ff65 ID |
1025 | if ((qual->false_cca > 512) && (qual->vgc_level < up_bound)) |
1026 | rt73usb_set_vgc(rt2x00dev, qual, | |
1027 | min_t(u8, qual->vgc_level + 4, up_bound)); | |
1028 | else if ((qual->false_cca < 100) && (qual->vgc_level > low_bound)) | |
1029 | rt73usb_set_vgc(rt2x00dev, qual, | |
1030 | max_t(u8, qual->vgc_level - 4, low_bound)); | |
95ea3627 ID |
1031 | } |
1032 | ||
5450b7e2 ID |
1033 | /* |
1034 | * Queue handlers. | |
1035 | */ | |
1036 | static void rt73usb_start_queue(struct data_queue *queue) | |
1037 | { | |
1038 | struct rt2x00_dev *rt2x00dev = queue->rt2x00dev; | |
1039 | u32 reg; | |
1040 | ||
1041 | switch (queue->qid) { | |
1042 | case QID_RX: | |
1043 | rt2x00usb_register_read(rt2x00dev, TXRX_CSR0, ®); | |
1044 | rt2x00_set_field32(®, TXRX_CSR0_DISABLE_RX, 0); | |
1045 | rt2x00usb_register_write(rt2x00dev, TXRX_CSR0, reg); | |
1046 | break; | |
1047 | case QID_BEACON: | |
1048 | rt2x00usb_register_read(rt2x00dev, TXRX_CSR9, ®); | |
1049 | rt2x00_set_field32(®, TXRX_CSR9_TSF_TICKING, 1); | |
1050 | rt2x00_set_field32(®, TXRX_CSR9_TBTT_ENABLE, 1); | |
1051 | rt2x00_set_field32(®, TXRX_CSR9_BEACON_GEN, 1); | |
1052 | rt2x00usb_register_write(rt2x00dev, TXRX_CSR9, reg); | |
1053 | break; | |
1054 | default: | |
1055 | break; | |
1056 | } | |
1057 | } | |
1058 | ||
1059 | static void rt73usb_stop_queue(struct data_queue *queue) | |
1060 | { | |
1061 | struct rt2x00_dev *rt2x00dev = queue->rt2x00dev; | |
1062 | u32 reg; | |
1063 | ||
1064 | switch (queue->qid) { | |
1065 | case QID_RX: | |
1066 | rt2x00usb_register_read(rt2x00dev, TXRX_CSR0, ®); | |
1067 | rt2x00_set_field32(®, TXRX_CSR0_DISABLE_RX, 1); | |
1068 | rt2x00usb_register_write(rt2x00dev, TXRX_CSR0, reg); | |
1069 | break; | |
1070 | case QID_BEACON: | |
1071 | rt2x00usb_register_read(rt2x00dev, TXRX_CSR9, ®); | |
1072 | rt2x00_set_field32(®, TXRX_CSR9_TSF_TICKING, 0); | |
1073 | rt2x00_set_field32(®, TXRX_CSR9_TBTT_ENABLE, 0); | |
1074 | rt2x00_set_field32(®, TXRX_CSR9_BEACON_GEN, 0); | |
1075 | rt2x00usb_register_write(rt2x00dev, TXRX_CSR9, reg); | |
1076 | break; | |
1077 | default: | |
1078 | break; | |
1079 | } | |
5450b7e2 ID |
1080 | } |
1081 | ||
95ea3627 | 1082 | /* |
a7f3a06c | 1083 | * Firmware functions |
95ea3627 ID |
1084 | */ |
1085 | static char *rt73usb_get_firmware_name(struct rt2x00_dev *rt2x00dev) | |
1086 | { | |
1087 | return FIRMWARE_RT2571; | |
1088 | } | |
1089 | ||
0cbe0064 ID |
1090 | static int rt73usb_check_firmware(struct rt2x00_dev *rt2x00dev, |
1091 | const u8 *data, const size_t len) | |
a7f3a06c | 1092 | { |
0cbe0064 | 1093 | u16 fw_crc; |
a7f3a06c ID |
1094 | u16 crc; |
1095 | ||
1096 | /* | |
0cbe0064 ID |
1097 | * Only support 2kb firmware files. |
1098 | */ | |
1099 | if (len != 2048) | |
1100 | return FW_BAD_LENGTH; | |
1101 | ||
1102 | /* | |
a7f3a06c ID |
1103 | * The last 2 bytes in the firmware array are the crc checksum itself, |
1104 | * this means that we should never pass those 2 bytes to the crc | |
1105 | * algorithm. | |
1106 | */ | |
0cbe0064 ID |
1107 | fw_crc = (data[len - 2] << 8 | data[len - 1]); |
1108 | ||
1109 | /* | |
1110 | * Use the crc itu-t algorithm. | |
1111 | */ | |
a7f3a06c ID |
1112 | crc = crc_itu_t(0, data, len - 2); |
1113 | crc = crc_itu_t_byte(crc, 0); | |
1114 | crc = crc_itu_t_byte(crc, 0); | |
1115 | ||
0cbe0064 | 1116 | return (fw_crc == crc) ? FW_OK : FW_BAD_CRC; |
a7f3a06c ID |
1117 | } |
1118 | ||
0cbe0064 ID |
1119 | static int rt73usb_load_firmware(struct rt2x00_dev *rt2x00dev, |
1120 | const u8 *data, const size_t len) | |
95ea3627 ID |
1121 | { |
1122 | unsigned int i; | |
1123 | int status; | |
1124 | u32 reg; | |
95ea3627 ID |
1125 | |
1126 | /* | |
1127 | * Wait for stable hardware. | |
1128 | */ | |
1129 | for (i = 0; i < 100; i++) { | |
0f829b1d | 1130 | rt2x00usb_register_read(rt2x00dev, MAC_CSR0, ®); |
95ea3627 ID |
1131 | if (reg) |
1132 | break; | |
1133 | msleep(1); | |
1134 | } | |
1135 | ||
1136 | if (!reg) { | |
1137 | ERROR(rt2x00dev, "Unstable hardware.\n"); | |
1138 | return -EBUSY; | |
1139 | } | |
1140 | ||
1141 | /* | |
1142 | * Write firmware to device. | |
95ea3627 | 1143 | */ |
96b61baf | 1144 | rt2x00usb_register_multiwrite(rt2x00dev, FIRMWARE_IMAGE_BASE, data, len); |
95ea3627 ID |
1145 | |
1146 | /* | |
1147 | * Send firmware request to device to load firmware, | |
1148 | * we need to specify a long timeout time. | |
1149 | */ | |
1150 | status = rt2x00usb_vendor_request_sw(rt2x00dev, USB_DEVICE_MODE, | |
3b640f21 | 1151 | 0, USB_MODE_FIRMWARE, |
95ea3627 ID |
1152 | REGISTER_TIMEOUT_FIRMWARE); |
1153 | if (status < 0) { | |
1154 | ERROR(rt2x00dev, "Failed to write Firmware to device.\n"); | |
1155 | return status; | |
1156 | } | |
1157 | ||
95ea3627 ID |
1158 | return 0; |
1159 | } | |
1160 | ||
a7f3a06c ID |
1161 | /* |
1162 | * Initialization functions. | |
1163 | */ | |
95ea3627 ID |
1164 | static int rt73usb_init_registers(struct rt2x00_dev *rt2x00dev) |
1165 | { | |
1166 | u32 reg; | |
1167 | ||
0f829b1d | 1168 | rt2x00usb_register_read(rt2x00dev, TXRX_CSR0, ®); |
95ea3627 ID |
1169 | rt2x00_set_field32(®, TXRX_CSR0_AUTO_TX_SEQ, 1); |
1170 | rt2x00_set_field32(®, TXRX_CSR0_DISABLE_RX, 0); | |
1171 | rt2x00_set_field32(®, TXRX_CSR0_TX_WITHOUT_WAITING, 0); | |
0f829b1d | 1172 | rt2x00usb_register_write(rt2x00dev, TXRX_CSR0, reg); |
95ea3627 | 1173 | |
0f829b1d | 1174 | rt2x00usb_register_read(rt2x00dev, TXRX_CSR1, ®); |
95ea3627 ID |
1175 | rt2x00_set_field32(®, TXRX_CSR1_BBP_ID0, 47); /* CCK Signal */ |
1176 | rt2x00_set_field32(®, TXRX_CSR1_BBP_ID0_VALID, 1); | |
1177 | rt2x00_set_field32(®, TXRX_CSR1_BBP_ID1, 30); /* Rssi */ | |
1178 | rt2x00_set_field32(®, TXRX_CSR1_BBP_ID1_VALID, 1); | |
1179 | rt2x00_set_field32(®, TXRX_CSR1_BBP_ID2, 42); /* OFDM Rate */ | |
1180 | rt2x00_set_field32(®, TXRX_CSR1_BBP_ID2_VALID, 1); | |
1181 | rt2x00_set_field32(®, TXRX_CSR1_BBP_ID3, 30); /* Rssi */ | |
1182 | rt2x00_set_field32(®, TXRX_CSR1_BBP_ID3_VALID, 1); | |
0f829b1d | 1183 | rt2x00usb_register_write(rt2x00dev, TXRX_CSR1, reg); |
95ea3627 ID |
1184 | |
1185 | /* | |
1186 | * CCK TXD BBP registers | |
1187 | */ | |
0f829b1d | 1188 | rt2x00usb_register_read(rt2x00dev, TXRX_CSR2, ®); |
95ea3627 ID |
1189 | rt2x00_set_field32(®, TXRX_CSR2_BBP_ID0, 13); |
1190 | rt2x00_set_field32(®, TXRX_CSR2_BBP_ID0_VALID, 1); | |
1191 | rt2x00_set_field32(®, TXRX_CSR2_BBP_ID1, 12); | |
1192 | rt2x00_set_field32(®, TXRX_CSR2_BBP_ID1_VALID, 1); | |
1193 | rt2x00_set_field32(®, TXRX_CSR2_BBP_ID2, 11); | |
1194 | rt2x00_set_field32(®, TXRX_CSR2_BBP_ID2_VALID, 1); | |
1195 | rt2x00_set_field32(®, TXRX_CSR2_BBP_ID3, 10); | |
1196 | rt2x00_set_field32(®, TXRX_CSR2_BBP_ID3_VALID, 1); | |
0f829b1d | 1197 | rt2x00usb_register_write(rt2x00dev, TXRX_CSR2, reg); |
95ea3627 ID |
1198 | |
1199 | /* | |
1200 | * OFDM TXD BBP registers | |
1201 | */ | |
0f829b1d | 1202 | rt2x00usb_register_read(rt2x00dev, TXRX_CSR3, ®); |
95ea3627 ID |
1203 | rt2x00_set_field32(®, TXRX_CSR3_BBP_ID0, 7); |
1204 | rt2x00_set_field32(®, TXRX_CSR3_BBP_ID0_VALID, 1); | |
1205 | rt2x00_set_field32(®, TXRX_CSR3_BBP_ID1, 6); | |
1206 | rt2x00_set_field32(®, TXRX_CSR3_BBP_ID1_VALID, 1); | |
1207 | rt2x00_set_field32(®, TXRX_CSR3_BBP_ID2, 5); | |
1208 | rt2x00_set_field32(®, TXRX_CSR3_BBP_ID2_VALID, 1); | |
0f829b1d | 1209 | rt2x00usb_register_write(rt2x00dev, TXRX_CSR3, reg); |
95ea3627 | 1210 | |
0f829b1d | 1211 | rt2x00usb_register_read(rt2x00dev, TXRX_CSR7, ®); |
95ea3627 ID |
1212 | rt2x00_set_field32(®, TXRX_CSR7_ACK_CTS_6MBS, 59); |
1213 | rt2x00_set_field32(®, TXRX_CSR7_ACK_CTS_9MBS, 53); | |
1214 | rt2x00_set_field32(®, TXRX_CSR7_ACK_CTS_12MBS, 49); | |
1215 | rt2x00_set_field32(®, TXRX_CSR7_ACK_CTS_18MBS, 46); | |
0f829b1d | 1216 | rt2x00usb_register_write(rt2x00dev, TXRX_CSR7, reg); |
95ea3627 | 1217 | |
0f829b1d | 1218 | rt2x00usb_register_read(rt2x00dev, TXRX_CSR8, ®); |
95ea3627 ID |
1219 | rt2x00_set_field32(®, TXRX_CSR8_ACK_CTS_24MBS, 44); |
1220 | rt2x00_set_field32(®, TXRX_CSR8_ACK_CTS_36MBS, 42); | |
1221 | rt2x00_set_field32(®, TXRX_CSR8_ACK_CTS_48MBS, 42); | |
1222 | rt2x00_set_field32(®, TXRX_CSR8_ACK_CTS_54MBS, 42); | |
0f829b1d | 1223 | rt2x00usb_register_write(rt2x00dev, TXRX_CSR8, reg); |
95ea3627 | 1224 | |
0f829b1d | 1225 | rt2x00usb_register_read(rt2x00dev, TXRX_CSR9, ®); |
1f909162 ID |
1226 | rt2x00_set_field32(®, TXRX_CSR9_BEACON_INTERVAL, 0); |
1227 | rt2x00_set_field32(®, TXRX_CSR9_TSF_TICKING, 0); | |
1228 | rt2x00_set_field32(®, TXRX_CSR9_TSF_SYNC, 0); | |
1229 | rt2x00_set_field32(®, TXRX_CSR9_TBTT_ENABLE, 0); | |
1230 | rt2x00_set_field32(®, TXRX_CSR9_BEACON_GEN, 0); | |
1231 | rt2x00_set_field32(®, TXRX_CSR9_TIMESTAMP_COMPENSATE, 0); | |
0f829b1d | 1232 | rt2x00usb_register_write(rt2x00dev, TXRX_CSR9, reg); |
1f909162 | 1233 | |
0f829b1d | 1234 | rt2x00usb_register_write(rt2x00dev, TXRX_CSR15, 0x0000000f); |
95ea3627 | 1235 | |
0f829b1d | 1236 | rt2x00usb_register_read(rt2x00dev, MAC_CSR6, ®); |
95ea3627 | 1237 | rt2x00_set_field32(®, MAC_CSR6_MAX_FRAME_UNIT, 0xfff); |
0f829b1d | 1238 | rt2x00usb_register_write(rt2x00dev, MAC_CSR6, reg); |
95ea3627 | 1239 | |
0f829b1d | 1240 | rt2x00usb_register_write(rt2x00dev, MAC_CSR10, 0x00000718); |
95ea3627 ID |
1241 | |
1242 | if (rt2x00dev->ops->lib->set_device_state(rt2x00dev, STATE_AWAKE)) | |
1243 | return -EBUSY; | |
1244 | ||
0f829b1d | 1245 | rt2x00usb_register_write(rt2x00dev, MAC_CSR13, 0x00007f00); |
95ea3627 ID |
1246 | |
1247 | /* | |
1248 | * Invalidate all Shared Keys (SEC_CSR0), | |
1249 | * and clear the Shared key Cipher algorithms (SEC_CSR1 & SEC_CSR5) | |
1250 | */ | |
0f829b1d ID |
1251 | rt2x00usb_register_write(rt2x00dev, SEC_CSR0, 0x00000000); |
1252 | rt2x00usb_register_write(rt2x00dev, SEC_CSR1, 0x00000000); | |
1253 | rt2x00usb_register_write(rt2x00dev, SEC_CSR5, 0x00000000); | |
95ea3627 ID |
1254 | |
1255 | reg = 0x000023b0; | |
5122d898 | 1256 | if (rt2x00_rf(rt2x00dev, RF5225) || rt2x00_rf(rt2x00dev, RF2527)) |
95ea3627 | 1257 | rt2x00_set_field32(®, PHY_CSR1_RF_RPI, 1); |
0f829b1d | 1258 | rt2x00usb_register_write(rt2x00dev, PHY_CSR1, reg); |
95ea3627 | 1259 | |
0f829b1d ID |
1260 | rt2x00usb_register_write(rt2x00dev, PHY_CSR5, 0x00040a06); |
1261 | rt2x00usb_register_write(rt2x00dev, PHY_CSR6, 0x00080606); | |
1262 | rt2x00usb_register_write(rt2x00dev, PHY_CSR7, 0x00000408); | |
95ea3627 | 1263 | |
0f829b1d | 1264 | rt2x00usb_register_read(rt2x00dev, MAC_CSR9, ®); |
95ea3627 | 1265 | rt2x00_set_field32(®, MAC_CSR9_CW_SELECT, 0); |
0f829b1d | 1266 | rt2x00usb_register_write(rt2x00dev, MAC_CSR9, reg); |
95ea3627 | 1267 | |
6bb40dd1 ID |
1268 | /* |
1269 | * Clear all beacons | |
1270 | * For the Beacon base registers we only need to clear | |
1271 | * the first byte since that byte contains the VALID and OWNER | |
1272 | * bits which (when set to 0) will invalidate the entire beacon. | |
1273 | */ | |
0f829b1d ID |
1274 | rt2x00usb_register_write(rt2x00dev, HW_BEACON_BASE0, 0); |
1275 | rt2x00usb_register_write(rt2x00dev, HW_BEACON_BASE1, 0); | |
1276 | rt2x00usb_register_write(rt2x00dev, HW_BEACON_BASE2, 0); | |
1277 | rt2x00usb_register_write(rt2x00dev, HW_BEACON_BASE3, 0); | |
6bb40dd1 | 1278 | |
95ea3627 ID |
1279 | /* |
1280 | * We must clear the error counters. | |
1281 | * These registers are cleared on read, | |
1282 | * so we may pass a useless variable to store the value. | |
1283 | */ | |
0f829b1d ID |
1284 | rt2x00usb_register_read(rt2x00dev, STA_CSR0, ®); |
1285 | rt2x00usb_register_read(rt2x00dev, STA_CSR1, ®); | |
1286 | rt2x00usb_register_read(rt2x00dev, STA_CSR2, ®); | |
95ea3627 ID |
1287 | |
1288 | /* | |
1289 | * Reset MAC and BBP registers. | |
1290 | */ | |
0f829b1d | 1291 | rt2x00usb_register_read(rt2x00dev, MAC_CSR1, ®); |
95ea3627 ID |
1292 | rt2x00_set_field32(®, MAC_CSR1_SOFT_RESET, 1); |
1293 | rt2x00_set_field32(®, MAC_CSR1_BBP_RESET, 1); | |
0f829b1d | 1294 | rt2x00usb_register_write(rt2x00dev, MAC_CSR1, reg); |
95ea3627 | 1295 | |
0f829b1d | 1296 | rt2x00usb_register_read(rt2x00dev, MAC_CSR1, ®); |
95ea3627 ID |
1297 | rt2x00_set_field32(®, MAC_CSR1_SOFT_RESET, 0); |
1298 | rt2x00_set_field32(®, MAC_CSR1_BBP_RESET, 0); | |
0f829b1d | 1299 | rt2x00usb_register_write(rt2x00dev, MAC_CSR1, reg); |
95ea3627 | 1300 | |
0f829b1d | 1301 | rt2x00usb_register_read(rt2x00dev, MAC_CSR1, ®); |
95ea3627 | 1302 | rt2x00_set_field32(®, MAC_CSR1_HOST_READY, 1); |
0f829b1d | 1303 | rt2x00usb_register_write(rt2x00dev, MAC_CSR1, reg); |
95ea3627 ID |
1304 | |
1305 | return 0; | |
1306 | } | |
1307 | ||
2b08da3f | 1308 | static int rt73usb_wait_bbp_ready(struct rt2x00_dev *rt2x00dev) |
95ea3627 ID |
1309 | { |
1310 | unsigned int i; | |
95ea3627 ID |
1311 | u8 value; |
1312 | ||
1313 | for (i = 0; i < REGISTER_BUSY_COUNT; i++) { | |
1314 | rt73usb_bbp_read(rt2x00dev, 0, &value); | |
1315 | if ((value != 0xff) && (value != 0x00)) | |
2b08da3f | 1316 | return 0; |
95ea3627 ID |
1317 | udelay(REGISTER_BUSY_DELAY); |
1318 | } | |
1319 | ||
1320 | ERROR(rt2x00dev, "BBP register access failed, aborting.\n"); | |
1321 | return -EACCES; | |
2b08da3f ID |
1322 | } |
1323 | ||
1324 | static int rt73usb_init_bbp(struct rt2x00_dev *rt2x00dev) | |
1325 | { | |
1326 | unsigned int i; | |
1327 | u16 eeprom; | |
1328 | u8 reg_id; | |
1329 | u8 value; | |
1330 | ||
1331 | if (unlikely(rt73usb_wait_bbp_ready(rt2x00dev))) | |
1332 | return -EACCES; | |
95ea3627 | 1333 | |
95ea3627 ID |
1334 | rt73usb_bbp_write(rt2x00dev, 3, 0x80); |
1335 | rt73usb_bbp_write(rt2x00dev, 15, 0x30); | |
1336 | rt73usb_bbp_write(rt2x00dev, 21, 0xc8); | |
1337 | rt73usb_bbp_write(rt2x00dev, 22, 0x38); | |
1338 | rt73usb_bbp_write(rt2x00dev, 23, 0x06); | |
1339 | rt73usb_bbp_write(rt2x00dev, 24, 0xfe); | |
1340 | rt73usb_bbp_write(rt2x00dev, 25, 0x0a); | |
1341 | rt73usb_bbp_write(rt2x00dev, 26, 0x0d); | |
1342 | rt73usb_bbp_write(rt2x00dev, 32, 0x0b); | |
1343 | rt73usb_bbp_write(rt2x00dev, 34, 0x12); | |
1344 | rt73usb_bbp_write(rt2x00dev, 37, 0x07); | |
1345 | rt73usb_bbp_write(rt2x00dev, 39, 0xf8); | |
1346 | rt73usb_bbp_write(rt2x00dev, 41, 0x60); | |
1347 | rt73usb_bbp_write(rt2x00dev, 53, 0x10); | |
1348 | rt73usb_bbp_write(rt2x00dev, 54, 0x18); | |
1349 | rt73usb_bbp_write(rt2x00dev, 60, 0x10); | |
1350 | rt73usb_bbp_write(rt2x00dev, 61, 0x04); | |
1351 | rt73usb_bbp_write(rt2x00dev, 62, 0x04); | |
1352 | rt73usb_bbp_write(rt2x00dev, 75, 0xfe); | |
1353 | rt73usb_bbp_write(rt2x00dev, 86, 0xfe); | |
1354 | rt73usb_bbp_write(rt2x00dev, 88, 0xfe); | |
1355 | rt73usb_bbp_write(rt2x00dev, 90, 0x0f); | |
1356 | rt73usb_bbp_write(rt2x00dev, 99, 0x00); | |
1357 | rt73usb_bbp_write(rt2x00dev, 102, 0x16); | |
1358 | rt73usb_bbp_write(rt2x00dev, 107, 0x04); | |
1359 | ||
95ea3627 ID |
1360 | for (i = 0; i < EEPROM_BBP_SIZE; i++) { |
1361 | rt2x00_eeprom_read(rt2x00dev, EEPROM_BBP_START + i, &eeprom); | |
1362 | ||
1363 | if (eeprom != 0xffff && eeprom != 0x0000) { | |
1364 | reg_id = rt2x00_get_field16(eeprom, EEPROM_BBP_REG_ID); | |
1365 | value = rt2x00_get_field16(eeprom, EEPROM_BBP_VALUE); | |
95ea3627 ID |
1366 | rt73usb_bbp_write(rt2x00dev, reg_id, value); |
1367 | } | |
1368 | } | |
95ea3627 ID |
1369 | |
1370 | return 0; | |
1371 | } | |
1372 | ||
1373 | /* | |
1374 | * Device state switch handlers. | |
1375 | */ | |
95ea3627 ID |
1376 | static int rt73usb_enable_radio(struct rt2x00_dev *rt2x00dev) |
1377 | { | |
1378 | /* | |
1379 | * Initialize all registers. | |
1380 | */ | |
2b08da3f ID |
1381 | if (unlikely(rt73usb_init_registers(rt2x00dev) || |
1382 | rt73usb_init_bbp(rt2x00dev))) | |
95ea3627 | 1383 | return -EIO; |
95ea3627 | 1384 | |
95ea3627 ID |
1385 | return 0; |
1386 | } | |
1387 | ||
1388 | static void rt73usb_disable_radio(struct rt2x00_dev *rt2x00dev) | |
1389 | { | |
0f829b1d | 1390 | rt2x00usb_register_write(rt2x00dev, MAC_CSR10, 0x00001818); |
95ea3627 ID |
1391 | |
1392 | /* | |
1393 | * Disable synchronisation. | |
1394 | */ | |
0f829b1d | 1395 | rt2x00usb_register_write(rt2x00dev, TXRX_CSR9, 0); |
95ea3627 ID |
1396 | |
1397 | rt2x00usb_disable_radio(rt2x00dev); | |
1398 | } | |
1399 | ||
1400 | static int rt73usb_set_state(struct rt2x00_dev *rt2x00dev, enum dev_state state) | |
1401 | { | |
9655a6ec | 1402 | u32 reg, reg2; |
95ea3627 ID |
1403 | unsigned int i; |
1404 | char put_to_sleep; | |
95ea3627 ID |
1405 | |
1406 | put_to_sleep = (state != STATE_AWAKE); | |
1407 | ||
0f829b1d | 1408 | rt2x00usb_register_read(rt2x00dev, MAC_CSR12, ®); |
95ea3627 ID |
1409 | rt2x00_set_field32(®, MAC_CSR12_FORCE_WAKEUP, !put_to_sleep); |
1410 | rt2x00_set_field32(®, MAC_CSR12_PUT_TO_SLEEP, put_to_sleep); | |
0f829b1d | 1411 | rt2x00usb_register_write(rt2x00dev, MAC_CSR12, reg); |
95ea3627 ID |
1412 | |
1413 | /* | |
1414 | * Device is not guaranteed to be in the requested state yet. | |
1415 | * We must wait until the register indicates that the | |
1416 | * device has entered the correct state. | |
1417 | */ | |
1418 | for (i = 0; i < REGISTER_BUSY_COUNT; i++) { | |
9655a6ec GW |
1419 | rt2x00usb_register_read(rt2x00dev, MAC_CSR12, ®2); |
1420 | state = rt2x00_get_field32(reg2, MAC_CSR12_BBP_CURRENT_STATE); | |
2b08da3f | 1421 | if (state == !put_to_sleep) |
95ea3627 | 1422 | return 0; |
9655a6ec | 1423 | rt2x00usb_register_write(rt2x00dev, MAC_CSR12, reg); |
95ea3627 ID |
1424 | msleep(10); |
1425 | } | |
1426 | ||
95ea3627 ID |
1427 | return -EBUSY; |
1428 | } | |
1429 | ||
1430 | static int rt73usb_set_device_state(struct rt2x00_dev *rt2x00dev, | |
1431 | enum dev_state state) | |
1432 | { | |
1433 | int retval = 0; | |
1434 | ||
1435 | switch (state) { | |
1436 | case STATE_RADIO_ON: | |
1437 | retval = rt73usb_enable_radio(rt2x00dev); | |
1438 | break; | |
1439 | case STATE_RADIO_OFF: | |
1440 | rt73usb_disable_radio(rt2x00dev); | |
1441 | break; | |
2b08da3f | 1442 | case STATE_RADIO_IRQ_ON: |
78e256c9 | 1443 | case STATE_RADIO_IRQ_ON_ISR: |
2b08da3f | 1444 | case STATE_RADIO_IRQ_OFF: |
78e256c9 | 1445 | case STATE_RADIO_IRQ_OFF_ISR: |
2b08da3f | 1446 | /* No support, but no error either */ |
95ea3627 ID |
1447 | break; |
1448 | case STATE_DEEP_SLEEP: | |
1449 | case STATE_SLEEP: | |
1450 | case STATE_STANDBY: | |
1451 | case STATE_AWAKE: | |
1452 | retval = rt73usb_set_state(rt2x00dev, state); | |
1453 | break; | |
1454 | default: | |
1455 | retval = -ENOTSUPP; | |
1456 | break; | |
1457 | } | |
1458 | ||
2b08da3f ID |
1459 | if (unlikely(retval)) |
1460 | ERROR(rt2x00dev, "Device failed to enter state %d (%d).\n", | |
1461 | state, retval); | |
1462 | ||
95ea3627 ID |
1463 | return retval; |
1464 | } | |
1465 | ||
1466 | /* | |
1467 | * TX descriptor initialization | |
1468 | */ | |
93331458 | 1469 | static void rt73usb_write_tx_desc(struct queue_entry *entry, |
906c110f | 1470 | struct txentry_desc *txdesc) |
95ea3627 | 1471 | { |
93331458 ID |
1472 | struct skb_frame_desc *skbdesc = get_skb_frame_desc(entry->skb); |
1473 | __le32 *txd = (__le32 *) entry->skb->data; | |
95ea3627 ID |
1474 | u32 word; |
1475 | ||
1476 | /* | |
1477 | * Start writing the descriptor words. | |
1478 | */ | |
e01f1ec3 GW |
1479 | rt2x00_desc_read(txd, 0, &word); |
1480 | rt2x00_set_field32(&word, TXD_W0_BURST, | |
1481 | test_bit(ENTRY_TXD_BURST, &txdesc->flags)); | |
1482 | rt2x00_set_field32(&word, TXD_W0_VALID, 1); | |
1483 | rt2x00_set_field32(&word, TXD_W0_MORE_FRAG, | |
1484 | test_bit(ENTRY_TXD_MORE_FRAG, &txdesc->flags)); | |
1485 | rt2x00_set_field32(&word, TXD_W0_ACK, | |
1486 | test_bit(ENTRY_TXD_ACK, &txdesc->flags)); | |
1487 | rt2x00_set_field32(&word, TXD_W0_TIMESTAMP, | |
1488 | test_bit(ENTRY_TXD_REQ_TIMESTAMP, &txdesc->flags)); | |
1489 | rt2x00_set_field32(&word, TXD_W0_OFDM, | |
1490 | (txdesc->rate_mode == RATE_MODE_OFDM)); | |
1491 | rt2x00_set_field32(&word, TXD_W0_IFS, txdesc->ifs); | |
1492 | rt2x00_set_field32(&word, TXD_W0_RETRY_MODE, | |
1493 | test_bit(ENTRY_TXD_RETRY_MODE, &txdesc->flags)); | |
1494 | rt2x00_set_field32(&word, TXD_W0_TKIP_MIC, | |
1495 | test_bit(ENTRY_TXD_ENCRYPT_MMIC, &txdesc->flags)); | |
1496 | rt2x00_set_field32(&word, TXD_W0_KEY_TABLE, | |
1497 | test_bit(ENTRY_TXD_ENCRYPT_PAIRWISE, &txdesc->flags)); | |
1498 | rt2x00_set_field32(&word, TXD_W0_KEY_INDEX, txdesc->key_idx); | |
1499 | rt2x00_set_field32(&word, TXD_W0_DATABYTE_COUNT, txdesc->length); | |
1500 | rt2x00_set_field32(&word, TXD_W0_BURST2, | |
1501 | test_bit(ENTRY_TXD_BURST, &txdesc->flags)); | |
1502 | rt2x00_set_field32(&word, TXD_W0_CIPHER_ALG, txdesc->cipher); | |
1503 | rt2x00_desc_write(txd, 0, word); | |
1504 | ||
95ea3627 | 1505 | rt2x00_desc_read(txd, 1, &word); |
2b23cdaa HS |
1506 | rt2x00_set_field32(&word, TXD_W1_HOST_Q_ID, entry->queue->qid); |
1507 | rt2x00_set_field32(&word, TXD_W1_AIFSN, entry->queue->aifs); | |
1508 | rt2x00_set_field32(&word, TXD_W1_CWMIN, entry->queue->cw_min); | |
1509 | rt2x00_set_field32(&word, TXD_W1_CWMAX, entry->queue->cw_max); | |
906c110f | 1510 | rt2x00_set_field32(&word, TXD_W1_IV_OFFSET, txdesc->iv_offset); |
5adf6d63 ID |
1511 | rt2x00_set_field32(&word, TXD_W1_HW_SEQUENCE, |
1512 | test_bit(ENTRY_TXD_GENERATE_SEQ, &txdesc->flags)); | |
95ea3627 ID |
1513 | rt2x00_desc_write(txd, 1, word); |
1514 | ||
1515 | rt2x00_desc_read(txd, 2, &word); | |
181d6902 ID |
1516 | rt2x00_set_field32(&word, TXD_W2_PLCP_SIGNAL, txdesc->signal); |
1517 | rt2x00_set_field32(&word, TXD_W2_PLCP_SERVICE, txdesc->service); | |
1518 | rt2x00_set_field32(&word, TXD_W2_PLCP_LENGTH_LOW, txdesc->length_low); | |
1519 | rt2x00_set_field32(&word, TXD_W2_PLCP_LENGTH_HIGH, txdesc->length_high); | |
95ea3627 ID |
1520 | rt2x00_desc_write(txd, 2, word); |
1521 | ||
906c110f | 1522 | if (test_bit(ENTRY_TXD_ENCRYPT, &txdesc->flags)) { |
1ce9cdac ID |
1523 | _rt2x00_desc_write(txd, 3, skbdesc->iv[0]); |
1524 | _rt2x00_desc_write(txd, 4, skbdesc->iv[1]); | |
906c110f ID |
1525 | } |
1526 | ||
95ea3627 ID |
1527 | rt2x00_desc_read(txd, 5, &word); |
1528 | rt2x00_set_field32(&word, TXD_W5_TX_POWER, | |
93331458 | 1529 | TXPOWER_TO_DEV(entry->queue->rt2x00dev->tx_power)); |
95ea3627 ID |
1530 | rt2x00_set_field32(&word, TXD_W5_WAITING_DMA_DONE_INT, 1); |
1531 | rt2x00_desc_write(txd, 5, word); | |
1532 | ||
85b7a8b3 GW |
1533 | /* |
1534 | * Register descriptor details in skb frame descriptor. | |
1535 | */ | |
0b8004aa | 1536 | skbdesc->flags |= SKBDESC_DESC_IN_SKB; |
85b7a8b3 GW |
1537 | skbdesc->desc = txd; |
1538 | skbdesc->desc_len = TXD_DESC_SIZE; | |
95ea3627 ID |
1539 | } |
1540 | ||
bd88a781 ID |
1541 | /* |
1542 | * TX data initialization | |
1543 | */ | |
f224f4ef GW |
1544 | static void rt73usb_write_beacon(struct queue_entry *entry, |
1545 | struct txentry_desc *txdesc) | |
bd88a781 ID |
1546 | { |
1547 | struct rt2x00_dev *rt2x00dev = entry->queue->rt2x00dev; | |
bd88a781 | 1548 | unsigned int beacon_base; |
739fd940 | 1549 | unsigned int padding_len; |
bd88a781 ID |
1550 | u32 reg; |
1551 | ||
bd88a781 ID |
1552 | /* |
1553 | * Disable beaconing while we are reloading the beacon data, | |
1554 | * otherwise we might be sending out invalid data. | |
1555 | */ | |
0f829b1d | 1556 | rt2x00usb_register_read(rt2x00dev, TXRX_CSR9, ®); |
bd88a781 | 1557 | rt2x00_set_field32(®, TXRX_CSR9_BEACON_GEN, 0); |
0f829b1d | 1558 | rt2x00usb_register_write(rt2x00dev, TXRX_CSR9, reg); |
bd88a781 | 1559 | |
0b8004aa GW |
1560 | /* |
1561 | * Add space for the descriptor in front of the skb. | |
1562 | */ | |
1563 | skb_push(entry->skb, TXD_DESC_SIZE); | |
1564 | memset(entry->skb->data, 0, TXD_DESC_SIZE); | |
1565 | ||
5c3b685c GW |
1566 | /* |
1567 | * Write the TX descriptor for the beacon. | |
1568 | */ | |
93331458 | 1569 | rt73usb_write_tx_desc(entry, txdesc); |
5c3b685c GW |
1570 | |
1571 | /* | |
1572 | * Dump beacon to userspace through debugfs. | |
1573 | */ | |
1574 | rt2x00debug_dump_frame(rt2x00dev, DUMP_FRAME_BEACON, entry->skb); | |
1575 | ||
bd88a781 | 1576 | /* |
739fd940 | 1577 | * Write entire beacon with descriptor and padding to register. |
bd88a781 | 1578 | */ |
739fd940 WK |
1579 | padding_len = roundup(entry->skb->len, 4) - entry->skb->len; |
1580 | skb_pad(entry->skb, padding_len); | |
bd88a781 | 1581 | beacon_base = HW_BEACON_OFFSET(entry->entry_idx); |
739fd940 WK |
1582 | rt2x00usb_register_multiwrite(rt2x00dev, beacon_base, entry->skb->data, |
1583 | entry->skb->len + padding_len); | |
bd88a781 | 1584 | |
d61cb266 GW |
1585 | /* |
1586 | * Enable beaconing again. | |
1587 | * | |
1588 | * For Wi-Fi faily generated beacons between participating stations. | |
1589 | * Set TBTT phase adaptive adjustment step to 8us (default 16us) | |
1590 | */ | |
1591 | rt2x00usb_register_write(rt2x00dev, TXRX_CSR10, 0x00001008); | |
1592 | ||
1593 | rt2x00_set_field32(®, TXRX_CSR9_TSF_TICKING, 1); | |
1594 | rt2x00_set_field32(®, TXRX_CSR9_TBTT_ENABLE, 1); | |
1595 | rt2x00_set_field32(®, TXRX_CSR9_BEACON_GEN, 1); | |
1596 | rt2x00usb_register_write(rt2x00dev, TXRX_CSR9, reg); | |
1597 | ||
bd88a781 ID |
1598 | /* |
1599 | * Clean up the beacon skb. | |
1600 | */ | |
1601 | dev_kfree_skb(entry->skb); | |
1602 | entry->skb = NULL; | |
1603 | } | |
1604 | ||
f1ca2167 | 1605 | static int rt73usb_get_tx_data_len(struct queue_entry *entry) |
dd9fa2d2 ID |
1606 | { |
1607 | int length; | |
1608 | ||
1609 | /* | |
1610 | * The length _must_ be a multiple of 4, | |
1611 | * but it must _not_ be a multiple of the USB packet size. | |
1612 | */ | |
f1ca2167 ID |
1613 | length = roundup(entry->skb->len, 4); |
1614 | length += (4 * !(length % entry->queue->usb_maxpacket)); | |
dd9fa2d2 ID |
1615 | |
1616 | return length; | |
1617 | } | |
1618 | ||
95ea3627 ID |
1619 | /* |
1620 | * RX control handlers | |
1621 | */ | |
1622 | static int rt73usb_agc_to_rssi(struct rt2x00_dev *rt2x00dev, int rxd_w1) | |
1623 | { | |
ba2ab471 | 1624 | u8 offset = rt2x00dev->lna_gain; |
95ea3627 ID |
1625 | u8 lna; |
1626 | ||
1627 | lna = rt2x00_get_field32(rxd_w1, RXD_W1_RSSI_LNA); | |
1628 | switch (lna) { | |
1629 | case 3: | |
ba2ab471 | 1630 | offset += 90; |
95ea3627 ID |
1631 | break; |
1632 | case 2: | |
ba2ab471 | 1633 | offset += 74; |
95ea3627 ID |
1634 | break; |
1635 | case 1: | |
ba2ab471 | 1636 | offset += 64; |
95ea3627 ID |
1637 | break; |
1638 | default: | |
1639 | return 0; | |
1640 | } | |
1641 | ||
e5ef5bad | 1642 | if (rt2x00dev->curr_band == IEEE80211_BAND_5GHZ) { |
95ea3627 ID |
1643 | if (test_bit(CONFIG_EXTERNAL_LNA_A, &rt2x00dev->flags)) { |
1644 | if (lna == 3 || lna == 2) | |
1645 | offset += 10; | |
1646 | } else { | |
1647 | if (lna == 3) | |
1648 | offset += 6; | |
1649 | else if (lna == 2) | |
1650 | offset += 8; | |
1651 | } | |
95ea3627 ID |
1652 | } |
1653 | ||
1654 | return rt2x00_get_field32(rxd_w1, RXD_W1_RSSI_AGC) * 2 - offset; | |
1655 | } | |
1656 | ||
181d6902 | 1657 | static void rt73usb_fill_rxdone(struct queue_entry *entry, |
55887511 | 1658 | struct rxdone_entry_desc *rxdesc) |
95ea3627 | 1659 | { |
906c110f | 1660 | struct rt2x00_dev *rt2x00dev = entry->queue->rt2x00dev; |
181d6902 | 1661 | struct skb_frame_desc *skbdesc = get_skb_frame_desc(entry->skb); |
4bd7c452 | 1662 | __le32 *rxd = (__le32 *)entry->skb->data; |
95ea3627 ID |
1663 | u32 word0; |
1664 | u32 word1; | |
1665 | ||
f855c10b | 1666 | /* |
a26cbc65 GW |
1667 | * Copy descriptor to the skbdesc->desc buffer, making it safe from moving of |
1668 | * frame data in rt2x00usb. | |
f855c10b | 1669 | */ |
a26cbc65 | 1670 | memcpy(skbdesc->desc, rxd, skbdesc->desc_len); |
70a96109 | 1671 | rxd = (__le32 *)skbdesc->desc; |
f855c10b ID |
1672 | |
1673 | /* | |
70a96109 | 1674 | * It is now safe to read the descriptor on all architectures. |
f855c10b | 1675 | */ |
95ea3627 ID |
1676 | rt2x00_desc_read(rxd, 0, &word0); |
1677 | rt2x00_desc_read(rxd, 1, &word1); | |
1678 | ||
4150c572 | 1679 | if (rt2x00_get_field32(word0, RXD_W0_CRC_ERROR)) |
181d6902 | 1680 | rxdesc->flags |= RX_FLAG_FAILED_FCS_CRC; |
95ea3627 | 1681 | |
78b8f3b0 GW |
1682 | rxdesc->cipher = rt2x00_get_field32(word0, RXD_W0_CIPHER_ALG); |
1683 | rxdesc->cipher_status = rt2x00_get_field32(word0, RXD_W0_CIPHER_ERROR); | |
906c110f ID |
1684 | |
1685 | if (rxdesc->cipher != CIPHER_NONE) { | |
1ce9cdac ID |
1686 | _rt2x00_desc_read(rxd, 2, &rxdesc->iv[0]); |
1687 | _rt2x00_desc_read(rxd, 3, &rxdesc->iv[1]); | |
74415edb ID |
1688 | rxdesc->dev_flags |= RXDONE_CRYPTO_IV; |
1689 | ||
906c110f | 1690 | _rt2x00_desc_read(rxd, 4, &rxdesc->icv); |
74415edb | 1691 | rxdesc->dev_flags |= RXDONE_CRYPTO_ICV; |
906c110f ID |
1692 | |
1693 | /* | |
1694 | * Hardware has stripped IV/EIV data from 802.11 frame during | |
3ad2f3fb | 1695 | * decryption. It has provided the data separately but rt2x00lib |
906c110f ID |
1696 | * should decide if it should be reinserted. |
1697 | */ | |
1698 | rxdesc->flags |= RX_FLAG_IV_STRIPPED; | |
1699 | ||
1700 | /* | |
1701 | * FIXME: Legacy driver indicates that the frame does | |
1702 | * contain the Michael Mic. Unfortunately, in rt2x00 | |
1703 | * the MIC seems to be missing completely... | |
1704 | */ | |
1705 | rxdesc->flags |= RX_FLAG_MMIC_STRIPPED; | |
1706 | ||
1707 | if (rxdesc->cipher_status == RX_CRYPTO_SUCCESS) | |
1708 | rxdesc->flags |= RX_FLAG_DECRYPTED; | |
1709 | else if (rxdesc->cipher_status == RX_CRYPTO_FAIL_MIC) | |
1710 | rxdesc->flags |= RX_FLAG_MMIC_ERROR; | |
1711 | } | |
1712 | ||
95ea3627 ID |
1713 | /* |
1714 | * Obtain the status about this packet. | |
89993890 ID |
1715 | * When frame was received with an OFDM bitrate, |
1716 | * the signal is the PLCP value. If it was received with | |
1717 | * a CCK bitrate the signal is the rate in 100kbit/s. | |
95ea3627 | 1718 | */ |
181d6902 | 1719 | rxdesc->signal = rt2x00_get_field32(word1, RXD_W1_SIGNAL); |
906c110f | 1720 | rxdesc->rssi = rt73usb_agc_to_rssi(rt2x00dev, word1); |
181d6902 | 1721 | rxdesc->size = rt2x00_get_field32(word0, RXD_W0_DATABYTE_COUNT); |
19d30e02 | 1722 | |
19d30e02 ID |
1723 | if (rt2x00_get_field32(word0, RXD_W0_OFDM)) |
1724 | rxdesc->dev_flags |= RXDONE_SIGNAL_PLCP; | |
6c6aa3c0 ID |
1725 | else |
1726 | rxdesc->dev_flags |= RXDONE_SIGNAL_BITRATE; | |
19d30e02 ID |
1727 | if (rt2x00_get_field32(word0, RXD_W0_MY_BSS)) |
1728 | rxdesc->dev_flags |= RXDONE_MY_BSS; | |
181d6902 | 1729 | |
2ae23854 | 1730 | /* |
70a96109 | 1731 | * Set skb pointers, and update frame information. |
2ae23854 | 1732 | */ |
70a96109 | 1733 | skb_pull(entry->skb, entry->queue->desc_size); |
2ae23854 | 1734 | skb_trim(entry->skb, rxdesc->size); |
95ea3627 ID |
1735 | } |
1736 | ||
1737 | /* | |
1738 | * Device probe functions. | |
1739 | */ | |
1740 | static int rt73usb_validate_eeprom(struct rt2x00_dev *rt2x00dev) | |
1741 | { | |
1742 | u16 word; | |
1743 | u8 *mac; | |
1744 | s8 value; | |
1745 | ||
1746 | rt2x00usb_eeprom_read(rt2x00dev, rt2x00dev->eeprom, EEPROM_SIZE); | |
1747 | ||
1748 | /* | |
1749 | * Start validation of the data that has been read. | |
1750 | */ | |
1751 | mac = rt2x00_eeprom_addr(rt2x00dev, EEPROM_MAC_ADDR_0); | |
1752 | if (!is_valid_ether_addr(mac)) { | |
1753 | random_ether_addr(mac); | |
e174961c | 1754 | EEPROM(rt2x00dev, "MAC: %pM\n", mac); |
95ea3627 ID |
1755 | } |
1756 | ||
1757 | rt2x00_eeprom_read(rt2x00dev, EEPROM_ANTENNA, &word); | |
1758 | if (word == 0xffff) { | |
1759 | rt2x00_set_field16(&word, EEPROM_ANTENNA_NUM, 2); | |
362f3b6b ID |
1760 | rt2x00_set_field16(&word, EEPROM_ANTENNA_TX_DEFAULT, |
1761 | ANTENNA_B); | |
1762 | rt2x00_set_field16(&word, EEPROM_ANTENNA_RX_DEFAULT, | |
1763 | ANTENNA_B); | |
95ea3627 ID |
1764 | rt2x00_set_field16(&word, EEPROM_ANTENNA_FRAME_TYPE, 0); |
1765 | rt2x00_set_field16(&word, EEPROM_ANTENNA_DYN_TXAGC, 0); | |
1766 | rt2x00_set_field16(&word, EEPROM_ANTENNA_HARDWARE_RADIO, 0); | |
1767 | rt2x00_set_field16(&word, EEPROM_ANTENNA_RF_TYPE, RF5226); | |
1768 | rt2x00_eeprom_write(rt2x00dev, EEPROM_ANTENNA, word); | |
1769 | EEPROM(rt2x00dev, "Antenna: 0x%04x\n", word); | |
1770 | } | |
1771 | ||
1772 | rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC, &word); | |
1773 | if (word == 0xffff) { | |
1774 | rt2x00_set_field16(&word, EEPROM_NIC_EXTERNAL_LNA, 0); | |
1775 | rt2x00_eeprom_write(rt2x00dev, EEPROM_NIC, word); | |
1776 | EEPROM(rt2x00dev, "NIC: 0x%04x\n", word); | |
1777 | } | |
1778 | ||
1779 | rt2x00_eeprom_read(rt2x00dev, EEPROM_LED, &word); | |
1780 | if (word == 0xffff) { | |
1781 | rt2x00_set_field16(&word, EEPROM_LED_POLARITY_RDY_G, 0); | |
1782 | rt2x00_set_field16(&word, EEPROM_LED_POLARITY_RDY_A, 0); | |
1783 | rt2x00_set_field16(&word, EEPROM_LED_POLARITY_ACT, 0); | |
1784 | rt2x00_set_field16(&word, EEPROM_LED_POLARITY_GPIO_0, 0); | |
1785 | rt2x00_set_field16(&word, EEPROM_LED_POLARITY_GPIO_1, 0); | |
1786 | rt2x00_set_field16(&word, EEPROM_LED_POLARITY_GPIO_2, 0); | |
1787 | rt2x00_set_field16(&word, EEPROM_LED_POLARITY_GPIO_3, 0); | |
1788 | rt2x00_set_field16(&word, EEPROM_LED_POLARITY_GPIO_4, 0); | |
1789 | rt2x00_set_field16(&word, EEPROM_LED_LED_MODE, | |
1790 | LED_MODE_DEFAULT); | |
1791 | rt2x00_eeprom_write(rt2x00dev, EEPROM_LED, word); | |
1792 | EEPROM(rt2x00dev, "Led: 0x%04x\n", word); | |
1793 | } | |
1794 | ||
1795 | rt2x00_eeprom_read(rt2x00dev, EEPROM_FREQ, &word); | |
1796 | if (word == 0xffff) { | |
1797 | rt2x00_set_field16(&word, EEPROM_FREQ_OFFSET, 0); | |
1798 | rt2x00_set_field16(&word, EEPROM_FREQ_SEQ, 0); | |
1799 | rt2x00_eeprom_write(rt2x00dev, EEPROM_FREQ, word); | |
1800 | EEPROM(rt2x00dev, "Freq: 0x%04x\n", word); | |
1801 | } | |
1802 | ||
1803 | rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_OFFSET_BG, &word); | |
1804 | if (word == 0xffff) { | |
1805 | rt2x00_set_field16(&word, EEPROM_RSSI_OFFSET_BG_1, 0); | |
1806 | rt2x00_set_field16(&word, EEPROM_RSSI_OFFSET_BG_2, 0); | |
1807 | rt2x00_eeprom_write(rt2x00dev, EEPROM_RSSI_OFFSET_BG, word); | |
1808 | EEPROM(rt2x00dev, "RSSI OFFSET BG: 0x%04x\n", word); | |
1809 | } else { | |
1810 | value = rt2x00_get_field16(word, EEPROM_RSSI_OFFSET_BG_1); | |
1811 | if (value < -10 || value > 10) | |
1812 | rt2x00_set_field16(&word, EEPROM_RSSI_OFFSET_BG_1, 0); | |
1813 | value = rt2x00_get_field16(word, EEPROM_RSSI_OFFSET_BG_2); | |
1814 | if (value < -10 || value > 10) | |
1815 | rt2x00_set_field16(&word, EEPROM_RSSI_OFFSET_BG_2, 0); | |
1816 | rt2x00_eeprom_write(rt2x00dev, EEPROM_RSSI_OFFSET_BG, word); | |
1817 | } | |
1818 | ||
1819 | rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_OFFSET_A, &word); | |
1820 | if (word == 0xffff) { | |
1821 | rt2x00_set_field16(&word, EEPROM_RSSI_OFFSET_A_1, 0); | |
1822 | rt2x00_set_field16(&word, EEPROM_RSSI_OFFSET_A_2, 0); | |
1823 | rt2x00_eeprom_write(rt2x00dev, EEPROM_RSSI_OFFSET_A, word); | |
417f412f | 1824 | EEPROM(rt2x00dev, "RSSI OFFSET A: 0x%04x\n", word); |
95ea3627 ID |
1825 | } else { |
1826 | value = rt2x00_get_field16(word, EEPROM_RSSI_OFFSET_A_1); | |
1827 | if (value < -10 || value > 10) | |
1828 | rt2x00_set_field16(&word, EEPROM_RSSI_OFFSET_A_1, 0); | |
1829 | value = rt2x00_get_field16(word, EEPROM_RSSI_OFFSET_A_2); | |
1830 | if (value < -10 || value > 10) | |
1831 | rt2x00_set_field16(&word, EEPROM_RSSI_OFFSET_A_2, 0); | |
1832 | rt2x00_eeprom_write(rt2x00dev, EEPROM_RSSI_OFFSET_A, word); | |
1833 | } | |
1834 | ||
1835 | return 0; | |
1836 | } | |
1837 | ||
1838 | static int rt73usb_init_eeprom(struct rt2x00_dev *rt2x00dev) | |
1839 | { | |
1840 | u32 reg; | |
1841 | u16 value; | |
1842 | u16 eeprom; | |
1843 | ||
1844 | /* | |
1845 | * Read EEPROM word for configuration. | |
1846 | */ | |
1847 | rt2x00_eeprom_read(rt2x00dev, EEPROM_ANTENNA, &eeprom); | |
1848 | ||
1849 | /* | |
1850 | * Identify RF chipset. | |
1851 | */ | |
1852 | value = rt2x00_get_field16(eeprom, EEPROM_ANTENNA_RF_TYPE); | |
0f829b1d | 1853 | rt2x00usb_register_read(rt2x00dev, MAC_CSR0, ®); |
49e721ec GW |
1854 | rt2x00_set_chip(rt2x00dev, rt2x00_get_field32(reg, MAC_CSR0_CHIPSET), |
1855 | value, rt2x00_get_field32(reg, MAC_CSR0_REVISION)); | |
95ea3627 | 1856 | |
49e721ec | 1857 | if (!rt2x00_rt(rt2x00dev, RT2573) || (rt2x00_rev(rt2x00dev) == 0)) { |
95ea3627 ID |
1858 | ERROR(rt2x00dev, "Invalid RT chipset detected.\n"); |
1859 | return -ENODEV; | |
1860 | } | |
1861 | ||
5122d898 GW |
1862 | if (!rt2x00_rf(rt2x00dev, RF5226) && |
1863 | !rt2x00_rf(rt2x00dev, RF2528) && | |
1864 | !rt2x00_rf(rt2x00dev, RF5225) && | |
1865 | !rt2x00_rf(rt2x00dev, RF2527)) { | |
95ea3627 ID |
1866 | ERROR(rt2x00dev, "Invalid RF chipset detected.\n"); |
1867 | return -ENODEV; | |
1868 | } | |
1869 | ||
1870 | /* | |
1871 | * Identify default antenna configuration. | |
1872 | */ | |
addc81bd | 1873 | rt2x00dev->default_ant.tx = |
95ea3627 | 1874 | rt2x00_get_field16(eeprom, EEPROM_ANTENNA_TX_DEFAULT); |
addc81bd | 1875 | rt2x00dev->default_ant.rx = |
95ea3627 ID |
1876 | rt2x00_get_field16(eeprom, EEPROM_ANTENNA_RX_DEFAULT); |
1877 | ||
1878 | /* | |
1879 | * Read the Frame type. | |
1880 | */ | |
1881 | if (rt2x00_get_field16(eeprom, EEPROM_ANTENNA_FRAME_TYPE)) | |
1882 | __set_bit(CONFIG_FRAME_TYPE, &rt2x00dev->flags); | |
1883 | ||
7396faf4 ID |
1884 | /* |
1885 | * Detect if this device has an hardware controlled radio. | |
1886 | */ | |
7396faf4 ID |
1887 | if (rt2x00_get_field16(eeprom, EEPROM_ANTENNA_HARDWARE_RADIO)) |
1888 | __set_bit(CONFIG_SUPPORT_HW_BUTTON, &rt2x00dev->flags); | |
7396faf4 | 1889 | |
95ea3627 ID |
1890 | /* |
1891 | * Read frequency offset. | |
1892 | */ | |
1893 | rt2x00_eeprom_read(rt2x00dev, EEPROM_FREQ, &eeprom); | |
1894 | rt2x00dev->freq_offset = rt2x00_get_field16(eeprom, EEPROM_FREQ_OFFSET); | |
1895 | ||
1896 | /* | |
1897 | * Read external LNA informations. | |
1898 | */ | |
1899 | rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC, &eeprom); | |
1900 | ||
1901 | if (rt2x00_get_field16(eeprom, EEPROM_NIC_EXTERNAL_LNA)) { | |
1902 | __set_bit(CONFIG_EXTERNAL_LNA_A, &rt2x00dev->flags); | |
1903 | __set_bit(CONFIG_EXTERNAL_LNA_BG, &rt2x00dev->flags); | |
1904 | } | |
1905 | ||
1906 | /* | |
1907 | * Store led settings, for correct led behaviour. | |
1908 | */ | |
771fd565 | 1909 | #ifdef CONFIG_RT2X00_LIB_LEDS |
95ea3627 ID |
1910 | rt2x00_eeprom_read(rt2x00dev, EEPROM_LED, &eeprom); |
1911 | ||
475433be ID |
1912 | rt73usb_init_led(rt2x00dev, &rt2x00dev->led_radio, LED_TYPE_RADIO); |
1913 | rt73usb_init_led(rt2x00dev, &rt2x00dev->led_assoc, LED_TYPE_ASSOC); | |
1914 | if (value == LED_MODE_SIGNAL_STRENGTH) | |
1915 | rt73usb_init_led(rt2x00dev, &rt2x00dev->led_qual, | |
1916 | LED_TYPE_QUALITY); | |
a9450b70 ID |
1917 | |
1918 | rt2x00_set_field16(&rt2x00dev->led_mcu_reg, MCU_LEDCS_LED_MODE, value); | |
1919 | rt2x00_set_field16(&rt2x00dev->led_mcu_reg, MCU_LEDCS_POLARITY_GPIO_0, | |
95ea3627 ID |
1920 | rt2x00_get_field16(eeprom, |
1921 | EEPROM_LED_POLARITY_GPIO_0)); | |
a9450b70 | 1922 | rt2x00_set_field16(&rt2x00dev->led_mcu_reg, MCU_LEDCS_POLARITY_GPIO_1, |
95ea3627 ID |
1923 | rt2x00_get_field16(eeprom, |
1924 | EEPROM_LED_POLARITY_GPIO_1)); | |
a9450b70 | 1925 | rt2x00_set_field16(&rt2x00dev->led_mcu_reg, MCU_LEDCS_POLARITY_GPIO_2, |
95ea3627 ID |
1926 | rt2x00_get_field16(eeprom, |
1927 | EEPROM_LED_POLARITY_GPIO_2)); | |
a9450b70 | 1928 | rt2x00_set_field16(&rt2x00dev->led_mcu_reg, MCU_LEDCS_POLARITY_GPIO_3, |
95ea3627 ID |
1929 | rt2x00_get_field16(eeprom, |
1930 | EEPROM_LED_POLARITY_GPIO_3)); | |
a9450b70 | 1931 | rt2x00_set_field16(&rt2x00dev->led_mcu_reg, MCU_LEDCS_POLARITY_GPIO_4, |
95ea3627 ID |
1932 | rt2x00_get_field16(eeprom, |
1933 | EEPROM_LED_POLARITY_GPIO_4)); | |
a9450b70 | 1934 | rt2x00_set_field16(&rt2x00dev->led_mcu_reg, MCU_LEDCS_POLARITY_ACT, |
95ea3627 | 1935 | rt2x00_get_field16(eeprom, EEPROM_LED_POLARITY_ACT)); |
a9450b70 | 1936 | rt2x00_set_field16(&rt2x00dev->led_mcu_reg, MCU_LEDCS_POLARITY_READY_BG, |
95ea3627 ID |
1937 | rt2x00_get_field16(eeprom, |
1938 | EEPROM_LED_POLARITY_RDY_G)); | |
a9450b70 | 1939 | rt2x00_set_field16(&rt2x00dev->led_mcu_reg, MCU_LEDCS_POLARITY_READY_A, |
95ea3627 ID |
1940 | rt2x00_get_field16(eeprom, |
1941 | EEPROM_LED_POLARITY_RDY_A)); | |
771fd565 | 1942 | #endif /* CONFIG_RT2X00_LIB_LEDS */ |
95ea3627 ID |
1943 | |
1944 | return 0; | |
1945 | } | |
1946 | ||
1947 | /* | |
1948 | * RF value list for RF2528 | |
1949 | * Supports: 2.4 GHz | |
1950 | */ | |
1951 | static const struct rf_channel rf_vals_bg_2528[] = { | |
1952 | { 1, 0x00002c0c, 0x00000786, 0x00068255, 0x000fea0b }, | |
1953 | { 2, 0x00002c0c, 0x00000786, 0x00068255, 0x000fea1f }, | |
1954 | { 3, 0x00002c0c, 0x0000078a, 0x00068255, 0x000fea0b }, | |
1955 | { 4, 0x00002c0c, 0x0000078a, 0x00068255, 0x000fea1f }, | |
1956 | { 5, 0x00002c0c, 0x0000078e, 0x00068255, 0x000fea0b }, | |
1957 | { 6, 0x00002c0c, 0x0000078e, 0x00068255, 0x000fea1f }, | |
1958 | { 7, 0x00002c0c, 0x00000792, 0x00068255, 0x000fea0b }, | |
1959 | { 8, 0x00002c0c, 0x00000792, 0x00068255, 0x000fea1f }, | |
1960 | { 9, 0x00002c0c, 0x00000796, 0x00068255, 0x000fea0b }, | |
1961 | { 10, 0x00002c0c, 0x00000796, 0x00068255, 0x000fea1f }, | |
1962 | { 11, 0x00002c0c, 0x0000079a, 0x00068255, 0x000fea0b }, | |
1963 | { 12, 0x00002c0c, 0x0000079a, 0x00068255, 0x000fea1f }, | |
1964 | { 13, 0x00002c0c, 0x0000079e, 0x00068255, 0x000fea0b }, | |
1965 | { 14, 0x00002c0c, 0x000007a2, 0x00068255, 0x000fea13 }, | |
1966 | }; | |
1967 | ||
1968 | /* | |
1969 | * RF value list for RF5226 | |
1970 | * Supports: 2.4 GHz & 5.2 GHz | |
1971 | */ | |
1972 | static const struct rf_channel rf_vals_5226[] = { | |
1973 | { 1, 0x00002c0c, 0x00000786, 0x00068255, 0x000fea0b }, | |
1974 | { 2, 0x00002c0c, 0x00000786, 0x00068255, 0x000fea1f }, | |
1975 | { 3, 0x00002c0c, 0x0000078a, 0x00068255, 0x000fea0b }, | |
1976 | { 4, 0x00002c0c, 0x0000078a, 0x00068255, 0x000fea1f }, | |
1977 | { 5, 0x00002c0c, 0x0000078e, 0x00068255, 0x000fea0b }, | |
1978 | { 6, 0x00002c0c, 0x0000078e, 0x00068255, 0x000fea1f }, | |
1979 | { 7, 0x00002c0c, 0x00000792, 0x00068255, 0x000fea0b }, | |
1980 | { 8, 0x00002c0c, 0x00000792, 0x00068255, 0x000fea1f }, | |
1981 | { 9, 0x00002c0c, 0x00000796, 0x00068255, 0x000fea0b }, | |
1982 | { 10, 0x00002c0c, 0x00000796, 0x00068255, 0x000fea1f }, | |
1983 | { 11, 0x00002c0c, 0x0000079a, 0x00068255, 0x000fea0b }, | |
1984 | { 12, 0x00002c0c, 0x0000079a, 0x00068255, 0x000fea1f }, | |
1985 | { 13, 0x00002c0c, 0x0000079e, 0x00068255, 0x000fea0b }, | |
1986 | { 14, 0x00002c0c, 0x000007a2, 0x00068255, 0x000fea13 }, | |
1987 | ||
1988 | /* 802.11 UNI / HyperLan 2 */ | |
1989 | { 36, 0x00002c0c, 0x0000099a, 0x00098255, 0x000fea23 }, | |
1990 | { 40, 0x00002c0c, 0x000009a2, 0x00098255, 0x000fea03 }, | |
1991 | { 44, 0x00002c0c, 0x000009a6, 0x00098255, 0x000fea0b }, | |
1992 | { 48, 0x00002c0c, 0x000009aa, 0x00098255, 0x000fea13 }, | |
1993 | { 52, 0x00002c0c, 0x000009ae, 0x00098255, 0x000fea1b }, | |
1994 | { 56, 0x00002c0c, 0x000009b2, 0x00098255, 0x000fea23 }, | |
1995 | { 60, 0x00002c0c, 0x000009ba, 0x00098255, 0x000fea03 }, | |
1996 | { 64, 0x00002c0c, 0x000009be, 0x00098255, 0x000fea0b }, | |
1997 | ||
1998 | /* 802.11 HyperLan 2 */ | |
1999 | { 100, 0x00002c0c, 0x00000a2a, 0x000b8255, 0x000fea03 }, | |
2000 | { 104, 0x00002c0c, 0x00000a2e, 0x000b8255, 0x000fea0b }, | |
2001 | { 108, 0x00002c0c, 0x00000a32, 0x000b8255, 0x000fea13 }, | |
2002 | { 112, 0x00002c0c, 0x00000a36, 0x000b8255, 0x000fea1b }, | |
2003 | { 116, 0x00002c0c, 0x00000a3a, 0x000b8255, 0x000fea23 }, | |
2004 | { 120, 0x00002c0c, 0x00000a82, 0x000b8255, 0x000fea03 }, | |
2005 | { 124, 0x00002c0c, 0x00000a86, 0x000b8255, 0x000fea0b }, | |
2006 | { 128, 0x00002c0c, 0x00000a8a, 0x000b8255, 0x000fea13 }, | |
2007 | { 132, 0x00002c0c, 0x00000a8e, 0x000b8255, 0x000fea1b }, | |
2008 | { 136, 0x00002c0c, 0x00000a92, 0x000b8255, 0x000fea23 }, | |
2009 | ||
2010 | /* 802.11 UNII */ | |
2011 | { 140, 0x00002c0c, 0x00000a9a, 0x000b8255, 0x000fea03 }, | |
2012 | { 149, 0x00002c0c, 0x00000aa2, 0x000b8255, 0x000fea1f }, | |
2013 | { 153, 0x00002c0c, 0x00000aa6, 0x000b8255, 0x000fea27 }, | |
2014 | { 157, 0x00002c0c, 0x00000aae, 0x000b8255, 0x000fea07 }, | |
2015 | { 161, 0x00002c0c, 0x00000ab2, 0x000b8255, 0x000fea0f }, | |
2016 | { 165, 0x00002c0c, 0x00000ab6, 0x000b8255, 0x000fea17 }, | |
2017 | ||
2018 | /* MMAC(Japan)J52 ch 34,38,42,46 */ | |
2019 | { 34, 0x00002c0c, 0x0008099a, 0x000da255, 0x000d3a0b }, | |
2020 | { 38, 0x00002c0c, 0x0008099e, 0x000da255, 0x000d3a13 }, | |
2021 | { 42, 0x00002c0c, 0x000809a2, 0x000da255, 0x000d3a1b }, | |
2022 | { 46, 0x00002c0c, 0x000809a6, 0x000da255, 0x000d3a23 }, | |
2023 | }; | |
2024 | ||
2025 | /* | |
2026 | * RF value list for RF5225 & RF2527 | |
2027 | * Supports: 2.4 GHz & 5.2 GHz | |
2028 | */ | |
2029 | static const struct rf_channel rf_vals_5225_2527[] = { | |
2030 | { 1, 0x00002ccc, 0x00004786, 0x00068455, 0x000ffa0b }, | |
2031 | { 2, 0x00002ccc, 0x00004786, 0x00068455, 0x000ffa1f }, | |
2032 | { 3, 0x00002ccc, 0x0000478a, 0x00068455, 0x000ffa0b }, | |
2033 | { 4, 0x00002ccc, 0x0000478a, 0x00068455, 0x000ffa1f }, | |
2034 | { 5, 0x00002ccc, 0x0000478e, 0x00068455, 0x000ffa0b }, | |
2035 | { 6, 0x00002ccc, 0x0000478e, 0x00068455, 0x000ffa1f }, | |
2036 | { 7, 0x00002ccc, 0x00004792, 0x00068455, 0x000ffa0b }, | |
2037 | { 8, 0x00002ccc, 0x00004792, 0x00068455, 0x000ffa1f }, | |
2038 | { 9, 0x00002ccc, 0x00004796, 0x00068455, 0x000ffa0b }, | |
2039 | { 10, 0x00002ccc, 0x00004796, 0x00068455, 0x000ffa1f }, | |
2040 | { 11, 0x00002ccc, 0x0000479a, 0x00068455, 0x000ffa0b }, | |
2041 | { 12, 0x00002ccc, 0x0000479a, 0x00068455, 0x000ffa1f }, | |
2042 | { 13, 0x00002ccc, 0x0000479e, 0x00068455, 0x000ffa0b }, | |
2043 | { 14, 0x00002ccc, 0x000047a2, 0x00068455, 0x000ffa13 }, | |
2044 | ||
2045 | /* 802.11 UNI / HyperLan 2 */ | |
2046 | { 36, 0x00002ccc, 0x0000499a, 0x0009be55, 0x000ffa23 }, | |
2047 | { 40, 0x00002ccc, 0x000049a2, 0x0009be55, 0x000ffa03 }, | |
2048 | { 44, 0x00002ccc, 0x000049a6, 0x0009be55, 0x000ffa0b }, | |
2049 | { 48, 0x00002ccc, 0x000049aa, 0x0009be55, 0x000ffa13 }, | |
2050 | { 52, 0x00002ccc, 0x000049ae, 0x0009ae55, 0x000ffa1b }, | |
2051 | { 56, 0x00002ccc, 0x000049b2, 0x0009ae55, 0x000ffa23 }, | |
2052 | { 60, 0x00002ccc, 0x000049ba, 0x0009ae55, 0x000ffa03 }, | |
2053 | { 64, 0x00002ccc, 0x000049be, 0x0009ae55, 0x000ffa0b }, | |
2054 | ||
2055 | /* 802.11 HyperLan 2 */ | |
2056 | { 100, 0x00002ccc, 0x00004a2a, 0x000bae55, 0x000ffa03 }, | |
2057 | { 104, 0x00002ccc, 0x00004a2e, 0x000bae55, 0x000ffa0b }, | |
2058 | { 108, 0x00002ccc, 0x00004a32, 0x000bae55, 0x000ffa13 }, | |
2059 | { 112, 0x00002ccc, 0x00004a36, 0x000bae55, 0x000ffa1b }, | |
2060 | { 116, 0x00002ccc, 0x00004a3a, 0x000bbe55, 0x000ffa23 }, | |
2061 | { 120, 0x00002ccc, 0x00004a82, 0x000bbe55, 0x000ffa03 }, | |
2062 | { 124, 0x00002ccc, 0x00004a86, 0x000bbe55, 0x000ffa0b }, | |
2063 | { 128, 0x00002ccc, 0x00004a8a, 0x000bbe55, 0x000ffa13 }, | |
2064 | { 132, 0x00002ccc, 0x00004a8e, 0x000bbe55, 0x000ffa1b }, | |
2065 | { 136, 0x00002ccc, 0x00004a92, 0x000bbe55, 0x000ffa23 }, | |
2066 | ||
2067 | /* 802.11 UNII */ | |
2068 | { 140, 0x00002ccc, 0x00004a9a, 0x000bbe55, 0x000ffa03 }, | |
2069 | { 149, 0x00002ccc, 0x00004aa2, 0x000bbe55, 0x000ffa1f }, | |
2070 | { 153, 0x00002ccc, 0x00004aa6, 0x000bbe55, 0x000ffa27 }, | |
2071 | { 157, 0x00002ccc, 0x00004aae, 0x000bbe55, 0x000ffa07 }, | |
2072 | { 161, 0x00002ccc, 0x00004ab2, 0x000bbe55, 0x000ffa0f }, | |
2073 | { 165, 0x00002ccc, 0x00004ab6, 0x000bbe55, 0x000ffa17 }, | |
2074 | ||
2075 | /* MMAC(Japan)J52 ch 34,38,42,46 */ | |
2076 | { 34, 0x00002ccc, 0x0000499a, 0x0009be55, 0x000ffa0b }, | |
2077 | { 38, 0x00002ccc, 0x0000499e, 0x0009be55, 0x000ffa13 }, | |
2078 | { 42, 0x00002ccc, 0x000049a2, 0x0009be55, 0x000ffa1b }, | |
2079 | { 46, 0x00002ccc, 0x000049a6, 0x0009be55, 0x000ffa23 }, | |
2080 | }; | |
2081 | ||
2082 | ||
8c5e7a5f | 2083 | static int rt73usb_probe_hw_mode(struct rt2x00_dev *rt2x00dev) |
95ea3627 ID |
2084 | { |
2085 | struct hw_mode_spec *spec = &rt2x00dev->spec; | |
8c5e7a5f ID |
2086 | struct channel_info *info; |
2087 | char *tx_power; | |
95ea3627 ID |
2088 | unsigned int i; |
2089 | ||
2090 | /* | |
2091 | * Initialize all hw fields. | |
5a5b6ed6 HS |
2092 | * |
2093 | * Don't set IEEE80211_HW_HOST_BROADCAST_PS_BUFFERING unless we are | |
2094 | * capable of sending the buffered frames out after the DTIM | |
2095 | * transmission using rt2x00lib_beacondone. This will send out | |
2096 | * multicast and broadcast traffic immediately instead of buffering it | |
2097 | * infinitly and thus dropping it after some time. | |
95ea3627 ID |
2098 | */ |
2099 | rt2x00dev->hw->flags = | |
4be8c387 JB |
2100 | IEEE80211_HW_SIGNAL_DBM | |
2101 | IEEE80211_HW_SUPPORTS_PS | | |
2102 | IEEE80211_HW_PS_NULLFUNC_STACK; | |
95ea3627 | 2103 | |
14a3bf89 | 2104 | SET_IEEE80211_DEV(rt2x00dev->hw, rt2x00dev->dev); |
95ea3627 ID |
2105 | SET_IEEE80211_PERM_ADDR(rt2x00dev->hw, |
2106 | rt2x00_eeprom_addr(rt2x00dev, | |
2107 | EEPROM_MAC_ADDR_0)); | |
2108 | ||
95ea3627 ID |
2109 | /* |
2110 | * Initialize hw_mode information. | |
2111 | */ | |
31562e80 ID |
2112 | spec->supported_bands = SUPPORT_BAND_2GHZ; |
2113 | spec->supported_rates = SUPPORT_RATE_CCK | SUPPORT_RATE_OFDM; | |
95ea3627 | 2114 | |
5122d898 | 2115 | if (rt2x00_rf(rt2x00dev, RF2528)) { |
95ea3627 ID |
2116 | spec->num_channels = ARRAY_SIZE(rf_vals_bg_2528); |
2117 | spec->channels = rf_vals_bg_2528; | |
5122d898 | 2118 | } else if (rt2x00_rf(rt2x00dev, RF5226)) { |
31562e80 | 2119 | spec->supported_bands |= SUPPORT_BAND_5GHZ; |
95ea3627 ID |
2120 | spec->num_channels = ARRAY_SIZE(rf_vals_5226); |
2121 | spec->channels = rf_vals_5226; | |
5122d898 | 2122 | } else if (rt2x00_rf(rt2x00dev, RF2527)) { |
95ea3627 ID |
2123 | spec->num_channels = 14; |
2124 | spec->channels = rf_vals_5225_2527; | |
5122d898 | 2125 | } else if (rt2x00_rf(rt2x00dev, RF5225)) { |
31562e80 | 2126 | spec->supported_bands |= SUPPORT_BAND_5GHZ; |
95ea3627 ID |
2127 | spec->num_channels = ARRAY_SIZE(rf_vals_5225_2527); |
2128 | spec->channels = rf_vals_5225_2527; | |
2129 | } | |
2130 | ||
8c5e7a5f ID |
2131 | /* |
2132 | * Create channel information array | |
2133 | */ | |
baeb2ffa | 2134 | info = kcalloc(spec->num_channels, sizeof(*info), GFP_KERNEL); |
8c5e7a5f ID |
2135 | if (!info) |
2136 | return -ENOMEM; | |
95ea3627 | 2137 | |
8c5e7a5f ID |
2138 | spec->channels_info = info; |
2139 | ||
2140 | tx_power = rt2x00_eeprom_addr(rt2x00dev, EEPROM_TXPOWER_G_START); | |
8d1331b3 ID |
2141 | for (i = 0; i < 14; i++) { |
2142 | info[i].max_power = MAX_TXPOWER; | |
2143 | info[i].default_power1 = TXPOWER_FROM_DEV(tx_power[i]); | |
2144 | } | |
8c5e7a5f ID |
2145 | |
2146 | if (spec->num_channels > 14) { | |
2147 | tx_power = rt2x00_eeprom_addr(rt2x00dev, EEPROM_TXPOWER_A_START); | |
8d1331b3 ID |
2148 | for (i = 14; i < spec->num_channels; i++) { |
2149 | info[i].max_power = MAX_TXPOWER; | |
2150 | info[i].default_power1 = TXPOWER_FROM_DEV(tx_power[i]); | |
2151 | } | |
95ea3627 | 2152 | } |
8c5e7a5f ID |
2153 | |
2154 | return 0; | |
95ea3627 ID |
2155 | } |
2156 | ||
2157 | static int rt73usb_probe_hw(struct rt2x00_dev *rt2x00dev) | |
2158 | { | |
2159 | int retval; | |
2160 | ||
2161 | /* | |
2162 | * Allocate eeprom data. | |
2163 | */ | |
2164 | retval = rt73usb_validate_eeprom(rt2x00dev); | |
2165 | if (retval) | |
2166 | return retval; | |
2167 | ||
2168 | retval = rt73usb_init_eeprom(rt2x00dev); | |
2169 | if (retval) | |
2170 | return retval; | |
2171 | ||
2172 | /* | |
2173 | * Initialize hw specifications. | |
2174 | */ | |
8c5e7a5f ID |
2175 | retval = rt73usb_probe_hw_mode(rt2x00dev); |
2176 | if (retval) | |
2177 | return retval; | |
95ea3627 | 2178 | |
1afcfd54 IP |
2179 | /* |
2180 | * This device has multiple filters for control frames, | |
2181 | * but has no a separate filter for PS Poll frames. | |
2182 | */ | |
2183 | __set_bit(DRIVER_SUPPORT_CONTROL_FILTERS, &rt2x00dev->flags); | |
2184 | ||
95ea3627 | 2185 | /* |
9404ef34 | 2186 | * This device requires firmware. |
95ea3627 | 2187 | */ |
066cb637 | 2188 | __set_bit(DRIVER_REQUIRE_FIRMWARE, &rt2x00dev->flags); |
008c4482 ID |
2189 | if (!modparam_nohwcrypt) |
2190 | __set_bit(CONFIG_SUPPORT_HW_CRYPTO, &rt2x00dev->flags); | |
27df2a9c | 2191 | __set_bit(DRIVER_SUPPORT_LINK_TUNING, &rt2x00dev->flags); |
c965c74b | 2192 | __set_bit(DRIVER_SUPPORT_WATCHDOG, &rt2x00dev->flags); |
95ea3627 ID |
2193 | |
2194 | /* | |
2195 | * Set the rssi offset. | |
2196 | */ | |
2197 | rt2x00dev->rssi_offset = DEFAULT_RSSI_OFFSET; | |
2198 | ||
2199 | return 0; | |
2200 | } | |
2201 | ||
2202 | /* | |
2203 | * IEEE80211 stack callback functions. | |
2204 | */ | |
2af0a570 ID |
2205 | static int rt73usb_conf_tx(struct ieee80211_hw *hw, u16 queue_idx, |
2206 | const struct ieee80211_tx_queue_params *params) | |
2207 | { | |
2208 | struct rt2x00_dev *rt2x00dev = hw->priv; | |
2209 | struct data_queue *queue; | |
2210 | struct rt2x00_field32 field; | |
2211 | int retval; | |
2212 | u32 reg; | |
5e790023 | 2213 | u32 offset; |
2af0a570 ID |
2214 | |
2215 | /* | |
2216 | * First pass the configuration through rt2x00lib, that will | |
2217 | * update the queue settings and validate the input. After that | |
2218 | * we are free to update the registers based on the value | |
2219 | * in the queue parameter. | |
2220 | */ | |
2221 | retval = rt2x00mac_conf_tx(hw, queue_idx, params); | |
2222 | if (retval) | |
2223 | return retval; | |
2224 | ||
5e790023 ID |
2225 | /* |
2226 | * We only need to perform additional register initialization | |
2227 | * for WMM queues/ | |
2228 | */ | |
2229 | if (queue_idx >= 4) | |
2230 | return 0; | |
2231 | ||
2af0a570 ID |
2232 | queue = rt2x00queue_get_queue(rt2x00dev, queue_idx); |
2233 | ||
2234 | /* Update WMM TXOP register */ | |
5e790023 ID |
2235 | offset = AC_TXOP_CSR0 + (sizeof(u32) * (!!(queue_idx & 2))); |
2236 | field.bit_offset = (queue_idx & 1) * 16; | |
2237 | field.bit_mask = 0xffff << field.bit_offset; | |
2238 | ||
2239 | rt2x00usb_register_read(rt2x00dev, offset, ®); | |
2240 | rt2x00_set_field32(®, field, queue->txop); | |
2241 | rt2x00usb_register_write(rt2x00dev, offset, reg); | |
2af0a570 ID |
2242 | |
2243 | /* Update WMM registers */ | |
2244 | field.bit_offset = queue_idx * 4; | |
2245 | field.bit_mask = 0xf << field.bit_offset; | |
2246 | ||
0f829b1d | 2247 | rt2x00usb_register_read(rt2x00dev, AIFSN_CSR, ®); |
2af0a570 | 2248 | rt2x00_set_field32(®, field, queue->aifs); |
0f829b1d | 2249 | rt2x00usb_register_write(rt2x00dev, AIFSN_CSR, reg); |
2af0a570 | 2250 | |
0f829b1d | 2251 | rt2x00usb_register_read(rt2x00dev, CWMIN_CSR, ®); |
2af0a570 | 2252 | rt2x00_set_field32(®, field, queue->cw_min); |
0f829b1d | 2253 | rt2x00usb_register_write(rt2x00dev, CWMIN_CSR, reg); |
2af0a570 | 2254 | |
0f829b1d | 2255 | rt2x00usb_register_read(rt2x00dev, CWMAX_CSR, ®); |
2af0a570 | 2256 | rt2x00_set_field32(®, field, queue->cw_max); |
0f829b1d | 2257 | rt2x00usb_register_write(rt2x00dev, CWMAX_CSR, reg); |
2af0a570 ID |
2258 | |
2259 | return 0; | |
2260 | } | |
2261 | ||
95ea3627 ID |
2262 | static u64 rt73usb_get_tsf(struct ieee80211_hw *hw) |
2263 | { | |
2264 | struct rt2x00_dev *rt2x00dev = hw->priv; | |
2265 | u64 tsf; | |
2266 | u32 reg; | |
2267 | ||
0f829b1d | 2268 | rt2x00usb_register_read(rt2x00dev, TXRX_CSR13, ®); |
95ea3627 | 2269 | tsf = (u64) rt2x00_get_field32(reg, TXRX_CSR13_HIGH_TSFTIMER) << 32; |
0f829b1d | 2270 | rt2x00usb_register_read(rt2x00dev, TXRX_CSR12, ®); |
95ea3627 ID |
2271 | tsf |= rt2x00_get_field32(reg, TXRX_CSR12_LOW_TSFTIMER); |
2272 | ||
2273 | return tsf; | |
2274 | } | |
95ea3627 | 2275 | |
95ea3627 ID |
2276 | static const struct ieee80211_ops rt73usb_mac80211_ops = { |
2277 | .tx = rt2x00mac_tx, | |
4150c572 JB |
2278 | .start = rt2x00mac_start, |
2279 | .stop = rt2x00mac_stop, | |
95ea3627 ID |
2280 | .add_interface = rt2x00mac_add_interface, |
2281 | .remove_interface = rt2x00mac_remove_interface, | |
2282 | .config = rt2x00mac_config, | |
3a643d24 | 2283 | .configure_filter = rt2x00mac_configure_filter, |
930c06f2 | 2284 | .set_tim = rt2x00mac_set_tim, |
906c110f | 2285 | .set_key = rt2x00mac_set_key, |
d8147f9d ID |
2286 | .sw_scan_start = rt2x00mac_sw_scan_start, |
2287 | .sw_scan_complete = rt2x00mac_sw_scan_complete, | |
95ea3627 | 2288 | .get_stats = rt2x00mac_get_stats, |
471b3efd | 2289 | .bss_info_changed = rt2x00mac_bss_info_changed, |
2af0a570 | 2290 | .conf_tx = rt73usb_conf_tx, |
95ea3627 | 2291 | .get_tsf = rt73usb_get_tsf, |
e47a5cdd | 2292 | .rfkill_poll = rt2x00mac_rfkill_poll, |
f44df18c | 2293 | .flush = rt2x00mac_flush, |
95ea3627 ID |
2294 | }; |
2295 | ||
2296 | static const struct rt2x00lib_ops rt73usb_rt2x00_ops = { | |
2297 | .probe_hw = rt73usb_probe_hw, | |
2298 | .get_firmware_name = rt73usb_get_firmware_name, | |
0cbe0064 | 2299 | .check_firmware = rt73usb_check_firmware, |
95ea3627 ID |
2300 | .load_firmware = rt73usb_load_firmware, |
2301 | .initialize = rt2x00usb_initialize, | |
2302 | .uninitialize = rt2x00usb_uninitialize, | |
798b7adb | 2303 | .clear_entry = rt2x00usb_clear_entry, |
95ea3627 | 2304 | .set_device_state = rt73usb_set_device_state, |
7396faf4 | 2305 | .rfkill_poll = rt73usb_rfkill_poll, |
95ea3627 ID |
2306 | .link_stats = rt73usb_link_stats, |
2307 | .reset_tuner = rt73usb_reset_tuner, | |
2308 | .link_tuner = rt73usb_link_tuner, | |
c965c74b | 2309 | .watchdog = rt2x00usb_watchdog, |
dbba306f ID |
2310 | .start_queue = rt73usb_start_queue, |
2311 | .kick_queue = rt2x00usb_kick_queue, | |
2312 | .stop_queue = rt73usb_stop_queue, | |
5be65609 | 2313 | .flush_queue = rt2x00usb_flush_queue, |
95ea3627 | 2314 | .write_tx_desc = rt73usb_write_tx_desc, |
bd88a781 | 2315 | .write_beacon = rt73usb_write_beacon, |
dd9fa2d2 | 2316 | .get_tx_data_len = rt73usb_get_tx_data_len, |
95ea3627 | 2317 | .fill_rxdone = rt73usb_fill_rxdone, |
906c110f ID |
2318 | .config_shared_key = rt73usb_config_shared_key, |
2319 | .config_pairwise_key = rt73usb_config_pairwise_key, | |
3a643d24 | 2320 | .config_filter = rt73usb_config_filter, |
6bb40dd1 | 2321 | .config_intf = rt73usb_config_intf, |
72810379 | 2322 | .config_erp = rt73usb_config_erp, |
e4ea1c40 | 2323 | .config_ant = rt73usb_config_ant, |
95ea3627 ID |
2324 | .config = rt73usb_config, |
2325 | }; | |
2326 | ||
181d6902 | 2327 | static const struct data_queue_desc rt73usb_queue_rx = { |
efd2f271 | 2328 | .entry_num = 32, |
181d6902 ID |
2329 | .data_size = DATA_FRAME_SIZE, |
2330 | .desc_size = RXD_DESC_SIZE, | |
b8be63ff | 2331 | .priv_size = sizeof(struct queue_entry_priv_usb), |
181d6902 ID |
2332 | }; |
2333 | ||
2334 | static const struct data_queue_desc rt73usb_queue_tx = { | |
efd2f271 | 2335 | .entry_num = 32, |
181d6902 ID |
2336 | .data_size = DATA_FRAME_SIZE, |
2337 | .desc_size = TXD_DESC_SIZE, | |
b8be63ff | 2338 | .priv_size = sizeof(struct queue_entry_priv_usb), |
181d6902 ID |
2339 | }; |
2340 | ||
2341 | static const struct data_queue_desc rt73usb_queue_bcn = { | |
efd2f271 | 2342 | .entry_num = 4, |
181d6902 ID |
2343 | .data_size = MGMT_FRAME_SIZE, |
2344 | .desc_size = TXINFO_SIZE, | |
b8be63ff | 2345 | .priv_size = sizeof(struct queue_entry_priv_usb), |
181d6902 ID |
2346 | }; |
2347 | ||
95ea3627 | 2348 | static const struct rt2x00_ops rt73usb_ops = { |
04d0362e GW |
2349 | .name = KBUILD_MODNAME, |
2350 | .max_sta_intf = 1, | |
2351 | .max_ap_intf = 4, | |
2352 | .eeprom_size = EEPROM_SIZE, | |
2353 | .rf_size = RF_SIZE, | |
2354 | .tx_queues = NUM_TX_QUEUES, | |
e6218cc4 | 2355 | .extra_tx_headroom = TXD_DESC_SIZE, |
04d0362e GW |
2356 | .rx = &rt73usb_queue_rx, |
2357 | .tx = &rt73usb_queue_tx, | |
2358 | .bcn = &rt73usb_queue_bcn, | |
2359 | .lib = &rt73usb_rt2x00_ops, | |
2360 | .hw = &rt73usb_mac80211_ops, | |
95ea3627 | 2361 | #ifdef CONFIG_RT2X00_LIB_DEBUGFS |
04d0362e | 2362 | .debugfs = &rt73usb_rt2x00debug, |
95ea3627 ID |
2363 | #endif /* CONFIG_RT2X00_LIB_DEBUGFS */ |
2364 | }; | |
2365 | ||
2366 | /* | |
2367 | * rt73usb module information. | |
2368 | */ | |
2369 | static struct usb_device_id rt73usb_device_table[] = { | |
2370 | /* AboCom */ | |
ef4bb70d XVP |
2371 | { USB_DEVICE(0x07b8, 0xb21b), USB_DEVICE_DATA(&rt73usb_ops) }, |
2372 | { USB_DEVICE(0x07b8, 0xb21c), USB_DEVICE_DATA(&rt73usb_ops) }, | |
95ea3627 | 2373 | { USB_DEVICE(0x07b8, 0xb21d), USB_DEVICE_DATA(&rt73usb_ops) }, |
ef4bb70d XVP |
2374 | { USB_DEVICE(0x07b8, 0xb21e), USB_DEVICE_DATA(&rt73usb_ops) }, |
2375 | { USB_DEVICE(0x07b8, 0xb21f), USB_DEVICE_DATA(&rt73usb_ops) }, | |
2376 | /* AL */ | |
2377 | { USB_DEVICE(0x14b2, 0x3c10), USB_DEVICE_DATA(&rt73usb_ops) }, | |
144d9ad9 ID |
2378 | /* Amigo */ |
2379 | { USB_DEVICE(0x148f, 0x9021), USB_DEVICE_DATA(&rt73usb_ops) }, | |
2380 | { USB_DEVICE(0x0eb0, 0x9021), USB_DEVICE_DATA(&rt73usb_ops) }, | |
ef4bb70d XVP |
2381 | /* AMIT */ |
2382 | { USB_DEVICE(0x18c5, 0x0002), USB_DEVICE_DATA(&rt73usb_ops) }, | |
95ea3627 ID |
2383 | /* Askey */ |
2384 | { USB_DEVICE(0x1690, 0x0722), USB_DEVICE_DATA(&rt73usb_ops) }, | |
2385 | /* ASUS */ | |
2386 | { USB_DEVICE(0x0b05, 0x1723), USB_DEVICE_DATA(&rt73usb_ops) }, | |
2387 | { USB_DEVICE(0x0b05, 0x1724), USB_DEVICE_DATA(&rt73usb_ops) }, | |
2388 | /* Belkin */ | |
2389 | { USB_DEVICE(0x050d, 0x7050), USB_DEVICE_DATA(&rt73usb_ops) }, | |
2390 | { USB_DEVICE(0x050d, 0x705a), USB_DEVICE_DATA(&rt73usb_ops) }, | |
2391 | { USB_DEVICE(0x050d, 0x905b), USB_DEVICE_DATA(&rt73usb_ops) }, | |
1f06862e | 2392 | { USB_DEVICE(0x050d, 0x905c), USB_DEVICE_DATA(&rt73usb_ops) }, |
95ea3627 ID |
2393 | /* Billionton */ |
2394 | { USB_DEVICE(0x1631, 0xc019), USB_DEVICE_DATA(&rt73usb_ops) }, | |
ef4bb70d | 2395 | { USB_DEVICE(0x08dd, 0x0120), USB_DEVICE_DATA(&rt73usb_ops) }, |
95ea3627 | 2396 | /* Buffalo */ |
964d6ad9 | 2397 | { USB_DEVICE(0x0411, 0x00d8), USB_DEVICE_DATA(&rt73usb_ops) }, |
050e8a47 | 2398 | { USB_DEVICE(0x0411, 0x00d9), USB_DEVICE_DATA(&rt73usb_ops) }, |
95ea3627 | 2399 | { USB_DEVICE(0x0411, 0x00f4), USB_DEVICE_DATA(&rt73usb_ops) }, |
6aabd4c4 ID |
2400 | { USB_DEVICE(0x0411, 0x0116), USB_DEVICE_DATA(&rt73usb_ops) }, |
2401 | { USB_DEVICE(0x0411, 0x0119), USB_DEVICE_DATA(&rt73usb_ops) }, | |
b1ef7252 | 2402 | { USB_DEVICE(0x0411, 0x0137), USB_DEVICE_DATA(&rt73usb_ops) }, |
51b2853f BP |
2403 | /* CEIVA */ |
2404 | { USB_DEVICE(0x178d, 0x02be), USB_DEVICE_DATA(&rt73usb_ops) }, | |
95ea3627 ID |
2405 | /* CNet */ |
2406 | { USB_DEVICE(0x1371, 0x9022), USB_DEVICE_DATA(&rt73usb_ops) }, | |
2407 | { USB_DEVICE(0x1371, 0x9032), USB_DEVICE_DATA(&rt73usb_ops) }, | |
2408 | /* Conceptronic */ | |
2409 | { USB_DEVICE(0x14b2, 0x3c22), USB_DEVICE_DATA(&rt73usb_ops) }, | |
0a74892b MM |
2410 | /* Corega */ |
2411 | { USB_DEVICE(0x07aa, 0x002e), USB_DEVICE_DATA(&rt73usb_ops) }, | |
95ea3627 ID |
2412 | /* D-Link */ |
2413 | { USB_DEVICE(0x07d1, 0x3c03), USB_DEVICE_DATA(&rt73usb_ops) }, | |
2414 | { USB_DEVICE(0x07d1, 0x3c04), USB_DEVICE_DATA(&rt73usb_ops) }, | |
cb62eccd | 2415 | { USB_DEVICE(0x07d1, 0x3c06), USB_DEVICE_DATA(&rt73usb_ops) }, |
445815d7 | 2416 | { USB_DEVICE(0x07d1, 0x3c07), USB_DEVICE_DATA(&rt73usb_ops) }, |
ef4bb70d XVP |
2417 | /* Edimax */ |
2418 | { USB_DEVICE(0x7392, 0x7318), USB_DEVICE_DATA(&rt73usb_ops) }, | |
2419 | { USB_DEVICE(0x7392, 0x7618), USB_DEVICE_DATA(&rt73usb_ops) }, | |
2420 | /* EnGenius */ | |
2421 | { USB_DEVICE(0x1740, 0x3701), USB_DEVICE_DATA(&rt73usb_ops) }, | |
95ea3627 ID |
2422 | /* Gemtek */ |
2423 | { USB_DEVICE(0x15a9, 0x0004), USB_DEVICE_DATA(&rt73usb_ops) }, | |
2424 | /* Gigabyte */ | |
2425 | { USB_DEVICE(0x1044, 0x8008), USB_DEVICE_DATA(&rt73usb_ops) }, | |
2426 | { USB_DEVICE(0x1044, 0x800a), USB_DEVICE_DATA(&rt73usb_ops) }, | |
2427 | /* Huawei-3Com */ | |
2428 | { USB_DEVICE(0x1472, 0x0009), USB_DEVICE_DATA(&rt73usb_ops) }, | |
2429 | /* Hercules */ | |
78bd6bbf | 2430 | { USB_DEVICE(0x06f8, 0xe002), USB_DEVICE_DATA(&rt73usb_ops) }, |
95ea3627 ID |
2431 | { USB_DEVICE(0x06f8, 0xe010), USB_DEVICE_DATA(&rt73usb_ops) }, |
2432 | { USB_DEVICE(0x06f8, 0xe020), USB_DEVICE_DATA(&rt73usb_ops) }, | |
2433 | /* Linksys */ | |
2434 | { USB_DEVICE(0x13b1, 0x0020), USB_DEVICE_DATA(&rt73usb_ops) }, | |
2435 | { USB_DEVICE(0x13b1, 0x0023), USB_DEVICE_DATA(&rt73usb_ops) }, | |
3be36ae2 | 2436 | { USB_DEVICE(0x13b1, 0x0028), USB_DEVICE_DATA(&rt73usb_ops) }, |
95ea3627 | 2437 | /* MSI */ |
22720645 | 2438 | { USB_DEVICE(0x0db0, 0x4600), USB_DEVICE_DATA(&rt73usb_ops) }, |
95ea3627 ID |
2439 | { USB_DEVICE(0x0db0, 0x6877), USB_DEVICE_DATA(&rt73usb_ops) }, |
2440 | { USB_DEVICE(0x0db0, 0x6874), USB_DEVICE_DATA(&rt73usb_ops) }, | |
2441 | { USB_DEVICE(0x0db0, 0xa861), USB_DEVICE_DATA(&rt73usb_ops) }, | |
2442 | { USB_DEVICE(0x0db0, 0xa874), USB_DEVICE_DATA(&rt73usb_ops) }, | |
22720645 XVP |
2443 | /* Ovislink */ |
2444 | { USB_DEVICE(0x1b75, 0x7318), USB_DEVICE_DATA(&rt73usb_ops) }, | |
95ea3627 | 2445 | /* Ralink */ |
144d9ad9 | 2446 | { USB_DEVICE(0x04bb, 0x093d), USB_DEVICE_DATA(&rt73usb_ops) }, |
95ea3627 ID |
2447 | { USB_DEVICE(0x148f, 0x2573), USB_DEVICE_DATA(&rt73usb_ops) }, |
2448 | { USB_DEVICE(0x148f, 0x2671), USB_DEVICE_DATA(&rt73usb_ops) }, | |
9c4cf6d9 | 2449 | { USB_DEVICE(0x0812, 0x3101), USB_DEVICE_DATA(&rt73usb_ops) }, |
95ea3627 ID |
2450 | /* Qcom */ |
2451 | { USB_DEVICE(0x18e8, 0x6196), USB_DEVICE_DATA(&rt73usb_ops) }, | |
2452 | { USB_DEVICE(0x18e8, 0x6229), USB_DEVICE_DATA(&rt73usb_ops) }, | |
2453 | { USB_DEVICE(0x18e8, 0x6238), USB_DEVICE_DATA(&rt73usb_ops) }, | |
ef4bb70d XVP |
2454 | /* Samsung */ |
2455 | { USB_DEVICE(0x04e8, 0x4471), USB_DEVICE_DATA(&rt73usb_ops) }, | |
95ea3627 ID |
2456 | /* Senao */ |
2457 | { USB_DEVICE(0x1740, 0x7100), USB_DEVICE_DATA(&rt73usb_ops) }, | |
2458 | /* Sitecom */ | |
ef4bb70d XVP |
2459 | { USB_DEVICE(0x0df6, 0x0024), USB_DEVICE_DATA(&rt73usb_ops) }, |
2460 | { USB_DEVICE(0x0df6, 0x0027), USB_DEVICE_DATA(&rt73usb_ops) }, | |
2461 | { USB_DEVICE(0x0df6, 0x002f), USB_DEVICE_DATA(&rt73usb_ops) }, | |
95ea3627 | 2462 | { USB_DEVICE(0x0df6, 0x90ac), USB_DEVICE_DATA(&rt73usb_ops) }, |
ef4bb70d | 2463 | { USB_DEVICE(0x0df6, 0x9712), USB_DEVICE_DATA(&rt73usb_ops) }, |
95ea3627 ID |
2464 | /* Surecom */ |
2465 | { USB_DEVICE(0x0769, 0x31f3), USB_DEVICE_DATA(&rt73usb_ops) }, | |
14344b81 ID |
2466 | /* Tilgin */ |
2467 | { USB_DEVICE(0x6933, 0x5001), USB_DEVICE_DATA(&rt73usb_ops) }, | |
ef4bb70d XVP |
2468 | /* Philips */ |
2469 | { USB_DEVICE(0x0471, 0x200a), USB_DEVICE_DATA(&rt73usb_ops) }, | |
95ea3627 ID |
2470 | /* Planex */ |
2471 | { USB_DEVICE(0x2019, 0xab01), USB_DEVICE_DATA(&rt73usb_ops) }, | |
2472 | { USB_DEVICE(0x2019, 0xab50), USB_DEVICE_DATA(&rt73usb_ops) }, | |
22720645 XVP |
2473 | /* WideTell */ |
2474 | { USB_DEVICE(0x7167, 0x3840), USB_DEVICE_DATA(&rt73usb_ops) }, | |
ef4bb70d XVP |
2475 | /* Zcom */ |
2476 | { USB_DEVICE(0x0cde, 0x001c), USB_DEVICE_DATA(&rt73usb_ops) }, | |
144d9ad9 ID |
2477 | /* ZyXEL */ |
2478 | { USB_DEVICE(0x0586, 0x3415), USB_DEVICE_DATA(&rt73usb_ops) }, | |
95ea3627 ID |
2479 | { 0, } |
2480 | }; | |
2481 | ||
2482 | MODULE_AUTHOR(DRV_PROJECT); | |
2483 | MODULE_VERSION(DRV_VERSION); | |
2484 | MODULE_DESCRIPTION("Ralink RT73 USB Wireless LAN driver."); | |
2485 | MODULE_SUPPORTED_DEVICE("Ralink RT2571W & RT2671 USB chipset based cards"); | |
2486 | MODULE_DEVICE_TABLE(usb, rt73usb_device_table); | |
2487 | MODULE_FIRMWARE(FIRMWARE_RT2571); | |
2488 | MODULE_LICENSE("GPL"); | |
2489 | ||
2490 | static struct usb_driver rt73usb_driver = { | |
2360157c | 2491 | .name = KBUILD_MODNAME, |
95ea3627 ID |
2492 | .id_table = rt73usb_device_table, |
2493 | .probe = rt2x00usb_probe, | |
2494 | .disconnect = rt2x00usb_disconnect, | |
2495 | .suspend = rt2x00usb_suspend, | |
2496 | .resume = rt2x00usb_resume, | |
2497 | }; | |
2498 | ||
2499 | static int __init rt73usb_init(void) | |
2500 | { | |
2501 | return usb_register(&rt73usb_driver); | |
2502 | } | |
2503 | ||
2504 | static void __exit rt73usb_exit(void) | |
2505 | { | |
2506 | usb_deregister(&rt73usb_driver); | |
2507 | } | |
2508 | ||
2509 | module_init(rt73usb_init); | |
2510 | module_exit(rt73usb_exit); |