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rt2x00: Move intf_work to mac82011 workqueue
[deliverable/linux.git] / drivers / net / wireless / rt2x00 / rt73usb.c
CommitLineData
95ea3627 1/*
4e54c711 2 Copyright (C) 2004 - 2009 rt2x00 SourceForge Project
95ea3627
ID		 3 <http://rt2x00.serialmonkey.com>
4
5 This program is free software; you can redistribute it and/or modify
6 it under the terms of the GNU General Public License as published by
7 the Free Software Foundation; either version 2 of the License, or
8 (at your option) any later version.
9
10 This program is distributed in the hope that it will be useful,
11 but WITHOUT ANY WARRANTY; without even the implied warranty of
12 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 GNU General Public License for more details.
14
15 You should have received a copy of the GNU General Public License
16 along with this program; if not, write to the
17 Free Software Foundation, Inc.,
18 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
19 */
20
21/*
22 Module: rt73usb
23 Abstract: rt73usb device specific routines.
24 Supported chipsets: rt2571W & rt2671.
25 */
26
a7f3a06c 27#include <linux/crc-itu-t.h>
95ea3627
ID		 28#include <linux/delay.h>
29#include <linux/etherdevice.h>
30#include <linux/init.h>
31#include <linux/kernel.h>
32#include <linux/module.h>
33#include <linux/usb.h>
34
35#include "rt2x00.h"
36#include "rt2x00usb.h"
37#include "rt73usb.h"
38
008c4482
ID		 39/*
40 * Allow hardware encryption to be disabled.
41 */
42static int modparam_nohwcrypt = 0;
43module_param_named(nohwcrypt, modparam_nohwcrypt, bool, S_IRUGO);
44MODULE_PARM_DESC(nohwcrypt, "Disable hardware encryption.");
45
95ea3627
ID		 46/*
47 * Register access.
48 * All access to the CSR registers will go through the methods
0f829b1d 49 * rt2x00usb_register_read and rt2x00usb_register_write.
95ea3627
ID		 50 * BBP and RF register require indirect register access,
51 * and use the CSR registers BBPCSR and RFCSR to achieve this.
52 * These indirect registers work with busy bits,
53 * and we will try maximal REGISTER_BUSY_COUNT times to access
54 * the register while taking a REGISTER_BUSY_DELAY us delay
55 * between each attampt. When the busy bit is still set at that time,
56 * the access attempt is considered to have failed,
57 * and we will print an error.
8ff48a8b 58 * The _lock versions must be used if you already hold the csr_mutex
95ea3627 59 */
c9c3b1a5 60#define WAIT_FOR_BBP(__dev, __reg) \
0f829b1d 61 rt2x00usb_regbusy_read((__dev), PHY_CSR3, PHY_CSR3_BUSY, (__reg))
c9c3b1a5 62#define WAIT_FOR_RF(__dev, __reg) \
0f829b1d 63 rt2x00usb_regbusy_read((__dev), PHY_CSR4, PHY_CSR4_BUSY, (__reg))
c9c3b1a5 64
0e14f6d3 65static void rt73usb_bbp_write(struct rt2x00_dev *rt2x00dev,
95ea3627
ID		 66 const unsigned int word, const u8 value)
67{
68 u32 reg;
69
8ff48a8b 70 mutex_lock(&rt2x00dev->csr_mutex);
3d82346c 71
95ea3627 72 /*
c9c3b1a5
ID		 73 * Wait until the BBP becomes available, afterwards we
74 * can safely write the new data into the register.
95ea3627 75 */
c9c3b1a5
ID		 76 if (WAIT_FOR_BBP(rt2x00dev, &reg)) {
77 reg = 0;
78 rt2x00_set_field32(&reg, PHY_CSR3_VALUE, value);
79 rt2x00_set_field32(&reg, PHY_CSR3_REGNUM, word);
80 rt2x00_set_field32(&reg, PHY_CSR3_BUSY, 1);
81 rt2x00_set_field32(&reg, PHY_CSR3_READ_CONTROL, 0);
82
0f829b1d 83 rt2x00usb_register_write_lock(rt2x00dev, PHY_CSR3, reg);
c9c3b1a5 84 }
99ade259 85
8ff48a8b 86 mutex_unlock(&rt2x00dev->csr_mutex);
95ea3627
ID		 87}
88
0e14f6d3 89static void rt73usb_bbp_read(struct rt2x00_dev *rt2x00dev,
95ea3627
ID		 90 const unsigned int word, u8 *value)
91{
92 u32 reg;
93
8ff48a8b 94 mutex_lock(&rt2x00dev->csr_mutex);
3d82346c 95
95ea3627 96 /*
c9c3b1a5
ID		 97 * Wait until the BBP becomes available, afterwards we
98 * can safely write the read request into the register.
99 * After the data has been written, we wait until hardware
100 * returns the correct value, if at any time the register
101 * doesn't become available in time, reg will be 0xffffffff
102 * which means we return 0xff to the caller.
95ea3627 103 */
c9c3b1a5
ID		 104 if (WAIT_FOR_BBP(rt2x00dev, &reg)) {
105 reg = 0;
106 rt2x00_set_field32(&reg, PHY_CSR3_REGNUM, word);
107 rt2x00_set_field32(&reg, PHY_CSR3_BUSY, 1);
108 rt2x00_set_field32(&reg, PHY_CSR3_READ_CONTROL, 1);
95ea3627 109
0f829b1d 110 rt2x00usb_register_write_lock(rt2x00dev, PHY_CSR3, reg);
95ea3627 111
c9c3b1a5
ID		 112 WAIT_FOR_BBP(rt2x00dev, &reg);
113 }
95ea3627
ID		 114
115 *value = rt2x00_get_field32(reg, PHY_CSR3_VALUE);
99ade259 116
8ff48a8b 117 mutex_unlock(&rt2x00dev->csr_mutex);
95ea3627
ID		 118}
119
0e14f6d3 120static void rt73usb_rf_write(struct rt2x00_dev *rt2x00dev,
95ea3627
ID		 121 const unsigned int word, const u32 value)
122{
123 u32 reg;
95ea3627
ID		 124
125 if (!word)
126 return;
127
8ff48a8b 128 mutex_lock(&rt2x00dev->csr_mutex);
3d82346c 129
4f5af6eb 130 /*
c9c3b1a5
ID		 131 * Wait until the RF becomes available, afterwards we
132 * can safely write the new data into the register.
4f5af6eb 133 */
c9c3b1a5
ID		 134 if (WAIT_FOR_RF(rt2x00dev, &reg)) {
135 reg = 0;
136 rt2x00_set_field32(&reg, PHY_CSR4_VALUE, value);
137 /*
138 * RF5225 and RF2527 contain 21 bits per RF register value,
139 * all others contain 20 bits.
140 */
141 rt2x00_set_field32(&reg, PHY_CSR4_NUMBER_OF_BITS,
142 20 + (rt2x00_rf(&rt2x00dev->chip, RF5225) ||
143 rt2x00_rf(&rt2x00dev->chip, RF2527)));
144 rt2x00_set_field32(&reg, PHY_CSR4_IF_SELECT, 0);
145 rt2x00_set_field32(&reg, PHY_CSR4_BUSY, 1);
146
0f829b1d 147 rt2x00usb_register_write_lock(rt2x00dev, PHY_CSR4, reg);
c9c3b1a5
ID		 148 rt2x00_rf_write(rt2x00dev, word, value);
149 }
8ff48a8b
ID		 150
151 mutex_unlock(&rt2x00dev->csr_mutex);
95ea3627
ID		 152}
153
154#ifdef CONFIG_RT2X00_LIB_DEBUGFS
95ea3627
ID		 155static const struct rt2x00debug rt73usb_rt2x00debug = {
156 .owner = THIS_MODULE,
157 .csr = {
0f829b1d
ID		 158 .read = rt2x00usb_register_read,
159 .write = rt2x00usb_register_write,
743b97ca
ID		 160 .flags = RT2X00DEBUGFS_OFFSET,
161 .word_base = CSR_REG_BASE,
95ea3627
ID		 162 .word_size = sizeof(u32),
163 .word_count = CSR_REG_SIZE / sizeof(u32),
164 },
165 .eeprom = {
166 .read = rt2x00_eeprom_read,
167 .write = rt2x00_eeprom_write,
743b97ca 168 .word_base = EEPROM_BASE,
95ea3627
ID		 169 .word_size = sizeof(u16),
170 .word_count = EEPROM_SIZE / sizeof(u16),
171 },
172 .bbp = {
173 .read = rt73usb_bbp_read,
174 .write = rt73usb_bbp_write,
743b97ca 175 .word_base = BBP_BASE,
95ea3627
ID		 176 .word_size = sizeof(u8),
177 .word_count = BBP_SIZE / sizeof(u8),
178 },
179 .rf = {
180 .read = rt2x00_rf_read,
181 .write = rt73usb_rf_write,
743b97ca 182 .word_base = RF_BASE,
95ea3627
ID		 183 .word_size = sizeof(u32),
184 .word_count = RF_SIZE / sizeof(u32),
185 },
186};
187#endif /* CONFIG_RT2X00_LIB_DEBUGFS */
188
7396faf4
ID		 189#ifdef CONFIG_RT2X00_LIB_RFKILL
190static int rt73usb_rfkill_poll(struct rt2x00_dev *rt2x00dev)
191{
192 u32 reg;
193
194 rt2x00usb_register_read(rt2x00dev, MAC_CSR13, &reg);
195 return rt2x00_get_field32(reg, MAC_CSR13_BIT7);
196}
197#else
198#define rt73usb_rfkill_poll NULL
199#endif /* CONFIG_RT2X00_LIB_RFKILL */
200
771fd565 201#ifdef CONFIG_RT2X00_LIB_LEDS
a2e1d52a 202static void rt73usb_brightness_set(struct led_classdev *led_cdev,
a9450b70
ID		 203 enum led_brightness brightness)
204{
205 struct rt2x00_led *led =
206 container_of(led_cdev, struct rt2x00_led, led_dev);
207 unsigned int enabled = brightness != LED_OFF;
208 unsigned int a_mode =
209 (enabled && led->rt2x00dev->curr_band == IEEE80211_BAND_5GHZ);
210 unsigned int bg_mode =
211 (enabled && led->rt2x00dev->curr_band == IEEE80211_BAND_2GHZ);
212
213 if (led->type == LED_TYPE_RADIO) {
214 rt2x00_set_field16(&led->rt2x00dev->led_mcu_reg,
215 MCU_LEDCS_RADIO_STATUS, enabled);
216
47b10cd1
ID		 217 rt2x00usb_vendor_request_sw(led->rt2x00dev, USB_LED_CONTROL,
218 0, led->rt2x00dev->led_mcu_reg,
219 REGISTER_TIMEOUT);
a9450b70
ID		 220 } else if (led->type == LED_TYPE_ASSOC) {
221 rt2x00_set_field16(&led->rt2x00dev->led_mcu_reg,
222 MCU_LEDCS_LINK_BG_STATUS, bg_mode);
223 rt2x00_set_field16(&led->rt2x00dev->led_mcu_reg,
224 MCU_LEDCS_LINK_A_STATUS, a_mode);
225
47b10cd1
ID		 226 rt2x00usb_vendor_request_sw(led->rt2x00dev, USB_LED_CONTROL,
227 0, led->rt2x00dev->led_mcu_reg,
228 REGISTER_TIMEOUT);
a9450b70
ID		 229 } else if (led->type == LED_TYPE_QUALITY) {
230 /*
231 * The brightness is divided into 6 levels (0 - 5),
232 * this means we need to convert the brightness
233 * argument into the matching level within that range.
234 */
47b10cd1
ID		 235 rt2x00usb_vendor_request_sw(led->rt2x00dev, USB_LED_CONTROL,
236 brightness / (LED_FULL / 6),
237 led->rt2x00dev->led_mcu_reg,
238 REGISTER_TIMEOUT);
a9450b70
ID		 239 }
240}
a2e1d52a
ID		 241
242static int rt73usb_blink_set(struct led_classdev *led_cdev,
243 unsigned long *delay_on,
244 unsigned long *delay_off)
245{
246 struct rt2x00_led *led =
247 container_of(led_cdev, struct rt2x00_led, led_dev);
248 u32 reg;
249
0f829b1d 250 rt2x00usb_register_read(led->rt2x00dev, MAC_CSR14, &reg);
a2e1d52a
ID		 251 rt2x00_set_field32(&reg, MAC_CSR14_ON_PERIOD, *delay_on);
252 rt2x00_set_field32(&reg, MAC_CSR14_OFF_PERIOD, *delay_off);
0f829b1d 253 rt2x00usb_register_write(led->rt2x00dev, MAC_CSR14, reg);
a2e1d52a
ID		 254
255 return 0;
256}
475433be
ID		 257
258static void rt73usb_init_led(struct rt2x00_dev *rt2x00dev,
259 struct rt2x00_led *led,
260 enum led_type type)
261{
262 led->rt2x00dev = rt2x00dev;
263 led->type = type;
264 led->led_dev.brightness_set = rt73usb_brightness_set;
265 led->led_dev.blink_set = rt73usb_blink_set;
266 led->flags = LED_INITIALIZED;
267}
771fd565 268#endif /* CONFIG_RT2X00_LIB_LEDS */
a9450b70 269
95ea3627
ID		 270/*
271 * Configuration handlers.
272 */
906c110f
ID		 273static int rt73usb_config_shared_key(struct rt2x00_dev *rt2x00dev,
274 struct rt2x00lib_crypto *crypto,
275 struct ieee80211_key_conf *key)
276{
277 struct hw_key_entry key_entry;
278 struct rt2x00_field32 field;
279 int timeout;
280 u32 mask;
281 u32 reg;
282
283 if (crypto->cmd == SET_KEY) {
284 /*
285 * rt2x00lib can't determine the correct free
286 * key_idx for shared keys. We have 1 register
287 * with key valid bits. The goal is simple, read
288 * the register, if that is full we have no slots
289 * left.
290 * Note that each BSS is allowed to have up to 4
291 * shared keys, so put a mask over the allowed
292 * entries.
293 */
294 mask = (0xf << crypto->bssidx);
295
0f829b1d 296 rt2x00usb_register_read(rt2x00dev, SEC_CSR0, &reg);
906c110f
ID		 297 reg &= mask;
298
299 if (reg && reg == mask)
300 return -ENOSPC;
301
acaf908d 302 key->hw_key_idx += reg ? ffz(reg) : 0;
906c110f
ID		 303
304 /*
305 * Upload key to hardware
306 */
307 memcpy(key_entry.key, crypto->key,
308 sizeof(key_entry.key));
309 memcpy(key_entry.tx_mic, crypto->tx_mic,
310 sizeof(key_entry.tx_mic));
311 memcpy(key_entry.rx_mic, crypto->rx_mic,
312 sizeof(key_entry.rx_mic));
313
314 reg = SHARED_KEY_ENTRY(key->hw_key_idx);
315 timeout = REGISTER_TIMEOUT32(sizeof(key_entry));
316 rt2x00usb_vendor_request_large_buff(rt2x00dev, USB_MULTI_WRITE,
317 USB_VENDOR_REQUEST_OUT, reg,
318 &key_entry,
319 sizeof(key_entry),
320 timeout);
321
322 /*
323 * The cipher types are stored over 2 registers.
324 * bssidx 0 and 1 keys are stored in SEC_CSR1 and
325 * bssidx 1 and 2 keys are stored in SEC_CSR5.
326 * Using the correct defines correctly will cause overhead,
327 * so just calculate the correct offset.
328 */
329 if (key->hw_key_idx < 8) {
330 field.bit_offset = (3 * key->hw_key_idx);
331 field.bit_mask = 0x7 << field.bit_offset;
332
0f829b1d 333 rt2x00usb_register_read(rt2x00dev, SEC_CSR1, &reg);
906c110f 334 rt2x00_set_field32(&reg, field, crypto->cipher);
0f829b1d 335 rt2x00usb_register_write(rt2x00dev, SEC_CSR1, reg);
906c110f
ID		 336 } else {
337 field.bit_offset = (3 * (key->hw_key_idx - 8));
338 field.bit_mask = 0x7 << field.bit_offset;
339
0f829b1d 340 rt2x00usb_register_read(rt2x00dev, SEC_CSR5, &reg);
906c110f 341 rt2x00_set_field32(&reg, field, crypto->cipher);
0f829b1d 342 rt2x00usb_register_write(rt2x00dev, SEC_CSR5, reg);
906c110f
ID		 343 }
344
345 /*
346 * The driver does not support the IV/EIV generation
347 * in hardware. However it doesn't support the IV/EIV
348 * inside the ieee80211 frame either, but requires it
349 * to be provided seperately for the descriptor.
350 * rt2x00lib will cut the IV/EIV data out of all frames
351 * given to us by mac80211, but we must tell mac80211
352 * to generate the IV/EIV data.
353 */
354 key->flags |= IEEE80211_KEY_FLAG_GENERATE_IV;
355 }
356
357 /*
358 * SEC_CSR0 contains only single-bit fields to indicate
359 * a particular key is valid. Because using the FIELD32()
360 * defines directly will cause a lot of overhead we use
361 * a calculation to determine the correct bit directly.
362 */
363 mask = 1 << key->hw_key_idx;
364
0f829b1d 365 rt2x00usb_register_read(rt2x00dev, SEC_CSR0, &reg);
906c110f
ID		 366 if (crypto->cmd == SET_KEY)
367 reg |= mask;
368 else if (crypto->cmd == DISABLE_KEY)
369 reg &= ~mask;
0f829b1d 370 rt2x00usb_register_write(rt2x00dev, SEC_CSR0, reg);
906c110f
ID		 371
372 return 0;
373}
374
375static int rt73usb_config_pairwise_key(struct rt2x00_dev *rt2x00dev,
376 struct rt2x00lib_crypto *crypto,
377 struct ieee80211_key_conf *key)
378{
379 struct hw_pairwise_ta_entry addr_entry;
380 struct hw_key_entry key_entry;
381 int timeout;
382 u32 mask;
383 u32 reg;
384
385 if (crypto->cmd == SET_KEY) {
386 /*
387 * rt2x00lib can't determine the correct free
388 * key_idx for pairwise keys. We have 2 registers
389 * with key valid bits. The goal is simple, read
390 * the first register, if that is full move to
391 * the next register.
392 * When both registers are full, we drop the key,
393 * otherwise we use the first invalid entry.
394 */
0f829b1d 395 rt2x00usb_register_read(rt2x00dev, SEC_CSR2, &reg);
906c110f
ID		 396 if (reg && reg == ~0) {
397 key->hw_key_idx = 32;
0f829b1d 398 rt2x00usb_register_read(rt2x00dev, SEC_CSR3, &reg);
906c110f
ID		 399 if (reg && reg == ~0)
400 return -ENOSPC;
401 }
402
acaf908d 403 key->hw_key_idx += reg ? ffz(reg) : 0;
906c110f
ID		 404
405 /*
406 * Upload key to hardware
407 */
408 memcpy(key_entry.key, crypto->key,
409 sizeof(key_entry.key));
410 memcpy(key_entry.tx_mic, crypto->tx_mic,
411 sizeof(key_entry.tx_mic));
412 memcpy(key_entry.rx_mic, crypto->rx_mic,
413 sizeof(key_entry.rx_mic));
414
415 reg = PAIRWISE_KEY_ENTRY(key->hw_key_idx);
416 timeout = REGISTER_TIMEOUT32(sizeof(key_entry));
417 rt2x00usb_vendor_request_large_buff(rt2x00dev, USB_MULTI_WRITE,
418 USB_VENDOR_REQUEST_OUT, reg,
419 &key_entry,
420 sizeof(key_entry),
421 timeout);
422
423 /*
424 * Send the address and cipher type to the hardware register.
425 * This data fits within the CSR cache size, so we can use
0f829b1d 426 * rt2x00usb_register_multiwrite() directly.
906c110f
ID		 427 */
428 memset(&addr_entry, 0, sizeof(addr_entry));
429 memcpy(&addr_entry, crypto->address, ETH_ALEN);
430 addr_entry.cipher = crypto->cipher;
431
432 reg = PAIRWISE_TA_ENTRY(key->hw_key_idx);
0f829b1d 433 rt2x00usb_register_multiwrite(rt2x00dev, reg,
906c110f
ID		 434 &addr_entry, sizeof(addr_entry));
435
436 /*
437 * Enable pairwise lookup table for given BSS idx,
438 * without this received frames will not be decrypted
439 * by the hardware.
440 */
0f829b1d 441 rt2x00usb_register_read(rt2x00dev, SEC_CSR4, &reg);
906c110f 442 reg |= (1 << crypto->bssidx);
0f829b1d 443 rt2x00usb_register_write(rt2x00dev, SEC_CSR4, reg);
906c110f
ID		 444
445 /*
446 * The driver does not support the IV/EIV generation
447 * in hardware. However it doesn't support the IV/EIV
448 * inside the ieee80211 frame either, but requires it
449 * to be provided seperately for the descriptor.
450 * rt2x00lib will cut the IV/EIV data out of all frames
451 * given to us by mac80211, but we must tell mac80211
452 * to generate the IV/EIV data.
453 */
454 key->flags |= IEEE80211_KEY_FLAG_GENERATE_IV;
455 }
456
457 /*
458 * SEC_CSR2 and SEC_CSR3 contain only single-bit fields to indicate
459 * a particular key is valid. Because using the FIELD32()
460 * defines directly will cause a lot of overhead we use
461 * a calculation to determine the correct bit directly.
462 */
463 if (key->hw_key_idx < 32) {
464 mask = 1 << key->hw_key_idx;
465
0f829b1d 466 rt2x00usb_register_read(rt2x00dev, SEC_CSR2, &reg);
906c110f
ID		 467 if (crypto->cmd == SET_KEY)
468 reg |= mask;
469 else if (crypto->cmd == DISABLE_KEY)
470 reg &= ~mask;
0f829b1d 471 rt2x00usb_register_write(rt2x00dev, SEC_CSR2, reg);
906c110f
ID		 472 } else {
473 mask = 1 << (key->hw_key_idx - 32);
474
0f829b1d 475 rt2x00usb_register_read(rt2x00dev, SEC_CSR3, &reg);
906c110f
ID		 476 if (crypto->cmd == SET_KEY)
477 reg |= mask;
478 else if (crypto->cmd == DISABLE_KEY)
479 reg &= ~mask;
0f829b1d 480 rt2x00usb_register_write(rt2x00dev, SEC_CSR3, reg);
906c110f
ID		 481 }
482
483 return 0;
484}
485
3a643d24
ID		 486static void rt73usb_config_filter(struct rt2x00_dev *rt2x00dev,
487 const unsigned int filter_flags)
488{
489 u32 reg;
490
491 /*
492 * Start configuration steps.
493 * Note that the version error will always be dropped
494 * and broadcast frames will always be accepted since
495 * there is no filter for it at this time.
496 */
0f829b1d 497 rt2x00usb_register_read(rt2x00dev, TXRX_CSR0, &reg);
3a643d24
ID		 498 rt2x00_set_field32(&reg, TXRX_CSR0_DROP_CRC,
499 !(filter_flags & FIF_FCSFAIL));
500 rt2x00_set_field32(&reg, TXRX_CSR0_DROP_PHYSICAL,
501 !(filter_flags & FIF_PLCPFAIL));
502 rt2x00_set_field32(&reg, TXRX_CSR0_DROP_CONTROL,
503 !(filter_flags & FIF_CONTROL));
504 rt2x00_set_field32(&reg, TXRX_CSR0_DROP_NOT_TO_ME,
505 !(filter_flags & FIF_PROMISC_IN_BSS));
506 rt2x00_set_field32(&reg, TXRX_CSR0_DROP_TO_DS,
e0b005fa
ID		 507 !(filter_flags & FIF_PROMISC_IN_BSS) &&
508 !rt2x00dev->intf_ap_count);
3a643d24
ID		 509 rt2x00_set_field32(&reg, TXRX_CSR0_DROP_VERSION_ERROR, 1);
510 rt2x00_set_field32(&reg, TXRX_CSR0_DROP_MULTICAST,
511 !(filter_flags & FIF_ALLMULTI));
512 rt2x00_set_field32(&reg, TXRX_CSR0_DROP_BROADCAST, 0);
513 rt2x00_set_field32(&reg, TXRX_CSR0_DROP_ACK_CTS,
514 !(filter_flags & FIF_CONTROL));
0f829b1d 515 rt2x00usb_register_write(rt2x00dev, TXRX_CSR0, reg);
3a643d24
ID		 516}
517
6bb40dd1
ID		 518static void rt73usb_config_intf(struct rt2x00_dev *rt2x00dev,
519 struct rt2x00_intf *intf,
520 struct rt2x00intf_conf *conf,
521 const unsigned int flags)
95ea3627 522{
6bb40dd1
ID		 523 unsigned int beacon_base;
524 u32 reg;
95ea3627 525
6bb40dd1
ID		 526 if (flags & CONFIG_UPDATE_TYPE) {
527 /*
528 * Clear current synchronisation setup.
529 * For the Beacon base registers we only need to clear
530 * the first byte since that byte contains the VALID and OWNER
531 * bits which (when set to 0) will invalidate the entire beacon.
532 */
533 beacon_base = HW_BEACON_OFFSET(intf->beacon->entry_idx);
0f829b1d 534 rt2x00usb_register_write(rt2x00dev, beacon_base, 0);
95ea3627 535
6bb40dd1
ID		 536 /*
537 * Enable synchronisation.
538 */
0f829b1d 539 rt2x00usb_register_read(rt2x00dev, TXRX_CSR9, &reg);
fd3c91c5 540 rt2x00_set_field32(&reg, TXRX_CSR9_TSF_TICKING, 1);
6bb40dd1 541 rt2x00_set_field32(&reg, TXRX_CSR9_TSF_SYNC, conf->sync);
fd3c91c5 542 rt2x00_set_field32(&reg, TXRX_CSR9_TBTT_ENABLE, 1);
0f829b1d 543 rt2x00usb_register_write(rt2x00dev, TXRX_CSR9, reg);
6bb40dd1 544 }
95ea3627 545
6bb40dd1
ID		 546 if (flags & CONFIG_UPDATE_MAC) {
547 reg = le32_to_cpu(conf->mac[1]);
548 rt2x00_set_field32(&reg, MAC_CSR3_UNICAST_TO_ME_MASK, 0xff);
549 conf->mac[1] = cpu_to_le32(reg);
95ea3627 550
0f829b1d 551 rt2x00usb_register_multiwrite(rt2x00dev, MAC_CSR2,
6bb40dd1
ID		 552 conf->mac, sizeof(conf->mac));
553 }
95ea3627 554
6bb40dd1
ID		 555 if (flags & CONFIG_UPDATE_BSSID) {
556 reg = le32_to_cpu(conf->bssid[1]);
557 rt2x00_set_field32(&reg, MAC_CSR5_BSS_ID_MASK, 3);
558 conf->bssid[1] = cpu_to_le32(reg);
95ea3627 559
0f829b1d 560 rt2x00usb_register_multiwrite(rt2x00dev, MAC_CSR4,
6bb40dd1
ID		 561 conf->bssid, sizeof(conf->bssid));
562 }
95ea3627
ID		 563}
564
3a643d24
ID		 565static void rt73usb_config_erp(struct rt2x00_dev *rt2x00dev,
566 struct rt2x00lib_erp *erp)
95ea3627 567{
95ea3627 568 u32 reg;
95ea3627 569
0f829b1d 570 rt2x00usb_register_read(rt2x00dev, TXRX_CSR0, &reg);
72810379 571 rt2x00_set_field32(&reg, TXRX_CSR0_RX_ACK_TIMEOUT, erp->ack_timeout);
0f829b1d 572 rt2x00usb_register_write(rt2x00dev, TXRX_CSR0, reg);
95ea3627 573
0f829b1d 574 rt2x00usb_register_read(rt2x00dev, TXRX_CSR4, &reg);
4f5af6eb 575 rt2x00_set_field32(&reg, TXRX_CSR4_AUTORESPOND_PREAMBLE,
72810379 576 !!erp->short_preamble);
0f829b1d 577 rt2x00usb_register_write(rt2x00dev, TXRX_CSR4, reg);
95ea3627 578
0f829b1d 579 rt2x00usb_register_write(rt2x00dev, TXRX_CSR5, erp->basic_rates);
95ea3627 580
0f829b1d 581 rt2x00usb_register_read(rt2x00dev, MAC_CSR9, &reg);
e4ea1c40 582 rt2x00_set_field32(&reg, MAC_CSR9_SLOT_TIME, erp->slot_time);
0f829b1d 583 rt2x00usb_register_write(rt2x00dev, MAC_CSR9, reg);
95ea3627 584
0f829b1d 585 rt2x00usb_register_read(rt2x00dev, MAC_CSR8, &reg);
e4ea1c40
ID		 586 rt2x00_set_field32(&reg, MAC_CSR8_SIFS, erp->sifs);
587 rt2x00_set_field32(&reg, MAC_CSR8_SIFS_AFTER_RX_OFDM, 3);
588 rt2x00_set_field32(&reg, MAC_CSR8_EIFS, erp->eifs);
0f829b1d 589 rt2x00usb_register_write(rt2x00dev, MAC_CSR8, reg);
95ea3627
ID		 590}
591
592static void rt73usb_config_antenna_5x(struct rt2x00_dev *rt2x00dev,
addc81bd 593 struct antenna_setup *ant)
95ea3627
ID		 594{
595 u8 r3;
596 u8 r4;
597 u8 r77;
2676c94d 598 u8 temp;
95ea3627
ID		 599
600 rt73usb_bbp_read(rt2x00dev, 3, &r3);
601 rt73usb_bbp_read(rt2x00dev, 4, &r4);
602 rt73usb_bbp_read(rt2x00dev, 77, &r77);
603
604 rt2x00_set_field8(&r3, BBP_R3_SMART_MODE, 0);
605
e4cd2ff8
ID		 606 /*
607 * Configure the RX antenna.
608 */
addc81bd 609 switch (ant->rx) {
95ea3627 610 case ANTENNA_HW_DIVERSITY:
2676c94d
MN		 611 rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA_CONTROL, 2);
612 temp = !test_bit(CONFIG_FRAME_TYPE, &rt2x00dev->flags)
8318d78a 613 && (rt2x00dev->curr_band != IEEE80211_BAND_5GHZ);
2676c94d 614 rt2x00_set_field8(&r4, BBP_R4_RX_FRAME_END, temp);
95ea3627
ID		 615 break;
616 case ANTENNA_A:
2676c94d 617 rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA_CONTROL, 1);
95ea3627 618 rt2x00_set_field8(&r4, BBP_R4_RX_FRAME_END, 0);
8318d78a 619 if (rt2x00dev->curr_band == IEEE80211_BAND_5GHZ)
2676c94d
MN		 620 rt2x00_set_field8(&r77, BBP_R77_RX_ANTENNA, 0);
621 else
622 rt2x00_set_field8(&r77, BBP_R77_RX_ANTENNA, 3);
95ea3627
ID		 623 break;
624 case ANTENNA_B:
a4fe07d9 625 default:
2676c94d 626 rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA_CONTROL, 1);
95ea3627 627 rt2x00_set_field8(&r4, BBP_R4_RX_FRAME_END, 0);
8318d78a 628 if (rt2x00dev->curr_band == IEEE80211_BAND_5GHZ)
2676c94d
MN		 629 rt2x00_set_field8(&r77, BBP_R77_RX_ANTENNA, 3);
630 else
631 rt2x00_set_field8(&r77, BBP_R77_RX_ANTENNA, 0);
95ea3627
ID		 632 break;
633 }
634
635 rt73usb_bbp_write(rt2x00dev, 77, r77);
636 rt73usb_bbp_write(rt2x00dev, 3, r3);
637 rt73usb_bbp_write(rt2x00dev, 4, r4);
638}
639
640static void rt73usb_config_antenna_2x(struct rt2x00_dev *rt2x00dev,
addc81bd 641 struct antenna_setup *ant)
95ea3627
ID		 642{
643 u8 r3;
644 u8 r4;
645 u8 r77;
646
647 rt73usb_bbp_read(rt2x00dev, 3, &r3);
648 rt73usb_bbp_read(rt2x00dev, 4, &r4);
649 rt73usb_bbp_read(rt2x00dev, 77, &r77);
650
651 rt2x00_set_field8(&r3, BBP_R3_SMART_MODE, 0);
652 rt2x00_set_field8(&r4, BBP_R4_RX_FRAME_END,
653 !test_bit(CONFIG_FRAME_TYPE, &rt2x00dev->flags));
654
e4cd2ff8
ID		 655 /*
656 * Configure the RX antenna.
657 */
addc81bd 658 switch (ant->rx) {
95ea3627 659 case ANTENNA_HW_DIVERSITY:
2676c94d 660 rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA_CONTROL, 2);
95ea3627
ID		 661 break;
662 case ANTENNA_A:
2676c94d
MN		 663 rt2x00_set_field8(&r77, BBP_R77_RX_ANTENNA, 3);
664 rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA_CONTROL, 1);
95ea3627
ID		 665 break;
666 case ANTENNA_B:
a4fe07d9 667 default:
2676c94d
MN		 668 rt2x00_set_field8(&r77, BBP_R77_RX_ANTENNA, 0);
669 rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA_CONTROL, 1);
95ea3627
ID		 670 break;
671 }
672
673 rt73usb_bbp_write(rt2x00dev, 77, r77);
674 rt73usb_bbp_write(rt2x00dev, 3, r3);
675 rt73usb_bbp_write(rt2x00dev, 4, r4);
676}
677
678struct antenna_sel {
679 u8 word;
680 /*
681 * value[0] -> non-LNA
682 * value[1] -> LNA
683 */
684 u8 value[2];
685};
686
687static const struct antenna_sel antenna_sel_a[] = {
688 { 96, { 0x58, 0x78 } },
689 { 104, { 0x38, 0x48 } },
690 { 75, { 0xfe, 0x80 } },
691 { 86, { 0xfe, 0x80 } },
692 { 88, { 0xfe, 0x80 } },
693 { 35, { 0x60, 0x60 } },
694 { 97, { 0x58, 0x58 } },
695 { 98, { 0x58, 0x58 } },
696};
697
698static const struct antenna_sel antenna_sel_bg[] = {
699 { 96, { 0x48, 0x68 } },
700 { 104, { 0x2c, 0x3c } },
701 { 75, { 0xfe, 0x80 } },
702 { 86, { 0xfe, 0x80 } },
703 { 88, { 0xfe, 0x80 } },
704 { 35, { 0x50, 0x50 } },
705 { 97, { 0x48, 0x48 } },
706 { 98, { 0x48, 0x48 } },
707};
708
e4ea1c40
ID		 709static void rt73usb_config_ant(struct rt2x00_dev *rt2x00dev,
710 struct antenna_setup *ant)
95ea3627
ID		 711{
712 const struct antenna_sel *sel;
713 unsigned int lna;
714 unsigned int i;
715 u32 reg;
716
a4fe07d9
ID		 717 /*
718 * We should never come here because rt2x00lib is supposed
719 * to catch this and send us the correct antenna explicitely.
720 */
721 BUG_ON(ant->rx == ANTENNA_SW_DIVERSITY ||
722 ant->tx == ANTENNA_SW_DIVERSITY);
723
8318d78a 724 if (rt2x00dev->curr_band == IEEE80211_BAND_5GHZ) {
95ea3627
ID		 725 sel = antenna_sel_a;
726 lna = test_bit(CONFIG_EXTERNAL_LNA_A, &rt2x00dev->flags);
95ea3627
ID		 727 } else {
728 sel = antenna_sel_bg;
729 lna = test_bit(CONFIG_EXTERNAL_LNA_BG, &rt2x00dev->flags);
95ea3627
ID		 730 }
731
2676c94d
MN		 732 for (i = 0; i < ARRAY_SIZE(antenna_sel_a); i++)
733 rt73usb_bbp_write(rt2x00dev, sel[i].word, sel[i].value[lna]);
734
0f829b1d 735 rt2x00usb_register_read(rt2x00dev, PHY_CSR0, &reg);
2676c94d 736
ddc827f9 737 rt2x00_set_field32(&reg, PHY_CSR0_PA_PE_BG,
8318d78a 738 (rt2x00dev->curr_band == IEEE80211_BAND_2GHZ));
ddc827f9 739 rt2x00_set_field32(&reg, PHY_CSR0_PA_PE_A,
8318d78a 740 (rt2x00dev->curr_band == IEEE80211_BAND_5GHZ));
ddc827f9 741
0f829b1d 742 rt2x00usb_register_write(rt2x00dev, PHY_CSR0, reg);
95ea3627
ID		 743
744 if (rt2x00_rf(&rt2x00dev->chip, RF5226) ||
745 rt2x00_rf(&rt2x00dev->chip, RF5225))
addc81bd 746 rt73usb_config_antenna_5x(rt2x00dev, ant);
95ea3627
ID		 747 else if (rt2x00_rf(&rt2x00dev->chip, RF2528) ||
748 rt2x00_rf(&rt2x00dev->chip, RF2527))
addc81bd 749 rt73usb_config_antenna_2x(rt2x00dev, ant);
95ea3627
ID		 750}
751
e4ea1c40 752static void rt73usb_config_lna_gain(struct rt2x00_dev *rt2x00dev,
5c58ee51 753 struct rt2x00lib_conf *libconf)
e4ea1c40
ID		 754{
755 u16 eeprom;
756 short lna_gain = 0;
757
758 if (libconf->conf->channel->band == IEEE80211_BAND_2GHZ) {
759 if (test_bit(CONFIG_EXTERNAL_LNA_BG, &rt2x00dev->flags))
760 lna_gain += 14;
761
762 rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_OFFSET_BG, &eeprom);
763 lna_gain -= rt2x00_get_field16(eeprom, EEPROM_RSSI_OFFSET_BG_1);
764 } else {
765 rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_OFFSET_A, &eeprom);
766 lna_gain -= rt2x00_get_field16(eeprom, EEPROM_RSSI_OFFSET_A_1);
767 }
768
769 rt2x00dev->lna_gain = lna_gain;
770}
771
772static void rt73usb_config_channel(struct rt2x00_dev *rt2x00dev,
773 struct rf_channel *rf, const int txpower)
774{
775 u8 r3;
776 u8 r94;
777 u8 smart;
778
779 rt2x00_set_field32(&rf->rf3, RF3_TXPOWER, TXPOWER_TO_DEV(txpower));
780 rt2x00_set_field32(&rf->rf4, RF4_FREQ_OFFSET, rt2x00dev->freq_offset);
781
782 smart = !(rt2x00_rf(&rt2x00dev->chip, RF5225) ||
783 rt2x00_rf(&rt2x00dev->chip, RF2527));
784
785 rt73usb_bbp_read(rt2x00dev, 3, &r3);
786 rt2x00_set_field8(&r3, BBP_R3_SMART_MODE, smart);
787 rt73usb_bbp_write(rt2x00dev, 3, r3);
788
789 r94 = 6;
790 if (txpower > MAX_TXPOWER && txpower <= (MAX_TXPOWER + r94))
791 r94 += txpower - MAX_TXPOWER;
792 else if (txpower < MIN_TXPOWER && txpower >= (MIN_TXPOWER - r94))
793 r94 += txpower;
794 rt73usb_bbp_write(rt2x00dev, 94, r94);
795
796 rt73usb_rf_write(rt2x00dev, 1, rf->rf1);
797 rt73usb_rf_write(rt2x00dev, 2, rf->rf2);
798 rt73usb_rf_write(rt2x00dev, 3, rf->rf3 & ~0x00000004);
799 rt73usb_rf_write(rt2x00dev, 4, rf->rf4);
800
801 rt73usb_rf_write(rt2x00dev, 1, rf->rf1);
802 rt73usb_rf_write(rt2x00dev, 2, rf->rf2);
803 rt73usb_rf_write(rt2x00dev, 3, rf->rf3 | 0x00000004);
804 rt73usb_rf_write(rt2x00dev, 4, rf->rf4);
805
806 rt73usb_rf_write(rt2x00dev, 1, rf->rf1);
807 rt73usb_rf_write(rt2x00dev, 2, rf->rf2);
808 rt73usb_rf_write(rt2x00dev, 3, rf->rf3 & ~0x00000004);
809 rt73usb_rf_write(rt2x00dev, 4, rf->rf4);
810
811 udelay(10);
812}
813
814static void rt73usb_config_txpower(struct rt2x00_dev *rt2x00dev,
815 const int txpower)
816{
817 struct rf_channel rf;
818
819 rt2x00_rf_read(rt2x00dev, 1, &rf.rf1);
820 rt2x00_rf_read(rt2x00dev, 2, &rf.rf2);
821 rt2x00_rf_read(rt2x00dev, 3, &rf.rf3);
822 rt2x00_rf_read(rt2x00dev, 4, &rf.rf4);
823
824 rt73usb_config_channel(rt2x00dev, &rf, txpower);
825}
826
827static void rt73usb_config_retry_limit(struct rt2x00_dev *rt2x00dev,
828 struct rt2x00lib_conf *libconf)
95ea3627
ID		 829{
830 u32 reg;
831
0f829b1d 832 rt2x00usb_register_read(rt2x00dev, TXRX_CSR4, &reg);
e4ea1c40
ID		 833 rt2x00_set_field32(&reg, TXRX_CSR4_LONG_RETRY_LIMIT,
834 libconf->conf->long_frame_max_tx_count);
835 rt2x00_set_field32(&reg, TXRX_CSR4_SHORT_RETRY_LIMIT,
836 libconf->conf->short_frame_max_tx_count);
0f829b1d 837 rt2x00usb_register_write(rt2x00dev, TXRX_CSR4, reg);
e4ea1c40 838}
95ea3627 839
e4ea1c40
ID		 840static void rt73usb_config_duration(struct rt2x00_dev *rt2x00dev,
841 struct rt2x00lib_conf *libconf)
842{
843 u32 reg;
95ea3627 844
0f829b1d 845 rt2x00usb_register_read(rt2x00dev, TXRX_CSR0, &reg);
95ea3627 846 rt2x00_set_field32(&reg, TXRX_CSR0_TSF_OFFSET, IEEE80211_HEADER);
0f829b1d 847 rt2x00usb_register_write(rt2x00dev, TXRX_CSR0, reg);
95ea3627 848
0f829b1d 849 rt2x00usb_register_read(rt2x00dev, TXRX_CSR4, &reg);
95ea3627 850 rt2x00_set_field32(&reg, TXRX_CSR4_AUTORESPOND_ENABLE, 1);
0f829b1d 851 rt2x00usb_register_write(rt2x00dev, TXRX_CSR4, reg);
95ea3627 852
0f829b1d 853 rt2x00usb_register_read(rt2x00dev, TXRX_CSR9, &reg);
5c58ee51
ID		 854 rt2x00_set_field32(&reg, TXRX_CSR9_BEACON_INTERVAL,
855 libconf->conf->beacon_int * 16);
0f829b1d 856 rt2x00usb_register_write(rt2x00dev, TXRX_CSR9, reg);
95ea3627
ID		 857}
858
7d7f19cc
ID		 859static void rt73usb_config_ps(struct rt2x00_dev *rt2x00dev,
860 struct rt2x00lib_conf *libconf)
861{
862 enum dev_state state =
863 (libconf->conf->flags & IEEE80211_CONF_PS) ?
864 STATE_SLEEP : STATE_AWAKE;
865 u32 reg;
866
867 if (state == STATE_SLEEP) {
868 rt2x00usb_register_read(rt2x00dev, MAC_CSR11, &reg);
869 rt2x00_set_field32(&reg, MAC_CSR11_DELAY_AFTER_TBCN,
870 libconf->conf->beacon_int - 10);
871 rt2x00_set_field32(&reg, MAC_CSR11_TBCN_BEFORE_WAKEUP,
872 libconf->conf->listen_interval - 1);
873 rt2x00_set_field32(&reg, MAC_CSR11_WAKEUP_LATENCY, 5);
874
875 /* We must first disable autowake before it can be enabled */
876 rt2x00_set_field32(&reg, MAC_CSR11_AUTOWAKE, 0);
877 rt2x00usb_register_write(rt2x00dev, MAC_CSR11, reg);
878
879 rt2x00_set_field32(&reg, MAC_CSR11_AUTOWAKE, 1);
880 rt2x00usb_register_write(rt2x00dev, MAC_CSR11, reg);
881
882 rt2x00usb_vendor_request_sw(rt2x00dev, USB_DEVICE_MODE, 0,
883 USB_MODE_SLEEP, REGISTER_TIMEOUT);
884 } else {
885 rt2x00usb_vendor_request_sw(rt2x00dev, USB_DEVICE_MODE, 0,
886 USB_MODE_WAKEUP, REGISTER_TIMEOUT);
887
888 rt2x00usb_register_read(rt2x00dev, MAC_CSR11, &reg);
889 rt2x00_set_field32(&reg, MAC_CSR11_DELAY_AFTER_TBCN, 0);
890 rt2x00_set_field32(&reg, MAC_CSR11_TBCN_BEFORE_WAKEUP, 0);
891 rt2x00_set_field32(&reg, MAC_CSR11_AUTOWAKE, 0);
892 rt2x00_set_field32(&reg, MAC_CSR11_WAKEUP_LATENCY, 0);
893 rt2x00usb_register_write(rt2x00dev, MAC_CSR11, reg);
894 }
895}
896
95ea3627 897static void rt73usb_config(struct rt2x00_dev *rt2x00dev,
6bb40dd1
ID		 898 struct rt2x00lib_conf *libconf,
899 const unsigned int flags)
95ea3627 900{
ba2ab471
ID		 901 /* Always recalculate LNA gain before changing configuration */
902 rt73usb_config_lna_gain(rt2x00dev, libconf);
903
e4ea1c40 904 if (flags & IEEE80211_CONF_CHANGE_CHANNEL)
5c58ee51
ID		 905 rt73usb_config_channel(rt2x00dev, &libconf->rf,
906 libconf->conf->power_level);
e4ea1c40
ID		 907 if ((flags & IEEE80211_CONF_CHANGE_POWER) &&
908 !(flags & IEEE80211_CONF_CHANGE_CHANNEL))
5c58ee51 909 rt73usb_config_txpower(rt2x00dev, libconf->conf->power_level);
e4ea1c40
ID		 910 if (flags & IEEE80211_CONF_CHANGE_RETRY_LIMITS)
911 rt73usb_config_retry_limit(rt2x00dev, libconf);
912 if (flags & IEEE80211_CONF_CHANGE_BEACON_INTERVAL)
5c58ee51 913 rt73usb_config_duration(rt2x00dev, libconf);
7d7f19cc
ID		 914 if (flags & IEEE80211_CONF_CHANGE_PS)
915 rt73usb_config_ps(rt2x00dev, libconf);
95ea3627
ID		 916}
917
95ea3627
ID		 918/*
919 * Link tuning
920 */
ebcf26da
ID		 921static void rt73usb_link_stats(struct rt2x00_dev *rt2x00dev,
922 struct link_qual *qual)
95ea3627
ID		 923{
924 u32 reg;
925
926 /*
927 * Update FCS error count from register.
928 */
0f829b1d 929 rt2x00usb_register_read(rt2x00dev, STA_CSR0, &reg);
ebcf26da 930 qual->rx_failed = rt2x00_get_field32(reg, STA_CSR0_FCS_ERROR);
95ea3627
ID		 931
932 /*
933 * Update False CCA count from register.
934 */
0f829b1d 935 rt2x00usb_register_read(rt2x00dev, STA_CSR1, &reg);
ebcf26da 936 qual->false_cca = rt2x00_get_field32(reg, STA_CSR1_FALSE_CCA_ERROR);
95ea3627
ID		 937}
938
5352ff65
ID		 939static inline void rt73usb_set_vgc(struct rt2x00_dev *rt2x00dev,
940 struct link_qual *qual, u8 vgc_level)
eb20b4e8 941{
5352ff65 942 if (qual->vgc_level != vgc_level) {
eb20b4e8 943 rt73usb_bbp_write(rt2x00dev, 17, vgc_level);
5352ff65
ID		 944 qual->vgc_level = vgc_level;
945 qual->vgc_level_reg = vgc_level;
eb20b4e8
ID		 946 }
947}
948
5352ff65
ID		 949static void rt73usb_reset_tuner(struct rt2x00_dev *rt2x00dev,
950 struct link_qual *qual)
95ea3627 951{
5352ff65 952 rt73usb_set_vgc(rt2x00dev, qual, 0x20);
95ea3627
ID		 953}
954
5352ff65
ID		 955static void rt73usb_link_tuner(struct rt2x00_dev *rt2x00dev,
956 struct link_qual *qual, const u32 count)
95ea3627 957{
95ea3627
ID		 958 u8 up_bound;
959 u8 low_bound;
960
95ea3627
ID		 961 /*
962 * Determine r17 bounds.
963 */
8318d78a 964 if (rt2x00dev->rx_status.band == IEEE80211_BAND_5GHZ) {
95ea3627
ID		 965 low_bound = 0x28;
966 up_bound = 0x48;
967
968 if (test_bit(CONFIG_EXTERNAL_LNA_A, &rt2x00dev->flags)) {
969 low_bound += 0x10;
970 up_bound += 0x10;
971 }
972 } else {
5352ff65 973 if (qual->rssi > -82) {
95ea3627
ID		 974 low_bound = 0x1c;
975 up_bound = 0x40;
5352ff65 976 } else if (qual->rssi > -84) {
95ea3627
ID		 977 low_bound = 0x1c;
978 up_bound = 0x20;
979 } else {
980 low_bound = 0x1c;
981 up_bound = 0x1c;
982 }
983
984 if (test_bit(CONFIG_EXTERNAL_LNA_BG, &rt2x00dev->flags)) {
985 low_bound += 0x14;
986 up_bound += 0x10;
987 }
988 }
989
6bb40dd1
ID		 990 /*
991 * If we are not associated, we should go straight to the
992 * dynamic CCA tuning.
993 */
994 if (!rt2x00dev->intf_associated)
995 goto dynamic_cca_tune;
996
95ea3627
ID		 997 /*
998 * Special big-R17 for very short distance
999 */
5352ff65
ID		 1000 if (qual->rssi > -35) {
1001 rt73usb_set_vgc(rt2x00dev, qual, 0x60);
95ea3627
ID		 1002 return;
1003 }
1004
1005 /*
1006 * Special big-R17 for short distance
1007 */
5352ff65
ID		 1008 if (qual->rssi >= -58) {
1009 rt73usb_set_vgc(rt2x00dev, qual, up_bound);
95ea3627
ID		 1010 return;
1011 }
1012
1013 /*
1014 * Special big-R17 for middle-short distance
1015 */
5352ff65
ID		 1016 if (qual->rssi >= -66) {
1017 rt73usb_set_vgc(rt2x00dev, qual, low_bound + 0x10);
95ea3627
ID		 1018 return;
1019 }
1020
1021 /*
1022 * Special mid-R17 for middle distance
1023 */
5352ff65
ID		 1024 if (qual->rssi >= -74) {
1025 rt73usb_set_vgc(rt2x00dev, qual, low_bound + 0x08);
95ea3627
ID		 1026 return;
1027 }
1028
1029 /*
1030 * Special case: Change up_bound based on the rssi.
1031 * Lower up_bound when rssi is weaker then -74 dBm.
1032 */
5352ff65 1033 up_bound -= 2 * (-74 - qual->rssi);
95ea3627
ID		 1034 if (low_bound > up_bound)
1035 up_bound = low_bound;
1036
5352ff65
ID		 1037 if (qual->vgc_level > up_bound) {
1038 rt73usb_set_vgc(rt2x00dev, qual, up_bound);
95ea3627
ID		 1039 return;
1040 }
1041
6bb40dd1
ID		 1042dynamic_cca_tune:
1043
95ea3627
ID		 1044 /*
1045 * r17 does not yet exceed upper limit, continue and base
1046 * the r17 tuning on the false CCA count.
1047 */
5352ff65
ID		 1048 if ((qual->false_cca > 512) && (qual->vgc_level < up_bound))
1049 rt73usb_set_vgc(rt2x00dev, qual,
1050 min_t(u8, qual->vgc_level + 4, up_bound));
1051 else if ((qual->false_cca < 100) && (qual->vgc_level > low_bound))
1052 rt73usb_set_vgc(rt2x00dev, qual,
1053 max_t(u8, qual->vgc_level - 4, low_bound));
95ea3627
ID		 1054}
1055
1056/*
a7f3a06c 1057 * Firmware functions
95ea3627
ID		 1058 */
1059static char *rt73usb_get_firmware_name(struct rt2x00_dev *rt2x00dev)
1060{
1061 return FIRMWARE_RT2571;
1062}
1063
f160ebcb 1064static u16 rt73usb_get_firmware_crc(const void *data, const size_t len)
a7f3a06c
ID		 1065{
1066 u16 crc;
1067
1068 /*
1069 * Use the crc itu-t algorithm.
1070 * The last 2 bytes in the firmware array are the crc checksum itself,
1071 * this means that we should never pass those 2 bytes to the crc
1072 * algorithm.
1073 */
1074 crc = crc_itu_t(0, data, len - 2);
1075 crc = crc_itu_t_byte(crc, 0);
1076 crc = crc_itu_t_byte(crc, 0);
1077
1078 return crc;
1079}
1080
f160ebcb 1081static int rt73usb_load_firmware(struct rt2x00_dev *rt2x00dev, const void *data,
95ea3627
ID		 1082 const size_t len)
1083{
1084 unsigned int i;
1085 int status;
1086 u32 reg;
95ea3627 1087
9752a7bd
ID		 1088 if (len != 2048) {
1089 ERROR(rt2x00dev, "Invalid firmware file length (len=%zu)\n", len);
1090 return -ENOENT;
1091 }
1092
95ea3627
ID		 1093 /*
1094 * Wait for stable hardware.
1095 */
1096 for (i = 0; i < 100; i++) {
0f829b1d 1097 rt2x00usb_register_read(rt2x00dev, MAC_CSR0, &reg);
95ea3627
ID		 1098 if (reg)
1099 break;
1100 msleep(1);
1101 }
1102
1103 if (!reg) {
1104 ERROR(rt2x00dev, "Unstable hardware.\n");
1105 return -EBUSY;
1106 }
1107
1108 /*
1109 * Write firmware to device.
95ea3627 1110 */
3e0c1abe
IM		 1111 rt2x00usb_vendor_request_large_buff(rt2x00dev, USB_MULTI_WRITE,
1112 USB_VENDOR_REQUEST_OUT,
1113 FIRMWARE_IMAGE_BASE,
1114 data, len,
1115 REGISTER_TIMEOUT32(len));
95ea3627
ID		 1116
1117 /*
1118 * Send firmware request to device to load firmware,
1119 * we need to specify a long timeout time.
1120 */
1121 status = rt2x00usb_vendor_request_sw(rt2x00dev, USB_DEVICE_MODE,
3b640f21 1122 0, USB_MODE_FIRMWARE,
95ea3627
ID		 1123 REGISTER_TIMEOUT_FIRMWARE);
1124 if (status < 0) {
1125 ERROR(rt2x00dev, "Failed to write Firmware to device.\n");
1126 return status;
1127 }
1128
95ea3627
ID		 1129 return 0;
1130}
1131
a7f3a06c
ID		 1132/*
1133 * Initialization functions.
1134 */
95ea3627
ID		 1135static int rt73usb_init_registers(struct rt2x00_dev *rt2x00dev)
1136{
1137 u32 reg;
1138
0f829b1d 1139 rt2x00usb_register_read(rt2x00dev, TXRX_CSR0, &reg);
95ea3627
ID		 1140 rt2x00_set_field32(&reg, TXRX_CSR0_AUTO_TX_SEQ, 1);
1141 rt2x00_set_field32(&reg, TXRX_CSR0_DISABLE_RX, 0);
1142 rt2x00_set_field32(&reg, TXRX_CSR0_TX_WITHOUT_WAITING, 0);
0f829b1d 1143 rt2x00usb_register_write(rt2x00dev, TXRX_CSR0, reg);
95ea3627 1144
0f829b1d 1145 rt2x00usb_register_read(rt2x00dev, TXRX_CSR1, &reg);
95ea3627
ID		 1146 rt2x00_set_field32(&reg, TXRX_CSR1_BBP_ID0, 47); /* CCK Signal */
1147 rt2x00_set_field32(&reg, TXRX_CSR1_BBP_ID0_VALID, 1);
1148 rt2x00_set_field32(&reg, TXRX_CSR1_BBP_ID1, 30); /* Rssi */
1149 rt2x00_set_field32(&reg, TXRX_CSR1_BBP_ID1_VALID, 1);
1150 rt2x00_set_field32(&reg, TXRX_CSR1_BBP_ID2, 42); /* OFDM Rate */
1151 rt2x00_set_field32(&reg, TXRX_CSR1_BBP_ID2_VALID, 1);
1152 rt2x00_set_field32(&reg, TXRX_CSR1_BBP_ID3, 30); /* Rssi */
1153 rt2x00_set_field32(&reg, TXRX_CSR1_BBP_ID3_VALID, 1);
0f829b1d 1154 rt2x00usb_register_write(rt2x00dev, TXRX_CSR1, reg);
95ea3627
ID		 1155
1156 /*
1157 * CCK TXD BBP registers
1158 */
0f829b1d 1159 rt2x00usb_register_read(rt2x00dev, TXRX_CSR2, &reg);
95ea3627
ID		 1160 rt2x00_set_field32(&reg, TXRX_CSR2_BBP_ID0, 13);
1161 rt2x00_set_field32(&reg, TXRX_CSR2_BBP_ID0_VALID, 1);
1162 rt2x00_set_field32(&reg, TXRX_CSR2_BBP_ID1, 12);
1163 rt2x00_set_field32(&reg, TXRX_CSR2_BBP_ID1_VALID, 1);
1164 rt2x00_set_field32(&reg, TXRX_CSR2_BBP_ID2, 11);
1165 rt2x00_set_field32(&reg, TXRX_CSR2_BBP_ID2_VALID, 1);
1166 rt2x00_set_field32(&reg, TXRX_CSR2_BBP_ID3, 10);
1167 rt2x00_set_field32(&reg, TXRX_CSR2_BBP_ID3_VALID, 1);
0f829b1d 1168 rt2x00usb_register_write(rt2x00dev, TXRX_CSR2, reg);
95ea3627
ID		 1169
1170 /*
1171 * OFDM TXD BBP registers
1172 */
0f829b1d 1173 rt2x00usb_register_read(rt2x00dev, TXRX_CSR3, &reg);
95ea3627
ID		 1174 rt2x00_set_field32(&reg, TXRX_CSR3_BBP_ID0, 7);
1175 rt2x00_set_field32(&reg, TXRX_CSR3_BBP_ID0_VALID, 1);
1176 rt2x00_set_field32(&reg, TXRX_CSR3_BBP_ID1, 6);
1177 rt2x00_set_field32(&reg, TXRX_CSR3_BBP_ID1_VALID, 1);
1178 rt2x00_set_field32(&reg, TXRX_CSR3_BBP_ID2, 5);
1179 rt2x00_set_field32(&reg, TXRX_CSR3_BBP_ID2_VALID, 1);
0f829b1d 1180 rt2x00usb_register_write(rt2x00dev, TXRX_CSR3, reg);
95ea3627 1181
0f829b1d 1182 rt2x00usb_register_read(rt2x00dev, TXRX_CSR7, &reg);
95ea3627
ID		 1183 rt2x00_set_field32(&reg, TXRX_CSR7_ACK_CTS_6MBS, 59);
1184 rt2x00_set_field32(&reg, TXRX_CSR7_ACK_CTS_9MBS, 53);
1185 rt2x00_set_field32(&reg, TXRX_CSR7_ACK_CTS_12MBS, 49);
1186 rt2x00_set_field32(&reg, TXRX_CSR7_ACK_CTS_18MBS, 46);
0f829b1d 1187 rt2x00usb_register_write(rt2x00dev, TXRX_CSR7, reg);
95ea3627 1188
0f829b1d 1189 rt2x00usb_register_read(rt2x00dev, TXRX_CSR8, &reg);
95ea3627
ID		 1190 rt2x00_set_field32(&reg, TXRX_CSR8_ACK_CTS_24MBS, 44);
1191 rt2x00_set_field32(&reg, TXRX_CSR8_ACK_CTS_36MBS, 42);
1192 rt2x00_set_field32(&reg, TXRX_CSR8_ACK_CTS_48MBS, 42);
1193 rt2x00_set_field32(&reg, TXRX_CSR8_ACK_CTS_54MBS, 42);
0f829b1d 1194 rt2x00usb_register_write(rt2x00dev, TXRX_CSR8, reg);
95ea3627 1195
0f829b1d 1196 rt2x00usb_register_read(rt2x00dev, TXRX_CSR9, &reg);
1f909162
ID		 1197 rt2x00_set_field32(&reg, TXRX_CSR9_BEACON_INTERVAL, 0);
1198 rt2x00_set_field32(&reg, TXRX_CSR9_TSF_TICKING, 0);
1199 rt2x00_set_field32(&reg, TXRX_CSR9_TSF_SYNC, 0);
1200 rt2x00_set_field32(&reg, TXRX_CSR9_TBTT_ENABLE, 0);
1201 rt2x00_set_field32(&reg, TXRX_CSR9_BEACON_GEN, 0);
1202 rt2x00_set_field32(&reg, TXRX_CSR9_TIMESTAMP_COMPENSATE, 0);
0f829b1d 1203 rt2x00usb_register_write(rt2x00dev, TXRX_CSR9, reg);
1f909162 1204
0f829b1d 1205 rt2x00usb_register_write(rt2x00dev, TXRX_CSR15, 0x0000000f);
95ea3627 1206
0f829b1d 1207 rt2x00usb_register_read(rt2x00dev, MAC_CSR6, &reg);
95ea3627 1208 rt2x00_set_field32(&reg, MAC_CSR6_MAX_FRAME_UNIT, 0xfff);
0f829b1d 1209 rt2x00usb_register_write(rt2x00dev, MAC_CSR6, reg);
95ea3627 1210
0f829b1d 1211 rt2x00usb_register_write(rt2x00dev, MAC_CSR10, 0x00000718);
95ea3627
ID		 1212
1213 if (rt2x00dev->ops->lib->set_device_state(rt2x00dev, STATE_AWAKE))
1214 return -EBUSY;
1215
0f829b1d 1216 rt2x00usb_register_write(rt2x00dev, MAC_CSR13, 0x00007f00);
95ea3627
ID		 1217
1218 /*
1219 * Invalidate all Shared Keys (SEC_CSR0),
1220 * and clear the Shared key Cipher algorithms (SEC_CSR1 & SEC_CSR5)
1221 */
0f829b1d
ID		 1222 rt2x00usb_register_write(rt2x00dev, SEC_CSR0, 0x00000000);
1223 rt2x00usb_register_write(rt2x00dev, SEC_CSR1, 0x00000000);
1224 rt2x00usb_register_write(rt2x00dev, SEC_CSR5, 0x00000000);
95ea3627
ID		 1225
1226 reg = 0x000023b0;
1227 if (rt2x00_rf(&rt2x00dev->chip, RF5225) ||
1228 rt2x00_rf(&rt2x00dev->chip, RF2527))
1229 rt2x00_set_field32(&reg, PHY_CSR1_RF_RPI, 1);
0f829b1d 1230 rt2x00usb_register_write(rt2x00dev, PHY_CSR1, reg);
95ea3627 1231
0f829b1d
ID		 1232 rt2x00usb_register_write(rt2x00dev, PHY_CSR5, 0x00040a06);
1233 rt2x00usb_register_write(rt2x00dev, PHY_CSR6, 0x00080606);
1234 rt2x00usb_register_write(rt2x00dev, PHY_CSR7, 0x00000408);
95ea3627 1235
0f829b1d 1236 rt2x00usb_register_read(rt2x00dev, MAC_CSR9, &reg);
95ea3627 1237 rt2x00_set_field32(&reg, MAC_CSR9_CW_SELECT, 0);
0f829b1d 1238 rt2x00usb_register_write(rt2x00dev, MAC_CSR9, reg);
95ea3627 1239
6bb40dd1
ID		 1240 /*
1241 * Clear all beacons
1242 * For the Beacon base registers we only need to clear
1243 * the first byte since that byte contains the VALID and OWNER
1244 * bits which (when set to 0) will invalidate the entire beacon.
1245 */
0f829b1d
ID		 1246 rt2x00usb_register_write(rt2x00dev, HW_BEACON_BASE0, 0);
1247 rt2x00usb_register_write(rt2x00dev, HW_BEACON_BASE1, 0);
1248 rt2x00usb_register_write(rt2x00dev, HW_BEACON_BASE2, 0);
1249 rt2x00usb_register_write(rt2x00dev, HW_BEACON_BASE3, 0);
6bb40dd1 1250
95ea3627
ID		 1251 /*
1252 * We must clear the error counters.
1253 * These registers are cleared on read,
1254 * so we may pass a useless variable to store the value.
1255 */
0f829b1d
ID		 1256 rt2x00usb_register_read(rt2x00dev, STA_CSR0, &reg);
1257 rt2x00usb_register_read(rt2x00dev, STA_CSR1, &reg);
1258 rt2x00usb_register_read(rt2x00dev, STA_CSR2, &reg);
95ea3627
ID		 1259
1260 /*
1261 * Reset MAC and BBP registers.
1262 */
0f829b1d 1263 rt2x00usb_register_read(rt2x00dev, MAC_CSR1, &reg);
95ea3627
ID		 1264 rt2x00_set_field32(&reg, MAC_CSR1_SOFT_RESET, 1);
1265 rt2x00_set_field32(&reg, MAC_CSR1_BBP_RESET, 1);
0f829b1d 1266 rt2x00usb_register_write(rt2x00dev, MAC_CSR1, reg);
95ea3627 1267
0f829b1d 1268 rt2x00usb_register_read(rt2x00dev, MAC_CSR1, &reg);
95ea3627
ID		 1269 rt2x00_set_field32(&reg, MAC_CSR1_SOFT_RESET, 0);
1270 rt2x00_set_field32(&reg, MAC_CSR1_BBP_RESET, 0);
0f829b1d 1271 rt2x00usb_register_write(rt2x00dev, MAC_CSR1, reg);
95ea3627 1272
0f829b1d 1273 rt2x00usb_register_read(rt2x00dev, MAC_CSR1, &reg);
95ea3627 1274 rt2x00_set_field32(&reg, MAC_CSR1_HOST_READY, 1);
0f829b1d 1275 rt2x00usb_register_write(rt2x00dev, MAC_CSR1, reg);
95ea3627
ID		 1276
1277 return 0;
1278}
1279
2b08da3f 1280static int rt73usb_wait_bbp_ready(struct rt2x00_dev *rt2x00dev)
95ea3627
ID		 1281{
1282 unsigned int i;
95ea3627
ID		 1283 u8 value;
1284
1285 for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
1286 rt73usb_bbp_read(rt2x00dev, 0, &value);
1287 if ((value != 0xff) && (value != 0x00))
2b08da3f 1288 return 0;
95ea3627
ID		 1289 udelay(REGISTER_BUSY_DELAY);
1290 }
1291
1292 ERROR(rt2x00dev, "BBP register access failed, aborting.\n");
1293 return -EACCES;
2b08da3f
ID		 1294}
1295
1296static int rt73usb_init_bbp(struct rt2x00_dev *rt2x00dev)
1297{
1298 unsigned int i;
1299 u16 eeprom;
1300 u8 reg_id;
1301 u8 value;
1302
1303 if (unlikely(rt73usb_wait_bbp_ready(rt2x00dev)))
1304 return -EACCES;
95ea3627 1305
95ea3627
ID		 1306 rt73usb_bbp_write(rt2x00dev, 3, 0x80);
1307 rt73usb_bbp_write(rt2x00dev, 15, 0x30);
1308 rt73usb_bbp_write(rt2x00dev, 21, 0xc8);
1309 rt73usb_bbp_write(rt2x00dev, 22, 0x38);
1310 rt73usb_bbp_write(rt2x00dev, 23, 0x06);
1311 rt73usb_bbp_write(rt2x00dev, 24, 0xfe);
1312 rt73usb_bbp_write(rt2x00dev, 25, 0x0a);
1313 rt73usb_bbp_write(rt2x00dev, 26, 0x0d);
1314 rt73usb_bbp_write(rt2x00dev, 32, 0x0b);
1315 rt73usb_bbp_write(rt2x00dev, 34, 0x12);
1316 rt73usb_bbp_write(rt2x00dev, 37, 0x07);
1317 rt73usb_bbp_write(rt2x00dev, 39, 0xf8);
1318 rt73usb_bbp_write(rt2x00dev, 41, 0x60);
1319 rt73usb_bbp_write(rt2x00dev, 53, 0x10);
1320 rt73usb_bbp_write(rt2x00dev, 54, 0x18);
1321 rt73usb_bbp_write(rt2x00dev, 60, 0x10);
1322 rt73usb_bbp_write(rt2x00dev, 61, 0x04);
1323 rt73usb_bbp_write(rt2x00dev, 62, 0x04);
1324 rt73usb_bbp_write(rt2x00dev, 75, 0xfe);
1325 rt73usb_bbp_write(rt2x00dev, 86, 0xfe);
1326 rt73usb_bbp_write(rt2x00dev, 88, 0xfe);
1327 rt73usb_bbp_write(rt2x00dev, 90, 0x0f);
1328 rt73usb_bbp_write(rt2x00dev, 99, 0x00);
1329 rt73usb_bbp_write(rt2x00dev, 102, 0x16);
1330 rt73usb_bbp_write(rt2x00dev, 107, 0x04);
1331
95ea3627
ID		 1332 for (i = 0; i < EEPROM_BBP_SIZE; i++) {
1333 rt2x00_eeprom_read(rt2x00dev, EEPROM_BBP_START + i, &eeprom);
1334
1335 if (eeprom != 0xffff && eeprom != 0x0000) {
1336 reg_id = rt2x00_get_field16(eeprom, EEPROM_BBP_REG_ID);
1337 value = rt2x00_get_field16(eeprom, EEPROM_BBP_VALUE);
95ea3627
ID		 1338 rt73usb_bbp_write(rt2x00dev, reg_id, value);
1339 }
1340 }
95ea3627
ID		 1341
1342 return 0;
1343}
1344
1345/*
1346 * Device state switch handlers.
1347 */
1348static void rt73usb_toggle_rx(struct rt2x00_dev *rt2x00dev,
1349 enum dev_state state)
1350{
1351 u32 reg;
1352
0f829b1d 1353 rt2x00usb_register_read(rt2x00dev, TXRX_CSR0, &reg);
95ea3627 1354 rt2x00_set_field32(&reg, TXRX_CSR0_DISABLE_RX,
2b08da3f
ID		 1355 (state == STATE_RADIO_RX_OFF) ||
1356 (state == STATE_RADIO_RX_OFF_LINK));
0f829b1d 1357 rt2x00usb_register_write(rt2x00dev, TXRX_CSR0, reg);
95ea3627
ID		 1358}
1359
1360static int rt73usb_enable_radio(struct rt2x00_dev *rt2x00dev)
1361{
1362 /*
1363 * Initialize all registers.
1364 */
2b08da3f
ID		 1365 if (unlikely(rt73usb_init_registers(rt2x00dev) ||
1366 rt73usb_init_bbp(rt2x00dev)))
95ea3627 1367 return -EIO;
95ea3627 1368
95ea3627
ID		 1369 return 0;
1370}
1371
1372static void rt73usb_disable_radio(struct rt2x00_dev *rt2x00dev)
1373{
0f829b1d 1374 rt2x00usb_register_write(rt2x00dev, MAC_CSR10, 0x00001818);
95ea3627
ID		 1375
1376 /*
1377 * Disable synchronisation.
1378 */
0f829b1d 1379 rt2x00usb_register_write(rt2x00dev, TXRX_CSR9, 0);
95ea3627
ID		 1380
1381 rt2x00usb_disable_radio(rt2x00dev);
1382}
1383
1384static int rt73usb_set_state(struct rt2x00_dev *rt2x00dev, enum dev_state state)
1385{
1386 u32 reg;
1387 unsigned int i;
1388 char put_to_sleep;
95ea3627
ID		 1389
1390 put_to_sleep = (state != STATE_AWAKE);
1391
0f829b1d 1392 rt2x00usb_register_read(rt2x00dev, MAC_CSR12, &reg);
95ea3627
ID		 1393 rt2x00_set_field32(&reg, MAC_CSR12_FORCE_WAKEUP, !put_to_sleep);
1394 rt2x00_set_field32(&reg, MAC_CSR12_PUT_TO_SLEEP, put_to_sleep);
0f829b1d 1395 rt2x00usb_register_write(rt2x00dev, MAC_CSR12, reg);
95ea3627
ID		 1396
1397 /*
1398 * Device is not guaranteed to be in the requested state yet.
1399 * We must wait until the register indicates that the
1400 * device has entered the correct state.
1401 */
1402 for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
0f829b1d 1403 rt2x00usb_register_read(rt2x00dev, MAC_CSR12, &reg);
2b08da3f
ID		 1404 state = rt2x00_get_field32(reg, MAC_CSR12_BBP_CURRENT_STATE);
1405 if (state == !put_to_sleep)
95ea3627
ID		 1406 return 0;
1407 msleep(10);
1408 }
1409
95ea3627
ID		 1410 return -EBUSY;
1411}
1412
1413static int rt73usb_set_device_state(struct rt2x00_dev *rt2x00dev,
1414 enum dev_state state)
1415{
1416 int retval = 0;
1417
1418 switch (state) {
1419 case STATE_RADIO_ON:
1420 retval = rt73usb_enable_radio(rt2x00dev);
1421 break;
1422 case STATE_RADIO_OFF:
1423 rt73usb_disable_radio(rt2x00dev);
1424 break;
1425 case STATE_RADIO_RX_ON:
61667d8d 1426 case STATE_RADIO_RX_ON_LINK:
95ea3627 1427 case STATE_RADIO_RX_OFF:
61667d8d 1428 case STATE_RADIO_RX_OFF_LINK:
2b08da3f
ID		 1429 rt73usb_toggle_rx(rt2x00dev, state);
1430 break;
1431 case STATE_RADIO_IRQ_ON:
1432 case STATE_RADIO_IRQ_OFF:
1433 /* No support, but no error either */
95ea3627
ID		 1434 break;
1435 case STATE_DEEP_SLEEP:
1436 case STATE_SLEEP:
1437 case STATE_STANDBY:
1438 case STATE_AWAKE:
1439 retval = rt73usb_set_state(rt2x00dev, state);
1440 break;
1441 default:
1442 retval = -ENOTSUPP;
1443 break;
1444 }
1445
2b08da3f
ID		 1446 if (unlikely(retval))
1447 ERROR(rt2x00dev, "Device failed to enter state %d (%d).\n",
1448 state, retval);
1449
95ea3627
ID		 1450 return retval;
1451}
1452
1453/*
1454 * TX descriptor initialization
1455 */
1456static void rt73usb_write_tx_desc(struct rt2x00_dev *rt2x00dev,
906c110f
ID		 1457 struct sk_buff *skb,
1458 struct txentry_desc *txdesc)
95ea3627 1459{
181d6902 1460 struct skb_frame_desc *skbdesc = get_skb_frame_desc(skb);
dd3193e1 1461 __le32 *txd = skbdesc->desc;
95ea3627
ID		 1462 u32 word;
1463
1464 /*
1465 * Start writing the descriptor words.
1466 */
1467 rt2x00_desc_read(txd, 1, &word);
181d6902
ID		 1468 rt2x00_set_field32(&word, TXD_W1_HOST_Q_ID, txdesc->queue);
1469 rt2x00_set_field32(&word, TXD_W1_AIFSN, txdesc->aifs);
1470 rt2x00_set_field32(&word, TXD_W1_CWMIN, txdesc->cw_min);
1471 rt2x00_set_field32(&word, TXD_W1_CWMAX, txdesc->cw_max);
906c110f 1472 rt2x00_set_field32(&word, TXD_W1_IV_OFFSET, txdesc->iv_offset);
5adf6d63
ID		 1473 rt2x00_set_field32(&word, TXD_W1_HW_SEQUENCE,
1474 test_bit(ENTRY_TXD_GENERATE_SEQ, &txdesc->flags));
95ea3627
ID		 1475 rt2x00_desc_write(txd, 1, word);
1476
1477 rt2x00_desc_read(txd, 2, &word);
181d6902
ID		 1478 rt2x00_set_field32(&word, TXD_W2_PLCP_SIGNAL, txdesc->signal);
1479 rt2x00_set_field32(&word, TXD_W2_PLCP_SERVICE, txdesc->service);
1480 rt2x00_set_field32(&word, TXD_W2_PLCP_LENGTH_LOW, txdesc->length_low);
1481 rt2x00_set_field32(&word, TXD_W2_PLCP_LENGTH_HIGH, txdesc->length_high);
95ea3627
ID		 1482 rt2x00_desc_write(txd, 2, word);
1483
906c110f 1484 if (test_bit(ENTRY_TXD_ENCRYPT, &txdesc->flags)) {
1ce9cdac
ID		 1485 _rt2x00_desc_write(txd, 3, skbdesc->iv[0]);
1486 _rt2x00_desc_write(txd, 4, skbdesc->iv[1]);
906c110f
ID		 1487 }
1488
95ea3627
ID		 1489 rt2x00_desc_read(txd, 5, &word);
1490 rt2x00_set_field32(&word, TXD_W5_TX_POWER,
ac1aa7e4 1491 TXPOWER_TO_DEV(rt2x00dev->tx_power));
95ea3627
ID		 1492 rt2x00_set_field32(&word, TXD_W5_WAITING_DMA_DONE_INT, 1);
1493 rt2x00_desc_write(txd, 5, word);
1494
1495 rt2x00_desc_read(txd, 0, &word);
1496 rt2x00_set_field32(&word, TXD_W0_BURST,
181d6902 1497 test_bit(ENTRY_TXD_BURST, &txdesc->flags));
95ea3627
ID		 1498 rt2x00_set_field32(&word, TXD_W0_VALID, 1);
1499 rt2x00_set_field32(&word, TXD_W0_MORE_FRAG,
181d6902 1500 test_bit(ENTRY_TXD_MORE_FRAG, &txdesc->flags));
95ea3627 1501 rt2x00_set_field32(&word, TXD_W0_ACK,
181d6902 1502 test_bit(ENTRY_TXD_ACK, &txdesc->flags));
95ea3627 1503 rt2x00_set_field32(&word, TXD_W0_TIMESTAMP,
181d6902 1504 test_bit(ENTRY_TXD_REQ_TIMESTAMP, &txdesc->flags));
95ea3627 1505 rt2x00_set_field32(&word, TXD_W0_OFDM,
076f9582 1506 (txdesc->rate_mode == RATE_MODE_OFDM));
181d6902 1507 rt2x00_set_field32(&word, TXD_W0_IFS, txdesc->ifs);
95ea3627 1508 rt2x00_set_field32(&word, TXD_W0_RETRY_MODE,
61486e0f 1509 test_bit(ENTRY_TXD_RETRY_MODE, &txdesc->flags));
906c110f
ID		 1510 rt2x00_set_field32(&word, TXD_W0_TKIP_MIC,
1511 test_bit(ENTRY_TXD_ENCRYPT_MMIC, &txdesc->flags));
1512 rt2x00_set_field32(&word, TXD_W0_KEY_TABLE,
1513 test_bit(ENTRY_TXD_ENCRYPT_PAIRWISE, &txdesc->flags));
1514 rt2x00_set_field32(&word, TXD_W0_KEY_INDEX, txdesc->key_idx);
1abc3656 1515 rt2x00_set_field32(&word, TXD_W0_DATABYTE_COUNT, skb->len);
95ea3627 1516 rt2x00_set_field32(&word, TXD_W0_BURST2,
181d6902 1517 test_bit(ENTRY_TXD_BURST, &txdesc->flags));
906c110f 1518 rt2x00_set_field32(&word, TXD_W0_CIPHER_ALG, txdesc->cipher);
95ea3627
ID		 1519 rt2x00_desc_write(txd, 0, word);
1520}
1521
bd88a781
ID		 1522/*
1523 * TX data initialization
1524 */
1525static void rt73usb_write_beacon(struct queue_entry *entry)
1526{
1527 struct rt2x00_dev *rt2x00dev = entry->queue->rt2x00dev;
1528 struct skb_frame_desc *skbdesc = get_skb_frame_desc(entry->skb);
1529 unsigned int beacon_base;
1530 u32 reg;
1531
1532 /*
1533 * Add the descriptor in front of the skb.
1534 */
1535 skb_push(entry->skb, entry->queue->desc_size);
1536 memcpy(entry->skb->data, skbdesc->desc, skbdesc->desc_len);
1537 skbdesc->desc = entry->skb->data;
1538
1539 /*
1540 * Disable beaconing while we are reloading the beacon data,
1541 * otherwise we might be sending out invalid data.
1542 */
0f829b1d 1543 rt2x00usb_register_read(rt2x00dev, TXRX_CSR9, &reg);
bd88a781
ID		 1544 rt2x00_set_field32(&reg, TXRX_CSR9_TSF_TICKING, 0);
1545 rt2x00_set_field32(&reg, TXRX_CSR9_TBTT_ENABLE, 0);
1546 rt2x00_set_field32(&reg, TXRX_CSR9_BEACON_GEN, 0);
0f829b1d 1547 rt2x00usb_register_write(rt2x00dev, TXRX_CSR9, reg);
bd88a781
ID		 1548
1549 /*
1550 * Write entire beacon with descriptor to register.
1551 */
1552 beacon_base = HW_BEACON_OFFSET(entry->entry_idx);
3e0c1abe
IM		 1553 rt2x00usb_vendor_request_large_buff(rt2x00dev, USB_MULTI_WRITE,
1554 USB_VENDOR_REQUEST_OUT, beacon_base,
1555 entry->skb->data, entry->skb->len,
1556 REGISTER_TIMEOUT32(entry->skb->len));
bd88a781
ID		 1557
1558 /*
1559 * Clean up the beacon skb.
1560 */
1561 dev_kfree_skb(entry->skb);
1562 entry->skb = NULL;
1563}
1564
f1ca2167 1565static int rt73usb_get_tx_data_len(struct queue_entry *entry)
dd9fa2d2
ID		 1566{
1567 int length;
1568
1569 /*
1570 * The length _must_ be a multiple of 4,
1571 * but it must _not_ be a multiple of the USB packet size.
1572 */
f1ca2167
ID		 1573 length = roundup(entry->skb->len, 4);
1574 length += (4 * !(length % entry->queue->usb_maxpacket));
dd9fa2d2
ID		 1575
1576 return length;
1577}
1578
95ea3627 1579static void rt73usb_kick_tx_queue(struct rt2x00_dev *rt2x00dev,
e58c6aca 1580 const enum data_queue_qid queue)
95ea3627
ID		 1581{
1582 u32 reg;
1583
f019d514
ID		 1584 if (queue != QID_BEACON) {
1585 rt2x00usb_kick_tx_queue(rt2x00dev, queue);
95ea3627 1586 return;
f019d514 1587 }
95ea3627
ID		 1588
1589 /*
1590 * For Wi-Fi faily generated beacons between participating stations.
1591 * Set TBTT phase adaptive adjustment step to 8us (default 16us)
1592 */
0f829b1d 1593 rt2x00usb_register_write(rt2x00dev, TXRX_CSR10, 0x00001008);
95ea3627 1594
0f829b1d 1595 rt2x00usb_register_read(rt2x00dev, TXRX_CSR9, &reg);
95ea3627 1596 if (!rt2x00_get_field32(reg, TXRX_CSR9_BEACON_GEN)) {
8af244cc
ID		 1597 rt2x00_set_field32(&reg, TXRX_CSR9_TSF_TICKING, 1);
1598 rt2x00_set_field32(&reg, TXRX_CSR9_TBTT_ENABLE, 1);
95ea3627 1599 rt2x00_set_field32(&reg, TXRX_CSR9_BEACON_GEN, 1);
0f829b1d 1600 rt2x00usb_register_write(rt2x00dev, TXRX_CSR9, reg);
95ea3627
ID		 1601 }
1602}
1603
1604/*
1605 * RX control handlers
1606 */
1607static int rt73usb_agc_to_rssi(struct rt2x00_dev *rt2x00dev, int rxd_w1)
1608{
ba2ab471 1609 u8 offset = rt2x00dev->lna_gain;
95ea3627
ID		 1610 u8 lna;
1611
1612 lna = rt2x00_get_field32(rxd_w1, RXD_W1_RSSI_LNA);
1613 switch (lna) {
1614 case 3:
ba2ab471 1615 offset += 90;
95ea3627
ID		 1616 break;
1617 case 2:
ba2ab471 1618 offset += 74;
95ea3627
ID		 1619 break;
1620 case 1:
ba2ab471 1621 offset += 64;
95ea3627
ID		 1622 break;
1623 default:
1624 return 0;
1625 }
1626
8318d78a 1627 if (rt2x00dev->rx_status.band == IEEE80211_BAND_5GHZ) {
95ea3627
ID		 1628 if (test_bit(CONFIG_EXTERNAL_LNA_A, &rt2x00dev->flags)) {
1629 if (lna == 3 || lna == 2)
1630 offset += 10;
1631 } else {
1632 if (lna == 3)
1633 offset += 6;
1634 else if (lna == 2)
1635 offset += 8;
1636 }
95ea3627
ID		 1637 }
1638
1639 return rt2x00_get_field32(rxd_w1, RXD_W1_RSSI_AGC) * 2 - offset;
1640}
1641
181d6902 1642static void rt73usb_fill_rxdone(struct queue_entry *entry,
55887511 1643 struct rxdone_entry_desc *rxdesc)
95ea3627 1644{
906c110f 1645 struct rt2x00_dev *rt2x00dev = entry->queue->rt2x00dev;
181d6902 1646 struct skb_frame_desc *skbdesc = get_skb_frame_desc(entry->skb);
4bd7c452 1647 __le32 *rxd = (__le32 *)entry->skb->data;
95ea3627
ID		 1648 u32 word0;
1649 u32 word1;
1650
f855c10b 1651 /*
a26cbc65
GW		 1652 * Copy descriptor to the skbdesc->desc buffer, making it safe from moving of
1653 * frame data in rt2x00usb.
f855c10b 1654 */
a26cbc65 1655 memcpy(skbdesc->desc, rxd, skbdesc->desc_len);
70a96109 1656 rxd = (__le32 *)skbdesc->desc;
f855c10b
ID		 1657
1658 /*
70a96109 1659 * It is now safe to read the descriptor on all architectures.
f855c10b 1660 */
95ea3627
ID		 1661 rt2x00_desc_read(rxd, 0, &word0);
1662 rt2x00_desc_read(rxd, 1, &word1);
1663
4150c572 1664 if (rt2x00_get_field32(word0, RXD_W0_CRC_ERROR))
181d6902 1665 rxdesc->flags |= RX_FLAG_FAILED_FCS_CRC;
95ea3627 1666
906c110f
ID		 1667 if (test_bit(CONFIG_SUPPORT_HW_CRYPTO, &rt2x00dev->flags)) {
1668 rxdesc->cipher =
1669 rt2x00_get_field32(word0, RXD_W0_CIPHER_ALG);
1670 rxdesc->cipher_status =
1671 rt2x00_get_field32(word0, RXD_W0_CIPHER_ERROR);
1672 }
1673
1674 if (rxdesc->cipher != CIPHER_NONE) {
1ce9cdac
ID		 1675 _rt2x00_desc_read(rxd, 2, &rxdesc->iv[0]);
1676 _rt2x00_desc_read(rxd, 3, &rxdesc->iv[1]);
74415edb
ID		 1677 rxdesc->dev_flags |= RXDONE_CRYPTO_IV;
1678
906c110f 1679 _rt2x00_desc_read(rxd, 4, &rxdesc->icv);
74415edb 1680 rxdesc->dev_flags |= RXDONE_CRYPTO_ICV;
906c110f
ID		 1681
1682 /*
1683 * Hardware has stripped IV/EIV data from 802.11 frame during
1684 * decryption. It has provided the data seperately but rt2x00lib
1685 * should decide if it should be reinserted.
1686 */
1687 rxdesc->flags |= RX_FLAG_IV_STRIPPED;
1688
1689 /*
1690 * FIXME: Legacy driver indicates that the frame does
1691 * contain the Michael Mic. Unfortunately, in rt2x00
1692 * the MIC seems to be missing completely...
1693 */
1694 rxdesc->flags |= RX_FLAG_MMIC_STRIPPED;
1695
1696 if (rxdesc->cipher_status == RX_CRYPTO_SUCCESS)
1697 rxdesc->flags |= RX_FLAG_DECRYPTED;
1698 else if (rxdesc->cipher_status == RX_CRYPTO_FAIL_MIC)
1699 rxdesc->flags |= RX_FLAG_MMIC_ERROR;
1700 }
1701
95ea3627
ID		 1702 /*
1703 * Obtain the status about this packet.
89993890
ID		 1704 * When frame was received with an OFDM bitrate,
1705 * the signal is the PLCP value. If it was received with
1706 * a CCK bitrate the signal is the rate in 100kbit/s.
95ea3627 1707 */
181d6902 1708 rxdesc->signal = rt2x00_get_field32(word1, RXD_W1_SIGNAL);
906c110f 1709 rxdesc->rssi = rt73usb_agc_to_rssi(rt2x00dev, word1);
181d6902 1710 rxdesc->size = rt2x00_get_field32(word0, RXD_W0_DATABYTE_COUNT);
19d30e02 1711
19d30e02
ID		 1712 if (rt2x00_get_field32(word0, RXD_W0_OFDM))
1713 rxdesc->dev_flags |= RXDONE_SIGNAL_PLCP;
6c6aa3c0
ID		 1714 else
1715 rxdesc->dev_flags |= RXDONE_SIGNAL_BITRATE;
19d30e02
ID		 1716 if (rt2x00_get_field32(word0, RXD_W0_MY_BSS))
1717 rxdesc->dev_flags |= RXDONE_MY_BSS;
181d6902 1718
2ae23854 1719 /*
70a96109 1720 * Set skb pointers, and update frame information.
2ae23854 1721 */
70a96109 1722 skb_pull(entry->skb, entry->queue->desc_size);
2ae23854 1723 skb_trim(entry->skb, rxdesc->size);
95ea3627
ID		 1724}
1725
1726/*
1727 * Device probe functions.
1728 */
1729static int rt73usb_validate_eeprom(struct rt2x00_dev *rt2x00dev)
1730{
1731 u16 word;
1732 u8 *mac;
1733 s8 value;
1734
1735 rt2x00usb_eeprom_read(rt2x00dev, rt2x00dev->eeprom, EEPROM_SIZE);
1736
1737 /*
1738 * Start validation of the data that has been read.
1739 */
1740 mac = rt2x00_eeprom_addr(rt2x00dev, EEPROM_MAC_ADDR_0);
1741 if (!is_valid_ether_addr(mac)) {
1742 random_ether_addr(mac);
e174961c 1743 EEPROM(rt2x00dev, "MAC: %pM\n", mac);
95ea3627
ID		 1744 }
1745
1746 rt2x00_eeprom_read(rt2x00dev, EEPROM_ANTENNA, &word);
1747 if (word == 0xffff) {
1748 rt2x00_set_field16(&word, EEPROM_ANTENNA_NUM, 2);
362f3b6b
ID		 1749 rt2x00_set_field16(&word, EEPROM_ANTENNA_TX_DEFAULT,
1750 ANTENNA_B);
1751 rt2x00_set_field16(&word, EEPROM_ANTENNA_RX_DEFAULT,
1752 ANTENNA_B);
95ea3627
ID		 1753 rt2x00_set_field16(&word, EEPROM_ANTENNA_FRAME_TYPE, 0);
1754 rt2x00_set_field16(&word, EEPROM_ANTENNA_DYN_TXAGC, 0);
1755 rt2x00_set_field16(&word, EEPROM_ANTENNA_HARDWARE_RADIO, 0);
1756 rt2x00_set_field16(&word, EEPROM_ANTENNA_RF_TYPE, RF5226);
1757 rt2x00_eeprom_write(rt2x00dev, EEPROM_ANTENNA, word);
1758 EEPROM(rt2x00dev, "Antenna: 0x%04x\n", word);
1759 }
1760
1761 rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC, &word);
1762 if (word == 0xffff) {
1763 rt2x00_set_field16(&word, EEPROM_NIC_EXTERNAL_LNA, 0);
1764 rt2x00_eeprom_write(rt2x00dev, EEPROM_NIC, word);
1765 EEPROM(rt2x00dev, "NIC: 0x%04x\n", word);
1766 }
1767
1768 rt2x00_eeprom_read(rt2x00dev, EEPROM_LED, &word);
1769 if (word == 0xffff) {
1770 rt2x00_set_field16(&word, EEPROM_LED_POLARITY_RDY_G, 0);
1771 rt2x00_set_field16(&word, EEPROM_LED_POLARITY_RDY_A, 0);
1772 rt2x00_set_field16(&word, EEPROM_LED_POLARITY_ACT, 0);
1773 rt2x00_set_field16(&word, EEPROM_LED_POLARITY_GPIO_0, 0);
1774 rt2x00_set_field16(&word, EEPROM_LED_POLARITY_GPIO_1, 0);
1775 rt2x00_set_field16(&word, EEPROM_LED_POLARITY_GPIO_2, 0);
1776 rt2x00_set_field16(&word, EEPROM_LED_POLARITY_GPIO_3, 0);
1777 rt2x00_set_field16(&word, EEPROM_LED_POLARITY_GPIO_4, 0);
1778 rt2x00_set_field16(&word, EEPROM_LED_LED_MODE,
1779 LED_MODE_DEFAULT);
1780 rt2x00_eeprom_write(rt2x00dev, EEPROM_LED, word);
1781 EEPROM(rt2x00dev, "Led: 0x%04x\n", word);
1782 }
1783
1784 rt2x00_eeprom_read(rt2x00dev, EEPROM_FREQ, &word);
1785 if (word == 0xffff) {
1786 rt2x00_set_field16(&word, EEPROM_FREQ_OFFSET, 0);
1787 rt2x00_set_field16(&word, EEPROM_FREQ_SEQ, 0);
1788 rt2x00_eeprom_write(rt2x00dev, EEPROM_FREQ, word);
1789 EEPROM(rt2x00dev, "Freq: 0x%04x\n", word);
1790 }
1791
1792 rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_OFFSET_BG, &word);
1793 if (word == 0xffff) {
1794 rt2x00_set_field16(&word, EEPROM_RSSI_OFFSET_BG_1, 0);
1795 rt2x00_set_field16(&word, EEPROM_RSSI_OFFSET_BG_2, 0);
1796 rt2x00_eeprom_write(rt2x00dev, EEPROM_RSSI_OFFSET_BG, word);
1797 EEPROM(rt2x00dev, "RSSI OFFSET BG: 0x%04x\n", word);
1798 } else {
1799 value = rt2x00_get_field16(word, EEPROM_RSSI_OFFSET_BG_1);
1800 if (value < -10 || value > 10)
1801 rt2x00_set_field16(&word, EEPROM_RSSI_OFFSET_BG_1, 0);
1802 value = rt2x00_get_field16(word, EEPROM_RSSI_OFFSET_BG_2);
1803 if (value < -10 || value > 10)
1804 rt2x00_set_field16(&word, EEPROM_RSSI_OFFSET_BG_2, 0);
1805 rt2x00_eeprom_write(rt2x00dev, EEPROM_RSSI_OFFSET_BG, word);
1806 }
1807
1808 rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_OFFSET_A, &word);
1809 if (word == 0xffff) {
1810 rt2x00_set_field16(&word, EEPROM_RSSI_OFFSET_A_1, 0);
1811 rt2x00_set_field16(&word, EEPROM_RSSI_OFFSET_A_2, 0);
1812 rt2x00_eeprom_write(rt2x00dev, EEPROM_RSSI_OFFSET_A, word);
417f412f 1813 EEPROM(rt2x00dev, "RSSI OFFSET A: 0x%04x\n", word);
95ea3627
ID		 1814 } else {
1815 value = rt2x00_get_field16(word, EEPROM_RSSI_OFFSET_A_1);
1816 if (value < -10 || value > 10)
1817 rt2x00_set_field16(&word, EEPROM_RSSI_OFFSET_A_1, 0);
1818 value = rt2x00_get_field16(word, EEPROM_RSSI_OFFSET_A_2);
1819 if (value < -10 || value > 10)
1820 rt2x00_set_field16(&word, EEPROM_RSSI_OFFSET_A_2, 0);
1821 rt2x00_eeprom_write(rt2x00dev, EEPROM_RSSI_OFFSET_A, word);
1822 }
1823
1824 return 0;
1825}
1826
1827static int rt73usb_init_eeprom(struct rt2x00_dev *rt2x00dev)
1828{
1829 u32 reg;
1830 u16 value;
1831 u16 eeprom;
1832
1833 /*
1834 * Read EEPROM word for configuration.
1835 */
1836 rt2x00_eeprom_read(rt2x00dev, EEPROM_ANTENNA, &eeprom);
1837
1838 /*
1839 * Identify RF chipset.
1840 */
1841 value = rt2x00_get_field16(eeprom, EEPROM_ANTENNA_RF_TYPE);
0f829b1d 1842 rt2x00usb_register_read(rt2x00dev, MAC_CSR0, &reg);
95ea3627
ID		 1843 rt2x00_set_chip(rt2x00dev, RT2571, value, reg);
1844
755a957d 1845 if (!rt2x00_check_rev(&rt2x00dev->chip, 0x25730)) {
95ea3627
ID		 1846 ERROR(rt2x00dev, "Invalid RT chipset detected.\n");
1847 return -ENODEV;
1848 }
1849
1850 if (!rt2x00_rf(&rt2x00dev->chip, RF5226) &&
1851 !rt2x00_rf(&rt2x00dev->chip, RF2528) &&
1852 !rt2x00_rf(&rt2x00dev->chip, RF5225) &&
1853 !rt2x00_rf(&rt2x00dev->chip, RF2527)) {
1854 ERROR(rt2x00dev, "Invalid RF chipset detected.\n");
1855 return -ENODEV;
1856 }
1857
1858 /*
1859 * Identify default antenna configuration.
1860 */
addc81bd 1861 rt2x00dev->default_ant.tx =
95ea3627 1862 rt2x00_get_field16(eeprom, EEPROM_ANTENNA_TX_DEFAULT);
addc81bd 1863 rt2x00dev->default_ant.rx =
95ea3627
ID		 1864 rt2x00_get_field16(eeprom, EEPROM_ANTENNA_RX_DEFAULT);
1865
1866 /*
1867 * Read the Frame type.
1868 */
1869 if (rt2x00_get_field16(eeprom, EEPROM_ANTENNA_FRAME_TYPE))
1870 __set_bit(CONFIG_FRAME_TYPE, &rt2x00dev->flags);
1871
7396faf4
ID		 1872 /*
1873 * Detect if this device has an hardware controlled radio.
1874 */
1875#ifdef CONFIG_RT2X00_LIB_RFKILL
1876 if (rt2x00_get_field16(eeprom, EEPROM_ANTENNA_HARDWARE_RADIO))
1877 __set_bit(CONFIG_SUPPORT_HW_BUTTON, &rt2x00dev->flags);
1878#endif /* CONFIG_RT2X00_LIB_RFKILL */
1879
95ea3627
ID		 1880 /*
1881 * Read frequency offset.
1882 */
1883 rt2x00_eeprom_read(rt2x00dev, EEPROM_FREQ, &eeprom);
1884 rt2x00dev->freq_offset = rt2x00_get_field16(eeprom, EEPROM_FREQ_OFFSET);
1885
1886 /*
1887 * Read external LNA informations.
1888 */
1889 rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC, &eeprom);
1890
1891 if (rt2x00_get_field16(eeprom, EEPROM_NIC_EXTERNAL_LNA)) {
1892 __set_bit(CONFIG_EXTERNAL_LNA_A, &rt2x00dev->flags);
1893 __set_bit(CONFIG_EXTERNAL_LNA_BG, &rt2x00dev->flags);
1894 }
1895
1896 /*
1897 * Store led settings, for correct led behaviour.
1898 */
771fd565 1899#ifdef CONFIG_RT2X00_LIB_LEDS
95ea3627
ID		 1900 rt2x00_eeprom_read(rt2x00dev, EEPROM_LED, &eeprom);
1901
475433be
ID		 1902 rt73usb_init_led(rt2x00dev, &rt2x00dev->led_radio, LED_TYPE_RADIO);
1903 rt73usb_init_led(rt2x00dev, &rt2x00dev->led_assoc, LED_TYPE_ASSOC);
1904 if (value == LED_MODE_SIGNAL_STRENGTH)
1905 rt73usb_init_led(rt2x00dev, &rt2x00dev->led_qual,
1906 LED_TYPE_QUALITY);
a9450b70
ID		 1907
1908 rt2x00_set_field16(&rt2x00dev->led_mcu_reg, MCU_LEDCS_LED_MODE, value);
1909 rt2x00_set_field16(&rt2x00dev->led_mcu_reg, MCU_LEDCS_POLARITY_GPIO_0,
95ea3627
ID		 1910 rt2x00_get_field16(eeprom,
1911 EEPROM_LED_POLARITY_GPIO_0));
a9450b70 1912 rt2x00_set_field16(&rt2x00dev->led_mcu_reg, MCU_LEDCS_POLARITY_GPIO_1,
95ea3627
ID		 1913 rt2x00_get_field16(eeprom,
1914 EEPROM_LED_POLARITY_GPIO_1));
a9450b70 1915 rt2x00_set_field16(&rt2x00dev->led_mcu_reg, MCU_LEDCS_POLARITY_GPIO_2,
95ea3627
ID		 1916 rt2x00_get_field16(eeprom,
1917 EEPROM_LED_POLARITY_GPIO_2));
a9450b70 1918 rt2x00_set_field16(&rt2x00dev->led_mcu_reg, MCU_LEDCS_POLARITY_GPIO_3,
95ea3627
ID		 1919 rt2x00_get_field16(eeprom,
1920 EEPROM_LED_POLARITY_GPIO_3));
a9450b70 1921 rt2x00_set_field16(&rt2x00dev->led_mcu_reg, MCU_LEDCS_POLARITY_GPIO_4,
95ea3627
ID		 1922 rt2x00_get_field16(eeprom,
1923 EEPROM_LED_POLARITY_GPIO_4));
a9450b70 1924 rt2x00_set_field16(&rt2x00dev->led_mcu_reg, MCU_LEDCS_POLARITY_ACT,
95ea3627 1925 rt2x00_get_field16(eeprom, EEPROM_LED_POLARITY_ACT));
a9450b70 1926 rt2x00_set_field16(&rt2x00dev->led_mcu_reg, MCU_LEDCS_POLARITY_READY_BG,
95ea3627
ID		 1927 rt2x00_get_field16(eeprom,
1928 EEPROM_LED_POLARITY_RDY_G));
a9450b70 1929 rt2x00_set_field16(&rt2x00dev->led_mcu_reg, MCU_LEDCS_POLARITY_READY_A,
95ea3627
ID		 1930 rt2x00_get_field16(eeprom,
1931 EEPROM_LED_POLARITY_RDY_A));
771fd565 1932#endif /* CONFIG_RT2X00_LIB_LEDS */
95ea3627
ID		 1933
1934 return 0;
1935}
1936
1937/*
1938 * RF value list for RF2528
1939 * Supports: 2.4 GHz
1940 */
1941static const struct rf_channel rf_vals_bg_2528[] = {
1942 { 1, 0x00002c0c, 0x00000786, 0x00068255, 0x000fea0b },
1943 { 2, 0x00002c0c, 0x00000786, 0x00068255, 0x000fea1f },
1944 { 3, 0x00002c0c, 0x0000078a, 0x00068255, 0x000fea0b },
1945 { 4, 0x00002c0c, 0x0000078a, 0x00068255, 0x000fea1f },
1946 { 5, 0x00002c0c, 0x0000078e, 0x00068255, 0x000fea0b },
1947 { 6, 0x00002c0c, 0x0000078e, 0x00068255, 0x000fea1f },
1948 { 7, 0x00002c0c, 0x00000792, 0x00068255, 0x000fea0b },
1949 { 8, 0x00002c0c, 0x00000792, 0x00068255, 0x000fea1f },
1950 { 9, 0x00002c0c, 0x00000796, 0x00068255, 0x000fea0b },
1951 { 10, 0x00002c0c, 0x00000796, 0x00068255, 0x000fea1f },
1952 { 11, 0x00002c0c, 0x0000079a, 0x00068255, 0x000fea0b },
1953 { 12, 0x00002c0c, 0x0000079a, 0x00068255, 0x000fea1f },
1954 { 13, 0x00002c0c, 0x0000079e, 0x00068255, 0x000fea0b },
1955 { 14, 0x00002c0c, 0x000007a2, 0x00068255, 0x000fea13 },
1956};
1957
1958/*
1959 * RF value list for RF5226
1960 * Supports: 2.4 GHz & 5.2 GHz
1961 */
1962static const struct rf_channel rf_vals_5226[] = {
1963 { 1, 0x00002c0c, 0x00000786, 0x00068255, 0x000fea0b },
1964 { 2, 0x00002c0c, 0x00000786, 0x00068255, 0x000fea1f },
1965 { 3, 0x00002c0c, 0x0000078a, 0x00068255, 0x000fea0b },
1966 { 4, 0x00002c0c, 0x0000078a, 0x00068255, 0x000fea1f },
1967 { 5, 0x00002c0c, 0x0000078e, 0x00068255, 0x000fea0b },
1968 { 6, 0x00002c0c, 0x0000078e, 0x00068255, 0x000fea1f },
1969 { 7, 0x00002c0c, 0x00000792, 0x00068255, 0x000fea0b },
1970 { 8, 0x00002c0c, 0x00000792, 0x00068255, 0x000fea1f },
1971 { 9, 0x00002c0c, 0x00000796, 0x00068255, 0x000fea0b },
1972 { 10, 0x00002c0c, 0x00000796, 0x00068255, 0x000fea1f },
1973 { 11, 0x00002c0c, 0x0000079a, 0x00068255, 0x000fea0b },
1974 { 12, 0x00002c0c, 0x0000079a, 0x00068255, 0x000fea1f },
1975 { 13, 0x00002c0c, 0x0000079e, 0x00068255, 0x000fea0b },
1976 { 14, 0x00002c0c, 0x000007a2, 0x00068255, 0x000fea13 },
1977
1978 /* 802.11 UNI / HyperLan 2 */
1979 { 36, 0x00002c0c, 0x0000099a, 0x00098255, 0x000fea23 },
1980 { 40, 0x00002c0c, 0x000009a2, 0x00098255, 0x000fea03 },
1981 { 44, 0x00002c0c, 0x000009a6, 0x00098255, 0x000fea0b },
1982 { 48, 0x00002c0c, 0x000009aa, 0x00098255, 0x000fea13 },
1983 { 52, 0x00002c0c, 0x000009ae, 0x00098255, 0x000fea1b },
1984 { 56, 0x00002c0c, 0x000009b2, 0x00098255, 0x000fea23 },
1985 { 60, 0x00002c0c, 0x000009ba, 0x00098255, 0x000fea03 },
1986 { 64, 0x00002c0c, 0x000009be, 0x00098255, 0x000fea0b },
1987
1988 /* 802.11 HyperLan 2 */
1989 { 100, 0x00002c0c, 0x00000a2a, 0x000b8255, 0x000fea03 },
1990 { 104, 0x00002c0c, 0x00000a2e, 0x000b8255, 0x000fea0b },
1991 { 108, 0x00002c0c, 0x00000a32, 0x000b8255, 0x000fea13 },
1992 { 112, 0x00002c0c, 0x00000a36, 0x000b8255, 0x000fea1b },
1993 { 116, 0x00002c0c, 0x00000a3a, 0x000b8255, 0x000fea23 },
1994 { 120, 0x00002c0c, 0x00000a82, 0x000b8255, 0x000fea03 },
1995 { 124, 0x00002c0c, 0x00000a86, 0x000b8255, 0x000fea0b },
1996 { 128, 0x00002c0c, 0x00000a8a, 0x000b8255, 0x000fea13 },
1997 { 132, 0x00002c0c, 0x00000a8e, 0x000b8255, 0x000fea1b },
1998 { 136, 0x00002c0c, 0x00000a92, 0x000b8255, 0x000fea23 },
1999
2000 /* 802.11 UNII */
2001 { 140, 0x00002c0c, 0x00000a9a, 0x000b8255, 0x000fea03 },
2002 { 149, 0x00002c0c, 0x00000aa2, 0x000b8255, 0x000fea1f },
2003 { 153, 0x00002c0c, 0x00000aa6, 0x000b8255, 0x000fea27 },
2004 { 157, 0x00002c0c, 0x00000aae, 0x000b8255, 0x000fea07 },
2005 { 161, 0x00002c0c, 0x00000ab2, 0x000b8255, 0x000fea0f },
2006 { 165, 0x00002c0c, 0x00000ab6, 0x000b8255, 0x000fea17 },
2007
2008 /* MMAC(Japan)J52 ch 34,38,42,46 */
2009 { 34, 0x00002c0c, 0x0008099a, 0x000da255, 0x000d3a0b },
2010 { 38, 0x00002c0c, 0x0008099e, 0x000da255, 0x000d3a13 },
2011 { 42, 0x00002c0c, 0x000809a2, 0x000da255, 0x000d3a1b },
2012 { 46, 0x00002c0c, 0x000809a6, 0x000da255, 0x000d3a23 },
2013};
2014
2015/*
2016 * RF value list for RF5225 & RF2527
2017 * Supports: 2.4 GHz & 5.2 GHz
2018 */
2019static const struct rf_channel rf_vals_5225_2527[] = {
2020 { 1, 0x00002ccc, 0x00004786, 0x00068455, 0x000ffa0b },
2021 { 2, 0x00002ccc, 0x00004786, 0x00068455, 0x000ffa1f },
2022 { 3, 0x00002ccc, 0x0000478a, 0x00068455, 0x000ffa0b },
2023 { 4, 0x00002ccc, 0x0000478a, 0x00068455, 0x000ffa1f },
2024 { 5, 0x00002ccc, 0x0000478e, 0x00068455, 0x000ffa0b },
2025 { 6, 0x00002ccc, 0x0000478e, 0x00068455, 0x000ffa1f },
2026 { 7, 0x00002ccc, 0x00004792, 0x00068455, 0x000ffa0b },
2027 { 8, 0x00002ccc, 0x00004792, 0x00068455, 0x000ffa1f },
2028 { 9, 0x00002ccc, 0x00004796, 0x00068455, 0x000ffa0b },
2029 { 10, 0x00002ccc, 0x00004796, 0x00068455, 0x000ffa1f },
2030 { 11, 0x00002ccc, 0x0000479a, 0x00068455, 0x000ffa0b },
2031 { 12, 0x00002ccc, 0x0000479a, 0x00068455, 0x000ffa1f },
2032 { 13, 0x00002ccc, 0x0000479e, 0x00068455, 0x000ffa0b },
2033 { 14, 0x00002ccc, 0x000047a2, 0x00068455, 0x000ffa13 },
2034
2035 /* 802.11 UNI / HyperLan 2 */
2036 { 36, 0x00002ccc, 0x0000499a, 0x0009be55, 0x000ffa23 },
2037 { 40, 0x00002ccc, 0x000049a2, 0x0009be55, 0x000ffa03 },
2038 { 44, 0x00002ccc, 0x000049a6, 0x0009be55, 0x000ffa0b },
2039 { 48, 0x00002ccc, 0x000049aa, 0x0009be55, 0x000ffa13 },
2040 { 52, 0x00002ccc, 0x000049ae, 0x0009ae55, 0x000ffa1b },
2041 { 56, 0x00002ccc, 0x000049b2, 0x0009ae55, 0x000ffa23 },
2042 { 60, 0x00002ccc, 0x000049ba, 0x0009ae55, 0x000ffa03 },
2043 { 64, 0x00002ccc, 0x000049be, 0x0009ae55, 0x000ffa0b },
2044
2045 /* 802.11 HyperLan 2 */
2046 { 100, 0x00002ccc, 0x00004a2a, 0x000bae55, 0x000ffa03 },
2047 { 104, 0x00002ccc, 0x00004a2e, 0x000bae55, 0x000ffa0b },
2048 { 108, 0x00002ccc, 0x00004a32, 0x000bae55, 0x000ffa13 },
2049 { 112, 0x00002ccc, 0x00004a36, 0x000bae55, 0x000ffa1b },
2050 { 116, 0x00002ccc, 0x00004a3a, 0x000bbe55, 0x000ffa23 },
2051 { 120, 0x00002ccc, 0x00004a82, 0x000bbe55, 0x000ffa03 },
2052 { 124, 0x00002ccc, 0x00004a86, 0x000bbe55, 0x000ffa0b },
2053 { 128, 0x00002ccc, 0x00004a8a, 0x000bbe55, 0x000ffa13 },
2054 { 132, 0x00002ccc, 0x00004a8e, 0x000bbe55, 0x000ffa1b },
2055 { 136, 0x00002ccc, 0x00004a92, 0x000bbe55, 0x000ffa23 },
2056
2057 /* 802.11 UNII */
2058 { 140, 0x00002ccc, 0x00004a9a, 0x000bbe55, 0x000ffa03 },
2059 { 149, 0x00002ccc, 0x00004aa2, 0x000bbe55, 0x000ffa1f },
2060 { 153, 0x00002ccc, 0x00004aa6, 0x000bbe55, 0x000ffa27 },
2061 { 157, 0x00002ccc, 0x00004aae, 0x000bbe55, 0x000ffa07 },
2062 { 161, 0x00002ccc, 0x00004ab2, 0x000bbe55, 0x000ffa0f },
2063 { 165, 0x00002ccc, 0x00004ab6, 0x000bbe55, 0x000ffa17 },
2064
2065 /* MMAC(Japan)J52 ch 34,38,42,46 */
2066 { 34, 0x00002ccc, 0x0000499a, 0x0009be55, 0x000ffa0b },
2067 { 38, 0x00002ccc, 0x0000499e, 0x0009be55, 0x000ffa13 },
2068 { 42, 0x00002ccc, 0x000049a2, 0x0009be55, 0x000ffa1b },
2069 { 46, 0x00002ccc, 0x000049a6, 0x0009be55, 0x000ffa23 },
2070};
2071
2072
8c5e7a5f 2073static int rt73usb_probe_hw_mode(struct rt2x00_dev *rt2x00dev)
95ea3627
ID		 2074{
2075 struct hw_mode_spec *spec = &rt2x00dev->spec;
8c5e7a5f
ID		 2076 struct channel_info *info;
2077 char *tx_power;
95ea3627
ID		 2078 unsigned int i;
2079
2080 /*
2081 * Initialize all hw fields.
2082 */
2083 rt2x00dev->hw->flags =
566bfe5a 2084 IEEE80211_HW_HOST_BROADCAST_PS_BUFFERING |
4be8c387
JB		 2085 IEEE80211_HW_SIGNAL_DBM |
2086 IEEE80211_HW_SUPPORTS_PS |
2087 IEEE80211_HW_PS_NULLFUNC_STACK;
95ea3627 2088 rt2x00dev->hw->extra_tx_headroom = TXD_DESC_SIZE;
95ea3627 2089
14a3bf89 2090 SET_IEEE80211_DEV(rt2x00dev->hw, rt2x00dev->dev);
95ea3627
ID		 2091 SET_IEEE80211_PERM_ADDR(rt2x00dev->hw,
2092 rt2x00_eeprom_addr(rt2x00dev,
2093 EEPROM_MAC_ADDR_0));
2094
95ea3627
ID		 2095 /*
2096 * Initialize hw_mode information.
2097 */
31562e80
ID		 2098 spec->supported_bands = SUPPORT_BAND_2GHZ;
2099 spec->supported_rates = SUPPORT_RATE_CCK | SUPPORT_RATE_OFDM;
95ea3627
ID		 2100
2101 if (rt2x00_rf(&rt2x00dev->chip, RF2528)) {
2102 spec->num_channels = ARRAY_SIZE(rf_vals_bg_2528);
2103 spec->channels = rf_vals_bg_2528;
2104 } else if (rt2x00_rf(&rt2x00dev->chip, RF5226)) {
31562e80 2105 spec->supported_bands |= SUPPORT_BAND_5GHZ;
95ea3627
ID		 2106 spec->num_channels = ARRAY_SIZE(rf_vals_5226);
2107 spec->channels = rf_vals_5226;
2108 } else if (rt2x00_rf(&rt2x00dev->chip, RF2527)) {
2109 spec->num_channels = 14;
2110 spec->channels = rf_vals_5225_2527;
2111 } else if (rt2x00_rf(&rt2x00dev->chip, RF5225)) {
31562e80 2112 spec->supported_bands |= SUPPORT_BAND_5GHZ;
95ea3627
ID		 2113 spec->num_channels = ARRAY_SIZE(rf_vals_5225_2527);
2114 spec->channels = rf_vals_5225_2527;
2115 }
2116
8c5e7a5f
ID		 2117 /*
2118 * Create channel information array
2119 */
2120 info = kzalloc(spec->num_channels * sizeof(*info), GFP_KERNEL);
2121 if (!info)
2122 return -ENOMEM;
95ea3627 2123
8c5e7a5f
ID		 2124 spec->channels_info = info;
2125
2126 tx_power = rt2x00_eeprom_addr(rt2x00dev, EEPROM_TXPOWER_G_START);
2127 for (i = 0; i < 14; i++)
2128 info[i].tx_power1 = TXPOWER_FROM_DEV(tx_power[i]);
2129
2130 if (spec->num_channels > 14) {
2131 tx_power = rt2x00_eeprom_addr(rt2x00dev, EEPROM_TXPOWER_A_START);
2132 for (i = 14; i < spec->num_channels; i++)
2133 info[i].tx_power1 = TXPOWER_FROM_DEV(tx_power[i]);
95ea3627 2134 }
8c5e7a5f
ID		 2135
2136 return 0;
95ea3627
ID		 2137}
2138
2139static int rt73usb_probe_hw(struct rt2x00_dev *rt2x00dev)
2140{
2141 int retval;
2142
2143 /*
2144 * Allocate eeprom data.
2145 */
2146 retval = rt73usb_validate_eeprom(rt2x00dev);
2147 if (retval)
2148 return retval;
2149
2150 retval = rt73usb_init_eeprom(rt2x00dev);
2151 if (retval)
2152 return retval;
2153
2154 /*
2155 * Initialize hw specifications.
2156 */
8c5e7a5f
ID		 2157 retval = rt73usb_probe_hw_mode(rt2x00dev);
2158 if (retval)
2159 return retval;
95ea3627
ID		 2160
2161 /*
9404ef34 2162 * This device requires firmware.
95ea3627 2163 */
066cb637 2164 __set_bit(DRIVER_REQUIRE_FIRMWARE, &rt2x00dev->flags);
3a643d24 2165 __set_bit(DRIVER_REQUIRE_SCHEDULED, &rt2x00dev->flags);
008c4482
ID		 2166 if (!modparam_nohwcrypt)
2167 __set_bit(CONFIG_SUPPORT_HW_CRYPTO, &rt2x00dev->flags);
95ea3627
ID		 2168
2169 /*
2170 * Set the rssi offset.
2171 */
2172 rt2x00dev->rssi_offset = DEFAULT_RSSI_OFFSET;
2173
2174 return 0;
2175}
2176
2177/*
2178 * IEEE80211 stack callback functions.
2179 */
2af0a570
ID		 2180static int rt73usb_conf_tx(struct ieee80211_hw *hw, u16 queue_idx,
2181 const struct ieee80211_tx_queue_params *params)
2182{
2183 struct rt2x00_dev *rt2x00dev = hw->priv;
2184 struct data_queue *queue;
2185 struct rt2x00_field32 field;
2186 int retval;
2187 u32 reg;
5e790023 2188 u32 offset;
2af0a570
ID		 2189
2190 /*
2191 * First pass the configuration through rt2x00lib, that will
2192 * update the queue settings and validate the input. After that
2193 * we are free to update the registers based on the value
2194 * in the queue parameter.
2195 */
2196 retval = rt2x00mac_conf_tx(hw, queue_idx, params);
2197 if (retval)
2198 return retval;
2199
5e790023
ID		 2200 /*
2201 * We only need to perform additional register initialization
2202 * for WMM queues/
2203 */
2204 if (queue_idx >= 4)
2205 return 0;
2206
2af0a570
ID		 2207 queue = rt2x00queue_get_queue(rt2x00dev, queue_idx);
2208
2209 /* Update WMM TXOP register */
5e790023
ID		 2210 offset = AC_TXOP_CSR0 + (sizeof(u32) * (!!(queue_idx & 2)));
2211 field.bit_offset = (queue_idx & 1) * 16;
2212 field.bit_mask = 0xffff << field.bit_offset;
2213
2214 rt2x00usb_register_read(rt2x00dev, offset, &reg);
2215 rt2x00_set_field32(&reg, field, queue->txop);
2216 rt2x00usb_register_write(rt2x00dev, offset, reg);
2af0a570
ID		 2217
2218 /* Update WMM registers */
2219 field.bit_offset = queue_idx * 4;
2220 field.bit_mask = 0xf << field.bit_offset;
2221
0f829b1d 2222 rt2x00usb_register_read(rt2x00dev, AIFSN_CSR, &reg);
2af0a570 2223 rt2x00_set_field32(&reg, field, queue->aifs);
0f829b1d 2224 rt2x00usb_register_write(rt2x00dev, AIFSN_CSR, reg);
2af0a570 2225
0f829b1d 2226 rt2x00usb_register_read(rt2x00dev, CWMIN_CSR, &reg);
2af0a570 2227 rt2x00_set_field32(&reg, field, queue->cw_min);
0f829b1d 2228 rt2x00usb_register_write(rt2x00dev, CWMIN_CSR, reg);
2af0a570 2229
0f829b1d 2230 rt2x00usb_register_read(rt2x00dev, CWMAX_CSR, &reg);
2af0a570 2231 rt2x00_set_field32(&reg, field, queue->cw_max);
0f829b1d 2232 rt2x00usb_register_write(rt2x00dev, CWMAX_CSR, reg);
2af0a570
ID		 2233
2234 return 0;
2235}
2236
95ea3627
ID		 2237#if 0
2238/*
2239 * Mac80211 demands get_tsf must be atomic.
2240 * This is not possible for rt73usb since all register access
2241 * functions require sleeping. Untill mac80211 no longer needs
2242 * get_tsf to be atomic, this function should be disabled.
2243 */
2244static u64 rt73usb_get_tsf(struct ieee80211_hw *hw)
2245{
2246 struct rt2x00_dev *rt2x00dev = hw->priv;
2247 u64 tsf;
2248 u32 reg;
2249
0f829b1d 2250 rt2x00usb_register_read(rt2x00dev, TXRX_CSR13, &reg);
95ea3627 2251 tsf = (u64) rt2x00_get_field32(reg, TXRX_CSR13_HIGH_TSFTIMER) << 32;
0f829b1d 2252 rt2x00usb_register_read(rt2x00dev, TXRX_CSR12, &reg);
95ea3627
ID		 2253 tsf |= rt2x00_get_field32(reg, TXRX_CSR12_LOW_TSFTIMER);
2254
2255 return tsf;
2256}
37894473
ID		 2257#else
2258#define rt73usb_get_tsf NULL
95ea3627
ID		 2259#endif
2260
95ea3627
ID		 2261static const struct ieee80211_ops rt73usb_mac80211_ops = {
2262 .tx = rt2x00mac_tx,
4150c572
JB		 2263 .start = rt2x00mac_start,
2264 .stop = rt2x00mac_stop,
95ea3627
ID		 2265 .add_interface = rt2x00mac_add_interface,
2266 .remove_interface = rt2x00mac_remove_interface,
2267 .config = rt2x00mac_config,
2268 .config_interface = rt2x00mac_config_interface,
3a643d24 2269 .configure_filter = rt2x00mac_configure_filter,
906c110f 2270 .set_key = rt2x00mac_set_key,
95ea3627 2271 .get_stats = rt2x00mac_get_stats,
471b3efd 2272 .bss_info_changed = rt2x00mac_bss_info_changed,
2af0a570 2273 .conf_tx = rt73usb_conf_tx,
95ea3627 2274 .get_tx_stats = rt2x00mac_get_tx_stats,
95ea3627 2275 .get_tsf = rt73usb_get_tsf,
95ea3627
ID		 2276};
2277
2278static const struct rt2x00lib_ops rt73usb_rt2x00_ops = {
2279 .probe_hw = rt73usb_probe_hw,
2280 .get_firmware_name = rt73usb_get_firmware_name,
a7f3a06c 2281 .get_firmware_crc = rt73usb_get_firmware_crc,
95ea3627
ID		 2282 .load_firmware = rt73usb_load_firmware,
2283 .initialize = rt2x00usb_initialize,
2284 .uninitialize = rt2x00usb_uninitialize,
798b7adb 2285 .clear_entry = rt2x00usb_clear_entry,
95ea3627 2286 .set_device_state = rt73usb_set_device_state,
7396faf4 2287 .rfkill_poll = rt73usb_rfkill_poll,
95ea3627
ID		 2288 .link_stats = rt73usb_link_stats,
2289 .reset_tuner = rt73usb_reset_tuner,
2290 .link_tuner = rt73usb_link_tuner,
2291 .write_tx_desc = rt73usb_write_tx_desc,
2292 .write_tx_data = rt2x00usb_write_tx_data,
bd88a781 2293 .write_beacon = rt73usb_write_beacon,
dd9fa2d2 2294 .get_tx_data_len = rt73usb_get_tx_data_len,
95ea3627
ID		 2295 .kick_tx_queue = rt73usb_kick_tx_queue,
2296 .fill_rxdone = rt73usb_fill_rxdone,
906c110f
ID		 2297 .config_shared_key = rt73usb_config_shared_key,
2298 .config_pairwise_key = rt73usb_config_pairwise_key,
3a643d24 2299 .config_filter = rt73usb_config_filter,
6bb40dd1 2300 .config_intf = rt73usb_config_intf,
72810379 2301 .config_erp = rt73usb_config_erp,
e4ea1c40 2302 .config_ant = rt73usb_config_ant,
95ea3627
ID		 2303 .config = rt73usb_config,
2304};
2305
181d6902
ID		 2306static const struct data_queue_desc rt73usb_queue_rx = {
2307 .entry_num = RX_ENTRIES,
2308 .data_size = DATA_FRAME_SIZE,
2309 .desc_size = RXD_DESC_SIZE,
b8be63ff 2310 .priv_size = sizeof(struct queue_entry_priv_usb),
181d6902
ID		 2311};
2312
2313static const struct data_queue_desc rt73usb_queue_tx = {
2314 .entry_num = TX_ENTRIES,
2315 .data_size = DATA_FRAME_SIZE,
2316 .desc_size = TXD_DESC_SIZE,
b8be63ff 2317 .priv_size = sizeof(struct queue_entry_priv_usb),
181d6902
ID		 2318};
2319
2320static const struct data_queue_desc rt73usb_queue_bcn = {
6bb40dd1 2321 .entry_num = 4 * BEACON_ENTRIES,
181d6902
ID		 2322 .data_size = MGMT_FRAME_SIZE,
2323 .desc_size = TXINFO_SIZE,
b8be63ff 2324 .priv_size = sizeof(struct queue_entry_priv_usb),
181d6902
ID		 2325};
2326
95ea3627 2327static const struct rt2x00_ops rt73usb_ops = {
2360157c 2328 .name = KBUILD_MODNAME,
6bb40dd1
ID		 2329 .max_sta_intf = 1,
2330 .max_ap_intf = 4,
95ea3627
ID		 2331 .eeprom_size = EEPROM_SIZE,
2332 .rf_size = RF_SIZE,
61448f88 2333 .tx_queues = NUM_TX_QUEUES,
181d6902
ID		 2334 .rx = &rt73usb_queue_rx,
2335 .tx = &rt73usb_queue_tx,
2336 .bcn = &rt73usb_queue_bcn,
95ea3627
ID		 2337 .lib = &rt73usb_rt2x00_ops,
2338 .hw = &rt73usb_mac80211_ops,
2339#ifdef CONFIG_RT2X00_LIB_DEBUGFS
2340 .debugfs = &rt73usb_rt2x00debug,
2341#endif /* CONFIG_RT2X00_LIB_DEBUGFS */
2342};
2343
2344/*
2345 * rt73usb module information.
2346 */
2347static struct usb_device_id rt73usb_device_table[] = {
2348 /* AboCom */
2349 { USB_DEVICE(0x07b8, 0xb21d), USB_DEVICE_DATA(&rt73usb_ops) },
2350 /* Askey */
2351 { USB_DEVICE(0x1690, 0x0722), USB_DEVICE_DATA(&rt73usb_ops) },
2352 /* ASUS */
2353 { USB_DEVICE(0x0b05, 0x1723), USB_DEVICE_DATA(&rt73usb_ops) },
2354 { USB_DEVICE(0x0b05, 0x1724), USB_DEVICE_DATA(&rt73usb_ops) },
2355 /* Belkin */
2356 { USB_DEVICE(0x050d, 0x7050), USB_DEVICE_DATA(&rt73usb_ops) },
2357 { USB_DEVICE(0x050d, 0x705a), USB_DEVICE_DATA(&rt73usb_ops) },
2358 { USB_DEVICE(0x050d, 0x905b), USB_DEVICE_DATA(&rt73usb_ops) },
1f06862e 2359 { USB_DEVICE(0x050d, 0x905c), USB_DEVICE_DATA(&rt73usb_ops) },
95ea3627
ID		 2360 /* Billionton */
2361 { USB_DEVICE(0x1631, 0xc019), USB_DEVICE_DATA(&rt73usb_ops) },
2362 /* Buffalo */
2363 { USB_DEVICE(0x0411, 0x00f4), USB_DEVICE_DATA(&rt73usb_ops) },
2364 /* CNet */
2365 { USB_DEVICE(0x1371, 0x9022), USB_DEVICE_DATA(&rt73usb_ops) },
2366 { USB_DEVICE(0x1371, 0x9032), USB_DEVICE_DATA(&rt73usb_ops) },
2367 /* Conceptronic */
2368 { USB_DEVICE(0x14b2, 0x3c22), USB_DEVICE_DATA(&rt73usb_ops) },
0a74892b
MM		 2369 /* Corega */
2370 { USB_DEVICE(0x07aa, 0x002e), USB_DEVICE_DATA(&rt73usb_ops) },
95ea3627
ID		 2371 /* D-Link */
2372 { USB_DEVICE(0x07d1, 0x3c03), USB_DEVICE_DATA(&rt73usb_ops) },
2373 { USB_DEVICE(0x07d1, 0x3c04), USB_DEVICE_DATA(&rt73usb_ops) },
cb62eccd 2374 { USB_DEVICE(0x07d1, 0x3c06), USB_DEVICE_DATA(&rt73usb_ops) },
445815d7 2375 { USB_DEVICE(0x07d1, 0x3c07), USB_DEVICE_DATA(&rt73usb_ops) },
95ea3627
ID		 2376 /* Gemtek */
2377 { USB_DEVICE(0x15a9, 0x0004), USB_DEVICE_DATA(&rt73usb_ops) },
2378 /* Gigabyte */
2379 { USB_DEVICE(0x1044, 0x8008), USB_DEVICE_DATA(&rt73usb_ops) },
2380 { USB_DEVICE(0x1044, 0x800a), USB_DEVICE_DATA(&rt73usb_ops) },
2381 /* Huawei-3Com */
2382 { USB_DEVICE(0x1472, 0x0009), USB_DEVICE_DATA(&rt73usb_ops) },
2383 /* Hercules */
2384 { USB_DEVICE(0x06f8, 0xe010), USB_DEVICE_DATA(&rt73usb_ops) },
2385 { USB_DEVICE(0x06f8, 0xe020), USB_DEVICE_DATA(&rt73usb_ops) },
2386 /* Linksys */
2387 { USB_DEVICE(0x13b1, 0x0020), USB_DEVICE_DATA(&rt73usb_ops) },
2388 { USB_DEVICE(0x13b1, 0x0023), USB_DEVICE_DATA(&rt73usb_ops) },
3be36ae2 2389 { USB_DEVICE(0x13b1, 0x0028), USB_DEVICE_DATA(&rt73usb_ops) },
95ea3627
ID		 2390 /* MSI */
2391 { USB_DEVICE(0x0db0, 0x6877), USB_DEVICE_DATA(&rt73usb_ops) },
2392 { USB_DEVICE(0x0db0, 0x6874), USB_DEVICE_DATA(&rt73usb_ops) },
2393 { USB_DEVICE(0x0db0, 0xa861), USB_DEVICE_DATA(&rt73usb_ops) },
2394 { USB_DEVICE(0x0db0, 0xa874), USB_DEVICE_DATA(&rt73usb_ops) },
2395 /* Ralink */
2396 { USB_DEVICE(0x148f, 0x2573), USB_DEVICE_DATA(&rt73usb_ops) },
2397 { USB_DEVICE(0x148f, 0x2671), USB_DEVICE_DATA(&rt73usb_ops) },
2398 /* Qcom */
2399 { USB_DEVICE(0x18e8, 0x6196), USB_DEVICE_DATA(&rt73usb_ops) },
2400 { USB_DEVICE(0x18e8, 0x6229), USB_DEVICE_DATA(&rt73usb_ops) },
2401 { USB_DEVICE(0x18e8, 0x6238), USB_DEVICE_DATA(&rt73usb_ops) },
2402 /* Senao */
2403 { USB_DEVICE(0x1740, 0x7100), USB_DEVICE_DATA(&rt73usb_ops) },
2404 /* Sitecom */
2405 { USB_DEVICE(0x0df6, 0x9712), USB_DEVICE_DATA(&rt73usb_ops) },
2406 { USB_DEVICE(0x0df6, 0x90ac), USB_DEVICE_DATA(&rt73usb_ops) },
2407 /* Surecom */
2408 { USB_DEVICE(0x0769, 0x31f3), USB_DEVICE_DATA(&rt73usb_ops) },
2409 /* Planex */
2410 { USB_DEVICE(0x2019, 0xab01), USB_DEVICE_DATA(&rt73usb_ops) },
2411 { USB_DEVICE(0x2019, 0xab50), USB_DEVICE_DATA(&rt73usb_ops) },
2412 { 0, }
2413};
2414
2415MODULE_AUTHOR(DRV_PROJECT);
2416MODULE_VERSION(DRV_VERSION);
2417MODULE_DESCRIPTION("Ralink RT73 USB Wireless LAN driver.");
2418MODULE_SUPPORTED_DEVICE("Ralink RT2571W & RT2671 USB chipset based cards");
2419MODULE_DEVICE_TABLE(usb, rt73usb_device_table);
2420MODULE_FIRMWARE(FIRMWARE_RT2571);
2421MODULE_LICENSE("GPL");
2422
2423static struct usb_driver rt73usb_driver = {
2360157c 2424 .name = KBUILD_MODNAME,
95ea3627
ID		 2425 .id_table = rt73usb_device_table,
2426 .probe = rt2x00usb_probe,
2427 .disconnect = rt2x00usb_disconnect,
2428 .suspend = rt2x00usb_suspend,
2429 .resume = rt2x00usb_resume,
2430};
2431
2432static int __init rt73usb_init(void)
2433{
2434 return usb_register(&rt73usb_driver);
2435}
2436
2437static void __exit rt73usb_exit(void)
2438{
2439 usb_deregister(&rt73usb_driver);
2440}
2441
2442module_init(rt73usb_init);
2443module_exit(rt73usb_exit);
Linux kernel - Deliverables
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