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rt2x00: Fix typo in debug statement
[deliverable/linux.git] / drivers / net / wireless / rt2x00 / rt73usb.c
CommitLineData
95ea3627 1/*
811aa9ca 2 Copyright (C) 2004 - 2008 rt2x00 SourceForge Project
95ea3627
ID		 3 <http://rt2x00.serialmonkey.com>
4
5 This program is free software; you can redistribute it and/or modify
6 it under the terms of the GNU General Public License as published by
7 the Free Software Foundation; either version 2 of the License, or
8 (at your option) any later version.
9
10 This program is distributed in the hope that it will be useful,
11 but WITHOUT ANY WARRANTY; without even the implied warranty of
12 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 GNU General Public License for more details.
14
15 You should have received a copy of the GNU General Public License
16 along with this program; if not, write to the
17 Free Software Foundation, Inc.,
18 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
19 */
20
21/*
22 Module: rt73usb
23 Abstract: rt73usb device specific routines.
24 Supported chipsets: rt2571W & rt2671.
25 */
26
95ea3627
ID		 27#include <linux/delay.h>
28#include <linux/etherdevice.h>
29#include <linux/init.h>
30#include <linux/kernel.h>
31#include <linux/module.h>
32#include <linux/usb.h>
33
34#include "rt2x00.h"
35#include "rt2x00usb.h"
36#include "rt73usb.h"
37
38/*
39 * Register access.
40 * All access to the CSR registers will go through the methods
41 * rt73usb_register_read and rt73usb_register_write.
42 * BBP and RF register require indirect register access,
43 * and use the CSR registers BBPCSR and RFCSR to achieve this.
44 * These indirect registers work with busy bits,
45 * and we will try maximal REGISTER_BUSY_COUNT times to access
46 * the register while taking a REGISTER_BUSY_DELAY us delay
47 * between each attampt. When the busy bit is still set at that time,
48 * the access attempt is considered to have failed,
49 * and we will print an error.
3d82346c 50 * The _lock versions must be used if you already hold the usb_cache_mutex
95ea3627 51 */
0e14f6d3 52static inline void rt73usb_register_read(struct rt2x00_dev *rt2x00dev,
95ea3627
ID		 53 const unsigned int offset, u32 *value)
54{
55 __le32 reg;
56 rt2x00usb_vendor_request_buff(rt2x00dev, USB_MULTI_READ,
57 USB_VENDOR_REQUEST_IN, offset,
58 &reg, sizeof(u32), REGISTER_TIMEOUT);
59 *value = le32_to_cpu(reg);
60}
61
3d82346c
AB		 62static inline void rt73usb_register_read_lock(struct rt2x00_dev *rt2x00dev,
63 const unsigned int offset, u32 *value)
64{
65 __le32 reg;
66 rt2x00usb_vendor_req_buff_lock(rt2x00dev, USB_MULTI_READ,
67 USB_VENDOR_REQUEST_IN, offset,
68 &reg, sizeof(u32), REGISTER_TIMEOUT);
69 *value = le32_to_cpu(reg);
70}
71
0e14f6d3 72static inline void rt73usb_register_multiread(struct rt2x00_dev *rt2x00dev,
95ea3627
ID		 73 const unsigned int offset,
74 void *value, const u32 length)
75{
76 int timeout = REGISTER_TIMEOUT * (length / sizeof(u32));
77 rt2x00usb_vendor_request_buff(rt2x00dev, USB_MULTI_READ,
78 USB_VENDOR_REQUEST_IN, offset,
79 value, length, timeout);
80}
81
0e14f6d3 82static inline void rt73usb_register_write(struct rt2x00_dev *rt2x00dev,
95ea3627
ID		 83 const unsigned int offset, u32 value)
84{
85 __le32 reg = cpu_to_le32(value);
86 rt2x00usb_vendor_request_buff(rt2x00dev, USB_MULTI_WRITE,
87 USB_VENDOR_REQUEST_OUT, offset,
88 &reg, sizeof(u32), REGISTER_TIMEOUT);
89}
90
3d82346c
AB		 91static inline void rt73usb_register_write_lock(struct rt2x00_dev *rt2x00dev,
92 const unsigned int offset, u32 value)
93{
94 __le32 reg = cpu_to_le32(value);
95 rt2x00usb_vendor_req_buff_lock(rt2x00dev, USB_MULTI_WRITE,
96 USB_VENDOR_REQUEST_OUT, offset,
97 &reg, sizeof(u32), REGISTER_TIMEOUT);
98}
99
0e14f6d3 100static inline void rt73usb_register_multiwrite(struct rt2x00_dev *rt2x00dev,
95ea3627
ID		 101 const unsigned int offset,
102 void *value, const u32 length)
103{
104 int timeout = REGISTER_TIMEOUT * (length / sizeof(u32));
105 rt2x00usb_vendor_request_buff(rt2x00dev, USB_MULTI_WRITE,
106 USB_VENDOR_REQUEST_OUT, offset,
107 value, length, timeout);
108}
109
0e14f6d3 110static u32 rt73usb_bbp_check(struct rt2x00_dev *rt2x00dev)
95ea3627
ID		 111{
112 u32 reg;
113 unsigned int i;
114
115 for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
3d82346c 116 rt73usb_register_read_lock(rt2x00dev, PHY_CSR3, &reg);
95ea3627
ID		 117 if (!rt2x00_get_field32(reg, PHY_CSR3_BUSY))
118 break;
119 udelay(REGISTER_BUSY_DELAY);
120 }
121
122 return reg;
123}
124
0e14f6d3 125static void rt73usb_bbp_write(struct rt2x00_dev *rt2x00dev,
95ea3627
ID		 126 const unsigned int word, const u8 value)
127{
128 u32 reg;
129
3d82346c
AB		 130 mutex_lock(&rt2x00dev->usb_cache_mutex);
131
95ea3627
ID		 132 /*
133 * Wait until the BBP becomes ready.
134 */
135 reg = rt73usb_bbp_check(rt2x00dev);
136 if (rt2x00_get_field32(reg, PHY_CSR3_BUSY)) {
137 ERROR(rt2x00dev, "PHY_CSR3 register busy. Write failed.\n");
3d82346c 138 mutex_unlock(&rt2x00dev->usb_cache_mutex);
95ea3627
ID		 139 return;
140 }
141
142 /*
143 * Write the data into the BBP.
144 */
145 reg = 0;
146 rt2x00_set_field32(&reg, PHY_CSR3_VALUE, value);
147 rt2x00_set_field32(&reg, PHY_CSR3_REGNUM, word);
148 rt2x00_set_field32(&reg, PHY_CSR3_BUSY, 1);
149 rt2x00_set_field32(&reg, PHY_CSR3_READ_CONTROL, 0);
150
3d82346c
AB		 151 rt73usb_register_write_lock(rt2x00dev, PHY_CSR3, reg);
152 mutex_unlock(&rt2x00dev->usb_cache_mutex);
95ea3627
ID		 153}
154
0e14f6d3 155static void rt73usb_bbp_read(struct rt2x00_dev *rt2x00dev,
95ea3627
ID		 156 const unsigned int word, u8 *value)
157{
158 u32 reg;
159
3d82346c
AB		 160 mutex_lock(&rt2x00dev->usb_cache_mutex);
161
95ea3627
ID		 162 /*
163 * Wait until the BBP becomes ready.
164 */
165 reg = rt73usb_bbp_check(rt2x00dev);
166 if (rt2x00_get_field32(reg, PHY_CSR3_BUSY)) {
167 ERROR(rt2x00dev, "PHY_CSR3 register busy. Read failed.\n");
3d82346c 168 mutex_unlock(&rt2x00dev->usb_cache_mutex);
95ea3627
ID		 169 return;
170 }
171
172 /*
173 * Write the request into the BBP.
174 */
175 reg = 0;
176 rt2x00_set_field32(&reg, PHY_CSR3_REGNUM, word);
177 rt2x00_set_field32(&reg, PHY_CSR3_BUSY, 1);
178 rt2x00_set_field32(&reg, PHY_CSR3_READ_CONTROL, 1);
179
3d82346c 180 rt73usb_register_write_lock(rt2x00dev, PHY_CSR3, reg);
95ea3627
ID		 181
182 /*
183 * Wait until the BBP becomes ready.
184 */
185 reg = rt73usb_bbp_check(rt2x00dev);
186 if (rt2x00_get_field32(reg, PHY_CSR3_BUSY)) {
187 ERROR(rt2x00dev, "PHY_CSR3 register busy. Read failed.\n");
188 *value = 0xff;
189 return;
190 }
191
192 *value = rt2x00_get_field32(reg, PHY_CSR3_VALUE);
3d82346c 193 mutex_unlock(&rt2x00dev->usb_cache_mutex);
95ea3627
ID		 194}
195
0e14f6d3 196static void rt73usb_rf_write(struct rt2x00_dev *rt2x00dev,
95ea3627
ID		 197 const unsigned int word, const u32 value)
198{
199 u32 reg;
200 unsigned int i;
201
202 if (!word)
203 return;
204
3d82346c
AB		 205 mutex_lock(&rt2x00dev->usb_cache_mutex);
206
95ea3627 207 for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
3d82346c 208 rt73usb_register_read_lock(rt2x00dev, PHY_CSR4, &reg);
95ea3627
ID		 209 if (!rt2x00_get_field32(reg, PHY_CSR4_BUSY))
210 goto rf_write;
211 udelay(REGISTER_BUSY_DELAY);
212 }
213
3d82346c 214 mutex_unlock(&rt2x00dev->usb_cache_mutex);
95ea3627
ID		 215 ERROR(rt2x00dev, "PHY_CSR4 register busy. Write failed.\n");
216 return;
217
218rf_write:
219 reg = 0;
220 rt2x00_set_field32(&reg, PHY_CSR4_VALUE, value);
221
4f5af6eb
ID		 222 /*
223 * RF5225 and RF2527 contain 21 bits per RF register value,
224 * all others contain 20 bits.
225 */
226 rt2x00_set_field32(&reg, PHY_CSR4_NUMBER_OF_BITS,
ddc827f9
ID		 227 20 + (rt2x00_rf(&rt2x00dev->chip, RF5225) ||
228 rt2x00_rf(&rt2x00dev->chip, RF2527)));
95ea3627
ID		 229 rt2x00_set_field32(&reg, PHY_CSR4_IF_SELECT, 0);
230 rt2x00_set_field32(&reg, PHY_CSR4_BUSY, 1);
231
3d82346c 232 rt73usb_register_write_lock(rt2x00dev, PHY_CSR4, reg);
95ea3627 233 rt2x00_rf_write(rt2x00dev, word, value);
3d82346c 234 mutex_unlock(&rt2x00dev->usb_cache_mutex);
95ea3627
ID		 235}
236
237#ifdef CONFIG_RT2X00_LIB_DEBUGFS
238#define CSR_OFFSET(__word) ( CSR_REG_BASE + ((__word) * sizeof(u32)) )
239
0e14f6d3 240static void rt73usb_read_csr(struct rt2x00_dev *rt2x00dev,
95ea3627
ID		 241 const unsigned int word, u32 *data)
242{
243 rt73usb_register_read(rt2x00dev, CSR_OFFSET(word), data);
244}
245
0e14f6d3 246static void rt73usb_write_csr(struct rt2x00_dev *rt2x00dev,
95ea3627
ID		 247 const unsigned int word, u32 data)
248{
249 rt73usb_register_write(rt2x00dev, CSR_OFFSET(word), data);
250}
251
252static const struct rt2x00debug rt73usb_rt2x00debug = {
253 .owner = THIS_MODULE,
254 .csr = {
255 .read = rt73usb_read_csr,
256 .write = rt73usb_write_csr,
257 .word_size = sizeof(u32),
258 .word_count = CSR_REG_SIZE / sizeof(u32),
259 },
260 .eeprom = {
261 .read = rt2x00_eeprom_read,
262 .write = rt2x00_eeprom_write,
263 .word_size = sizeof(u16),
264 .word_count = EEPROM_SIZE / sizeof(u16),
265 },
266 .bbp = {
267 .read = rt73usb_bbp_read,
268 .write = rt73usb_bbp_write,
269 .word_size = sizeof(u8),
270 .word_count = BBP_SIZE / sizeof(u8),
271 },
272 .rf = {
273 .read = rt2x00_rf_read,
274 .write = rt73usb_rf_write,
275 .word_size = sizeof(u32),
276 .word_count = RF_SIZE / sizeof(u32),
277 },
278};
279#endif /* CONFIG_RT2X00_LIB_DEBUGFS */
280
a9450b70
ID		 281#ifdef CONFIG_RT73USB_LEDS
282static void rt73usb_led_brightness(struct led_classdev *led_cdev,
283 enum led_brightness brightness)
284{
285 struct rt2x00_led *led =
286 container_of(led_cdev, struct rt2x00_led, led_dev);
287 unsigned int enabled = brightness != LED_OFF;
288 unsigned int a_mode =
289 (enabled && led->rt2x00dev->curr_band == IEEE80211_BAND_5GHZ);
290 unsigned int bg_mode =
291 (enabled && led->rt2x00dev->curr_band == IEEE80211_BAND_2GHZ);
292
293 if (led->type == LED_TYPE_RADIO) {
294 rt2x00_set_field16(&led->rt2x00dev->led_mcu_reg,
295 MCU_LEDCS_RADIO_STATUS, enabled);
296
3b640f21
ID		 297 rt2x00usb_vendor_request_async(led->rt2x00dev, USB_LED_CONTROL,
298 0, led->rt2x00dev->led_mcu_reg);
a9450b70
ID		 299 } else if (led->type == LED_TYPE_ASSOC) {
300 rt2x00_set_field16(&led->rt2x00dev->led_mcu_reg,
301 MCU_LEDCS_LINK_BG_STATUS, bg_mode);
302 rt2x00_set_field16(&led->rt2x00dev->led_mcu_reg,
303 MCU_LEDCS_LINK_A_STATUS, a_mode);
304
3b640f21
ID		 305 rt2x00usb_vendor_request_async(led->rt2x00dev, USB_LED_CONTROL,
306 0, led->rt2x00dev->led_mcu_reg);
a9450b70
ID		 307 } else if (led->type == LED_TYPE_QUALITY) {
308 /*
309 * The brightness is divided into 6 levels (0 - 5),
310 * this means we need to convert the brightness
311 * argument into the matching level within that range.
312 */
3b640f21
ID		 313 rt2x00usb_vendor_request_async(led->rt2x00dev, USB_LED_CONTROL,
314 brightness / (LED_FULL / 6),
315 led->rt2x00dev->led_mcu_reg);
a9450b70
ID		 316 }
317}
318#else
319#define rt73usb_led_brightness NULL
320#endif /* CONFIG_RT73USB_LEDS */
321
95ea3627
ID		 322/*
323 * Configuration handlers.
324 */
6bb40dd1
ID		 325static void rt73usb_config_intf(struct rt2x00_dev *rt2x00dev,
326 struct rt2x00_intf *intf,
327 struct rt2x00intf_conf *conf,
328 const unsigned int flags)
95ea3627 329{
6bb40dd1
ID		 330 unsigned int beacon_base;
331 u32 reg;
95ea3627 332
6bb40dd1
ID		 333 if (flags & CONFIG_UPDATE_TYPE) {
334 /*
335 * Clear current synchronisation setup.
336 * For the Beacon base registers we only need to clear
337 * the first byte since that byte contains the VALID and OWNER
338 * bits which (when set to 0) will invalidate the entire beacon.
339 */
340 beacon_base = HW_BEACON_OFFSET(intf->beacon->entry_idx);
341 rt73usb_register_write(rt2x00dev, TXRX_CSR9, 0);
342 rt73usb_register_write(rt2x00dev, beacon_base, 0);
95ea3627 343
6bb40dd1
ID		 344 /*
345 * Enable synchronisation.
346 */
347 rt73usb_register_read(rt2x00dev, TXRX_CSR9, &reg);
348 rt2x00_set_field32(&reg, TXRX_CSR9_TSF_TICKING, 1);
349 rt2x00_set_field32(&reg, TXRX_CSR9_TBTT_ENABLE,
350 (conf->sync == TSF_SYNC_BEACON));
351 rt2x00_set_field32(&reg, TXRX_CSR9_BEACON_GEN, 0);
352 rt2x00_set_field32(&reg, TXRX_CSR9_TSF_SYNC, conf->sync);
353 rt73usb_register_write(rt2x00dev, TXRX_CSR9, reg);
354 }
95ea3627 355
6bb40dd1
ID		 356 if (flags & CONFIG_UPDATE_MAC) {
357 reg = le32_to_cpu(conf->mac[1]);
358 rt2x00_set_field32(&reg, MAC_CSR3_UNICAST_TO_ME_MASK, 0xff);
359 conf->mac[1] = cpu_to_le32(reg);
95ea3627 360
6bb40dd1
ID		 361 rt73usb_register_multiwrite(rt2x00dev, MAC_CSR2,
362 conf->mac, sizeof(conf->mac));
363 }
95ea3627 364
6bb40dd1
ID		 365 if (flags & CONFIG_UPDATE_BSSID) {
366 reg = le32_to_cpu(conf->bssid[1]);
367 rt2x00_set_field32(&reg, MAC_CSR5_BSS_ID_MASK, 3);
368 conf->bssid[1] = cpu_to_le32(reg);
95ea3627 369
6bb40dd1
ID		 370 rt73usb_register_multiwrite(rt2x00dev, MAC_CSR4,
371 conf->bssid, sizeof(conf->bssid));
372 }
95ea3627
ID		 373}
374
6bb40dd1
ID		 375static int rt73usb_config_preamble(struct rt2x00_dev *rt2x00dev,
376 const int short_preamble,
377 const int ack_timeout,
378 const int ack_consume_time)
95ea3627 379{
95ea3627 380 u32 reg;
95ea3627 381
5c58ee51 382 /*
6bb40dd1
ID		 383 * When in atomic context, we should let rt2x00lib
384 * try this configuration again later.
5c58ee51 385 */
6bb40dd1
ID		 386 if (in_atomic())
387 return -EAGAIN;
95ea3627
ID		 388
389 rt73usb_register_read(rt2x00dev, TXRX_CSR0, &reg);
5c58ee51 390 rt2x00_set_field32(&reg, TXRX_CSR0_RX_ACK_TIMEOUT, ack_timeout);
95ea3627
ID		 391 rt73usb_register_write(rt2x00dev, TXRX_CSR0, reg);
392
393 rt73usb_register_read(rt2x00dev, TXRX_CSR4, &reg);
4f5af6eb 394 rt2x00_set_field32(&reg, TXRX_CSR4_AUTORESPOND_PREAMBLE,
5c58ee51 395 !!short_preamble);
95ea3627 396 rt73usb_register_write(rt2x00dev, TXRX_CSR4, reg);
6bb40dd1
ID		 397
398 return 0;
95ea3627
ID		 399}
400
401static void rt73usb_config_phymode(struct rt2x00_dev *rt2x00dev,
5c58ee51 402 const int basic_rate_mask)
95ea3627 403{
5c58ee51 404 rt73usb_register_write(rt2x00dev, TXRX_CSR5, basic_rate_mask);
95ea3627
ID		 405}
406
5c58ee51
ID		 407static void rt73usb_config_channel(struct rt2x00_dev *rt2x00dev,
408 struct rf_channel *rf, const int txpower)
95ea3627
ID		 409{
410 u8 r3;
411 u8 r94;
412 u8 smart;
413
414 rt2x00_set_field32(&rf->rf3, RF3_TXPOWER, TXPOWER_TO_DEV(txpower));
415 rt2x00_set_field32(&rf->rf4, RF4_FREQ_OFFSET, rt2x00dev->freq_offset);
416
417 smart = !(rt2x00_rf(&rt2x00dev->chip, RF5225) ||
418 rt2x00_rf(&rt2x00dev->chip, RF2527));
419
420 rt73usb_bbp_read(rt2x00dev, 3, &r3);
421 rt2x00_set_field8(&r3, BBP_R3_SMART_MODE, smart);
422 rt73usb_bbp_write(rt2x00dev, 3, r3);
423
424 r94 = 6;
425 if (txpower > MAX_TXPOWER && txpower <= (MAX_TXPOWER + r94))
426 r94 += txpower - MAX_TXPOWER;
427 else if (txpower < MIN_TXPOWER && txpower >= (MIN_TXPOWER - r94))
428 r94 += txpower;
429 rt73usb_bbp_write(rt2x00dev, 94, r94);
430
431 rt73usb_rf_write(rt2x00dev, 1, rf->rf1);
432 rt73usb_rf_write(rt2x00dev, 2, rf->rf2);
433 rt73usb_rf_write(rt2x00dev, 3, rf->rf3 & ~0x00000004);
434 rt73usb_rf_write(rt2x00dev, 4, rf->rf4);
435
436 rt73usb_rf_write(rt2x00dev, 1, rf->rf1);
437 rt73usb_rf_write(rt2x00dev, 2, rf->rf2);
438 rt73usb_rf_write(rt2x00dev, 3, rf->rf3 | 0x00000004);
439 rt73usb_rf_write(rt2x00dev, 4, rf->rf4);
440
441 rt73usb_rf_write(rt2x00dev, 1, rf->rf1);
442 rt73usb_rf_write(rt2x00dev, 2, rf->rf2);
443 rt73usb_rf_write(rt2x00dev, 3, rf->rf3 & ~0x00000004);
444 rt73usb_rf_write(rt2x00dev, 4, rf->rf4);
445
446 udelay(10);
447}
448
95ea3627
ID		 449static void rt73usb_config_txpower(struct rt2x00_dev *rt2x00dev,
450 const int txpower)
451{
452 struct rf_channel rf;
453
454 rt2x00_rf_read(rt2x00dev, 1, &rf.rf1);
455 rt2x00_rf_read(rt2x00dev, 2, &rf.rf2);
456 rt2x00_rf_read(rt2x00dev, 3, &rf.rf3);
457 rt2x00_rf_read(rt2x00dev, 4, &rf.rf4);
458
5c58ee51 459 rt73usb_config_channel(rt2x00dev, &rf, txpower);
95ea3627
ID		 460}
461
462static void rt73usb_config_antenna_5x(struct rt2x00_dev *rt2x00dev,
addc81bd 463 struct antenna_setup *ant)
95ea3627
ID		 464{
465 u8 r3;
466 u8 r4;
467 u8 r77;
2676c94d 468 u8 temp;
95ea3627
ID		 469
470 rt73usb_bbp_read(rt2x00dev, 3, &r3);
471 rt73usb_bbp_read(rt2x00dev, 4, &r4);
472 rt73usb_bbp_read(rt2x00dev, 77, &r77);
473
474 rt2x00_set_field8(&r3, BBP_R3_SMART_MODE, 0);
475
e4cd2ff8
ID		 476 /*
477 * Configure the RX antenna.
478 */
addc81bd 479 switch (ant->rx) {
95ea3627 480 case ANTENNA_HW_DIVERSITY:
2676c94d
MN		 481 rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA_CONTROL, 2);
482 temp = !test_bit(CONFIG_FRAME_TYPE, &rt2x00dev->flags)
8318d78a 483 && (rt2x00dev->curr_band != IEEE80211_BAND_5GHZ);
2676c94d 484 rt2x00_set_field8(&r4, BBP_R4_RX_FRAME_END, temp);
95ea3627
ID		 485 break;
486 case ANTENNA_A:
2676c94d 487 rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA_CONTROL, 1);
95ea3627 488 rt2x00_set_field8(&r4, BBP_R4_RX_FRAME_END, 0);
8318d78a 489 if (rt2x00dev->curr_band == IEEE80211_BAND_5GHZ)
2676c94d
MN		 490 rt2x00_set_field8(&r77, BBP_R77_RX_ANTENNA, 0);
491 else
492 rt2x00_set_field8(&r77, BBP_R77_RX_ANTENNA, 3);
95ea3627 493 break;
39e75857
ID		 494 case ANTENNA_SW_DIVERSITY:
495 /*
496 * NOTE: We should never come here because rt2x00lib is
497 * supposed to catch this and send us the correct antenna
498 * explicitely. However we are nog going to bug about this.
499 * Instead, just default to antenna B.
500 */
95ea3627 501 case ANTENNA_B:
2676c94d 502 rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA_CONTROL, 1);
95ea3627 503 rt2x00_set_field8(&r4, BBP_R4_RX_FRAME_END, 0);
8318d78a 504 if (rt2x00dev->curr_band == IEEE80211_BAND_5GHZ)
2676c94d
MN		 505 rt2x00_set_field8(&r77, BBP_R77_RX_ANTENNA, 3);
506 else
507 rt2x00_set_field8(&r77, BBP_R77_RX_ANTENNA, 0);
95ea3627
ID		 508 break;
509 }
510
511 rt73usb_bbp_write(rt2x00dev, 77, r77);
512 rt73usb_bbp_write(rt2x00dev, 3, r3);
513 rt73usb_bbp_write(rt2x00dev, 4, r4);
514}
515
516static void rt73usb_config_antenna_2x(struct rt2x00_dev *rt2x00dev,
addc81bd 517 struct antenna_setup *ant)
95ea3627
ID		 518{
519 u8 r3;
520 u8 r4;
521 u8 r77;
522
523 rt73usb_bbp_read(rt2x00dev, 3, &r3);
524 rt73usb_bbp_read(rt2x00dev, 4, &r4);
525 rt73usb_bbp_read(rt2x00dev, 77, &r77);
526
527 rt2x00_set_field8(&r3, BBP_R3_SMART_MODE, 0);
528 rt2x00_set_field8(&r4, BBP_R4_RX_FRAME_END,
529 !test_bit(CONFIG_FRAME_TYPE, &rt2x00dev->flags));
530
e4cd2ff8
ID		 531 /*
532 * Configure the RX antenna.
533 */
addc81bd 534 switch (ant->rx) {
95ea3627 535 case ANTENNA_HW_DIVERSITY:
2676c94d 536 rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA_CONTROL, 2);
95ea3627
ID		 537 break;
538 case ANTENNA_A:
2676c94d
MN		 539 rt2x00_set_field8(&r77, BBP_R77_RX_ANTENNA, 3);
540 rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA_CONTROL, 1);
95ea3627 541 break;
39e75857
ID		 542 case ANTENNA_SW_DIVERSITY:
543 /*
544 * NOTE: We should never come here because rt2x00lib is
545 * supposed to catch this and send us the correct antenna
546 * explicitely. However we are nog going to bug about this.
547 * Instead, just default to antenna B.
548 */
95ea3627 549 case ANTENNA_B:
2676c94d
MN		 550 rt2x00_set_field8(&r77, BBP_R77_RX_ANTENNA, 0);
551 rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA_CONTROL, 1);
95ea3627
ID		 552 break;
553 }
554
555 rt73usb_bbp_write(rt2x00dev, 77, r77);
556 rt73usb_bbp_write(rt2x00dev, 3, r3);
557 rt73usb_bbp_write(rt2x00dev, 4, r4);
558}
559
560struct antenna_sel {
561 u8 word;
562 /*
563 * value[0] -> non-LNA
564 * value[1] -> LNA
565 */
566 u8 value[2];
567};
568
569static const struct antenna_sel antenna_sel_a[] = {
570 { 96, { 0x58, 0x78 } },
571 { 104, { 0x38, 0x48 } },
572 { 75, { 0xfe, 0x80 } },
573 { 86, { 0xfe, 0x80 } },
574 { 88, { 0xfe, 0x80 } },
575 { 35, { 0x60, 0x60 } },
576 { 97, { 0x58, 0x58 } },
577 { 98, { 0x58, 0x58 } },
578};
579
580static const struct antenna_sel antenna_sel_bg[] = {
581 { 96, { 0x48, 0x68 } },
582 { 104, { 0x2c, 0x3c } },
583 { 75, { 0xfe, 0x80 } },
584 { 86, { 0xfe, 0x80 } },
585 { 88, { 0xfe, 0x80 } },
586 { 35, { 0x50, 0x50 } },
587 { 97, { 0x48, 0x48 } },
588 { 98, { 0x48, 0x48 } },
589};
590
591static void rt73usb_config_antenna(struct rt2x00_dev *rt2x00dev,
addc81bd 592 struct antenna_setup *ant)
95ea3627
ID		 593{
594 const struct antenna_sel *sel;
595 unsigned int lna;
596 unsigned int i;
597 u32 reg;
598
8318d78a 599 if (rt2x00dev->curr_band == IEEE80211_BAND_5GHZ) {
95ea3627
ID		 600 sel = antenna_sel_a;
601 lna = test_bit(CONFIG_EXTERNAL_LNA_A, &rt2x00dev->flags);
95ea3627
ID		 602 } else {
603 sel = antenna_sel_bg;
604 lna = test_bit(CONFIG_EXTERNAL_LNA_BG, &rt2x00dev->flags);
95ea3627
ID		 605 }
606
2676c94d
MN		 607 for (i = 0; i < ARRAY_SIZE(antenna_sel_a); i++)
608 rt73usb_bbp_write(rt2x00dev, sel[i].word, sel[i].value[lna]);
609
610 rt73usb_register_read(rt2x00dev, PHY_CSR0, &reg);
611
ddc827f9 612 rt2x00_set_field32(&reg, PHY_CSR0_PA_PE_BG,
8318d78a 613 (rt2x00dev->curr_band == IEEE80211_BAND_2GHZ));
ddc827f9 614 rt2x00_set_field32(&reg, PHY_CSR0_PA_PE_A,
8318d78a 615 (rt2x00dev->curr_band == IEEE80211_BAND_5GHZ));
ddc827f9 616
95ea3627
ID		 617 rt73usb_register_write(rt2x00dev, PHY_CSR0, reg);
618
619 if (rt2x00_rf(&rt2x00dev->chip, RF5226) ||
620 rt2x00_rf(&rt2x00dev->chip, RF5225))
addc81bd 621 rt73usb_config_antenna_5x(rt2x00dev, ant);
95ea3627
ID		 622 else if (rt2x00_rf(&rt2x00dev->chip, RF2528) ||
623 rt2x00_rf(&rt2x00dev->chip, RF2527))
addc81bd 624 rt73usb_config_antenna_2x(rt2x00dev, ant);
95ea3627
ID		 625}
626
627static void rt73usb_config_duration(struct rt2x00_dev *rt2x00dev,
5c58ee51 628 struct rt2x00lib_conf *libconf)
95ea3627
ID		 629{
630 u32 reg;
631
632 rt73usb_register_read(rt2x00dev, MAC_CSR9, &reg);
5c58ee51 633 rt2x00_set_field32(&reg, MAC_CSR9_SLOT_TIME, libconf->slot_time);
95ea3627
ID		 634 rt73usb_register_write(rt2x00dev, MAC_CSR9, reg);
635
636 rt73usb_register_read(rt2x00dev, MAC_CSR8, &reg);
5c58ee51 637 rt2x00_set_field32(&reg, MAC_CSR8_SIFS, libconf->sifs);
95ea3627 638 rt2x00_set_field32(&reg, MAC_CSR8_SIFS_AFTER_RX_OFDM, 3);
5c58ee51 639 rt2x00_set_field32(&reg, MAC_CSR8_EIFS, libconf->eifs);
95ea3627
ID		 640 rt73usb_register_write(rt2x00dev, MAC_CSR8, reg);
641
642 rt73usb_register_read(rt2x00dev, TXRX_CSR0, &reg);
643 rt2x00_set_field32(&reg, TXRX_CSR0_TSF_OFFSET, IEEE80211_HEADER);
644 rt73usb_register_write(rt2x00dev, TXRX_CSR0, reg);
645
646 rt73usb_register_read(rt2x00dev, TXRX_CSR4, &reg);
647 rt2x00_set_field32(&reg, TXRX_CSR4_AUTORESPOND_ENABLE, 1);
648 rt73usb_register_write(rt2x00dev, TXRX_CSR4, reg);
649
650 rt73usb_register_read(rt2x00dev, TXRX_CSR9, &reg);
5c58ee51
ID		 651 rt2x00_set_field32(&reg, TXRX_CSR9_BEACON_INTERVAL,
652 libconf->conf->beacon_int * 16);
95ea3627
ID		 653 rt73usb_register_write(rt2x00dev, TXRX_CSR9, reg);
654}
655
656static void rt73usb_config(struct rt2x00_dev *rt2x00dev,
6bb40dd1
ID		 657 struct rt2x00lib_conf *libconf,
658 const unsigned int flags)
95ea3627 659{
95ea3627 660 if (flags & CONFIG_UPDATE_PHYMODE)
5c58ee51 661 rt73usb_config_phymode(rt2x00dev, libconf->basic_rates);
95ea3627 662 if (flags & CONFIG_UPDATE_CHANNEL)
5c58ee51
ID		 663 rt73usb_config_channel(rt2x00dev, &libconf->rf,
664 libconf->conf->power_level);
95ea3627 665 if ((flags & CONFIG_UPDATE_TXPOWER) && !(flags & CONFIG_UPDATE_CHANNEL))
5c58ee51 666 rt73usb_config_txpower(rt2x00dev, libconf->conf->power_level);
95ea3627 667 if (flags & CONFIG_UPDATE_ANTENNA)
addc81bd 668 rt73usb_config_antenna(rt2x00dev, &libconf->ant);
95ea3627 669 if (flags & (CONFIG_UPDATE_SLOT_TIME | CONFIG_UPDATE_BEACON_INT))
5c58ee51 670 rt73usb_config_duration(rt2x00dev, libconf);
95ea3627
ID		 671}
672
95ea3627
ID		 673/*
674 * Link tuning
675 */
ebcf26da
ID		 676static void rt73usb_link_stats(struct rt2x00_dev *rt2x00dev,
677 struct link_qual *qual)
95ea3627
ID		 678{
679 u32 reg;
680
681 /*
682 * Update FCS error count from register.
683 */
684 rt73usb_register_read(rt2x00dev, STA_CSR0, &reg);
ebcf26da 685 qual->rx_failed = rt2x00_get_field32(reg, STA_CSR0_FCS_ERROR);
95ea3627
ID		 686
687 /*
688 * Update False CCA count from register.
689 */
690 rt73usb_register_read(rt2x00dev, STA_CSR1, &reg);
ebcf26da 691 qual->false_cca = rt2x00_get_field32(reg, STA_CSR1_FALSE_CCA_ERROR);
95ea3627
ID		 692}
693
694static void rt73usb_reset_tuner(struct rt2x00_dev *rt2x00dev)
695{
696 rt73usb_bbp_write(rt2x00dev, 17, 0x20);
697 rt2x00dev->link.vgc_level = 0x20;
698}
699
700static void rt73usb_link_tuner(struct rt2x00_dev *rt2x00dev)
701{
702 int rssi = rt2x00_get_link_rssi(&rt2x00dev->link);
703 u8 r17;
704 u8 up_bound;
705 u8 low_bound;
706
95ea3627
ID		 707 rt73usb_bbp_read(rt2x00dev, 17, &r17);
708
709 /*
710 * Determine r17 bounds.
711 */
8318d78a 712 if (rt2x00dev->rx_status.band == IEEE80211_BAND_5GHZ) {
95ea3627
ID		 713 low_bound = 0x28;
714 up_bound = 0x48;
715
716 if (test_bit(CONFIG_EXTERNAL_LNA_A, &rt2x00dev->flags)) {
717 low_bound += 0x10;
718 up_bound += 0x10;
719 }
720 } else {
721 if (rssi > -82) {
722 low_bound = 0x1c;
723 up_bound = 0x40;
724 } else if (rssi > -84) {
725 low_bound = 0x1c;
726 up_bound = 0x20;
727 } else {
728 low_bound = 0x1c;
729 up_bound = 0x1c;
730 }
731
732 if (test_bit(CONFIG_EXTERNAL_LNA_BG, &rt2x00dev->flags)) {
733 low_bound += 0x14;
734 up_bound += 0x10;
735 }
736 }
737
6bb40dd1
ID		 738 /*
739 * If we are not associated, we should go straight to the
740 * dynamic CCA tuning.
741 */
742 if (!rt2x00dev->intf_associated)
743 goto dynamic_cca_tune;
744
95ea3627
ID		 745 /*
746 * Special big-R17 for very short distance
747 */
748 if (rssi > -35) {
749 if (r17 != 0x60)
750 rt73usb_bbp_write(rt2x00dev, 17, 0x60);
751 return;
752 }
753
754 /*
755 * Special big-R17 for short distance
756 */
757 if (rssi >= -58) {
758 if (r17 != up_bound)
759 rt73usb_bbp_write(rt2x00dev, 17, up_bound);
760 return;
761 }
762
763 /*
764 * Special big-R17 for middle-short distance
765 */
766 if (rssi >= -66) {
767 low_bound += 0x10;
768 if (r17 != low_bound)
769 rt73usb_bbp_write(rt2x00dev, 17, low_bound);
770 return;
771 }
772
773 /*
774 * Special mid-R17 for middle distance
775 */
776 if (rssi >= -74) {
777 if (r17 != (low_bound + 0x10))
778 rt73usb_bbp_write(rt2x00dev, 17, low_bound + 0x08);
779 return;
780 }
781
782 /*
783 * Special case: Change up_bound based on the rssi.
784 * Lower up_bound when rssi is weaker then -74 dBm.
785 */
786 up_bound -= 2 * (-74 - rssi);
787 if (low_bound > up_bound)
788 up_bound = low_bound;
789
790 if (r17 > up_bound) {
791 rt73usb_bbp_write(rt2x00dev, 17, up_bound);
792 return;
793 }
794
6bb40dd1
ID		 795dynamic_cca_tune:
796
95ea3627
ID		 797 /*
798 * r17 does not yet exceed upper limit, continue and base
799 * the r17 tuning on the false CCA count.
800 */
ebcf26da 801 if (rt2x00dev->link.qual.false_cca > 512 && r17 < up_bound) {
95ea3627
ID		 802 r17 += 4;
803 if (r17 > up_bound)
804 r17 = up_bound;
805 rt73usb_bbp_write(rt2x00dev, 17, r17);
ebcf26da 806 } else if (rt2x00dev->link.qual.false_cca < 100 && r17 > low_bound) {
95ea3627
ID		 807 r17 -= 4;
808 if (r17 < low_bound)
809 r17 = low_bound;
810 rt73usb_bbp_write(rt2x00dev, 17, r17);
811 }
812}
813
814/*
815 * Firmware name function.
816 */
817static char *rt73usb_get_firmware_name(struct rt2x00_dev *rt2x00dev)
818{
819 return FIRMWARE_RT2571;
820}
821
822/*
823 * Initialization functions.
824 */
825static int rt73usb_load_firmware(struct rt2x00_dev *rt2x00dev, void *data,
826 const size_t len)
827{
828 unsigned int i;
829 int status;
830 u32 reg;
831 char *ptr = data;
832 char *cache;
833 int buflen;
834 int timeout;
835
836 /*
837 * Wait for stable hardware.
838 */
839 for (i = 0; i < 100; i++) {
840 rt73usb_register_read(rt2x00dev, MAC_CSR0, &reg);
841 if (reg)
842 break;
843 msleep(1);
844 }
845
846 if (!reg) {
847 ERROR(rt2x00dev, "Unstable hardware.\n");
848 return -EBUSY;
849 }
850
851 /*
852 * Write firmware to device.
853 * We setup a seperate cache for this action,
854 * since we are going to write larger chunks of data
855 * then normally used cache size.
856 */
857 cache = kmalloc(CSR_CACHE_SIZE_FIRMWARE, GFP_KERNEL);
858 if (!cache) {
859 ERROR(rt2x00dev, "Failed to allocate firmware cache.\n");
860 return -ENOMEM;
861 }
862
863 for (i = 0; i < len; i += CSR_CACHE_SIZE_FIRMWARE) {
864 buflen = min_t(int, len - i, CSR_CACHE_SIZE_FIRMWARE);
865 timeout = REGISTER_TIMEOUT * (buflen / sizeof(u32));
866
867 memcpy(cache, ptr, buflen);
868
869 rt2x00usb_vendor_request(rt2x00dev, USB_MULTI_WRITE,
870 USB_VENDOR_REQUEST_OUT,
3b640f21 871 FIRMWARE_IMAGE_BASE + i, 0,
95ea3627
ID		 872 cache, buflen, timeout);
873
874 ptr += buflen;
875 }
876
877 kfree(cache);
878
879 /*
880 * Send firmware request to device to load firmware,
881 * we need to specify a long timeout time.
882 */
883 status = rt2x00usb_vendor_request_sw(rt2x00dev, USB_DEVICE_MODE,
3b640f21 884 0, USB_MODE_FIRMWARE,
95ea3627
ID		 885 REGISTER_TIMEOUT_FIRMWARE);
886 if (status < 0) {
887 ERROR(rt2x00dev, "Failed to write Firmware to device.\n");
888 return status;
889 }
890
95ea3627
ID		 891 return 0;
892}
893
894static int rt73usb_init_registers(struct rt2x00_dev *rt2x00dev)
895{
896 u32 reg;
897
898 rt73usb_register_read(rt2x00dev, TXRX_CSR0, &reg);
899 rt2x00_set_field32(&reg, TXRX_CSR0_AUTO_TX_SEQ, 1);
900 rt2x00_set_field32(&reg, TXRX_CSR0_DISABLE_RX, 0);
901 rt2x00_set_field32(&reg, TXRX_CSR0_TX_WITHOUT_WAITING, 0);
902 rt73usb_register_write(rt2x00dev, TXRX_CSR0, reg);
903
904 rt73usb_register_read(rt2x00dev, TXRX_CSR1, &reg);
905 rt2x00_set_field32(&reg, TXRX_CSR1_BBP_ID0, 47); /* CCK Signal */
906 rt2x00_set_field32(&reg, TXRX_CSR1_BBP_ID0_VALID, 1);
907 rt2x00_set_field32(&reg, TXRX_CSR1_BBP_ID1, 30); /* Rssi */
908 rt2x00_set_field32(&reg, TXRX_CSR1_BBP_ID1_VALID, 1);
909 rt2x00_set_field32(&reg, TXRX_CSR1_BBP_ID2, 42); /* OFDM Rate */
910 rt2x00_set_field32(&reg, TXRX_CSR1_BBP_ID2_VALID, 1);
911 rt2x00_set_field32(&reg, TXRX_CSR1_BBP_ID3, 30); /* Rssi */
912 rt2x00_set_field32(&reg, TXRX_CSR1_BBP_ID3_VALID, 1);
913 rt73usb_register_write(rt2x00dev, TXRX_CSR1, reg);
914
915 /*
916 * CCK TXD BBP registers
917 */
918 rt73usb_register_read(rt2x00dev, TXRX_CSR2, &reg);
919 rt2x00_set_field32(&reg, TXRX_CSR2_BBP_ID0, 13);
920 rt2x00_set_field32(&reg, TXRX_CSR2_BBP_ID0_VALID, 1);
921 rt2x00_set_field32(&reg, TXRX_CSR2_BBP_ID1, 12);
922 rt2x00_set_field32(&reg, TXRX_CSR2_BBP_ID1_VALID, 1);
923 rt2x00_set_field32(&reg, TXRX_CSR2_BBP_ID2, 11);
924 rt2x00_set_field32(&reg, TXRX_CSR2_BBP_ID2_VALID, 1);
925 rt2x00_set_field32(&reg, TXRX_CSR2_BBP_ID3, 10);
926 rt2x00_set_field32(&reg, TXRX_CSR2_BBP_ID3_VALID, 1);
927 rt73usb_register_write(rt2x00dev, TXRX_CSR2, reg);
928
929 /*
930 * OFDM TXD BBP registers
931 */
932 rt73usb_register_read(rt2x00dev, TXRX_CSR3, &reg);
933 rt2x00_set_field32(&reg, TXRX_CSR3_BBP_ID0, 7);
934 rt2x00_set_field32(&reg, TXRX_CSR3_BBP_ID0_VALID, 1);
935 rt2x00_set_field32(&reg, TXRX_CSR3_BBP_ID1, 6);
936 rt2x00_set_field32(&reg, TXRX_CSR3_BBP_ID1_VALID, 1);
937 rt2x00_set_field32(&reg, TXRX_CSR3_BBP_ID2, 5);
938 rt2x00_set_field32(&reg, TXRX_CSR3_BBP_ID2_VALID, 1);
939 rt73usb_register_write(rt2x00dev, TXRX_CSR3, reg);
940
941 rt73usb_register_read(rt2x00dev, TXRX_CSR7, &reg);
942 rt2x00_set_field32(&reg, TXRX_CSR7_ACK_CTS_6MBS, 59);
943 rt2x00_set_field32(&reg, TXRX_CSR7_ACK_CTS_9MBS, 53);
944 rt2x00_set_field32(&reg, TXRX_CSR7_ACK_CTS_12MBS, 49);
945 rt2x00_set_field32(&reg, TXRX_CSR7_ACK_CTS_18MBS, 46);
946 rt73usb_register_write(rt2x00dev, TXRX_CSR7, reg);
947
948 rt73usb_register_read(rt2x00dev, TXRX_CSR8, &reg);
949 rt2x00_set_field32(&reg, TXRX_CSR8_ACK_CTS_24MBS, 44);
950 rt2x00_set_field32(&reg, TXRX_CSR8_ACK_CTS_36MBS, 42);
951 rt2x00_set_field32(&reg, TXRX_CSR8_ACK_CTS_48MBS, 42);
952 rt2x00_set_field32(&reg, TXRX_CSR8_ACK_CTS_54MBS, 42);
953 rt73usb_register_write(rt2x00dev, TXRX_CSR8, reg);
954
955 rt73usb_register_write(rt2x00dev, TXRX_CSR15, 0x0000000f);
956
957 rt73usb_register_read(rt2x00dev, MAC_CSR6, &reg);
958 rt2x00_set_field32(&reg, MAC_CSR6_MAX_FRAME_UNIT, 0xfff);
959 rt73usb_register_write(rt2x00dev, MAC_CSR6, reg);
960
961 rt73usb_register_write(rt2x00dev, MAC_CSR10, 0x00000718);
962
963 if (rt2x00dev->ops->lib->set_device_state(rt2x00dev, STATE_AWAKE))
964 return -EBUSY;
965
966 rt73usb_register_write(rt2x00dev, MAC_CSR13, 0x00007f00);
967
a9450b70
ID		 968 rt73usb_register_read(rt2x00dev, MAC_CSR14, &reg);
969 rt2x00_set_field32(&reg, MAC_CSR14_ON_PERIOD, 70);
970 rt2x00_set_field32(&reg, MAC_CSR14_OFF_PERIOD, 30);
971 rt73usb_register_write(rt2x00dev, MAC_CSR14, reg);
972
95ea3627
ID		 973 /*
974 * Invalidate all Shared Keys (SEC_CSR0),
975 * and clear the Shared key Cipher algorithms (SEC_CSR1 & SEC_CSR5)
976 */
977 rt73usb_register_write(rt2x00dev, SEC_CSR0, 0x00000000);
978 rt73usb_register_write(rt2x00dev, SEC_CSR1, 0x00000000);
979 rt73usb_register_write(rt2x00dev, SEC_CSR5, 0x00000000);
980
981 reg = 0x000023b0;
982 if (rt2x00_rf(&rt2x00dev->chip, RF5225) ||
983 rt2x00_rf(&rt2x00dev->chip, RF2527))
984 rt2x00_set_field32(&reg, PHY_CSR1_RF_RPI, 1);
985 rt73usb_register_write(rt2x00dev, PHY_CSR1, reg);
986
987 rt73usb_register_write(rt2x00dev, PHY_CSR5, 0x00040a06);
988 rt73usb_register_write(rt2x00dev, PHY_CSR6, 0x00080606);
989 rt73usb_register_write(rt2x00dev, PHY_CSR7, 0x00000408);
990
991 rt73usb_register_read(rt2x00dev, AC_TXOP_CSR0, &reg);
992 rt2x00_set_field32(&reg, AC_TXOP_CSR0_AC0_TX_OP, 0);
993 rt2x00_set_field32(&reg, AC_TXOP_CSR0_AC1_TX_OP, 0);
994 rt73usb_register_write(rt2x00dev, AC_TXOP_CSR0, reg);
995
996 rt73usb_register_read(rt2x00dev, AC_TXOP_CSR1, &reg);
997 rt2x00_set_field32(&reg, AC_TXOP_CSR1_AC2_TX_OP, 192);
998 rt2x00_set_field32(&reg, AC_TXOP_CSR1_AC3_TX_OP, 48);
999 rt73usb_register_write(rt2x00dev, AC_TXOP_CSR1, reg);
1000
1001 rt73usb_register_read(rt2x00dev, MAC_CSR9, &reg);
1002 rt2x00_set_field32(&reg, MAC_CSR9_CW_SELECT, 0);
1003 rt73usb_register_write(rt2x00dev, MAC_CSR9, reg);
1004
6bb40dd1
ID		 1005 /*
1006 * Clear all beacons
1007 * For the Beacon base registers we only need to clear
1008 * the first byte since that byte contains the VALID and OWNER
1009 * bits which (when set to 0) will invalidate the entire beacon.
1010 */
1011 rt73usb_register_write(rt2x00dev, HW_BEACON_BASE0, 0);
1012 rt73usb_register_write(rt2x00dev, HW_BEACON_BASE1, 0);
1013 rt73usb_register_write(rt2x00dev, HW_BEACON_BASE2, 0);
1014 rt73usb_register_write(rt2x00dev, HW_BEACON_BASE3, 0);
1015
95ea3627
ID		 1016 /*
1017 * We must clear the error counters.
1018 * These registers are cleared on read,
1019 * so we may pass a useless variable to store the value.
1020 */
1021 rt73usb_register_read(rt2x00dev, STA_CSR0, &reg);
1022 rt73usb_register_read(rt2x00dev, STA_CSR1, &reg);
1023 rt73usb_register_read(rt2x00dev, STA_CSR2, &reg);
1024
1025 /*
1026 * Reset MAC and BBP registers.
1027 */
1028 rt73usb_register_read(rt2x00dev, MAC_CSR1, &reg);
1029 rt2x00_set_field32(&reg, MAC_CSR1_SOFT_RESET, 1);
1030 rt2x00_set_field32(&reg, MAC_CSR1_BBP_RESET, 1);
1031 rt73usb_register_write(rt2x00dev, MAC_CSR1, reg);
1032
1033 rt73usb_register_read(rt2x00dev, MAC_CSR1, &reg);
1034 rt2x00_set_field32(&reg, MAC_CSR1_SOFT_RESET, 0);
1035 rt2x00_set_field32(&reg, MAC_CSR1_BBP_RESET, 0);
1036 rt73usb_register_write(rt2x00dev, MAC_CSR1, reg);
1037
1038 rt73usb_register_read(rt2x00dev, MAC_CSR1, &reg);
1039 rt2x00_set_field32(&reg, MAC_CSR1_HOST_READY, 1);
1040 rt73usb_register_write(rt2x00dev, MAC_CSR1, reg);
1041
1042 return 0;
1043}
1044
1045static int rt73usb_init_bbp(struct rt2x00_dev *rt2x00dev)
1046{
1047 unsigned int i;
1048 u16 eeprom;
1049 u8 reg_id;
1050 u8 value;
1051
1052 for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
1053 rt73usb_bbp_read(rt2x00dev, 0, &value);
1054 if ((value != 0xff) && (value != 0x00))
1055 goto continue_csr_init;
1056 NOTICE(rt2x00dev, "Waiting for BBP register.\n");
1057 udelay(REGISTER_BUSY_DELAY);
1058 }
1059
1060 ERROR(rt2x00dev, "BBP register access failed, aborting.\n");
1061 return -EACCES;
1062
1063continue_csr_init:
1064 rt73usb_bbp_write(rt2x00dev, 3, 0x80);
1065 rt73usb_bbp_write(rt2x00dev, 15, 0x30);
1066 rt73usb_bbp_write(rt2x00dev, 21, 0xc8);
1067 rt73usb_bbp_write(rt2x00dev, 22, 0x38);
1068 rt73usb_bbp_write(rt2x00dev, 23, 0x06);
1069 rt73usb_bbp_write(rt2x00dev, 24, 0xfe);
1070 rt73usb_bbp_write(rt2x00dev, 25, 0x0a);
1071 rt73usb_bbp_write(rt2x00dev, 26, 0x0d);
1072 rt73usb_bbp_write(rt2x00dev, 32, 0x0b);
1073 rt73usb_bbp_write(rt2x00dev, 34, 0x12);
1074 rt73usb_bbp_write(rt2x00dev, 37, 0x07);
1075 rt73usb_bbp_write(rt2x00dev, 39, 0xf8);
1076 rt73usb_bbp_write(rt2x00dev, 41, 0x60);
1077 rt73usb_bbp_write(rt2x00dev, 53, 0x10);
1078 rt73usb_bbp_write(rt2x00dev, 54, 0x18);
1079 rt73usb_bbp_write(rt2x00dev, 60, 0x10);
1080 rt73usb_bbp_write(rt2x00dev, 61, 0x04);
1081 rt73usb_bbp_write(rt2x00dev, 62, 0x04);
1082 rt73usb_bbp_write(rt2x00dev, 75, 0xfe);
1083 rt73usb_bbp_write(rt2x00dev, 86, 0xfe);
1084 rt73usb_bbp_write(rt2x00dev, 88, 0xfe);
1085 rt73usb_bbp_write(rt2x00dev, 90, 0x0f);
1086 rt73usb_bbp_write(rt2x00dev, 99, 0x00);
1087 rt73usb_bbp_write(rt2x00dev, 102, 0x16);
1088 rt73usb_bbp_write(rt2x00dev, 107, 0x04);
1089
95ea3627
ID		 1090 for (i = 0; i < EEPROM_BBP_SIZE; i++) {
1091 rt2x00_eeprom_read(rt2x00dev, EEPROM_BBP_START + i, &eeprom);
1092
1093 if (eeprom != 0xffff && eeprom != 0x0000) {
1094 reg_id = rt2x00_get_field16(eeprom, EEPROM_BBP_REG_ID);
1095 value = rt2x00_get_field16(eeprom, EEPROM_BBP_VALUE);
95ea3627
ID		 1096 rt73usb_bbp_write(rt2x00dev, reg_id, value);
1097 }
1098 }
95ea3627
ID		 1099
1100 return 0;
1101}
1102
1103/*
1104 * Device state switch handlers.
1105 */
1106static void rt73usb_toggle_rx(struct rt2x00_dev *rt2x00dev,
1107 enum dev_state state)
1108{
1109 u32 reg;
1110
1111 rt73usb_register_read(rt2x00dev, TXRX_CSR0, &reg);
1112 rt2x00_set_field32(&reg, TXRX_CSR0_DISABLE_RX,
1113 state == STATE_RADIO_RX_OFF);
1114 rt73usb_register_write(rt2x00dev, TXRX_CSR0, reg);
1115}
1116
1117static int rt73usb_enable_radio(struct rt2x00_dev *rt2x00dev)
1118{
1119 /*
1120 * Initialize all registers.
1121 */
1122 if (rt73usb_init_registers(rt2x00dev) ||
1123 rt73usb_init_bbp(rt2x00dev)) {
1124 ERROR(rt2x00dev, "Register initialization failed.\n");
1125 return -EIO;
1126 }
1127
95ea3627
ID		 1128 return 0;
1129}
1130
1131static void rt73usb_disable_radio(struct rt2x00_dev *rt2x00dev)
1132{
95ea3627
ID		 1133 rt73usb_register_write(rt2x00dev, MAC_CSR10, 0x00001818);
1134
1135 /*
1136 * Disable synchronisation.
1137 */
1138 rt73usb_register_write(rt2x00dev, TXRX_CSR9, 0);
1139
1140 rt2x00usb_disable_radio(rt2x00dev);
1141}
1142
1143static int rt73usb_set_state(struct rt2x00_dev *rt2x00dev, enum dev_state state)
1144{
1145 u32 reg;
1146 unsigned int i;
1147 char put_to_sleep;
1148 char current_state;
1149
1150 put_to_sleep = (state != STATE_AWAKE);
1151
1152 rt73usb_register_read(rt2x00dev, MAC_CSR12, &reg);
1153 rt2x00_set_field32(&reg, MAC_CSR12_FORCE_WAKEUP, !put_to_sleep);
1154 rt2x00_set_field32(&reg, MAC_CSR12_PUT_TO_SLEEP, put_to_sleep);
1155 rt73usb_register_write(rt2x00dev, MAC_CSR12, reg);
1156
1157 /*
1158 * Device is not guaranteed to be in the requested state yet.
1159 * We must wait until the register indicates that the
1160 * device has entered the correct state.
1161 */
1162 for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
1163 rt73usb_register_read(rt2x00dev, MAC_CSR12, &reg);
1164 current_state =
1165 rt2x00_get_field32(reg, MAC_CSR12_BBP_CURRENT_STATE);
1166 if (current_state == !put_to_sleep)
1167 return 0;
1168 msleep(10);
1169 }
1170
1171 NOTICE(rt2x00dev, "Device failed to enter state %d, "
1172 "current device state %d.\n", !put_to_sleep, current_state);
1173
1174 return -EBUSY;
1175}
1176
1177static int rt73usb_set_device_state(struct rt2x00_dev *rt2x00dev,
1178 enum dev_state state)
1179{
1180 int retval = 0;
1181
1182 switch (state) {
1183 case STATE_RADIO_ON:
1184 retval = rt73usb_enable_radio(rt2x00dev);
1185 break;
1186 case STATE_RADIO_OFF:
1187 rt73usb_disable_radio(rt2x00dev);
1188 break;
1189 case STATE_RADIO_RX_ON:
61667d8d
ID		 1190 case STATE_RADIO_RX_ON_LINK:
1191 rt73usb_toggle_rx(rt2x00dev, STATE_RADIO_RX_ON);
1192 break;
95ea3627 1193 case STATE_RADIO_RX_OFF:
61667d8d
ID		 1194 case STATE_RADIO_RX_OFF_LINK:
1195 rt73usb_toggle_rx(rt2x00dev, STATE_RADIO_RX_OFF);
95ea3627
ID		 1196 break;
1197 case STATE_DEEP_SLEEP:
1198 case STATE_SLEEP:
1199 case STATE_STANDBY:
1200 case STATE_AWAKE:
1201 retval = rt73usb_set_state(rt2x00dev, state);
1202 break;
1203 default:
1204 retval = -ENOTSUPP;
1205 break;
1206 }
1207
1208 return retval;
1209}
1210
1211/*
1212 * TX descriptor initialization
1213 */
1214static void rt73usb_write_tx_desc(struct rt2x00_dev *rt2x00dev,
dd3193e1 1215 struct sk_buff *skb,
181d6902 1216 struct txentry_desc *txdesc,
dd3193e1 1217 struct ieee80211_tx_control *control)
95ea3627 1218{
181d6902 1219 struct skb_frame_desc *skbdesc = get_skb_frame_desc(skb);
dd3193e1 1220 __le32 *txd = skbdesc->desc;
95ea3627
ID		 1221 u32 word;
1222
1223 /*
1224 * Start writing the descriptor words.
1225 */
1226 rt2x00_desc_read(txd, 1, &word);
181d6902
ID		 1227 rt2x00_set_field32(&word, TXD_W1_HOST_Q_ID, txdesc->queue);
1228 rt2x00_set_field32(&word, TXD_W1_AIFSN, txdesc->aifs);
1229 rt2x00_set_field32(&word, TXD_W1_CWMIN, txdesc->cw_min);
1230 rt2x00_set_field32(&word, TXD_W1_CWMAX, txdesc->cw_max);
95ea3627
ID		 1231 rt2x00_set_field32(&word, TXD_W1_IV_OFFSET, IEEE80211_HEADER);
1232 rt2x00_set_field32(&word, TXD_W1_HW_SEQUENCE, 1);
1233 rt2x00_desc_write(txd, 1, word);
1234
1235 rt2x00_desc_read(txd, 2, &word);
181d6902
ID		 1236 rt2x00_set_field32(&word, TXD_W2_PLCP_SIGNAL, txdesc->signal);
1237 rt2x00_set_field32(&word, TXD_W2_PLCP_SERVICE, txdesc->service);
1238 rt2x00_set_field32(&word, TXD_W2_PLCP_LENGTH_LOW, txdesc->length_low);
1239 rt2x00_set_field32(&word, TXD_W2_PLCP_LENGTH_HIGH, txdesc->length_high);
95ea3627
ID		 1240 rt2x00_desc_write(txd, 2, word);
1241
1242 rt2x00_desc_read(txd, 5, &word);
8318d78a 1243/* XXX: removed for now
95ea3627
ID		 1244 rt2x00_set_field32(&word, TXD_W5_TX_POWER,
1245 TXPOWER_TO_DEV(control->power_level));
8318d78a 1246 */
95ea3627
ID		 1247 rt2x00_set_field32(&word, TXD_W5_WAITING_DMA_DONE_INT, 1);
1248 rt2x00_desc_write(txd, 5, word);
1249
1250 rt2x00_desc_read(txd, 0, &word);
1251 rt2x00_set_field32(&word, TXD_W0_BURST,
181d6902 1252 test_bit(ENTRY_TXD_BURST, &txdesc->flags));
95ea3627
ID		 1253 rt2x00_set_field32(&word, TXD_W0_VALID, 1);
1254 rt2x00_set_field32(&word, TXD_W0_MORE_FRAG,
181d6902 1255 test_bit(ENTRY_TXD_MORE_FRAG, &txdesc->flags));
95ea3627 1256 rt2x00_set_field32(&word, TXD_W0_ACK,
181d6902 1257 test_bit(ENTRY_TXD_ACK, &txdesc->flags));
95ea3627 1258 rt2x00_set_field32(&word, TXD_W0_TIMESTAMP,
181d6902 1259 test_bit(ENTRY_TXD_REQ_TIMESTAMP, &txdesc->flags));
95ea3627 1260 rt2x00_set_field32(&word, TXD_W0_OFDM,
181d6902
ID		 1261 test_bit(ENTRY_TXD_OFDM_RATE, &txdesc->flags));
1262 rt2x00_set_field32(&word, TXD_W0_IFS, txdesc->ifs);
95ea3627
ID		 1263 rt2x00_set_field32(&word, TXD_W0_RETRY_MODE,
1264 !!(control->flags &
1265 IEEE80211_TXCTL_LONG_RETRY_LIMIT));
1266 rt2x00_set_field32(&word, TXD_W0_TKIP_MIC, 0);
dd3193e1 1267 rt2x00_set_field32(&word, TXD_W0_DATABYTE_COUNT, skbdesc->data_len);
95ea3627 1268 rt2x00_set_field32(&word, TXD_W0_BURST2,
181d6902 1269 test_bit(ENTRY_TXD_BURST, &txdesc->flags));
95ea3627
ID		 1270 rt2x00_set_field32(&word, TXD_W0_CIPHER_ALG, CIPHER_NONE);
1271 rt2x00_desc_write(txd, 0, word);
1272}
1273
dd9fa2d2 1274static int rt73usb_get_tx_data_len(struct rt2x00_dev *rt2x00dev,
b242e891 1275 struct sk_buff *skb)
dd9fa2d2
ID		 1276{
1277 int length;
1278
1279 /*
1280 * The length _must_ be a multiple of 4,
1281 * but it must _not_ be a multiple of the USB packet size.
1282 */
1283 length = roundup(skb->len, 4);
b242e891 1284 length += (4 * !(length % rt2x00dev->usb_maxpacket));
dd9fa2d2
ID		 1285
1286 return length;
1287}
1288
95ea3627
ID		 1289/*
1290 * TX data initialization
1291 */
1292static void rt73usb_kick_tx_queue(struct rt2x00_dev *rt2x00dev,
5957da4c 1293 const unsigned int queue)
95ea3627
ID		 1294{
1295 u32 reg;
1296
5957da4c 1297 if (queue != RT2X00_BCN_QUEUE_BEACON)
95ea3627
ID		 1298 return;
1299
1300 /*
1301 * For Wi-Fi faily generated beacons between participating stations.
1302 * Set TBTT phase adaptive adjustment step to 8us (default 16us)
1303 */
1304 rt73usb_register_write(rt2x00dev, TXRX_CSR10, 0x00001008);
1305
1306 rt73usb_register_read(rt2x00dev, TXRX_CSR9, &reg);
1307 if (!rt2x00_get_field32(reg, TXRX_CSR9_BEACON_GEN)) {
1308 rt2x00_set_field32(&reg, TXRX_CSR9_BEACON_GEN, 1);
1309 rt73usb_register_write(rt2x00dev, TXRX_CSR9, reg);
1310 }
1311}
1312
1313/*
1314 * RX control handlers
1315 */
1316static int rt73usb_agc_to_rssi(struct rt2x00_dev *rt2x00dev, int rxd_w1)
1317{
1318 u16 eeprom;
1319 u8 offset;
1320 u8 lna;
1321
1322 lna = rt2x00_get_field32(rxd_w1, RXD_W1_RSSI_LNA);
1323 switch (lna) {
1324 case 3:
1325 offset = 90;
1326 break;
1327 case 2:
1328 offset = 74;
1329 break;
1330 case 1:
1331 offset = 64;
1332 break;
1333 default:
1334 return 0;
1335 }
1336
8318d78a 1337 if (rt2x00dev->rx_status.band == IEEE80211_BAND_5GHZ) {
95ea3627
ID		 1338 if (test_bit(CONFIG_EXTERNAL_LNA_A, &rt2x00dev->flags)) {
1339 if (lna == 3 || lna == 2)
1340 offset += 10;
1341 } else {
1342 if (lna == 3)
1343 offset += 6;
1344 else if (lna == 2)
1345 offset += 8;
1346 }
1347
1348 rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_OFFSET_A, &eeprom);
1349 offset -= rt2x00_get_field16(eeprom, EEPROM_RSSI_OFFSET_A_1);
1350 } else {
1351 if (test_bit(CONFIG_EXTERNAL_LNA_BG, &rt2x00dev->flags))
1352 offset += 14;
1353
1354 rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_OFFSET_BG, &eeprom);
1355 offset -= rt2x00_get_field16(eeprom, EEPROM_RSSI_OFFSET_BG_1);
1356 }
1357
1358 return rt2x00_get_field32(rxd_w1, RXD_W1_RSSI_AGC) * 2 - offset;
1359}
1360
181d6902
ID		 1361static void rt73usb_fill_rxdone(struct queue_entry *entry,
1362 struct rxdone_entry_desc *rxdesc)
95ea3627 1363{
181d6902 1364 struct skb_frame_desc *skbdesc = get_skb_frame_desc(entry->skb);
4bd7c452 1365 __le32 *rxd = (__le32 *)entry->skb->data;
181d6902
ID		 1366 struct ieee80211_hdr *hdr =
1367 (struct ieee80211_hdr *)entry->skb->data + entry->queue->desc_size;
1368 int header_size = ieee80211_get_hdrlen(le16_to_cpu(hdr->frame_control));
95ea3627
ID		 1369 u32 word0;
1370 u32 word1;
1371
1372 rt2x00_desc_read(rxd, 0, &word0);
1373 rt2x00_desc_read(rxd, 1, &word1);
1374
181d6902 1375 rxdesc->flags = 0;
4150c572 1376 if (rt2x00_get_field32(word0, RXD_W0_CRC_ERROR))
181d6902 1377 rxdesc->flags |= RX_FLAG_FAILED_FCS_CRC;
95ea3627
ID		 1378
1379 /*
1380 * Obtain the status about this packet.
1381 */
181d6902
ID		 1382 rxdesc->signal = rt2x00_get_field32(word1, RXD_W1_SIGNAL);
1383 rxdesc->rssi = rt73usb_agc_to_rssi(entry->queue->rt2x00dev, word1);
1384 rxdesc->ofdm = rt2x00_get_field32(word0, RXD_W0_OFDM);
1385 rxdesc->size = rt2x00_get_field32(word0, RXD_W0_DATABYTE_COUNT);
1386 rxdesc->my_bss = !!rt2x00_get_field32(word0, RXD_W0_MY_BSS);
1387
1388 /*
1389 * The data behind the ieee80211 header must be
1390 * aligned on a 4 byte boundary.
1391 */
1392 if (header_size % 4 == 0) {
1393 skb_push(entry->skb, 2);
1394 memmove(entry->skb->data, entry->skb->data + 2,
1395 entry->skb->len - 2);
1396 }
95ea3627 1397
7d1de806
ID		 1398 /*
1399 * Set descriptor and data pointer.
1400 */
181d6902
ID		 1401 skbdesc->data = entry->skb->data + entry->queue->desc_size;
1402 skbdesc->data_len = entry->queue->data_size;
40561b84 1403 skbdesc->desc = entry->skb->data;
181d6902
ID		 1404 skbdesc->desc_len = entry->queue->desc_size;
1405
1406 /*
1407 * Remove descriptor from skb buffer and trim the whole thing
1408 * down to only contain data.
1409 */
1410 skb_pull(entry->skb, skbdesc->desc_len);
1411 skb_trim(entry->skb, rxdesc->size);
95ea3627
ID		 1412}
1413
1414/*
1415 * Device probe functions.
1416 */
1417static int rt73usb_validate_eeprom(struct rt2x00_dev *rt2x00dev)
1418{
1419 u16 word;
1420 u8 *mac;
1421 s8 value;
1422
1423 rt2x00usb_eeprom_read(rt2x00dev, rt2x00dev->eeprom, EEPROM_SIZE);
1424
1425 /*
1426 * Start validation of the data that has been read.
1427 */
1428 mac = rt2x00_eeprom_addr(rt2x00dev, EEPROM_MAC_ADDR_0);
1429 if (!is_valid_ether_addr(mac)) {
0795af57
JP		 1430 DECLARE_MAC_BUF(macbuf);
1431
95ea3627 1432 random_ether_addr(mac);
0795af57 1433 EEPROM(rt2x00dev, "MAC: %s\n", print_mac(macbuf, mac));
95ea3627
ID		 1434 }
1435
1436 rt2x00_eeprom_read(rt2x00dev, EEPROM_ANTENNA, &word);
1437 if (word == 0xffff) {
1438 rt2x00_set_field16(&word, EEPROM_ANTENNA_NUM, 2);
362f3b6b
ID		 1439 rt2x00_set_field16(&word, EEPROM_ANTENNA_TX_DEFAULT,
1440 ANTENNA_B);
1441 rt2x00_set_field16(&word, EEPROM_ANTENNA_RX_DEFAULT,
1442 ANTENNA_B);
95ea3627
ID		 1443 rt2x00_set_field16(&word, EEPROM_ANTENNA_FRAME_TYPE, 0);
1444 rt2x00_set_field16(&word, EEPROM_ANTENNA_DYN_TXAGC, 0);
1445 rt2x00_set_field16(&word, EEPROM_ANTENNA_HARDWARE_RADIO, 0);
1446 rt2x00_set_field16(&word, EEPROM_ANTENNA_RF_TYPE, RF5226);
1447 rt2x00_eeprom_write(rt2x00dev, EEPROM_ANTENNA, word);
1448 EEPROM(rt2x00dev, "Antenna: 0x%04x\n", word);
1449 }
1450
1451 rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC, &word);
1452 if (word == 0xffff) {
1453 rt2x00_set_field16(&word, EEPROM_NIC_EXTERNAL_LNA, 0);
1454 rt2x00_eeprom_write(rt2x00dev, EEPROM_NIC, word);
1455 EEPROM(rt2x00dev, "NIC: 0x%04x\n", word);
1456 }
1457
1458 rt2x00_eeprom_read(rt2x00dev, EEPROM_LED, &word);
1459 if (word == 0xffff) {
1460 rt2x00_set_field16(&word, EEPROM_LED_POLARITY_RDY_G, 0);
1461 rt2x00_set_field16(&word, EEPROM_LED_POLARITY_RDY_A, 0);
1462 rt2x00_set_field16(&word, EEPROM_LED_POLARITY_ACT, 0);
1463 rt2x00_set_field16(&word, EEPROM_LED_POLARITY_GPIO_0, 0);
1464 rt2x00_set_field16(&word, EEPROM_LED_POLARITY_GPIO_1, 0);
1465 rt2x00_set_field16(&word, EEPROM_LED_POLARITY_GPIO_2, 0);
1466 rt2x00_set_field16(&word, EEPROM_LED_POLARITY_GPIO_3, 0);
1467 rt2x00_set_field16(&word, EEPROM_LED_POLARITY_GPIO_4, 0);
1468 rt2x00_set_field16(&word, EEPROM_LED_LED_MODE,
1469 LED_MODE_DEFAULT);
1470 rt2x00_eeprom_write(rt2x00dev, EEPROM_LED, word);
1471 EEPROM(rt2x00dev, "Led: 0x%04x\n", word);
1472 }
1473
1474 rt2x00_eeprom_read(rt2x00dev, EEPROM_FREQ, &word);
1475 if (word == 0xffff) {
1476 rt2x00_set_field16(&word, EEPROM_FREQ_OFFSET, 0);
1477 rt2x00_set_field16(&word, EEPROM_FREQ_SEQ, 0);
1478 rt2x00_eeprom_write(rt2x00dev, EEPROM_FREQ, word);
1479 EEPROM(rt2x00dev, "Freq: 0x%04x\n", word);
1480 }
1481
1482 rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_OFFSET_BG, &word);
1483 if (word == 0xffff) {
1484 rt2x00_set_field16(&word, EEPROM_RSSI_OFFSET_BG_1, 0);
1485 rt2x00_set_field16(&word, EEPROM_RSSI_OFFSET_BG_2, 0);
1486 rt2x00_eeprom_write(rt2x00dev, EEPROM_RSSI_OFFSET_BG, word);
1487 EEPROM(rt2x00dev, "RSSI OFFSET BG: 0x%04x\n", word);
1488 } else {
1489 value = rt2x00_get_field16(word, EEPROM_RSSI_OFFSET_BG_1);
1490 if (value < -10 || value > 10)
1491 rt2x00_set_field16(&word, EEPROM_RSSI_OFFSET_BG_1, 0);
1492 value = rt2x00_get_field16(word, EEPROM_RSSI_OFFSET_BG_2);
1493 if (value < -10 || value > 10)
1494 rt2x00_set_field16(&word, EEPROM_RSSI_OFFSET_BG_2, 0);
1495 rt2x00_eeprom_write(rt2x00dev, EEPROM_RSSI_OFFSET_BG, word);
1496 }
1497
1498 rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_OFFSET_A, &word);
1499 if (word == 0xffff) {
1500 rt2x00_set_field16(&word, EEPROM_RSSI_OFFSET_A_1, 0);
1501 rt2x00_set_field16(&word, EEPROM_RSSI_OFFSET_A_2, 0);
1502 rt2x00_eeprom_write(rt2x00dev, EEPROM_RSSI_OFFSET_A, word);
417f412f 1503 EEPROM(rt2x00dev, "RSSI OFFSET A: 0x%04x\n", word);
95ea3627
ID		 1504 } else {
1505 value = rt2x00_get_field16(word, EEPROM_RSSI_OFFSET_A_1);
1506 if (value < -10 || value > 10)
1507 rt2x00_set_field16(&word, EEPROM_RSSI_OFFSET_A_1, 0);
1508 value = rt2x00_get_field16(word, EEPROM_RSSI_OFFSET_A_2);
1509 if (value < -10 || value > 10)
1510 rt2x00_set_field16(&word, EEPROM_RSSI_OFFSET_A_2, 0);
1511 rt2x00_eeprom_write(rt2x00dev, EEPROM_RSSI_OFFSET_A, word);
1512 }
1513
1514 return 0;
1515}
1516
1517static int rt73usb_init_eeprom(struct rt2x00_dev *rt2x00dev)
1518{
1519 u32 reg;
1520 u16 value;
1521 u16 eeprom;
1522
1523 /*
1524 * Read EEPROM word for configuration.
1525 */
1526 rt2x00_eeprom_read(rt2x00dev, EEPROM_ANTENNA, &eeprom);
1527
1528 /*
1529 * Identify RF chipset.
1530 */
1531 value = rt2x00_get_field16(eeprom, EEPROM_ANTENNA_RF_TYPE);
1532 rt73usb_register_read(rt2x00dev, MAC_CSR0, &reg);
1533 rt2x00_set_chip(rt2x00dev, RT2571, value, reg);
1534
755a957d 1535 if (!rt2x00_check_rev(&rt2x00dev->chip, 0x25730)) {
95ea3627
ID		 1536 ERROR(rt2x00dev, "Invalid RT chipset detected.\n");
1537 return -ENODEV;
1538 }
1539
1540 if (!rt2x00_rf(&rt2x00dev->chip, RF5226) &&
1541 !rt2x00_rf(&rt2x00dev->chip, RF2528) &&
1542 !rt2x00_rf(&rt2x00dev->chip, RF5225) &&
1543 !rt2x00_rf(&rt2x00dev->chip, RF2527)) {
1544 ERROR(rt2x00dev, "Invalid RF chipset detected.\n");
1545 return -ENODEV;
1546 }
1547
1548 /*
1549 * Identify default antenna configuration.
1550 */
addc81bd 1551 rt2x00dev->default_ant.tx =
95ea3627 1552 rt2x00_get_field16(eeprom, EEPROM_ANTENNA_TX_DEFAULT);
addc81bd 1553 rt2x00dev->default_ant.rx =
95ea3627
ID		 1554 rt2x00_get_field16(eeprom, EEPROM_ANTENNA_RX_DEFAULT);
1555
1556 /*
1557 * Read the Frame type.
1558 */
1559 if (rt2x00_get_field16(eeprom, EEPROM_ANTENNA_FRAME_TYPE))
1560 __set_bit(CONFIG_FRAME_TYPE, &rt2x00dev->flags);
1561
1562 /*
1563 * Read frequency offset.
1564 */
1565 rt2x00_eeprom_read(rt2x00dev, EEPROM_FREQ, &eeprom);
1566 rt2x00dev->freq_offset = rt2x00_get_field16(eeprom, EEPROM_FREQ_OFFSET);
1567
1568 /*
1569 * Read external LNA informations.
1570 */
1571 rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC, &eeprom);
1572
1573 if (rt2x00_get_field16(eeprom, EEPROM_NIC_EXTERNAL_LNA)) {
1574 __set_bit(CONFIG_EXTERNAL_LNA_A, &rt2x00dev->flags);
1575 __set_bit(CONFIG_EXTERNAL_LNA_BG, &rt2x00dev->flags);
1576 }
1577
1578 /*
1579 * Store led settings, for correct led behaviour.
1580 */
a9450b70 1581#ifdef CONFIG_RT73USB_LEDS
95ea3627
ID		 1582 rt2x00_eeprom_read(rt2x00dev, EEPROM_LED, &eeprom);
1583
a9450b70
ID		 1584 switch (value) {
1585 case LED_MODE_TXRX_ACTIVITY:
1586 case LED_MODE_ASUS:
1587 case LED_MODE_ALPHA:
1588 case LED_MODE_DEFAULT:
1589 rt2x00dev->led_flags =
1590 LED_SUPPORT_RADIO | LED_SUPPORT_ASSOC;
1591 break;
1592 case LED_MODE_SIGNAL_STRENGTH:
1593 rt2x00dev->led_flags =
1594 LED_SUPPORT_RADIO | LED_SUPPORT_ASSOC |
1595 LED_SUPPORT_QUALITY;
1596 break;
1597 }
1598
1599 rt2x00_set_field16(&rt2x00dev->led_mcu_reg, MCU_LEDCS_LED_MODE, value);
1600 rt2x00_set_field16(&rt2x00dev->led_mcu_reg, MCU_LEDCS_POLARITY_GPIO_0,
95ea3627
ID		 1601 rt2x00_get_field16(eeprom,
1602 EEPROM_LED_POLARITY_GPIO_0));
a9450b70 1603 rt2x00_set_field16(&rt2x00dev->led_mcu_reg, MCU_LEDCS_POLARITY_GPIO_1,
95ea3627
ID		 1604 rt2x00_get_field16(eeprom,
1605 EEPROM_LED_POLARITY_GPIO_1));
a9450b70 1606 rt2x00_set_field16(&rt2x00dev->led_mcu_reg, MCU_LEDCS_POLARITY_GPIO_2,
95ea3627
ID		 1607 rt2x00_get_field16(eeprom,
1608 EEPROM_LED_POLARITY_GPIO_2));
a9450b70 1609 rt2x00_set_field16(&rt2x00dev->led_mcu_reg, MCU_LEDCS_POLARITY_GPIO_3,
95ea3627
ID		 1610 rt2x00_get_field16(eeprom,
1611 EEPROM_LED_POLARITY_GPIO_3));
a9450b70 1612 rt2x00_set_field16(&rt2x00dev->led_mcu_reg, MCU_LEDCS_POLARITY_GPIO_4,
95ea3627
ID		 1613 rt2x00_get_field16(eeprom,
1614 EEPROM_LED_POLARITY_GPIO_4));
a9450b70 1615 rt2x00_set_field16(&rt2x00dev->led_mcu_reg, MCU_LEDCS_POLARITY_ACT,
95ea3627 1616 rt2x00_get_field16(eeprom, EEPROM_LED_POLARITY_ACT));
a9450b70 1617 rt2x00_set_field16(&rt2x00dev->led_mcu_reg, MCU_LEDCS_POLARITY_READY_BG,
95ea3627
ID		 1618 rt2x00_get_field16(eeprom,
1619 EEPROM_LED_POLARITY_RDY_G));
a9450b70 1620 rt2x00_set_field16(&rt2x00dev->led_mcu_reg, MCU_LEDCS_POLARITY_READY_A,
95ea3627
ID		 1621 rt2x00_get_field16(eeprom,
1622 EEPROM_LED_POLARITY_RDY_A));
a9450b70 1623#endif /* CONFIG_RT73USB_LEDS */
95ea3627
ID		 1624
1625 return 0;
1626}
1627
1628/*
1629 * RF value list for RF2528
1630 * Supports: 2.4 GHz
1631 */
1632static const struct rf_channel rf_vals_bg_2528[] = {
1633 { 1, 0x00002c0c, 0x00000786, 0x00068255, 0x000fea0b },
1634 { 2, 0x00002c0c, 0x00000786, 0x00068255, 0x000fea1f },
1635 { 3, 0x00002c0c, 0x0000078a, 0x00068255, 0x000fea0b },
1636 { 4, 0x00002c0c, 0x0000078a, 0x00068255, 0x000fea1f },
1637 { 5, 0x00002c0c, 0x0000078e, 0x00068255, 0x000fea0b },
1638 { 6, 0x00002c0c, 0x0000078e, 0x00068255, 0x000fea1f },
1639 { 7, 0x00002c0c, 0x00000792, 0x00068255, 0x000fea0b },
1640 { 8, 0x00002c0c, 0x00000792, 0x00068255, 0x000fea1f },
1641 { 9, 0x00002c0c, 0x00000796, 0x00068255, 0x000fea0b },
1642 { 10, 0x00002c0c, 0x00000796, 0x00068255, 0x000fea1f },
1643 { 11, 0x00002c0c, 0x0000079a, 0x00068255, 0x000fea0b },
1644 { 12, 0x00002c0c, 0x0000079a, 0x00068255, 0x000fea1f },
1645 { 13, 0x00002c0c, 0x0000079e, 0x00068255, 0x000fea0b },
1646 { 14, 0x00002c0c, 0x000007a2, 0x00068255, 0x000fea13 },
1647};
1648
1649/*
1650 * RF value list for RF5226
1651 * Supports: 2.4 GHz & 5.2 GHz
1652 */
1653static const struct rf_channel rf_vals_5226[] = {
1654 { 1, 0x00002c0c, 0x00000786, 0x00068255, 0x000fea0b },
1655 { 2, 0x00002c0c, 0x00000786, 0x00068255, 0x000fea1f },
1656 { 3, 0x00002c0c, 0x0000078a, 0x00068255, 0x000fea0b },
1657 { 4, 0x00002c0c, 0x0000078a, 0x00068255, 0x000fea1f },
1658 { 5, 0x00002c0c, 0x0000078e, 0x00068255, 0x000fea0b },
1659 { 6, 0x00002c0c, 0x0000078e, 0x00068255, 0x000fea1f },
1660 { 7, 0x00002c0c, 0x00000792, 0x00068255, 0x000fea0b },
1661 { 8, 0x00002c0c, 0x00000792, 0x00068255, 0x000fea1f },
1662 { 9, 0x00002c0c, 0x00000796, 0x00068255, 0x000fea0b },
1663 { 10, 0x00002c0c, 0x00000796, 0x00068255, 0x000fea1f },
1664 { 11, 0x00002c0c, 0x0000079a, 0x00068255, 0x000fea0b },
1665 { 12, 0x00002c0c, 0x0000079a, 0x00068255, 0x000fea1f },
1666 { 13, 0x00002c0c, 0x0000079e, 0x00068255, 0x000fea0b },
1667 { 14, 0x00002c0c, 0x000007a2, 0x00068255, 0x000fea13 },
1668
1669 /* 802.11 UNI / HyperLan 2 */
1670 { 36, 0x00002c0c, 0x0000099a, 0x00098255, 0x000fea23 },
1671 { 40, 0x00002c0c, 0x000009a2, 0x00098255, 0x000fea03 },
1672 { 44, 0x00002c0c, 0x000009a6, 0x00098255, 0x000fea0b },
1673 { 48, 0x00002c0c, 0x000009aa, 0x00098255, 0x000fea13 },
1674 { 52, 0x00002c0c, 0x000009ae, 0x00098255, 0x000fea1b },
1675 { 56, 0x00002c0c, 0x000009b2, 0x00098255, 0x000fea23 },
1676 { 60, 0x00002c0c, 0x000009ba, 0x00098255, 0x000fea03 },
1677 { 64, 0x00002c0c, 0x000009be, 0x00098255, 0x000fea0b },
1678
1679 /* 802.11 HyperLan 2 */
1680 { 100, 0x00002c0c, 0x00000a2a, 0x000b8255, 0x000fea03 },
1681 { 104, 0x00002c0c, 0x00000a2e, 0x000b8255, 0x000fea0b },
1682 { 108, 0x00002c0c, 0x00000a32, 0x000b8255, 0x000fea13 },
1683 { 112, 0x00002c0c, 0x00000a36, 0x000b8255, 0x000fea1b },
1684 { 116, 0x00002c0c, 0x00000a3a, 0x000b8255, 0x000fea23 },
1685 { 120, 0x00002c0c, 0x00000a82, 0x000b8255, 0x000fea03 },
1686 { 124, 0x00002c0c, 0x00000a86, 0x000b8255, 0x000fea0b },
1687 { 128, 0x00002c0c, 0x00000a8a, 0x000b8255, 0x000fea13 },
1688 { 132, 0x00002c0c, 0x00000a8e, 0x000b8255, 0x000fea1b },
1689 { 136, 0x00002c0c, 0x00000a92, 0x000b8255, 0x000fea23 },
1690
1691 /* 802.11 UNII */
1692 { 140, 0x00002c0c, 0x00000a9a, 0x000b8255, 0x000fea03 },
1693 { 149, 0x00002c0c, 0x00000aa2, 0x000b8255, 0x000fea1f },
1694 { 153, 0x00002c0c, 0x00000aa6, 0x000b8255, 0x000fea27 },
1695 { 157, 0x00002c0c, 0x00000aae, 0x000b8255, 0x000fea07 },
1696 { 161, 0x00002c0c, 0x00000ab2, 0x000b8255, 0x000fea0f },
1697 { 165, 0x00002c0c, 0x00000ab6, 0x000b8255, 0x000fea17 },
1698
1699 /* MMAC(Japan)J52 ch 34,38,42,46 */
1700 { 34, 0x00002c0c, 0x0008099a, 0x000da255, 0x000d3a0b },
1701 { 38, 0x00002c0c, 0x0008099e, 0x000da255, 0x000d3a13 },
1702 { 42, 0x00002c0c, 0x000809a2, 0x000da255, 0x000d3a1b },
1703 { 46, 0x00002c0c, 0x000809a6, 0x000da255, 0x000d3a23 },
1704};
1705
1706/*
1707 * RF value list for RF5225 & RF2527
1708 * Supports: 2.4 GHz & 5.2 GHz
1709 */
1710static const struct rf_channel rf_vals_5225_2527[] = {
1711 { 1, 0x00002ccc, 0x00004786, 0x00068455, 0x000ffa0b },
1712 { 2, 0x00002ccc, 0x00004786, 0x00068455, 0x000ffa1f },
1713 { 3, 0x00002ccc, 0x0000478a, 0x00068455, 0x000ffa0b },
1714 { 4, 0x00002ccc, 0x0000478a, 0x00068455, 0x000ffa1f },
1715 { 5, 0x00002ccc, 0x0000478e, 0x00068455, 0x000ffa0b },
1716 { 6, 0x00002ccc, 0x0000478e, 0x00068455, 0x000ffa1f },
1717 { 7, 0x00002ccc, 0x00004792, 0x00068455, 0x000ffa0b },
1718 { 8, 0x00002ccc, 0x00004792, 0x00068455, 0x000ffa1f },
1719 { 9, 0x00002ccc, 0x00004796, 0x00068455, 0x000ffa0b },
1720 { 10, 0x00002ccc, 0x00004796, 0x00068455, 0x000ffa1f },
1721 { 11, 0x00002ccc, 0x0000479a, 0x00068455, 0x000ffa0b },
1722 { 12, 0x00002ccc, 0x0000479a, 0x00068455, 0x000ffa1f },
1723 { 13, 0x00002ccc, 0x0000479e, 0x00068455, 0x000ffa0b },
1724 { 14, 0x00002ccc, 0x000047a2, 0x00068455, 0x000ffa13 },
1725
1726 /* 802.11 UNI / HyperLan 2 */
1727 { 36, 0x00002ccc, 0x0000499a, 0x0009be55, 0x000ffa23 },
1728 { 40, 0x00002ccc, 0x000049a2, 0x0009be55, 0x000ffa03 },
1729 { 44, 0x00002ccc, 0x000049a6, 0x0009be55, 0x000ffa0b },
1730 { 48, 0x00002ccc, 0x000049aa, 0x0009be55, 0x000ffa13 },
1731 { 52, 0x00002ccc, 0x000049ae, 0x0009ae55, 0x000ffa1b },
1732 { 56, 0x00002ccc, 0x000049b2, 0x0009ae55, 0x000ffa23 },
1733 { 60, 0x00002ccc, 0x000049ba, 0x0009ae55, 0x000ffa03 },
1734 { 64, 0x00002ccc, 0x000049be, 0x0009ae55, 0x000ffa0b },
1735
1736 /* 802.11 HyperLan 2 */
1737 { 100, 0x00002ccc, 0x00004a2a, 0x000bae55, 0x000ffa03 },
1738 { 104, 0x00002ccc, 0x00004a2e, 0x000bae55, 0x000ffa0b },
1739 { 108, 0x00002ccc, 0x00004a32, 0x000bae55, 0x000ffa13 },
1740 { 112, 0x00002ccc, 0x00004a36, 0x000bae55, 0x000ffa1b },
1741 { 116, 0x00002ccc, 0x00004a3a, 0x000bbe55, 0x000ffa23 },
1742 { 120, 0x00002ccc, 0x00004a82, 0x000bbe55, 0x000ffa03 },
1743 { 124, 0x00002ccc, 0x00004a86, 0x000bbe55, 0x000ffa0b },
1744 { 128, 0x00002ccc, 0x00004a8a, 0x000bbe55, 0x000ffa13 },
1745 { 132, 0x00002ccc, 0x00004a8e, 0x000bbe55, 0x000ffa1b },
1746 { 136, 0x00002ccc, 0x00004a92, 0x000bbe55, 0x000ffa23 },
1747
1748 /* 802.11 UNII */
1749 { 140, 0x00002ccc, 0x00004a9a, 0x000bbe55, 0x000ffa03 },
1750 { 149, 0x00002ccc, 0x00004aa2, 0x000bbe55, 0x000ffa1f },
1751 { 153, 0x00002ccc, 0x00004aa6, 0x000bbe55, 0x000ffa27 },
1752 { 157, 0x00002ccc, 0x00004aae, 0x000bbe55, 0x000ffa07 },
1753 { 161, 0x00002ccc, 0x00004ab2, 0x000bbe55, 0x000ffa0f },
1754 { 165, 0x00002ccc, 0x00004ab6, 0x000bbe55, 0x000ffa17 },
1755
1756 /* MMAC(Japan)J52 ch 34,38,42,46 */
1757 { 34, 0x00002ccc, 0x0000499a, 0x0009be55, 0x000ffa0b },
1758 { 38, 0x00002ccc, 0x0000499e, 0x0009be55, 0x000ffa13 },
1759 { 42, 0x00002ccc, 0x000049a2, 0x0009be55, 0x000ffa1b },
1760 { 46, 0x00002ccc, 0x000049a6, 0x0009be55, 0x000ffa23 },
1761};
1762
1763
1764static void rt73usb_probe_hw_mode(struct rt2x00_dev *rt2x00dev)
1765{
1766 struct hw_mode_spec *spec = &rt2x00dev->spec;
1767 u8 *txpower;
1768 unsigned int i;
1769
1770 /*
1771 * Initialize all hw fields.
1772 */
1773 rt2x00dev->hw->flags =
1774 IEEE80211_HW_HOST_GEN_BEACON_TEMPLATE |
4150c572 1775 IEEE80211_HW_HOST_BROADCAST_PS_BUFFERING;
95ea3627
ID		 1776 rt2x00dev->hw->extra_tx_headroom = TXD_DESC_SIZE;
1777 rt2x00dev->hw->max_signal = MAX_SIGNAL;
1778 rt2x00dev->hw->max_rssi = MAX_RX_SSI;
871ff6ed 1779 rt2x00dev->hw->queues = 4;
95ea3627
ID		 1780
1781 SET_IEEE80211_DEV(rt2x00dev->hw, &rt2x00dev_usb(rt2x00dev)->dev);
1782 SET_IEEE80211_PERM_ADDR(rt2x00dev->hw,
1783 rt2x00_eeprom_addr(rt2x00dev,
1784 EEPROM_MAC_ADDR_0));
1785
1786 /*
1787 * Convert tx_power array in eeprom.
1788 */
1789 txpower = rt2x00_eeprom_addr(rt2x00dev, EEPROM_TXPOWER_G_START);
1790 for (i = 0; i < 14; i++)
1791 txpower[i] = TXPOWER_FROM_DEV(txpower[i]);
1792
1793 /*
1794 * Initialize hw_mode information.
1795 */
1796 spec->num_modes = 2;
1797 spec->num_rates = 12;
1798 spec->tx_power_a = NULL;
1799 spec->tx_power_bg = txpower;
1800 spec->tx_power_default = DEFAULT_TXPOWER;
1801
1802 if (rt2x00_rf(&rt2x00dev->chip, RF2528)) {
1803 spec->num_channels = ARRAY_SIZE(rf_vals_bg_2528);
1804 spec->channels = rf_vals_bg_2528;
1805 } else if (rt2x00_rf(&rt2x00dev->chip, RF5226)) {
1806 spec->num_channels = ARRAY_SIZE(rf_vals_5226);
1807 spec->channels = rf_vals_5226;
1808 } else if (rt2x00_rf(&rt2x00dev->chip, RF2527)) {
1809 spec->num_channels = 14;
1810 spec->channels = rf_vals_5225_2527;
1811 } else if (rt2x00_rf(&rt2x00dev->chip, RF5225)) {
1812 spec->num_channels = ARRAY_SIZE(rf_vals_5225_2527);
1813 spec->channels = rf_vals_5225_2527;
1814 }
1815
1816 if (rt2x00_rf(&rt2x00dev->chip, RF5225) ||
1817 rt2x00_rf(&rt2x00dev->chip, RF5226)) {
1818 spec->num_modes = 3;
1819
1820 txpower = rt2x00_eeprom_addr(rt2x00dev, EEPROM_TXPOWER_A_START);
1821 for (i = 0; i < 14; i++)
1822 txpower[i] = TXPOWER_FROM_DEV(txpower[i]);
1823
1824 spec->tx_power_a = txpower;
1825 }
1826}
1827
1828static int rt73usb_probe_hw(struct rt2x00_dev *rt2x00dev)
1829{
1830 int retval;
1831
1832 /*
1833 * Allocate eeprom data.
1834 */
1835 retval = rt73usb_validate_eeprom(rt2x00dev);
1836 if (retval)
1837 return retval;
1838
1839 retval = rt73usb_init_eeprom(rt2x00dev);
1840 if (retval)
1841 return retval;
1842
1843 /*
1844 * Initialize hw specifications.
1845 */
1846 rt73usb_probe_hw_mode(rt2x00dev);
1847
1848 /*
9404ef34 1849 * This device requires firmware.
95ea3627 1850 */
066cb637 1851 __set_bit(DRIVER_REQUIRE_FIRMWARE, &rt2x00dev->flags);
9404ef34 1852 __set_bit(DRIVER_REQUIRE_FIRMWARE_CRC_ITU_T, &rt2x00dev->flags);
95ea3627
ID		 1853
1854 /*
1855 * Set the rssi offset.
1856 */
1857 rt2x00dev->rssi_offset = DEFAULT_RSSI_OFFSET;
1858
1859 return 0;
1860}
1861
1862/*
1863 * IEEE80211 stack callback functions.
1864 */
4150c572
JB		 1865static void rt73usb_configure_filter(struct ieee80211_hw *hw,
1866 unsigned int changed_flags,
1867 unsigned int *total_flags,
1868 int mc_count,
1869 struct dev_addr_list *mc_list)
1870{
1871 struct rt2x00_dev *rt2x00dev = hw->priv;
4150c572
JB		 1872 u32 reg;
1873
1874 /*
1875 * Mask off any flags we are going to ignore from
1876 * the total_flags field.
1877 */
1878 *total_flags &=
1879 FIF_ALLMULTI |
1880 FIF_FCSFAIL |
1881 FIF_PLCPFAIL |
1882 FIF_CONTROL |
1883 FIF_OTHER_BSS |
1884 FIF_PROMISC_IN_BSS;
1885
1886 /*
1887 * Apply some rules to the filters:
1888 * - Some filters imply different filters to be set.
1889 * - Some things we can't filter out at all.
4150c572
JB		 1890 */
1891 if (mc_count)
1892 *total_flags |= FIF_ALLMULTI;
5886d0db
ID		 1893 if (*total_flags & FIF_OTHER_BSS ||
1894 *total_flags & FIF_PROMISC_IN_BSS)
4150c572 1895 *total_flags |= FIF_PROMISC_IN_BSS | FIF_OTHER_BSS;
4150c572
JB		 1896
1897 /*
1898 * Check if there is any work left for us.
1899 */
3c4f2085 1900 if (rt2x00dev->packet_filter == *total_flags)
4150c572 1901 return;
3c4f2085 1902 rt2x00dev->packet_filter = *total_flags;
4150c572
JB		 1903
1904 /*
1905 * When in atomic context, reschedule and let rt2x00lib
1906 * call this function again.
1907 */
1908 if (in_atomic()) {
1909 queue_work(rt2x00dev->hw->workqueue, &rt2x00dev->filter_work);
1910 return;
1911 }
1912
1913 /*
1914 * Start configuration steps.
1915 * Note that the version error will always be dropped
1916 * and broadcast frames will always be accepted since
1917 * there is no filter for it at this time.
1918 */
1919 rt73usb_register_read(rt2x00dev, TXRX_CSR0, &reg);
1920 rt2x00_set_field32(&reg, TXRX_CSR0_DROP_CRC,
1921 !(*total_flags & FIF_FCSFAIL));
1922 rt2x00_set_field32(&reg, TXRX_CSR0_DROP_PHYSICAL,
1923 !(*total_flags & FIF_PLCPFAIL));
1924 rt2x00_set_field32(&reg, TXRX_CSR0_DROP_CONTROL,
1925 !(*total_flags & FIF_CONTROL));
1926 rt2x00_set_field32(&reg, TXRX_CSR0_DROP_NOT_TO_ME,
1927 !(*total_flags & FIF_PROMISC_IN_BSS));
1928 rt2x00_set_field32(&reg, TXRX_CSR0_DROP_TO_DS,
1929 !(*total_flags & FIF_PROMISC_IN_BSS));
1930 rt2x00_set_field32(&reg, TXRX_CSR0_DROP_VERSION_ERROR, 1);
1931 rt2x00_set_field32(&reg, TXRX_CSR0_DROP_MULTICAST,
1932 !(*total_flags & FIF_ALLMULTI));
1933 rt2x00_set_field32(&reg, TXRX_CSR0_DROP_BROADCAST, 0);
1934 rt2x00_set_field32(&reg, TXRX_CSR0_DROP_ACK_CTS, 1);
1935 rt73usb_register_write(rt2x00dev, TXRX_CSR0, reg);
1936}
1937
95ea3627
ID		 1938static int rt73usb_set_retry_limit(struct ieee80211_hw *hw,
1939 u32 short_retry, u32 long_retry)
1940{
1941 struct rt2x00_dev *rt2x00dev = hw->priv;
1942 u32 reg;
1943
1944 rt73usb_register_read(rt2x00dev, TXRX_CSR4, &reg);
1945 rt2x00_set_field32(&reg, TXRX_CSR4_LONG_RETRY_LIMIT, long_retry);
1946 rt2x00_set_field32(&reg, TXRX_CSR4_SHORT_RETRY_LIMIT, short_retry);
1947 rt73usb_register_write(rt2x00dev, TXRX_CSR4, reg);
1948
1949 return 0;
1950}
1951
1952#if 0
1953/*
1954 * Mac80211 demands get_tsf must be atomic.
1955 * This is not possible for rt73usb since all register access
1956 * functions require sleeping. Untill mac80211 no longer needs
1957 * get_tsf to be atomic, this function should be disabled.
1958 */
1959static u64 rt73usb_get_tsf(struct ieee80211_hw *hw)
1960{
1961 struct rt2x00_dev *rt2x00dev = hw->priv;
1962 u64 tsf;
1963 u32 reg;
1964
1965 rt73usb_register_read(rt2x00dev, TXRX_CSR13, &reg);
1966 tsf = (u64) rt2x00_get_field32(reg, TXRX_CSR13_HIGH_TSFTIMER) << 32;
1967 rt73usb_register_read(rt2x00dev, TXRX_CSR12, &reg);
1968 tsf |= rt2x00_get_field32(reg, TXRX_CSR12_LOW_TSFTIMER);
1969
1970 return tsf;
1971}
37894473
ID		 1972#else
1973#define rt73usb_get_tsf NULL
95ea3627
ID		 1974#endif
1975
1976static void rt73usb_reset_tsf(struct ieee80211_hw *hw)
1977{
1978 struct rt2x00_dev *rt2x00dev = hw->priv;
1979
1980 rt73usb_register_write(rt2x00dev, TXRX_CSR12, 0);
1981 rt73usb_register_write(rt2x00dev, TXRX_CSR13, 0);
1982}
1983
24845910 1984static int rt73usb_beacon_update(struct ieee80211_hw *hw, struct sk_buff *skb,
6bb40dd1 1985 struct ieee80211_tx_control *control)
95ea3627
ID		 1986{
1987 struct rt2x00_dev *rt2x00dev = hw->priv;
6bb40dd1 1988 struct rt2x00_intf *intf = vif_to_intf(control->vif);
181d6902 1989 struct skb_frame_desc *skbdesc;
6bb40dd1
ID		 1990 unsigned int beacon_base;
1991 unsigned int timeout;
95ea3627 1992
6bb40dd1
ID		 1993 if (unlikely(!intf->beacon))
1994 return -ENOBUFS;
95ea3627
ID		 1995
1996 /*
08992f7f 1997 * Add the descriptor in front of the skb.
95ea3627 1998 */
6bb40dd1
ID		 1999 skb_push(skb, intf->beacon->queue->desc_size);
2000 memset(skb->data, 0, intf->beacon->queue->desc_size);
c22eb87b 2001
08992f7f
ID		 2002 /*
2003 * Fill in skb descriptor
2004 */
181d6902
ID		 2005 skbdesc = get_skb_frame_desc(skb);
2006 memset(skbdesc, 0, sizeof(*skbdesc));
6bb40dd1
ID		 2007 skbdesc->data = skb->data + intf->beacon->queue->desc_size;
2008 skbdesc->data_len = skb->len - intf->beacon->queue->desc_size;
181d6902 2009 skbdesc->desc = skb->data;
6bb40dd1
ID		 2010 skbdesc->desc_len = intf->beacon->queue->desc_size;
2011 skbdesc->entry = intf->beacon;
08992f7f 2012
6bb40dd1 2013 /*
5957da4c
ID		 2014 * mac80211 doesn't provide the control->queue variable
2015 * for beacons. Set our own queue identification so
2016 * it can be used during descriptor initialization.
6bb40dd1 2017 */
5957da4c 2018 control->queue = RT2X00_BCN_QUEUE_BEACON;
08992f7f 2019 rt2x00lib_write_tx_desc(rt2x00dev, skb, control);
95ea3627
ID		 2020
2021 /*
2022 * Write entire beacon with descriptor to register,
2023 * and kick the beacon generator.
2024 */
6bb40dd1 2025 beacon_base = HW_BEACON_OFFSET(intf->beacon->entry_idx);
95ea3627
ID		 2026 timeout = REGISTER_TIMEOUT * (skb->len / sizeof(u32));
2027 rt2x00usb_vendor_request(rt2x00dev, USB_MULTI_WRITE,
6bb40dd1 2028 USB_VENDOR_REQUEST_OUT, beacon_base, 0,
95ea3627 2029 skb->data, skb->len, timeout);
6bb40dd1 2030 rt73usb_kick_tx_queue(rt2x00dev, control->queue);
95ea3627
ID		 2031
2032 return 0;
2033}
2034
2035static const struct ieee80211_ops rt73usb_mac80211_ops = {
2036 .tx = rt2x00mac_tx,
4150c572
JB		 2037 .start = rt2x00mac_start,
2038 .stop = rt2x00mac_stop,
95ea3627
ID		 2039 .add_interface = rt2x00mac_add_interface,
2040 .remove_interface = rt2x00mac_remove_interface,
2041 .config = rt2x00mac_config,
2042 .config_interface = rt2x00mac_config_interface,
4150c572 2043 .configure_filter = rt73usb_configure_filter,
95ea3627
ID		 2044 .get_stats = rt2x00mac_get_stats,
2045 .set_retry_limit = rt73usb_set_retry_limit,
471b3efd 2046 .bss_info_changed = rt2x00mac_bss_info_changed,
95ea3627
ID		 2047 .conf_tx = rt2x00mac_conf_tx,
2048 .get_tx_stats = rt2x00mac_get_tx_stats,
95ea3627 2049 .get_tsf = rt73usb_get_tsf,
95ea3627
ID		 2050 .reset_tsf = rt73usb_reset_tsf,
2051 .beacon_update = rt73usb_beacon_update,
2052};
2053
2054static const struct rt2x00lib_ops rt73usb_rt2x00_ops = {
2055 .probe_hw = rt73usb_probe_hw,
2056 .get_firmware_name = rt73usb_get_firmware_name,
2057 .load_firmware = rt73usb_load_firmware,
2058 .initialize = rt2x00usb_initialize,
2059 .uninitialize = rt2x00usb_uninitialize,
837e7f24
ID		 2060 .init_rxentry = rt2x00usb_init_rxentry,
2061 .init_txentry = rt2x00usb_init_txentry,
95ea3627
ID		 2062 .set_device_state = rt73usb_set_device_state,
2063 .link_stats = rt73usb_link_stats,
2064 .reset_tuner = rt73usb_reset_tuner,
2065 .link_tuner = rt73usb_link_tuner,
a9450b70 2066 .led_brightness = rt73usb_led_brightness,
95ea3627
ID		 2067 .write_tx_desc = rt73usb_write_tx_desc,
2068 .write_tx_data = rt2x00usb_write_tx_data,
dd9fa2d2 2069 .get_tx_data_len = rt73usb_get_tx_data_len,
95ea3627
ID		 2070 .kick_tx_queue = rt73usb_kick_tx_queue,
2071 .fill_rxdone = rt73usb_fill_rxdone,
6bb40dd1 2072 .config_intf = rt73usb_config_intf,
5c58ee51 2073 .config_preamble = rt73usb_config_preamble,
95ea3627
ID		 2074 .config = rt73usb_config,
2075};
2076
181d6902
ID		 2077static const struct data_queue_desc rt73usb_queue_rx = {
2078 .entry_num = RX_ENTRIES,
2079 .data_size = DATA_FRAME_SIZE,
2080 .desc_size = RXD_DESC_SIZE,
2081 .priv_size = sizeof(struct queue_entry_priv_usb_rx),
2082};
2083
2084static const struct data_queue_desc rt73usb_queue_tx = {
2085 .entry_num = TX_ENTRIES,
2086 .data_size = DATA_FRAME_SIZE,
2087 .desc_size = TXD_DESC_SIZE,
2088 .priv_size = sizeof(struct queue_entry_priv_usb_tx),
2089};
2090
2091static const struct data_queue_desc rt73usb_queue_bcn = {
6bb40dd1 2092 .entry_num = 4 * BEACON_ENTRIES,
181d6902
ID		 2093 .data_size = MGMT_FRAME_SIZE,
2094 .desc_size = TXINFO_SIZE,
2095 .priv_size = sizeof(struct queue_entry_priv_usb_tx),
2096};
2097
95ea3627 2098static const struct rt2x00_ops rt73usb_ops = {
2360157c 2099 .name = KBUILD_MODNAME,
6bb40dd1
ID		 2100 .max_sta_intf = 1,
2101 .max_ap_intf = 4,
95ea3627
ID		 2102 .eeprom_size = EEPROM_SIZE,
2103 .rf_size = RF_SIZE,
181d6902
ID		 2104 .rx = &rt73usb_queue_rx,
2105 .tx = &rt73usb_queue_tx,
2106 .bcn = &rt73usb_queue_bcn,
95ea3627
ID		 2107 .lib = &rt73usb_rt2x00_ops,
2108 .hw = &rt73usb_mac80211_ops,
2109#ifdef CONFIG_RT2X00_LIB_DEBUGFS
2110 .debugfs = &rt73usb_rt2x00debug,
2111#endif /* CONFIG_RT2X00_LIB_DEBUGFS */
2112};
2113
2114/*
2115 * rt73usb module information.
2116 */
2117static struct usb_device_id rt73usb_device_table[] = {
2118 /* AboCom */
2119 { USB_DEVICE(0x07b8, 0xb21d), USB_DEVICE_DATA(&rt73usb_ops) },
2120 /* Askey */
2121 { USB_DEVICE(0x1690, 0x0722), USB_DEVICE_DATA(&rt73usb_ops) },
2122 /* ASUS */
2123 { USB_DEVICE(0x0b05, 0x1723), USB_DEVICE_DATA(&rt73usb_ops) },
2124 { USB_DEVICE(0x0b05, 0x1724), USB_DEVICE_DATA(&rt73usb_ops) },
2125 /* Belkin */
2126 { USB_DEVICE(0x050d, 0x7050), USB_DEVICE_DATA(&rt73usb_ops) },
2127 { USB_DEVICE(0x050d, 0x705a), USB_DEVICE_DATA(&rt73usb_ops) },
2128 { USB_DEVICE(0x050d, 0x905b), USB_DEVICE_DATA(&rt73usb_ops) },
1f06862e 2129 { USB_DEVICE(0x050d, 0x905c), USB_DEVICE_DATA(&rt73usb_ops) },
95ea3627
ID		 2130 /* Billionton */
2131 { USB_DEVICE(0x1631, 0xc019), USB_DEVICE_DATA(&rt73usb_ops) },
2132 /* Buffalo */
2133 { USB_DEVICE(0x0411, 0x00f4), USB_DEVICE_DATA(&rt73usb_ops) },
2134 /* CNet */
2135 { USB_DEVICE(0x1371, 0x9022), USB_DEVICE_DATA(&rt73usb_ops) },
2136 { USB_DEVICE(0x1371, 0x9032), USB_DEVICE_DATA(&rt73usb_ops) },
2137 /* Conceptronic */
2138 { USB_DEVICE(0x14b2, 0x3c22), USB_DEVICE_DATA(&rt73usb_ops) },
2139 /* D-Link */
2140 { USB_DEVICE(0x07d1, 0x3c03), USB_DEVICE_DATA(&rt73usb_ops) },
2141 { USB_DEVICE(0x07d1, 0x3c04), USB_DEVICE_DATA(&rt73usb_ops) },
2142 /* Gemtek */
2143 { USB_DEVICE(0x15a9, 0x0004), USB_DEVICE_DATA(&rt73usb_ops) },
2144 /* Gigabyte */
2145 { USB_DEVICE(0x1044, 0x8008), USB_DEVICE_DATA(&rt73usb_ops) },
2146 { USB_DEVICE(0x1044, 0x800a), USB_DEVICE_DATA(&rt73usb_ops) },
2147 /* Huawei-3Com */
2148 { USB_DEVICE(0x1472, 0x0009), USB_DEVICE_DATA(&rt73usb_ops) },
2149 /* Hercules */
2150 { USB_DEVICE(0x06f8, 0xe010), USB_DEVICE_DATA(&rt73usb_ops) },
2151 { USB_DEVICE(0x06f8, 0xe020), USB_DEVICE_DATA(&rt73usb_ops) },
2152 /* Linksys */
2153 { USB_DEVICE(0x13b1, 0x0020), USB_DEVICE_DATA(&rt73usb_ops) },
2154 { USB_DEVICE(0x13b1, 0x0023), USB_DEVICE_DATA(&rt73usb_ops) },
2155 /* MSI */
2156 { USB_DEVICE(0x0db0, 0x6877), USB_DEVICE_DATA(&rt73usb_ops) },
2157 { USB_DEVICE(0x0db0, 0x6874), USB_DEVICE_DATA(&rt73usb_ops) },
2158 { USB_DEVICE(0x0db0, 0xa861), USB_DEVICE_DATA(&rt73usb_ops) },
2159 { USB_DEVICE(0x0db0, 0xa874), USB_DEVICE_DATA(&rt73usb_ops) },
2160 /* Ralink */
2161 { USB_DEVICE(0x148f, 0x2573), USB_DEVICE_DATA(&rt73usb_ops) },
2162 { USB_DEVICE(0x148f, 0x2671), USB_DEVICE_DATA(&rt73usb_ops) },
2163 /* Qcom */
2164 { USB_DEVICE(0x18e8, 0x6196), USB_DEVICE_DATA(&rt73usb_ops) },
2165 { USB_DEVICE(0x18e8, 0x6229), USB_DEVICE_DATA(&rt73usb_ops) },
2166 { USB_DEVICE(0x18e8, 0x6238), USB_DEVICE_DATA(&rt73usb_ops) },
2167 /* Senao */
2168 { USB_DEVICE(0x1740, 0x7100), USB_DEVICE_DATA(&rt73usb_ops) },
2169 /* Sitecom */
2170 { USB_DEVICE(0x0df6, 0x9712), USB_DEVICE_DATA(&rt73usb_ops) },
2171 { USB_DEVICE(0x0df6, 0x90ac), USB_DEVICE_DATA(&rt73usb_ops) },
2172 /* Surecom */
2173 { USB_DEVICE(0x0769, 0x31f3), USB_DEVICE_DATA(&rt73usb_ops) },
2174 /* Planex */
2175 { USB_DEVICE(0x2019, 0xab01), USB_DEVICE_DATA(&rt73usb_ops) },
2176 { USB_DEVICE(0x2019, 0xab50), USB_DEVICE_DATA(&rt73usb_ops) },
2177 { 0, }
2178};
2179
2180MODULE_AUTHOR(DRV_PROJECT);
2181MODULE_VERSION(DRV_VERSION);
2182MODULE_DESCRIPTION("Ralink RT73 USB Wireless LAN driver.");
2183MODULE_SUPPORTED_DEVICE("Ralink RT2571W & RT2671 USB chipset based cards");
2184MODULE_DEVICE_TABLE(usb, rt73usb_device_table);
2185MODULE_FIRMWARE(FIRMWARE_RT2571);
2186MODULE_LICENSE("GPL");
2187
2188static struct usb_driver rt73usb_driver = {
2360157c 2189 .name = KBUILD_MODNAME,
95ea3627
ID		 2190 .id_table = rt73usb_device_table,
2191 .probe = rt2x00usb_probe,
2192 .disconnect = rt2x00usb_disconnect,
2193 .suspend = rt2x00usb_suspend,
2194 .resume = rt2x00usb_resume,
2195};
2196
2197static int __init rt73usb_init(void)
2198{
2199 return usb_register(&rt73usb_driver);
2200}
2201
2202static void __exit rt73usb_exit(void)
2203{
2204 usb_deregister(&rt73usb_driver);
2205}
2206
2207module_init(rt73usb_init);
2208module_exit(rt73usb_exit);
Linux kernel - Deliverables
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