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rt2x00: Remove unused variables
[deliverable/linux.git] / drivers / net / wireless / rt2x00 / rt73usb.c
CommitLineData
95ea3627
ID		 1/*
2 Copyright (C) 2004 - 2007 rt2x00 SourceForge Project
3 <http://rt2x00.serialmonkey.com>
4
5 This program is free software; you can redistribute it and/or modify
6 it under the terms of the GNU General Public License as published by
7 the Free Software Foundation; either version 2 of the License, or
8 (at your option) any later version.
9
10 This program is distributed in the hope that it will be useful,
11 but WITHOUT ANY WARRANTY; without even the implied warranty of
12 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 GNU General Public License for more details.
14
15 You should have received a copy of the GNU General Public License
16 along with this program; if not, write to the
17 Free Software Foundation, Inc.,
18 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
19 */
20
21/*
22 Module: rt73usb
23 Abstract: rt73usb device specific routines.
24 Supported chipsets: rt2571W & rt2671.
25 */
26
27/*
28 * Set enviroment defines for rt2x00.h
29 */
30#define DRV_NAME "rt73usb"
31
32#include <linux/delay.h>
33#include <linux/etherdevice.h>
34#include <linux/init.h>
35#include <linux/kernel.h>
36#include <linux/module.h>
37#include <linux/usb.h>
38
39#include "rt2x00.h"
40#include "rt2x00usb.h"
41#include "rt73usb.h"
42
43/*
44 * Register access.
45 * All access to the CSR registers will go through the methods
46 * rt73usb_register_read and rt73usb_register_write.
47 * BBP and RF register require indirect register access,
48 * and use the CSR registers BBPCSR and RFCSR to achieve this.
49 * These indirect registers work with busy bits,
50 * and we will try maximal REGISTER_BUSY_COUNT times to access
51 * the register while taking a REGISTER_BUSY_DELAY us delay
52 * between each attampt. When the busy bit is still set at that time,
53 * the access attempt is considered to have failed,
54 * and we will print an error.
55 */
0e14f6d3 56static inline void rt73usb_register_read(struct rt2x00_dev *rt2x00dev,
95ea3627
ID		 57 const unsigned int offset, u32 *value)
58{
59 __le32 reg;
60 rt2x00usb_vendor_request_buff(rt2x00dev, USB_MULTI_READ,
61 USB_VENDOR_REQUEST_IN, offset,
62 &reg, sizeof(u32), REGISTER_TIMEOUT);
63 *value = le32_to_cpu(reg);
64}
65
0e14f6d3 66static inline void rt73usb_register_multiread(struct rt2x00_dev *rt2x00dev,
95ea3627
ID		 67 const unsigned int offset,
68 void *value, const u32 length)
69{
70 int timeout = REGISTER_TIMEOUT * (length / sizeof(u32));
71 rt2x00usb_vendor_request_buff(rt2x00dev, USB_MULTI_READ,
72 USB_VENDOR_REQUEST_IN, offset,
73 value, length, timeout);
74}
75
0e14f6d3 76static inline void rt73usb_register_write(struct rt2x00_dev *rt2x00dev,
95ea3627
ID		 77 const unsigned int offset, u32 value)
78{
79 __le32 reg = cpu_to_le32(value);
80 rt2x00usb_vendor_request_buff(rt2x00dev, USB_MULTI_WRITE,
81 USB_VENDOR_REQUEST_OUT, offset,
82 &reg, sizeof(u32), REGISTER_TIMEOUT);
83}
84
0e14f6d3 85static inline void rt73usb_register_multiwrite(struct rt2x00_dev *rt2x00dev,
95ea3627
ID		 86 const unsigned int offset,
87 void *value, const u32 length)
88{
89 int timeout = REGISTER_TIMEOUT * (length / sizeof(u32));
90 rt2x00usb_vendor_request_buff(rt2x00dev, USB_MULTI_WRITE,
91 USB_VENDOR_REQUEST_OUT, offset,
92 value, length, timeout);
93}
94
0e14f6d3 95static u32 rt73usb_bbp_check(struct rt2x00_dev *rt2x00dev)
95ea3627
ID		 96{
97 u32 reg;
98 unsigned int i;
99
100 for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
101 rt73usb_register_read(rt2x00dev, PHY_CSR3, &reg);
102 if (!rt2x00_get_field32(reg, PHY_CSR3_BUSY))
103 break;
104 udelay(REGISTER_BUSY_DELAY);
105 }
106
107 return reg;
108}
109
0e14f6d3 110static void rt73usb_bbp_write(struct rt2x00_dev *rt2x00dev,
95ea3627
ID		 111 const unsigned int word, const u8 value)
112{
113 u32 reg;
114
115 /*
116 * Wait until the BBP becomes ready.
117 */
118 reg = rt73usb_bbp_check(rt2x00dev);
119 if (rt2x00_get_field32(reg, PHY_CSR3_BUSY)) {
120 ERROR(rt2x00dev, "PHY_CSR3 register busy. Write failed.\n");
121 return;
122 }
123
124 /*
125 * Write the data into the BBP.
126 */
127 reg = 0;
128 rt2x00_set_field32(&reg, PHY_CSR3_VALUE, value);
129 rt2x00_set_field32(&reg, PHY_CSR3_REGNUM, word);
130 rt2x00_set_field32(&reg, PHY_CSR3_BUSY, 1);
131 rt2x00_set_field32(&reg, PHY_CSR3_READ_CONTROL, 0);
132
133 rt73usb_register_write(rt2x00dev, PHY_CSR3, reg);
134}
135
0e14f6d3 136static void rt73usb_bbp_read(struct rt2x00_dev *rt2x00dev,
95ea3627
ID		 137 const unsigned int word, u8 *value)
138{
139 u32 reg;
140
141 /*
142 * Wait until the BBP becomes ready.
143 */
144 reg = rt73usb_bbp_check(rt2x00dev);
145 if (rt2x00_get_field32(reg, PHY_CSR3_BUSY)) {
146 ERROR(rt2x00dev, "PHY_CSR3 register busy. Read failed.\n");
147 return;
148 }
149
150 /*
151 * Write the request into the BBP.
152 */
153 reg = 0;
154 rt2x00_set_field32(&reg, PHY_CSR3_REGNUM, word);
155 rt2x00_set_field32(&reg, PHY_CSR3_BUSY, 1);
156 rt2x00_set_field32(&reg, PHY_CSR3_READ_CONTROL, 1);
157
158 rt73usb_register_write(rt2x00dev, PHY_CSR3, reg);
159
160 /*
161 * Wait until the BBP becomes ready.
162 */
163 reg = rt73usb_bbp_check(rt2x00dev);
164 if (rt2x00_get_field32(reg, PHY_CSR3_BUSY)) {
165 ERROR(rt2x00dev, "PHY_CSR3 register busy. Read failed.\n");
166 *value = 0xff;
167 return;
168 }
169
170 *value = rt2x00_get_field32(reg, PHY_CSR3_VALUE);
171}
172
0e14f6d3 173static void rt73usb_rf_write(struct rt2x00_dev *rt2x00dev,
95ea3627
ID		 174 const unsigned int word, const u32 value)
175{
176 u32 reg;
177 unsigned int i;
178
179 if (!word)
180 return;
181
182 for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
183 rt73usb_register_read(rt2x00dev, PHY_CSR4, &reg);
184 if (!rt2x00_get_field32(reg, PHY_CSR4_BUSY))
185 goto rf_write;
186 udelay(REGISTER_BUSY_DELAY);
187 }
188
189 ERROR(rt2x00dev, "PHY_CSR4 register busy. Write failed.\n");
190 return;
191
192rf_write:
193 reg = 0;
194 rt2x00_set_field32(&reg, PHY_CSR4_VALUE, value);
195
4f5af6eb
ID		 196 /*
197 * RF5225 and RF2527 contain 21 bits per RF register value,
198 * all others contain 20 bits.
199 */
200 rt2x00_set_field32(&reg, PHY_CSR4_NUMBER_OF_BITS,
ddc827f9
ID		 201 20 + (rt2x00_rf(&rt2x00dev->chip, RF5225) ||
202 rt2x00_rf(&rt2x00dev->chip, RF2527)));
95ea3627
ID		 203 rt2x00_set_field32(&reg, PHY_CSR4_IF_SELECT, 0);
204 rt2x00_set_field32(&reg, PHY_CSR4_BUSY, 1);
205
206 rt73usb_register_write(rt2x00dev, PHY_CSR4, reg);
207 rt2x00_rf_write(rt2x00dev, word, value);
208}
209
210#ifdef CONFIG_RT2X00_LIB_DEBUGFS
211#define CSR_OFFSET(__word) ( CSR_REG_BASE + ((__word) * sizeof(u32)) )
212
0e14f6d3 213static void rt73usb_read_csr(struct rt2x00_dev *rt2x00dev,
95ea3627
ID		 214 const unsigned int word, u32 *data)
215{
216 rt73usb_register_read(rt2x00dev, CSR_OFFSET(word), data);
217}
218
0e14f6d3 219static void rt73usb_write_csr(struct rt2x00_dev *rt2x00dev,
95ea3627
ID		 220 const unsigned int word, u32 data)
221{
222 rt73usb_register_write(rt2x00dev, CSR_OFFSET(word), data);
223}
224
225static const struct rt2x00debug rt73usb_rt2x00debug = {
226 .owner = THIS_MODULE,
227 .csr = {
228 .read = rt73usb_read_csr,
229 .write = rt73usb_write_csr,
230 .word_size = sizeof(u32),
231 .word_count = CSR_REG_SIZE / sizeof(u32),
232 },
233 .eeprom = {
234 .read = rt2x00_eeprom_read,
235 .write = rt2x00_eeprom_write,
236 .word_size = sizeof(u16),
237 .word_count = EEPROM_SIZE / sizeof(u16),
238 },
239 .bbp = {
240 .read = rt73usb_bbp_read,
241 .write = rt73usb_bbp_write,
242 .word_size = sizeof(u8),
243 .word_count = BBP_SIZE / sizeof(u8),
244 },
245 .rf = {
246 .read = rt2x00_rf_read,
247 .write = rt73usb_rf_write,
248 .word_size = sizeof(u32),
249 .word_count = RF_SIZE / sizeof(u32),
250 },
251};
252#endif /* CONFIG_RT2X00_LIB_DEBUGFS */
253
254/*
255 * Configuration handlers.
256 */
4abee4bb 257static void rt73usb_config_mac_addr(struct rt2x00_dev *rt2x00dev, __le32 *mac)
95ea3627 258{
95ea3627
ID		 259 u32 tmp;
260
4abee4bb 261 tmp = le32_to_cpu(mac[1]);
95ea3627 262 rt2x00_set_field32(&tmp, MAC_CSR3_UNICAST_TO_ME_MASK, 0xff);
4abee4bb 263 mac[1] = cpu_to_le32(tmp);
95ea3627 264
4abee4bb
ID		 265 rt73usb_register_multiwrite(rt2x00dev, MAC_CSR2, mac,
266 (2 * sizeof(__le32)));
95ea3627
ID		 267}
268
4abee4bb 269static void rt73usb_config_bssid(struct rt2x00_dev *rt2x00dev, __le32 *bssid)
95ea3627 270{
95ea3627
ID		 271 u32 tmp;
272
4abee4bb 273 tmp = le32_to_cpu(bssid[1]);
95ea3627 274 rt2x00_set_field32(&tmp, MAC_CSR5_BSS_ID_MASK, 3);
4abee4bb 275 bssid[1] = cpu_to_le32(tmp);
95ea3627 276
4abee4bb
ID		 277 rt73usb_register_multiwrite(rt2x00dev, MAC_CSR4, bssid,
278 (2 * sizeof(__le32)));
95ea3627
ID		 279}
280
feb24691
ID		 281static void rt73usb_config_type(struct rt2x00_dev *rt2x00dev, const int type,
282 const int tsf_sync)
95ea3627
ID		 283{
284 u32 reg;
285
286 /*
287 * Clear current synchronisation setup.
288 * For the Beacon base registers we only need to clear
289 * the first byte since that byte contains the VALID and OWNER
290 * bits which (when set to 0) will invalidate the entire beacon.
291 */
292 rt73usb_register_write(rt2x00dev, TXRX_CSR9, 0);
293 rt73usb_register_write(rt2x00dev, HW_BEACON_BASE0, 0);
294 rt73usb_register_write(rt2x00dev, HW_BEACON_BASE1, 0);
295 rt73usb_register_write(rt2x00dev, HW_BEACON_BASE2, 0);
296 rt73usb_register_write(rt2x00dev, HW_BEACON_BASE3, 0);
297
95ea3627
ID		 298 /*
299 * Enable synchronisation.
300 */
301 rt73usb_register_read(rt2x00dev, TXRX_CSR9, &reg);
4150c572
JB		 302 rt2x00_set_field32(&reg, TXRX_CSR9_TSF_TICKING, 1);
303 rt2x00_set_field32(&reg, TXRX_CSR9_TBTT_ENABLE, 1);
95ea3627 304 rt2x00_set_field32(&reg, TXRX_CSR9_BEACON_GEN, 0);
feb24691 305 rt2x00_set_field32(&reg, TXRX_CSR9_TSF_SYNC, tsf_sync);
95ea3627
ID		 306 rt73usb_register_write(rt2x00dev, TXRX_CSR9, reg);
307}
308
5c58ee51
ID		 309static void rt73usb_config_preamble(struct rt2x00_dev *rt2x00dev,
310 const int short_preamble,
311 const int ack_timeout,
312 const int ack_consume_time)
95ea3627 313{
95ea3627 314 u32 reg;
95ea3627 315
5c58ee51
ID		 316 /*
317 * When in atomic context, reschedule and let rt2x00lib
318 * call this function again.
319 */
320 if (in_atomic()) {
321 queue_work(rt2x00dev->hw->workqueue, &rt2x00dev->config_work);
322 return;
323 }
95ea3627
ID		 324
325 rt73usb_register_read(rt2x00dev, TXRX_CSR0, &reg);
5c58ee51 326 rt2x00_set_field32(&reg, TXRX_CSR0_RX_ACK_TIMEOUT, ack_timeout);
95ea3627
ID		 327 rt73usb_register_write(rt2x00dev, TXRX_CSR0, reg);
328
329 rt73usb_register_read(rt2x00dev, TXRX_CSR4, &reg);
4f5af6eb 330 rt2x00_set_field32(&reg, TXRX_CSR4_AUTORESPOND_PREAMBLE,
5c58ee51 331 !!short_preamble);
95ea3627
ID		 332 rt73usb_register_write(rt2x00dev, TXRX_CSR4, reg);
333}
334
335static void rt73usb_config_phymode(struct rt2x00_dev *rt2x00dev,
5c58ee51 336 const int basic_rate_mask)
95ea3627 337{
5c58ee51 338 rt73usb_register_write(rt2x00dev, TXRX_CSR5, basic_rate_mask);
95ea3627
ID		 339}
340
5c58ee51
ID		 341static void rt73usb_config_channel(struct rt2x00_dev *rt2x00dev,
342 struct rf_channel *rf, const int txpower)
95ea3627
ID		 343{
344 u8 r3;
345 u8 r94;
346 u8 smart;
347
348 rt2x00_set_field32(&rf->rf3, RF3_TXPOWER, TXPOWER_TO_DEV(txpower));
349 rt2x00_set_field32(&rf->rf4, RF4_FREQ_OFFSET, rt2x00dev->freq_offset);
350
351 smart = !(rt2x00_rf(&rt2x00dev->chip, RF5225) ||
352 rt2x00_rf(&rt2x00dev->chip, RF2527));
353
354 rt73usb_bbp_read(rt2x00dev, 3, &r3);
355 rt2x00_set_field8(&r3, BBP_R3_SMART_MODE, smart);
356 rt73usb_bbp_write(rt2x00dev, 3, r3);
357
358 r94 = 6;
359 if (txpower > MAX_TXPOWER && txpower <= (MAX_TXPOWER + r94))
360 r94 += txpower - MAX_TXPOWER;
361 else if (txpower < MIN_TXPOWER && txpower >= (MIN_TXPOWER - r94))
362 r94 += txpower;
363 rt73usb_bbp_write(rt2x00dev, 94, r94);
364
365 rt73usb_rf_write(rt2x00dev, 1, rf->rf1);
366 rt73usb_rf_write(rt2x00dev, 2, rf->rf2);
367 rt73usb_rf_write(rt2x00dev, 3, rf->rf3 & ~0x00000004);
368 rt73usb_rf_write(rt2x00dev, 4, rf->rf4);
369
370 rt73usb_rf_write(rt2x00dev, 1, rf->rf1);
371 rt73usb_rf_write(rt2x00dev, 2, rf->rf2);
372 rt73usb_rf_write(rt2x00dev, 3, rf->rf3 | 0x00000004);
373 rt73usb_rf_write(rt2x00dev, 4, rf->rf4);
374
375 rt73usb_rf_write(rt2x00dev, 1, rf->rf1);
376 rt73usb_rf_write(rt2x00dev, 2, rf->rf2);
377 rt73usb_rf_write(rt2x00dev, 3, rf->rf3 & ~0x00000004);
378 rt73usb_rf_write(rt2x00dev, 4, rf->rf4);
379
380 udelay(10);
381}
382
95ea3627
ID		 383static void rt73usb_config_txpower(struct rt2x00_dev *rt2x00dev,
384 const int txpower)
385{
386 struct rf_channel rf;
387
388 rt2x00_rf_read(rt2x00dev, 1, &rf.rf1);
389 rt2x00_rf_read(rt2x00dev, 2, &rf.rf2);
390 rt2x00_rf_read(rt2x00dev, 3, &rf.rf3);
391 rt2x00_rf_read(rt2x00dev, 4, &rf.rf4);
392
5c58ee51 393 rt73usb_config_channel(rt2x00dev, &rf, txpower);
95ea3627
ID		 394}
395
396static void rt73usb_config_antenna_5x(struct rt2x00_dev *rt2x00dev,
addc81bd 397 struct antenna_setup *ant)
95ea3627
ID		 398{
399 u8 r3;
400 u8 r4;
401 u8 r77;
402
403 rt73usb_bbp_read(rt2x00dev, 3, &r3);
404 rt73usb_bbp_read(rt2x00dev, 4, &r4);
405 rt73usb_bbp_read(rt2x00dev, 77, &r77);
406
407 rt2x00_set_field8(&r3, BBP_R3_SMART_MODE, 0);
408
e4cd2ff8
ID		 409 /*
410 * Configure the TX antenna.
411 */
412 switch (ant->tx) {
413 case ANTENNA_A:
414 rt2x00_set_field8(&r77, BBP_R77_TX_ANTENNA, 0);
415 break;
416 case ANTENNA_SW_DIVERSITY:
417 case ANTENNA_HW_DIVERSITY:
418 /*
419 * NOTE: We should never come here because rt2x00lib is
420 * supposed to catch this and send us the correct antenna
421 * explicitely. However we are nog going to bug about this.
422 * Instead, just default to antenna B.
423 */
424 case ANTENNA_B:
425 rt2x00_set_field8(&r77, BBP_R77_TX_ANTENNA, 3);
426 break;
427 }
428
429 /*
430 * Configure the RX antenna.
431 */
addc81bd 432 switch (ant->rx) {
95ea3627
ID		 433 case ANTENNA_HW_DIVERSITY:
434 rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA, 2);
435 rt2x00_set_field8(&r4, BBP_R4_RX_FRAME_END,
ddc827f9 436 (rt2x00dev->curr_hwmode != HWMODE_A));
95ea3627
ID		 437 break;
438 case ANTENNA_A:
439 rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA, 1);
440 rt2x00_set_field8(&r4, BBP_R4_RX_FRAME_END, 0);
95ea3627 441 break;
39e75857
ID		 442 case ANTENNA_SW_DIVERSITY:
443 /*
444 * NOTE: We should never come here because rt2x00lib is
445 * supposed to catch this and send us the correct antenna
446 * explicitely. However we are nog going to bug about this.
447 * Instead, just default to antenna B.
448 */
95ea3627
ID		 449 case ANTENNA_B:
450 rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA, 1);
451 rt2x00_set_field8(&r4, BBP_R4_RX_FRAME_END, 0);
95ea3627
ID		 452 break;
453 }
454
455 rt73usb_bbp_write(rt2x00dev, 77, r77);
456 rt73usb_bbp_write(rt2x00dev, 3, r3);
457 rt73usb_bbp_write(rt2x00dev, 4, r4);
458}
459
460static void rt73usb_config_antenna_2x(struct rt2x00_dev *rt2x00dev,
addc81bd 461 struct antenna_setup *ant)
95ea3627
ID		 462{
463 u8 r3;
464 u8 r4;
465 u8 r77;
466
467 rt73usb_bbp_read(rt2x00dev, 3, &r3);
468 rt73usb_bbp_read(rt2x00dev, 4, &r4);
469 rt73usb_bbp_read(rt2x00dev, 77, &r77);
470
471 rt2x00_set_field8(&r3, BBP_R3_SMART_MODE, 0);
472 rt2x00_set_field8(&r4, BBP_R4_RX_FRAME_END,
473 !test_bit(CONFIG_FRAME_TYPE, &rt2x00dev->flags));
474
e4cd2ff8
ID		 475 /*
476 * Configure the TX antenna.
477 */
478 switch (ant->tx) {
479 case ANTENNA_A:
480 rt2x00_set_field8(&r77, BBP_R77_TX_ANTENNA, 0);
481 break;
482 case ANTENNA_SW_DIVERSITY:
483 case ANTENNA_HW_DIVERSITY:
484 /*
485 * NOTE: We should never come here because rt2x00lib is
486 * supposed to catch this and send us the correct antenna
487 * explicitely. However we are nog going to bug about this.
488 * Instead, just default to antenna B.
489 */
490 case ANTENNA_B:
491 rt2x00_set_field8(&r77, BBP_R77_TX_ANTENNA, 3);
492 break;
493 }
494
495 /*
496 * Configure the RX antenna.
497 */
addc81bd 498 switch (ant->rx) {
95ea3627
ID		 499 case ANTENNA_HW_DIVERSITY:
500 rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA, 2);
501 break;
502 case ANTENNA_A:
503 rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA, 1);
95ea3627 504 break;
39e75857
ID		 505 case ANTENNA_SW_DIVERSITY:
506 /*
507 * NOTE: We should never come here because rt2x00lib is
508 * supposed to catch this and send us the correct antenna
509 * explicitely. However we are nog going to bug about this.
510 * Instead, just default to antenna B.
511 */
95ea3627
ID		 512 case ANTENNA_B:
513 rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA, 1);
95ea3627
ID		 514 break;
515 }
516
517 rt73usb_bbp_write(rt2x00dev, 77, r77);
518 rt73usb_bbp_write(rt2x00dev, 3, r3);
519 rt73usb_bbp_write(rt2x00dev, 4, r4);
520}
521
522struct antenna_sel {
523 u8 word;
524 /*
525 * value[0] -> non-LNA
526 * value[1] -> LNA
527 */
528 u8 value[2];
529};
530
531static const struct antenna_sel antenna_sel_a[] = {
532 { 96, { 0x58, 0x78 } },
533 { 104, { 0x38, 0x48 } },
534 { 75, { 0xfe, 0x80 } },
535 { 86, { 0xfe, 0x80 } },
536 { 88, { 0xfe, 0x80 } },
537 { 35, { 0x60, 0x60 } },
538 { 97, { 0x58, 0x58 } },
539 { 98, { 0x58, 0x58 } },
540};
541
542static const struct antenna_sel antenna_sel_bg[] = {
543 { 96, { 0x48, 0x68 } },
544 { 104, { 0x2c, 0x3c } },
545 { 75, { 0xfe, 0x80 } },
546 { 86, { 0xfe, 0x80 } },
547 { 88, { 0xfe, 0x80 } },
548 { 35, { 0x50, 0x50 } },
549 { 97, { 0x48, 0x48 } },
550 { 98, { 0x48, 0x48 } },
551};
552
553static void rt73usb_config_antenna(struct rt2x00_dev *rt2x00dev,
addc81bd 554 struct antenna_setup *ant)
95ea3627
ID		 555{
556 const struct antenna_sel *sel;
557 unsigned int lna;
558 unsigned int i;
559 u32 reg;
560
561 rt73usb_register_read(rt2x00dev, PHY_CSR0, &reg);
562
563 if (rt2x00dev->curr_hwmode == HWMODE_A) {
564 sel = antenna_sel_a;
565 lna = test_bit(CONFIG_EXTERNAL_LNA_A, &rt2x00dev->flags);
95ea3627
ID		 566 } else {
567 sel = antenna_sel_bg;
568 lna = test_bit(CONFIG_EXTERNAL_LNA_BG, &rt2x00dev->flags);
95ea3627
ID		 569 }
570
ddc827f9
ID		 571 rt2x00_set_field32(&reg, PHY_CSR0_PA_PE_BG,
572 (rt2x00dev->curr_hwmode == HWMODE_B ||
573 rt2x00dev->curr_hwmode == HWMODE_G));
574 rt2x00_set_field32(&reg, PHY_CSR0_PA_PE_A,
575 (rt2x00dev->curr_hwmode == HWMODE_A));
576
95ea3627
ID		 577 for (i = 0; i < ARRAY_SIZE(antenna_sel_a); i++)
578 rt73usb_bbp_write(rt2x00dev, sel[i].word, sel[i].value[lna]);
579
580 rt73usb_register_write(rt2x00dev, PHY_CSR0, reg);
581
582 if (rt2x00_rf(&rt2x00dev->chip, RF5226) ||
583 rt2x00_rf(&rt2x00dev->chip, RF5225))
addc81bd 584 rt73usb_config_antenna_5x(rt2x00dev, ant);
95ea3627
ID		 585 else if (rt2x00_rf(&rt2x00dev->chip, RF2528) ||
586 rt2x00_rf(&rt2x00dev->chip, RF2527))
addc81bd 587 rt73usb_config_antenna_2x(rt2x00dev, ant);
95ea3627
ID		 588}
589
590static void rt73usb_config_duration(struct rt2x00_dev *rt2x00dev,
5c58ee51 591 struct rt2x00lib_conf *libconf)
95ea3627
ID		 592{
593 u32 reg;
594
595 rt73usb_register_read(rt2x00dev, MAC_CSR9, &reg);
5c58ee51 596 rt2x00_set_field32(&reg, MAC_CSR9_SLOT_TIME, libconf->slot_time);
95ea3627
ID		 597 rt73usb_register_write(rt2x00dev, MAC_CSR9, reg);
598
599 rt73usb_register_read(rt2x00dev, MAC_CSR8, &reg);
5c58ee51 600 rt2x00_set_field32(&reg, MAC_CSR8_SIFS, libconf->sifs);
95ea3627 601 rt2x00_set_field32(&reg, MAC_CSR8_SIFS_AFTER_RX_OFDM, 3);
5c58ee51 602 rt2x00_set_field32(&reg, MAC_CSR8_EIFS, libconf->eifs);
95ea3627
ID		 603 rt73usb_register_write(rt2x00dev, MAC_CSR8, reg);
604
605 rt73usb_register_read(rt2x00dev, TXRX_CSR0, &reg);
606 rt2x00_set_field32(&reg, TXRX_CSR0_TSF_OFFSET, IEEE80211_HEADER);
607 rt73usb_register_write(rt2x00dev, TXRX_CSR0, reg);
608
609 rt73usb_register_read(rt2x00dev, TXRX_CSR4, &reg);
610 rt2x00_set_field32(&reg, TXRX_CSR4_AUTORESPOND_ENABLE, 1);
611 rt73usb_register_write(rt2x00dev, TXRX_CSR4, reg);
612
613 rt73usb_register_read(rt2x00dev, TXRX_CSR9, &reg);
5c58ee51
ID		 614 rt2x00_set_field32(&reg, TXRX_CSR9_BEACON_INTERVAL,
615 libconf->conf->beacon_int * 16);
95ea3627
ID		 616 rt73usb_register_write(rt2x00dev, TXRX_CSR9, reg);
617}
618
619static void rt73usb_config(struct rt2x00_dev *rt2x00dev,
620 const unsigned int flags,
5c58ee51 621 struct rt2x00lib_conf *libconf)
95ea3627 622{
95ea3627 623 if (flags & CONFIG_UPDATE_PHYMODE)
5c58ee51 624 rt73usb_config_phymode(rt2x00dev, libconf->basic_rates);
95ea3627 625 if (flags & CONFIG_UPDATE_CHANNEL)
5c58ee51
ID		 626 rt73usb_config_channel(rt2x00dev, &libconf->rf,
627 libconf->conf->power_level);
95ea3627 628 if ((flags & CONFIG_UPDATE_TXPOWER) && !(flags & CONFIG_UPDATE_CHANNEL))
5c58ee51 629 rt73usb_config_txpower(rt2x00dev, libconf->conf->power_level);
95ea3627 630 if (flags & CONFIG_UPDATE_ANTENNA)
addc81bd 631 rt73usb_config_antenna(rt2x00dev, &libconf->ant);
95ea3627 632 if (flags & (CONFIG_UPDATE_SLOT_TIME | CONFIG_UPDATE_BEACON_INT))
5c58ee51 633 rt73usb_config_duration(rt2x00dev, libconf);
95ea3627
ID		 634}
635
636/*
637 * LED functions.
638 */
639static void rt73usb_enable_led(struct rt2x00_dev *rt2x00dev)
640{
641 u32 reg;
642
643 rt73usb_register_read(rt2x00dev, MAC_CSR14, &reg);
644 rt2x00_set_field32(&reg, MAC_CSR14_ON_PERIOD, 70);
645 rt2x00_set_field32(&reg, MAC_CSR14_OFF_PERIOD, 30);
646 rt73usb_register_write(rt2x00dev, MAC_CSR14, reg);
647
648 rt2x00_set_field16(&rt2x00dev->led_reg, MCU_LEDCS_RADIO_STATUS, 1);
ddc827f9
ID		 649 rt2x00_set_field16(&rt2x00dev->led_reg, MCU_LEDCS_LINK_A_STATUS,
650 (rt2x00dev->rx_status.phymode == MODE_IEEE80211A));
651 rt2x00_set_field16(&rt2x00dev->led_reg, MCU_LEDCS_LINK_BG_STATUS,
652 (rt2x00dev->rx_status.phymode != MODE_IEEE80211A));
95ea3627
ID		 653
654 rt2x00usb_vendor_request_sw(rt2x00dev, USB_LED_CONTROL, 0x0000,
655 rt2x00dev->led_reg, REGISTER_TIMEOUT);
656}
657
658static void rt73usb_disable_led(struct rt2x00_dev *rt2x00dev)
659{
660 rt2x00_set_field16(&rt2x00dev->led_reg, MCU_LEDCS_RADIO_STATUS, 0);
661 rt2x00_set_field16(&rt2x00dev->led_reg, MCU_LEDCS_LINK_BG_STATUS, 0);
662 rt2x00_set_field16(&rt2x00dev->led_reg, MCU_LEDCS_LINK_A_STATUS, 0);
663
664 rt2x00usb_vendor_request_sw(rt2x00dev, USB_LED_CONTROL, 0x0000,
665 rt2x00dev->led_reg, REGISTER_TIMEOUT);
666}
667
668static void rt73usb_activity_led(struct rt2x00_dev *rt2x00dev, int rssi)
669{
670 u32 led;
671
672 if (rt2x00dev->led_mode != LED_MODE_SIGNAL_STRENGTH)
673 return;
674
675 /*
676 * Led handling requires a positive value for the rssi,
677 * to do that correctly we need to add the correction.
678 */
679 rssi += rt2x00dev->rssi_offset;
680
681 if (rssi <= 30)
682 led = 0;
683 else if (rssi <= 39)
684 led = 1;
685 else if (rssi <= 49)
686 led = 2;
687 else if (rssi <= 53)
688 led = 3;
689 else if (rssi <= 63)
690 led = 4;
691 else
692 led = 5;
693
694 rt2x00usb_vendor_request_sw(rt2x00dev, USB_LED_CONTROL, led,
695 rt2x00dev->led_reg, REGISTER_TIMEOUT);
696}
697
698/*
699 * Link tuning
700 */
ebcf26da
ID		 701static void rt73usb_link_stats(struct rt2x00_dev *rt2x00dev,
702 struct link_qual *qual)
95ea3627
ID		 703{
704 u32 reg;
705
706 /*
707 * Update FCS error count from register.
708 */
709 rt73usb_register_read(rt2x00dev, STA_CSR0, &reg);
ebcf26da 710 qual->rx_failed = rt2x00_get_field32(reg, STA_CSR0_FCS_ERROR);
95ea3627
ID		 711
712 /*
713 * Update False CCA count from register.
714 */
715 rt73usb_register_read(rt2x00dev, STA_CSR1, &reg);
ebcf26da 716 qual->false_cca = rt2x00_get_field32(reg, STA_CSR1_FALSE_CCA_ERROR);
95ea3627
ID		 717}
718
719static void rt73usb_reset_tuner(struct rt2x00_dev *rt2x00dev)
720{
721 rt73usb_bbp_write(rt2x00dev, 17, 0x20);
722 rt2x00dev->link.vgc_level = 0x20;
723}
724
725static void rt73usb_link_tuner(struct rt2x00_dev *rt2x00dev)
726{
727 int rssi = rt2x00_get_link_rssi(&rt2x00dev->link);
728 u8 r17;
729 u8 up_bound;
730 u8 low_bound;
731
732 /*
733 * Update Led strength
734 */
735 rt73usb_activity_led(rt2x00dev, rssi);
736
737 rt73usb_bbp_read(rt2x00dev, 17, &r17);
738
739 /*
740 * Determine r17 bounds.
741 */
742 if (rt2x00dev->rx_status.phymode == MODE_IEEE80211A) {
743 low_bound = 0x28;
744 up_bound = 0x48;
745
746 if (test_bit(CONFIG_EXTERNAL_LNA_A, &rt2x00dev->flags)) {
747 low_bound += 0x10;
748 up_bound += 0x10;
749 }
750 } else {
751 if (rssi > -82) {
752 low_bound = 0x1c;
753 up_bound = 0x40;
754 } else if (rssi > -84) {
755 low_bound = 0x1c;
756 up_bound = 0x20;
757 } else {
758 low_bound = 0x1c;
759 up_bound = 0x1c;
760 }
761
762 if (test_bit(CONFIG_EXTERNAL_LNA_BG, &rt2x00dev->flags)) {
763 low_bound += 0x14;
764 up_bound += 0x10;
765 }
766 }
767
768 /*
769 * Special big-R17 for very short distance
770 */
771 if (rssi > -35) {
772 if (r17 != 0x60)
773 rt73usb_bbp_write(rt2x00dev, 17, 0x60);
774 return;
775 }
776
777 /*
778 * Special big-R17 for short distance
779 */
780 if (rssi >= -58) {
781 if (r17 != up_bound)
782 rt73usb_bbp_write(rt2x00dev, 17, up_bound);
783 return;
784 }
785
786 /*
787 * Special big-R17 for middle-short distance
788 */
789 if (rssi >= -66) {
790 low_bound += 0x10;
791 if (r17 != low_bound)
792 rt73usb_bbp_write(rt2x00dev, 17, low_bound);
793 return;
794 }
795
796 /*
797 * Special mid-R17 for middle distance
798 */
799 if (rssi >= -74) {
800 if (r17 != (low_bound + 0x10))
801 rt73usb_bbp_write(rt2x00dev, 17, low_bound + 0x08);
802 return;
803 }
804
805 /*
806 * Special case: Change up_bound based on the rssi.
807 * Lower up_bound when rssi is weaker then -74 dBm.
808 */
809 up_bound -= 2 * (-74 - rssi);
810 if (low_bound > up_bound)
811 up_bound = low_bound;
812
813 if (r17 > up_bound) {
814 rt73usb_bbp_write(rt2x00dev, 17, up_bound);
815 return;
816 }
817
818 /*
819 * r17 does not yet exceed upper limit, continue and base
820 * the r17 tuning on the false CCA count.
821 */
ebcf26da 822 if (rt2x00dev->link.qual.false_cca > 512 && r17 < up_bound) {
95ea3627
ID		 823 r17 += 4;
824 if (r17 > up_bound)
825 r17 = up_bound;
826 rt73usb_bbp_write(rt2x00dev, 17, r17);
ebcf26da 827 } else if (rt2x00dev->link.qual.false_cca < 100 && r17 > low_bound) {
95ea3627
ID		 828 r17 -= 4;
829 if (r17 < low_bound)
830 r17 = low_bound;
831 rt73usb_bbp_write(rt2x00dev, 17, r17);
832 }
833}
834
835/*
836 * Firmware name function.
837 */
838static char *rt73usb_get_firmware_name(struct rt2x00_dev *rt2x00dev)
839{
840 return FIRMWARE_RT2571;
841}
842
843/*
844 * Initialization functions.
845 */
846static int rt73usb_load_firmware(struct rt2x00_dev *rt2x00dev, void *data,
847 const size_t len)
848{
849 unsigned int i;
850 int status;
851 u32 reg;
852 char *ptr = data;
853 char *cache;
854 int buflen;
855 int timeout;
856
857 /*
858 * Wait for stable hardware.
859 */
860 for (i = 0; i < 100; i++) {
861 rt73usb_register_read(rt2x00dev, MAC_CSR0, &reg);
862 if (reg)
863 break;
864 msleep(1);
865 }
866
867 if (!reg) {
868 ERROR(rt2x00dev, "Unstable hardware.\n");
869 return -EBUSY;
870 }
871
872 /*
873 * Write firmware to device.
874 * We setup a seperate cache for this action,
875 * since we are going to write larger chunks of data
876 * then normally used cache size.
877 */
878 cache = kmalloc(CSR_CACHE_SIZE_FIRMWARE, GFP_KERNEL);
879 if (!cache) {
880 ERROR(rt2x00dev, "Failed to allocate firmware cache.\n");
881 return -ENOMEM;
882 }
883
884 for (i = 0; i < len; i += CSR_CACHE_SIZE_FIRMWARE) {
885 buflen = min_t(int, len - i, CSR_CACHE_SIZE_FIRMWARE);
886 timeout = REGISTER_TIMEOUT * (buflen / sizeof(u32));
887
888 memcpy(cache, ptr, buflen);
889
890 rt2x00usb_vendor_request(rt2x00dev, USB_MULTI_WRITE,
891 USB_VENDOR_REQUEST_OUT,
892 FIRMWARE_IMAGE_BASE + i, 0x0000,
893 cache, buflen, timeout);
894
895 ptr += buflen;
896 }
897
898 kfree(cache);
899
900 /*
901 * Send firmware request to device to load firmware,
902 * we need to specify a long timeout time.
903 */
904 status = rt2x00usb_vendor_request_sw(rt2x00dev, USB_DEVICE_MODE,
905 0x0000, USB_MODE_FIRMWARE,
906 REGISTER_TIMEOUT_FIRMWARE);
907 if (status < 0) {
908 ERROR(rt2x00dev, "Failed to write Firmware to device.\n");
909 return status;
910 }
911
912 rt73usb_disable_led(rt2x00dev);
913
914 return 0;
915}
916
917static int rt73usb_init_registers(struct rt2x00_dev *rt2x00dev)
918{
919 u32 reg;
920
921 rt73usb_register_read(rt2x00dev, TXRX_CSR0, &reg);
922 rt2x00_set_field32(&reg, TXRX_CSR0_AUTO_TX_SEQ, 1);
923 rt2x00_set_field32(&reg, TXRX_CSR0_DISABLE_RX, 0);
924 rt2x00_set_field32(&reg, TXRX_CSR0_TX_WITHOUT_WAITING, 0);
925 rt73usb_register_write(rt2x00dev, TXRX_CSR0, reg);
926
927 rt73usb_register_read(rt2x00dev, TXRX_CSR1, &reg);
928 rt2x00_set_field32(&reg, TXRX_CSR1_BBP_ID0, 47); /* CCK Signal */
929 rt2x00_set_field32(&reg, TXRX_CSR1_BBP_ID0_VALID, 1);
930 rt2x00_set_field32(&reg, TXRX_CSR1_BBP_ID1, 30); /* Rssi */
931 rt2x00_set_field32(&reg, TXRX_CSR1_BBP_ID1_VALID, 1);
932 rt2x00_set_field32(&reg, TXRX_CSR1_BBP_ID2, 42); /* OFDM Rate */
933 rt2x00_set_field32(&reg, TXRX_CSR1_BBP_ID2_VALID, 1);
934 rt2x00_set_field32(&reg, TXRX_CSR1_BBP_ID3, 30); /* Rssi */
935 rt2x00_set_field32(&reg, TXRX_CSR1_BBP_ID3_VALID, 1);
936 rt73usb_register_write(rt2x00dev, TXRX_CSR1, reg);
937
938 /*
939 * CCK TXD BBP registers
940 */
941 rt73usb_register_read(rt2x00dev, TXRX_CSR2, &reg);
942 rt2x00_set_field32(&reg, TXRX_CSR2_BBP_ID0, 13);
943 rt2x00_set_field32(&reg, TXRX_CSR2_BBP_ID0_VALID, 1);
944 rt2x00_set_field32(&reg, TXRX_CSR2_BBP_ID1, 12);
945 rt2x00_set_field32(&reg, TXRX_CSR2_BBP_ID1_VALID, 1);
946 rt2x00_set_field32(&reg, TXRX_CSR2_BBP_ID2, 11);
947 rt2x00_set_field32(&reg, TXRX_CSR2_BBP_ID2_VALID, 1);
948 rt2x00_set_field32(&reg, TXRX_CSR2_BBP_ID3, 10);
949 rt2x00_set_field32(&reg, TXRX_CSR2_BBP_ID3_VALID, 1);
950 rt73usb_register_write(rt2x00dev, TXRX_CSR2, reg);
951
952 /*
953 * OFDM TXD BBP registers
954 */
955 rt73usb_register_read(rt2x00dev, TXRX_CSR3, &reg);
956 rt2x00_set_field32(&reg, TXRX_CSR3_BBP_ID0, 7);
957 rt2x00_set_field32(&reg, TXRX_CSR3_BBP_ID0_VALID, 1);
958 rt2x00_set_field32(&reg, TXRX_CSR3_BBP_ID1, 6);
959 rt2x00_set_field32(&reg, TXRX_CSR3_BBP_ID1_VALID, 1);
960 rt2x00_set_field32(&reg, TXRX_CSR3_BBP_ID2, 5);
961 rt2x00_set_field32(&reg, TXRX_CSR3_BBP_ID2_VALID, 1);
962 rt73usb_register_write(rt2x00dev, TXRX_CSR3, reg);
963
964 rt73usb_register_read(rt2x00dev, TXRX_CSR7, &reg);
965 rt2x00_set_field32(&reg, TXRX_CSR7_ACK_CTS_6MBS, 59);
966 rt2x00_set_field32(&reg, TXRX_CSR7_ACK_CTS_9MBS, 53);
967 rt2x00_set_field32(&reg, TXRX_CSR7_ACK_CTS_12MBS, 49);
968 rt2x00_set_field32(&reg, TXRX_CSR7_ACK_CTS_18MBS, 46);
969 rt73usb_register_write(rt2x00dev, TXRX_CSR7, reg);
970
971 rt73usb_register_read(rt2x00dev, TXRX_CSR8, &reg);
972 rt2x00_set_field32(&reg, TXRX_CSR8_ACK_CTS_24MBS, 44);
973 rt2x00_set_field32(&reg, TXRX_CSR8_ACK_CTS_36MBS, 42);
974 rt2x00_set_field32(&reg, TXRX_CSR8_ACK_CTS_48MBS, 42);
975 rt2x00_set_field32(&reg, TXRX_CSR8_ACK_CTS_54MBS, 42);
976 rt73usb_register_write(rt2x00dev, TXRX_CSR8, reg);
977
978 rt73usb_register_write(rt2x00dev, TXRX_CSR15, 0x0000000f);
979
980 rt73usb_register_read(rt2x00dev, MAC_CSR6, &reg);
981 rt2x00_set_field32(&reg, MAC_CSR6_MAX_FRAME_UNIT, 0xfff);
982 rt73usb_register_write(rt2x00dev, MAC_CSR6, reg);
983
984 rt73usb_register_write(rt2x00dev, MAC_CSR10, 0x00000718);
985
986 if (rt2x00dev->ops->lib->set_device_state(rt2x00dev, STATE_AWAKE))
987 return -EBUSY;
988
989 rt73usb_register_write(rt2x00dev, MAC_CSR13, 0x00007f00);
990
991 /*
992 * Invalidate all Shared Keys (SEC_CSR0),
993 * and clear the Shared key Cipher algorithms (SEC_CSR1 & SEC_CSR5)
994 */
995 rt73usb_register_write(rt2x00dev, SEC_CSR0, 0x00000000);
996 rt73usb_register_write(rt2x00dev, SEC_CSR1, 0x00000000);
997 rt73usb_register_write(rt2x00dev, SEC_CSR5, 0x00000000);
998
999 reg = 0x000023b0;
1000 if (rt2x00_rf(&rt2x00dev->chip, RF5225) ||
1001 rt2x00_rf(&rt2x00dev->chip, RF2527))
1002 rt2x00_set_field32(&reg, PHY_CSR1_RF_RPI, 1);
1003 rt73usb_register_write(rt2x00dev, PHY_CSR1, reg);
1004
1005 rt73usb_register_write(rt2x00dev, PHY_CSR5, 0x00040a06);
1006 rt73usb_register_write(rt2x00dev, PHY_CSR6, 0x00080606);
1007 rt73usb_register_write(rt2x00dev, PHY_CSR7, 0x00000408);
1008
1009 rt73usb_register_read(rt2x00dev, AC_TXOP_CSR0, &reg);
1010 rt2x00_set_field32(&reg, AC_TXOP_CSR0_AC0_TX_OP, 0);
1011 rt2x00_set_field32(&reg, AC_TXOP_CSR0_AC1_TX_OP, 0);
1012 rt73usb_register_write(rt2x00dev, AC_TXOP_CSR0, reg);
1013
1014 rt73usb_register_read(rt2x00dev, AC_TXOP_CSR1, &reg);
1015 rt2x00_set_field32(&reg, AC_TXOP_CSR1_AC2_TX_OP, 192);
1016 rt2x00_set_field32(&reg, AC_TXOP_CSR1_AC3_TX_OP, 48);
1017 rt73usb_register_write(rt2x00dev, AC_TXOP_CSR1, reg);
1018
1019 rt73usb_register_read(rt2x00dev, MAC_CSR9, &reg);
1020 rt2x00_set_field32(&reg, MAC_CSR9_CW_SELECT, 0);
1021 rt73usb_register_write(rt2x00dev, MAC_CSR9, reg);
1022
1023 /*
1024 * We must clear the error counters.
1025 * These registers are cleared on read,
1026 * so we may pass a useless variable to store the value.
1027 */
1028 rt73usb_register_read(rt2x00dev, STA_CSR0, &reg);
1029 rt73usb_register_read(rt2x00dev, STA_CSR1, &reg);
1030 rt73usb_register_read(rt2x00dev, STA_CSR2, &reg);
1031
1032 /*
1033 * Reset MAC and BBP registers.
1034 */
1035 rt73usb_register_read(rt2x00dev, MAC_CSR1, &reg);
1036 rt2x00_set_field32(&reg, MAC_CSR1_SOFT_RESET, 1);
1037 rt2x00_set_field32(&reg, MAC_CSR1_BBP_RESET, 1);
1038 rt73usb_register_write(rt2x00dev, MAC_CSR1, reg);
1039
1040 rt73usb_register_read(rt2x00dev, MAC_CSR1, &reg);
1041 rt2x00_set_field32(&reg, MAC_CSR1_SOFT_RESET, 0);
1042 rt2x00_set_field32(&reg, MAC_CSR1_BBP_RESET, 0);
1043 rt73usb_register_write(rt2x00dev, MAC_CSR1, reg);
1044
1045 rt73usb_register_read(rt2x00dev, MAC_CSR1, &reg);
1046 rt2x00_set_field32(&reg, MAC_CSR1_HOST_READY, 1);
1047 rt73usb_register_write(rt2x00dev, MAC_CSR1, reg);
1048
1049 return 0;
1050}
1051
1052static int rt73usb_init_bbp(struct rt2x00_dev *rt2x00dev)
1053{
1054 unsigned int i;
1055 u16 eeprom;
1056 u8 reg_id;
1057 u8 value;
1058
1059 for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
1060 rt73usb_bbp_read(rt2x00dev, 0, &value);
1061 if ((value != 0xff) && (value != 0x00))
1062 goto continue_csr_init;
1063 NOTICE(rt2x00dev, "Waiting for BBP register.\n");
1064 udelay(REGISTER_BUSY_DELAY);
1065 }
1066
1067 ERROR(rt2x00dev, "BBP register access failed, aborting.\n");
1068 return -EACCES;
1069
1070continue_csr_init:
1071 rt73usb_bbp_write(rt2x00dev, 3, 0x80);
1072 rt73usb_bbp_write(rt2x00dev, 15, 0x30);
1073 rt73usb_bbp_write(rt2x00dev, 21, 0xc8);
1074 rt73usb_bbp_write(rt2x00dev, 22, 0x38);
1075 rt73usb_bbp_write(rt2x00dev, 23, 0x06);
1076 rt73usb_bbp_write(rt2x00dev, 24, 0xfe);
1077 rt73usb_bbp_write(rt2x00dev, 25, 0x0a);
1078 rt73usb_bbp_write(rt2x00dev, 26, 0x0d);
1079 rt73usb_bbp_write(rt2x00dev, 32, 0x0b);
1080 rt73usb_bbp_write(rt2x00dev, 34, 0x12);
1081 rt73usb_bbp_write(rt2x00dev, 37, 0x07);
1082 rt73usb_bbp_write(rt2x00dev, 39, 0xf8);
1083 rt73usb_bbp_write(rt2x00dev, 41, 0x60);
1084 rt73usb_bbp_write(rt2x00dev, 53, 0x10);
1085 rt73usb_bbp_write(rt2x00dev, 54, 0x18);
1086 rt73usb_bbp_write(rt2x00dev, 60, 0x10);
1087 rt73usb_bbp_write(rt2x00dev, 61, 0x04);
1088 rt73usb_bbp_write(rt2x00dev, 62, 0x04);
1089 rt73usb_bbp_write(rt2x00dev, 75, 0xfe);
1090 rt73usb_bbp_write(rt2x00dev, 86, 0xfe);
1091 rt73usb_bbp_write(rt2x00dev, 88, 0xfe);
1092 rt73usb_bbp_write(rt2x00dev, 90, 0x0f);
1093 rt73usb_bbp_write(rt2x00dev, 99, 0x00);
1094 rt73usb_bbp_write(rt2x00dev, 102, 0x16);
1095 rt73usb_bbp_write(rt2x00dev, 107, 0x04);
1096
1097 DEBUG(rt2x00dev, "Start initialization from EEPROM...\n");
1098 for (i = 0; i < EEPROM_BBP_SIZE; i++) {
1099 rt2x00_eeprom_read(rt2x00dev, EEPROM_BBP_START + i, &eeprom);
1100
1101 if (eeprom != 0xffff && eeprom != 0x0000) {
1102 reg_id = rt2x00_get_field16(eeprom, EEPROM_BBP_REG_ID);
1103 value = rt2x00_get_field16(eeprom, EEPROM_BBP_VALUE);
1104 DEBUG(rt2x00dev, "BBP: 0x%02x, value: 0x%02x.\n",
1105 reg_id, value);
1106 rt73usb_bbp_write(rt2x00dev, reg_id, value);
1107 }
1108 }
1109 DEBUG(rt2x00dev, "...End initialization from EEPROM.\n");
1110
1111 return 0;
1112}
1113
1114/*
1115 * Device state switch handlers.
1116 */
1117static void rt73usb_toggle_rx(struct rt2x00_dev *rt2x00dev,
1118 enum dev_state state)
1119{
1120 u32 reg;
1121
1122 rt73usb_register_read(rt2x00dev, TXRX_CSR0, &reg);
1123 rt2x00_set_field32(&reg, TXRX_CSR0_DISABLE_RX,
1124 state == STATE_RADIO_RX_OFF);
1125 rt73usb_register_write(rt2x00dev, TXRX_CSR0, reg);
1126}
1127
1128static int rt73usb_enable_radio(struct rt2x00_dev *rt2x00dev)
1129{
1130 /*
1131 * Initialize all registers.
1132 */
1133 if (rt73usb_init_registers(rt2x00dev) ||
1134 rt73usb_init_bbp(rt2x00dev)) {
1135 ERROR(rt2x00dev, "Register initialization failed.\n");
1136 return -EIO;
1137 }
1138
1139 rt2x00usb_enable_radio(rt2x00dev);
1140
1141 /*
1142 * Enable LED
1143 */
1144 rt73usb_enable_led(rt2x00dev);
1145
1146 return 0;
1147}
1148
1149static void rt73usb_disable_radio(struct rt2x00_dev *rt2x00dev)
1150{
1151 /*
1152 * Disable LED
1153 */
1154 rt73usb_disable_led(rt2x00dev);
1155
1156 rt73usb_register_write(rt2x00dev, MAC_CSR10, 0x00001818);
1157
1158 /*
1159 * Disable synchronisation.
1160 */
1161 rt73usb_register_write(rt2x00dev, TXRX_CSR9, 0);
1162
1163 rt2x00usb_disable_radio(rt2x00dev);
1164}
1165
1166static int rt73usb_set_state(struct rt2x00_dev *rt2x00dev, enum dev_state state)
1167{
1168 u32 reg;
1169 unsigned int i;
1170 char put_to_sleep;
1171 char current_state;
1172
1173 put_to_sleep = (state != STATE_AWAKE);
1174
1175 rt73usb_register_read(rt2x00dev, MAC_CSR12, &reg);
1176 rt2x00_set_field32(&reg, MAC_CSR12_FORCE_WAKEUP, !put_to_sleep);
1177 rt2x00_set_field32(&reg, MAC_CSR12_PUT_TO_SLEEP, put_to_sleep);
1178 rt73usb_register_write(rt2x00dev, MAC_CSR12, reg);
1179
1180 /*
1181 * Device is not guaranteed to be in the requested state yet.
1182 * We must wait until the register indicates that the
1183 * device has entered the correct state.
1184 */
1185 for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
1186 rt73usb_register_read(rt2x00dev, MAC_CSR12, &reg);
1187 current_state =
1188 rt2x00_get_field32(reg, MAC_CSR12_BBP_CURRENT_STATE);
1189 if (current_state == !put_to_sleep)
1190 return 0;
1191 msleep(10);
1192 }
1193
1194 NOTICE(rt2x00dev, "Device failed to enter state %d, "
1195 "current device state %d.\n", !put_to_sleep, current_state);
1196
1197 return -EBUSY;
1198}
1199
1200static int rt73usb_set_device_state(struct rt2x00_dev *rt2x00dev,
1201 enum dev_state state)
1202{
1203 int retval = 0;
1204
1205 switch (state) {
1206 case STATE_RADIO_ON:
1207 retval = rt73usb_enable_radio(rt2x00dev);
1208 break;
1209 case STATE_RADIO_OFF:
1210 rt73usb_disable_radio(rt2x00dev);
1211 break;
1212 case STATE_RADIO_RX_ON:
1213 case STATE_RADIO_RX_OFF:
1214 rt73usb_toggle_rx(rt2x00dev, state);
1215 break;
1216 case STATE_DEEP_SLEEP:
1217 case STATE_SLEEP:
1218 case STATE_STANDBY:
1219 case STATE_AWAKE:
1220 retval = rt73usb_set_state(rt2x00dev, state);
1221 break;
1222 default:
1223 retval = -ENOTSUPP;
1224 break;
1225 }
1226
1227 return retval;
1228}
1229
1230/*
1231 * TX descriptor initialization
1232 */
1233static void rt73usb_write_tx_desc(struct rt2x00_dev *rt2x00dev,
1234 struct data_desc *txd,
4150c572 1235 struct txdata_entry_desc *desc,
95ea3627
ID		 1236 struct ieee80211_hdr *ieee80211hdr,
1237 unsigned int length,
1238 struct ieee80211_tx_control *control)
1239{
1240 u32 word;
1241
1242 /*
1243 * Start writing the descriptor words.
1244 */
1245 rt2x00_desc_read(txd, 1, &word);
1246 rt2x00_set_field32(&word, TXD_W1_HOST_Q_ID, desc->queue);
1247 rt2x00_set_field32(&word, TXD_W1_AIFSN, desc->aifs);
1248 rt2x00_set_field32(&word, TXD_W1_CWMIN, desc->cw_min);
1249 rt2x00_set_field32(&word, TXD_W1_CWMAX, desc->cw_max);
1250 rt2x00_set_field32(&word, TXD_W1_IV_OFFSET, IEEE80211_HEADER);
1251 rt2x00_set_field32(&word, TXD_W1_HW_SEQUENCE, 1);
1252 rt2x00_desc_write(txd, 1, word);
1253
1254 rt2x00_desc_read(txd, 2, &word);
1255 rt2x00_set_field32(&word, TXD_W2_PLCP_SIGNAL, desc->signal);
1256 rt2x00_set_field32(&word, TXD_W2_PLCP_SERVICE, desc->service);
1257 rt2x00_set_field32(&word, TXD_W2_PLCP_LENGTH_LOW, desc->length_low);
1258 rt2x00_set_field32(&word, TXD_W2_PLCP_LENGTH_HIGH, desc->length_high);
1259 rt2x00_desc_write(txd, 2, word);
1260
1261 rt2x00_desc_read(txd, 5, &word);
1262 rt2x00_set_field32(&word, TXD_W5_TX_POWER,
1263 TXPOWER_TO_DEV(control->power_level));
1264 rt2x00_set_field32(&word, TXD_W5_WAITING_DMA_DONE_INT, 1);
1265 rt2x00_desc_write(txd, 5, word);
1266
1267 rt2x00_desc_read(txd, 0, &word);
1268 rt2x00_set_field32(&word, TXD_W0_BURST,
1269 test_bit(ENTRY_TXD_BURST, &desc->flags));
1270 rt2x00_set_field32(&word, TXD_W0_VALID, 1);
1271 rt2x00_set_field32(&word, TXD_W0_MORE_FRAG,
1272 test_bit(ENTRY_TXD_MORE_FRAG, &desc->flags));
1273 rt2x00_set_field32(&word, TXD_W0_ACK,
1274 !(control->flags & IEEE80211_TXCTL_NO_ACK));
1275 rt2x00_set_field32(&word, TXD_W0_TIMESTAMP,
1276 test_bit(ENTRY_TXD_REQ_TIMESTAMP, &desc->flags));
1277 rt2x00_set_field32(&word, TXD_W0_OFDM,
1278 test_bit(ENTRY_TXD_OFDM_RATE, &desc->flags));
1279 rt2x00_set_field32(&word, TXD_W0_IFS, desc->ifs);
1280 rt2x00_set_field32(&word, TXD_W0_RETRY_MODE,
1281 !!(control->flags &
1282 IEEE80211_TXCTL_LONG_RETRY_LIMIT));
1283 rt2x00_set_field32(&word, TXD_W0_TKIP_MIC, 0);
1284 rt2x00_set_field32(&word, TXD_W0_DATABYTE_COUNT, length);
1285 rt2x00_set_field32(&word, TXD_W0_BURST2,
1286 test_bit(ENTRY_TXD_BURST, &desc->flags));
1287 rt2x00_set_field32(&word, TXD_W0_CIPHER_ALG, CIPHER_NONE);
1288 rt2x00_desc_write(txd, 0, word);
1289}
1290
dd9fa2d2 1291static int rt73usb_get_tx_data_len(struct rt2x00_dev *rt2x00dev,
b242e891 1292 struct sk_buff *skb)
dd9fa2d2
ID		 1293{
1294 int length;
1295
1296 /*
1297 * The length _must_ be a multiple of 4,
1298 * but it must _not_ be a multiple of the USB packet size.
1299 */
1300 length = roundup(skb->len, 4);
b242e891 1301 length += (4 * !(length % rt2x00dev->usb_maxpacket));
dd9fa2d2
ID		 1302
1303 return length;
1304}
1305
95ea3627
ID		 1306/*
1307 * TX data initialization
1308 */
1309static void rt73usb_kick_tx_queue(struct rt2x00_dev *rt2x00dev,
1310 unsigned int queue)
1311{
1312 u32 reg;
1313
1314 if (queue != IEEE80211_TX_QUEUE_BEACON)
1315 return;
1316
1317 /*
1318 * For Wi-Fi faily generated beacons between participating stations.
1319 * Set TBTT phase adaptive adjustment step to 8us (default 16us)
1320 */
1321 rt73usb_register_write(rt2x00dev, TXRX_CSR10, 0x00001008);
1322
1323 rt73usb_register_read(rt2x00dev, TXRX_CSR9, &reg);
1324 if (!rt2x00_get_field32(reg, TXRX_CSR9_BEACON_GEN)) {
1325 rt2x00_set_field32(&reg, TXRX_CSR9_BEACON_GEN, 1);
1326 rt73usb_register_write(rt2x00dev, TXRX_CSR9, reg);
1327 }
1328}
1329
1330/*
1331 * RX control handlers
1332 */
1333static int rt73usb_agc_to_rssi(struct rt2x00_dev *rt2x00dev, int rxd_w1)
1334{
1335 u16 eeprom;
1336 u8 offset;
1337 u8 lna;
1338
1339 lna = rt2x00_get_field32(rxd_w1, RXD_W1_RSSI_LNA);
1340 switch (lna) {
1341 case 3:
1342 offset = 90;
1343 break;
1344 case 2:
1345 offset = 74;
1346 break;
1347 case 1:
1348 offset = 64;
1349 break;
1350 default:
1351 return 0;
1352 }
1353
1354 if (rt2x00dev->rx_status.phymode == MODE_IEEE80211A) {
1355 if (test_bit(CONFIG_EXTERNAL_LNA_A, &rt2x00dev->flags)) {
1356 if (lna == 3 || lna == 2)
1357 offset += 10;
1358 } else {
1359 if (lna == 3)
1360 offset += 6;
1361 else if (lna == 2)
1362 offset += 8;
1363 }
1364
1365 rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_OFFSET_A, &eeprom);
1366 offset -= rt2x00_get_field16(eeprom, EEPROM_RSSI_OFFSET_A_1);
1367 } else {
1368 if (test_bit(CONFIG_EXTERNAL_LNA_BG, &rt2x00dev->flags))
1369 offset += 14;
1370
1371 rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_OFFSET_BG, &eeprom);
1372 offset -= rt2x00_get_field16(eeprom, EEPROM_RSSI_OFFSET_BG_1);
1373 }
1374
1375 return rt2x00_get_field32(rxd_w1, RXD_W1_RSSI_AGC) * 2 - offset;
1376}
1377
4150c572
JB		 1378static void rt73usb_fill_rxdone(struct data_entry *entry,
1379 struct rxdata_entry_desc *desc)
95ea3627
ID		 1380{
1381 struct data_desc *rxd = (struct data_desc *)entry->skb->data;
1382 u32 word0;
1383 u32 word1;
1384
1385 rt2x00_desc_read(rxd, 0, &word0);
1386 rt2x00_desc_read(rxd, 1, &word1);
1387
4150c572
JB		 1388 desc->flags = 0;
1389 if (rt2x00_get_field32(word0, RXD_W0_CRC_ERROR))
1390 desc->flags |= RX_FLAG_FAILED_FCS_CRC;
95ea3627
ID		 1391
1392 /*
1393 * Obtain the status about this packet.
1394 */
4150c572
JB		 1395 desc->signal = rt2x00_get_field32(word1, RXD_W1_SIGNAL);
1396 desc->rssi = rt73usb_agc_to_rssi(entry->ring->rt2x00dev, word1);
1397 desc->ofdm = rt2x00_get_field32(word0, RXD_W0_OFDM);
1398 desc->size = rt2x00_get_field32(word0, RXD_W0_DATABYTE_COUNT);
95ea3627
ID		 1399
1400 /*
1401 * Pull the skb to clear the descriptor area.
1402 */
1403 skb_pull(entry->skb, entry->ring->desc_size);
1404
4150c572 1405 return;
95ea3627
ID		 1406}
1407
1408/*
1409 * Device probe functions.
1410 */
1411static int rt73usb_validate_eeprom(struct rt2x00_dev *rt2x00dev)
1412{
1413 u16 word;
1414 u8 *mac;
1415 s8 value;
1416
1417 rt2x00usb_eeprom_read(rt2x00dev, rt2x00dev->eeprom, EEPROM_SIZE);
1418
1419 /*
1420 * Start validation of the data that has been read.
1421 */
1422 mac = rt2x00_eeprom_addr(rt2x00dev, EEPROM_MAC_ADDR_0);
1423 if (!is_valid_ether_addr(mac)) {
0795af57
JP		 1424 DECLARE_MAC_BUF(macbuf);
1425
95ea3627 1426 random_ether_addr(mac);
0795af57 1427 EEPROM(rt2x00dev, "MAC: %s\n", print_mac(macbuf, mac));
95ea3627
ID		 1428 }
1429
1430 rt2x00_eeprom_read(rt2x00dev, EEPROM_ANTENNA, &word);
1431 if (word == 0xffff) {
1432 rt2x00_set_field16(&word, EEPROM_ANTENNA_NUM, 2);
362f3b6b
ID		 1433 rt2x00_set_field16(&word, EEPROM_ANTENNA_TX_DEFAULT,
1434 ANTENNA_B);
1435 rt2x00_set_field16(&word, EEPROM_ANTENNA_RX_DEFAULT,
1436 ANTENNA_B);
95ea3627
ID		 1437 rt2x00_set_field16(&word, EEPROM_ANTENNA_FRAME_TYPE, 0);
1438 rt2x00_set_field16(&word, EEPROM_ANTENNA_DYN_TXAGC, 0);
1439 rt2x00_set_field16(&word, EEPROM_ANTENNA_HARDWARE_RADIO, 0);
1440 rt2x00_set_field16(&word, EEPROM_ANTENNA_RF_TYPE, RF5226);
1441 rt2x00_eeprom_write(rt2x00dev, EEPROM_ANTENNA, word);
1442 EEPROM(rt2x00dev, "Antenna: 0x%04x\n", word);
1443 }
1444
1445 rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC, &word);
1446 if (word == 0xffff) {
1447 rt2x00_set_field16(&word, EEPROM_NIC_EXTERNAL_LNA, 0);
1448 rt2x00_eeprom_write(rt2x00dev, EEPROM_NIC, word);
1449 EEPROM(rt2x00dev, "NIC: 0x%04x\n", word);
1450 }
1451
1452 rt2x00_eeprom_read(rt2x00dev, EEPROM_LED, &word);
1453 if (word == 0xffff) {
1454 rt2x00_set_field16(&word, EEPROM_LED_POLARITY_RDY_G, 0);
1455 rt2x00_set_field16(&word, EEPROM_LED_POLARITY_RDY_A, 0);
1456 rt2x00_set_field16(&word, EEPROM_LED_POLARITY_ACT, 0);
1457 rt2x00_set_field16(&word, EEPROM_LED_POLARITY_GPIO_0, 0);
1458 rt2x00_set_field16(&word, EEPROM_LED_POLARITY_GPIO_1, 0);
1459 rt2x00_set_field16(&word, EEPROM_LED_POLARITY_GPIO_2, 0);
1460 rt2x00_set_field16(&word, EEPROM_LED_POLARITY_GPIO_3, 0);
1461 rt2x00_set_field16(&word, EEPROM_LED_POLARITY_GPIO_4, 0);
1462 rt2x00_set_field16(&word, EEPROM_LED_LED_MODE,
1463 LED_MODE_DEFAULT);
1464 rt2x00_eeprom_write(rt2x00dev, EEPROM_LED, word);
1465 EEPROM(rt2x00dev, "Led: 0x%04x\n", word);
1466 }
1467
1468 rt2x00_eeprom_read(rt2x00dev, EEPROM_FREQ, &word);
1469 if (word == 0xffff) {
1470 rt2x00_set_field16(&word, EEPROM_FREQ_OFFSET, 0);
1471 rt2x00_set_field16(&word, EEPROM_FREQ_SEQ, 0);
1472 rt2x00_eeprom_write(rt2x00dev, EEPROM_FREQ, word);
1473 EEPROM(rt2x00dev, "Freq: 0x%04x\n", word);
1474 }
1475
1476 rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_OFFSET_BG, &word);
1477 if (word == 0xffff) {
1478 rt2x00_set_field16(&word, EEPROM_RSSI_OFFSET_BG_1, 0);
1479 rt2x00_set_field16(&word, EEPROM_RSSI_OFFSET_BG_2, 0);
1480 rt2x00_eeprom_write(rt2x00dev, EEPROM_RSSI_OFFSET_BG, word);
1481 EEPROM(rt2x00dev, "RSSI OFFSET BG: 0x%04x\n", word);
1482 } else {
1483 value = rt2x00_get_field16(word, EEPROM_RSSI_OFFSET_BG_1);
1484 if (value < -10 || value > 10)
1485 rt2x00_set_field16(&word, EEPROM_RSSI_OFFSET_BG_1, 0);
1486 value = rt2x00_get_field16(word, EEPROM_RSSI_OFFSET_BG_2);
1487 if (value < -10 || value > 10)
1488 rt2x00_set_field16(&word, EEPROM_RSSI_OFFSET_BG_2, 0);
1489 rt2x00_eeprom_write(rt2x00dev, EEPROM_RSSI_OFFSET_BG, word);
1490 }
1491
1492 rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_OFFSET_A, &word);
1493 if (word == 0xffff) {
1494 rt2x00_set_field16(&word, EEPROM_RSSI_OFFSET_A_1, 0);
1495 rt2x00_set_field16(&word, EEPROM_RSSI_OFFSET_A_2, 0);
1496 rt2x00_eeprom_write(rt2x00dev, EEPROM_RSSI_OFFSET_A, word);
1497 EEPROM(rt2x00dev, "RSSI OFFSET BG: 0x%04x\n", word);
1498 } else {
1499 value = rt2x00_get_field16(word, EEPROM_RSSI_OFFSET_A_1);
1500 if (value < -10 || value > 10)
1501 rt2x00_set_field16(&word, EEPROM_RSSI_OFFSET_A_1, 0);
1502 value = rt2x00_get_field16(word, EEPROM_RSSI_OFFSET_A_2);
1503 if (value < -10 || value > 10)
1504 rt2x00_set_field16(&word, EEPROM_RSSI_OFFSET_A_2, 0);
1505 rt2x00_eeprom_write(rt2x00dev, EEPROM_RSSI_OFFSET_A, word);
1506 }
1507
1508 return 0;
1509}
1510
1511static int rt73usb_init_eeprom(struct rt2x00_dev *rt2x00dev)
1512{
1513 u32 reg;
1514 u16 value;
1515 u16 eeprom;
1516
1517 /*
1518 * Read EEPROM word for configuration.
1519 */
1520 rt2x00_eeprom_read(rt2x00dev, EEPROM_ANTENNA, &eeprom);
1521
1522 /*
1523 * Identify RF chipset.
1524 */
1525 value = rt2x00_get_field16(eeprom, EEPROM_ANTENNA_RF_TYPE);
1526 rt73usb_register_read(rt2x00dev, MAC_CSR0, &reg);
1527 rt2x00_set_chip(rt2x00dev, RT2571, value, reg);
1528
755a957d 1529 if (!rt2x00_check_rev(&rt2x00dev->chip, 0x25730)) {
95ea3627
ID		 1530 ERROR(rt2x00dev, "Invalid RT chipset detected.\n");
1531 return -ENODEV;
1532 }
1533
1534 if (!rt2x00_rf(&rt2x00dev->chip, RF5226) &&
1535 !rt2x00_rf(&rt2x00dev->chip, RF2528) &&
1536 !rt2x00_rf(&rt2x00dev->chip, RF5225) &&
1537 !rt2x00_rf(&rt2x00dev->chip, RF2527)) {
1538 ERROR(rt2x00dev, "Invalid RF chipset detected.\n");
1539 return -ENODEV;
1540 }
1541
1542 /*
1543 * Identify default antenna configuration.
1544 */
addc81bd 1545 rt2x00dev->default_ant.tx =
95ea3627 1546 rt2x00_get_field16(eeprom, EEPROM_ANTENNA_TX_DEFAULT);
addc81bd 1547 rt2x00dev->default_ant.rx =
95ea3627
ID		 1548 rt2x00_get_field16(eeprom, EEPROM_ANTENNA_RX_DEFAULT);
1549
1550 /*
1551 * Read the Frame type.
1552 */
1553 if (rt2x00_get_field16(eeprom, EEPROM_ANTENNA_FRAME_TYPE))
1554 __set_bit(CONFIG_FRAME_TYPE, &rt2x00dev->flags);
1555
1556 /*
1557 * Read frequency offset.
1558 */
1559 rt2x00_eeprom_read(rt2x00dev, EEPROM_FREQ, &eeprom);
1560 rt2x00dev->freq_offset = rt2x00_get_field16(eeprom, EEPROM_FREQ_OFFSET);
1561
1562 /*
1563 * Read external LNA informations.
1564 */
1565 rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC, &eeprom);
1566
1567 if (rt2x00_get_field16(eeprom, EEPROM_NIC_EXTERNAL_LNA)) {
1568 __set_bit(CONFIG_EXTERNAL_LNA_A, &rt2x00dev->flags);
1569 __set_bit(CONFIG_EXTERNAL_LNA_BG, &rt2x00dev->flags);
1570 }
1571
1572 /*
1573 * Store led settings, for correct led behaviour.
1574 */
1575 rt2x00_eeprom_read(rt2x00dev, EEPROM_LED, &eeprom);
1576
1577 rt2x00_set_field16(&rt2x00dev->led_reg, MCU_LEDCS_LED_MODE,
1578 rt2x00dev->led_mode);
1579 rt2x00_set_field16(&rt2x00dev->led_reg, MCU_LEDCS_POLARITY_GPIO_0,
1580 rt2x00_get_field16(eeprom,
1581 EEPROM_LED_POLARITY_GPIO_0));
1582 rt2x00_set_field16(&rt2x00dev->led_reg, MCU_LEDCS_POLARITY_GPIO_1,
1583 rt2x00_get_field16(eeprom,
1584 EEPROM_LED_POLARITY_GPIO_1));
1585 rt2x00_set_field16(&rt2x00dev->led_reg, MCU_LEDCS_POLARITY_GPIO_2,
1586 rt2x00_get_field16(eeprom,
1587 EEPROM_LED_POLARITY_GPIO_2));
1588 rt2x00_set_field16(&rt2x00dev->led_reg, MCU_LEDCS_POLARITY_GPIO_3,
1589 rt2x00_get_field16(eeprom,
1590 EEPROM_LED_POLARITY_GPIO_3));
1591 rt2x00_set_field16(&rt2x00dev->led_reg, MCU_LEDCS_POLARITY_GPIO_4,
1592 rt2x00_get_field16(eeprom,
1593 EEPROM_LED_POLARITY_GPIO_4));
1594 rt2x00_set_field16(&rt2x00dev->led_reg, MCU_LEDCS_POLARITY_ACT,
1595 rt2x00_get_field16(eeprom, EEPROM_LED_POLARITY_ACT));
1596 rt2x00_set_field16(&rt2x00dev->led_reg, MCU_LEDCS_POLARITY_READY_BG,
1597 rt2x00_get_field16(eeprom,
1598 EEPROM_LED_POLARITY_RDY_G));
1599 rt2x00_set_field16(&rt2x00dev->led_reg, MCU_LEDCS_POLARITY_READY_A,
1600 rt2x00_get_field16(eeprom,
1601 EEPROM_LED_POLARITY_RDY_A));
1602
1603 return 0;
1604}
1605
1606/*
1607 * RF value list for RF2528
1608 * Supports: 2.4 GHz
1609 */
1610static const struct rf_channel rf_vals_bg_2528[] = {
1611 { 1, 0x00002c0c, 0x00000786, 0x00068255, 0x000fea0b },
1612 { 2, 0x00002c0c, 0x00000786, 0x00068255, 0x000fea1f },
1613 { 3, 0x00002c0c, 0x0000078a, 0x00068255, 0x000fea0b },
1614 { 4, 0x00002c0c, 0x0000078a, 0x00068255, 0x000fea1f },
1615 { 5, 0x00002c0c, 0x0000078e, 0x00068255, 0x000fea0b },
1616 { 6, 0x00002c0c, 0x0000078e, 0x00068255, 0x000fea1f },
1617 { 7, 0x00002c0c, 0x00000792, 0x00068255, 0x000fea0b },
1618 { 8, 0x00002c0c, 0x00000792, 0x00068255, 0x000fea1f },
1619 { 9, 0x00002c0c, 0x00000796, 0x00068255, 0x000fea0b },
1620 { 10, 0x00002c0c, 0x00000796, 0x00068255, 0x000fea1f },
1621 { 11, 0x00002c0c, 0x0000079a, 0x00068255, 0x000fea0b },
1622 { 12, 0x00002c0c, 0x0000079a, 0x00068255, 0x000fea1f },
1623 { 13, 0x00002c0c, 0x0000079e, 0x00068255, 0x000fea0b },
1624 { 14, 0x00002c0c, 0x000007a2, 0x00068255, 0x000fea13 },
1625};
1626
1627/*
1628 * RF value list for RF5226
1629 * Supports: 2.4 GHz & 5.2 GHz
1630 */
1631static const struct rf_channel rf_vals_5226[] = {
1632 { 1, 0x00002c0c, 0x00000786, 0x00068255, 0x000fea0b },
1633 { 2, 0x00002c0c, 0x00000786, 0x00068255, 0x000fea1f },
1634 { 3, 0x00002c0c, 0x0000078a, 0x00068255, 0x000fea0b },
1635 { 4, 0x00002c0c, 0x0000078a, 0x00068255, 0x000fea1f },
1636 { 5, 0x00002c0c, 0x0000078e, 0x00068255, 0x000fea0b },
1637 { 6, 0x00002c0c, 0x0000078e, 0x00068255, 0x000fea1f },
1638 { 7, 0x00002c0c, 0x00000792, 0x00068255, 0x000fea0b },
1639 { 8, 0x00002c0c, 0x00000792, 0x00068255, 0x000fea1f },
1640 { 9, 0x00002c0c, 0x00000796, 0x00068255, 0x000fea0b },
1641 { 10, 0x00002c0c, 0x00000796, 0x00068255, 0x000fea1f },
1642 { 11, 0x00002c0c, 0x0000079a, 0x00068255, 0x000fea0b },
1643 { 12, 0x00002c0c, 0x0000079a, 0x00068255, 0x000fea1f },
1644 { 13, 0x00002c0c, 0x0000079e, 0x00068255, 0x000fea0b },
1645 { 14, 0x00002c0c, 0x000007a2, 0x00068255, 0x000fea13 },
1646
1647 /* 802.11 UNI / HyperLan 2 */
1648 { 36, 0x00002c0c, 0x0000099a, 0x00098255, 0x000fea23 },
1649 { 40, 0x00002c0c, 0x000009a2, 0x00098255, 0x000fea03 },
1650 { 44, 0x00002c0c, 0x000009a6, 0x00098255, 0x000fea0b },
1651 { 48, 0x00002c0c, 0x000009aa, 0x00098255, 0x000fea13 },
1652 { 52, 0x00002c0c, 0x000009ae, 0x00098255, 0x000fea1b },
1653 { 56, 0x00002c0c, 0x000009b2, 0x00098255, 0x000fea23 },
1654 { 60, 0x00002c0c, 0x000009ba, 0x00098255, 0x000fea03 },
1655 { 64, 0x00002c0c, 0x000009be, 0x00098255, 0x000fea0b },
1656
1657 /* 802.11 HyperLan 2 */
1658 { 100, 0x00002c0c, 0x00000a2a, 0x000b8255, 0x000fea03 },
1659 { 104, 0x00002c0c, 0x00000a2e, 0x000b8255, 0x000fea0b },
1660 { 108, 0x00002c0c, 0x00000a32, 0x000b8255, 0x000fea13 },
1661 { 112, 0x00002c0c, 0x00000a36, 0x000b8255, 0x000fea1b },
1662 { 116, 0x00002c0c, 0x00000a3a, 0x000b8255, 0x000fea23 },
1663 { 120, 0x00002c0c, 0x00000a82, 0x000b8255, 0x000fea03 },
1664 { 124, 0x00002c0c, 0x00000a86, 0x000b8255, 0x000fea0b },
1665 { 128, 0x00002c0c, 0x00000a8a, 0x000b8255, 0x000fea13 },
1666 { 132, 0x00002c0c, 0x00000a8e, 0x000b8255, 0x000fea1b },
1667 { 136, 0x00002c0c, 0x00000a92, 0x000b8255, 0x000fea23 },
1668
1669 /* 802.11 UNII */
1670 { 140, 0x00002c0c, 0x00000a9a, 0x000b8255, 0x000fea03 },
1671 { 149, 0x00002c0c, 0x00000aa2, 0x000b8255, 0x000fea1f },
1672 { 153, 0x00002c0c, 0x00000aa6, 0x000b8255, 0x000fea27 },
1673 { 157, 0x00002c0c, 0x00000aae, 0x000b8255, 0x000fea07 },
1674 { 161, 0x00002c0c, 0x00000ab2, 0x000b8255, 0x000fea0f },
1675 { 165, 0x00002c0c, 0x00000ab6, 0x000b8255, 0x000fea17 },
1676
1677 /* MMAC(Japan)J52 ch 34,38,42,46 */
1678 { 34, 0x00002c0c, 0x0008099a, 0x000da255, 0x000d3a0b },
1679 { 38, 0x00002c0c, 0x0008099e, 0x000da255, 0x000d3a13 },
1680 { 42, 0x00002c0c, 0x000809a2, 0x000da255, 0x000d3a1b },
1681 { 46, 0x00002c0c, 0x000809a6, 0x000da255, 0x000d3a23 },
1682};
1683
1684/*
1685 * RF value list for RF5225 & RF2527
1686 * Supports: 2.4 GHz & 5.2 GHz
1687 */
1688static const struct rf_channel rf_vals_5225_2527[] = {
1689 { 1, 0x00002ccc, 0x00004786, 0x00068455, 0x000ffa0b },
1690 { 2, 0x00002ccc, 0x00004786, 0x00068455, 0x000ffa1f },
1691 { 3, 0x00002ccc, 0x0000478a, 0x00068455, 0x000ffa0b },
1692 { 4, 0x00002ccc, 0x0000478a, 0x00068455, 0x000ffa1f },
1693 { 5, 0x00002ccc, 0x0000478e, 0x00068455, 0x000ffa0b },
1694 { 6, 0x00002ccc, 0x0000478e, 0x00068455, 0x000ffa1f },
1695 { 7, 0x00002ccc, 0x00004792, 0x00068455, 0x000ffa0b },
1696 { 8, 0x00002ccc, 0x00004792, 0x00068455, 0x000ffa1f },
1697 { 9, 0x00002ccc, 0x00004796, 0x00068455, 0x000ffa0b },
1698 { 10, 0x00002ccc, 0x00004796, 0x00068455, 0x000ffa1f },
1699 { 11, 0x00002ccc, 0x0000479a, 0x00068455, 0x000ffa0b },
1700 { 12, 0x00002ccc, 0x0000479a, 0x00068455, 0x000ffa1f },
1701 { 13, 0x00002ccc, 0x0000479e, 0x00068455, 0x000ffa0b },
1702 { 14, 0x00002ccc, 0x000047a2, 0x00068455, 0x000ffa13 },
1703
1704 /* 802.11 UNI / HyperLan 2 */
1705 { 36, 0x00002ccc, 0x0000499a, 0x0009be55, 0x000ffa23 },
1706 { 40, 0x00002ccc, 0x000049a2, 0x0009be55, 0x000ffa03 },
1707 { 44, 0x00002ccc, 0x000049a6, 0x0009be55, 0x000ffa0b },
1708 { 48, 0x00002ccc, 0x000049aa, 0x0009be55, 0x000ffa13 },
1709 { 52, 0x00002ccc, 0x000049ae, 0x0009ae55, 0x000ffa1b },
1710 { 56, 0x00002ccc, 0x000049b2, 0x0009ae55, 0x000ffa23 },
1711 { 60, 0x00002ccc, 0x000049ba, 0x0009ae55, 0x000ffa03 },
1712 { 64, 0x00002ccc, 0x000049be, 0x0009ae55, 0x000ffa0b },
1713
1714 /* 802.11 HyperLan 2 */
1715 { 100, 0x00002ccc, 0x00004a2a, 0x000bae55, 0x000ffa03 },
1716 { 104, 0x00002ccc, 0x00004a2e, 0x000bae55, 0x000ffa0b },
1717 { 108, 0x00002ccc, 0x00004a32, 0x000bae55, 0x000ffa13 },
1718 { 112, 0x00002ccc, 0x00004a36, 0x000bae55, 0x000ffa1b },
1719 { 116, 0x00002ccc, 0x00004a3a, 0x000bbe55, 0x000ffa23 },
1720 { 120, 0x00002ccc, 0x00004a82, 0x000bbe55, 0x000ffa03 },
1721 { 124, 0x00002ccc, 0x00004a86, 0x000bbe55, 0x000ffa0b },
1722 { 128, 0x00002ccc, 0x00004a8a, 0x000bbe55, 0x000ffa13 },
1723 { 132, 0x00002ccc, 0x00004a8e, 0x000bbe55, 0x000ffa1b },
1724 { 136, 0x00002ccc, 0x00004a92, 0x000bbe55, 0x000ffa23 },
1725
1726 /* 802.11 UNII */
1727 { 140, 0x00002ccc, 0x00004a9a, 0x000bbe55, 0x000ffa03 },
1728 { 149, 0x00002ccc, 0x00004aa2, 0x000bbe55, 0x000ffa1f },
1729 { 153, 0x00002ccc, 0x00004aa6, 0x000bbe55, 0x000ffa27 },
1730 { 157, 0x00002ccc, 0x00004aae, 0x000bbe55, 0x000ffa07 },
1731 { 161, 0x00002ccc, 0x00004ab2, 0x000bbe55, 0x000ffa0f },
1732 { 165, 0x00002ccc, 0x00004ab6, 0x000bbe55, 0x000ffa17 },
1733
1734 /* MMAC(Japan)J52 ch 34,38,42,46 */
1735 { 34, 0x00002ccc, 0x0000499a, 0x0009be55, 0x000ffa0b },
1736 { 38, 0x00002ccc, 0x0000499e, 0x0009be55, 0x000ffa13 },
1737 { 42, 0x00002ccc, 0x000049a2, 0x0009be55, 0x000ffa1b },
1738 { 46, 0x00002ccc, 0x000049a6, 0x0009be55, 0x000ffa23 },
1739};
1740
1741
1742static void rt73usb_probe_hw_mode(struct rt2x00_dev *rt2x00dev)
1743{
1744 struct hw_mode_spec *spec = &rt2x00dev->spec;
1745 u8 *txpower;
1746 unsigned int i;
1747
1748 /*
1749 * Initialize all hw fields.
1750 */
1751 rt2x00dev->hw->flags =
1752 IEEE80211_HW_HOST_GEN_BEACON_TEMPLATE |
4150c572 1753 IEEE80211_HW_HOST_BROADCAST_PS_BUFFERING;
95ea3627
ID		 1754 rt2x00dev->hw->extra_tx_headroom = TXD_DESC_SIZE;
1755 rt2x00dev->hw->max_signal = MAX_SIGNAL;
1756 rt2x00dev->hw->max_rssi = MAX_RX_SSI;
1757 rt2x00dev->hw->queues = 5;
1758
1759 SET_IEEE80211_DEV(rt2x00dev->hw, &rt2x00dev_usb(rt2x00dev)->dev);
1760 SET_IEEE80211_PERM_ADDR(rt2x00dev->hw,
1761 rt2x00_eeprom_addr(rt2x00dev,
1762 EEPROM_MAC_ADDR_0));
1763
1764 /*
1765 * Convert tx_power array in eeprom.
1766 */
1767 txpower = rt2x00_eeprom_addr(rt2x00dev, EEPROM_TXPOWER_G_START);
1768 for (i = 0; i < 14; i++)
1769 txpower[i] = TXPOWER_FROM_DEV(txpower[i]);
1770
1771 /*
1772 * Initialize hw_mode information.
1773 */
1774 spec->num_modes = 2;
1775 spec->num_rates = 12;
1776 spec->tx_power_a = NULL;
1777 spec->tx_power_bg = txpower;
1778 spec->tx_power_default = DEFAULT_TXPOWER;
1779
1780 if (rt2x00_rf(&rt2x00dev->chip, RF2528)) {
1781 spec->num_channels = ARRAY_SIZE(rf_vals_bg_2528);
1782 spec->channels = rf_vals_bg_2528;
1783 } else if (rt2x00_rf(&rt2x00dev->chip, RF5226)) {
1784 spec->num_channels = ARRAY_SIZE(rf_vals_5226);
1785 spec->channels = rf_vals_5226;
1786 } else if (rt2x00_rf(&rt2x00dev->chip, RF2527)) {
1787 spec->num_channels = 14;
1788 spec->channels = rf_vals_5225_2527;
1789 } else if (rt2x00_rf(&rt2x00dev->chip, RF5225)) {
1790 spec->num_channels = ARRAY_SIZE(rf_vals_5225_2527);
1791 spec->channels = rf_vals_5225_2527;
1792 }
1793
1794 if (rt2x00_rf(&rt2x00dev->chip, RF5225) ||
1795 rt2x00_rf(&rt2x00dev->chip, RF5226)) {
1796 spec->num_modes = 3;
1797
1798 txpower = rt2x00_eeprom_addr(rt2x00dev, EEPROM_TXPOWER_A_START);
1799 for (i = 0; i < 14; i++)
1800 txpower[i] = TXPOWER_FROM_DEV(txpower[i]);
1801
1802 spec->tx_power_a = txpower;
1803 }
1804}
1805
1806static int rt73usb_probe_hw(struct rt2x00_dev *rt2x00dev)
1807{
1808 int retval;
1809
1810 /*
1811 * Allocate eeprom data.
1812 */
1813 retval = rt73usb_validate_eeprom(rt2x00dev);
1814 if (retval)
1815 return retval;
1816
1817 retval = rt73usb_init_eeprom(rt2x00dev);
1818 if (retval)
1819 return retval;
1820
1821 /*
1822 * Initialize hw specifications.
1823 */
1824 rt73usb_probe_hw_mode(rt2x00dev);
1825
1826 /*
95ea3627
ID		 1827 * This device requires firmware
1828 */
066cb637 1829 __set_bit(DRIVER_REQUIRE_FIRMWARE, &rt2x00dev->flags);
95ea3627
ID		 1830
1831 /*
1832 * Set the rssi offset.
1833 */
1834 rt2x00dev->rssi_offset = DEFAULT_RSSI_OFFSET;
1835
1836 return 0;
1837}
1838
1839/*
1840 * IEEE80211 stack callback functions.
1841 */
4150c572
JB		 1842static void rt73usb_configure_filter(struct ieee80211_hw *hw,
1843 unsigned int changed_flags,
1844 unsigned int *total_flags,
1845 int mc_count,
1846 struct dev_addr_list *mc_list)
1847{
1848 struct rt2x00_dev *rt2x00dev = hw->priv;
1849 struct interface *intf = &rt2x00dev->interface;
1850 u32 reg;
1851
1852 /*
1853 * Mask off any flags we are going to ignore from
1854 * the total_flags field.
1855 */
1856 *total_flags &=
1857 FIF_ALLMULTI |
1858 FIF_FCSFAIL |
1859 FIF_PLCPFAIL |
1860 FIF_CONTROL |
1861 FIF_OTHER_BSS |
1862 FIF_PROMISC_IN_BSS;
1863
1864 /*
1865 * Apply some rules to the filters:
1866 * - Some filters imply different filters to be set.
1867 * - Some things we can't filter out at all.
1868 * - Some filters are set based on interface type.
1869 */
1870 if (mc_count)
1871 *total_flags |= FIF_ALLMULTI;
5886d0db
ID		 1872 if (*total_flags & FIF_OTHER_BSS ||
1873 *total_flags & FIF_PROMISC_IN_BSS)
4150c572
JB		 1874 *total_flags |= FIF_PROMISC_IN_BSS | FIF_OTHER_BSS;
1875 if (is_interface_type(intf, IEEE80211_IF_TYPE_AP))
1876 *total_flags |= FIF_PROMISC_IN_BSS;
1877
1878 /*
1879 * Check if there is any work left for us.
1880 */
1881 if (intf->filter == *total_flags)
1882 return;
1883 intf->filter = *total_flags;
1884
1885 /*
1886 * When in atomic context, reschedule and let rt2x00lib
1887 * call this function again.
1888 */
1889 if (in_atomic()) {
1890 queue_work(rt2x00dev->hw->workqueue, &rt2x00dev->filter_work);
1891 return;
1892 }
1893
1894 /*
1895 * Start configuration steps.
1896 * Note that the version error will always be dropped
1897 * and broadcast frames will always be accepted since
1898 * there is no filter for it at this time.
1899 */
1900 rt73usb_register_read(rt2x00dev, TXRX_CSR0, &reg);
1901 rt2x00_set_field32(&reg, TXRX_CSR0_DROP_CRC,
1902 !(*total_flags & FIF_FCSFAIL));
1903 rt2x00_set_field32(&reg, TXRX_CSR0_DROP_PHYSICAL,
1904 !(*total_flags & FIF_PLCPFAIL));
1905 rt2x00_set_field32(&reg, TXRX_CSR0_DROP_CONTROL,
1906 !(*total_flags & FIF_CONTROL));
1907 rt2x00_set_field32(&reg, TXRX_CSR0_DROP_NOT_TO_ME,
1908 !(*total_flags & FIF_PROMISC_IN_BSS));
1909 rt2x00_set_field32(&reg, TXRX_CSR0_DROP_TO_DS,
1910 !(*total_flags & FIF_PROMISC_IN_BSS));
1911 rt2x00_set_field32(&reg, TXRX_CSR0_DROP_VERSION_ERROR, 1);
1912 rt2x00_set_field32(&reg, TXRX_CSR0_DROP_MULTICAST,
1913 !(*total_flags & FIF_ALLMULTI));
1914 rt2x00_set_field32(&reg, TXRX_CSR0_DROP_BROADCAST, 0);
1915 rt2x00_set_field32(&reg, TXRX_CSR0_DROP_ACK_CTS, 1);
1916 rt73usb_register_write(rt2x00dev, TXRX_CSR0, reg);
1917}
1918
95ea3627
ID		 1919static int rt73usb_set_retry_limit(struct ieee80211_hw *hw,
1920 u32 short_retry, u32 long_retry)
1921{
1922 struct rt2x00_dev *rt2x00dev = hw->priv;
1923 u32 reg;
1924
1925 rt73usb_register_read(rt2x00dev, TXRX_CSR4, &reg);
1926 rt2x00_set_field32(&reg, TXRX_CSR4_LONG_RETRY_LIMIT, long_retry);
1927 rt2x00_set_field32(&reg, TXRX_CSR4_SHORT_RETRY_LIMIT, short_retry);
1928 rt73usb_register_write(rt2x00dev, TXRX_CSR4, reg);
1929
1930 return 0;
1931}
1932
1933#if 0
1934/*
1935 * Mac80211 demands get_tsf must be atomic.
1936 * This is not possible for rt73usb since all register access
1937 * functions require sleeping. Untill mac80211 no longer needs
1938 * get_tsf to be atomic, this function should be disabled.
1939 */
1940static u64 rt73usb_get_tsf(struct ieee80211_hw *hw)
1941{
1942 struct rt2x00_dev *rt2x00dev = hw->priv;
1943 u64 tsf;
1944 u32 reg;
1945
1946 rt73usb_register_read(rt2x00dev, TXRX_CSR13, &reg);
1947 tsf = (u64) rt2x00_get_field32(reg, TXRX_CSR13_HIGH_TSFTIMER) << 32;
1948 rt73usb_register_read(rt2x00dev, TXRX_CSR12, &reg);
1949 tsf |= rt2x00_get_field32(reg, TXRX_CSR12_LOW_TSFTIMER);
1950
1951 return tsf;
1952}
37894473
ID		 1953#else
1954#define rt73usb_get_tsf NULL
95ea3627
ID		 1955#endif
1956
1957static void rt73usb_reset_tsf(struct ieee80211_hw *hw)
1958{
1959 struct rt2x00_dev *rt2x00dev = hw->priv;
1960
1961 rt73usb_register_write(rt2x00dev, TXRX_CSR12, 0);
1962 rt73usb_register_write(rt2x00dev, TXRX_CSR13, 0);
1963}
1964
24845910 1965static int rt73usb_beacon_update(struct ieee80211_hw *hw, struct sk_buff *skb,
95ea3627
ID		 1966 struct ieee80211_tx_control *control)
1967{
1968 struct rt2x00_dev *rt2x00dev = hw->priv;
1969 int timeout;
1970
1971 /*
1972 * Just in case the ieee80211 doesn't set this,
1973 * but we need this queue set for the descriptor
1974 * initialization.
1975 */
1976 control->queue = IEEE80211_TX_QUEUE_BEACON;
1977
1978 /*
1979 * First we create the beacon.
1980 */
1981 skb_push(skb, TXD_DESC_SIZE);
c22eb87b
ID		 1982 memset(skb->data, 0, TXD_DESC_SIZE);
1983
95ea3627
ID		 1984 rt2x00lib_write_tx_desc(rt2x00dev, (struct data_desc *)skb->data,
1985 (struct ieee80211_hdr *)(skb->data +
1986 TXD_DESC_SIZE),
1987 skb->len - TXD_DESC_SIZE, control);
1988
1989 /*
1990 * Write entire beacon with descriptor to register,
1991 * and kick the beacon generator.
1992 */
1993 timeout = REGISTER_TIMEOUT * (skb->len / sizeof(u32));
1994 rt2x00usb_vendor_request(rt2x00dev, USB_MULTI_WRITE,
1995 USB_VENDOR_REQUEST_OUT,
1996 HW_BEACON_BASE0, 0x0000,
1997 skb->data, skb->len, timeout);
1998 rt73usb_kick_tx_queue(rt2x00dev, IEEE80211_TX_QUEUE_BEACON);
1999
2000 return 0;
2001}
2002
2003static const struct ieee80211_ops rt73usb_mac80211_ops = {
2004 .tx = rt2x00mac_tx,
4150c572
JB		 2005 .start = rt2x00mac_start,
2006 .stop = rt2x00mac_stop,
95ea3627
ID		 2007 .add_interface = rt2x00mac_add_interface,
2008 .remove_interface = rt2x00mac_remove_interface,
2009 .config = rt2x00mac_config,
2010 .config_interface = rt2x00mac_config_interface,
4150c572 2011 .configure_filter = rt73usb_configure_filter,
95ea3627
ID		 2012 .get_stats = rt2x00mac_get_stats,
2013 .set_retry_limit = rt73usb_set_retry_limit,
5c58ee51 2014 .erp_ie_changed = rt2x00mac_erp_ie_changed,
95ea3627
ID		 2015 .conf_tx = rt2x00mac_conf_tx,
2016 .get_tx_stats = rt2x00mac_get_tx_stats,
95ea3627 2017 .get_tsf = rt73usb_get_tsf,
95ea3627
ID		 2018 .reset_tsf = rt73usb_reset_tsf,
2019 .beacon_update = rt73usb_beacon_update,
2020};
2021
2022static const struct rt2x00lib_ops rt73usb_rt2x00_ops = {
2023 .probe_hw = rt73usb_probe_hw,
2024 .get_firmware_name = rt73usb_get_firmware_name,
2025 .load_firmware = rt73usb_load_firmware,
2026 .initialize = rt2x00usb_initialize,
2027 .uninitialize = rt2x00usb_uninitialize,
2028 .set_device_state = rt73usb_set_device_state,
2029 .link_stats = rt73usb_link_stats,
2030 .reset_tuner = rt73usb_reset_tuner,
2031 .link_tuner = rt73usb_link_tuner,
2032 .write_tx_desc = rt73usb_write_tx_desc,
2033 .write_tx_data = rt2x00usb_write_tx_data,
dd9fa2d2 2034 .get_tx_data_len = rt73usb_get_tx_data_len,
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ID		 2035 .kick_tx_queue = rt73usb_kick_tx_queue,
2036 .fill_rxdone = rt73usb_fill_rxdone,
2037 .config_mac_addr = rt73usb_config_mac_addr,
2038 .config_bssid = rt73usb_config_bssid,
95ea3627 2039 .config_type = rt73usb_config_type,
5c58ee51 2040 .config_preamble = rt73usb_config_preamble,
95ea3627
ID		 2041 .config = rt73usb_config,
2042};
2043
2044static const struct rt2x00_ops rt73usb_ops = {
2045 .name = DRV_NAME,
2046 .rxd_size = RXD_DESC_SIZE,
2047 .txd_size = TXD_DESC_SIZE,
2048 .eeprom_size = EEPROM_SIZE,
2049 .rf_size = RF_SIZE,
2050 .lib = &rt73usb_rt2x00_ops,
2051 .hw = &rt73usb_mac80211_ops,
2052#ifdef CONFIG_RT2X00_LIB_DEBUGFS
2053 .debugfs = &rt73usb_rt2x00debug,
2054#endif /* CONFIG_RT2X00_LIB_DEBUGFS */
2055};
2056
2057/*
2058 * rt73usb module information.
2059 */
2060static struct usb_device_id rt73usb_device_table[] = {
2061 /* AboCom */
2062 { USB_DEVICE(0x07b8, 0xb21d), USB_DEVICE_DATA(&rt73usb_ops) },
2063 /* Askey */
2064 { USB_DEVICE(0x1690, 0x0722), USB_DEVICE_DATA(&rt73usb_ops) },
2065 /* ASUS */
2066 { USB_DEVICE(0x0b05, 0x1723), USB_DEVICE_DATA(&rt73usb_ops) },
2067 { USB_DEVICE(0x0b05, 0x1724), USB_DEVICE_DATA(&rt73usb_ops) },
2068 /* Belkin */
2069 { USB_DEVICE(0x050d, 0x7050), USB_DEVICE_DATA(&rt73usb_ops) },
2070 { USB_DEVICE(0x050d, 0x705a), USB_DEVICE_DATA(&rt73usb_ops) },
2071 { USB_DEVICE(0x050d, 0x905b), USB_DEVICE_DATA(&rt73usb_ops) },
1f06862e 2072 { USB_DEVICE(0x050d, 0x905c), USB_DEVICE_DATA(&rt73usb_ops) },
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ID		 2073 /* Billionton */
2074 { USB_DEVICE(0x1631, 0xc019), USB_DEVICE_DATA(&rt73usb_ops) },
2075 /* Buffalo */
2076 { USB_DEVICE(0x0411, 0x00f4), USB_DEVICE_DATA(&rt73usb_ops) },
2077 /* CNet */
2078 { USB_DEVICE(0x1371, 0x9022), USB_DEVICE_DATA(&rt73usb_ops) },
2079 { USB_DEVICE(0x1371, 0x9032), USB_DEVICE_DATA(&rt73usb_ops) },
2080 /* Conceptronic */
2081 { USB_DEVICE(0x14b2, 0x3c22), USB_DEVICE_DATA(&rt73usb_ops) },
2082 /* D-Link */
2083 { USB_DEVICE(0x07d1, 0x3c03), USB_DEVICE_DATA(&rt73usb_ops) },
2084 { USB_DEVICE(0x07d1, 0x3c04), USB_DEVICE_DATA(&rt73usb_ops) },
2085 /* Gemtek */
2086 { USB_DEVICE(0x15a9, 0x0004), USB_DEVICE_DATA(&rt73usb_ops) },
2087 /* Gigabyte */
2088 { USB_DEVICE(0x1044, 0x8008), USB_DEVICE_DATA(&rt73usb_ops) },
2089 { USB_DEVICE(0x1044, 0x800a), USB_DEVICE_DATA(&rt73usb_ops) },
2090 /* Huawei-3Com */
2091 { USB_DEVICE(0x1472, 0x0009), USB_DEVICE_DATA(&rt73usb_ops) },
2092 /* Hercules */
2093 { USB_DEVICE(0x06f8, 0xe010), USB_DEVICE_DATA(&rt73usb_ops) },
2094 { USB_DEVICE(0x06f8, 0xe020), USB_DEVICE_DATA(&rt73usb_ops) },
2095 /* Linksys */
2096 { USB_DEVICE(0x13b1, 0x0020), USB_DEVICE_DATA(&rt73usb_ops) },
2097 { USB_DEVICE(0x13b1, 0x0023), USB_DEVICE_DATA(&rt73usb_ops) },
2098 /* MSI */
2099 { USB_DEVICE(0x0db0, 0x6877), USB_DEVICE_DATA(&rt73usb_ops) },
2100 { USB_DEVICE(0x0db0, 0x6874), USB_DEVICE_DATA(&rt73usb_ops) },
2101 { USB_DEVICE(0x0db0, 0xa861), USB_DEVICE_DATA(&rt73usb_ops) },
2102 { USB_DEVICE(0x0db0, 0xa874), USB_DEVICE_DATA(&rt73usb_ops) },
2103 /* Ralink */
2104 { USB_DEVICE(0x148f, 0x2573), USB_DEVICE_DATA(&rt73usb_ops) },
2105 { USB_DEVICE(0x148f, 0x2671), USB_DEVICE_DATA(&rt73usb_ops) },
2106 /* Qcom */
2107 { USB_DEVICE(0x18e8, 0x6196), USB_DEVICE_DATA(&rt73usb_ops) },
2108 { USB_DEVICE(0x18e8, 0x6229), USB_DEVICE_DATA(&rt73usb_ops) },
2109 { USB_DEVICE(0x18e8, 0x6238), USB_DEVICE_DATA(&rt73usb_ops) },
2110 /* Senao */
2111 { USB_DEVICE(0x1740, 0x7100), USB_DEVICE_DATA(&rt73usb_ops) },
2112 /* Sitecom */
2113 { USB_DEVICE(0x0df6, 0x9712), USB_DEVICE_DATA(&rt73usb_ops) },
2114 { USB_DEVICE(0x0df6, 0x90ac), USB_DEVICE_DATA(&rt73usb_ops) },
2115 /* Surecom */
2116 { USB_DEVICE(0x0769, 0x31f3), USB_DEVICE_DATA(&rt73usb_ops) },
2117 /* Planex */
2118 { USB_DEVICE(0x2019, 0xab01), USB_DEVICE_DATA(&rt73usb_ops) },
2119 { USB_DEVICE(0x2019, 0xab50), USB_DEVICE_DATA(&rt73usb_ops) },
2120 { 0, }
2121};
2122
2123MODULE_AUTHOR(DRV_PROJECT);
2124MODULE_VERSION(DRV_VERSION);
2125MODULE_DESCRIPTION("Ralink RT73 USB Wireless LAN driver.");
2126MODULE_SUPPORTED_DEVICE("Ralink RT2571W & RT2671 USB chipset based cards");
2127MODULE_DEVICE_TABLE(usb, rt73usb_device_table);
2128MODULE_FIRMWARE(FIRMWARE_RT2571);
2129MODULE_LICENSE("GPL");
2130
2131static struct usb_driver rt73usb_driver = {
2132 .name = DRV_NAME,
2133 .id_table = rt73usb_device_table,
2134 .probe = rt2x00usb_probe,
2135 .disconnect = rt2x00usb_disconnect,
2136 .suspend = rt2x00usb_suspend,
2137 .resume = rt2x00usb_resume,
2138};
2139
2140static int __init rt73usb_init(void)
2141{
2142 return usb_register(&rt73usb_driver);
2143}
2144
2145static void __exit rt73usb_exit(void)
2146{
2147 usb_deregister(&rt73usb_driver);
2148}
2149
2150module_init(rt73usb_init);
2151module_exit(rt73usb_exit);
Linux kernel - Deliverables
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