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rt2x00: Upgrade queue->lock to use irqsave
[deliverable/linux.git] / drivers / net / wireless / rt2x00 / rt73usb.c
CommitLineData
95ea3627 1/*
811aa9ca 2 Copyright (C) 2004 - 2008 rt2x00 SourceForge Project
95ea3627
ID		 3 <http://rt2x00.serialmonkey.com>
4
5 This program is free software; you can redistribute it and/or modify
6 it under the terms of the GNU General Public License as published by
7 the Free Software Foundation; either version 2 of the License, or
8 (at your option) any later version.
9
10 This program is distributed in the hope that it will be useful,
11 but WITHOUT ANY WARRANTY; without even the implied warranty of
12 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 GNU General Public License for more details.
14
15 You should have received a copy of the GNU General Public License
16 along with this program; if not, write to the
17 Free Software Foundation, Inc.,
18 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
19 */
20
21/*
22 Module: rt73usb
23 Abstract: rt73usb device specific routines.
24 Supported chipsets: rt2571W & rt2671.
25 */
26
95ea3627
ID		 27#include <linux/delay.h>
28#include <linux/etherdevice.h>
29#include <linux/init.h>
30#include <linux/kernel.h>
31#include <linux/module.h>
32#include <linux/usb.h>
33
34#include "rt2x00.h"
35#include "rt2x00usb.h"
36#include "rt73usb.h"
37
38/*
39 * Register access.
40 * All access to the CSR registers will go through the methods
41 * rt73usb_register_read and rt73usb_register_write.
42 * BBP and RF register require indirect register access,
43 * and use the CSR registers BBPCSR and RFCSR to achieve this.
44 * These indirect registers work with busy bits,
45 * and we will try maximal REGISTER_BUSY_COUNT times to access
46 * the register while taking a REGISTER_BUSY_DELAY us delay
47 * between each attampt. When the busy bit is still set at that time,
48 * the access attempt is considered to have failed,
49 * and we will print an error.
3d82346c 50 * The _lock versions must be used if you already hold the usb_cache_mutex
95ea3627 51 */
0e14f6d3 52static inline void rt73usb_register_read(struct rt2x00_dev *rt2x00dev,
95ea3627
ID		 53 const unsigned int offset, u32 *value)
54{
55 __le32 reg;
56 rt2x00usb_vendor_request_buff(rt2x00dev, USB_MULTI_READ,
57 USB_VENDOR_REQUEST_IN, offset,
58 &reg, sizeof(u32), REGISTER_TIMEOUT);
59 *value = le32_to_cpu(reg);
60}
61
3d82346c
AB		 62static inline void rt73usb_register_read_lock(struct rt2x00_dev *rt2x00dev,
63 const unsigned int offset, u32 *value)
64{
65 __le32 reg;
66 rt2x00usb_vendor_req_buff_lock(rt2x00dev, USB_MULTI_READ,
67 USB_VENDOR_REQUEST_IN, offset,
68 &reg, sizeof(u32), REGISTER_TIMEOUT);
69 *value = le32_to_cpu(reg);
70}
71
0e14f6d3 72static inline void rt73usb_register_multiread(struct rt2x00_dev *rt2x00dev,
95ea3627
ID		 73 const unsigned int offset,
74 void *value, const u32 length)
75{
76 int timeout = REGISTER_TIMEOUT * (length / sizeof(u32));
77 rt2x00usb_vendor_request_buff(rt2x00dev, USB_MULTI_READ,
78 USB_VENDOR_REQUEST_IN, offset,
79 value, length, timeout);
80}
81
0e14f6d3 82static inline void rt73usb_register_write(struct rt2x00_dev *rt2x00dev,
95ea3627
ID		 83 const unsigned int offset, u32 value)
84{
85 __le32 reg = cpu_to_le32(value);
86 rt2x00usb_vendor_request_buff(rt2x00dev, USB_MULTI_WRITE,
87 USB_VENDOR_REQUEST_OUT, offset,
88 &reg, sizeof(u32), REGISTER_TIMEOUT);
89}
90
3d82346c
AB		 91static inline void rt73usb_register_write_lock(struct rt2x00_dev *rt2x00dev,
92 const unsigned int offset, u32 value)
93{
94 __le32 reg = cpu_to_le32(value);
95 rt2x00usb_vendor_req_buff_lock(rt2x00dev, USB_MULTI_WRITE,
96 USB_VENDOR_REQUEST_OUT, offset,
97 &reg, sizeof(u32), REGISTER_TIMEOUT);
98}
99
0e14f6d3 100static inline void rt73usb_register_multiwrite(struct rt2x00_dev *rt2x00dev,
95ea3627
ID		 101 const unsigned int offset,
102 void *value, const u32 length)
103{
104 int timeout = REGISTER_TIMEOUT * (length / sizeof(u32));
105 rt2x00usb_vendor_request_buff(rt2x00dev, USB_MULTI_WRITE,
106 USB_VENDOR_REQUEST_OUT, offset,
107 value, length, timeout);
108}
109
0e14f6d3 110static u32 rt73usb_bbp_check(struct rt2x00_dev *rt2x00dev)
95ea3627
ID		 111{
112 u32 reg;
113 unsigned int i;
114
115 for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
3d82346c 116 rt73usb_register_read_lock(rt2x00dev, PHY_CSR3, &reg);
95ea3627
ID		 117 if (!rt2x00_get_field32(reg, PHY_CSR3_BUSY))
118 break;
119 udelay(REGISTER_BUSY_DELAY);
120 }
121
122 return reg;
123}
124
0e14f6d3 125static void rt73usb_bbp_write(struct rt2x00_dev *rt2x00dev,
95ea3627
ID		 126 const unsigned int word, const u8 value)
127{
128 u32 reg;
129
3d82346c
AB		 130 mutex_lock(&rt2x00dev->usb_cache_mutex);
131
95ea3627
ID		 132 /*
133 * Wait until the BBP becomes ready.
134 */
135 reg = rt73usb_bbp_check(rt2x00dev);
136 if (rt2x00_get_field32(reg, PHY_CSR3_BUSY)) {
137 ERROR(rt2x00dev, "PHY_CSR3 register busy. Write failed.\n");
3d82346c 138 mutex_unlock(&rt2x00dev->usb_cache_mutex);
95ea3627
ID		 139 return;
140 }
141
142 /*
143 * Write the data into the BBP.
144 */
145 reg = 0;
146 rt2x00_set_field32(&reg, PHY_CSR3_VALUE, value);
147 rt2x00_set_field32(&reg, PHY_CSR3_REGNUM, word);
148 rt2x00_set_field32(&reg, PHY_CSR3_BUSY, 1);
149 rt2x00_set_field32(&reg, PHY_CSR3_READ_CONTROL, 0);
150
3d82346c
AB		 151 rt73usb_register_write_lock(rt2x00dev, PHY_CSR3, reg);
152 mutex_unlock(&rt2x00dev->usb_cache_mutex);
95ea3627
ID		 153}
154
0e14f6d3 155static void rt73usb_bbp_read(struct rt2x00_dev *rt2x00dev,
95ea3627
ID		 156 const unsigned int word, u8 *value)
157{
158 u32 reg;
159
3d82346c
AB		 160 mutex_lock(&rt2x00dev->usb_cache_mutex);
161
95ea3627
ID		 162 /*
163 * Wait until the BBP becomes ready.
164 */
165 reg = rt73usb_bbp_check(rt2x00dev);
166 if (rt2x00_get_field32(reg, PHY_CSR3_BUSY)) {
167 ERROR(rt2x00dev, "PHY_CSR3 register busy. Read failed.\n");
3d82346c 168 mutex_unlock(&rt2x00dev->usb_cache_mutex);
95ea3627
ID		 169 return;
170 }
171
172 /*
173 * Write the request into the BBP.
174 */
175 reg = 0;
176 rt2x00_set_field32(&reg, PHY_CSR3_REGNUM, word);
177 rt2x00_set_field32(&reg, PHY_CSR3_BUSY, 1);
178 rt2x00_set_field32(&reg, PHY_CSR3_READ_CONTROL, 1);
179
3d82346c 180 rt73usb_register_write_lock(rt2x00dev, PHY_CSR3, reg);
95ea3627
ID		 181
182 /*
183 * Wait until the BBP becomes ready.
184 */
185 reg = rt73usb_bbp_check(rt2x00dev);
186 if (rt2x00_get_field32(reg, PHY_CSR3_BUSY)) {
187 ERROR(rt2x00dev, "PHY_CSR3 register busy. Read failed.\n");
188 *value = 0xff;
189 return;
190 }
191
192 *value = rt2x00_get_field32(reg, PHY_CSR3_VALUE);
3d82346c 193 mutex_unlock(&rt2x00dev->usb_cache_mutex);
95ea3627
ID		 194}
195
0e14f6d3 196static void rt73usb_rf_write(struct rt2x00_dev *rt2x00dev,
95ea3627
ID		 197 const unsigned int word, const u32 value)
198{
199 u32 reg;
200 unsigned int i;
201
202 if (!word)
203 return;
204
3d82346c
AB		 205 mutex_lock(&rt2x00dev->usb_cache_mutex);
206
95ea3627 207 for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
3d82346c 208 rt73usb_register_read_lock(rt2x00dev, PHY_CSR4, &reg);
95ea3627
ID		 209 if (!rt2x00_get_field32(reg, PHY_CSR4_BUSY))
210 goto rf_write;
211 udelay(REGISTER_BUSY_DELAY);
212 }
213
3d82346c 214 mutex_unlock(&rt2x00dev->usb_cache_mutex);
95ea3627
ID		 215 ERROR(rt2x00dev, "PHY_CSR4 register busy. Write failed.\n");
216 return;
217
218rf_write:
219 reg = 0;
220 rt2x00_set_field32(&reg, PHY_CSR4_VALUE, value);
221
4f5af6eb
ID		 222 /*
223 * RF5225 and RF2527 contain 21 bits per RF register value,
224 * all others contain 20 bits.
225 */
226 rt2x00_set_field32(&reg, PHY_CSR4_NUMBER_OF_BITS,
ddc827f9
ID		 227 20 + (rt2x00_rf(&rt2x00dev->chip, RF5225) ||
228 rt2x00_rf(&rt2x00dev->chip, RF2527)));
95ea3627
ID		 229 rt2x00_set_field32(&reg, PHY_CSR4_IF_SELECT, 0);
230 rt2x00_set_field32(&reg, PHY_CSR4_BUSY, 1);
231
3d82346c 232 rt73usb_register_write_lock(rt2x00dev, PHY_CSR4, reg);
95ea3627 233 rt2x00_rf_write(rt2x00dev, word, value);
3d82346c 234 mutex_unlock(&rt2x00dev->usb_cache_mutex);
95ea3627
ID		 235}
236
237#ifdef CONFIG_RT2X00_LIB_DEBUGFS
238#define CSR_OFFSET(__word) ( CSR_REG_BASE + ((__word) * sizeof(u32)) )
239
0e14f6d3 240static void rt73usb_read_csr(struct rt2x00_dev *rt2x00dev,
95ea3627
ID		 241 const unsigned int word, u32 *data)
242{
243 rt73usb_register_read(rt2x00dev, CSR_OFFSET(word), data);
244}
245
0e14f6d3 246static void rt73usb_write_csr(struct rt2x00_dev *rt2x00dev,
95ea3627
ID		 247 const unsigned int word, u32 data)
248{
249 rt73usb_register_write(rt2x00dev, CSR_OFFSET(word), data);
250}
251
252static const struct rt2x00debug rt73usb_rt2x00debug = {
253 .owner = THIS_MODULE,
254 .csr = {
255 .read = rt73usb_read_csr,
256 .write = rt73usb_write_csr,
257 .word_size = sizeof(u32),
258 .word_count = CSR_REG_SIZE / sizeof(u32),
259 },
260 .eeprom = {
261 .read = rt2x00_eeprom_read,
262 .write = rt2x00_eeprom_write,
263 .word_size = sizeof(u16),
264 .word_count = EEPROM_SIZE / sizeof(u16),
265 },
266 .bbp = {
267 .read = rt73usb_bbp_read,
268 .write = rt73usb_bbp_write,
269 .word_size = sizeof(u8),
270 .word_count = BBP_SIZE / sizeof(u8),
271 },
272 .rf = {
273 .read = rt2x00_rf_read,
274 .write = rt73usb_rf_write,
275 .word_size = sizeof(u32),
276 .word_count = RF_SIZE / sizeof(u32),
277 },
278};
279#endif /* CONFIG_RT2X00_LIB_DEBUGFS */
280
a9450b70
ID		 281#ifdef CONFIG_RT73USB_LEDS
282static void rt73usb_led_brightness(struct led_classdev *led_cdev,
283 enum led_brightness brightness)
284{
285 struct rt2x00_led *led =
286 container_of(led_cdev, struct rt2x00_led, led_dev);
287 unsigned int enabled = brightness != LED_OFF;
288 unsigned int a_mode =
289 (enabled && led->rt2x00dev->curr_band == IEEE80211_BAND_5GHZ);
290 unsigned int bg_mode =
291 (enabled && led->rt2x00dev->curr_band == IEEE80211_BAND_2GHZ);
292
47b10cd1
ID		 293 if (in_atomic()) {
294 NOTICE(led->rt2x00dev,
61191fb2
LC		 295 "Ignoring LED brightness command for led %d\n",
296 led->type);
47b10cd1
ID		 297 return;
298 }
299
a9450b70
ID		 300 if (led->type == LED_TYPE_RADIO) {
301 rt2x00_set_field16(&led->rt2x00dev->led_mcu_reg,
302 MCU_LEDCS_RADIO_STATUS, enabled);
303
47b10cd1
ID		 304 rt2x00usb_vendor_request_sw(led->rt2x00dev, USB_LED_CONTROL,
305 0, led->rt2x00dev->led_mcu_reg,
306 REGISTER_TIMEOUT);
a9450b70
ID		 307 } else if (led->type == LED_TYPE_ASSOC) {
308 rt2x00_set_field16(&led->rt2x00dev->led_mcu_reg,
309 MCU_LEDCS_LINK_BG_STATUS, bg_mode);
310 rt2x00_set_field16(&led->rt2x00dev->led_mcu_reg,
311 MCU_LEDCS_LINK_A_STATUS, a_mode);
312
47b10cd1
ID		 313 rt2x00usb_vendor_request_sw(led->rt2x00dev, USB_LED_CONTROL,
314 0, led->rt2x00dev->led_mcu_reg,
315 REGISTER_TIMEOUT);
a9450b70
ID		 316 } else if (led->type == LED_TYPE_QUALITY) {
317 /*
318 * The brightness is divided into 6 levels (0 - 5),
319 * this means we need to convert the brightness
320 * argument into the matching level within that range.
321 */
47b10cd1
ID		 322 rt2x00usb_vendor_request_sw(led->rt2x00dev, USB_LED_CONTROL,
323 brightness / (LED_FULL / 6),
324 led->rt2x00dev->led_mcu_reg,
325 REGISTER_TIMEOUT);
a9450b70
ID		 326 }
327}
328#else
329#define rt73usb_led_brightness NULL
330#endif /* CONFIG_RT73USB_LEDS */
331
95ea3627
ID		 332/*
333 * Configuration handlers.
334 */
6bb40dd1
ID		 335static void rt73usb_config_intf(struct rt2x00_dev *rt2x00dev,
336 struct rt2x00_intf *intf,
337 struct rt2x00intf_conf *conf,
338 const unsigned int flags)
95ea3627 339{
6bb40dd1
ID		 340 unsigned int beacon_base;
341 u32 reg;
95ea3627 342
6bb40dd1
ID		 343 if (flags & CONFIG_UPDATE_TYPE) {
344 /*
345 * Clear current synchronisation setup.
346 * For the Beacon base registers we only need to clear
347 * the first byte since that byte contains the VALID and OWNER
348 * bits which (when set to 0) will invalidate the entire beacon.
349 */
350 beacon_base = HW_BEACON_OFFSET(intf->beacon->entry_idx);
6bb40dd1 351 rt73usb_register_write(rt2x00dev, beacon_base, 0);
95ea3627 352
6bb40dd1
ID		 353 /*
354 * Enable synchronisation.
355 */
356 rt73usb_register_read(rt2x00dev, TXRX_CSR9, &reg);
6bb40dd1
ID		 357 rt2x00_set_field32(&reg, TXRX_CSR9_TSF_SYNC, conf->sync);
358 rt73usb_register_write(rt2x00dev, TXRX_CSR9, reg);
359 }
95ea3627 360
6bb40dd1
ID		 361 if (flags & CONFIG_UPDATE_MAC) {
362 reg = le32_to_cpu(conf->mac[1]);
363 rt2x00_set_field32(&reg, MAC_CSR3_UNICAST_TO_ME_MASK, 0xff);
364 conf->mac[1] = cpu_to_le32(reg);
95ea3627 365
6bb40dd1
ID		 366 rt73usb_register_multiwrite(rt2x00dev, MAC_CSR2,
367 conf->mac, sizeof(conf->mac));
368 }
95ea3627 369
6bb40dd1
ID		 370 if (flags & CONFIG_UPDATE_BSSID) {
371 reg = le32_to_cpu(conf->bssid[1]);
372 rt2x00_set_field32(&reg, MAC_CSR5_BSS_ID_MASK, 3);
373 conf->bssid[1] = cpu_to_le32(reg);
95ea3627 374
6bb40dd1
ID		 375 rt73usb_register_multiwrite(rt2x00dev, MAC_CSR4,
376 conf->bssid, sizeof(conf->bssid));
377 }
95ea3627
ID		 378}
379
6bb40dd1
ID		 380static int rt73usb_config_preamble(struct rt2x00_dev *rt2x00dev,
381 const int short_preamble,
382 const int ack_timeout,
383 const int ack_consume_time)
95ea3627 384{
95ea3627 385 u32 reg;
95ea3627 386
5c58ee51 387 /*
6bb40dd1
ID		 388 * When in atomic context, we should let rt2x00lib
389 * try this configuration again later.
5c58ee51 390 */
6bb40dd1
ID		 391 if (in_atomic())
392 return -EAGAIN;
95ea3627
ID		 393
394 rt73usb_register_read(rt2x00dev, TXRX_CSR0, &reg);
5c58ee51 395 rt2x00_set_field32(&reg, TXRX_CSR0_RX_ACK_TIMEOUT, ack_timeout);
95ea3627
ID		 396 rt73usb_register_write(rt2x00dev, TXRX_CSR0, reg);
397
398 rt73usb_register_read(rt2x00dev, TXRX_CSR4, &reg);
4f5af6eb 399 rt2x00_set_field32(&reg, TXRX_CSR4_AUTORESPOND_PREAMBLE,
5c58ee51 400 !!short_preamble);
95ea3627 401 rt73usb_register_write(rt2x00dev, TXRX_CSR4, reg);
6bb40dd1
ID		 402
403 return 0;
95ea3627
ID		 404}
405
406static void rt73usb_config_phymode(struct rt2x00_dev *rt2x00dev,
5c58ee51 407 const int basic_rate_mask)
95ea3627 408{
5c58ee51 409 rt73usb_register_write(rt2x00dev, TXRX_CSR5, basic_rate_mask);
95ea3627
ID		 410}
411
5c58ee51
ID		 412static void rt73usb_config_channel(struct rt2x00_dev *rt2x00dev,
413 struct rf_channel *rf, const int txpower)
95ea3627
ID		 414{
415 u8 r3;
416 u8 r94;
417 u8 smart;
418
419 rt2x00_set_field32(&rf->rf3, RF3_TXPOWER, TXPOWER_TO_DEV(txpower));
420 rt2x00_set_field32(&rf->rf4, RF4_FREQ_OFFSET, rt2x00dev->freq_offset);
421
422 smart = !(rt2x00_rf(&rt2x00dev->chip, RF5225) ||
423 rt2x00_rf(&rt2x00dev->chip, RF2527));
424
425 rt73usb_bbp_read(rt2x00dev, 3, &r3);
426 rt2x00_set_field8(&r3, BBP_R3_SMART_MODE, smart);
427 rt73usb_bbp_write(rt2x00dev, 3, r3);
428
429 r94 = 6;
430 if (txpower > MAX_TXPOWER && txpower <= (MAX_TXPOWER + r94))
431 r94 += txpower - MAX_TXPOWER;
432 else if (txpower < MIN_TXPOWER && txpower >= (MIN_TXPOWER - r94))
433 r94 += txpower;
434 rt73usb_bbp_write(rt2x00dev, 94, r94);
435
436 rt73usb_rf_write(rt2x00dev, 1, rf->rf1);
437 rt73usb_rf_write(rt2x00dev, 2, rf->rf2);
438 rt73usb_rf_write(rt2x00dev, 3, rf->rf3 & ~0x00000004);
439 rt73usb_rf_write(rt2x00dev, 4, rf->rf4);
440
441 rt73usb_rf_write(rt2x00dev, 1, rf->rf1);
442 rt73usb_rf_write(rt2x00dev, 2, rf->rf2);
443 rt73usb_rf_write(rt2x00dev, 3, rf->rf3 | 0x00000004);
444 rt73usb_rf_write(rt2x00dev, 4, rf->rf4);
445
446 rt73usb_rf_write(rt2x00dev, 1, rf->rf1);
447 rt73usb_rf_write(rt2x00dev, 2, rf->rf2);
448 rt73usb_rf_write(rt2x00dev, 3, rf->rf3 & ~0x00000004);
449 rt73usb_rf_write(rt2x00dev, 4, rf->rf4);
450
451 udelay(10);
452}
453
95ea3627
ID		 454static void rt73usb_config_txpower(struct rt2x00_dev *rt2x00dev,
455 const int txpower)
456{
457 struct rf_channel rf;
458
459 rt2x00_rf_read(rt2x00dev, 1, &rf.rf1);
460 rt2x00_rf_read(rt2x00dev, 2, &rf.rf2);
461 rt2x00_rf_read(rt2x00dev, 3, &rf.rf3);
462 rt2x00_rf_read(rt2x00dev, 4, &rf.rf4);
463
5c58ee51 464 rt73usb_config_channel(rt2x00dev, &rf, txpower);
95ea3627
ID		 465}
466
467static void rt73usb_config_antenna_5x(struct rt2x00_dev *rt2x00dev,
addc81bd 468 struct antenna_setup *ant)
95ea3627
ID		 469{
470 u8 r3;
471 u8 r4;
472 u8 r77;
2676c94d 473 u8 temp;
95ea3627
ID		 474
475 rt73usb_bbp_read(rt2x00dev, 3, &r3);
476 rt73usb_bbp_read(rt2x00dev, 4, &r4);
477 rt73usb_bbp_read(rt2x00dev, 77, &r77);
478
479 rt2x00_set_field8(&r3, BBP_R3_SMART_MODE, 0);
480
e4cd2ff8
ID		 481 /*
482 * Configure the RX antenna.
483 */
addc81bd 484 switch (ant->rx) {
95ea3627 485 case ANTENNA_HW_DIVERSITY:
2676c94d
MN		 486 rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA_CONTROL, 2);
487 temp = !test_bit(CONFIG_FRAME_TYPE, &rt2x00dev->flags)
8318d78a 488 && (rt2x00dev->curr_band != IEEE80211_BAND_5GHZ);
2676c94d 489 rt2x00_set_field8(&r4, BBP_R4_RX_FRAME_END, temp);
95ea3627
ID		 490 break;
491 case ANTENNA_A:
2676c94d 492 rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA_CONTROL, 1);
95ea3627 493 rt2x00_set_field8(&r4, BBP_R4_RX_FRAME_END, 0);
8318d78a 494 if (rt2x00dev->curr_band == IEEE80211_BAND_5GHZ)
2676c94d
MN		 495 rt2x00_set_field8(&r77, BBP_R77_RX_ANTENNA, 0);
496 else
497 rt2x00_set_field8(&r77, BBP_R77_RX_ANTENNA, 3);
95ea3627 498 break;
39e75857
ID		 499 case ANTENNA_SW_DIVERSITY:
500 /*
501 * NOTE: We should never come here because rt2x00lib is
502 * supposed to catch this and send us the correct antenna
503 * explicitely. However we are nog going to bug about this.
504 * Instead, just default to antenna B.
505 */
95ea3627 506 case ANTENNA_B:
2676c94d 507 rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA_CONTROL, 1);
95ea3627 508 rt2x00_set_field8(&r4, BBP_R4_RX_FRAME_END, 0);
8318d78a 509 if (rt2x00dev->curr_band == IEEE80211_BAND_5GHZ)
2676c94d
MN		 510 rt2x00_set_field8(&r77, BBP_R77_RX_ANTENNA, 3);
511 else
512 rt2x00_set_field8(&r77, BBP_R77_RX_ANTENNA, 0);
95ea3627
ID		 513 break;
514 }
515
516 rt73usb_bbp_write(rt2x00dev, 77, r77);
517 rt73usb_bbp_write(rt2x00dev, 3, r3);
518 rt73usb_bbp_write(rt2x00dev, 4, r4);
519}
520
521static void rt73usb_config_antenna_2x(struct rt2x00_dev *rt2x00dev,
addc81bd 522 struct antenna_setup *ant)
95ea3627
ID		 523{
524 u8 r3;
525 u8 r4;
526 u8 r77;
527
528 rt73usb_bbp_read(rt2x00dev, 3, &r3);
529 rt73usb_bbp_read(rt2x00dev, 4, &r4);
530 rt73usb_bbp_read(rt2x00dev, 77, &r77);
531
532 rt2x00_set_field8(&r3, BBP_R3_SMART_MODE, 0);
533 rt2x00_set_field8(&r4, BBP_R4_RX_FRAME_END,
534 !test_bit(CONFIG_FRAME_TYPE, &rt2x00dev->flags));
535
e4cd2ff8
ID		 536 /*
537 * Configure the RX antenna.
538 */
addc81bd 539 switch (ant->rx) {
95ea3627 540 case ANTENNA_HW_DIVERSITY:
2676c94d 541 rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA_CONTROL, 2);
95ea3627
ID		 542 break;
543 case ANTENNA_A:
2676c94d
MN		 544 rt2x00_set_field8(&r77, BBP_R77_RX_ANTENNA, 3);
545 rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA_CONTROL, 1);
95ea3627 546 break;
39e75857
ID		 547 case ANTENNA_SW_DIVERSITY:
548 /*
549 * NOTE: We should never come here because rt2x00lib is
550 * supposed to catch this and send us the correct antenna
551 * explicitely. However we are nog going to bug about this.
552 * Instead, just default to antenna B.
553 */
95ea3627 554 case ANTENNA_B:
2676c94d
MN		 555 rt2x00_set_field8(&r77, BBP_R77_RX_ANTENNA, 0);
556 rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA_CONTROL, 1);
95ea3627
ID		 557 break;
558 }
559
560 rt73usb_bbp_write(rt2x00dev, 77, r77);
561 rt73usb_bbp_write(rt2x00dev, 3, r3);
562 rt73usb_bbp_write(rt2x00dev, 4, r4);
563}
564
565struct antenna_sel {
566 u8 word;
567 /*
568 * value[0] -> non-LNA
569 * value[1] -> LNA
570 */
571 u8 value[2];
572};
573
574static const struct antenna_sel antenna_sel_a[] = {
575 { 96, { 0x58, 0x78 } },
576 { 104, { 0x38, 0x48 } },
577 { 75, { 0xfe, 0x80 } },
578 { 86, { 0xfe, 0x80 } },
579 { 88, { 0xfe, 0x80 } },
580 { 35, { 0x60, 0x60 } },
581 { 97, { 0x58, 0x58 } },
582 { 98, { 0x58, 0x58 } },
583};
584
585static const struct antenna_sel antenna_sel_bg[] = {
586 { 96, { 0x48, 0x68 } },
587 { 104, { 0x2c, 0x3c } },
588 { 75, { 0xfe, 0x80 } },
589 { 86, { 0xfe, 0x80 } },
590 { 88, { 0xfe, 0x80 } },
591 { 35, { 0x50, 0x50 } },
592 { 97, { 0x48, 0x48 } },
593 { 98, { 0x48, 0x48 } },
594};
595
596static void rt73usb_config_antenna(struct rt2x00_dev *rt2x00dev,
addc81bd 597 struct antenna_setup *ant)
95ea3627
ID		 598{
599 const struct antenna_sel *sel;
600 unsigned int lna;
601 unsigned int i;
602 u32 reg;
603
8318d78a 604 if (rt2x00dev->curr_band == IEEE80211_BAND_5GHZ) {
95ea3627
ID		 605 sel = antenna_sel_a;
606 lna = test_bit(CONFIG_EXTERNAL_LNA_A, &rt2x00dev->flags);
95ea3627
ID		 607 } else {
608 sel = antenna_sel_bg;
609 lna = test_bit(CONFIG_EXTERNAL_LNA_BG, &rt2x00dev->flags);
95ea3627
ID		 610 }
611
2676c94d
MN		 612 for (i = 0; i < ARRAY_SIZE(antenna_sel_a); i++)
613 rt73usb_bbp_write(rt2x00dev, sel[i].word, sel[i].value[lna]);
614
615 rt73usb_register_read(rt2x00dev, PHY_CSR0, &reg);
616
ddc827f9 617 rt2x00_set_field32(&reg, PHY_CSR0_PA_PE_BG,
8318d78a 618 (rt2x00dev->curr_band == IEEE80211_BAND_2GHZ));
ddc827f9 619 rt2x00_set_field32(&reg, PHY_CSR0_PA_PE_A,
8318d78a 620 (rt2x00dev->curr_band == IEEE80211_BAND_5GHZ));
ddc827f9 621
95ea3627
ID		 622 rt73usb_register_write(rt2x00dev, PHY_CSR0, reg);
623
624 if (rt2x00_rf(&rt2x00dev->chip, RF5226) ||
625 rt2x00_rf(&rt2x00dev->chip, RF5225))
addc81bd 626 rt73usb_config_antenna_5x(rt2x00dev, ant);
95ea3627
ID		 627 else if (rt2x00_rf(&rt2x00dev->chip, RF2528) ||
628 rt2x00_rf(&rt2x00dev->chip, RF2527))
addc81bd 629 rt73usb_config_antenna_2x(rt2x00dev, ant);
95ea3627
ID		 630}
631
632static void rt73usb_config_duration(struct rt2x00_dev *rt2x00dev,
5c58ee51 633 struct rt2x00lib_conf *libconf)
95ea3627
ID		 634{
635 u32 reg;
636
637 rt73usb_register_read(rt2x00dev, MAC_CSR9, &reg);
5c58ee51 638 rt2x00_set_field32(&reg, MAC_CSR9_SLOT_TIME, libconf->slot_time);
95ea3627
ID		 639 rt73usb_register_write(rt2x00dev, MAC_CSR9, reg);
640
641 rt73usb_register_read(rt2x00dev, MAC_CSR8, &reg);
5c58ee51 642 rt2x00_set_field32(&reg, MAC_CSR8_SIFS, libconf->sifs);
95ea3627 643 rt2x00_set_field32(&reg, MAC_CSR8_SIFS_AFTER_RX_OFDM, 3);
5c58ee51 644 rt2x00_set_field32(&reg, MAC_CSR8_EIFS, libconf->eifs);
95ea3627
ID		 645 rt73usb_register_write(rt2x00dev, MAC_CSR8, reg);
646
647 rt73usb_register_read(rt2x00dev, TXRX_CSR0, &reg);
648 rt2x00_set_field32(&reg, TXRX_CSR0_TSF_OFFSET, IEEE80211_HEADER);
649 rt73usb_register_write(rt2x00dev, TXRX_CSR0, reg);
650
651 rt73usb_register_read(rt2x00dev, TXRX_CSR4, &reg);
652 rt2x00_set_field32(&reg, TXRX_CSR4_AUTORESPOND_ENABLE, 1);
653 rt73usb_register_write(rt2x00dev, TXRX_CSR4, reg);
654
655 rt73usb_register_read(rt2x00dev, TXRX_CSR9, &reg);
5c58ee51
ID		 656 rt2x00_set_field32(&reg, TXRX_CSR9_BEACON_INTERVAL,
657 libconf->conf->beacon_int * 16);
95ea3627
ID		 658 rt73usb_register_write(rt2x00dev, TXRX_CSR9, reg);
659}
660
661static void rt73usb_config(struct rt2x00_dev *rt2x00dev,
6bb40dd1
ID		 662 struct rt2x00lib_conf *libconf,
663 const unsigned int flags)
95ea3627 664{
95ea3627 665 if (flags & CONFIG_UPDATE_PHYMODE)
5c58ee51 666 rt73usb_config_phymode(rt2x00dev, libconf->basic_rates);
95ea3627 667 if (flags & CONFIG_UPDATE_CHANNEL)
5c58ee51
ID		 668 rt73usb_config_channel(rt2x00dev, &libconf->rf,
669 libconf->conf->power_level);
95ea3627 670 if ((flags & CONFIG_UPDATE_TXPOWER) && !(flags & CONFIG_UPDATE_CHANNEL))
5c58ee51 671 rt73usb_config_txpower(rt2x00dev, libconf->conf->power_level);
95ea3627 672 if (flags & CONFIG_UPDATE_ANTENNA)
addc81bd 673 rt73usb_config_antenna(rt2x00dev, &libconf->ant);
95ea3627 674 if (flags & (CONFIG_UPDATE_SLOT_TIME | CONFIG_UPDATE_BEACON_INT))
5c58ee51 675 rt73usb_config_duration(rt2x00dev, libconf);
95ea3627
ID		 676}
677
95ea3627
ID		 678/*
679 * Link tuning
680 */
ebcf26da
ID		 681static void rt73usb_link_stats(struct rt2x00_dev *rt2x00dev,
682 struct link_qual *qual)
95ea3627
ID		 683{
684 u32 reg;
685
686 /*
687 * Update FCS error count from register.
688 */
689 rt73usb_register_read(rt2x00dev, STA_CSR0, &reg);
ebcf26da 690 qual->rx_failed = rt2x00_get_field32(reg, STA_CSR0_FCS_ERROR);
95ea3627
ID		 691
692 /*
693 * Update False CCA count from register.
694 */
695 rt73usb_register_read(rt2x00dev, STA_CSR1, &reg);
ebcf26da 696 qual->false_cca = rt2x00_get_field32(reg, STA_CSR1_FALSE_CCA_ERROR);
95ea3627
ID		 697}
698
699static void rt73usb_reset_tuner(struct rt2x00_dev *rt2x00dev)
700{
701 rt73usb_bbp_write(rt2x00dev, 17, 0x20);
702 rt2x00dev->link.vgc_level = 0x20;
703}
704
705static void rt73usb_link_tuner(struct rt2x00_dev *rt2x00dev)
706{
707 int rssi = rt2x00_get_link_rssi(&rt2x00dev->link);
708 u8 r17;
709 u8 up_bound;
710 u8 low_bound;
711
95ea3627
ID		 712 rt73usb_bbp_read(rt2x00dev, 17, &r17);
713
714 /*
715 * Determine r17 bounds.
716 */
8318d78a 717 if (rt2x00dev->rx_status.band == IEEE80211_BAND_5GHZ) {
95ea3627
ID		 718 low_bound = 0x28;
719 up_bound = 0x48;
720
721 if (test_bit(CONFIG_EXTERNAL_LNA_A, &rt2x00dev->flags)) {
722 low_bound += 0x10;
723 up_bound += 0x10;
724 }
725 } else {
726 if (rssi > -82) {
727 low_bound = 0x1c;
728 up_bound = 0x40;
729 } else if (rssi > -84) {
730 low_bound = 0x1c;
731 up_bound = 0x20;
732 } else {
733 low_bound = 0x1c;
734 up_bound = 0x1c;
735 }
736
737 if (test_bit(CONFIG_EXTERNAL_LNA_BG, &rt2x00dev->flags)) {
738 low_bound += 0x14;
739 up_bound += 0x10;
740 }
741 }
742
6bb40dd1
ID		 743 /*
744 * If we are not associated, we should go straight to the
745 * dynamic CCA tuning.
746 */
747 if (!rt2x00dev->intf_associated)
748 goto dynamic_cca_tune;
749
95ea3627
ID		 750 /*
751 * Special big-R17 for very short distance
752 */
753 if (rssi > -35) {
754 if (r17 != 0x60)
755 rt73usb_bbp_write(rt2x00dev, 17, 0x60);
756 return;
757 }
758
759 /*
760 * Special big-R17 for short distance
761 */
762 if (rssi >= -58) {
763 if (r17 != up_bound)
764 rt73usb_bbp_write(rt2x00dev, 17, up_bound);
765 return;
766 }
767
768 /*
769 * Special big-R17 for middle-short distance
770 */
771 if (rssi >= -66) {
772 low_bound += 0x10;
773 if (r17 != low_bound)
774 rt73usb_bbp_write(rt2x00dev, 17, low_bound);
775 return;
776 }
777
778 /*
779 * Special mid-R17 for middle distance
780 */
781 if (rssi >= -74) {
782 if (r17 != (low_bound + 0x10))
783 rt73usb_bbp_write(rt2x00dev, 17, low_bound + 0x08);
784 return;
785 }
786
787 /*
788 * Special case: Change up_bound based on the rssi.
789 * Lower up_bound when rssi is weaker then -74 dBm.
790 */
791 up_bound -= 2 * (-74 - rssi);
792 if (low_bound > up_bound)
793 up_bound = low_bound;
794
795 if (r17 > up_bound) {
796 rt73usb_bbp_write(rt2x00dev, 17, up_bound);
797 return;
798 }
799
6bb40dd1
ID		 800dynamic_cca_tune:
801
95ea3627
ID		 802 /*
803 * r17 does not yet exceed upper limit, continue and base
804 * the r17 tuning on the false CCA count.
805 */
ebcf26da 806 if (rt2x00dev->link.qual.false_cca > 512 && r17 < up_bound) {
95ea3627
ID		 807 r17 += 4;
808 if (r17 > up_bound)
809 r17 = up_bound;
810 rt73usb_bbp_write(rt2x00dev, 17, r17);
ebcf26da 811 } else if (rt2x00dev->link.qual.false_cca < 100 && r17 > low_bound) {
95ea3627
ID		 812 r17 -= 4;
813 if (r17 < low_bound)
814 r17 = low_bound;
815 rt73usb_bbp_write(rt2x00dev, 17, r17);
816 }
817}
818
819/*
820 * Firmware name function.
821 */
822static char *rt73usb_get_firmware_name(struct rt2x00_dev *rt2x00dev)
823{
824 return FIRMWARE_RT2571;
825}
826
827/*
828 * Initialization functions.
829 */
830static int rt73usb_load_firmware(struct rt2x00_dev *rt2x00dev, void *data,
831 const size_t len)
832{
833 unsigned int i;
834 int status;
835 u32 reg;
836 char *ptr = data;
837 char *cache;
838 int buflen;
839 int timeout;
840
841 /*
842 * Wait for stable hardware.
843 */
844 for (i = 0; i < 100; i++) {
845 rt73usb_register_read(rt2x00dev, MAC_CSR0, &reg);
846 if (reg)
847 break;
848 msleep(1);
849 }
850
851 if (!reg) {
852 ERROR(rt2x00dev, "Unstable hardware.\n");
853 return -EBUSY;
854 }
855
856 /*
857 * Write firmware to device.
858 * We setup a seperate cache for this action,
859 * since we are going to write larger chunks of data
860 * then normally used cache size.
861 */
862 cache = kmalloc(CSR_CACHE_SIZE_FIRMWARE, GFP_KERNEL);
863 if (!cache) {
864 ERROR(rt2x00dev, "Failed to allocate firmware cache.\n");
865 return -ENOMEM;
866 }
867
868 for (i = 0; i < len; i += CSR_CACHE_SIZE_FIRMWARE) {
869 buflen = min_t(int, len - i, CSR_CACHE_SIZE_FIRMWARE);
870 timeout = REGISTER_TIMEOUT * (buflen / sizeof(u32));
871
872 memcpy(cache, ptr, buflen);
873
874 rt2x00usb_vendor_request(rt2x00dev, USB_MULTI_WRITE,
875 USB_VENDOR_REQUEST_OUT,
3b640f21 876 FIRMWARE_IMAGE_BASE + i, 0,
95ea3627
ID		 877 cache, buflen, timeout);
878
879 ptr += buflen;
880 }
881
882 kfree(cache);
883
884 /*
885 * Send firmware request to device to load firmware,
886 * we need to specify a long timeout time.
887 */
888 status = rt2x00usb_vendor_request_sw(rt2x00dev, USB_DEVICE_MODE,
3b640f21 889 0, USB_MODE_FIRMWARE,
95ea3627
ID		 890 REGISTER_TIMEOUT_FIRMWARE);
891 if (status < 0) {
892 ERROR(rt2x00dev, "Failed to write Firmware to device.\n");
893 return status;
894 }
895
95ea3627
ID		 896 return 0;
897}
898
899static int rt73usb_init_registers(struct rt2x00_dev *rt2x00dev)
900{
901 u32 reg;
902
903 rt73usb_register_read(rt2x00dev, TXRX_CSR0, &reg);
904 rt2x00_set_field32(&reg, TXRX_CSR0_AUTO_TX_SEQ, 1);
905 rt2x00_set_field32(&reg, TXRX_CSR0_DISABLE_RX, 0);
906 rt2x00_set_field32(&reg, TXRX_CSR0_TX_WITHOUT_WAITING, 0);
907 rt73usb_register_write(rt2x00dev, TXRX_CSR0, reg);
908
909 rt73usb_register_read(rt2x00dev, TXRX_CSR1, &reg);
910 rt2x00_set_field32(&reg, TXRX_CSR1_BBP_ID0, 47); /* CCK Signal */
911 rt2x00_set_field32(&reg, TXRX_CSR1_BBP_ID0_VALID, 1);
912 rt2x00_set_field32(&reg, TXRX_CSR1_BBP_ID1, 30); /* Rssi */
913 rt2x00_set_field32(&reg, TXRX_CSR1_BBP_ID1_VALID, 1);
914 rt2x00_set_field32(&reg, TXRX_CSR1_BBP_ID2, 42); /* OFDM Rate */
915 rt2x00_set_field32(&reg, TXRX_CSR1_BBP_ID2_VALID, 1);
916 rt2x00_set_field32(&reg, TXRX_CSR1_BBP_ID3, 30); /* Rssi */
917 rt2x00_set_field32(&reg, TXRX_CSR1_BBP_ID3_VALID, 1);
918 rt73usb_register_write(rt2x00dev, TXRX_CSR1, reg);
919
920 /*
921 * CCK TXD BBP registers
922 */
923 rt73usb_register_read(rt2x00dev, TXRX_CSR2, &reg);
924 rt2x00_set_field32(&reg, TXRX_CSR2_BBP_ID0, 13);
925 rt2x00_set_field32(&reg, TXRX_CSR2_BBP_ID0_VALID, 1);
926 rt2x00_set_field32(&reg, TXRX_CSR2_BBP_ID1, 12);
927 rt2x00_set_field32(&reg, TXRX_CSR2_BBP_ID1_VALID, 1);
928 rt2x00_set_field32(&reg, TXRX_CSR2_BBP_ID2, 11);
929 rt2x00_set_field32(&reg, TXRX_CSR2_BBP_ID2_VALID, 1);
930 rt2x00_set_field32(&reg, TXRX_CSR2_BBP_ID3, 10);
931 rt2x00_set_field32(&reg, TXRX_CSR2_BBP_ID3_VALID, 1);
932 rt73usb_register_write(rt2x00dev, TXRX_CSR2, reg);
933
934 /*
935 * OFDM TXD BBP registers
936 */
937 rt73usb_register_read(rt2x00dev, TXRX_CSR3, &reg);
938 rt2x00_set_field32(&reg, TXRX_CSR3_BBP_ID0, 7);
939 rt2x00_set_field32(&reg, TXRX_CSR3_BBP_ID0_VALID, 1);
940 rt2x00_set_field32(&reg, TXRX_CSR3_BBP_ID1, 6);
941 rt2x00_set_field32(&reg, TXRX_CSR3_BBP_ID1_VALID, 1);
942 rt2x00_set_field32(&reg, TXRX_CSR3_BBP_ID2, 5);
943 rt2x00_set_field32(&reg, TXRX_CSR3_BBP_ID2_VALID, 1);
944 rt73usb_register_write(rt2x00dev, TXRX_CSR3, reg);
945
946 rt73usb_register_read(rt2x00dev, TXRX_CSR7, &reg);
947 rt2x00_set_field32(&reg, TXRX_CSR7_ACK_CTS_6MBS, 59);
948 rt2x00_set_field32(&reg, TXRX_CSR7_ACK_CTS_9MBS, 53);
949 rt2x00_set_field32(&reg, TXRX_CSR7_ACK_CTS_12MBS, 49);
950 rt2x00_set_field32(&reg, TXRX_CSR7_ACK_CTS_18MBS, 46);
951 rt73usb_register_write(rt2x00dev, TXRX_CSR7, reg);
952
953 rt73usb_register_read(rt2x00dev, TXRX_CSR8, &reg);
954 rt2x00_set_field32(&reg, TXRX_CSR8_ACK_CTS_24MBS, 44);
955 rt2x00_set_field32(&reg, TXRX_CSR8_ACK_CTS_36MBS, 42);
956 rt2x00_set_field32(&reg, TXRX_CSR8_ACK_CTS_48MBS, 42);
957 rt2x00_set_field32(&reg, TXRX_CSR8_ACK_CTS_54MBS, 42);
958 rt73usb_register_write(rt2x00dev, TXRX_CSR8, reg);
959
960 rt73usb_register_write(rt2x00dev, TXRX_CSR15, 0x0000000f);
961
962 rt73usb_register_read(rt2x00dev, MAC_CSR6, &reg);
963 rt2x00_set_field32(&reg, MAC_CSR6_MAX_FRAME_UNIT, 0xfff);
964 rt73usb_register_write(rt2x00dev, MAC_CSR6, reg);
965
966 rt73usb_register_write(rt2x00dev, MAC_CSR10, 0x00000718);
967
968 if (rt2x00dev->ops->lib->set_device_state(rt2x00dev, STATE_AWAKE))
969 return -EBUSY;
970
971 rt73usb_register_write(rt2x00dev, MAC_CSR13, 0x00007f00);
972
a9450b70
ID		 973 rt73usb_register_read(rt2x00dev, MAC_CSR14, &reg);
974 rt2x00_set_field32(&reg, MAC_CSR14_ON_PERIOD, 70);
975 rt2x00_set_field32(&reg, MAC_CSR14_OFF_PERIOD, 30);
976 rt73usb_register_write(rt2x00dev, MAC_CSR14, reg);
977
95ea3627
ID		 978 /*
979 * Invalidate all Shared Keys (SEC_CSR0),
980 * and clear the Shared key Cipher algorithms (SEC_CSR1 & SEC_CSR5)
981 */
982 rt73usb_register_write(rt2x00dev, SEC_CSR0, 0x00000000);
983 rt73usb_register_write(rt2x00dev, SEC_CSR1, 0x00000000);
984 rt73usb_register_write(rt2x00dev, SEC_CSR5, 0x00000000);
985
986 reg = 0x000023b0;
987 if (rt2x00_rf(&rt2x00dev->chip, RF5225) ||
988 rt2x00_rf(&rt2x00dev->chip, RF2527))
989 rt2x00_set_field32(&reg, PHY_CSR1_RF_RPI, 1);
990 rt73usb_register_write(rt2x00dev, PHY_CSR1, reg);
991
992 rt73usb_register_write(rt2x00dev, PHY_CSR5, 0x00040a06);
993 rt73usb_register_write(rt2x00dev, PHY_CSR6, 0x00080606);
994 rt73usb_register_write(rt2x00dev, PHY_CSR7, 0x00000408);
995
996 rt73usb_register_read(rt2x00dev, AC_TXOP_CSR0, &reg);
997 rt2x00_set_field32(&reg, AC_TXOP_CSR0_AC0_TX_OP, 0);
998 rt2x00_set_field32(&reg, AC_TXOP_CSR0_AC1_TX_OP, 0);
999 rt73usb_register_write(rt2x00dev, AC_TXOP_CSR0, reg);
1000
1001 rt73usb_register_read(rt2x00dev, AC_TXOP_CSR1, &reg);
1002 rt2x00_set_field32(&reg, AC_TXOP_CSR1_AC2_TX_OP, 192);
1003 rt2x00_set_field32(&reg, AC_TXOP_CSR1_AC3_TX_OP, 48);
1004 rt73usb_register_write(rt2x00dev, AC_TXOP_CSR1, reg);
1005
1006 rt73usb_register_read(rt2x00dev, MAC_CSR9, &reg);
1007 rt2x00_set_field32(&reg, MAC_CSR9_CW_SELECT, 0);
1008 rt73usb_register_write(rt2x00dev, MAC_CSR9, reg);
1009
6bb40dd1
ID		 1010 /*
1011 * Clear all beacons
1012 * For the Beacon base registers we only need to clear
1013 * the first byte since that byte contains the VALID and OWNER
1014 * bits which (when set to 0) will invalidate the entire beacon.
1015 */
1016 rt73usb_register_write(rt2x00dev, HW_BEACON_BASE0, 0);
1017 rt73usb_register_write(rt2x00dev, HW_BEACON_BASE1, 0);
1018 rt73usb_register_write(rt2x00dev, HW_BEACON_BASE2, 0);
1019 rt73usb_register_write(rt2x00dev, HW_BEACON_BASE3, 0);
1020
95ea3627
ID		 1021 /*
1022 * We must clear the error counters.
1023 * These registers are cleared on read,
1024 * so we may pass a useless variable to store the value.
1025 */
1026 rt73usb_register_read(rt2x00dev, STA_CSR0, &reg);
1027 rt73usb_register_read(rt2x00dev, STA_CSR1, &reg);
1028 rt73usb_register_read(rt2x00dev, STA_CSR2, &reg);
1029
1030 /*
1031 * Reset MAC and BBP registers.
1032 */
1033 rt73usb_register_read(rt2x00dev, MAC_CSR1, &reg);
1034 rt2x00_set_field32(&reg, MAC_CSR1_SOFT_RESET, 1);
1035 rt2x00_set_field32(&reg, MAC_CSR1_BBP_RESET, 1);
1036 rt73usb_register_write(rt2x00dev, MAC_CSR1, reg);
1037
1038 rt73usb_register_read(rt2x00dev, MAC_CSR1, &reg);
1039 rt2x00_set_field32(&reg, MAC_CSR1_SOFT_RESET, 0);
1040 rt2x00_set_field32(&reg, MAC_CSR1_BBP_RESET, 0);
1041 rt73usb_register_write(rt2x00dev, MAC_CSR1, reg);
1042
1043 rt73usb_register_read(rt2x00dev, MAC_CSR1, &reg);
1044 rt2x00_set_field32(&reg, MAC_CSR1_HOST_READY, 1);
1045 rt73usb_register_write(rt2x00dev, MAC_CSR1, reg);
1046
1047 return 0;
1048}
1049
1050static int rt73usb_init_bbp(struct rt2x00_dev *rt2x00dev)
1051{
1052 unsigned int i;
1053 u16 eeprom;
1054 u8 reg_id;
1055 u8 value;
1056
1057 for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
1058 rt73usb_bbp_read(rt2x00dev, 0, &value);
1059 if ((value != 0xff) && (value != 0x00))
1060 goto continue_csr_init;
1061 NOTICE(rt2x00dev, "Waiting for BBP register.\n");
1062 udelay(REGISTER_BUSY_DELAY);
1063 }
1064
1065 ERROR(rt2x00dev, "BBP register access failed, aborting.\n");
1066 return -EACCES;
1067
1068continue_csr_init:
1069 rt73usb_bbp_write(rt2x00dev, 3, 0x80);
1070 rt73usb_bbp_write(rt2x00dev, 15, 0x30);
1071 rt73usb_bbp_write(rt2x00dev, 21, 0xc8);
1072 rt73usb_bbp_write(rt2x00dev, 22, 0x38);
1073 rt73usb_bbp_write(rt2x00dev, 23, 0x06);
1074 rt73usb_bbp_write(rt2x00dev, 24, 0xfe);
1075 rt73usb_bbp_write(rt2x00dev, 25, 0x0a);
1076 rt73usb_bbp_write(rt2x00dev, 26, 0x0d);
1077 rt73usb_bbp_write(rt2x00dev, 32, 0x0b);
1078 rt73usb_bbp_write(rt2x00dev, 34, 0x12);
1079 rt73usb_bbp_write(rt2x00dev, 37, 0x07);
1080 rt73usb_bbp_write(rt2x00dev, 39, 0xf8);
1081 rt73usb_bbp_write(rt2x00dev, 41, 0x60);
1082 rt73usb_bbp_write(rt2x00dev, 53, 0x10);
1083 rt73usb_bbp_write(rt2x00dev, 54, 0x18);
1084 rt73usb_bbp_write(rt2x00dev, 60, 0x10);
1085 rt73usb_bbp_write(rt2x00dev, 61, 0x04);
1086 rt73usb_bbp_write(rt2x00dev, 62, 0x04);
1087 rt73usb_bbp_write(rt2x00dev, 75, 0xfe);
1088 rt73usb_bbp_write(rt2x00dev, 86, 0xfe);
1089 rt73usb_bbp_write(rt2x00dev, 88, 0xfe);
1090 rt73usb_bbp_write(rt2x00dev, 90, 0x0f);
1091 rt73usb_bbp_write(rt2x00dev, 99, 0x00);
1092 rt73usb_bbp_write(rt2x00dev, 102, 0x16);
1093 rt73usb_bbp_write(rt2x00dev, 107, 0x04);
1094
95ea3627
ID		 1095 for (i = 0; i < EEPROM_BBP_SIZE; i++) {
1096 rt2x00_eeprom_read(rt2x00dev, EEPROM_BBP_START + i, &eeprom);
1097
1098 if (eeprom != 0xffff && eeprom != 0x0000) {
1099 reg_id = rt2x00_get_field16(eeprom, EEPROM_BBP_REG_ID);
1100 value = rt2x00_get_field16(eeprom, EEPROM_BBP_VALUE);
95ea3627
ID		 1101 rt73usb_bbp_write(rt2x00dev, reg_id, value);
1102 }
1103 }
95ea3627
ID		 1104
1105 return 0;
1106}
1107
1108/*
1109 * Device state switch handlers.
1110 */
1111static void rt73usb_toggle_rx(struct rt2x00_dev *rt2x00dev,
1112 enum dev_state state)
1113{
1114 u32 reg;
1115
1116 rt73usb_register_read(rt2x00dev, TXRX_CSR0, &reg);
1117 rt2x00_set_field32(&reg, TXRX_CSR0_DISABLE_RX,
1118 state == STATE_RADIO_RX_OFF);
1119 rt73usb_register_write(rt2x00dev, TXRX_CSR0, reg);
1120}
1121
1122static int rt73usb_enable_radio(struct rt2x00_dev *rt2x00dev)
1123{
1124 /*
1125 * Initialize all registers.
1126 */
1127 if (rt73usb_init_registers(rt2x00dev) ||
1128 rt73usb_init_bbp(rt2x00dev)) {
1129 ERROR(rt2x00dev, "Register initialization failed.\n");
1130 return -EIO;
1131 }
1132
95ea3627
ID		 1133 return 0;
1134}
1135
1136static void rt73usb_disable_radio(struct rt2x00_dev *rt2x00dev)
1137{
95ea3627
ID		 1138 rt73usb_register_write(rt2x00dev, MAC_CSR10, 0x00001818);
1139
1140 /*
1141 * Disable synchronisation.
1142 */
1143 rt73usb_register_write(rt2x00dev, TXRX_CSR9, 0);
1144
1145 rt2x00usb_disable_radio(rt2x00dev);
1146}
1147
1148static int rt73usb_set_state(struct rt2x00_dev *rt2x00dev, enum dev_state state)
1149{
1150 u32 reg;
1151 unsigned int i;
1152 char put_to_sleep;
1153 char current_state;
1154
1155 put_to_sleep = (state != STATE_AWAKE);
1156
1157 rt73usb_register_read(rt2x00dev, MAC_CSR12, &reg);
1158 rt2x00_set_field32(&reg, MAC_CSR12_FORCE_WAKEUP, !put_to_sleep);
1159 rt2x00_set_field32(&reg, MAC_CSR12_PUT_TO_SLEEP, put_to_sleep);
1160 rt73usb_register_write(rt2x00dev, MAC_CSR12, reg);
1161
1162 /*
1163 * Device is not guaranteed to be in the requested state yet.
1164 * We must wait until the register indicates that the
1165 * device has entered the correct state.
1166 */
1167 for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
1168 rt73usb_register_read(rt2x00dev, MAC_CSR12, &reg);
1169 current_state =
1170 rt2x00_get_field32(reg, MAC_CSR12_BBP_CURRENT_STATE);
1171 if (current_state == !put_to_sleep)
1172 return 0;
1173 msleep(10);
1174 }
1175
1176 NOTICE(rt2x00dev, "Device failed to enter state %d, "
1177 "current device state %d.\n", !put_to_sleep, current_state);
1178
1179 return -EBUSY;
1180}
1181
1182static int rt73usb_set_device_state(struct rt2x00_dev *rt2x00dev,
1183 enum dev_state state)
1184{
1185 int retval = 0;
1186
1187 switch (state) {
1188 case STATE_RADIO_ON:
1189 retval = rt73usb_enable_radio(rt2x00dev);
1190 break;
1191 case STATE_RADIO_OFF:
1192 rt73usb_disable_radio(rt2x00dev);
1193 break;
1194 case STATE_RADIO_RX_ON:
61667d8d
ID		 1195 case STATE_RADIO_RX_ON_LINK:
1196 rt73usb_toggle_rx(rt2x00dev, STATE_RADIO_RX_ON);
1197 break;
95ea3627 1198 case STATE_RADIO_RX_OFF:
61667d8d
ID		 1199 case STATE_RADIO_RX_OFF_LINK:
1200 rt73usb_toggle_rx(rt2x00dev, STATE_RADIO_RX_OFF);
95ea3627
ID		 1201 break;
1202 case STATE_DEEP_SLEEP:
1203 case STATE_SLEEP:
1204 case STATE_STANDBY:
1205 case STATE_AWAKE:
1206 retval = rt73usb_set_state(rt2x00dev, state);
1207 break;
1208 default:
1209 retval = -ENOTSUPP;
1210 break;
1211 }
1212
1213 return retval;
1214}
1215
1216/*
1217 * TX descriptor initialization
1218 */
1219static void rt73usb_write_tx_desc(struct rt2x00_dev *rt2x00dev,
dd3193e1 1220 struct sk_buff *skb,
181d6902 1221 struct txentry_desc *txdesc,
dd3193e1 1222 struct ieee80211_tx_control *control)
95ea3627 1223{
181d6902 1224 struct skb_frame_desc *skbdesc = get_skb_frame_desc(skb);
dd3193e1 1225 __le32 *txd = skbdesc->desc;
95ea3627
ID		 1226 u32 word;
1227
1228 /*
1229 * Start writing the descriptor words.
1230 */
1231 rt2x00_desc_read(txd, 1, &word);
181d6902
ID		 1232 rt2x00_set_field32(&word, TXD_W1_HOST_Q_ID, txdesc->queue);
1233 rt2x00_set_field32(&word, TXD_W1_AIFSN, txdesc->aifs);
1234 rt2x00_set_field32(&word, TXD_W1_CWMIN, txdesc->cw_min);
1235 rt2x00_set_field32(&word, TXD_W1_CWMAX, txdesc->cw_max);
95ea3627
ID		 1236 rt2x00_set_field32(&word, TXD_W1_IV_OFFSET, IEEE80211_HEADER);
1237 rt2x00_set_field32(&word, TXD_W1_HW_SEQUENCE, 1);
1238 rt2x00_desc_write(txd, 1, word);
1239
1240 rt2x00_desc_read(txd, 2, &word);
181d6902
ID		 1241 rt2x00_set_field32(&word, TXD_W2_PLCP_SIGNAL, txdesc->signal);
1242 rt2x00_set_field32(&word, TXD_W2_PLCP_SERVICE, txdesc->service);
1243 rt2x00_set_field32(&word, TXD_W2_PLCP_LENGTH_LOW, txdesc->length_low);
1244 rt2x00_set_field32(&word, TXD_W2_PLCP_LENGTH_HIGH, txdesc->length_high);
95ea3627
ID		 1245 rt2x00_desc_write(txd, 2, word);
1246
1247 rt2x00_desc_read(txd, 5, &word);
1248 rt2x00_set_field32(&word, TXD_W5_TX_POWER,
ac1aa7e4 1249 TXPOWER_TO_DEV(rt2x00dev->tx_power));
95ea3627
ID		 1250 rt2x00_set_field32(&word, TXD_W5_WAITING_DMA_DONE_INT, 1);
1251 rt2x00_desc_write(txd, 5, word);
1252
1253 rt2x00_desc_read(txd, 0, &word);
1254 rt2x00_set_field32(&word, TXD_W0_BURST,
181d6902 1255 test_bit(ENTRY_TXD_BURST, &txdesc->flags));
95ea3627
ID		 1256 rt2x00_set_field32(&word, TXD_W0_VALID, 1);
1257 rt2x00_set_field32(&word, TXD_W0_MORE_FRAG,
181d6902 1258 test_bit(ENTRY_TXD_MORE_FRAG, &txdesc->flags));
95ea3627 1259 rt2x00_set_field32(&word, TXD_W0_ACK,
181d6902 1260 test_bit(ENTRY_TXD_ACK, &txdesc->flags));
95ea3627 1261 rt2x00_set_field32(&word, TXD_W0_TIMESTAMP,
181d6902 1262 test_bit(ENTRY_TXD_REQ_TIMESTAMP, &txdesc->flags));
95ea3627 1263 rt2x00_set_field32(&word, TXD_W0_OFDM,
181d6902
ID		 1264 test_bit(ENTRY_TXD_OFDM_RATE, &txdesc->flags));
1265 rt2x00_set_field32(&word, TXD_W0_IFS, txdesc->ifs);
95ea3627
ID		 1266 rt2x00_set_field32(&word, TXD_W0_RETRY_MODE,
1267 !!(control->flags &
1268 IEEE80211_TXCTL_LONG_RETRY_LIMIT));
1269 rt2x00_set_field32(&word, TXD_W0_TKIP_MIC, 0);
dd3193e1 1270 rt2x00_set_field32(&word, TXD_W0_DATABYTE_COUNT, skbdesc->data_len);
95ea3627 1271 rt2x00_set_field32(&word, TXD_W0_BURST2,
181d6902 1272 test_bit(ENTRY_TXD_BURST, &txdesc->flags));
95ea3627
ID		 1273 rt2x00_set_field32(&word, TXD_W0_CIPHER_ALG, CIPHER_NONE);
1274 rt2x00_desc_write(txd, 0, word);
1275}
1276
dd9fa2d2 1277static int rt73usb_get_tx_data_len(struct rt2x00_dev *rt2x00dev,
b242e891 1278 struct sk_buff *skb)
dd9fa2d2
ID		 1279{
1280 int length;
1281
1282 /*
1283 * The length _must_ be a multiple of 4,
1284 * but it must _not_ be a multiple of the USB packet size.
1285 */
1286 length = roundup(skb->len, 4);
b242e891 1287 length += (4 * !(length % rt2x00dev->usb_maxpacket));
dd9fa2d2
ID		 1288
1289 return length;
1290}
1291
95ea3627
ID		 1292/*
1293 * TX data initialization
1294 */
1295static void rt73usb_kick_tx_queue(struct rt2x00_dev *rt2x00dev,
5957da4c 1296 const unsigned int queue)
95ea3627
ID		 1297{
1298 u32 reg;
1299
5957da4c 1300 if (queue != RT2X00_BCN_QUEUE_BEACON)
95ea3627
ID		 1301 return;
1302
1303 /*
1304 * For Wi-Fi faily generated beacons between participating stations.
1305 * Set TBTT phase adaptive adjustment step to 8us (default 16us)
1306 */
1307 rt73usb_register_write(rt2x00dev, TXRX_CSR10, 0x00001008);
1308
1309 rt73usb_register_read(rt2x00dev, TXRX_CSR9, &reg);
1310 if (!rt2x00_get_field32(reg, TXRX_CSR9_BEACON_GEN)) {
8af244cc
ID		 1311 rt2x00_set_field32(&reg, TXRX_CSR9_TSF_TICKING, 1);
1312 rt2x00_set_field32(&reg, TXRX_CSR9_TBTT_ENABLE, 1);
95ea3627
ID		 1313 rt2x00_set_field32(&reg, TXRX_CSR9_BEACON_GEN, 1);
1314 rt73usb_register_write(rt2x00dev, TXRX_CSR9, reg);
1315 }
1316}
1317
1318/*
1319 * RX control handlers
1320 */
1321static int rt73usb_agc_to_rssi(struct rt2x00_dev *rt2x00dev, int rxd_w1)
1322{
1323 u16 eeprom;
1324 u8 offset;
1325 u8 lna;
1326
1327 lna = rt2x00_get_field32(rxd_w1, RXD_W1_RSSI_LNA);
1328 switch (lna) {
1329 case 3:
1330 offset = 90;
1331 break;
1332 case 2:
1333 offset = 74;
1334 break;
1335 case 1:
1336 offset = 64;
1337 break;
1338 default:
1339 return 0;
1340 }
1341
8318d78a 1342 if (rt2x00dev->rx_status.band == IEEE80211_BAND_5GHZ) {
95ea3627
ID		 1343 if (test_bit(CONFIG_EXTERNAL_LNA_A, &rt2x00dev->flags)) {
1344 if (lna == 3 || lna == 2)
1345 offset += 10;
1346 } else {
1347 if (lna == 3)
1348 offset += 6;
1349 else if (lna == 2)
1350 offset += 8;
1351 }
1352
1353 rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_OFFSET_A, &eeprom);
1354 offset -= rt2x00_get_field16(eeprom, EEPROM_RSSI_OFFSET_A_1);
1355 } else {
1356 if (test_bit(CONFIG_EXTERNAL_LNA_BG, &rt2x00dev->flags))
1357 offset += 14;
1358
1359 rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_OFFSET_BG, &eeprom);
1360 offset -= rt2x00_get_field16(eeprom, EEPROM_RSSI_OFFSET_BG_1);
1361 }
1362
1363 return rt2x00_get_field32(rxd_w1, RXD_W1_RSSI_AGC) * 2 - offset;
1364}
1365
181d6902
ID		 1366static void rt73usb_fill_rxdone(struct queue_entry *entry,
1367 struct rxdone_entry_desc *rxdesc)
95ea3627 1368{
181d6902 1369 struct skb_frame_desc *skbdesc = get_skb_frame_desc(entry->skb);
4bd7c452 1370 __le32 *rxd = (__le32 *)entry->skb->data;
f855c10b 1371 unsigned int offset = entry->queue->desc_size + 2;
95ea3627
ID		 1372 u32 word0;
1373 u32 word1;
1374
f855c10b
ID		 1375 /*
1376 * Copy descriptor to the available headroom inside the skbuffer.
f855c10b
ID		 1377 */
1378 skb_push(entry->skb, offset);
1379 memcpy(entry->skb->data, rxd, entry->queue->desc_size);
1380 rxd = (__le32 *)entry->skb->data;
f855c10b
ID		 1381
1382 /*
1383 * The descriptor is now aligned to 4 bytes and thus it is
1384 * now safe to read it on all architectures.
1385 */
95ea3627
ID		 1386 rt2x00_desc_read(rxd, 0, &word0);
1387 rt2x00_desc_read(rxd, 1, &word1);
1388
181d6902 1389 rxdesc->flags = 0;
4150c572 1390 if (rt2x00_get_field32(word0, RXD_W0_CRC_ERROR))
181d6902 1391 rxdesc->flags |= RX_FLAG_FAILED_FCS_CRC;
95ea3627
ID		 1392
1393 /*
1394 * Obtain the status about this packet.
1395 */
181d6902
ID		 1396 rxdesc->signal = rt2x00_get_field32(word1, RXD_W1_SIGNAL);
1397 rxdesc->rssi = rt73usb_agc_to_rssi(entry->queue->rt2x00dev, word1);
1398 rxdesc->ofdm = rt2x00_get_field32(word0, RXD_W0_OFDM);
1399 rxdesc->size = rt2x00_get_field32(word0, RXD_W0_DATABYTE_COUNT);
1400 rxdesc->my_bss = !!rt2x00_get_field32(word0, RXD_W0_MY_BSS);
1401
2ae23854
MN		 1402 /*
1403 * Adjust the skb memory window to the frame boundaries.
1404 */
1405 skb_pull(entry->skb, offset + entry->queue->desc_size);
1406 skb_trim(entry->skb, rxdesc->size);
1407
7d1de806
ID		 1408 /*
1409 * Set descriptor and data pointer.
1410 */
f855c10b 1411 skbdesc->data = entry->skb->data;
647d0ca9 1412 skbdesc->data_len = rxdesc->size;
2ae23854 1413 skbdesc->desc = rxd;
181d6902 1414 skbdesc->desc_len = entry->queue->desc_size;
95ea3627
ID		 1415}
1416
1417/*
1418 * Device probe functions.
1419 */
1420static int rt73usb_validate_eeprom(struct rt2x00_dev *rt2x00dev)
1421{
1422 u16 word;
1423 u8 *mac;
1424 s8 value;
1425
1426 rt2x00usb_eeprom_read(rt2x00dev, rt2x00dev->eeprom, EEPROM_SIZE);
1427
1428 /*
1429 * Start validation of the data that has been read.
1430 */
1431 mac = rt2x00_eeprom_addr(rt2x00dev, EEPROM_MAC_ADDR_0);
1432 if (!is_valid_ether_addr(mac)) {
0795af57
JP		 1433 DECLARE_MAC_BUF(macbuf);
1434
95ea3627 1435 random_ether_addr(mac);
0795af57 1436 EEPROM(rt2x00dev, "MAC: %s\n", print_mac(macbuf, mac));
95ea3627
ID		 1437 }
1438
1439 rt2x00_eeprom_read(rt2x00dev, EEPROM_ANTENNA, &word);
1440 if (word == 0xffff) {
1441 rt2x00_set_field16(&word, EEPROM_ANTENNA_NUM, 2);
362f3b6b
ID		 1442 rt2x00_set_field16(&word, EEPROM_ANTENNA_TX_DEFAULT,
1443 ANTENNA_B);
1444 rt2x00_set_field16(&word, EEPROM_ANTENNA_RX_DEFAULT,
1445 ANTENNA_B);
95ea3627
ID		 1446 rt2x00_set_field16(&word, EEPROM_ANTENNA_FRAME_TYPE, 0);
1447 rt2x00_set_field16(&word, EEPROM_ANTENNA_DYN_TXAGC, 0);
1448 rt2x00_set_field16(&word, EEPROM_ANTENNA_HARDWARE_RADIO, 0);
1449 rt2x00_set_field16(&word, EEPROM_ANTENNA_RF_TYPE, RF5226);
1450 rt2x00_eeprom_write(rt2x00dev, EEPROM_ANTENNA, word);
1451 EEPROM(rt2x00dev, "Antenna: 0x%04x\n", word);
1452 }
1453
1454 rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC, &word);
1455 if (word == 0xffff) {
1456 rt2x00_set_field16(&word, EEPROM_NIC_EXTERNAL_LNA, 0);
1457 rt2x00_eeprom_write(rt2x00dev, EEPROM_NIC, word);
1458 EEPROM(rt2x00dev, "NIC: 0x%04x\n", word);
1459 }
1460
1461 rt2x00_eeprom_read(rt2x00dev, EEPROM_LED, &word);
1462 if (word == 0xffff) {
1463 rt2x00_set_field16(&word, EEPROM_LED_POLARITY_RDY_G, 0);
1464 rt2x00_set_field16(&word, EEPROM_LED_POLARITY_RDY_A, 0);
1465 rt2x00_set_field16(&word, EEPROM_LED_POLARITY_ACT, 0);
1466 rt2x00_set_field16(&word, EEPROM_LED_POLARITY_GPIO_0, 0);
1467 rt2x00_set_field16(&word, EEPROM_LED_POLARITY_GPIO_1, 0);
1468 rt2x00_set_field16(&word, EEPROM_LED_POLARITY_GPIO_2, 0);
1469 rt2x00_set_field16(&word, EEPROM_LED_POLARITY_GPIO_3, 0);
1470 rt2x00_set_field16(&word, EEPROM_LED_POLARITY_GPIO_4, 0);
1471 rt2x00_set_field16(&word, EEPROM_LED_LED_MODE,
1472 LED_MODE_DEFAULT);
1473 rt2x00_eeprom_write(rt2x00dev, EEPROM_LED, word);
1474 EEPROM(rt2x00dev, "Led: 0x%04x\n", word);
1475 }
1476
1477 rt2x00_eeprom_read(rt2x00dev, EEPROM_FREQ, &word);
1478 if (word == 0xffff) {
1479 rt2x00_set_field16(&word, EEPROM_FREQ_OFFSET, 0);
1480 rt2x00_set_field16(&word, EEPROM_FREQ_SEQ, 0);
1481 rt2x00_eeprom_write(rt2x00dev, EEPROM_FREQ, word);
1482 EEPROM(rt2x00dev, "Freq: 0x%04x\n", word);
1483 }
1484
1485 rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_OFFSET_BG, &word);
1486 if (word == 0xffff) {
1487 rt2x00_set_field16(&word, EEPROM_RSSI_OFFSET_BG_1, 0);
1488 rt2x00_set_field16(&word, EEPROM_RSSI_OFFSET_BG_2, 0);
1489 rt2x00_eeprom_write(rt2x00dev, EEPROM_RSSI_OFFSET_BG, word);
1490 EEPROM(rt2x00dev, "RSSI OFFSET BG: 0x%04x\n", word);
1491 } else {
1492 value = rt2x00_get_field16(word, EEPROM_RSSI_OFFSET_BG_1);
1493 if (value < -10 || value > 10)
1494 rt2x00_set_field16(&word, EEPROM_RSSI_OFFSET_BG_1, 0);
1495 value = rt2x00_get_field16(word, EEPROM_RSSI_OFFSET_BG_2);
1496 if (value < -10 || value > 10)
1497 rt2x00_set_field16(&word, EEPROM_RSSI_OFFSET_BG_2, 0);
1498 rt2x00_eeprom_write(rt2x00dev, EEPROM_RSSI_OFFSET_BG, word);
1499 }
1500
1501 rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_OFFSET_A, &word);
1502 if (word == 0xffff) {
1503 rt2x00_set_field16(&word, EEPROM_RSSI_OFFSET_A_1, 0);
1504 rt2x00_set_field16(&word, EEPROM_RSSI_OFFSET_A_2, 0);
1505 rt2x00_eeprom_write(rt2x00dev, EEPROM_RSSI_OFFSET_A, word);
417f412f 1506 EEPROM(rt2x00dev, "RSSI OFFSET A: 0x%04x\n", word);
95ea3627
ID		 1507 } else {
1508 value = rt2x00_get_field16(word, EEPROM_RSSI_OFFSET_A_1);
1509 if (value < -10 || value > 10)
1510 rt2x00_set_field16(&word, EEPROM_RSSI_OFFSET_A_1, 0);
1511 value = rt2x00_get_field16(word, EEPROM_RSSI_OFFSET_A_2);
1512 if (value < -10 || value > 10)
1513 rt2x00_set_field16(&word, EEPROM_RSSI_OFFSET_A_2, 0);
1514 rt2x00_eeprom_write(rt2x00dev, EEPROM_RSSI_OFFSET_A, word);
1515 }
1516
1517 return 0;
1518}
1519
1520static int rt73usb_init_eeprom(struct rt2x00_dev *rt2x00dev)
1521{
1522 u32 reg;
1523 u16 value;
1524 u16 eeprom;
1525
1526 /*
1527 * Read EEPROM word for configuration.
1528 */
1529 rt2x00_eeprom_read(rt2x00dev, EEPROM_ANTENNA, &eeprom);
1530
1531 /*
1532 * Identify RF chipset.
1533 */
1534 value = rt2x00_get_field16(eeprom, EEPROM_ANTENNA_RF_TYPE);
1535 rt73usb_register_read(rt2x00dev, MAC_CSR0, &reg);
1536 rt2x00_set_chip(rt2x00dev, RT2571, value, reg);
1537
755a957d 1538 if (!rt2x00_check_rev(&rt2x00dev->chip, 0x25730)) {
95ea3627
ID		 1539 ERROR(rt2x00dev, "Invalid RT chipset detected.\n");
1540 return -ENODEV;
1541 }
1542
1543 if (!rt2x00_rf(&rt2x00dev->chip, RF5226) &&
1544 !rt2x00_rf(&rt2x00dev->chip, RF2528) &&
1545 !rt2x00_rf(&rt2x00dev->chip, RF5225) &&
1546 !rt2x00_rf(&rt2x00dev->chip, RF2527)) {
1547 ERROR(rt2x00dev, "Invalid RF chipset detected.\n");
1548 return -ENODEV;
1549 }
1550
1551 /*
1552 * Identify default antenna configuration.
1553 */
addc81bd 1554 rt2x00dev->default_ant.tx =
95ea3627 1555 rt2x00_get_field16(eeprom, EEPROM_ANTENNA_TX_DEFAULT);
addc81bd 1556 rt2x00dev->default_ant.rx =
95ea3627
ID		 1557 rt2x00_get_field16(eeprom, EEPROM_ANTENNA_RX_DEFAULT);
1558
1559 /*
1560 * Read the Frame type.
1561 */
1562 if (rt2x00_get_field16(eeprom, EEPROM_ANTENNA_FRAME_TYPE))
1563 __set_bit(CONFIG_FRAME_TYPE, &rt2x00dev->flags);
1564
1565 /*
1566 * Read frequency offset.
1567 */
1568 rt2x00_eeprom_read(rt2x00dev, EEPROM_FREQ, &eeprom);
1569 rt2x00dev->freq_offset = rt2x00_get_field16(eeprom, EEPROM_FREQ_OFFSET);
1570
1571 /*
1572 * Read external LNA informations.
1573 */
1574 rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC, &eeprom);
1575
1576 if (rt2x00_get_field16(eeprom, EEPROM_NIC_EXTERNAL_LNA)) {
1577 __set_bit(CONFIG_EXTERNAL_LNA_A, &rt2x00dev->flags);
1578 __set_bit(CONFIG_EXTERNAL_LNA_BG, &rt2x00dev->flags);
1579 }
1580
1581 /*
1582 * Store led settings, for correct led behaviour.
1583 */
a9450b70 1584#ifdef CONFIG_RT73USB_LEDS
95ea3627
ID		 1585 rt2x00_eeprom_read(rt2x00dev, EEPROM_LED, &eeprom);
1586
a9450b70
ID		 1587 switch (value) {
1588 case LED_MODE_TXRX_ACTIVITY:
1589 case LED_MODE_ASUS:
1590 case LED_MODE_ALPHA:
1591 case LED_MODE_DEFAULT:
1592 rt2x00dev->led_flags =
1593 LED_SUPPORT_RADIO | LED_SUPPORT_ASSOC;
1594 break;
1595 case LED_MODE_SIGNAL_STRENGTH:
1596 rt2x00dev->led_flags =
1597 LED_SUPPORT_RADIO | LED_SUPPORT_ASSOC |
1598 LED_SUPPORT_QUALITY;
1599 break;
1600 }
1601
1602 rt2x00_set_field16(&rt2x00dev->led_mcu_reg, MCU_LEDCS_LED_MODE, value);
1603 rt2x00_set_field16(&rt2x00dev->led_mcu_reg, MCU_LEDCS_POLARITY_GPIO_0,
95ea3627
ID		 1604 rt2x00_get_field16(eeprom,
1605 EEPROM_LED_POLARITY_GPIO_0));
a9450b70 1606 rt2x00_set_field16(&rt2x00dev->led_mcu_reg, MCU_LEDCS_POLARITY_GPIO_1,
95ea3627
ID		 1607 rt2x00_get_field16(eeprom,
1608 EEPROM_LED_POLARITY_GPIO_1));
a9450b70 1609 rt2x00_set_field16(&rt2x00dev->led_mcu_reg, MCU_LEDCS_POLARITY_GPIO_2,
95ea3627
ID		 1610 rt2x00_get_field16(eeprom,
1611 EEPROM_LED_POLARITY_GPIO_2));
a9450b70 1612 rt2x00_set_field16(&rt2x00dev->led_mcu_reg, MCU_LEDCS_POLARITY_GPIO_3,
95ea3627
ID		 1613 rt2x00_get_field16(eeprom,
1614 EEPROM_LED_POLARITY_GPIO_3));
a9450b70 1615 rt2x00_set_field16(&rt2x00dev->led_mcu_reg, MCU_LEDCS_POLARITY_GPIO_4,
95ea3627
ID		 1616 rt2x00_get_field16(eeprom,
1617 EEPROM_LED_POLARITY_GPIO_4));
a9450b70 1618 rt2x00_set_field16(&rt2x00dev->led_mcu_reg, MCU_LEDCS_POLARITY_ACT,
95ea3627 1619 rt2x00_get_field16(eeprom, EEPROM_LED_POLARITY_ACT));
a9450b70 1620 rt2x00_set_field16(&rt2x00dev->led_mcu_reg, MCU_LEDCS_POLARITY_READY_BG,
95ea3627
ID		 1621 rt2x00_get_field16(eeprom,
1622 EEPROM_LED_POLARITY_RDY_G));
a9450b70 1623 rt2x00_set_field16(&rt2x00dev->led_mcu_reg, MCU_LEDCS_POLARITY_READY_A,
95ea3627
ID		 1624 rt2x00_get_field16(eeprom,
1625 EEPROM_LED_POLARITY_RDY_A));
a9450b70 1626#endif /* CONFIG_RT73USB_LEDS */
95ea3627
ID		 1627
1628 return 0;
1629}
1630
1631/*
1632 * RF value list for RF2528
1633 * Supports: 2.4 GHz
1634 */
1635static const struct rf_channel rf_vals_bg_2528[] = {
1636 { 1, 0x00002c0c, 0x00000786, 0x00068255, 0x000fea0b },
1637 { 2, 0x00002c0c, 0x00000786, 0x00068255, 0x000fea1f },
1638 { 3, 0x00002c0c, 0x0000078a, 0x00068255, 0x000fea0b },
1639 { 4, 0x00002c0c, 0x0000078a, 0x00068255, 0x000fea1f },
1640 { 5, 0x00002c0c, 0x0000078e, 0x00068255, 0x000fea0b },
1641 { 6, 0x00002c0c, 0x0000078e, 0x00068255, 0x000fea1f },
1642 { 7, 0x00002c0c, 0x00000792, 0x00068255, 0x000fea0b },
1643 { 8, 0x00002c0c, 0x00000792, 0x00068255, 0x000fea1f },
1644 { 9, 0x00002c0c, 0x00000796, 0x00068255, 0x000fea0b },
1645 { 10, 0x00002c0c, 0x00000796, 0x00068255, 0x000fea1f },
1646 { 11, 0x00002c0c, 0x0000079a, 0x00068255, 0x000fea0b },
1647 { 12, 0x00002c0c, 0x0000079a, 0x00068255, 0x000fea1f },
1648 { 13, 0x00002c0c, 0x0000079e, 0x00068255, 0x000fea0b },
1649 { 14, 0x00002c0c, 0x000007a2, 0x00068255, 0x000fea13 },
1650};
1651
1652/*
1653 * RF value list for RF5226
1654 * Supports: 2.4 GHz & 5.2 GHz
1655 */
1656static const struct rf_channel rf_vals_5226[] = {
1657 { 1, 0x00002c0c, 0x00000786, 0x00068255, 0x000fea0b },
1658 { 2, 0x00002c0c, 0x00000786, 0x00068255, 0x000fea1f },
1659 { 3, 0x00002c0c, 0x0000078a, 0x00068255, 0x000fea0b },
1660 { 4, 0x00002c0c, 0x0000078a, 0x00068255, 0x000fea1f },
1661 { 5, 0x00002c0c, 0x0000078e, 0x00068255, 0x000fea0b },
1662 { 6, 0x00002c0c, 0x0000078e, 0x00068255, 0x000fea1f },
1663 { 7, 0x00002c0c, 0x00000792, 0x00068255, 0x000fea0b },
1664 { 8, 0x00002c0c, 0x00000792, 0x00068255, 0x000fea1f },
1665 { 9, 0x00002c0c, 0x00000796, 0x00068255, 0x000fea0b },
1666 { 10, 0x00002c0c, 0x00000796, 0x00068255, 0x000fea1f },
1667 { 11, 0x00002c0c, 0x0000079a, 0x00068255, 0x000fea0b },
1668 { 12, 0x00002c0c, 0x0000079a, 0x00068255, 0x000fea1f },
1669 { 13, 0x00002c0c, 0x0000079e, 0x00068255, 0x000fea0b },
1670 { 14, 0x00002c0c, 0x000007a2, 0x00068255, 0x000fea13 },
1671
1672 /* 802.11 UNI / HyperLan 2 */
1673 { 36, 0x00002c0c, 0x0000099a, 0x00098255, 0x000fea23 },
1674 { 40, 0x00002c0c, 0x000009a2, 0x00098255, 0x000fea03 },
1675 { 44, 0x00002c0c, 0x000009a6, 0x00098255, 0x000fea0b },
1676 { 48, 0x00002c0c, 0x000009aa, 0x00098255, 0x000fea13 },
1677 { 52, 0x00002c0c, 0x000009ae, 0x00098255, 0x000fea1b },
1678 { 56, 0x00002c0c, 0x000009b2, 0x00098255, 0x000fea23 },
1679 { 60, 0x00002c0c, 0x000009ba, 0x00098255, 0x000fea03 },
1680 { 64, 0x00002c0c, 0x000009be, 0x00098255, 0x000fea0b },
1681
1682 /* 802.11 HyperLan 2 */
1683 { 100, 0x00002c0c, 0x00000a2a, 0x000b8255, 0x000fea03 },
1684 { 104, 0x00002c0c, 0x00000a2e, 0x000b8255, 0x000fea0b },
1685 { 108, 0x00002c0c, 0x00000a32, 0x000b8255, 0x000fea13 },
1686 { 112, 0x00002c0c, 0x00000a36, 0x000b8255, 0x000fea1b },
1687 { 116, 0x00002c0c, 0x00000a3a, 0x000b8255, 0x000fea23 },
1688 { 120, 0x00002c0c, 0x00000a82, 0x000b8255, 0x000fea03 },
1689 { 124, 0x00002c0c, 0x00000a86, 0x000b8255, 0x000fea0b },
1690 { 128, 0x00002c0c, 0x00000a8a, 0x000b8255, 0x000fea13 },
1691 { 132, 0x00002c0c, 0x00000a8e, 0x000b8255, 0x000fea1b },
1692 { 136, 0x00002c0c, 0x00000a92, 0x000b8255, 0x000fea23 },
1693
1694 /* 802.11 UNII */
1695 { 140, 0x00002c0c, 0x00000a9a, 0x000b8255, 0x000fea03 },
1696 { 149, 0x00002c0c, 0x00000aa2, 0x000b8255, 0x000fea1f },
1697 { 153, 0x00002c0c, 0x00000aa6, 0x000b8255, 0x000fea27 },
1698 { 157, 0x00002c0c, 0x00000aae, 0x000b8255, 0x000fea07 },
1699 { 161, 0x00002c0c, 0x00000ab2, 0x000b8255, 0x000fea0f },
1700 { 165, 0x00002c0c, 0x00000ab6, 0x000b8255, 0x000fea17 },
1701
1702 /* MMAC(Japan)J52 ch 34,38,42,46 */
1703 { 34, 0x00002c0c, 0x0008099a, 0x000da255, 0x000d3a0b },
1704 { 38, 0x00002c0c, 0x0008099e, 0x000da255, 0x000d3a13 },
1705 { 42, 0x00002c0c, 0x000809a2, 0x000da255, 0x000d3a1b },
1706 { 46, 0x00002c0c, 0x000809a6, 0x000da255, 0x000d3a23 },
1707};
1708
1709/*
1710 * RF value list for RF5225 & RF2527
1711 * Supports: 2.4 GHz & 5.2 GHz
1712 */
1713static const struct rf_channel rf_vals_5225_2527[] = {
1714 { 1, 0x00002ccc, 0x00004786, 0x00068455, 0x000ffa0b },
1715 { 2, 0x00002ccc, 0x00004786, 0x00068455, 0x000ffa1f },
1716 { 3, 0x00002ccc, 0x0000478a, 0x00068455, 0x000ffa0b },
1717 { 4, 0x00002ccc, 0x0000478a, 0x00068455, 0x000ffa1f },
1718 { 5, 0x00002ccc, 0x0000478e, 0x00068455, 0x000ffa0b },
1719 { 6, 0x00002ccc, 0x0000478e, 0x00068455, 0x000ffa1f },
1720 { 7, 0x00002ccc, 0x00004792, 0x00068455, 0x000ffa0b },
1721 { 8, 0x00002ccc, 0x00004792, 0x00068455, 0x000ffa1f },
1722 { 9, 0x00002ccc, 0x00004796, 0x00068455, 0x000ffa0b },
1723 { 10, 0x00002ccc, 0x00004796, 0x00068455, 0x000ffa1f },
1724 { 11, 0x00002ccc, 0x0000479a, 0x00068455, 0x000ffa0b },
1725 { 12, 0x00002ccc, 0x0000479a, 0x00068455, 0x000ffa1f },
1726 { 13, 0x00002ccc, 0x0000479e, 0x00068455, 0x000ffa0b },
1727 { 14, 0x00002ccc, 0x000047a2, 0x00068455, 0x000ffa13 },
1728
1729 /* 802.11 UNI / HyperLan 2 */
1730 { 36, 0x00002ccc, 0x0000499a, 0x0009be55, 0x000ffa23 },
1731 { 40, 0x00002ccc, 0x000049a2, 0x0009be55, 0x000ffa03 },
1732 { 44, 0x00002ccc, 0x000049a6, 0x0009be55, 0x000ffa0b },
1733 { 48, 0x00002ccc, 0x000049aa, 0x0009be55, 0x000ffa13 },
1734 { 52, 0x00002ccc, 0x000049ae, 0x0009ae55, 0x000ffa1b },
1735 { 56, 0x00002ccc, 0x000049b2, 0x0009ae55, 0x000ffa23 },
1736 { 60, 0x00002ccc, 0x000049ba, 0x0009ae55, 0x000ffa03 },
1737 { 64, 0x00002ccc, 0x000049be, 0x0009ae55, 0x000ffa0b },
1738
1739 /* 802.11 HyperLan 2 */
1740 { 100, 0x00002ccc, 0x00004a2a, 0x000bae55, 0x000ffa03 },
1741 { 104, 0x00002ccc, 0x00004a2e, 0x000bae55, 0x000ffa0b },
1742 { 108, 0x00002ccc, 0x00004a32, 0x000bae55, 0x000ffa13 },
1743 { 112, 0x00002ccc, 0x00004a36, 0x000bae55, 0x000ffa1b },
1744 { 116, 0x00002ccc, 0x00004a3a, 0x000bbe55, 0x000ffa23 },
1745 { 120, 0x00002ccc, 0x00004a82, 0x000bbe55, 0x000ffa03 },
1746 { 124, 0x00002ccc, 0x00004a86, 0x000bbe55, 0x000ffa0b },
1747 { 128, 0x00002ccc, 0x00004a8a, 0x000bbe55, 0x000ffa13 },
1748 { 132, 0x00002ccc, 0x00004a8e, 0x000bbe55, 0x000ffa1b },
1749 { 136, 0x00002ccc, 0x00004a92, 0x000bbe55, 0x000ffa23 },
1750
1751 /* 802.11 UNII */
1752 { 140, 0x00002ccc, 0x00004a9a, 0x000bbe55, 0x000ffa03 },
1753 { 149, 0x00002ccc, 0x00004aa2, 0x000bbe55, 0x000ffa1f },
1754 { 153, 0x00002ccc, 0x00004aa6, 0x000bbe55, 0x000ffa27 },
1755 { 157, 0x00002ccc, 0x00004aae, 0x000bbe55, 0x000ffa07 },
1756 { 161, 0x00002ccc, 0x00004ab2, 0x000bbe55, 0x000ffa0f },
1757 { 165, 0x00002ccc, 0x00004ab6, 0x000bbe55, 0x000ffa17 },
1758
1759 /* MMAC(Japan)J52 ch 34,38,42,46 */
1760 { 34, 0x00002ccc, 0x0000499a, 0x0009be55, 0x000ffa0b },
1761 { 38, 0x00002ccc, 0x0000499e, 0x0009be55, 0x000ffa13 },
1762 { 42, 0x00002ccc, 0x000049a2, 0x0009be55, 0x000ffa1b },
1763 { 46, 0x00002ccc, 0x000049a6, 0x0009be55, 0x000ffa23 },
1764};
1765
1766
1767static void rt73usb_probe_hw_mode(struct rt2x00_dev *rt2x00dev)
1768{
1769 struct hw_mode_spec *spec = &rt2x00dev->spec;
1770 u8 *txpower;
1771 unsigned int i;
1772
1773 /*
1774 * Initialize all hw fields.
1775 */
1776 rt2x00dev->hw->flags =
1777 IEEE80211_HW_HOST_GEN_BEACON_TEMPLATE |
4150c572 1778 IEEE80211_HW_HOST_BROADCAST_PS_BUFFERING;
95ea3627
ID		 1779 rt2x00dev->hw->extra_tx_headroom = TXD_DESC_SIZE;
1780 rt2x00dev->hw->max_signal = MAX_SIGNAL;
1781 rt2x00dev->hw->max_rssi = MAX_RX_SSI;
871ff6ed 1782 rt2x00dev->hw->queues = 4;
95ea3627
ID		 1783
1784 SET_IEEE80211_DEV(rt2x00dev->hw, &rt2x00dev_usb(rt2x00dev)->dev);
1785 SET_IEEE80211_PERM_ADDR(rt2x00dev->hw,
1786 rt2x00_eeprom_addr(rt2x00dev,
1787 EEPROM_MAC_ADDR_0));
1788
1789 /*
1790 * Convert tx_power array in eeprom.
1791 */
1792 txpower = rt2x00_eeprom_addr(rt2x00dev, EEPROM_TXPOWER_G_START);
1793 for (i = 0; i < 14; i++)
1794 txpower[i] = TXPOWER_FROM_DEV(txpower[i]);
1795
1796 /*
1797 * Initialize hw_mode information.
1798 */
31562e80
ID		 1799 spec->supported_bands = SUPPORT_BAND_2GHZ;
1800 spec->supported_rates = SUPPORT_RATE_CCK | SUPPORT_RATE_OFDM;
95ea3627
ID		 1801 spec->tx_power_a = NULL;
1802 spec->tx_power_bg = txpower;
1803 spec->tx_power_default = DEFAULT_TXPOWER;
1804
1805 if (rt2x00_rf(&rt2x00dev->chip, RF2528)) {
1806 spec->num_channels = ARRAY_SIZE(rf_vals_bg_2528);
1807 spec->channels = rf_vals_bg_2528;
1808 } else if (rt2x00_rf(&rt2x00dev->chip, RF5226)) {
31562e80 1809 spec->supported_bands |= SUPPORT_BAND_5GHZ;
95ea3627
ID		 1810 spec->num_channels = ARRAY_SIZE(rf_vals_5226);
1811 spec->channels = rf_vals_5226;
1812 } else if (rt2x00_rf(&rt2x00dev->chip, RF2527)) {
1813 spec->num_channels = 14;
1814 spec->channels = rf_vals_5225_2527;
1815 } else if (rt2x00_rf(&rt2x00dev->chip, RF5225)) {
31562e80 1816 spec->supported_bands |= SUPPORT_BAND_5GHZ;
95ea3627
ID		 1817 spec->num_channels = ARRAY_SIZE(rf_vals_5225_2527);
1818 spec->channels = rf_vals_5225_2527;
1819 }
1820
1821 if (rt2x00_rf(&rt2x00dev->chip, RF5225) ||
1822 rt2x00_rf(&rt2x00dev->chip, RF5226)) {
95ea3627
ID		 1823 txpower = rt2x00_eeprom_addr(rt2x00dev, EEPROM_TXPOWER_A_START);
1824 for (i = 0; i < 14; i++)
1825 txpower[i] = TXPOWER_FROM_DEV(txpower[i]);
1826
1827 spec->tx_power_a = txpower;
1828 }
1829}
1830
1831static int rt73usb_probe_hw(struct rt2x00_dev *rt2x00dev)
1832{
1833 int retval;
1834
1835 /*
1836 * Allocate eeprom data.
1837 */
1838 retval = rt73usb_validate_eeprom(rt2x00dev);
1839 if (retval)
1840 return retval;
1841
1842 retval = rt73usb_init_eeprom(rt2x00dev);
1843 if (retval)
1844 return retval;
1845
1846 /*
1847 * Initialize hw specifications.
1848 */
1849 rt73usb_probe_hw_mode(rt2x00dev);
1850
1851 /*
9404ef34 1852 * This device requires firmware.
95ea3627 1853 */
066cb637 1854 __set_bit(DRIVER_REQUIRE_FIRMWARE, &rt2x00dev->flags);
9404ef34 1855 __set_bit(DRIVER_REQUIRE_FIRMWARE_CRC_ITU_T, &rt2x00dev->flags);
95ea3627
ID		 1856
1857 /*
1858 * Set the rssi offset.
1859 */
1860 rt2x00dev->rssi_offset = DEFAULT_RSSI_OFFSET;
1861
1862 return 0;
1863}
1864
1865/*
1866 * IEEE80211 stack callback functions.
1867 */
4150c572
JB		 1868static void rt73usb_configure_filter(struct ieee80211_hw *hw,
1869 unsigned int changed_flags,
1870 unsigned int *total_flags,
1871 int mc_count,
1872 struct dev_addr_list *mc_list)
1873{
1874 struct rt2x00_dev *rt2x00dev = hw->priv;
4150c572
JB		 1875 u32 reg;
1876
1877 /*
1878 * Mask off any flags we are going to ignore from
1879 * the total_flags field.
1880 */
1881 *total_flags &=
1882 FIF_ALLMULTI |
1883 FIF_FCSFAIL |
1884 FIF_PLCPFAIL |
1885 FIF_CONTROL |
1886 FIF_OTHER_BSS |
1887 FIF_PROMISC_IN_BSS;
1888
1889 /*
1890 * Apply some rules to the filters:
1891 * - Some filters imply different filters to be set.
1892 * - Some things we can't filter out at all.
4150c572
JB		 1893 */
1894 if (mc_count)
1895 *total_flags |= FIF_ALLMULTI;
5886d0db
ID		 1896 if (*total_flags & FIF_OTHER_BSS ||
1897 *total_flags & FIF_PROMISC_IN_BSS)
4150c572 1898 *total_flags |= FIF_PROMISC_IN_BSS | FIF_OTHER_BSS;
4150c572
JB		 1899
1900 /*
1901 * Check if there is any work left for us.
1902 */
3c4f2085 1903 if (rt2x00dev->packet_filter == *total_flags)
4150c572 1904 return;
3c4f2085 1905 rt2x00dev->packet_filter = *total_flags;
4150c572
JB		 1906
1907 /*
1908 * When in atomic context, reschedule and let rt2x00lib
1909 * call this function again.
1910 */
1911 if (in_atomic()) {
1912 queue_work(rt2x00dev->hw->workqueue, &rt2x00dev->filter_work);
1913 return;
1914 }
1915
1916 /*
1917 * Start configuration steps.
1918 * Note that the version error will always be dropped
1919 * and broadcast frames will always be accepted since
1920 * there is no filter for it at this time.
1921 */
1922 rt73usb_register_read(rt2x00dev, TXRX_CSR0, &reg);
1923 rt2x00_set_field32(&reg, TXRX_CSR0_DROP_CRC,
1924 !(*total_flags & FIF_FCSFAIL));
1925 rt2x00_set_field32(&reg, TXRX_CSR0_DROP_PHYSICAL,
1926 !(*total_flags & FIF_PLCPFAIL));
1927 rt2x00_set_field32(&reg, TXRX_CSR0_DROP_CONTROL,
1928 !(*total_flags & FIF_CONTROL));
1929 rt2x00_set_field32(&reg, TXRX_CSR0_DROP_NOT_TO_ME,
1930 !(*total_flags & FIF_PROMISC_IN_BSS));
1931 rt2x00_set_field32(&reg, TXRX_CSR0_DROP_TO_DS,
1932 !(*total_flags & FIF_PROMISC_IN_BSS));
1933 rt2x00_set_field32(&reg, TXRX_CSR0_DROP_VERSION_ERROR, 1);
1934 rt2x00_set_field32(&reg, TXRX_CSR0_DROP_MULTICAST,
1935 !(*total_flags & FIF_ALLMULTI));
1936 rt2x00_set_field32(&reg, TXRX_CSR0_DROP_BROADCAST, 0);
e542239f
ID		 1937 rt2x00_set_field32(&reg, TXRX_CSR0_DROP_ACK_CTS,
1938 !(*total_flags & FIF_CONTROL));
4150c572
JB		 1939 rt73usb_register_write(rt2x00dev, TXRX_CSR0, reg);
1940}
1941
95ea3627
ID		 1942static int rt73usb_set_retry_limit(struct ieee80211_hw *hw,
1943 u32 short_retry, u32 long_retry)
1944{
1945 struct rt2x00_dev *rt2x00dev = hw->priv;
1946 u32 reg;
1947
1948 rt73usb_register_read(rt2x00dev, TXRX_CSR4, &reg);
1949 rt2x00_set_field32(&reg, TXRX_CSR4_LONG_RETRY_LIMIT, long_retry);
1950 rt2x00_set_field32(&reg, TXRX_CSR4_SHORT_RETRY_LIMIT, short_retry);
1951 rt73usb_register_write(rt2x00dev, TXRX_CSR4, reg);
1952
1953 return 0;
1954}
1955
1956#if 0
1957/*
1958 * Mac80211 demands get_tsf must be atomic.
1959 * This is not possible for rt73usb since all register access
1960 * functions require sleeping. Untill mac80211 no longer needs
1961 * get_tsf to be atomic, this function should be disabled.
1962 */
1963static u64 rt73usb_get_tsf(struct ieee80211_hw *hw)
1964{
1965 struct rt2x00_dev *rt2x00dev = hw->priv;
1966 u64 tsf;
1967 u32 reg;
1968
1969 rt73usb_register_read(rt2x00dev, TXRX_CSR13, &reg);
1970 tsf = (u64) rt2x00_get_field32(reg, TXRX_CSR13_HIGH_TSFTIMER) << 32;
1971 rt73usb_register_read(rt2x00dev, TXRX_CSR12, &reg);
1972 tsf |= rt2x00_get_field32(reg, TXRX_CSR12_LOW_TSFTIMER);
1973
1974 return tsf;
1975}
37894473
ID		 1976#else
1977#define rt73usb_get_tsf NULL
95ea3627
ID		 1978#endif
1979
24845910 1980static int rt73usb_beacon_update(struct ieee80211_hw *hw, struct sk_buff *skb,
6bb40dd1 1981 struct ieee80211_tx_control *control)
95ea3627
ID		 1982{
1983 struct rt2x00_dev *rt2x00dev = hw->priv;
6bb40dd1 1984 struct rt2x00_intf *intf = vif_to_intf(control->vif);
181d6902 1985 struct skb_frame_desc *skbdesc;
6bb40dd1
ID		 1986 unsigned int beacon_base;
1987 unsigned int timeout;
8af244cc 1988 u32 reg;
95ea3627 1989
6bb40dd1
ID		 1990 if (unlikely(!intf->beacon))
1991 return -ENOBUFS;
95ea3627
ID		 1992
1993 /*
08992f7f 1994 * Add the descriptor in front of the skb.
95ea3627 1995 */
6bb40dd1
ID		 1996 skb_push(skb, intf->beacon->queue->desc_size);
1997 memset(skb->data, 0, intf->beacon->queue->desc_size);
c22eb87b 1998
08992f7f
ID		 1999 /*
2000 * Fill in skb descriptor
2001 */
181d6902
ID		 2002 skbdesc = get_skb_frame_desc(skb);
2003 memset(skbdesc, 0, sizeof(*skbdesc));
baf26a7e 2004 skbdesc->flags |= FRAME_DESC_DRIVER_GENERATED;
6bb40dd1
ID		 2005 skbdesc->data = skb->data + intf->beacon->queue->desc_size;
2006 skbdesc->data_len = skb->len - intf->beacon->queue->desc_size;
181d6902 2007 skbdesc->desc = skb->data;
6bb40dd1
ID		 2008 skbdesc->desc_len = intf->beacon->queue->desc_size;
2009 skbdesc->entry = intf->beacon;
08992f7f 2010
8af244cc
ID		 2011 /*
2012 * Disable beaconing while we are reloading the beacon data,
2013 * otherwise we might be sending out invalid data.
2014 */
2015 rt73usb_register_read(rt2x00dev, TXRX_CSR9, &reg);
2016 rt2x00_set_field32(&reg, TXRX_CSR9_TSF_TICKING, 0);
2017 rt2x00_set_field32(&reg, TXRX_CSR9_TBTT_ENABLE, 0);
2018 rt2x00_set_field32(&reg, TXRX_CSR9_BEACON_GEN, 0);
2019 rt73usb_register_write(rt2x00dev, TXRX_CSR9, reg);
2020
6bb40dd1 2021 /*
5957da4c
ID		 2022 * mac80211 doesn't provide the control->queue variable
2023 * for beacons. Set our own queue identification so
2024 * it can be used during descriptor initialization.
6bb40dd1 2025 */
5957da4c 2026 control->queue = RT2X00_BCN_QUEUE_BEACON;
08992f7f 2027 rt2x00lib_write_tx_desc(rt2x00dev, skb, control);
95ea3627
ID		 2028
2029 /*
2030 * Write entire beacon with descriptor to register,
2031 * and kick the beacon generator.
2032 */
6bb40dd1 2033 beacon_base = HW_BEACON_OFFSET(intf->beacon->entry_idx);
95ea3627
ID		 2034 timeout = REGISTER_TIMEOUT * (skb->len / sizeof(u32));
2035 rt2x00usb_vendor_request(rt2x00dev, USB_MULTI_WRITE,
6bb40dd1 2036 USB_VENDOR_REQUEST_OUT, beacon_base, 0,
95ea3627 2037 skb->data, skb->len, timeout);
6bb40dd1 2038 rt73usb_kick_tx_queue(rt2x00dev, control->queue);
95ea3627
ID		 2039
2040 return 0;
2041}
2042
2043static const struct ieee80211_ops rt73usb_mac80211_ops = {
2044 .tx = rt2x00mac_tx,
4150c572
JB		 2045 .start = rt2x00mac_start,
2046 .stop = rt2x00mac_stop,
95ea3627
ID		 2047 .add_interface = rt2x00mac_add_interface,
2048 .remove_interface = rt2x00mac_remove_interface,
2049 .config = rt2x00mac_config,
2050 .config_interface = rt2x00mac_config_interface,
4150c572 2051 .configure_filter = rt73usb_configure_filter,
95ea3627
ID		 2052 .get_stats = rt2x00mac_get_stats,
2053 .set_retry_limit = rt73usb_set_retry_limit,
471b3efd 2054 .bss_info_changed = rt2x00mac_bss_info_changed,
95ea3627
ID		 2055 .conf_tx = rt2x00mac_conf_tx,
2056 .get_tx_stats = rt2x00mac_get_tx_stats,
95ea3627 2057 .get_tsf = rt73usb_get_tsf,
95ea3627
ID		 2058 .beacon_update = rt73usb_beacon_update,
2059};
2060
2061static const struct rt2x00lib_ops rt73usb_rt2x00_ops = {
2062 .probe_hw = rt73usb_probe_hw,
2063 .get_firmware_name = rt73usb_get_firmware_name,
2064 .load_firmware = rt73usb_load_firmware,
2065 .initialize = rt2x00usb_initialize,
2066 .uninitialize = rt2x00usb_uninitialize,
837e7f24
ID		 2067 .init_rxentry = rt2x00usb_init_rxentry,
2068 .init_txentry = rt2x00usb_init_txentry,
95ea3627
ID		 2069 .set_device_state = rt73usb_set_device_state,
2070 .link_stats = rt73usb_link_stats,
2071 .reset_tuner = rt73usb_reset_tuner,
2072 .link_tuner = rt73usb_link_tuner,
a9450b70 2073 .led_brightness = rt73usb_led_brightness,
95ea3627
ID		 2074 .write_tx_desc = rt73usb_write_tx_desc,
2075 .write_tx_data = rt2x00usb_write_tx_data,
dd9fa2d2 2076 .get_tx_data_len = rt73usb_get_tx_data_len,
95ea3627
ID		 2077 .kick_tx_queue = rt73usb_kick_tx_queue,
2078 .fill_rxdone = rt73usb_fill_rxdone,
6bb40dd1 2079 .config_intf = rt73usb_config_intf,
5c58ee51 2080 .config_preamble = rt73usb_config_preamble,
95ea3627
ID		 2081 .config = rt73usb_config,
2082};
2083
181d6902
ID		 2084static const struct data_queue_desc rt73usb_queue_rx = {
2085 .entry_num = RX_ENTRIES,
2086 .data_size = DATA_FRAME_SIZE,
2087 .desc_size = RXD_DESC_SIZE,
2088 .priv_size = sizeof(struct queue_entry_priv_usb_rx),
2089};
2090
2091static const struct data_queue_desc rt73usb_queue_tx = {
2092 .entry_num = TX_ENTRIES,
2093 .data_size = DATA_FRAME_SIZE,
2094 .desc_size = TXD_DESC_SIZE,
2095 .priv_size = sizeof(struct queue_entry_priv_usb_tx),
2096};
2097
2098static const struct data_queue_desc rt73usb_queue_bcn = {
6bb40dd1 2099 .entry_num = 4 * BEACON_ENTRIES,
181d6902
ID		 2100 .data_size = MGMT_FRAME_SIZE,
2101 .desc_size = TXINFO_SIZE,
2102 .priv_size = sizeof(struct queue_entry_priv_usb_tx),
2103};
2104
95ea3627 2105static const struct rt2x00_ops rt73usb_ops = {
2360157c 2106 .name = KBUILD_MODNAME,
6bb40dd1
ID		 2107 .max_sta_intf = 1,
2108 .max_ap_intf = 4,
95ea3627
ID		 2109 .eeprom_size = EEPROM_SIZE,
2110 .rf_size = RF_SIZE,
181d6902
ID		 2111 .rx = &rt73usb_queue_rx,
2112 .tx = &rt73usb_queue_tx,
2113 .bcn = &rt73usb_queue_bcn,
95ea3627
ID		 2114 .lib = &rt73usb_rt2x00_ops,
2115 .hw = &rt73usb_mac80211_ops,
2116#ifdef CONFIG_RT2X00_LIB_DEBUGFS
2117 .debugfs = &rt73usb_rt2x00debug,
2118#endif /* CONFIG_RT2X00_LIB_DEBUGFS */
2119};
2120
2121/*
2122 * rt73usb module information.
2123 */
2124static struct usb_device_id rt73usb_device_table[] = {
2125 /* AboCom */
2126 { USB_DEVICE(0x07b8, 0xb21d), USB_DEVICE_DATA(&rt73usb_ops) },
2127 /* Askey */
2128 { USB_DEVICE(0x1690, 0x0722), USB_DEVICE_DATA(&rt73usb_ops) },
2129 /* ASUS */
2130 { USB_DEVICE(0x0b05, 0x1723), USB_DEVICE_DATA(&rt73usb_ops) },
2131 { USB_DEVICE(0x0b05, 0x1724), USB_DEVICE_DATA(&rt73usb_ops) },
2132 /* Belkin */
2133 { USB_DEVICE(0x050d, 0x7050), USB_DEVICE_DATA(&rt73usb_ops) },
2134 { USB_DEVICE(0x050d, 0x705a), USB_DEVICE_DATA(&rt73usb_ops) },
2135 { USB_DEVICE(0x050d, 0x905b), USB_DEVICE_DATA(&rt73usb_ops) },
1f06862e 2136 { USB_DEVICE(0x050d, 0x905c), USB_DEVICE_DATA(&rt73usb_ops) },
95ea3627
ID		 2137 /* Billionton */
2138 { USB_DEVICE(0x1631, 0xc019), USB_DEVICE_DATA(&rt73usb_ops) },
2139 /* Buffalo */
2140 { USB_DEVICE(0x0411, 0x00f4), USB_DEVICE_DATA(&rt73usb_ops) },
2141 /* CNet */
2142 { USB_DEVICE(0x1371, 0x9022), USB_DEVICE_DATA(&rt73usb_ops) },
2143 { USB_DEVICE(0x1371, 0x9032), USB_DEVICE_DATA(&rt73usb_ops) },
2144 /* Conceptronic */
2145 { USB_DEVICE(0x14b2, 0x3c22), USB_DEVICE_DATA(&rt73usb_ops) },
2146 /* D-Link */
2147 { USB_DEVICE(0x07d1, 0x3c03), USB_DEVICE_DATA(&rt73usb_ops) },
2148 { USB_DEVICE(0x07d1, 0x3c04), USB_DEVICE_DATA(&rt73usb_ops) },
2149 /* Gemtek */
2150 { USB_DEVICE(0x15a9, 0x0004), USB_DEVICE_DATA(&rt73usb_ops) },
2151 /* Gigabyte */
2152 { USB_DEVICE(0x1044, 0x8008), USB_DEVICE_DATA(&rt73usb_ops) },
2153 { USB_DEVICE(0x1044, 0x800a), USB_DEVICE_DATA(&rt73usb_ops) },
2154 /* Huawei-3Com */
2155 { USB_DEVICE(0x1472, 0x0009), USB_DEVICE_DATA(&rt73usb_ops) },
2156 /* Hercules */
2157 { USB_DEVICE(0x06f8, 0xe010), USB_DEVICE_DATA(&rt73usb_ops) },
2158 { USB_DEVICE(0x06f8, 0xe020), USB_DEVICE_DATA(&rt73usb_ops) },
2159 /* Linksys */
2160 { USB_DEVICE(0x13b1, 0x0020), USB_DEVICE_DATA(&rt73usb_ops) },
2161 { USB_DEVICE(0x13b1, 0x0023), USB_DEVICE_DATA(&rt73usb_ops) },
2162 /* MSI */
2163 { USB_DEVICE(0x0db0, 0x6877), USB_DEVICE_DATA(&rt73usb_ops) },
2164 { USB_DEVICE(0x0db0, 0x6874), USB_DEVICE_DATA(&rt73usb_ops) },
2165 { USB_DEVICE(0x0db0, 0xa861), USB_DEVICE_DATA(&rt73usb_ops) },
2166 { USB_DEVICE(0x0db0, 0xa874), USB_DEVICE_DATA(&rt73usb_ops) },
2167 /* Ralink */
2168 { USB_DEVICE(0x148f, 0x2573), USB_DEVICE_DATA(&rt73usb_ops) },
2169 { USB_DEVICE(0x148f, 0x2671), USB_DEVICE_DATA(&rt73usb_ops) },
2170 /* Qcom */
2171 { USB_DEVICE(0x18e8, 0x6196), USB_DEVICE_DATA(&rt73usb_ops) },
2172 { USB_DEVICE(0x18e8, 0x6229), USB_DEVICE_DATA(&rt73usb_ops) },
2173 { USB_DEVICE(0x18e8, 0x6238), USB_DEVICE_DATA(&rt73usb_ops) },
2174 /* Senao */
2175 { USB_DEVICE(0x1740, 0x7100), USB_DEVICE_DATA(&rt73usb_ops) },
2176 /* Sitecom */
2177 { USB_DEVICE(0x0df6, 0x9712), USB_DEVICE_DATA(&rt73usb_ops) },
2178 { USB_DEVICE(0x0df6, 0x90ac), USB_DEVICE_DATA(&rt73usb_ops) },
2179 /* Surecom */
2180 { USB_DEVICE(0x0769, 0x31f3), USB_DEVICE_DATA(&rt73usb_ops) },
2181 /* Planex */
2182 { USB_DEVICE(0x2019, 0xab01), USB_DEVICE_DATA(&rt73usb_ops) },
2183 { USB_DEVICE(0x2019, 0xab50), USB_DEVICE_DATA(&rt73usb_ops) },
2184 { 0, }
2185};
2186
2187MODULE_AUTHOR(DRV_PROJECT);
2188MODULE_VERSION(DRV_VERSION);
2189MODULE_DESCRIPTION("Ralink RT73 USB Wireless LAN driver.");
2190MODULE_SUPPORTED_DEVICE("Ralink RT2571W & RT2671 USB chipset based cards");
2191MODULE_DEVICE_TABLE(usb, rt73usb_device_table);
2192MODULE_FIRMWARE(FIRMWARE_RT2571);
2193MODULE_LICENSE("GPL");
2194
2195static struct usb_driver rt73usb_driver = {
2360157c 2196 .name = KBUILD_MODNAME,
95ea3627
ID		 2197 .id_table = rt73usb_device_table,
2198 .probe = rt2x00usb_probe,
2199 .disconnect = rt2x00usb_disconnect,
2200 .suspend = rt2x00usb_suspend,
2201 .resume = rt2x00usb_resume,
2202};
2203
2204static int __init rt73usb_init(void)
2205{
2206 return usb_register(&rt73usb_driver);
2207}
2208
2209static void __exit rt73usb_exit(void)
2210{
2211 usb_deregister(&rt73usb_driver);
2212}
2213
2214module_init(rt73usb_init);
2215module_exit(rt73usb_exit);
Linux kernel - Deliverables
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