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rt2x00: Add per-interface structure
[deliverable/linux.git] / drivers / net / wireless / rt2x00 / rt73usb.c
CommitLineData
95ea3627 1/*
811aa9ca 2 Copyright (C) 2004 - 2008 rt2x00 SourceForge Project
95ea3627
ID		 3 <http://rt2x00.serialmonkey.com>
4
5 This program is free software; you can redistribute it and/or modify
6 it under the terms of the GNU General Public License as published by
7 the Free Software Foundation; either version 2 of the License, or
8 (at your option) any later version.
9
10 This program is distributed in the hope that it will be useful,
11 but WITHOUT ANY WARRANTY; without even the implied warranty of
12 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 GNU General Public License for more details.
14
15 You should have received a copy of the GNU General Public License
16 along with this program; if not, write to the
17 Free Software Foundation, Inc.,
18 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
19 */
20
21/*
22 Module: rt73usb
23 Abstract: rt73usb device specific routines.
24 Supported chipsets: rt2571W & rt2671.
25 */
26
95ea3627
ID		 27#include <linux/delay.h>
28#include <linux/etherdevice.h>
29#include <linux/init.h>
30#include <linux/kernel.h>
31#include <linux/module.h>
32#include <linux/usb.h>
33
34#include "rt2x00.h"
35#include "rt2x00usb.h"
36#include "rt73usb.h"
37
38/*
39 * Register access.
40 * All access to the CSR registers will go through the methods
41 * rt73usb_register_read and rt73usb_register_write.
42 * BBP and RF register require indirect register access,
43 * and use the CSR registers BBPCSR and RFCSR to achieve this.
44 * These indirect registers work with busy bits,
45 * and we will try maximal REGISTER_BUSY_COUNT times to access
46 * the register while taking a REGISTER_BUSY_DELAY us delay
47 * between each attampt. When the busy bit is still set at that time,
48 * the access attempt is considered to have failed,
49 * and we will print an error.
3d82346c 50 * The _lock versions must be used if you already hold the usb_cache_mutex
95ea3627 51 */
0e14f6d3 52static inline void rt73usb_register_read(struct rt2x00_dev *rt2x00dev,
95ea3627
ID		 53 const unsigned int offset, u32 *value)
54{
55 __le32 reg;
56 rt2x00usb_vendor_request_buff(rt2x00dev, USB_MULTI_READ,
57 USB_VENDOR_REQUEST_IN, offset,
58 &reg, sizeof(u32), REGISTER_TIMEOUT);
59 *value = le32_to_cpu(reg);
60}
61
3d82346c
AB		 62static inline void rt73usb_register_read_lock(struct rt2x00_dev *rt2x00dev,
63 const unsigned int offset, u32 *value)
64{
65 __le32 reg;
66 rt2x00usb_vendor_req_buff_lock(rt2x00dev, USB_MULTI_READ,
67 USB_VENDOR_REQUEST_IN, offset,
68 &reg, sizeof(u32), REGISTER_TIMEOUT);
69 *value = le32_to_cpu(reg);
70}
71
0e14f6d3 72static inline void rt73usb_register_multiread(struct rt2x00_dev *rt2x00dev,
95ea3627
ID		 73 const unsigned int offset,
74 void *value, const u32 length)
75{
76 int timeout = REGISTER_TIMEOUT * (length / sizeof(u32));
77 rt2x00usb_vendor_request_buff(rt2x00dev, USB_MULTI_READ,
78 USB_VENDOR_REQUEST_IN, offset,
79 value, length, timeout);
80}
81
0e14f6d3 82static inline void rt73usb_register_write(struct rt2x00_dev *rt2x00dev,
95ea3627
ID		 83 const unsigned int offset, u32 value)
84{
85 __le32 reg = cpu_to_le32(value);
86 rt2x00usb_vendor_request_buff(rt2x00dev, USB_MULTI_WRITE,
87 USB_VENDOR_REQUEST_OUT, offset,
88 &reg, sizeof(u32), REGISTER_TIMEOUT);
89}
90
3d82346c
AB		 91static inline void rt73usb_register_write_lock(struct rt2x00_dev *rt2x00dev,
92 const unsigned int offset, u32 value)
93{
94 __le32 reg = cpu_to_le32(value);
95 rt2x00usb_vendor_req_buff_lock(rt2x00dev, USB_MULTI_WRITE,
96 USB_VENDOR_REQUEST_OUT, offset,
97 &reg, sizeof(u32), REGISTER_TIMEOUT);
98}
99
0e14f6d3 100static inline void rt73usb_register_multiwrite(struct rt2x00_dev *rt2x00dev,
95ea3627
ID		 101 const unsigned int offset,
102 void *value, const u32 length)
103{
104 int timeout = REGISTER_TIMEOUT * (length / sizeof(u32));
105 rt2x00usb_vendor_request_buff(rt2x00dev, USB_MULTI_WRITE,
106 USB_VENDOR_REQUEST_OUT, offset,
107 value, length, timeout);
108}
109
0e14f6d3 110static u32 rt73usb_bbp_check(struct rt2x00_dev *rt2x00dev)
95ea3627
ID		 111{
112 u32 reg;
113 unsigned int i;
114
115 for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
3d82346c 116 rt73usb_register_read_lock(rt2x00dev, PHY_CSR3, &reg);
95ea3627
ID		 117 if (!rt2x00_get_field32(reg, PHY_CSR3_BUSY))
118 break;
119 udelay(REGISTER_BUSY_DELAY);
120 }
121
122 return reg;
123}
124
0e14f6d3 125static void rt73usb_bbp_write(struct rt2x00_dev *rt2x00dev,
95ea3627
ID		 126 const unsigned int word, const u8 value)
127{
128 u32 reg;
129
3d82346c
AB		 130 mutex_lock(&rt2x00dev->usb_cache_mutex);
131
95ea3627
ID		 132 /*
133 * Wait until the BBP becomes ready.
134 */
135 reg = rt73usb_bbp_check(rt2x00dev);
136 if (rt2x00_get_field32(reg, PHY_CSR3_BUSY)) {
137 ERROR(rt2x00dev, "PHY_CSR3 register busy. Write failed.\n");
3d82346c 138 mutex_unlock(&rt2x00dev->usb_cache_mutex);
95ea3627
ID		 139 return;
140 }
141
142 /*
143 * Write the data into the BBP.
144 */
145 reg = 0;
146 rt2x00_set_field32(&reg, PHY_CSR3_VALUE, value);
147 rt2x00_set_field32(&reg, PHY_CSR3_REGNUM, word);
148 rt2x00_set_field32(&reg, PHY_CSR3_BUSY, 1);
149 rt2x00_set_field32(&reg, PHY_CSR3_READ_CONTROL, 0);
150
3d82346c
AB		 151 rt73usb_register_write_lock(rt2x00dev, PHY_CSR3, reg);
152 mutex_unlock(&rt2x00dev->usb_cache_mutex);
95ea3627
ID		 153}
154
0e14f6d3 155static void rt73usb_bbp_read(struct rt2x00_dev *rt2x00dev,
95ea3627
ID		 156 const unsigned int word, u8 *value)
157{
158 u32 reg;
159
3d82346c
AB		 160 mutex_lock(&rt2x00dev->usb_cache_mutex);
161
95ea3627
ID		 162 /*
163 * Wait until the BBP becomes ready.
164 */
165 reg = rt73usb_bbp_check(rt2x00dev);
166 if (rt2x00_get_field32(reg, PHY_CSR3_BUSY)) {
167 ERROR(rt2x00dev, "PHY_CSR3 register busy. Read failed.\n");
3d82346c 168 mutex_unlock(&rt2x00dev->usb_cache_mutex);
95ea3627
ID		 169 return;
170 }
171
172 /*
173 * Write the request into the BBP.
174 */
175 reg = 0;
176 rt2x00_set_field32(&reg, PHY_CSR3_REGNUM, word);
177 rt2x00_set_field32(&reg, PHY_CSR3_BUSY, 1);
178 rt2x00_set_field32(&reg, PHY_CSR3_READ_CONTROL, 1);
179
3d82346c 180 rt73usb_register_write_lock(rt2x00dev, PHY_CSR3, reg);
95ea3627
ID		 181
182 /*
183 * Wait until the BBP becomes ready.
184 */
185 reg = rt73usb_bbp_check(rt2x00dev);
186 if (rt2x00_get_field32(reg, PHY_CSR3_BUSY)) {
187 ERROR(rt2x00dev, "PHY_CSR3 register busy. Read failed.\n");
188 *value = 0xff;
189 return;
190 }
191
192 *value = rt2x00_get_field32(reg, PHY_CSR3_VALUE);
3d82346c 193 mutex_unlock(&rt2x00dev->usb_cache_mutex);
95ea3627
ID		 194}
195
0e14f6d3 196static void rt73usb_rf_write(struct rt2x00_dev *rt2x00dev,
95ea3627
ID		 197 const unsigned int word, const u32 value)
198{
199 u32 reg;
200 unsigned int i;
201
202 if (!word)
203 return;
204
3d82346c
AB		 205 mutex_lock(&rt2x00dev->usb_cache_mutex);
206
95ea3627 207 for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
3d82346c 208 rt73usb_register_read_lock(rt2x00dev, PHY_CSR4, &reg);
95ea3627
ID		 209 if (!rt2x00_get_field32(reg, PHY_CSR4_BUSY))
210 goto rf_write;
211 udelay(REGISTER_BUSY_DELAY);
212 }
213
3d82346c 214 mutex_unlock(&rt2x00dev->usb_cache_mutex);
95ea3627
ID		 215 ERROR(rt2x00dev, "PHY_CSR4 register busy. Write failed.\n");
216 return;
217
218rf_write:
219 reg = 0;
220 rt2x00_set_field32(&reg, PHY_CSR4_VALUE, value);
221
4f5af6eb
ID		 222 /*
223 * RF5225 and RF2527 contain 21 bits per RF register value,
224 * all others contain 20 bits.
225 */
226 rt2x00_set_field32(&reg, PHY_CSR4_NUMBER_OF_BITS,
ddc827f9
ID		 227 20 + (rt2x00_rf(&rt2x00dev->chip, RF5225) ||
228 rt2x00_rf(&rt2x00dev->chip, RF2527)));
95ea3627
ID		 229 rt2x00_set_field32(&reg, PHY_CSR4_IF_SELECT, 0);
230 rt2x00_set_field32(&reg, PHY_CSR4_BUSY, 1);
231
3d82346c 232 rt73usb_register_write_lock(rt2x00dev, PHY_CSR4, reg);
95ea3627 233 rt2x00_rf_write(rt2x00dev, word, value);
3d82346c 234 mutex_unlock(&rt2x00dev->usb_cache_mutex);
95ea3627
ID		 235}
236
237#ifdef CONFIG_RT2X00_LIB_DEBUGFS
238#define CSR_OFFSET(__word) ( CSR_REG_BASE + ((__word) * sizeof(u32)) )
239
0e14f6d3 240static void rt73usb_read_csr(struct rt2x00_dev *rt2x00dev,
95ea3627
ID		 241 const unsigned int word, u32 *data)
242{
243 rt73usb_register_read(rt2x00dev, CSR_OFFSET(word), data);
244}
245
0e14f6d3 246static void rt73usb_write_csr(struct rt2x00_dev *rt2x00dev,
95ea3627
ID		 247 const unsigned int word, u32 data)
248{
249 rt73usb_register_write(rt2x00dev, CSR_OFFSET(word), data);
250}
251
252static const struct rt2x00debug rt73usb_rt2x00debug = {
253 .owner = THIS_MODULE,
254 .csr = {
255 .read = rt73usb_read_csr,
256 .write = rt73usb_write_csr,
257 .word_size = sizeof(u32),
258 .word_count = CSR_REG_SIZE / sizeof(u32),
259 },
260 .eeprom = {
261 .read = rt2x00_eeprom_read,
262 .write = rt2x00_eeprom_write,
263 .word_size = sizeof(u16),
264 .word_count = EEPROM_SIZE / sizeof(u16),
265 },
266 .bbp = {
267 .read = rt73usb_bbp_read,
268 .write = rt73usb_bbp_write,
269 .word_size = sizeof(u8),
270 .word_count = BBP_SIZE / sizeof(u8),
271 },
272 .rf = {
273 .read = rt2x00_rf_read,
274 .write = rt73usb_rf_write,
275 .word_size = sizeof(u32),
276 .word_count = RF_SIZE / sizeof(u32),
277 },
278};
279#endif /* CONFIG_RT2X00_LIB_DEBUGFS */
280
281/*
282 * Configuration handlers.
283 */
6bb40dd1
ID		 284static void rt73usb_config_intf(struct rt2x00_dev *rt2x00dev,
285 struct rt2x00_intf *intf,
286 struct rt2x00intf_conf *conf,
287 const unsigned int flags)
95ea3627 288{
6bb40dd1
ID		 289 unsigned int beacon_base;
290 u32 reg;
95ea3627 291
6bb40dd1
ID		 292 if (flags & CONFIG_UPDATE_TYPE) {
293 /*
294 * Clear current synchronisation setup.
295 * For the Beacon base registers we only need to clear
296 * the first byte since that byte contains the VALID and OWNER
297 * bits which (when set to 0) will invalidate the entire beacon.
298 */
299 beacon_base = HW_BEACON_OFFSET(intf->beacon->entry_idx);
300 rt73usb_register_write(rt2x00dev, TXRX_CSR9, 0);
301 rt73usb_register_write(rt2x00dev, beacon_base, 0);
95ea3627 302
6bb40dd1
ID		 303 /*
304 * Enable synchronisation.
305 */
306 rt73usb_register_read(rt2x00dev, TXRX_CSR9, &reg);
307 rt2x00_set_field32(&reg, TXRX_CSR9_TSF_TICKING, 1);
308 rt2x00_set_field32(&reg, TXRX_CSR9_TBTT_ENABLE,
309 (conf->sync == TSF_SYNC_BEACON));
310 rt2x00_set_field32(&reg, TXRX_CSR9_BEACON_GEN, 0);
311 rt2x00_set_field32(&reg, TXRX_CSR9_TSF_SYNC, conf->sync);
312 rt73usb_register_write(rt2x00dev, TXRX_CSR9, reg);
313 }
95ea3627 314
6bb40dd1
ID		 315 if (flags & CONFIG_UPDATE_MAC) {
316 reg = le32_to_cpu(conf->mac[1]);
317 rt2x00_set_field32(&reg, MAC_CSR3_UNICAST_TO_ME_MASK, 0xff);
318 conf->mac[1] = cpu_to_le32(reg);
95ea3627 319
6bb40dd1
ID		 320 rt73usb_register_multiwrite(rt2x00dev, MAC_CSR2,
321 conf->mac, sizeof(conf->mac));
322 }
95ea3627 323
6bb40dd1
ID		 324 if (flags & CONFIG_UPDATE_BSSID) {
325 reg = le32_to_cpu(conf->bssid[1]);
326 rt2x00_set_field32(&reg, MAC_CSR5_BSS_ID_MASK, 3);
327 conf->bssid[1] = cpu_to_le32(reg);
95ea3627 328
6bb40dd1
ID		 329 rt73usb_register_multiwrite(rt2x00dev, MAC_CSR4,
330 conf->bssid, sizeof(conf->bssid));
331 }
95ea3627
ID		 332}
333
6bb40dd1
ID		 334static int rt73usb_config_preamble(struct rt2x00_dev *rt2x00dev,
335 const int short_preamble,
336 const int ack_timeout,
337 const int ack_consume_time)
95ea3627 338{
95ea3627 339 u32 reg;
95ea3627 340
5c58ee51 341 /*
6bb40dd1
ID		 342 * When in atomic context, we should let rt2x00lib
343 * try this configuration again later.
5c58ee51 344 */
6bb40dd1
ID		 345 if (in_atomic())
346 return -EAGAIN;
95ea3627
ID		 347
348 rt73usb_register_read(rt2x00dev, TXRX_CSR0, &reg);
5c58ee51 349 rt2x00_set_field32(&reg, TXRX_CSR0_RX_ACK_TIMEOUT, ack_timeout);
95ea3627
ID		 350 rt73usb_register_write(rt2x00dev, TXRX_CSR0, reg);
351
352 rt73usb_register_read(rt2x00dev, TXRX_CSR4, &reg);
4f5af6eb 353 rt2x00_set_field32(&reg, TXRX_CSR4_AUTORESPOND_PREAMBLE,
5c58ee51 354 !!short_preamble);
95ea3627 355 rt73usb_register_write(rt2x00dev, TXRX_CSR4, reg);
6bb40dd1
ID		 356
357 return 0;
95ea3627
ID		 358}
359
360static void rt73usb_config_phymode(struct rt2x00_dev *rt2x00dev,
5c58ee51 361 const int basic_rate_mask)
95ea3627 362{
5c58ee51 363 rt73usb_register_write(rt2x00dev, TXRX_CSR5, basic_rate_mask);
95ea3627
ID		 364}
365
5c58ee51
ID		 366static void rt73usb_config_channel(struct rt2x00_dev *rt2x00dev,
367 struct rf_channel *rf, const int txpower)
95ea3627
ID		 368{
369 u8 r3;
370 u8 r94;
371 u8 smart;
372
373 rt2x00_set_field32(&rf->rf3, RF3_TXPOWER, TXPOWER_TO_DEV(txpower));
374 rt2x00_set_field32(&rf->rf4, RF4_FREQ_OFFSET, rt2x00dev->freq_offset);
375
376 smart = !(rt2x00_rf(&rt2x00dev->chip, RF5225) ||
377 rt2x00_rf(&rt2x00dev->chip, RF2527));
378
379 rt73usb_bbp_read(rt2x00dev, 3, &r3);
380 rt2x00_set_field8(&r3, BBP_R3_SMART_MODE, smart);
381 rt73usb_bbp_write(rt2x00dev, 3, r3);
382
383 r94 = 6;
384 if (txpower > MAX_TXPOWER && txpower <= (MAX_TXPOWER + r94))
385 r94 += txpower - MAX_TXPOWER;
386 else if (txpower < MIN_TXPOWER && txpower >= (MIN_TXPOWER - r94))
387 r94 += txpower;
388 rt73usb_bbp_write(rt2x00dev, 94, r94);
389
390 rt73usb_rf_write(rt2x00dev, 1, rf->rf1);
391 rt73usb_rf_write(rt2x00dev, 2, rf->rf2);
392 rt73usb_rf_write(rt2x00dev, 3, rf->rf3 & ~0x00000004);
393 rt73usb_rf_write(rt2x00dev, 4, rf->rf4);
394
395 rt73usb_rf_write(rt2x00dev, 1, rf->rf1);
396 rt73usb_rf_write(rt2x00dev, 2, rf->rf2);
397 rt73usb_rf_write(rt2x00dev, 3, rf->rf3 | 0x00000004);
398 rt73usb_rf_write(rt2x00dev, 4, rf->rf4);
399
400 rt73usb_rf_write(rt2x00dev, 1, rf->rf1);
401 rt73usb_rf_write(rt2x00dev, 2, rf->rf2);
402 rt73usb_rf_write(rt2x00dev, 3, rf->rf3 & ~0x00000004);
403 rt73usb_rf_write(rt2x00dev, 4, rf->rf4);
404
405 udelay(10);
406}
407
95ea3627
ID		 408static void rt73usb_config_txpower(struct rt2x00_dev *rt2x00dev,
409 const int txpower)
410{
411 struct rf_channel rf;
412
413 rt2x00_rf_read(rt2x00dev, 1, &rf.rf1);
414 rt2x00_rf_read(rt2x00dev, 2, &rf.rf2);
415 rt2x00_rf_read(rt2x00dev, 3, &rf.rf3);
416 rt2x00_rf_read(rt2x00dev, 4, &rf.rf4);
417
5c58ee51 418 rt73usb_config_channel(rt2x00dev, &rf, txpower);
95ea3627
ID		 419}
420
421static void rt73usb_config_antenna_5x(struct rt2x00_dev *rt2x00dev,
addc81bd 422 struct antenna_setup *ant)
95ea3627
ID		 423{
424 u8 r3;
425 u8 r4;
426 u8 r77;
2676c94d 427 u8 temp;
95ea3627
ID		 428
429 rt73usb_bbp_read(rt2x00dev, 3, &r3);
430 rt73usb_bbp_read(rt2x00dev, 4, &r4);
431 rt73usb_bbp_read(rt2x00dev, 77, &r77);
432
433 rt2x00_set_field8(&r3, BBP_R3_SMART_MODE, 0);
434
e4cd2ff8
ID		 435 /*
436 * Configure the RX antenna.
437 */
addc81bd 438 switch (ant->rx) {
95ea3627 439 case ANTENNA_HW_DIVERSITY:
2676c94d
MN		 440 rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA_CONTROL, 2);
441 temp = !test_bit(CONFIG_FRAME_TYPE, &rt2x00dev->flags)
442 && (rt2x00dev->curr_hwmode != HWMODE_A);
443 rt2x00_set_field8(&r4, BBP_R4_RX_FRAME_END, temp);
95ea3627
ID		 444 break;
445 case ANTENNA_A:
2676c94d 446 rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA_CONTROL, 1);
95ea3627 447 rt2x00_set_field8(&r4, BBP_R4_RX_FRAME_END, 0);
2676c94d
MN		 448 if (rt2x00dev->curr_hwmode == HWMODE_A)
449 rt2x00_set_field8(&r77, BBP_R77_RX_ANTENNA, 0);
450 else
451 rt2x00_set_field8(&r77, BBP_R77_RX_ANTENNA, 3);
95ea3627 452 break;
39e75857
ID		 453 case ANTENNA_SW_DIVERSITY:
454 /*
455 * NOTE: We should never come here because rt2x00lib is
456 * supposed to catch this and send us the correct antenna
457 * explicitely. However we are nog going to bug about this.
458 * Instead, just default to antenna B.
459 */
95ea3627 460 case ANTENNA_B:
2676c94d 461 rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA_CONTROL, 1);
95ea3627 462 rt2x00_set_field8(&r4, BBP_R4_RX_FRAME_END, 0);
2676c94d
MN		 463 if (rt2x00dev->curr_hwmode == HWMODE_A)
464 rt2x00_set_field8(&r77, BBP_R77_RX_ANTENNA, 3);
465 else
466 rt2x00_set_field8(&r77, BBP_R77_RX_ANTENNA, 0);
95ea3627
ID		 467 break;
468 }
469
470 rt73usb_bbp_write(rt2x00dev, 77, r77);
471 rt73usb_bbp_write(rt2x00dev, 3, r3);
472 rt73usb_bbp_write(rt2x00dev, 4, r4);
473}
474
475static void rt73usb_config_antenna_2x(struct rt2x00_dev *rt2x00dev,
addc81bd 476 struct antenna_setup *ant)
95ea3627
ID		 477{
478 u8 r3;
479 u8 r4;
480 u8 r77;
481
482 rt73usb_bbp_read(rt2x00dev, 3, &r3);
483 rt73usb_bbp_read(rt2x00dev, 4, &r4);
484 rt73usb_bbp_read(rt2x00dev, 77, &r77);
485
486 rt2x00_set_field8(&r3, BBP_R3_SMART_MODE, 0);
487 rt2x00_set_field8(&r4, BBP_R4_RX_FRAME_END,
488 !test_bit(CONFIG_FRAME_TYPE, &rt2x00dev->flags));
489
e4cd2ff8
ID		 490 /*
491 * Configure the RX antenna.
492 */
addc81bd 493 switch (ant->rx) {
95ea3627 494 case ANTENNA_HW_DIVERSITY:
2676c94d 495 rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA_CONTROL, 2);
95ea3627
ID		 496 break;
497 case ANTENNA_A:
2676c94d
MN		 498 rt2x00_set_field8(&r77, BBP_R77_RX_ANTENNA, 3);
499 rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA_CONTROL, 1);
95ea3627 500 break;
39e75857
ID		 501 case ANTENNA_SW_DIVERSITY:
502 /*
503 * NOTE: We should never come here because rt2x00lib is
504 * supposed to catch this and send us the correct antenna
505 * explicitely. However we are nog going to bug about this.
506 * Instead, just default to antenna B.
507 */
95ea3627 508 case ANTENNA_B:
2676c94d
MN		 509 rt2x00_set_field8(&r77, BBP_R77_RX_ANTENNA, 0);
510 rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA_CONTROL, 1);
95ea3627
ID		 511 break;
512 }
513
514 rt73usb_bbp_write(rt2x00dev, 77, r77);
515 rt73usb_bbp_write(rt2x00dev, 3, r3);
516 rt73usb_bbp_write(rt2x00dev, 4, r4);
517}
518
519struct antenna_sel {
520 u8 word;
521 /*
522 * value[0] -> non-LNA
523 * value[1] -> LNA
524 */
525 u8 value[2];
526};
527
528static const struct antenna_sel antenna_sel_a[] = {
529 { 96, { 0x58, 0x78 } },
530 { 104, { 0x38, 0x48 } },
531 { 75, { 0xfe, 0x80 } },
532 { 86, { 0xfe, 0x80 } },
533 { 88, { 0xfe, 0x80 } },
534 { 35, { 0x60, 0x60 } },
535 { 97, { 0x58, 0x58 } },
536 { 98, { 0x58, 0x58 } },
537};
538
539static const struct antenna_sel antenna_sel_bg[] = {
540 { 96, { 0x48, 0x68 } },
541 { 104, { 0x2c, 0x3c } },
542 { 75, { 0xfe, 0x80 } },
543 { 86, { 0xfe, 0x80 } },
544 { 88, { 0xfe, 0x80 } },
545 { 35, { 0x50, 0x50 } },
546 { 97, { 0x48, 0x48 } },
547 { 98, { 0x48, 0x48 } },
548};
549
550static void rt73usb_config_antenna(struct rt2x00_dev *rt2x00dev,
addc81bd 551 struct antenna_setup *ant)
95ea3627
ID		 552{
553 const struct antenna_sel *sel;
554 unsigned int lna;
555 unsigned int i;
556 u32 reg;
557
95ea3627
ID		 558 if (rt2x00dev->curr_hwmode == HWMODE_A) {
559 sel = antenna_sel_a;
560 lna = test_bit(CONFIG_EXTERNAL_LNA_A, &rt2x00dev->flags);
95ea3627
ID		 561 } else {
562 sel = antenna_sel_bg;
563 lna = test_bit(CONFIG_EXTERNAL_LNA_BG, &rt2x00dev->flags);
95ea3627
ID		 564 }
565
2676c94d
MN		 566 for (i = 0; i < ARRAY_SIZE(antenna_sel_a); i++)
567 rt73usb_bbp_write(rt2x00dev, sel[i].word, sel[i].value[lna]);
568
569 rt73usb_register_read(rt2x00dev, PHY_CSR0, &reg);
570
ddc827f9
ID		 571 rt2x00_set_field32(&reg, PHY_CSR0_PA_PE_BG,
572 (rt2x00dev->curr_hwmode == HWMODE_B ||
573 rt2x00dev->curr_hwmode == HWMODE_G));
574 rt2x00_set_field32(&reg, PHY_CSR0_PA_PE_A,
575 (rt2x00dev->curr_hwmode == HWMODE_A));
576
95ea3627
ID		 577 rt73usb_register_write(rt2x00dev, PHY_CSR0, reg);
578
579 if (rt2x00_rf(&rt2x00dev->chip, RF5226) ||
580 rt2x00_rf(&rt2x00dev->chip, RF5225))
addc81bd 581 rt73usb_config_antenna_5x(rt2x00dev, ant);
95ea3627
ID		 582 else if (rt2x00_rf(&rt2x00dev->chip, RF2528) ||
583 rt2x00_rf(&rt2x00dev->chip, RF2527))
addc81bd 584 rt73usb_config_antenna_2x(rt2x00dev, ant);
95ea3627
ID		 585}
586
587static void rt73usb_config_duration(struct rt2x00_dev *rt2x00dev,
5c58ee51 588 struct rt2x00lib_conf *libconf)
95ea3627
ID		 589{
590 u32 reg;
591
592 rt73usb_register_read(rt2x00dev, MAC_CSR9, &reg);
5c58ee51 593 rt2x00_set_field32(&reg, MAC_CSR9_SLOT_TIME, libconf->slot_time);
95ea3627
ID		 594 rt73usb_register_write(rt2x00dev, MAC_CSR9, reg);
595
596 rt73usb_register_read(rt2x00dev, MAC_CSR8, &reg);
5c58ee51 597 rt2x00_set_field32(&reg, MAC_CSR8_SIFS, libconf->sifs);
95ea3627 598 rt2x00_set_field32(&reg, MAC_CSR8_SIFS_AFTER_RX_OFDM, 3);
5c58ee51 599 rt2x00_set_field32(&reg, MAC_CSR8_EIFS, libconf->eifs);
95ea3627
ID		 600 rt73usb_register_write(rt2x00dev, MAC_CSR8, reg);
601
602 rt73usb_register_read(rt2x00dev, TXRX_CSR0, &reg);
603 rt2x00_set_field32(&reg, TXRX_CSR0_TSF_OFFSET, IEEE80211_HEADER);
604 rt73usb_register_write(rt2x00dev, TXRX_CSR0, reg);
605
606 rt73usb_register_read(rt2x00dev, TXRX_CSR4, &reg);
607 rt2x00_set_field32(&reg, TXRX_CSR4_AUTORESPOND_ENABLE, 1);
608 rt73usb_register_write(rt2x00dev, TXRX_CSR4, reg);
609
610 rt73usb_register_read(rt2x00dev, TXRX_CSR9, &reg);
5c58ee51
ID		 611 rt2x00_set_field32(&reg, TXRX_CSR9_BEACON_INTERVAL,
612 libconf->conf->beacon_int * 16);
95ea3627
ID		 613 rt73usb_register_write(rt2x00dev, TXRX_CSR9, reg);
614}
615
616static void rt73usb_config(struct rt2x00_dev *rt2x00dev,
6bb40dd1
ID		 617 struct rt2x00lib_conf *libconf,
618 const unsigned int flags)
95ea3627 619{
95ea3627 620 if (flags & CONFIG_UPDATE_PHYMODE)
5c58ee51 621 rt73usb_config_phymode(rt2x00dev, libconf->basic_rates);
95ea3627 622 if (flags & CONFIG_UPDATE_CHANNEL)
5c58ee51
ID		 623 rt73usb_config_channel(rt2x00dev, &libconf->rf,
624 libconf->conf->power_level);
95ea3627 625 if ((flags & CONFIG_UPDATE_TXPOWER) && !(flags & CONFIG_UPDATE_CHANNEL))
5c58ee51 626 rt73usb_config_txpower(rt2x00dev, libconf->conf->power_level);
95ea3627 627 if (flags & CONFIG_UPDATE_ANTENNA)
addc81bd 628 rt73usb_config_antenna(rt2x00dev, &libconf->ant);
95ea3627 629 if (flags & (CONFIG_UPDATE_SLOT_TIME | CONFIG_UPDATE_BEACON_INT))
5c58ee51 630 rt73usb_config_duration(rt2x00dev, libconf);
95ea3627
ID		 631}
632
633/*
634 * LED functions.
635 */
636static void rt73usb_enable_led(struct rt2x00_dev *rt2x00dev)
637{
638 u32 reg;
639
640 rt73usb_register_read(rt2x00dev, MAC_CSR14, &reg);
641 rt2x00_set_field32(&reg, MAC_CSR14_ON_PERIOD, 70);
642 rt2x00_set_field32(&reg, MAC_CSR14_OFF_PERIOD, 30);
643 rt73usb_register_write(rt2x00dev, MAC_CSR14, reg);
644
645 rt2x00_set_field16(&rt2x00dev->led_reg, MCU_LEDCS_RADIO_STATUS, 1);
ddc827f9
ID		 646 rt2x00_set_field16(&rt2x00dev->led_reg, MCU_LEDCS_LINK_A_STATUS,
647 (rt2x00dev->rx_status.phymode == MODE_IEEE80211A));
648 rt2x00_set_field16(&rt2x00dev->led_reg, MCU_LEDCS_LINK_BG_STATUS,
649 (rt2x00dev->rx_status.phymode != MODE_IEEE80211A));
95ea3627
ID		 650
651 rt2x00usb_vendor_request_sw(rt2x00dev, USB_LED_CONTROL, 0x0000,
652 rt2x00dev->led_reg, REGISTER_TIMEOUT);
653}
654
655static void rt73usb_disable_led(struct rt2x00_dev *rt2x00dev)
656{
657 rt2x00_set_field16(&rt2x00dev->led_reg, MCU_LEDCS_RADIO_STATUS, 0);
658 rt2x00_set_field16(&rt2x00dev->led_reg, MCU_LEDCS_LINK_BG_STATUS, 0);
659 rt2x00_set_field16(&rt2x00dev->led_reg, MCU_LEDCS_LINK_A_STATUS, 0);
660
661 rt2x00usb_vendor_request_sw(rt2x00dev, USB_LED_CONTROL, 0x0000,
662 rt2x00dev->led_reg, REGISTER_TIMEOUT);
663}
664
665static void rt73usb_activity_led(struct rt2x00_dev *rt2x00dev, int rssi)
666{
667 u32 led;
668
669 if (rt2x00dev->led_mode != LED_MODE_SIGNAL_STRENGTH)
670 return;
671
672 /*
673 * Led handling requires a positive value for the rssi,
674 * to do that correctly we need to add the correction.
675 */
676 rssi += rt2x00dev->rssi_offset;
677
678 if (rssi <= 30)
679 led = 0;
680 else if (rssi <= 39)
681 led = 1;
682 else if (rssi <= 49)
683 led = 2;
684 else if (rssi <= 53)
685 led = 3;
686 else if (rssi <= 63)
687 led = 4;
688 else
689 led = 5;
690
691 rt2x00usb_vendor_request_sw(rt2x00dev, USB_LED_CONTROL, led,
692 rt2x00dev->led_reg, REGISTER_TIMEOUT);
693}
694
695/*
696 * Link tuning
697 */
ebcf26da
ID		 698static void rt73usb_link_stats(struct rt2x00_dev *rt2x00dev,
699 struct link_qual *qual)
95ea3627
ID		 700{
701 u32 reg;
702
703 /*
704 * Update FCS error count from register.
705 */
706 rt73usb_register_read(rt2x00dev, STA_CSR0, &reg);
ebcf26da 707 qual->rx_failed = rt2x00_get_field32(reg, STA_CSR0_FCS_ERROR);
95ea3627
ID		 708
709 /*
710 * Update False CCA count from register.
711 */
712 rt73usb_register_read(rt2x00dev, STA_CSR1, &reg);
ebcf26da 713 qual->false_cca = rt2x00_get_field32(reg, STA_CSR1_FALSE_CCA_ERROR);
95ea3627
ID		 714}
715
716static void rt73usb_reset_tuner(struct rt2x00_dev *rt2x00dev)
717{
718 rt73usb_bbp_write(rt2x00dev, 17, 0x20);
719 rt2x00dev->link.vgc_level = 0x20;
720}
721
722static void rt73usb_link_tuner(struct rt2x00_dev *rt2x00dev)
723{
724 int rssi = rt2x00_get_link_rssi(&rt2x00dev->link);
725 u8 r17;
726 u8 up_bound;
727 u8 low_bound;
728
729 /*
730 * Update Led strength
731 */
732 rt73usb_activity_led(rt2x00dev, rssi);
733
734 rt73usb_bbp_read(rt2x00dev, 17, &r17);
735
736 /*
737 * Determine r17 bounds.
738 */
739 if (rt2x00dev->rx_status.phymode == MODE_IEEE80211A) {
740 low_bound = 0x28;
741 up_bound = 0x48;
742
743 if (test_bit(CONFIG_EXTERNAL_LNA_A, &rt2x00dev->flags)) {
744 low_bound += 0x10;
745 up_bound += 0x10;
746 }
747 } else {
748 if (rssi > -82) {
749 low_bound = 0x1c;
750 up_bound = 0x40;
751 } else if (rssi > -84) {
752 low_bound = 0x1c;
753 up_bound = 0x20;
754 } else {
755 low_bound = 0x1c;
756 up_bound = 0x1c;
757 }
758
759 if (test_bit(CONFIG_EXTERNAL_LNA_BG, &rt2x00dev->flags)) {
760 low_bound += 0x14;
761 up_bound += 0x10;
762 }
763 }
764
6bb40dd1
ID		 765 /*
766 * If we are not associated, we should go straight to the
767 * dynamic CCA tuning.
768 */
769 if (!rt2x00dev->intf_associated)
770 goto dynamic_cca_tune;
771
95ea3627
ID		 772 /*
773 * Special big-R17 for very short distance
774 */
775 if (rssi > -35) {
776 if (r17 != 0x60)
777 rt73usb_bbp_write(rt2x00dev, 17, 0x60);
778 return;
779 }
780
781 /*
782 * Special big-R17 for short distance
783 */
784 if (rssi >= -58) {
785 if (r17 != up_bound)
786 rt73usb_bbp_write(rt2x00dev, 17, up_bound);
787 return;
788 }
789
790 /*
791 * Special big-R17 for middle-short distance
792 */
793 if (rssi >= -66) {
794 low_bound += 0x10;
795 if (r17 != low_bound)
796 rt73usb_bbp_write(rt2x00dev, 17, low_bound);
797 return;
798 }
799
800 /*
801 * Special mid-R17 for middle distance
802 */
803 if (rssi >= -74) {
804 if (r17 != (low_bound + 0x10))
805 rt73usb_bbp_write(rt2x00dev, 17, low_bound + 0x08);
806 return;
807 }
808
809 /*
810 * Special case: Change up_bound based on the rssi.
811 * Lower up_bound when rssi is weaker then -74 dBm.
812 */
813 up_bound -= 2 * (-74 - rssi);
814 if (low_bound > up_bound)
815 up_bound = low_bound;
816
817 if (r17 > up_bound) {
818 rt73usb_bbp_write(rt2x00dev, 17, up_bound);
819 return;
820 }
821
6bb40dd1
ID		 822dynamic_cca_tune:
823
95ea3627
ID		 824 /*
825 * r17 does not yet exceed upper limit, continue and base
826 * the r17 tuning on the false CCA count.
827 */
ebcf26da 828 if (rt2x00dev->link.qual.false_cca > 512 && r17 < up_bound) {
95ea3627
ID		 829 r17 += 4;
830 if (r17 > up_bound)
831 r17 = up_bound;
832 rt73usb_bbp_write(rt2x00dev, 17, r17);
ebcf26da 833 } else if (rt2x00dev->link.qual.false_cca < 100 && r17 > low_bound) {
95ea3627
ID		 834 r17 -= 4;
835 if (r17 < low_bound)
836 r17 = low_bound;
837 rt73usb_bbp_write(rt2x00dev, 17, r17);
838 }
839}
840
841/*
842 * Firmware name function.
843 */
844static char *rt73usb_get_firmware_name(struct rt2x00_dev *rt2x00dev)
845{
846 return FIRMWARE_RT2571;
847}
848
849/*
850 * Initialization functions.
851 */
852static int rt73usb_load_firmware(struct rt2x00_dev *rt2x00dev, void *data,
853 const size_t len)
854{
855 unsigned int i;
856 int status;
857 u32 reg;
858 char *ptr = data;
859 char *cache;
860 int buflen;
861 int timeout;
862
863 /*
864 * Wait for stable hardware.
865 */
866 for (i = 0; i < 100; i++) {
867 rt73usb_register_read(rt2x00dev, MAC_CSR0, &reg);
868 if (reg)
869 break;
870 msleep(1);
871 }
872
873 if (!reg) {
874 ERROR(rt2x00dev, "Unstable hardware.\n");
875 return -EBUSY;
876 }
877
878 /*
879 * Write firmware to device.
880 * We setup a seperate cache for this action,
881 * since we are going to write larger chunks of data
882 * then normally used cache size.
883 */
884 cache = kmalloc(CSR_CACHE_SIZE_FIRMWARE, GFP_KERNEL);
885 if (!cache) {
886 ERROR(rt2x00dev, "Failed to allocate firmware cache.\n");
887 return -ENOMEM;
888 }
889
890 for (i = 0; i < len; i += CSR_CACHE_SIZE_FIRMWARE) {
891 buflen = min_t(int, len - i, CSR_CACHE_SIZE_FIRMWARE);
892 timeout = REGISTER_TIMEOUT * (buflen / sizeof(u32));
893
894 memcpy(cache, ptr, buflen);
895
896 rt2x00usb_vendor_request(rt2x00dev, USB_MULTI_WRITE,
897 USB_VENDOR_REQUEST_OUT,
898 FIRMWARE_IMAGE_BASE + i, 0x0000,
899 cache, buflen, timeout);
900
901 ptr += buflen;
902 }
903
904 kfree(cache);
905
906 /*
907 * Send firmware request to device to load firmware,
908 * we need to specify a long timeout time.
909 */
910 status = rt2x00usb_vendor_request_sw(rt2x00dev, USB_DEVICE_MODE,
911 0x0000, USB_MODE_FIRMWARE,
912 REGISTER_TIMEOUT_FIRMWARE);
913 if (status < 0) {
914 ERROR(rt2x00dev, "Failed to write Firmware to device.\n");
915 return status;
916 }
917
918 rt73usb_disable_led(rt2x00dev);
919
920 return 0;
921}
922
923static int rt73usb_init_registers(struct rt2x00_dev *rt2x00dev)
924{
925 u32 reg;
926
927 rt73usb_register_read(rt2x00dev, TXRX_CSR0, &reg);
928 rt2x00_set_field32(&reg, TXRX_CSR0_AUTO_TX_SEQ, 1);
929 rt2x00_set_field32(&reg, TXRX_CSR0_DISABLE_RX, 0);
930 rt2x00_set_field32(&reg, TXRX_CSR0_TX_WITHOUT_WAITING, 0);
931 rt73usb_register_write(rt2x00dev, TXRX_CSR0, reg);
932
933 rt73usb_register_read(rt2x00dev, TXRX_CSR1, &reg);
934 rt2x00_set_field32(&reg, TXRX_CSR1_BBP_ID0, 47); /* CCK Signal */
935 rt2x00_set_field32(&reg, TXRX_CSR1_BBP_ID0_VALID, 1);
936 rt2x00_set_field32(&reg, TXRX_CSR1_BBP_ID1, 30); /* Rssi */
937 rt2x00_set_field32(&reg, TXRX_CSR1_BBP_ID1_VALID, 1);
938 rt2x00_set_field32(&reg, TXRX_CSR1_BBP_ID2, 42); /* OFDM Rate */
939 rt2x00_set_field32(&reg, TXRX_CSR1_BBP_ID2_VALID, 1);
940 rt2x00_set_field32(&reg, TXRX_CSR1_BBP_ID3, 30); /* Rssi */
941 rt2x00_set_field32(&reg, TXRX_CSR1_BBP_ID3_VALID, 1);
942 rt73usb_register_write(rt2x00dev, TXRX_CSR1, reg);
943
944 /*
945 * CCK TXD BBP registers
946 */
947 rt73usb_register_read(rt2x00dev, TXRX_CSR2, &reg);
948 rt2x00_set_field32(&reg, TXRX_CSR2_BBP_ID0, 13);
949 rt2x00_set_field32(&reg, TXRX_CSR2_BBP_ID0_VALID, 1);
950 rt2x00_set_field32(&reg, TXRX_CSR2_BBP_ID1, 12);
951 rt2x00_set_field32(&reg, TXRX_CSR2_BBP_ID1_VALID, 1);
952 rt2x00_set_field32(&reg, TXRX_CSR2_BBP_ID2, 11);
953 rt2x00_set_field32(&reg, TXRX_CSR2_BBP_ID2_VALID, 1);
954 rt2x00_set_field32(&reg, TXRX_CSR2_BBP_ID3, 10);
955 rt2x00_set_field32(&reg, TXRX_CSR2_BBP_ID3_VALID, 1);
956 rt73usb_register_write(rt2x00dev, TXRX_CSR2, reg);
957
958 /*
959 * OFDM TXD BBP registers
960 */
961 rt73usb_register_read(rt2x00dev, TXRX_CSR3, &reg);
962 rt2x00_set_field32(&reg, TXRX_CSR3_BBP_ID0, 7);
963 rt2x00_set_field32(&reg, TXRX_CSR3_BBP_ID0_VALID, 1);
964 rt2x00_set_field32(&reg, TXRX_CSR3_BBP_ID1, 6);
965 rt2x00_set_field32(&reg, TXRX_CSR3_BBP_ID1_VALID, 1);
966 rt2x00_set_field32(&reg, TXRX_CSR3_BBP_ID2, 5);
967 rt2x00_set_field32(&reg, TXRX_CSR3_BBP_ID2_VALID, 1);
968 rt73usb_register_write(rt2x00dev, TXRX_CSR3, reg);
969
970 rt73usb_register_read(rt2x00dev, TXRX_CSR7, &reg);
971 rt2x00_set_field32(&reg, TXRX_CSR7_ACK_CTS_6MBS, 59);
972 rt2x00_set_field32(&reg, TXRX_CSR7_ACK_CTS_9MBS, 53);
973 rt2x00_set_field32(&reg, TXRX_CSR7_ACK_CTS_12MBS, 49);
974 rt2x00_set_field32(&reg, TXRX_CSR7_ACK_CTS_18MBS, 46);
975 rt73usb_register_write(rt2x00dev, TXRX_CSR7, reg);
976
977 rt73usb_register_read(rt2x00dev, TXRX_CSR8, &reg);
978 rt2x00_set_field32(&reg, TXRX_CSR8_ACK_CTS_24MBS, 44);
979 rt2x00_set_field32(&reg, TXRX_CSR8_ACK_CTS_36MBS, 42);
980 rt2x00_set_field32(&reg, TXRX_CSR8_ACK_CTS_48MBS, 42);
981 rt2x00_set_field32(&reg, TXRX_CSR8_ACK_CTS_54MBS, 42);
982 rt73usb_register_write(rt2x00dev, TXRX_CSR8, reg);
983
984 rt73usb_register_write(rt2x00dev, TXRX_CSR15, 0x0000000f);
985
986 rt73usb_register_read(rt2x00dev, MAC_CSR6, &reg);
987 rt2x00_set_field32(&reg, MAC_CSR6_MAX_FRAME_UNIT, 0xfff);
988 rt73usb_register_write(rt2x00dev, MAC_CSR6, reg);
989
990 rt73usb_register_write(rt2x00dev, MAC_CSR10, 0x00000718);
991
992 if (rt2x00dev->ops->lib->set_device_state(rt2x00dev, STATE_AWAKE))
993 return -EBUSY;
994
995 rt73usb_register_write(rt2x00dev, MAC_CSR13, 0x00007f00);
996
997 /*
998 * Invalidate all Shared Keys (SEC_CSR0),
999 * and clear the Shared key Cipher algorithms (SEC_CSR1 & SEC_CSR5)
1000 */
1001 rt73usb_register_write(rt2x00dev, SEC_CSR0, 0x00000000);
1002 rt73usb_register_write(rt2x00dev, SEC_CSR1, 0x00000000);
1003 rt73usb_register_write(rt2x00dev, SEC_CSR5, 0x00000000);
1004
1005 reg = 0x000023b0;
1006 if (rt2x00_rf(&rt2x00dev->chip, RF5225) ||
1007 rt2x00_rf(&rt2x00dev->chip, RF2527))
1008 rt2x00_set_field32(&reg, PHY_CSR1_RF_RPI, 1);
1009 rt73usb_register_write(rt2x00dev, PHY_CSR1, reg);
1010
1011 rt73usb_register_write(rt2x00dev, PHY_CSR5, 0x00040a06);
1012 rt73usb_register_write(rt2x00dev, PHY_CSR6, 0x00080606);
1013 rt73usb_register_write(rt2x00dev, PHY_CSR7, 0x00000408);
1014
1015 rt73usb_register_read(rt2x00dev, AC_TXOP_CSR0, &reg);
1016 rt2x00_set_field32(&reg, AC_TXOP_CSR0_AC0_TX_OP, 0);
1017 rt2x00_set_field32(&reg, AC_TXOP_CSR0_AC1_TX_OP, 0);
1018 rt73usb_register_write(rt2x00dev, AC_TXOP_CSR0, reg);
1019
1020 rt73usb_register_read(rt2x00dev, AC_TXOP_CSR1, &reg);
1021 rt2x00_set_field32(&reg, AC_TXOP_CSR1_AC2_TX_OP, 192);
1022 rt2x00_set_field32(&reg, AC_TXOP_CSR1_AC3_TX_OP, 48);
1023 rt73usb_register_write(rt2x00dev, AC_TXOP_CSR1, reg);
1024
1025 rt73usb_register_read(rt2x00dev, MAC_CSR9, &reg);
1026 rt2x00_set_field32(&reg, MAC_CSR9_CW_SELECT, 0);
1027 rt73usb_register_write(rt2x00dev, MAC_CSR9, reg);
1028
6bb40dd1
ID		 1029 /*
1030 * Clear all beacons
1031 * For the Beacon base registers we only need to clear
1032 * the first byte since that byte contains the VALID and OWNER
1033 * bits which (when set to 0) will invalidate the entire beacon.
1034 */
1035 rt73usb_register_write(rt2x00dev, HW_BEACON_BASE0, 0);
1036 rt73usb_register_write(rt2x00dev, HW_BEACON_BASE1, 0);
1037 rt73usb_register_write(rt2x00dev, HW_BEACON_BASE2, 0);
1038 rt73usb_register_write(rt2x00dev, HW_BEACON_BASE3, 0);
1039
95ea3627
ID		 1040 /*
1041 * We must clear the error counters.
1042 * These registers are cleared on read,
1043 * so we may pass a useless variable to store the value.
1044 */
1045 rt73usb_register_read(rt2x00dev, STA_CSR0, &reg);
1046 rt73usb_register_read(rt2x00dev, STA_CSR1, &reg);
1047 rt73usb_register_read(rt2x00dev, STA_CSR2, &reg);
1048
1049 /*
1050 * Reset MAC and BBP registers.
1051 */
1052 rt73usb_register_read(rt2x00dev, MAC_CSR1, &reg);
1053 rt2x00_set_field32(&reg, MAC_CSR1_SOFT_RESET, 1);
1054 rt2x00_set_field32(&reg, MAC_CSR1_BBP_RESET, 1);
1055 rt73usb_register_write(rt2x00dev, MAC_CSR1, reg);
1056
1057 rt73usb_register_read(rt2x00dev, MAC_CSR1, &reg);
1058 rt2x00_set_field32(&reg, MAC_CSR1_SOFT_RESET, 0);
1059 rt2x00_set_field32(&reg, MAC_CSR1_BBP_RESET, 0);
1060 rt73usb_register_write(rt2x00dev, MAC_CSR1, reg);
1061
1062 rt73usb_register_read(rt2x00dev, MAC_CSR1, &reg);
1063 rt2x00_set_field32(&reg, MAC_CSR1_HOST_READY, 1);
1064 rt73usb_register_write(rt2x00dev, MAC_CSR1, reg);
1065
1066 return 0;
1067}
1068
1069static int rt73usb_init_bbp(struct rt2x00_dev *rt2x00dev)
1070{
1071 unsigned int i;
1072 u16 eeprom;
1073 u8 reg_id;
1074 u8 value;
1075
1076 for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
1077 rt73usb_bbp_read(rt2x00dev, 0, &value);
1078 if ((value != 0xff) && (value != 0x00))
1079 goto continue_csr_init;
1080 NOTICE(rt2x00dev, "Waiting for BBP register.\n");
1081 udelay(REGISTER_BUSY_DELAY);
1082 }
1083
1084 ERROR(rt2x00dev, "BBP register access failed, aborting.\n");
1085 return -EACCES;
1086
1087continue_csr_init:
1088 rt73usb_bbp_write(rt2x00dev, 3, 0x80);
1089 rt73usb_bbp_write(rt2x00dev, 15, 0x30);
1090 rt73usb_bbp_write(rt2x00dev, 21, 0xc8);
1091 rt73usb_bbp_write(rt2x00dev, 22, 0x38);
1092 rt73usb_bbp_write(rt2x00dev, 23, 0x06);
1093 rt73usb_bbp_write(rt2x00dev, 24, 0xfe);
1094 rt73usb_bbp_write(rt2x00dev, 25, 0x0a);
1095 rt73usb_bbp_write(rt2x00dev, 26, 0x0d);
1096 rt73usb_bbp_write(rt2x00dev, 32, 0x0b);
1097 rt73usb_bbp_write(rt2x00dev, 34, 0x12);
1098 rt73usb_bbp_write(rt2x00dev, 37, 0x07);
1099 rt73usb_bbp_write(rt2x00dev, 39, 0xf8);
1100 rt73usb_bbp_write(rt2x00dev, 41, 0x60);
1101 rt73usb_bbp_write(rt2x00dev, 53, 0x10);
1102 rt73usb_bbp_write(rt2x00dev, 54, 0x18);
1103 rt73usb_bbp_write(rt2x00dev, 60, 0x10);
1104 rt73usb_bbp_write(rt2x00dev, 61, 0x04);
1105 rt73usb_bbp_write(rt2x00dev, 62, 0x04);
1106 rt73usb_bbp_write(rt2x00dev, 75, 0xfe);
1107 rt73usb_bbp_write(rt2x00dev, 86, 0xfe);
1108 rt73usb_bbp_write(rt2x00dev, 88, 0xfe);
1109 rt73usb_bbp_write(rt2x00dev, 90, 0x0f);
1110 rt73usb_bbp_write(rt2x00dev, 99, 0x00);
1111 rt73usb_bbp_write(rt2x00dev, 102, 0x16);
1112 rt73usb_bbp_write(rt2x00dev, 107, 0x04);
1113
1114 DEBUG(rt2x00dev, "Start initialization from EEPROM...\n");
1115 for (i = 0; i < EEPROM_BBP_SIZE; i++) {
1116 rt2x00_eeprom_read(rt2x00dev, EEPROM_BBP_START + i, &eeprom);
1117
1118 if (eeprom != 0xffff && eeprom != 0x0000) {
1119 reg_id = rt2x00_get_field16(eeprom, EEPROM_BBP_REG_ID);
1120 value = rt2x00_get_field16(eeprom, EEPROM_BBP_VALUE);
1121 DEBUG(rt2x00dev, "BBP: 0x%02x, value: 0x%02x.\n",
1122 reg_id, value);
1123 rt73usb_bbp_write(rt2x00dev, reg_id, value);
1124 }
1125 }
1126 DEBUG(rt2x00dev, "...End initialization from EEPROM.\n");
1127
1128 return 0;
1129}
1130
1131/*
1132 * Device state switch handlers.
1133 */
1134static void rt73usb_toggle_rx(struct rt2x00_dev *rt2x00dev,
1135 enum dev_state state)
1136{
1137 u32 reg;
1138
1139 rt73usb_register_read(rt2x00dev, TXRX_CSR0, &reg);
1140 rt2x00_set_field32(&reg, TXRX_CSR0_DISABLE_RX,
1141 state == STATE_RADIO_RX_OFF);
1142 rt73usb_register_write(rt2x00dev, TXRX_CSR0, reg);
1143}
1144
1145static int rt73usb_enable_radio(struct rt2x00_dev *rt2x00dev)
1146{
1147 /*
1148 * Initialize all registers.
1149 */
1150 if (rt73usb_init_registers(rt2x00dev) ||
1151 rt73usb_init_bbp(rt2x00dev)) {
1152 ERROR(rt2x00dev, "Register initialization failed.\n");
1153 return -EIO;
1154 }
1155
95ea3627
ID		 1156 /*
1157 * Enable LED
1158 */
1159 rt73usb_enable_led(rt2x00dev);
1160
1161 return 0;
1162}
1163
1164static void rt73usb_disable_radio(struct rt2x00_dev *rt2x00dev)
1165{
1166 /*
1167 * Disable LED
1168 */
1169 rt73usb_disable_led(rt2x00dev);
1170
1171 rt73usb_register_write(rt2x00dev, MAC_CSR10, 0x00001818);
1172
1173 /*
1174 * Disable synchronisation.
1175 */
1176 rt73usb_register_write(rt2x00dev, TXRX_CSR9, 0);
1177
1178 rt2x00usb_disable_radio(rt2x00dev);
1179}
1180
1181static int rt73usb_set_state(struct rt2x00_dev *rt2x00dev, enum dev_state state)
1182{
1183 u32 reg;
1184 unsigned int i;
1185 char put_to_sleep;
1186 char current_state;
1187
1188 put_to_sleep = (state != STATE_AWAKE);
1189
1190 rt73usb_register_read(rt2x00dev, MAC_CSR12, &reg);
1191 rt2x00_set_field32(&reg, MAC_CSR12_FORCE_WAKEUP, !put_to_sleep);
1192 rt2x00_set_field32(&reg, MAC_CSR12_PUT_TO_SLEEP, put_to_sleep);
1193 rt73usb_register_write(rt2x00dev, MAC_CSR12, reg);
1194
1195 /*
1196 * Device is not guaranteed to be in the requested state yet.
1197 * We must wait until the register indicates that the
1198 * device has entered the correct state.
1199 */
1200 for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
1201 rt73usb_register_read(rt2x00dev, MAC_CSR12, &reg);
1202 current_state =
1203 rt2x00_get_field32(reg, MAC_CSR12_BBP_CURRENT_STATE);
1204 if (current_state == !put_to_sleep)
1205 return 0;
1206 msleep(10);
1207 }
1208
1209 NOTICE(rt2x00dev, "Device failed to enter state %d, "
1210 "current device state %d.\n", !put_to_sleep, current_state);
1211
1212 return -EBUSY;
1213}
1214
1215static int rt73usb_set_device_state(struct rt2x00_dev *rt2x00dev,
1216 enum dev_state state)
1217{
1218 int retval = 0;
1219
1220 switch (state) {
1221 case STATE_RADIO_ON:
1222 retval = rt73usb_enable_radio(rt2x00dev);
1223 break;
1224 case STATE_RADIO_OFF:
1225 rt73usb_disable_radio(rt2x00dev);
1226 break;
1227 case STATE_RADIO_RX_ON:
61667d8d
ID		 1228 case STATE_RADIO_RX_ON_LINK:
1229 rt73usb_toggle_rx(rt2x00dev, STATE_RADIO_RX_ON);
1230 break;
95ea3627 1231 case STATE_RADIO_RX_OFF:
61667d8d
ID		 1232 case STATE_RADIO_RX_OFF_LINK:
1233 rt73usb_toggle_rx(rt2x00dev, STATE_RADIO_RX_OFF);
95ea3627
ID		 1234 break;
1235 case STATE_DEEP_SLEEP:
1236 case STATE_SLEEP:
1237 case STATE_STANDBY:
1238 case STATE_AWAKE:
1239 retval = rt73usb_set_state(rt2x00dev, state);
1240 break;
1241 default:
1242 retval = -ENOTSUPP;
1243 break;
1244 }
1245
1246 return retval;
1247}
1248
1249/*
1250 * TX descriptor initialization
1251 */
1252static void rt73usb_write_tx_desc(struct rt2x00_dev *rt2x00dev,
dd3193e1 1253 struct sk_buff *skb,
181d6902 1254 struct txentry_desc *txdesc,
dd3193e1 1255 struct ieee80211_tx_control *control)
95ea3627 1256{
181d6902 1257 struct skb_frame_desc *skbdesc = get_skb_frame_desc(skb);
dd3193e1 1258 __le32 *txd = skbdesc->desc;
95ea3627
ID		 1259 u32 word;
1260
1261 /*
1262 * Start writing the descriptor words.
1263 */
1264 rt2x00_desc_read(txd, 1, &word);
181d6902
ID		 1265 rt2x00_set_field32(&word, TXD_W1_HOST_Q_ID, txdesc->queue);
1266 rt2x00_set_field32(&word, TXD_W1_AIFSN, txdesc->aifs);
1267 rt2x00_set_field32(&word, TXD_W1_CWMIN, txdesc->cw_min);
1268 rt2x00_set_field32(&word, TXD_W1_CWMAX, txdesc->cw_max);
95ea3627
ID		 1269 rt2x00_set_field32(&word, TXD_W1_IV_OFFSET, IEEE80211_HEADER);
1270 rt2x00_set_field32(&word, TXD_W1_HW_SEQUENCE, 1);
1271 rt2x00_desc_write(txd, 1, word);
1272
1273 rt2x00_desc_read(txd, 2, &word);
181d6902
ID		 1274 rt2x00_set_field32(&word, TXD_W2_PLCP_SIGNAL, txdesc->signal);
1275 rt2x00_set_field32(&word, TXD_W2_PLCP_SERVICE, txdesc->service);
1276 rt2x00_set_field32(&word, TXD_W2_PLCP_LENGTH_LOW, txdesc->length_low);
1277 rt2x00_set_field32(&word, TXD_W2_PLCP_LENGTH_HIGH, txdesc->length_high);
95ea3627
ID		 1278 rt2x00_desc_write(txd, 2, word);
1279
1280 rt2x00_desc_read(txd, 5, &word);
1281 rt2x00_set_field32(&word, TXD_W5_TX_POWER,
1282 TXPOWER_TO_DEV(control->power_level));
1283 rt2x00_set_field32(&word, TXD_W5_WAITING_DMA_DONE_INT, 1);
1284 rt2x00_desc_write(txd, 5, word);
1285
1286 rt2x00_desc_read(txd, 0, &word);
1287 rt2x00_set_field32(&word, TXD_W0_BURST,
181d6902 1288 test_bit(ENTRY_TXD_BURST, &txdesc->flags));
95ea3627
ID		 1289 rt2x00_set_field32(&word, TXD_W0_VALID, 1);
1290 rt2x00_set_field32(&word, TXD_W0_MORE_FRAG,
181d6902 1291 test_bit(ENTRY_TXD_MORE_FRAG, &txdesc->flags));
95ea3627 1292 rt2x00_set_field32(&word, TXD_W0_ACK,
181d6902 1293 test_bit(ENTRY_TXD_ACK, &txdesc->flags));
95ea3627 1294 rt2x00_set_field32(&word, TXD_W0_TIMESTAMP,
181d6902 1295 test_bit(ENTRY_TXD_REQ_TIMESTAMP, &txdesc->flags));
95ea3627 1296 rt2x00_set_field32(&word, TXD_W0_OFDM,
181d6902
ID		 1297 test_bit(ENTRY_TXD_OFDM_RATE, &txdesc->flags));
1298 rt2x00_set_field32(&word, TXD_W0_IFS, txdesc->ifs);
95ea3627
ID		 1299 rt2x00_set_field32(&word, TXD_W0_RETRY_MODE,
1300 !!(control->flags &
1301 IEEE80211_TXCTL_LONG_RETRY_LIMIT));
1302 rt2x00_set_field32(&word, TXD_W0_TKIP_MIC, 0);
dd3193e1 1303 rt2x00_set_field32(&word, TXD_W0_DATABYTE_COUNT, skbdesc->data_len);
95ea3627 1304 rt2x00_set_field32(&word, TXD_W0_BURST2,
181d6902 1305 test_bit(ENTRY_TXD_BURST, &txdesc->flags));
95ea3627
ID		 1306 rt2x00_set_field32(&word, TXD_W0_CIPHER_ALG, CIPHER_NONE);
1307 rt2x00_desc_write(txd, 0, word);
1308}
1309
dd9fa2d2 1310static int rt73usb_get_tx_data_len(struct rt2x00_dev *rt2x00dev,
b242e891 1311 struct sk_buff *skb)
dd9fa2d2
ID		 1312{
1313 int length;
1314
1315 /*
1316 * The length _must_ be a multiple of 4,
1317 * but it must _not_ be a multiple of the USB packet size.
1318 */
1319 length = roundup(skb->len, 4);
b242e891 1320 length += (4 * !(length % rt2x00dev->usb_maxpacket));
dd9fa2d2
ID		 1321
1322 return length;
1323}
1324
95ea3627
ID		 1325/*
1326 * TX data initialization
1327 */
1328static void rt73usb_kick_tx_queue(struct rt2x00_dev *rt2x00dev,
1329 unsigned int queue)
1330{
1331 u32 reg;
1332
1333 if (queue != IEEE80211_TX_QUEUE_BEACON)
1334 return;
1335
1336 /*
1337 * For Wi-Fi faily generated beacons between participating stations.
1338 * Set TBTT phase adaptive adjustment step to 8us (default 16us)
1339 */
1340 rt73usb_register_write(rt2x00dev, TXRX_CSR10, 0x00001008);
1341
1342 rt73usb_register_read(rt2x00dev, TXRX_CSR9, &reg);
1343 if (!rt2x00_get_field32(reg, TXRX_CSR9_BEACON_GEN)) {
1344 rt2x00_set_field32(&reg, TXRX_CSR9_BEACON_GEN, 1);
1345 rt73usb_register_write(rt2x00dev, TXRX_CSR9, reg);
1346 }
1347}
1348
1349/*
1350 * RX control handlers
1351 */
1352static int rt73usb_agc_to_rssi(struct rt2x00_dev *rt2x00dev, int rxd_w1)
1353{
1354 u16 eeprom;
1355 u8 offset;
1356 u8 lna;
1357
1358 lna = rt2x00_get_field32(rxd_w1, RXD_W1_RSSI_LNA);
1359 switch (lna) {
1360 case 3:
1361 offset = 90;
1362 break;
1363 case 2:
1364 offset = 74;
1365 break;
1366 case 1:
1367 offset = 64;
1368 break;
1369 default:
1370 return 0;
1371 }
1372
1373 if (rt2x00dev->rx_status.phymode == MODE_IEEE80211A) {
1374 if (test_bit(CONFIG_EXTERNAL_LNA_A, &rt2x00dev->flags)) {
1375 if (lna == 3 || lna == 2)
1376 offset += 10;
1377 } else {
1378 if (lna == 3)
1379 offset += 6;
1380 else if (lna == 2)
1381 offset += 8;
1382 }
1383
1384 rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_OFFSET_A, &eeprom);
1385 offset -= rt2x00_get_field16(eeprom, EEPROM_RSSI_OFFSET_A_1);
1386 } else {
1387 if (test_bit(CONFIG_EXTERNAL_LNA_BG, &rt2x00dev->flags))
1388 offset += 14;
1389
1390 rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_OFFSET_BG, &eeprom);
1391 offset -= rt2x00_get_field16(eeprom, EEPROM_RSSI_OFFSET_BG_1);
1392 }
1393
1394 return rt2x00_get_field32(rxd_w1, RXD_W1_RSSI_AGC) * 2 - offset;
1395}
1396
181d6902
ID		 1397static void rt73usb_fill_rxdone(struct queue_entry *entry,
1398 struct rxdone_entry_desc *rxdesc)
95ea3627 1399{
181d6902 1400 struct skb_frame_desc *skbdesc = get_skb_frame_desc(entry->skb);
4bd7c452 1401 __le32 *rxd = (__le32 *)entry->skb->data;
181d6902
ID		 1402 struct ieee80211_hdr *hdr =
1403 (struct ieee80211_hdr *)entry->skb->data + entry->queue->desc_size;
1404 int header_size = ieee80211_get_hdrlen(le16_to_cpu(hdr->frame_control));
95ea3627
ID		 1405 u32 word0;
1406 u32 word1;
1407
1408 rt2x00_desc_read(rxd, 0, &word0);
1409 rt2x00_desc_read(rxd, 1, &word1);
1410
181d6902 1411 rxdesc->flags = 0;
4150c572 1412 if (rt2x00_get_field32(word0, RXD_W0_CRC_ERROR))
181d6902 1413 rxdesc->flags |= RX_FLAG_FAILED_FCS_CRC;
95ea3627
ID		 1414
1415 /*
1416 * Obtain the status about this packet.
1417 */
181d6902
ID		 1418 rxdesc->signal = rt2x00_get_field32(word1, RXD_W1_SIGNAL);
1419 rxdesc->rssi = rt73usb_agc_to_rssi(entry->queue->rt2x00dev, word1);
1420 rxdesc->ofdm = rt2x00_get_field32(word0, RXD_W0_OFDM);
1421 rxdesc->size = rt2x00_get_field32(word0, RXD_W0_DATABYTE_COUNT);
1422 rxdesc->my_bss = !!rt2x00_get_field32(word0, RXD_W0_MY_BSS);
1423
1424 /*
1425 * The data behind the ieee80211 header must be
1426 * aligned on a 4 byte boundary.
1427 */
1428 if (header_size % 4 == 0) {
1429 skb_push(entry->skb, 2);
1430 memmove(entry->skb->data, entry->skb->data + 2,
1431 entry->skb->len - 2);
1432 }
95ea3627 1433
7d1de806
ID		 1434 /*
1435 * Set descriptor and data pointer.
1436 */
181d6902
ID		 1437 skbdesc->data = entry->skb->data + entry->queue->desc_size;
1438 skbdesc->data_len = entry->queue->data_size;
40561b84 1439 skbdesc->desc = entry->skb->data;
181d6902
ID		 1440 skbdesc->desc_len = entry->queue->desc_size;
1441
1442 /*
1443 * Remove descriptor from skb buffer and trim the whole thing
1444 * down to only contain data.
1445 */
1446 skb_pull(entry->skb, skbdesc->desc_len);
1447 skb_trim(entry->skb, rxdesc->size);
95ea3627
ID		 1448}
1449
1450/*
1451 * Device probe functions.
1452 */
1453static int rt73usb_validate_eeprom(struct rt2x00_dev *rt2x00dev)
1454{
1455 u16 word;
1456 u8 *mac;
1457 s8 value;
1458
1459 rt2x00usb_eeprom_read(rt2x00dev, rt2x00dev->eeprom, EEPROM_SIZE);
1460
1461 /*
1462 * Start validation of the data that has been read.
1463 */
1464 mac = rt2x00_eeprom_addr(rt2x00dev, EEPROM_MAC_ADDR_0);
1465 if (!is_valid_ether_addr(mac)) {
0795af57
JP		 1466 DECLARE_MAC_BUF(macbuf);
1467
95ea3627 1468 random_ether_addr(mac);
0795af57 1469 EEPROM(rt2x00dev, "MAC: %s\n", print_mac(macbuf, mac));
95ea3627
ID		 1470 }
1471
1472 rt2x00_eeprom_read(rt2x00dev, EEPROM_ANTENNA, &word);
1473 if (word == 0xffff) {
1474 rt2x00_set_field16(&word, EEPROM_ANTENNA_NUM, 2);
362f3b6b
ID		 1475 rt2x00_set_field16(&word, EEPROM_ANTENNA_TX_DEFAULT,
1476 ANTENNA_B);
1477 rt2x00_set_field16(&word, EEPROM_ANTENNA_RX_DEFAULT,
1478 ANTENNA_B);
95ea3627
ID		 1479 rt2x00_set_field16(&word, EEPROM_ANTENNA_FRAME_TYPE, 0);
1480 rt2x00_set_field16(&word, EEPROM_ANTENNA_DYN_TXAGC, 0);
1481 rt2x00_set_field16(&word, EEPROM_ANTENNA_HARDWARE_RADIO, 0);
1482 rt2x00_set_field16(&word, EEPROM_ANTENNA_RF_TYPE, RF5226);
1483 rt2x00_eeprom_write(rt2x00dev, EEPROM_ANTENNA, word);
1484 EEPROM(rt2x00dev, "Antenna: 0x%04x\n", word);
1485 }
1486
1487 rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC, &word);
1488 if (word == 0xffff) {
1489 rt2x00_set_field16(&word, EEPROM_NIC_EXTERNAL_LNA, 0);
1490 rt2x00_eeprom_write(rt2x00dev, EEPROM_NIC, word);
1491 EEPROM(rt2x00dev, "NIC: 0x%04x\n", word);
1492 }
1493
1494 rt2x00_eeprom_read(rt2x00dev, EEPROM_LED, &word);
1495 if (word == 0xffff) {
1496 rt2x00_set_field16(&word, EEPROM_LED_POLARITY_RDY_G, 0);
1497 rt2x00_set_field16(&word, EEPROM_LED_POLARITY_RDY_A, 0);
1498 rt2x00_set_field16(&word, EEPROM_LED_POLARITY_ACT, 0);
1499 rt2x00_set_field16(&word, EEPROM_LED_POLARITY_GPIO_0, 0);
1500 rt2x00_set_field16(&word, EEPROM_LED_POLARITY_GPIO_1, 0);
1501 rt2x00_set_field16(&word, EEPROM_LED_POLARITY_GPIO_2, 0);
1502 rt2x00_set_field16(&word, EEPROM_LED_POLARITY_GPIO_3, 0);
1503 rt2x00_set_field16(&word, EEPROM_LED_POLARITY_GPIO_4, 0);
1504 rt2x00_set_field16(&word, EEPROM_LED_LED_MODE,
1505 LED_MODE_DEFAULT);
1506 rt2x00_eeprom_write(rt2x00dev, EEPROM_LED, word);
1507 EEPROM(rt2x00dev, "Led: 0x%04x\n", word);
1508 }
1509
1510 rt2x00_eeprom_read(rt2x00dev, EEPROM_FREQ, &word);
1511 if (word == 0xffff) {
1512 rt2x00_set_field16(&word, EEPROM_FREQ_OFFSET, 0);
1513 rt2x00_set_field16(&word, EEPROM_FREQ_SEQ, 0);
1514 rt2x00_eeprom_write(rt2x00dev, EEPROM_FREQ, word);
1515 EEPROM(rt2x00dev, "Freq: 0x%04x\n", word);
1516 }
1517
1518 rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_OFFSET_BG, &word);
1519 if (word == 0xffff) {
1520 rt2x00_set_field16(&word, EEPROM_RSSI_OFFSET_BG_1, 0);
1521 rt2x00_set_field16(&word, EEPROM_RSSI_OFFSET_BG_2, 0);
1522 rt2x00_eeprom_write(rt2x00dev, EEPROM_RSSI_OFFSET_BG, word);
1523 EEPROM(rt2x00dev, "RSSI OFFSET BG: 0x%04x\n", word);
1524 } else {
1525 value = rt2x00_get_field16(word, EEPROM_RSSI_OFFSET_BG_1);
1526 if (value < -10 || value > 10)
1527 rt2x00_set_field16(&word, EEPROM_RSSI_OFFSET_BG_1, 0);
1528 value = rt2x00_get_field16(word, EEPROM_RSSI_OFFSET_BG_2);
1529 if (value < -10 || value > 10)
1530 rt2x00_set_field16(&word, EEPROM_RSSI_OFFSET_BG_2, 0);
1531 rt2x00_eeprom_write(rt2x00dev, EEPROM_RSSI_OFFSET_BG, word);
1532 }
1533
1534 rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_OFFSET_A, &word);
1535 if (word == 0xffff) {
1536 rt2x00_set_field16(&word, EEPROM_RSSI_OFFSET_A_1, 0);
1537 rt2x00_set_field16(&word, EEPROM_RSSI_OFFSET_A_2, 0);
1538 rt2x00_eeprom_write(rt2x00dev, EEPROM_RSSI_OFFSET_A, word);
1539 EEPROM(rt2x00dev, "RSSI OFFSET BG: 0x%04x\n", word);
1540 } else {
1541 value = rt2x00_get_field16(word, EEPROM_RSSI_OFFSET_A_1);
1542 if (value < -10 || value > 10)
1543 rt2x00_set_field16(&word, EEPROM_RSSI_OFFSET_A_1, 0);
1544 value = rt2x00_get_field16(word, EEPROM_RSSI_OFFSET_A_2);
1545 if (value < -10 || value > 10)
1546 rt2x00_set_field16(&word, EEPROM_RSSI_OFFSET_A_2, 0);
1547 rt2x00_eeprom_write(rt2x00dev, EEPROM_RSSI_OFFSET_A, word);
1548 }
1549
1550 return 0;
1551}
1552
1553static int rt73usb_init_eeprom(struct rt2x00_dev *rt2x00dev)
1554{
1555 u32 reg;
1556 u16 value;
1557 u16 eeprom;
1558
1559 /*
1560 * Read EEPROM word for configuration.
1561 */
1562 rt2x00_eeprom_read(rt2x00dev, EEPROM_ANTENNA, &eeprom);
1563
1564 /*
1565 * Identify RF chipset.
1566 */
1567 value = rt2x00_get_field16(eeprom, EEPROM_ANTENNA_RF_TYPE);
1568 rt73usb_register_read(rt2x00dev, MAC_CSR0, &reg);
1569 rt2x00_set_chip(rt2x00dev, RT2571, value, reg);
1570
755a957d 1571 if (!rt2x00_check_rev(&rt2x00dev->chip, 0x25730)) {
95ea3627
ID		 1572 ERROR(rt2x00dev, "Invalid RT chipset detected.\n");
1573 return -ENODEV;
1574 }
1575
1576 if (!rt2x00_rf(&rt2x00dev->chip, RF5226) &&
1577 !rt2x00_rf(&rt2x00dev->chip, RF2528) &&
1578 !rt2x00_rf(&rt2x00dev->chip, RF5225) &&
1579 !rt2x00_rf(&rt2x00dev->chip, RF2527)) {
1580 ERROR(rt2x00dev, "Invalid RF chipset detected.\n");
1581 return -ENODEV;
1582 }
1583
1584 /*
1585 * Identify default antenna configuration.
1586 */
addc81bd 1587 rt2x00dev->default_ant.tx =
95ea3627 1588 rt2x00_get_field16(eeprom, EEPROM_ANTENNA_TX_DEFAULT);
addc81bd 1589 rt2x00dev->default_ant.rx =
95ea3627
ID		 1590 rt2x00_get_field16(eeprom, EEPROM_ANTENNA_RX_DEFAULT);
1591
1592 /*
1593 * Read the Frame type.
1594 */
1595 if (rt2x00_get_field16(eeprom, EEPROM_ANTENNA_FRAME_TYPE))
1596 __set_bit(CONFIG_FRAME_TYPE, &rt2x00dev->flags);
1597
1598 /*
1599 * Read frequency offset.
1600 */
1601 rt2x00_eeprom_read(rt2x00dev, EEPROM_FREQ, &eeprom);
1602 rt2x00dev->freq_offset = rt2x00_get_field16(eeprom, EEPROM_FREQ_OFFSET);
1603
1604 /*
1605 * Read external LNA informations.
1606 */
1607 rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC, &eeprom);
1608
1609 if (rt2x00_get_field16(eeprom, EEPROM_NIC_EXTERNAL_LNA)) {
1610 __set_bit(CONFIG_EXTERNAL_LNA_A, &rt2x00dev->flags);
1611 __set_bit(CONFIG_EXTERNAL_LNA_BG, &rt2x00dev->flags);
1612 }
1613
1614 /*
1615 * Store led settings, for correct led behaviour.
1616 */
1617 rt2x00_eeprom_read(rt2x00dev, EEPROM_LED, &eeprom);
1618
1619 rt2x00_set_field16(&rt2x00dev->led_reg, MCU_LEDCS_LED_MODE,
1620 rt2x00dev->led_mode);
1621 rt2x00_set_field16(&rt2x00dev->led_reg, MCU_LEDCS_POLARITY_GPIO_0,
1622 rt2x00_get_field16(eeprom,
1623 EEPROM_LED_POLARITY_GPIO_0));
1624 rt2x00_set_field16(&rt2x00dev->led_reg, MCU_LEDCS_POLARITY_GPIO_1,
1625 rt2x00_get_field16(eeprom,
1626 EEPROM_LED_POLARITY_GPIO_1));
1627 rt2x00_set_field16(&rt2x00dev->led_reg, MCU_LEDCS_POLARITY_GPIO_2,
1628 rt2x00_get_field16(eeprom,
1629 EEPROM_LED_POLARITY_GPIO_2));
1630 rt2x00_set_field16(&rt2x00dev->led_reg, MCU_LEDCS_POLARITY_GPIO_3,
1631 rt2x00_get_field16(eeprom,
1632 EEPROM_LED_POLARITY_GPIO_3));
1633 rt2x00_set_field16(&rt2x00dev->led_reg, MCU_LEDCS_POLARITY_GPIO_4,
1634 rt2x00_get_field16(eeprom,
1635 EEPROM_LED_POLARITY_GPIO_4));
1636 rt2x00_set_field16(&rt2x00dev->led_reg, MCU_LEDCS_POLARITY_ACT,
1637 rt2x00_get_field16(eeprom, EEPROM_LED_POLARITY_ACT));
1638 rt2x00_set_field16(&rt2x00dev->led_reg, MCU_LEDCS_POLARITY_READY_BG,
1639 rt2x00_get_field16(eeprom,
1640 EEPROM_LED_POLARITY_RDY_G));
1641 rt2x00_set_field16(&rt2x00dev->led_reg, MCU_LEDCS_POLARITY_READY_A,
1642 rt2x00_get_field16(eeprom,
1643 EEPROM_LED_POLARITY_RDY_A));
1644
1645 return 0;
1646}
1647
1648/*
1649 * RF value list for RF2528
1650 * Supports: 2.4 GHz
1651 */
1652static const struct rf_channel rf_vals_bg_2528[] = {
1653 { 1, 0x00002c0c, 0x00000786, 0x00068255, 0x000fea0b },
1654 { 2, 0x00002c0c, 0x00000786, 0x00068255, 0x000fea1f },
1655 { 3, 0x00002c0c, 0x0000078a, 0x00068255, 0x000fea0b },
1656 { 4, 0x00002c0c, 0x0000078a, 0x00068255, 0x000fea1f },
1657 { 5, 0x00002c0c, 0x0000078e, 0x00068255, 0x000fea0b },
1658 { 6, 0x00002c0c, 0x0000078e, 0x00068255, 0x000fea1f },
1659 { 7, 0x00002c0c, 0x00000792, 0x00068255, 0x000fea0b },
1660 { 8, 0x00002c0c, 0x00000792, 0x00068255, 0x000fea1f },
1661 { 9, 0x00002c0c, 0x00000796, 0x00068255, 0x000fea0b },
1662 { 10, 0x00002c0c, 0x00000796, 0x00068255, 0x000fea1f },
1663 { 11, 0x00002c0c, 0x0000079a, 0x00068255, 0x000fea0b },
1664 { 12, 0x00002c0c, 0x0000079a, 0x00068255, 0x000fea1f },
1665 { 13, 0x00002c0c, 0x0000079e, 0x00068255, 0x000fea0b },
1666 { 14, 0x00002c0c, 0x000007a2, 0x00068255, 0x000fea13 },
1667};
1668
1669/*
1670 * RF value list for RF5226
1671 * Supports: 2.4 GHz & 5.2 GHz
1672 */
1673static const struct rf_channel rf_vals_5226[] = {
1674 { 1, 0x00002c0c, 0x00000786, 0x00068255, 0x000fea0b },
1675 { 2, 0x00002c0c, 0x00000786, 0x00068255, 0x000fea1f },
1676 { 3, 0x00002c0c, 0x0000078a, 0x00068255, 0x000fea0b },
1677 { 4, 0x00002c0c, 0x0000078a, 0x00068255, 0x000fea1f },
1678 { 5, 0x00002c0c, 0x0000078e, 0x00068255, 0x000fea0b },
1679 { 6, 0x00002c0c, 0x0000078e, 0x00068255, 0x000fea1f },
1680 { 7, 0x00002c0c, 0x00000792, 0x00068255, 0x000fea0b },
1681 { 8, 0x00002c0c, 0x00000792, 0x00068255, 0x000fea1f },
1682 { 9, 0x00002c0c, 0x00000796, 0x00068255, 0x000fea0b },
1683 { 10, 0x00002c0c, 0x00000796, 0x00068255, 0x000fea1f },
1684 { 11, 0x00002c0c, 0x0000079a, 0x00068255, 0x000fea0b },
1685 { 12, 0x00002c0c, 0x0000079a, 0x00068255, 0x000fea1f },
1686 { 13, 0x00002c0c, 0x0000079e, 0x00068255, 0x000fea0b },
1687 { 14, 0x00002c0c, 0x000007a2, 0x00068255, 0x000fea13 },
1688
1689 /* 802.11 UNI / HyperLan 2 */
1690 { 36, 0x00002c0c, 0x0000099a, 0x00098255, 0x000fea23 },
1691 { 40, 0x00002c0c, 0x000009a2, 0x00098255, 0x000fea03 },
1692 { 44, 0x00002c0c, 0x000009a6, 0x00098255, 0x000fea0b },
1693 { 48, 0x00002c0c, 0x000009aa, 0x00098255, 0x000fea13 },
1694 { 52, 0x00002c0c, 0x000009ae, 0x00098255, 0x000fea1b },
1695 { 56, 0x00002c0c, 0x000009b2, 0x00098255, 0x000fea23 },
1696 { 60, 0x00002c0c, 0x000009ba, 0x00098255, 0x000fea03 },
1697 { 64, 0x00002c0c, 0x000009be, 0x00098255, 0x000fea0b },
1698
1699 /* 802.11 HyperLan 2 */
1700 { 100, 0x00002c0c, 0x00000a2a, 0x000b8255, 0x000fea03 },
1701 { 104, 0x00002c0c, 0x00000a2e, 0x000b8255, 0x000fea0b },
1702 { 108, 0x00002c0c, 0x00000a32, 0x000b8255, 0x000fea13 },
1703 { 112, 0x00002c0c, 0x00000a36, 0x000b8255, 0x000fea1b },
1704 { 116, 0x00002c0c, 0x00000a3a, 0x000b8255, 0x000fea23 },
1705 { 120, 0x00002c0c, 0x00000a82, 0x000b8255, 0x000fea03 },
1706 { 124, 0x00002c0c, 0x00000a86, 0x000b8255, 0x000fea0b },
1707 { 128, 0x00002c0c, 0x00000a8a, 0x000b8255, 0x000fea13 },
1708 { 132, 0x00002c0c, 0x00000a8e, 0x000b8255, 0x000fea1b },
1709 { 136, 0x00002c0c, 0x00000a92, 0x000b8255, 0x000fea23 },
1710
1711 /* 802.11 UNII */
1712 { 140, 0x00002c0c, 0x00000a9a, 0x000b8255, 0x000fea03 },
1713 { 149, 0x00002c0c, 0x00000aa2, 0x000b8255, 0x000fea1f },
1714 { 153, 0x00002c0c, 0x00000aa6, 0x000b8255, 0x000fea27 },
1715 { 157, 0x00002c0c, 0x00000aae, 0x000b8255, 0x000fea07 },
1716 { 161, 0x00002c0c, 0x00000ab2, 0x000b8255, 0x000fea0f },
1717 { 165, 0x00002c0c, 0x00000ab6, 0x000b8255, 0x000fea17 },
1718
1719 /* MMAC(Japan)J52 ch 34,38,42,46 */
1720 { 34, 0x00002c0c, 0x0008099a, 0x000da255, 0x000d3a0b },
1721 { 38, 0x00002c0c, 0x0008099e, 0x000da255, 0x000d3a13 },
1722 { 42, 0x00002c0c, 0x000809a2, 0x000da255, 0x000d3a1b },
1723 { 46, 0x00002c0c, 0x000809a6, 0x000da255, 0x000d3a23 },
1724};
1725
1726/*
1727 * RF value list for RF5225 & RF2527
1728 * Supports: 2.4 GHz & 5.2 GHz
1729 */
1730static const struct rf_channel rf_vals_5225_2527[] = {
1731 { 1, 0x00002ccc, 0x00004786, 0x00068455, 0x000ffa0b },
1732 { 2, 0x00002ccc, 0x00004786, 0x00068455, 0x000ffa1f },
1733 { 3, 0x00002ccc, 0x0000478a, 0x00068455, 0x000ffa0b },
1734 { 4, 0x00002ccc, 0x0000478a, 0x00068455, 0x000ffa1f },
1735 { 5, 0x00002ccc, 0x0000478e, 0x00068455, 0x000ffa0b },
1736 { 6, 0x00002ccc, 0x0000478e, 0x00068455, 0x000ffa1f },
1737 { 7, 0x00002ccc, 0x00004792, 0x00068455, 0x000ffa0b },
1738 { 8, 0x00002ccc, 0x00004792, 0x00068455, 0x000ffa1f },
1739 { 9, 0x00002ccc, 0x00004796, 0x00068455, 0x000ffa0b },
1740 { 10, 0x00002ccc, 0x00004796, 0x00068455, 0x000ffa1f },
1741 { 11, 0x00002ccc, 0x0000479a, 0x00068455, 0x000ffa0b },
1742 { 12, 0x00002ccc, 0x0000479a, 0x00068455, 0x000ffa1f },
1743 { 13, 0x00002ccc, 0x0000479e, 0x00068455, 0x000ffa0b },
1744 { 14, 0x00002ccc, 0x000047a2, 0x00068455, 0x000ffa13 },
1745
1746 /* 802.11 UNI / HyperLan 2 */
1747 { 36, 0x00002ccc, 0x0000499a, 0x0009be55, 0x000ffa23 },
1748 { 40, 0x00002ccc, 0x000049a2, 0x0009be55, 0x000ffa03 },
1749 { 44, 0x00002ccc, 0x000049a6, 0x0009be55, 0x000ffa0b },
1750 { 48, 0x00002ccc, 0x000049aa, 0x0009be55, 0x000ffa13 },
1751 { 52, 0x00002ccc, 0x000049ae, 0x0009ae55, 0x000ffa1b },
1752 { 56, 0x00002ccc, 0x000049b2, 0x0009ae55, 0x000ffa23 },
1753 { 60, 0x00002ccc, 0x000049ba, 0x0009ae55, 0x000ffa03 },
1754 { 64, 0x00002ccc, 0x000049be, 0x0009ae55, 0x000ffa0b },
1755
1756 /* 802.11 HyperLan 2 */
1757 { 100, 0x00002ccc, 0x00004a2a, 0x000bae55, 0x000ffa03 },
1758 { 104, 0x00002ccc, 0x00004a2e, 0x000bae55, 0x000ffa0b },
1759 { 108, 0x00002ccc, 0x00004a32, 0x000bae55, 0x000ffa13 },
1760 { 112, 0x00002ccc, 0x00004a36, 0x000bae55, 0x000ffa1b },
1761 { 116, 0x00002ccc, 0x00004a3a, 0x000bbe55, 0x000ffa23 },
1762 { 120, 0x00002ccc, 0x00004a82, 0x000bbe55, 0x000ffa03 },
1763 { 124, 0x00002ccc, 0x00004a86, 0x000bbe55, 0x000ffa0b },
1764 { 128, 0x00002ccc, 0x00004a8a, 0x000bbe55, 0x000ffa13 },
1765 { 132, 0x00002ccc, 0x00004a8e, 0x000bbe55, 0x000ffa1b },
1766 { 136, 0x00002ccc, 0x00004a92, 0x000bbe55, 0x000ffa23 },
1767
1768 /* 802.11 UNII */
1769 { 140, 0x00002ccc, 0x00004a9a, 0x000bbe55, 0x000ffa03 },
1770 { 149, 0x00002ccc, 0x00004aa2, 0x000bbe55, 0x000ffa1f },
1771 { 153, 0x00002ccc, 0x00004aa6, 0x000bbe55, 0x000ffa27 },
1772 { 157, 0x00002ccc, 0x00004aae, 0x000bbe55, 0x000ffa07 },
1773 { 161, 0x00002ccc, 0x00004ab2, 0x000bbe55, 0x000ffa0f },
1774 { 165, 0x00002ccc, 0x00004ab6, 0x000bbe55, 0x000ffa17 },
1775
1776 /* MMAC(Japan)J52 ch 34,38,42,46 */
1777 { 34, 0x00002ccc, 0x0000499a, 0x0009be55, 0x000ffa0b },
1778 { 38, 0x00002ccc, 0x0000499e, 0x0009be55, 0x000ffa13 },
1779 { 42, 0x00002ccc, 0x000049a2, 0x0009be55, 0x000ffa1b },
1780 { 46, 0x00002ccc, 0x000049a6, 0x0009be55, 0x000ffa23 },
1781};
1782
1783
1784static void rt73usb_probe_hw_mode(struct rt2x00_dev *rt2x00dev)
1785{
1786 struct hw_mode_spec *spec = &rt2x00dev->spec;
1787 u8 *txpower;
1788 unsigned int i;
1789
1790 /*
1791 * Initialize all hw fields.
1792 */
1793 rt2x00dev->hw->flags =
1794 IEEE80211_HW_HOST_GEN_BEACON_TEMPLATE |
4150c572 1795 IEEE80211_HW_HOST_BROADCAST_PS_BUFFERING;
95ea3627
ID		 1796 rt2x00dev->hw->extra_tx_headroom = TXD_DESC_SIZE;
1797 rt2x00dev->hw->max_signal = MAX_SIGNAL;
1798 rt2x00dev->hw->max_rssi = MAX_RX_SSI;
1799 rt2x00dev->hw->queues = 5;
1800
1801 SET_IEEE80211_DEV(rt2x00dev->hw, &rt2x00dev_usb(rt2x00dev)->dev);
1802 SET_IEEE80211_PERM_ADDR(rt2x00dev->hw,
1803 rt2x00_eeprom_addr(rt2x00dev,
1804 EEPROM_MAC_ADDR_0));
1805
1806 /*
1807 * Convert tx_power array in eeprom.
1808 */
1809 txpower = rt2x00_eeprom_addr(rt2x00dev, EEPROM_TXPOWER_G_START);
1810 for (i = 0; i < 14; i++)
1811 txpower[i] = TXPOWER_FROM_DEV(txpower[i]);
1812
1813 /*
1814 * Initialize hw_mode information.
1815 */
1816 spec->num_modes = 2;
1817 spec->num_rates = 12;
1818 spec->tx_power_a = NULL;
1819 spec->tx_power_bg = txpower;
1820 spec->tx_power_default = DEFAULT_TXPOWER;
1821
1822 if (rt2x00_rf(&rt2x00dev->chip, RF2528)) {
1823 spec->num_channels = ARRAY_SIZE(rf_vals_bg_2528);
1824 spec->channels = rf_vals_bg_2528;
1825 } else if (rt2x00_rf(&rt2x00dev->chip, RF5226)) {
1826 spec->num_channels = ARRAY_SIZE(rf_vals_5226);
1827 spec->channels = rf_vals_5226;
1828 } else if (rt2x00_rf(&rt2x00dev->chip, RF2527)) {
1829 spec->num_channels = 14;
1830 spec->channels = rf_vals_5225_2527;
1831 } else if (rt2x00_rf(&rt2x00dev->chip, RF5225)) {
1832 spec->num_channels = ARRAY_SIZE(rf_vals_5225_2527);
1833 spec->channels = rf_vals_5225_2527;
1834 }
1835
1836 if (rt2x00_rf(&rt2x00dev->chip, RF5225) ||
1837 rt2x00_rf(&rt2x00dev->chip, RF5226)) {
1838 spec->num_modes = 3;
1839
1840 txpower = rt2x00_eeprom_addr(rt2x00dev, EEPROM_TXPOWER_A_START);
1841 for (i = 0; i < 14; i++)
1842 txpower[i] = TXPOWER_FROM_DEV(txpower[i]);
1843
1844 spec->tx_power_a = txpower;
1845 }
1846}
1847
1848static int rt73usb_probe_hw(struct rt2x00_dev *rt2x00dev)
1849{
1850 int retval;
1851
1852 /*
1853 * Allocate eeprom data.
1854 */
1855 retval = rt73usb_validate_eeprom(rt2x00dev);
1856 if (retval)
1857 return retval;
1858
1859 retval = rt73usb_init_eeprom(rt2x00dev);
1860 if (retval)
1861 return retval;
1862
1863 /*
1864 * Initialize hw specifications.
1865 */
1866 rt73usb_probe_hw_mode(rt2x00dev);
1867
1868 /*
9404ef34 1869 * This device requires firmware.
95ea3627 1870 */
066cb637 1871 __set_bit(DRIVER_REQUIRE_FIRMWARE, &rt2x00dev->flags);
9404ef34 1872 __set_bit(DRIVER_REQUIRE_FIRMWARE_CRC_ITU_T, &rt2x00dev->flags);
95ea3627
ID		 1873
1874 /*
1875 * Set the rssi offset.
1876 */
1877 rt2x00dev->rssi_offset = DEFAULT_RSSI_OFFSET;
1878
1879 return 0;
1880}
1881
1882/*
1883 * IEEE80211 stack callback functions.
1884 */
4150c572
JB		 1885static void rt73usb_configure_filter(struct ieee80211_hw *hw,
1886 unsigned int changed_flags,
1887 unsigned int *total_flags,
1888 int mc_count,
1889 struct dev_addr_list *mc_list)
1890{
1891 struct rt2x00_dev *rt2x00dev = hw->priv;
4150c572
JB		 1892 u32 reg;
1893
1894 /*
1895 * Mask off any flags we are going to ignore from
1896 * the total_flags field.
1897 */
1898 *total_flags &=
1899 FIF_ALLMULTI |
1900 FIF_FCSFAIL |
1901 FIF_PLCPFAIL |
1902 FIF_CONTROL |
1903 FIF_OTHER_BSS |
1904 FIF_PROMISC_IN_BSS;
1905
1906 /*
1907 * Apply some rules to the filters:
1908 * - Some filters imply different filters to be set.
1909 * - Some things we can't filter out at all.
4150c572
JB		 1910 */
1911 if (mc_count)
1912 *total_flags |= FIF_ALLMULTI;
5886d0db
ID		 1913 if (*total_flags & FIF_OTHER_BSS ||
1914 *total_flags & FIF_PROMISC_IN_BSS)
4150c572 1915 *total_flags |= FIF_PROMISC_IN_BSS | FIF_OTHER_BSS;
4150c572
JB		 1916
1917 /*
1918 * Check if there is any work left for us.
1919 */
3c4f2085 1920 if (rt2x00dev->packet_filter == *total_flags)
4150c572 1921 return;
3c4f2085 1922 rt2x00dev->packet_filter = *total_flags;
4150c572
JB		 1923
1924 /*
1925 * When in atomic context, reschedule and let rt2x00lib
1926 * call this function again.
1927 */
1928 if (in_atomic()) {
1929 queue_work(rt2x00dev->hw->workqueue, &rt2x00dev->filter_work);
1930 return;
1931 }
1932
1933 /*
1934 * Start configuration steps.
1935 * Note that the version error will always be dropped
1936 * and broadcast frames will always be accepted since
1937 * there is no filter for it at this time.
1938 */
1939 rt73usb_register_read(rt2x00dev, TXRX_CSR0, &reg);
1940 rt2x00_set_field32(&reg, TXRX_CSR0_DROP_CRC,
1941 !(*total_flags & FIF_FCSFAIL));
1942 rt2x00_set_field32(&reg, TXRX_CSR0_DROP_PHYSICAL,
1943 !(*total_flags & FIF_PLCPFAIL));
1944 rt2x00_set_field32(&reg, TXRX_CSR0_DROP_CONTROL,
1945 !(*total_flags & FIF_CONTROL));
1946 rt2x00_set_field32(&reg, TXRX_CSR0_DROP_NOT_TO_ME,
1947 !(*total_flags & FIF_PROMISC_IN_BSS));
1948 rt2x00_set_field32(&reg, TXRX_CSR0_DROP_TO_DS,
1949 !(*total_flags & FIF_PROMISC_IN_BSS));
1950 rt2x00_set_field32(&reg, TXRX_CSR0_DROP_VERSION_ERROR, 1);
1951 rt2x00_set_field32(&reg, TXRX_CSR0_DROP_MULTICAST,
1952 !(*total_flags & FIF_ALLMULTI));
1953 rt2x00_set_field32(&reg, TXRX_CSR0_DROP_BROADCAST, 0);
1954 rt2x00_set_field32(&reg, TXRX_CSR0_DROP_ACK_CTS, 1);
1955 rt73usb_register_write(rt2x00dev, TXRX_CSR0, reg);
1956}
1957
95ea3627
ID		 1958static int rt73usb_set_retry_limit(struct ieee80211_hw *hw,
1959 u32 short_retry, u32 long_retry)
1960{
1961 struct rt2x00_dev *rt2x00dev = hw->priv;
1962 u32 reg;
1963
1964 rt73usb_register_read(rt2x00dev, TXRX_CSR4, &reg);
1965 rt2x00_set_field32(&reg, TXRX_CSR4_LONG_RETRY_LIMIT, long_retry);
1966 rt2x00_set_field32(&reg, TXRX_CSR4_SHORT_RETRY_LIMIT, short_retry);
1967 rt73usb_register_write(rt2x00dev, TXRX_CSR4, reg);
1968
1969 return 0;
1970}
1971
1972#if 0
1973/*
1974 * Mac80211 demands get_tsf must be atomic.
1975 * This is not possible for rt73usb since all register access
1976 * functions require sleeping. Untill mac80211 no longer needs
1977 * get_tsf to be atomic, this function should be disabled.
1978 */
1979static u64 rt73usb_get_tsf(struct ieee80211_hw *hw)
1980{
1981 struct rt2x00_dev *rt2x00dev = hw->priv;
1982 u64 tsf;
1983 u32 reg;
1984
1985 rt73usb_register_read(rt2x00dev, TXRX_CSR13, &reg);
1986 tsf = (u64) rt2x00_get_field32(reg, TXRX_CSR13_HIGH_TSFTIMER) << 32;
1987 rt73usb_register_read(rt2x00dev, TXRX_CSR12, &reg);
1988 tsf |= rt2x00_get_field32(reg, TXRX_CSR12_LOW_TSFTIMER);
1989
1990 return tsf;
1991}
37894473
ID		 1992#else
1993#define rt73usb_get_tsf NULL
95ea3627
ID		 1994#endif
1995
1996static void rt73usb_reset_tsf(struct ieee80211_hw *hw)
1997{
1998 struct rt2x00_dev *rt2x00dev = hw->priv;
1999
2000 rt73usb_register_write(rt2x00dev, TXRX_CSR12, 0);
2001 rt73usb_register_write(rt2x00dev, TXRX_CSR13, 0);
2002}
2003
24845910 2004static int rt73usb_beacon_update(struct ieee80211_hw *hw, struct sk_buff *skb,
6bb40dd1 2005 struct ieee80211_tx_control *control)
95ea3627
ID		 2006{
2007 struct rt2x00_dev *rt2x00dev = hw->priv;
6bb40dd1 2008 struct rt2x00_intf *intf = vif_to_intf(control->vif);
181d6902 2009 struct skb_frame_desc *skbdesc;
6bb40dd1
ID		 2010 unsigned int beacon_base;
2011 unsigned int timeout;
95ea3627 2012
6bb40dd1
ID		 2013 if (unlikely(!intf->beacon))
2014 return -ENOBUFS;
95ea3627
ID		 2015
2016 /*
08992f7f 2017 * Add the descriptor in front of the skb.
95ea3627 2018 */
6bb40dd1
ID		 2019 skb_push(skb, intf->beacon->queue->desc_size);
2020 memset(skb->data, 0, intf->beacon->queue->desc_size);
c22eb87b 2021
08992f7f
ID		 2022 /*
2023 * Fill in skb descriptor
2024 */
181d6902
ID		 2025 skbdesc = get_skb_frame_desc(skb);
2026 memset(skbdesc, 0, sizeof(*skbdesc));
6bb40dd1
ID		 2027 skbdesc->data = skb->data + intf->beacon->queue->desc_size;
2028 skbdesc->data_len = skb->len - intf->beacon->queue->desc_size;
181d6902 2029 skbdesc->desc = skb->data;
6bb40dd1
ID		 2030 skbdesc->desc_len = intf->beacon->queue->desc_size;
2031 skbdesc->entry = intf->beacon;
08992f7f 2032
6bb40dd1
ID		 2033 /*
2034 * Just in case the ieee80211 doesn't set this,
2035 * but we need this queue set for the descriptor
2036 * initialization.
2037 */
2038 control->queue = IEEE80211_TX_QUEUE_BEACON;
08992f7f 2039 rt2x00lib_write_tx_desc(rt2x00dev, skb, control);
95ea3627
ID		 2040
2041 /*
2042 * Write entire beacon with descriptor to register,
2043 * and kick the beacon generator.
2044 */
6bb40dd1 2045 beacon_base = HW_BEACON_OFFSET(intf->beacon->entry_idx);
95ea3627
ID		 2046 timeout = REGISTER_TIMEOUT * (skb->len / sizeof(u32));
2047 rt2x00usb_vendor_request(rt2x00dev, USB_MULTI_WRITE,
6bb40dd1 2048 USB_VENDOR_REQUEST_OUT, beacon_base, 0,
95ea3627 2049 skb->data, skb->len, timeout);
6bb40dd1 2050 rt73usb_kick_tx_queue(rt2x00dev, control->queue);
95ea3627
ID		 2051
2052 return 0;
2053}
2054
2055static const struct ieee80211_ops rt73usb_mac80211_ops = {
2056 .tx = rt2x00mac_tx,
4150c572
JB		 2057 .start = rt2x00mac_start,
2058 .stop = rt2x00mac_stop,
95ea3627
ID		 2059 .add_interface = rt2x00mac_add_interface,
2060 .remove_interface = rt2x00mac_remove_interface,
2061 .config = rt2x00mac_config,
2062 .config_interface = rt2x00mac_config_interface,
4150c572 2063 .configure_filter = rt73usb_configure_filter,
95ea3627
ID		 2064 .get_stats = rt2x00mac_get_stats,
2065 .set_retry_limit = rt73usb_set_retry_limit,
471b3efd 2066 .bss_info_changed = rt2x00mac_bss_info_changed,
95ea3627
ID		 2067 .conf_tx = rt2x00mac_conf_tx,
2068 .get_tx_stats = rt2x00mac_get_tx_stats,
95ea3627 2069 .get_tsf = rt73usb_get_tsf,
95ea3627
ID		 2070 .reset_tsf = rt73usb_reset_tsf,
2071 .beacon_update = rt73usb_beacon_update,
2072};
2073
2074static const struct rt2x00lib_ops rt73usb_rt2x00_ops = {
2075 .probe_hw = rt73usb_probe_hw,
2076 .get_firmware_name = rt73usb_get_firmware_name,
2077 .load_firmware = rt73usb_load_firmware,
2078 .initialize = rt2x00usb_initialize,
2079 .uninitialize = rt2x00usb_uninitialize,
837e7f24
ID		 2080 .init_rxentry = rt2x00usb_init_rxentry,
2081 .init_txentry = rt2x00usb_init_txentry,
95ea3627
ID		 2082 .set_device_state = rt73usb_set_device_state,
2083 .link_stats = rt73usb_link_stats,
2084 .reset_tuner = rt73usb_reset_tuner,
2085 .link_tuner = rt73usb_link_tuner,
2086 .write_tx_desc = rt73usb_write_tx_desc,
2087 .write_tx_data = rt2x00usb_write_tx_data,
dd9fa2d2 2088 .get_tx_data_len = rt73usb_get_tx_data_len,
95ea3627
ID		 2089 .kick_tx_queue = rt73usb_kick_tx_queue,
2090 .fill_rxdone = rt73usb_fill_rxdone,
6bb40dd1 2091 .config_intf = rt73usb_config_intf,
5c58ee51 2092 .config_preamble = rt73usb_config_preamble,
95ea3627
ID		 2093 .config = rt73usb_config,
2094};
2095
181d6902
ID		 2096static const struct data_queue_desc rt73usb_queue_rx = {
2097 .entry_num = RX_ENTRIES,
2098 .data_size = DATA_FRAME_SIZE,
2099 .desc_size = RXD_DESC_SIZE,
2100 .priv_size = sizeof(struct queue_entry_priv_usb_rx),
2101};
2102
2103static const struct data_queue_desc rt73usb_queue_tx = {
2104 .entry_num = TX_ENTRIES,
2105 .data_size = DATA_FRAME_SIZE,
2106 .desc_size = TXD_DESC_SIZE,
2107 .priv_size = sizeof(struct queue_entry_priv_usb_tx),
2108};
2109
2110static const struct data_queue_desc rt73usb_queue_bcn = {
6bb40dd1 2111 .entry_num = 4 * BEACON_ENTRIES,
181d6902
ID		 2112 .data_size = MGMT_FRAME_SIZE,
2113 .desc_size = TXINFO_SIZE,
2114 .priv_size = sizeof(struct queue_entry_priv_usb_tx),
2115};
2116
95ea3627 2117static const struct rt2x00_ops rt73usb_ops = {
2360157c 2118 .name = KBUILD_MODNAME,
6bb40dd1
ID		 2119 .max_sta_intf = 1,
2120 .max_ap_intf = 4,
95ea3627
ID		 2121 .eeprom_size = EEPROM_SIZE,
2122 .rf_size = RF_SIZE,
181d6902
ID		 2123 .rx = &rt73usb_queue_rx,
2124 .tx = &rt73usb_queue_tx,
2125 .bcn = &rt73usb_queue_bcn,
95ea3627
ID		 2126 .lib = &rt73usb_rt2x00_ops,
2127 .hw = &rt73usb_mac80211_ops,
2128#ifdef CONFIG_RT2X00_LIB_DEBUGFS
2129 .debugfs = &rt73usb_rt2x00debug,
2130#endif /* CONFIG_RT2X00_LIB_DEBUGFS */
2131};
2132
2133/*
2134 * rt73usb module information.
2135 */
2136static struct usb_device_id rt73usb_device_table[] = {
2137 /* AboCom */
2138 { USB_DEVICE(0x07b8, 0xb21d), USB_DEVICE_DATA(&rt73usb_ops) },
2139 /* Askey */
2140 { USB_DEVICE(0x1690, 0x0722), USB_DEVICE_DATA(&rt73usb_ops) },
2141 /* ASUS */
2142 { USB_DEVICE(0x0b05, 0x1723), USB_DEVICE_DATA(&rt73usb_ops) },
2143 { USB_DEVICE(0x0b05, 0x1724), USB_DEVICE_DATA(&rt73usb_ops) },
2144 /* Belkin */
2145 { USB_DEVICE(0x050d, 0x7050), USB_DEVICE_DATA(&rt73usb_ops) },
2146 { USB_DEVICE(0x050d, 0x705a), USB_DEVICE_DATA(&rt73usb_ops) },
2147 { USB_DEVICE(0x050d, 0x905b), USB_DEVICE_DATA(&rt73usb_ops) },
1f06862e 2148 { USB_DEVICE(0x050d, 0x905c), USB_DEVICE_DATA(&rt73usb_ops) },
95ea3627
ID		 2149 /* Billionton */
2150 { USB_DEVICE(0x1631, 0xc019), USB_DEVICE_DATA(&rt73usb_ops) },
2151 /* Buffalo */
2152 { USB_DEVICE(0x0411, 0x00f4), USB_DEVICE_DATA(&rt73usb_ops) },
2153 /* CNet */
2154 { USB_DEVICE(0x1371, 0x9022), USB_DEVICE_DATA(&rt73usb_ops) },
2155 { USB_DEVICE(0x1371, 0x9032), USB_DEVICE_DATA(&rt73usb_ops) },
2156 /* Conceptronic */
2157 { USB_DEVICE(0x14b2, 0x3c22), USB_DEVICE_DATA(&rt73usb_ops) },
2158 /* D-Link */
2159 { USB_DEVICE(0x07d1, 0x3c03), USB_DEVICE_DATA(&rt73usb_ops) },
2160 { USB_DEVICE(0x07d1, 0x3c04), USB_DEVICE_DATA(&rt73usb_ops) },
2161 /* Gemtek */
2162 { USB_DEVICE(0x15a9, 0x0004), USB_DEVICE_DATA(&rt73usb_ops) },
2163 /* Gigabyte */
2164 { USB_DEVICE(0x1044, 0x8008), USB_DEVICE_DATA(&rt73usb_ops) },
2165 { USB_DEVICE(0x1044, 0x800a), USB_DEVICE_DATA(&rt73usb_ops) },
2166 /* Huawei-3Com */
2167 { USB_DEVICE(0x1472, 0x0009), USB_DEVICE_DATA(&rt73usb_ops) },
2168 /* Hercules */
2169 { USB_DEVICE(0x06f8, 0xe010), USB_DEVICE_DATA(&rt73usb_ops) },
2170 { USB_DEVICE(0x06f8, 0xe020), USB_DEVICE_DATA(&rt73usb_ops) },
2171 /* Linksys */
2172 { USB_DEVICE(0x13b1, 0x0020), USB_DEVICE_DATA(&rt73usb_ops) },
2173 { USB_DEVICE(0x13b1, 0x0023), USB_DEVICE_DATA(&rt73usb_ops) },
2174 /* MSI */
2175 { USB_DEVICE(0x0db0, 0x6877), USB_DEVICE_DATA(&rt73usb_ops) },
2176 { USB_DEVICE(0x0db0, 0x6874), USB_DEVICE_DATA(&rt73usb_ops) },
2177 { USB_DEVICE(0x0db0, 0xa861), USB_DEVICE_DATA(&rt73usb_ops) },
2178 { USB_DEVICE(0x0db0, 0xa874), USB_DEVICE_DATA(&rt73usb_ops) },
2179 /* Ralink */
2180 { USB_DEVICE(0x148f, 0x2573), USB_DEVICE_DATA(&rt73usb_ops) },
2181 { USB_DEVICE(0x148f, 0x2671), USB_DEVICE_DATA(&rt73usb_ops) },
2182 /* Qcom */
2183 { USB_DEVICE(0x18e8, 0x6196), USB_DEVICE_DATA(&rt73usb_ops) },
2184 { USB_DEVICE(0x18e8, 0x6229), USB_DEVICE_DATA(&rt73usb_ops) },
2185 { USB_DEVICE(0x18e8, 0x6238), USB_DEVICE_DATA(&rt73usb_ops) },
2186 /* Senao */
2187 { USB_DEVICE(0x1740, 0x7100), USB_DEVICE_DATA(&rt73usb_ops) },
2188 /* Sitecom */
2189 { USB_DEVICE(0x0df6, 0x9712), USB_DEVICE_DATA(&rt73usb_ops) },
2190 { USB_DEVICE(0x0df6, 0x90ac), USB_DEVICE_DATA(&rt73usb_ops) },
2191 /* Surecom */
2192 { USB_DEVICE(0x0769, 0x31f3), USB_DEVICE_DATA(&rt73usb_ops) },
2193 /* Planex */
2194 { USB_DEVICE(0x2019, 0xab01), USB_DEVICE_DATA(&rt73usb_ops) },
2195 { USB_DEVICE(0x2019, 0xab50), USB_DEVICE_DATA(&rt73usb_ops) },
2196 { 0, }
2197};
2198
2199MODULE_AUTHOR(DRV_PROJECT);
2200MODULE_VERSION(DRV_VERSION);
2201MODULE_DESCRIPTION("Ralink RT73 USB Wireless LAN driver.");
2202MODULE_SUPPORTED_DEVICE("Ralink RT2571W & RT2671 USB chipset based cards");
2203MODULE_DEVICE_TABLE(usb, rt73usb_device_table);
2204MODULE_FIRMWARE(FIRMWARE_RT2571);
2205MODULE_LICENSE("GPL");
2206
2207static struct usb_driver rt73usb_driver = {
2360157c 2208 .name = KBUILD_MODNAME,
95ea3627
ID		 2209 .id_table = rt73usb_device_table,
2210 .probe = rt2x00usb_probe,
2211 .disconnect = rt2x00usb_disconnect,
2212 .suspend = rt2x00usb_suspend,
2213 .resume = rt2x00usb_resume,
2214};
2215
2216static int __init rt73usb_init(void)
2217{
2218 return usb_register(&rt73usb_driver);
2219}
2220
2221static void __exit rt73usb_exit(void)
2222{
2223 usb_deregister(&rt73usb_driver);
2224}
2225
2226module_init(rt73usb_init);
2227module_exit(rt73usb_exit);
Linux kernel - Deliverables
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