projects / deliverable / linux.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
rt2x00: Move firmware checksumming to driver
[deliverable/linux.git] / drivers / net / wireless / rt2x00 / rt73usb.c
CommitLineData
95ea3627 1/*
811aa9ca 2 Copyright (C) 2004 - 2008 rt2x00 SourceForge Project
95ea3627
ID		 3 <http://rt2x00.serialmonkey.com>
4
5 This program is free software; you can redistribute it and/or modify
6 it under the terms of the GNU General Public License as published by
7 the Free Software Foundation; either version 2 of the License, or
8 (at your option) any later version.
9
10 This program is distributed in the hope that it will be useful,
11 but WITHOUT ANY WARRANTY; without even the implied warranty of
12 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 GNU General Public License for more details.
14
15 You should have received a copy of the GNU General Public License
16 along with this program; if not, write to the
17 Free Software Foundation, Inc.,
18 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
19 */
20
21/*
22 Module: rt73usb
23 Abstract: rt73usb device specific routines.
24 Supported chipsets: rt2571W & rt2671.
25 */
26
a7f3a06c 27#include <linux/crc-itu-t.h>
95ea3627
ID		 28#include <linux/delay.h>
29#include <linux/etherdevice.h>
30#include <linux/init.h>
31#include <linux/kernel.h>
32#include <linux/module.h>
33#include <linux/usb.h>
34
35#include "rt2x00.h"
36#include "rt2x00usb.h"
37#include "rt73usb.h"
38
39/*
40 * Register access.
41 * All access to the CSR registers will go through the methods
42 * rt73usb_register_read and rt73usb_register_write.
43 * BBP and RF register require indirect register access,
44 * and use the CSR registers BBPCSR and RFCSR to achieve this.
45 * These indirect registers work with busy bits,
46 * and we will try maximal REGISTER_BUSY_COUNT times to access
47 * the register while taking a REGISTER_BUSY_DELAY us delay
48 * between each attampt. When the busy bit is still set at that time,
49 * the access attempt is considered to have failed,
50 * and we will print an error.
3d82346c 51 * The _lock versions must be used if you already hold the usb_cache_mutex
95ea3627 52 */
0e14f6d3 53static inline void rt73usb_register_read(struct rt2x00_dev *rt2x00dev,
95ea3627
ID		 54 const unsigned int offset, u32 *value)
55{
56 __le32 reg;
57 rt2x00usb_vendor_request_buff(rt2x00dev, USB_MULTI_READ,
58 USB_VENDOR_REQUEST_IN, offset,
59 &reg, sizeof(u32), REGISTER_TIMEOUT);
60 *value = le32_to_cpu(reg);
61}
62
3d82346c
AB		 63static inline void rt73usb_register_read_lock(struct rt2x00_dev *rt2x00dev,
64 const unsigned int offset, u32 *value)
65{
66 __le32 reg;
67 rt2x00usb_vendor_req_buff_lock(rt2x00dev, USB_MULTI_READ,
68 USB_VENDOR_REQUEST_IN, offset,
69 &reg, sizeof(u32), REGISTER_TIMEOUT);
70 *value = le32_to_cpu(reg);
71}
72
0e14f6d3 73static inline void rt73usb_register_multiread(struct rt2x00_dev *rt2x00dev,
95ea3627
ID		 74 const unsigned int offset,
75 void *value, const u32 length)
76{
77 int timeout = REGISTER_TIMEOUT * (length / sizeof(u32));
78 rt2x00usb_vendor_request_buff(rt2x00dev, USB_MULTI_READ,
79 USB_VENDOR_REQUEST_IN, offset,
80 value, length, timeout);
81}
82
0e14f6d3 83static inline void rt73usb_register_write(struct rt2x00_dev *rt2x00dev,
95ea3627
ID		 84 const unsigned int offset, u32 value)
85{
86 __le32 reg = cpu_to_le32(value);
87 rt2x00usb_vendor_request_buff(rt2x00dev, USB_MULTI_WRITE,
88 USB_VENDOR_REQUEST_OUT, offset,
89 &reg, sizeof(u32), REGISTER_TIMEOUT);
90}
91
3d82346c
AB		 92static inline void rt73usb_register_write_lock(struct rt2x00_dev *rt2x00dev,
93 const unsigned int offset, u32 value)
94{
95 __le32 reg = cpu_to_le32(value);
96 rt2x00usb_vendor_req_buff_lock(rt2x00dev, USB_MULTI_WRITE,
97 USB_VENDOR_REQUEST_OUT, offset,
98 &reg, sizeof(u32), REGISTER_TIMEOUT);
99}
100
0e14f6d3 101static inline void rt73usb_register_multiwrite(struct rt2x00_dev *rt2x00dev,
95ea3627
ID		 102 const unsigned int offset,
103 void *value, const u32 length)
104{
105 int timeout = REGISTER_TIMEOUT * (length / sizeof(u32));
106 rt2x00usb_vendor_request_buff(rt2x00dev, USB_MULTI_WRITE,
107 USB_VENDOR_REQUEST_OUT, offset,
108 value, length, timeout);
109}
110
0e14f6d3 111static u32 rt73usb_bbp_check(struct rt2x00_dev *rt2x00dev)
95ea3627
ID		 112{
113 u32 reg;
114 unsigned int i;
115
116 for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
3d82346c 117 rt73usb_register_read_lock(rt2x00dev, PHY_CSR3, &reg);
95ea3627
ID		 118 if (!rt2x00_get_field32(reg, PHY_CSR3_BUSY))
119 break;
120 udelay(REGISTER_BUSY_DELAY);
121 }
122
123 return reg;
124}
125
0e14f6d3 126static void rt73usb_bbp_write(struct rt2x00_dev *rt2x00dev,
95ea3627
ID		 127 const unsigned int word, const u8 value)
128{
129 u32 reg;
130
3d82346c
AB		 131 mutex_lock(&rt2x00dev->usb_cache_mutex);
132
95ea3627
ID		 133 /*
134 * Wait until the BBP becomes ready.
135 */
136 reg = rt73usb_bbp_check(rt2x00dev);
137 if (rt2x00_get_field32(reg, PHY_CSR3_BUSY)) {
138 ERROR(rt2x00dev, "PHY_CSR3 register busy. Write failed.\n");
3d82346c 139 mutex_unlock(&rt2x00dev->usb_cache_mutex);
95ea3627
ID		 140 return;
141 }
142
143 /*
144 * Write the data into the BBP.
145 */
146 reg = 0;
147 rt2x00_set_field32(&reg, PHY_CSR3_VALUE, value);
148 rt2x00_set_field32(&reg, PHY_CSR3_REGNUM, word);
149 rt2x00_set_field32(&reg, PHY_CSR3_BUSY, 1);
150 rt2x00_set_field32(&reg, PHY_CSR3_READ_CONTROL, 0);
151
3d82346c
AB		 152 rt73usb_register_write_lock(rt2x00dev, PHY_CSR3, reg);
153 mutex_unlock(&rt2x00dev->usb_cache_mutex);
95ea3627
ID		 154}
155
0e14f6d3 156static void rt73usb_bbp_read(struct rt2x00_dev *rt2x00dev,
95ea3627
ID		 157 const unsigned int word, u8 *value)
158{
159 u32 reg;
160
3d82346c
AB		 161 mutex_lock(&rt2x00dev->usb_cache_mutex);
162
95ea3627
ID		 163 /*
164 * Wait until the BBP becomes ready.
165 */
166 reg = rt73usb_bbp_check(rt2x00dev);
167 if (rt2x00_get_field32(reg, PHY_CSR3_BUSY)) {
168 ERROR(rt2x00dev, "PHY_CSR3 register busy. Read failed.\n");
3d82346c 169 mutex_unlock(&rt2x00dev->usb_cache_mutex);
95ea3627
ID		 170 return;
171 }
172
173 /*
174 * Write the request into the BBP.
175 */
176 reg = 0;
177 rt2x00_set_field32(&reg, PHY_CSR3_REGNUM, word);
178 rt2x00_set_field32(&reg, PHY_CSR3_BUSY, 1);
179 rt2x00_set_field32(&reg, PHY_CSR3_READ_CONTROL, 1);
180
3d82346c 181 rt73usb_register_write_lock(rt2x00dev, PHY_CSR3, reg);
95ea3627
ID		 182
183 /*
184 * Wait until the BBP becomes ready.
185 */
186 reg = rt73usb_bbp_check(rt2x00dev);
187 if (rt2x00_get_field32(reg, PHY_CSR3_BUSY)) {
188 ERROR(rt2x00dev, "PHY_CSR3 register busy. Read failed.\n");
189 *value = 0xff;
190 return;
191 }
192
193 *value = rt2x00_get_field32(reg, PHY_CSR3_VALUE);
3d82346c 194 mutex_unlock(&rt2x00dev->usb_cache_mutex);
95ea3627
ID		 195}
196
0e14f6d3 197static void rt73usb_rf_write(struct rt2x00_dev *rt2x00dev,
95ea3627
ID		 198 const unsigned int word, const u32 value)
199{
200 u32 reg;
201 unsigned int i;
202
203 if (!word)
204 return;
205
3d82346c
AB		 206 mutex_lock(&rt2x00dev->usb_cache_mutex);
207
95ea3627 208 for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
3d82346c 209 rt73usb_register_read_lock(rt2x00dev, PHY_CSR4, &reg);
95ea3627
ID		 210 if (!rt2x00_get_field32(reg, PHY_CSR4_BUSY))
211 goto rf_write;
212 udelay(REGISTER_BUSY_DELAY);
213 }
214
3d82346c 215 mutex_unlock(&rt2x00dev->usb_cache_mutex);
95ea3627
ID		 216 ERROR(rt2x00dev, "PHY_CSR4 register busy. Write failed.\n");
217 return;
218
219rf_write:
220 reg = 0;
221 rt2x00_set_field32(&reg, PHY_CSR4_VALUE, value);
222
4f5af6eb
ID		 223 /*
224 * RF5225 and RF2527 contain 21 bits per RF register value,
225 * all others contain 20 bits.
226 */
227 rt2x00_set_field32(&reg, PHY_CSR4_NUMBER_OF_BITS,
ddc827f9
ID		 228 20 + (rt2x00_rf(&rt2x00dev->chip, RF5225) ||
229 rt2x00_rf(&rt2x00dev->chip, RF2527)));
95ea3627
ID		 230 rt2x00_set_field32(&reg, PHY_CSR4_IF_SELECT, 0);
231 rt2x00_set_field32(&reg, PHY_CSR4_BUSY, 1);
232
3d82346c 233 rt73usb_register_write_lock(rt2x00dev, PHY_CSR4, reg);
95ea3627 234 rt2x00_rf_write(rt2x00dev, word, value);
3d82346c 235 mutex_unlock(&rt2x00dev->usb_cache_mutex);
95ea3627
ID		 236}
237
238#ifdef CONFIG_RT2X00_LIB_DEBUGFS
239#define CSR_OFFSET(__word) ( CSR_REG_BASE + ((__word) * sizeof(u32)) )
240
0e14f6d3 241static void rt73usb_read_csr(struct rt2x00_dev *rt2x00dev,
95ea3627
ID		 242 const unsigned int word, u32 *data)
243{
244 rt73usb_register_read(rt2x00dev, CSR_OFFSET(word), data);
245}
246
0e14f6d3 247static void rt73usb_write_csr(struct rt2x00_dev *rt2x00dev,
95ea3627
ID		 248 const unsigned int word, u32 data)
249{
250 rt73usb_register_write(rt2x00dev, CSR_OFFSET(word), data);
251}
252
253static const struct rt2x00debug rt73usb_rt2x00debug = {
254 .owner = THIS_MODULE,
255 .csr = {
256 .read = rt73usb_read_csr,
257 .write = rt73usb_write_csr,
258 .word_size = sizeof(u32),
259 .word_count = CSR_REG_SIZE / sizeof(u32),
260 },
261 .eeprom = {
262 .read = rt2x00_eeprom_read,
263 .write = rt2x00_eeprom_write,
264 .word_size = sizeof(u16),
265 .word_count = EEPROM_SIZE / sizeof(u16),
266 },
267 .bbp = {
268 .read = rt73usb_bbp_read,
269 .write = rt73usb_bbp_write,
270 .word_size = sizeof(u8),
271 .word_count = BBP_SIZE / sizeof(u8),
272 },
273 .rf = {
274 .read = rt2x00_rf_read,
275 .write = rt73usb_rf_write,
276 .word_size = sizeof(u32),
277 .word_count = RF_SIZE / sizeof(u32),
278 },
279};
280#endif /* CONFIG_RT2X00_LIB_DEBUGFS */
281
a9450b70
ID		 282#ifdef CONFIG_RT73USB_LEDS
283static void rt73usb_led_brightness(struct led_classdev *led_cdev,
284 enum led_brightness brightness)
285{
286 struct rt2x00_led *led =
287 container_of(led_cdev, struct rt2x00_led, led_dev);
288 unsigned int enabled = brightness != LED_OFF;
289 unsigned int a_mode =
290 (enabled && led->rt2x00dev->curr_band == IEEE80211_BAND_5GHZ);
291 unsigned int bg_mode =
292 (enabled && led->rt2x00dev->curr_band == IEEE80211_BAND_2GHZ);
293
47b10cd1
ID		 294 if (in_atomic()) {
295 NOTICE(led->rt2x00dev,
61191fb2
LC		 296 "Ignoring LED brightness command for led %d\n",
297 led->type);
47b10cd1
ID		 298 return;
299 }
300
a9450b70
ID		 301 if (led->type == LED_TYPE_RADIO) {
302 rt2x00_set_field16(&led->rt2x00dev->led_mcu_reg,
303 MCU_LEDCS_RADIO_STATUS, enabled);
304
47b10cd1
ID		 305 rt2x00usb_vendor_request_sw(led->rt2x00dev, USB_LED_CONTROL,
306 0, led->rt2x00dev->led_mcu_reg,
307 REGISTER_TIMEOUT);
a9450b70
ID		 308 } else if (led->type == LED_TYPE_ASSOC) {
309 rt2x00_set_field16(&led->rt2x00dev->led_mcu_reg,
310 MCU_LEDCS_LINK_BG_STATUS, bg_mode);
311 rt2x00_set_field16(&led->rt2x00dev->led_mcu_reg,
312 MCU_LEDCS_LINK_A_STATUS, a_mode);
313
47b10cd1
ID		 314 rt2x00usb_vendor_request_sw(led->rt2x00dev, USB_LED_CONTROL,
315 0, led->rt2x00dev->led_mcu_reg,
316 REGISTER_TIMEOUT);
a9450b70
ID		 317 } else if (led->type == LED_TYPE_QUALITY) {
318 /*
319 * The brightness is divided into 6 levels (0 - 5),
320 * this means we need to convert the brightness
321 * argument into the matching level within that range.
322 */
47b10cd1
ID		 323 rt2x00usb_vendor_request_sw(led->rt2x00dev, USB_LED_CONTROL,
324 brightness / (LED_FULL / 6),
325 led->rt2x00dev->led_mcu_reg,
326 REGISTER_TIMEOUT);
a9450b70
ID		 327 }
328}
329#else
330#define rt73usb_led_brightness NULL
331#endif /* CONFIG_RT73USB_LEDS */
332
95ea3627
ID		 333/*
334 * Configuration handlers.
335 */
6bb40dd1
ID		 336static void rt73usb_config_intf(struct rt2x00_dev *rt2x00dev,
337 struct rt2x00_intf *intf,
338 struct rt2x00intf_conf *conf,
339 const unsigned int flags)
95ea3627 340{
6bb40dd1
ID		 341 unsigned int beacon_base;
342 u32 reg;
95ea3627 343
6bb40dd1
ID		 344 if (flags & CONFIG_UPDATE_TYPE) {
345 /*
346 * Clear current synchronisation setup.
347 * For the Beacon base registers we only need to clear
348 * the first byte since that byte contains the VALID and OWNER
349 * bits which (when set to 0) will invalidate the entire beacon.
350 */
351 beacon_base = HW_BEACON_OFFSET(intf->beacon->entry_idx);
6bb40dd1 352 rt73usb_register_write(rt2x00dev, beacon_base, 0);
95ea3627 353
6bb40dd1
ID		 354 /*
355 * Enable synchronisation.
356 */
357 rt73usb_register_read(rt2x00dev, TXRX_CSR9, &reg);
6bb40dd1
ID		 358 rt2x00_set_field32(&reg, TXRX_CSR9_TSF_SYNC, conf->sync);
359 rt73usb_register_write(rt2x00dev, TXRX_CSR9, reg);
360 }
95ea3627 361
6bb40dd1
ID		 362 if (flags & CONFIG_UPDATE_MAC) {
363 reg = le32_to_cpu(conf->mac[1]);
364 rt2x00_set_field32(&reg, MAC_CSR3_UNICAST_TO_ME_MASK, 0xff);
365 conf->mac[1] = cpu_to_le32(reg);
95ea3627 366
6bb40dd1
ID		 367 rt73usb_register_multiwrite(rt2x00dev, MAC_CSR2,
368 conf->mac, sizeof(conf->mac));
369 }
95ea3627 370
6bb40dd1
ID		 371 if (flags & CONFIG_UPDATE_BSSID) {
372 reg = le32_to_cpu(conf->bssid[1]);
373 rt2x00_set_field32(&reg, MAC_CSR5_BSS_ID_MASK, 3);
374 conf->bssid[1] = cpu_to_le32(reg);
95ea3627 375
6bb40dd1
ID		 376 rt73usb_register_multiwrite(rt2x00dev, MAC_CSR4,
377 conf->bssid, sizeof(conf->bssid));
378 }
95ea3627
ID		 379}
380
6bb40dd1
ID		 381static int rt73usb_config_preamble(struct rt2x00_dev *rt2x00dev,
382 const int short_preamble,
383 const int ack_timeout,
384 const int ack_consume_time)
95ea3627 385{
95ea3627 386 u32 reg;
95ea3627 387
5c58ee51 388 /*
6bb40dd1
ID		 389 * When in atomic context, we should let rt2x00lib
390 * try this configuration again later.
5c58ee51 391 */
6bb40dd1
ID		 392 if (in_atomic())
393 return -EAGAIN;
95ea3627
ID		 394
395 rt73usb_register_read(rt2x00dev, TXRX_CSR0, &reg);
5c58ee51 396 rt2x00_set_field32(&reg, TXRX_CSR0_RX_ACK_TIMEOUT, ack_timeout);
95ea3627
ID		 397 rt73usb_register_write(rt2x00dev, TXRX_CSR0, reg);
398
399 rt73usb_register_read(rt2x00dev, TXRX_CSR4, &reg);
4f5af6eb 400 rt2x00_set_field32(&reg, TXRX_CSR4_AUTORESPOND_PREAMBLE,
5c58ee51 401 !!short_preamble);
95ea3627 402 rt73usb_register_write(rt2x00dev, TXRX_CSR4, reg);
6bb40dd1
ID		 403
404 return 0;
95ea3627
ID		 405}
406
407static void rt73usb_config_phymode(struct rt2x00_dev *rt2x00dev,
5c58ee51 408 const int basic_rate_mask)
95ea3627 409{
5c58ee51 410 rt73usb_register_write(rt2x00dev, TXRX_CSR5, basic_rate_mask);
95ea3627
ID		 411}
412
5c58ee51
ID		 413static void rt73usb_config_channel(struct rt2x00_dev *rt2x00dev,
414 struct rf_channel *rf, const int txpower)
95ea3627
ID		 415{
416 u8 r3;
417 u8 r94;
418 u8 smart;
419
420 rt2x00_set_field32(&rf->rf3, RF3_TXPOWER, TXPOWER_TO_DEV(txpower));
421 rt2x00_set_field32(&rf->rf4, RF4_FREQ_OFFSET, rt2x00dev->freq_offset);
422
423 smart = !(rt2x00_rf(&rt2x00dev->chip, RF5225) ||
424 rt2x00_rf(&rt2x00dev->chip, RF2527));
425
426 rt73usb_bbp_read(rt2x00dev, 3, &r3);
427 rt2x00_set_field8(&r3, BBP_R3_SMART_MODE, smart);
428 rt73usb_bbp_write(rt2x00dev, 3, r3);
429
430 r94 = 6;
431 if (txpower > MAX_TXPOWER && txpower <= (MAX_TXPOWER + r94))
432 r94 += txpower - MAX_TXPOWER;
433 else if (txpower < MIN_TXPOWER && txpower >= (MIN_TXPOWER - r94))
434 r94 += txpower;
435 rt73usb_bbp_write(rt2x00dev, 94, r94);
436
437 rt73usb_rf_write(rt2x00dev, 1, rf->rf1);
438 rt73usb_rf_write(rt2x00dev, 2, rf->rf2);
439 rt73usb_rf_write(rt2x00dev, 3, rf->rf3 & ~0x00000004);
440 rt73usb_rf_write(rt2x00dev, 4, rf->rf4);
441
442 rt73usb_rf_write(rt2x00dev, 1, rf->rf1);
443 rt73usb_rf_write(rt2x00dev, 2, rf->rf2);
444 rt73usb_rf_write(rt2x00dev, 3, rf->rf3 | 0x00000004);
445 rt73usb_rf_write(rt2x00dev, 4, rf->rf4);
446
447 rt73usb_rf_write(rt2x00dev, 1, rf->rf1);
448 rt73usb_rf_write(rt2x00dev, 2, rf->rf2);
449 rt73usb_rf_write(rt2x00dev, 3, rf->rf3 & ~0x00000004);
450 rt73usb_rf_write(rt2x00dev, 4, rf->rf4);
451
452 udelay(10);
453}
454
95ea3627
ID		 455static void rt73usb_config_txpower(struct rt2x00_dev *rt2x00dev,
456 const int txpower)
457{
458 struct rf_channel rf;
459
460 rt2x00_rf_read(rt2x00dev, 1, &rf.rf1);
461 rt2x00_rf_read(rt2x00dev, 2, &rf.rf2);
462 rt2x00_rf_read(rt2x00dev, 3, &rf.rf3);
463 rt2x00_rf_read(rt2x00dev, 4, &rf.rf4);
464
5c58ee51 465 rt73usb_config_channel(rt2x00dev, &rf, txpower);
95ea3627
ID		 466}
467
468static void rt73usb_config_antenna_5x(struct rt2x00_dev *rt2x00dev,
addc81bd 469 struct antenna_setup *ant)
95ea3627
ID		 470{
471 u8 r3;
472 u8 r4;
473 u8 r77;
2676c94d 474 u8 temp;
95ea3627
ID		 475
476 rt73usb_bbp_read(rt2x00dev, 3, &r3);
477 rt73usb_bbp_read(rt2x00dev, 4, &r4);
478 rt73usb_bbp_read(rt2x00dev, 77, &r77);
479
480 rt2x00_set_field8(&r3, BBP_R3_SMART_MODE, 0);
481
e4cd2ff8
ID		 482 /*
483 * Configure the RX antenna.
484 */
addc81bd 485 switch (ant->rx) {
95ea3627 486 case ANTENNA_HW_DIVERSITY:
2676c94d
MN		 487 rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA_CONTROL, 2);
488 temp = !test_bit(CONFIG_FRAME_TYPE, &rt2x00dev->flags)
8318d78a 489 && (rt2x00dev->curr_band != IEEE80211_BAND_5GHZ);
2676c94d 490 rt2x00_set_field8(&r4, BBP_R4_RX_FRAME_END, temp);
95ea3627
ID		 491 break;
492 case ANTENNA_A:
2676c94d 493 rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA_CONTROL, 1);
95ea3627 494 rt2x00_set_field8(&r4, BBP_R4_RX_FRAME_END, 0);
8318d78a 495 if (rt2x00dev->curr_band == IEEE80211_BAND_5GHZ)
2676c94d
MN		 496 rt2x00_set_field8(&r77, BBP_R77_RX_ANTENNA, 0);
497 else
498 rt2x00_set_field8(&r77, BBP_R77_RX_ANTENNA, 3);
95ea3627 499 break;
39e75857
ID		 500 case ANTENNA_SW_DIVERSITY:
501 /*
502 * NOTE: We should never come here because rt2x00lib is
503 * supposed to catch this and send us the correct antenna
504 * explicitely. However we are nog going to bug about this.
505 * Instead, just default to antenna B.
506 */
95ea3627 507 case ANTENNA_B:
2676c94d 508 rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA_CONTROL, 1);
95ea3627 509 rt2x00_set_field8(&r4, BBP_R4_RX_FRAME_END, 0);
8318d78a 510 if (rt2x00dev->curr_band == IEEE80211_BAND_5GHZ)
2676c94d
MN		 511 rt2x00_set_field8(&r77, BBP_R77_RX_ANTENNA, 3);
512 else
513 rt2x00_set_field8(&r77, BBP_R77_RX_ANTENNA, 0);
95ea3627
ID		 514 break;
515 }
516
517 rt73usb_bbp_write(rt2x00dev, 77, r77);
518 rt73usb_bbp_write(rt2x00dev, 3, r3);
519 rt73usb_bbp_write(rt2x00dev, 4, r4);
520}
521
522static void rt73usb_config_antenna_2x(struct rt2x00_dev *rt2x00dev,
addc81bd 523 struct antenna_setup *ant)
95ea3627
ID		 524{
525 u8 r3;
526 u8 r4;
527 u8 r77;
528
529 rt73usb_bbp_read(rt2x00dev, 3, &r3);
530 rt73usb_bbp_read(rt2x00dev, 4, &r4);
531 rt73usb_bbp_read(rt2x00dev, 77, &r77);
532
533 rt2x00_set_field8(&r3, BBP_R3_SMART_MODE, 0);
534 rt2x00_set_field8(&r4, BBP_R4_RX_FRAME_END,
535 !test_bit(CONFIG_FRAME_TYPE, &rt2x00dev->flags));
536
e4cd2ff8
ID		 537 /*
538 * Configure the RX antenna.
539 */
addc81bd 540 switch (ant->rx) {
95ea3627 541 case ANTENNA_HW_DIVERSITY:
2676c94d 542 rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA_CONTROL, 2);
95ea3627
ID		 543 break;
544 case ANTENNA_A:
2676c94d
MN		 545 rt2x00_set_field8(&r77, BBP_R77_RX_ANTENNA, 3);
546 rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA_CONTROL, 1);
95ea3627 547 break;
39e75857
ID		 548 case ANTENNA_SW_DIVERSITY:
549 /*
550 * NOTE: We should never come here because rt2x00lib is
551 * supposed to catch this and send us the correct antenna
552 * explicitely. However we are nog going to bug about this.
553 * Instead, just default to antenna B.
554 */
95ea3627 555 case ANTENNA_B:
2676c94d
MN		 556 rt2x00_set_field8(&r77, BBP_R77_RX_ANTENNA, 0);
557 rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA_CONTROL, 1);
95ea3627
ID		 558 break;
559 }
560
561 rt73usb_bbp_write(rt2x00dev, 77, r77);
562 rt73usb_bbp_write(rt2x00dev, 3, r3);
563 rt73usb_bbp_write(rt2x00dev, 4, r4);
564}
565
566struct antenna_sel {
567 u8 word;
568 /*
569 * value[0] -> non-LNA
570 * value[1] -> LNA
571 */
572 u8 value[2];
573};
574
575static const struct antenna_sel antenna_sel_a[] = {
576 { 96, { 0x58, 0x78 } },
577 { 104, { 0x38, 0x48 } },
578 { 75, { 0xfe, 0x80 } },
579 { 86, { 0xfe, 0x80 } },
580 { 88, { 0xfe, 0x80 } },
581 { 35, { 0x60, 0x60 } },
582 { 97, { 0x58, 0x58 } },
583 { 98, { 0x58, 0x58 } },
584};
585
586static const struct antenna_sel antenna_sel_bg[] = {
587 { 96, { 0x48, 0x68 } },
588 { 104, { 0x2c, 0x3c } },
589 { 75, { 0xfe, 0x80 } },
590 { 86, { 0xfe, 0x80 } },
591 { 88, { 0xfe, 0x80 } },
592 { 35, { 0x50, 0x50 } },
593 { 97, { 0x48, 0x48 } },
594 { 98, { 0x48, 0x48 } },
595};
596
597static void rt73usb_config_antenna(struct rt2x00_dev *rt2x00dev,
addc81bd 598 struct antenna_setup *ant)
95ea3627
ID		 599{
600 const struct antenna_sel *sel;
601 unsigned int lna;
602 unsigned int i;
603 u32 reg;
604
8318d78a 605 if (rt2x00dev->curr_band == IEEE80211_BAND_5GHZ) {
95ea3627
ID		 606 sel = antenna_sel_a;
607 lna = test_bit(CONFIG_EXTERNAL_LNA_A, &rt2x00dev->flags);
95ea3627
ID		 608 } else {
609 sel = antenna_sel_bg;
610 lna = test_bit(CONFIG_EXTERNAL_LNA_BG, &rt2x00dev->flags);
95ea3627
ID		 611 }
612
2676c94d
MN		 613 for (i = 0; i < ARRAY_SIZE(antenna_sel_a); i++)
614 rt73usb_bbp_write(rt2x00dev, sel[i].word, sel[i].value[lna]);
615
616 rt73usb_register_read(rt2x00dev, PHY_CSR0, &reg);
617
ddc827f9 618 rt2x00_set_field32(&reg, PHY_CSR0_PA_PE_BG,
8318d78a 619 (rt2x00dev->curr_band == IEEE80211_BAND_2GHZ));
ddc827f9 620 rt2x00_set_field32(&reg, PHY_CSR0_PA_PE_A,
8318d78a 621 (rt2x00dev->curr_band == IEEE80211_BAND_5GHZ));
ddc827f9 622
95ea3627
ID		 623 rt73usb_register_write(rt2x00dev, PHY_CSR0, reg);
624
625 if (rt2x00_rf(&rt2x00dev->chip, RF5226) ||
626 rt2x00_rf(&rt2x00dev->chip, RF5225))
addc81bd 627 rt73usb_config_antenna_5x(rt2x00dev, ant);
95ea3627
ID		 628 else if (rt2x00_rf(&rt2x00dev->chip, RF2528) ||
629 rt2x00_rf(&rt2x00dev->chip, RF2527))
addc81bd 630 rt73usb_config_antenna_2x(rt2x00dev, ant);
95ea3627
ID		 631}
632
633static void rt73usb_config_duration(struct rt2x00_dev *rt2x00dev,
5c58ee51 634 struct rt2x00lib_conf *libconf)
95ea3627
ID		 635{
636 u32 reg;
637
638 rt73usb_register_read(rt2x00dev, MAC_CSR9, &reg);
5c58ee51 639 rt2x00_set_field32(&reg, MAC_CSR9_SLOT_TIME, libconf->slot_time);
95ea3627
ID		 640 rt73usb_register_write(rt2x00dev, MAC_CSR9, reg);
641
642 rt73usb_register_read(rt2x00dev, MAC_CSR8, &reg);
5c58ee51 643 rt2x00_set_field32(&reg, MAC_CSR8_SIFS, libconf->sifs);
95ea3627 644 rt2x00_set_field32(&reg, MAC_CSR8_SIFS_AFTER_RX_OFDM, 3);
5c58ee51 645 rt2x00_set_field32(&reg, MAC_CSR8_EIFS, libconf->eifs);
95ea3627
ID		 646 rt73usb_register_write(rt2x00dev, MAC_CSR8, reg);
647
648 rt73usb_register_read(rt2x00dev, TXRX_CSR0, &reg);
649 rt2x00_set_field32(&reg, TXRX_CSR0_TSF_OFFSET, IEEE80211_HEADER);
650 rt73usb_register_write(rt2x00dev, TXRX_CSR0, reg);
651
652 rt73usb_register_read(rt2x00dev, TXRX_CSR4, &reg);
653 rt2x00_set_field32(&reg, TXRX_CSR4_AUTORESPOND_ENABLE, 1);
654 rt73usb_register_write(rt2x00dev, TXRX_CSR4, reg);
655
656 rt73usb_register_read(rt2x00dev, TXRX_CSR9, &reg);
5c58ee51
ID		 657 rt2x00_set_field32(&reg, TXRX_CSR9_BEACON_INTERVAL,
658 libconf->conf->beacon_int * 16);
95ea3627
ID		 659 rt73usb_register_write(rt2x00dev, TXRX_CSR9, reg);
660}
661
662static void rt73usb_config(struct rt2x00_dev *rt2x00dev,
6bb40dd1
ID		 663 struct rt2x00lib_conf *libconf,
664 const unsigned int flags)
95ea3627 665{
95ea3627 666 if (flags & CONFIG_UPDATE_PHYMODE)
5c58ee51 667 rt73usb_config_phymode(rt2x00dev, libconf->basic_rates);
95ea3627 668 if (flags & CONFIG_UPDATE_CHANNEL)
5c58ee51
ID		 669 rt73usb_config_channel(rt2x00dev, &libconf->rf,
670 libconf->conf->power_level);
95ea3627 671 if ((flags & CONFIG_UPDATE_TXPOWER) && !(flags & CONFIG_UPDATE_CHANNEL))
5c58ee51 672 rt73usb_config_txpower(rt2x00dev, libconf->conf->power_level);
95ea3627 673 if (flags & CONFIG_UPDATE_ANTENNA)
addc81bd 674 rt73usb_config_antenna(rt2x00dev, &libconf->ant);
95ea3627 675 if (flags & (CONFIG_UPDATE_SLOT_TIME | CONFIG_UPDATE_BEACON_INT))
5c58ee51 676 rt73usb_config_duration(rt2x00dev, libconf);
95ea3627
ID		 677}
678
95ea3627
ID		 679/*
680 * Link tuning
681 */
ebcf26da
ID		 682static void rt73usb_link_stats(struct rt2x00_dev *rt2x00dev,
683 struct link_qual *qual)
95ea3627
ID		 684{
685 u32 reg;
686
687 /*
688 * Update FCS error count from register.
689 */
690 rt73usb_register_read(rt2x00dev, STA_CSR0, &reg);
ebcf26da 691 qual->rx_failed = rt2x00_get_field32(reg, STA_CSR0_FCS_ERROR);
95ea3627
ID		 692
693 /*
694 * Update False CCA count from register.
695 */
696 rt73usb_register_read(rt2x00dev, STA_CSR1, &reg);
ebcf26da 697 qual->false_cca = rt2x00_get_field32(reg, STA_CSR1_FALSE_CCA_ERROR);
95ea3627
ID		 698}
699
700static void rt73usb_reset_tuner(struct rt2x00_dev *rt2x00dev)
701{
702 rt73usb_bbp_write(rt2x00dev, 17, 0x20);
703 rt2x00dev->link.vgc_level = 0x20;
704}
705
706static void rt73usb_link_tuner(struct rt2x00_dev *rt2x00dev)
707{
708 int rssi = rt2x00_get_link_rssi(&rt2x00dev->link);
709 u8 r17;
710 u8 up_bound;
711 u8 low_bound;
712
95ea3627
ID		 713 rt73usb_bbp_read(rt2x00dev, 17, &r17);
714
715 /*
716 * Determine r17 bounds.
717 */
8318d78a 718 if (rt2x00dev->rx_status.band == IEEE80211_BAND_5GHZ) {
95ea3627
ID		 719 low_bound = 0x28;
720 up_bound = 0x48;
721
722 if (test_bit(CONFIG_EXTERNAL_LNA_A, &rt2x00dev->flags)) {
723 low_bound += 0x10;
724 up_bound += 0x10;
725 }
726 } else {
727 if (rssi > -82) {
728 low_bound = 0x1c;
729 up_bound = 0x40;
730 } else if (rssi > -84) {
731 low_bound = 0x1c;
732 up_bound = 0x20;
733 } else {
734 low_bound = 0x1c;
735 up_bound = 0x1c;
736 }
737
738 if (test_bit(CONFIG_EXTERNAL_LNA_BG, &rt2x00dev->flags)) {
739 low_bound += 0x14;
740 up_bound += 0x10;
741 }
742 }
743
6bb40dd1
ID		 744 /*
745 * If we are not associated, we should go straight to the
746 * dynamic CCA tuning.
747 */
748 if (!rt2x00dev->intf_associated)
749 goto dynamic_cca_tune;
750
95ea3627
ID		 751 /*
752 * Special big-R17 for very short distance
753 */
754 if (rssi > -35) {
755 if (r17 != 0x60)
756 rt73usb_bbp_write(rt2x00dev, 17, 0x60);
757 return;
758 }
759
760 /*
761 * Special big-R17 for short distance
762 */
763 if (rssi >= -58) {
764 if (r17 != up_bound)
765 rt73usb_bbp_write(rt2x00dev, 17, up_bound);
766 return;
767 }
768
769 /*
770 * Special big-R17 for middle-short distance
771 */
772 if (rssi >= -66) {
773 low_bound += 0x10;
774 if (r17 != low_bound)
775 rt73usb_bbp_write(rt2x00dev, 17, low_bound);
776 return;
777 }
778
779 /*
780 * Special mid-R17 for middle distance
781 */
782 if (rssi >= -74) {
783 if (r17 != (low_bound + 0x10))
784 rt73usb_bbp_write(rt2x00dev, 17, low_bound + 0x08);
785 return;
786 }
787
788 /*
789 * Special case: Change up_bound based on the rssi.
790 * Lower up_bound when rssi is weaker then -74 dBm.
791 */
792 up_bound -= 2 * (-74 - rssi);
793 if (low_bound > up_bound)
794 up_bound = low_bound;
795
796 if (r17 > up_bound) {
797 rt73usb_bbp_write(rt2x00dev, 17, up_bound);
798 return;
799 }
800
6bb40dd1
ID		 801dynamic_cca_tune:
802
95ea3627
ID		 803 /*
804 * r17 does not yet exceed upper limit, continue and base
805 * the r17 tuning on the false CCA count.
806 */
ebcf26da 807 if (rt2x00dev->link.qual.false_cca > 512 && r17 < up_bound) {
95ea3627
ID		 808 r17 += 4;
809 if (r17 > up_bound)
810 r17 = up_bound;
811 rt73usb_bbp_write(rt2x00dev, 17, r17);
ebcf26da 812 } else if (rt2x00dev->link.qual.false_cca < 100 && r17 > low_bound) {
95ea3627
ID		 813 r17 -= 4;
814 if (r17 < low_bound)
815 r17 = low_bound;
816 rt73usb_bbp_write(rt2x00dev, 17, r17);
817 }
818}
819
820/*
a7f3a06c 821 * Firmware functions
95ea3627
ID		 822 */
823static char *rt73usb_get_firmware_name(struct rt2x00_dev *rt2x00dev)
824{
825 return FIRMWARE_RT2571;
826}
827
a7f3a06c
ID		 828static u16 rt73usb_get_firmware_crc(void *data, const size_t len)
829{
830 u16 crc;
831
832 /*
833 * Use the crc itu-t algorithm.
834 * The last 2 bytes in the firmware array are the crc checksum itself,
835 * this means that we should never pass those 2 bytes to the crc
836 * algorithm.
837 */
838 crc = crc_itu_t(0, data, len - 2);
839 crc = crc_itu_t_byte(crc, 0);
840 crc = crc_itu_t_byte(crc, 0);
841
842 return crc;
843}
844
95ea3627
ID		 845static int rt73usb_load_firmware(struct rt2x00_dev *rt2x00dev, void *data,
846 const size_t len)
847{
848 unsigned int i;
849 int status;
850 u32 reg;
851 char *ptr = data;
852 char *cache;
853 int buflen;
854 int timeout;
855
856 /*
857 * Wait for stable hardware.
858 */
859 for (i = 0; i < 100; i++) {
860 rt73usb_register_read(rt2x00dev, MAC_CSR0, &reg);
861 if (reg)
862 break;
863 msleep(1);
864 }
865
866 if (!reg) {
867 ERROR(rt2x00dev, "Unstable hardware.\n");
868 return -EBUSY;
869 }
870
871 /*
872 * Write firmware to device.
873 * We setup a seperate cache for this action,
874 * since we are going to write larger chunks of data
875 * then normally used cache size.
876 */
877 cache = kmalloc(CSR_CACHE_SIZE_FIRMWARE, GFP_KERNEL);
878 if (!cache) {
879 ERROR(rt2x00dev, "Failed to allocate firmware cache.\n");
880 return -ENOMEM;
881 }
882
883 for (i = 0; i < len; i += CSR_CACHE_SIZE_FIRMWARE) {
884 buflen = min_t(int, len - i, CSR_CACHE_SIZE_FIRMWARE);
885 timeout = REGISTER_TIMEOUT * (buflen / sizeof(u32));
886
887 memcpy(cache, ptr, buflen);
888
889 rt2x00usb_vendor_request(rt2x00dev, USB_MULTI_WRITE,
890 USB_VENDOR_REQUEST_OUT,
3b640f21 891 FIRMWARE_IMAGE_BASE + i, 0,
95ea3627
ID		 892 cache, buflen, timeout);
893
894 ptr += buflen;
895 }
896
897 kfree(cache);
898
899 /*
900 * Send firmware request to device to load firmware,
901 * we need to specify a long timeout time.
902 */
903 status = rt2x00usb_vendor_request_sw(rt2x00dev, USB_DEVICE_MODE,
3b640f21 904 0, USB_MODE_FIRMWARE,
95ea3627
ID		 905 REGISTER_TIMEOUT_FIRMWARE);
906 if (status < 0) {
907 ERROR(rt2x00dev, "Failed to write Firmware to device.\n");
908 return status;
909 }
910
95ea3627
ID		 911 return 0;
912}
913
a7f3a06c
ID		 914/*
915 * Initialization functions.
916 */
95ea3627
ID		 917static int rt73usb_init_registers(struct rt2x00_dev *rt2x00dev)
918{
919 u32 reg;
920
921 rt73usb_register_read(rt2x00dev, TXRX_CSR0, &reg);
922 rt2x00_set_field32(&reg, TXRX_CSR0_AUTO_TX_SEQ, 1);
923 rt2x00_set_field32(&reg, TXRX_CSR0_DISABLE_RX, 0);
924 rt2x00_set_field32(&reg, TXRX_CSR0_TX_WITHOUT_WAITING, 0);
925 rt73usb_register_write(rt2x00dev, TXRX_CSR0, reg);
926
927 rt73usb_register_read(rt2x00dev, TXRX_CSR1, &reg);
928 rt2x00_set_field32(&reg, TXRX_CSR1_BBP_ID0, 47); /* CCK Signal */
929 rt2x00_set_field32(&reg, TXRX_CSR1_BBP_ID0_VALID, 1);
930 rt2x00_set_field32(&reg, TXRX_CSR1_BBP_ID1, 30); /* Rssi */
931 rt2x00_set_field32(&reg, TXRX_CSR1_BBP_ID1_VALID, 1);
932 rt2x00_set_field32(&reg, TXRX_CSR1_BBP_ID2, 42); /* OFDM Rate */
933 rt2x00_set_field32(&reg, TXRX_CSR1_BBP_ID2_VALID, 1);
934 rt2x00_set_field32(&reg, TXRX_CSR1_BBP_ID3, 30); /* Rssi */
935 rt2x00_set_field32(&reg, TXRX_CSR1_BBP_ID3_VALID, 1);
936 rt73usb_register_write(rt2x00dev, TXRX_CSR1, reg);
937
938 /*
939 * CCK TXD BBP registers
940 */
941 rt73usb_register_read(rt2x00dev, TXRX_CSR2, &reg);
942 rt2x00_set_field32(&reg, TXRX_CSR2_BBP_ID0, 13);
943 rt2x00_set_field32(&reg, TXRX_CSR2_BBP_ID0_VALID, 1);
944 rt2x00_set_field32(&reg, TXRX_CSR2_BBP_ID1, 12);
945 rt2x00_set_field32(&reg, TXRX_CSR2_BBP_ID1_VALID, 1);
946 rt2x00_set_field32(&reg, TXRX_CSR2_BBP_ID2, 11);
947 rt2x00_set_field32(&reg, TXRX_CSR2_BBP_ID2_VALID, 1);
948 rt2x00_set_field32(&reg, TXRX_CSR2_BBP_ID3, 10);
949 rt2x00_set_field32(&reg, TXRX_CSR2_BBP_ID3_VALID, 1);
950 rt73usb_register_write(rt2x00dev, TXRX_CSR2, reg);
951
952 /*
953 * OFDM TXD BBP registers
954 */
955 rt73usb_register_read(rt2x00dev, TXRX_CSR3, &reg);
956 rt2x00_set_field32(&reg, TXRX_CSR3_BBP_ID0, 7);
957 rt2x00_set_field32(&reg, TXRX_CSR3_BBP_ID0_VALID, 1);
958 rt2x00_set_field32(&reg, TXRX_CSR3_BBP_ID1, 6);
959 rt2x00_set_field32(&reg, TXRX_CSR3_BBP_ID1_VALID, 1);
960 rt2x00_set_field32(&reg, TXRX_CSR3_BBP_ID2, 5);
961 rt2x00_set_field32(&reg, TXRX_CSR3_BBP_ID2_VALID, 1);
962 rt73usb_register_write(rt2x00dev, TXRX_CSR3, reg);
963
964 rt73usb_register_read(rt2x00dev, TXRX_CSR7, &reg);
965 rt2x00_set_field32(&reg, TXRX_CSR7_ACK_CTS_6MBS, 59);
966 rt2x00_set_field32(&reg, TXRX_CSR7_ACK_CTS_9MBS, 53);
967 rt2x00_set_field32(&reg, TXRX_CSR7_ACK_CTS_12MBS, 49);
968 rt2x00_set_field32(&reg, TXRX_CSR7_ACK_CTS_18MBS, 46);
969 rt73usb_register_write(rt2x00dev, TXRX_CSR7, reg);
970
971 rt73usb_register_read(rt2x00dev, TXRX_CSR8, &reg);
972 rt2x00_set_field32(&reg, TXRX_CSR8_ACK_CTS_24MBS, 44);
973 rt2x00_set_field32(&reg, TXRX_CSR8_ACK_CTS_36MBS, 42);
974 rt2x00_set_field32(&reg, TXRX_CSR8_ACK_CTS_48MBS, 42);
975 rt2x00_set_field32(&reg, TXRX_CSR8_ACK_CTS_54MBS, 42);
976 rt73usb_register_write(rt2x00dev, TXRX_CSR8, reg);
977
978 rt73usb_register_write(rt2x00dev, TXRX_CSR15, 0x0000000f);
979
980 rt73usb_register_read(rt2x00dev, MAC_CSR6, &reg);
981 rt2x00_set_field32(&reg, MAC_CSR6_MAX_FRAME_UNIT, 0xfff);
982 rt73usb_register_write(rt2x00dev, MAC_CSR6, reg);
983
984 rt73usb_register_write(rt2x00dev, MAC_CSR10, 0x00000718);
985
986 if (rt2x00dev->ops->lib->set_device_state(rt2x00dev, STATE_AWAKE))
987 return -EBUSY;
988
989 rt73usb_register_write(rt2x00dev, MAC_CSR13, 0x00007f00);
990
a9450b70
ID		 991 rt73usb_register_read(rt2x00dev, MAC_CSR14, &reg);
992 rt2x00_set_field32(&reg, MAC_CSR14_ON_PERIOD, 70);
993 rt2x00_set_field32(&reg, MAC_CSR14_OFF_PERIOD, 30);
994 rt73usb_register_write(rt2x00dev, MAC_CSR14, reg);
995
95ea3627
ID		 996 /*
997 * Invalidate all Shared Keys (SEC_CSR0),
998 * and clear the Shared key Cipher algorithms (SEC_CSR1 & SEC_CSR5)
999 */
1000 rt73usb_register_write(rt2x00dev, SEC_CSR0, 0x00000000);
1001 rt73usb_register_write(rt2x00dev, SEC_CSR1, 0x00000000);
1002 rt73usb_register_write(rt2x00dev, SEC_CSR5, 0x00000000);
1003
1004 reg = 0x000023b0;
1005 if (rt2x00_rf(&rt2x00dev->chip, RF5225) ||
1006 rt2x00_rf(&rt2x00dev->chip, RF2527))
1007 rt2x00_set_field32(&reg, PHY_CSR1_RF_RPI, 1);
1008 rt73usb_register_write(rt2x00dev, PHY_CSR1, reg);
1009
1010 rt73usb_register_write(rt2x00dev, PHY_CSR5, 0x00040a06);
1011 rt73usb_register_write(rt2x00dev, PHY_CSR6, 0x00080606);
1012 rt73usb_register_write(rt2x00dev, PHY_CSR7, 0x00000408);
1013
1014 rt73usb_register_read(rt2x00dev, AC_TXOP_CSR0, &reg);
1015 rt2x00_set_field32(&reg, AC_TXOP_CSR0_AC0_TX_OP, 0);
1016 rt2x00_set_field32(&reg, AC_TXOP_CSR0_AC1_TX_OP, 0);
1017 rt73usb_register_write(rt2x00dev, AC_TXOP_CSR0, reg);
1018
1019 rt73usb_register_read(rt2x00dev, AC_TXOP_CSR1, &reg);
1020 rt2x00_set_field32(&reg, AC_TXOP_CSR1_AC2_TX_OP, 192);
1021 rt2x00_set_field32(&reg, AC_TXOP_CSR1_AC3_TX_OP, 48);
1022 rt73usb_register_write(rt2x00dev, AC_TXOP_CSR1, reg);
1023
1024 rt73usb_register_read(rt2x00dev, MAC_CSR9, &reg);
1025 rt2x00_set_field32(&reg, MAC_CSR9_CW_SELECT, 0);
1026 rt73usb_register_write(rt2x00dev, MAC_CSR9, reg);
1027
6bb40dd1
ID		 1028 /*
1029 * Clear all beacons
1030 * For the Beacon base registers we only need to clear
1031 * the first byte since that byte contains the VALID and OWNER
1032 * bits which (when set to 0) will invalidate the entire beacon.
1033 */
1034 rt73usb_register_write(rt2x00dev, HW_BEACON_BASE0, 0);
1035 rt73usb_register_write(rt2x00dev, HW_BEACON_BASE1, 0);
1036 rt73usb_register_write(rt2x00dev, HW_BEACON_BASE2, 0);
1037 rt73usb_register_write(rt2x00dev, HW_BEACON_BASE3, 0);
1038
95ea3627
ID		 1039 /*
1040 * We must clear the error counters.
1041 * These registers are cleared on read,
1042 * so we may pass a useless variable to store the value.
1043 */
1044 rt73usb_register_read(rt2x00dev, STA_CSR0, &reg);
1045 rt73usb_register_read(rt2x00dev, STA_CSR1, &reg);
1046 rt73usb_register_read(rt2x00dev, STA_CSR2, &reg);
1047
1048 /*
1049 * Reset MAC and BBP registers.
1050 */
1051 rt73usb_register_read(rt2x00dev, MAC_CSR1, &reg);
1052 rt2x00_set_field32(&reg, MAC_CSR1_SOFT_RESET, 1);
1053 rt2x00_set_field32(&reg, MAC_CSR1_BBP_RESET, 1);
1054 rt73usb_register_write(rt2x00dev, MAC_CSR1, reg);
1055
1056 rt73usb_register_read(rt2x00dev, MAC_CSR1, &reg);
1057 rt2x00_set_field32(&reg, MAC_CSR1_SOFT_RESET, 0);
1058 rt2x00_set_field32(&reg, MAC_CSR1_BBP_RESET, 0);
1059 rt73usb_register_write(rt2x00dev, MAC_CSR1, reg);
1060
1061 rt73usb_register_read(rt2x00dev, MAC_CSR1, &reg);
1062 rt2x00_set_field32(&reg, MAC_CSR1_HOST_READY, 1);
1063 rt73usb_register_write(rt2x00dev, MAC_CSR1, reg);
1064
1065 return 0;
1066}
1067
1068static int rt73usb_init_bbp(struct rt2x00_dev *rt2x00dev)
1069{
1070 unsigned int i;
1071 u16 eeprom;
1072 u8 reg_id;
1073 u8 value;
1074
1075 for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
1076 rt73usb_bbp_read(rt2x00dev, 0, &value);
1077 if ((value != 0xff) && (value != 0x00))
1078 goto continue_csr_init;
1079 NOTICE(rt2x00dev, "Waiting for BBP register.\n");
1080 udelay(REGISTER_BUSY_DELAY);
1081 }
1082
1083 ERROR(rt2x00dev, "BBP register access failed, aborting.\n");
1084 return -EACCES;
1085
1086continue_csr_init:
1087 rt73usb_bbp_write(rt2x00dev, 3, 0x80);
1088 rt73usb_bbp_write(rt2x00dev, 15, 0x30);
1089 rt73usb_bbp_write(rt2x00dev, 21, 0xc8);
1090 rt73usb_bbp_write(rt2x00dev, 22, 0x38);
1091 rt73usb_bbp_write(rt2x00dev, 23, 0x06);
1092 rt73usb_bbp_write(rt2x00dev, 24, 0xfe);
1093 rt73usb_bbp_write(rt2x00dev, 25, 0x0a);
1094 rt73usb_bbp_write(rt2x00dev, 26, 0x0d);
1095 rt73usb_bbp_write(rt2x00dev, 32, 0x0b);
1096 rt73usb_bbp_write(rt2x00dev, 34, 0x12);
1097 rt73usb_bbp_write(rt2x00dev, 37, 0x07);
1098 rt73usb_bbp_write(rt2x00dev, 39, 0xf8);
1099 rt73usb_bbp_write(rt2x00dev, 41, 0x60);
1100 rt73usb_bbp_write(rt2x00dev, 53, 0x10);
1101 rt73usb_bbp_write(rt2x00dev, 54, 0x18);
1102 rt73usb_bbp_write(rt2x00dev, 60, 0x10);
1103 rt73usb_bbp_write(rt2x00dev, 61, 0x04);
1104 rt73usb_bbp_write(rt2x00dev, 62, 0x04);
1105 rt73usb_bbp_write(rt2x00dev, 75, 0xfe);
1106 rt73usb_bbp_write(rt2x00dev, 86, 0xfe);
1107 rt73usb_bbp_write(rt2x00dev, 88, 0xfe);
1108 rt73usb_bbp_write(rt2x00dev, 90, 0x0f);
1109 rt73usb_bbp_write(rt2x00dev, 99, 0x00);
1110 rt73usb_bbp_write(rt2x00dev, 102, 0x16);
1111 rt73usb_bbp_write(rt2x00dev, 107, 0x04);
1112
95ea3627
ID		 1113 for (i = 0; i < EEPROM_BBP_SIZE; i++) {
1114 rt2x00_eeprom_read(rt2x00dev, EEPROM_BBP_START + i, &eeprom);
1115
1116 if (eeprom != 0xffff && eeprom != 0x0000) {
1117 reg_id = rt2x00_get_field16(eeprom, EEPROM_BBP_REG_ID);
1118 value = rt2x00_get_field16(eeprom, EEPROM_BBP_VALUE);
95ea3627
ID		 1119 rt73usb_bbp_write(rt2x00dev, reg_id, value);
1120 }
1121 }
95ea3627
ID		 1122
1123 return 0;
1124}
1125
1126/*
1127 * Device state switch handlers.
1128 */
1129static void rt73usb_toggle_rx(struct rt2x00_dev *rt2x00dev,
1130 enum dev_state state)
1131{
1132 u32 reg;
1133
1134 rt73usb_register_read(rt2x00dev, TXRX_CSR0, &reg);
1135 rt2x00_set_field32(&reg, TXRX_CSR0_DISABLE_RX,
1136 state == STATE_RADIO_RX_OFF);
1137 rt73usb_register_write(rt2x00dev, TXRX_CSR0, reg);
1138}
1139
1140static int rt73usb_enable_radio(struct rt2x00_dev *rt2x00dev)
1141{
1142 /*
1143 * Initialize all registers.
1144 */
1145 if (rt73usb_init_registers(rt2x00dev) ||
1146 rt73usb_init_bbp(rt2x00dev)) {
1147 ERROR(rt2x00dev, "Register initialization failed.\n");
1148 return -EIO;
1149 }
1150
95ea3627
ID		 1151 return 0;
1152}
1153
1154static void rt73usb_disable_radio(struct rt2x00_dev *rt2x00dev)
1155{
95ea3627
ID		 1156 rt73usb_register_write(rt2x00dev, MAC_CSR10, 0x00001818);
1157
1158 /*
1159 * Disable synchronisation.
1160 */
1161 rt73usb_register_write(rt2x00dev, TXRX_CSR9, 0);
1162
1163 rt2x00usb_disable_radio(rt2x00dev);
1164}
1165
1166static int rt73usb_set_state(struct rt2x00_dev *rt2x00dev, enum dev_state state)
1167{
1168 u32 reg;
1169 unsigned int i;
1170 char put_to_sleep;
1171 char current_state;
1172
1173 put_to_sleep = (state != STATE_AWAKE);
1174
1175 rt73usb_register_read(rt2x00dev, MAC_CSR12, &reg);
1176 rt2x00_set_field32(&reg, MAC_CSR12_FORCE_WAKEUP, !put_to_sleep);
1177 rt2x00_set_field32(&reg, MAC_CSR12_PUT_TO_SLEEP, put_to_sleep);
1178 rt73usb_register_write(rt2x00dev, MAC_CSR12, reg);
1179
1180 /*
1181 * Device is not guaranteed to be in the requested state yet.
1182 * We must wait until the register indicates that the
1183 * device has entered the correct state.
1184 */
1185 for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
1186 rt73usb_register_read(rt2x00dev, MAC_CSR12, &reg);
1187 current_state =
1188 rt2x00_get_field32(reg, MAC_CSR12_BBP_CURRENT_STATE);
1189 if (current_state == !put_to_sleep)
1190 return 0;
1191 msleep(10);
1192 }
1193
1194 NOTICE(rt2x00dev, "Device failed to enter state %d, "
1195 "current device state %d.\n", !put_to_sleep, current_state);
1196
1197 return -EBUSY;
1198}
1199
1200static int rt73usb_set_device_state(struct rt2x00_dev *rt2x00dev,
1201 enum dev_state state)
1202{
1203 int retval = 0;
1204
1205 switch (state) {
1206 case STATE_RADIO_ON:
1207 retval = rt73usb_enable_radio(rt2x00dev);
1208 break;
1209 case STATE_RADIO_OFF:
1210 rt73usb_disable_radio(rt2x00dev);
1211 break;
1212 case STATE_RADIO_RX_ON:
61667d8d
ID		 1213 case STATE_RADIO_RX_ON_LINK:
1214 rt73usb_toggle_rx(rt2x00dev, STATE_RADIO_RX_ON);
1215 break;
95ea3627 1216 case STATE_RADIO_RX_OFF:
61667d8d
ID		 1217 case STATE_RADIO_RX_OFF_LINK:
1218 rt73usb_toggle_rx(rt2x00dev, STATE_RADIO_RX_OFF);
95ea3627
ID		 1219 break;
1220 case STATE_DEEP_SLEEP:
1221 case STATE_SLEEP:
1222 case STATE_STANDBY:
1223 case STATE_AWAKE:
1224 retval = rt73usb_set_state(rt2x00dev, state);
1225 break;
1226 default:
1227 retval = -ENOTSUPP;
1228 break;
1229 }
1230
1231 return retval;
1232}
1233
1234/*
1235 * TX descriptor initialization
1236 */
1237static void rt73usb_write_tx_desc(struct rt2x00_dev *rt2x00dev,
dd3193e1 1238 struct sk_buff *skb,
181d6902 1239 struct txentry_desc *txdesc,
dd3193e1 1240 struct ieee80211_tx_control *control)
95ea3627 1241{
181d6902 1242 struct skb_frame_desc *skbdesc = get_skb_frame_desc(skb);
dd3193e1 1243 __le32 *txd = skbdesc->desc;
95ea3627
ID		 1244 u32 word;
1245
1246 /*
1247 * Start writing the descriptor words.
1248 */
1249 rt2x00_desc_read(txd, 1, &word);
181d6902
ID		 1250 rt2x00_set_field32(&word, TXD_W1_HOST_Q_ID, txdesc->queue);
1251 rt2x00_set_field32(&word, TXD_W1_AIFSN, txdesc->aifs);
1252 rt2x00_set_field32(&word, TXD_W1_CWMIN, txdesc->cw_min);
1253 rt2x00_set_field32(&word, TXD_W1_CWMAX, txdesc->cw_max);
95ea3627
ID		 1254 rt2x00_set_field32(&word, TXD_W1_IV_OFFSET, IEEE80211_HEADER);
1255 rt2x00_set_field32(&word, TXD_W1_HW_SEQUENCE, 1);
1256 rt2x00_desc_write(txd, 1, word);
1257
1258 rt2x00_desc_read(txd, 2, &word);
181d6902
ID		 1259 rt2x00_set_field32(&word, TXD_W2_PLCP_SIGNAL, txdesc->signal);
1260 rt2x00_set_field32(&word, TXD_W2_PLCP_SERVICE, txdesc->service);
1261 rt2x00_set_field32(&word, TXD_W2_PLCP_LENGTH_LOW, txdesc->length_low);
1262 rt2x00_set_field32(&word, TXD_W2_PLCP_LENGTH_HIGH, txdesc->length_high);
95ea3627
ID		 1263 rt2x00_desc_write(txd, 2, word);
1264
1265 rt2x00_desc_read(txd, 5, &word);
1266 rt2x00_set_field32(&word, TXD_W5_TX_POWER,
ac1aa7e4 1267 TXPOWER_TO_DEV(rt2x00dev->tx_power));
95ea3627
ID		 1268 rt2x00_set_field32(&word, TXD_W5_WAITING_DMA_DONE_INT, 1);
1269 rt2x00_desc_write(txd, 5, word);
1270
1271 rt2x00_desc_read(txd, 0, &word);
1272 rt2x00_set_field32(&word, TXD_W0_BURST,
181d6902 1273 test_bit(ENTRY_TXD_BURST, &txdesc->flags));
95ea3627
ID		 1274 rt2x00_set_field32(&word, TXD_W0_VALID, 1);
1275 rt2x00_set_field32(&word, TXD_W0_MORE_FRAG,
181d6902 1276 test_bit(ENTRY_TXD_MORE_FRAG, &txdesc->flags));
95ea3627 1277 rt2x00_set_field32(&word, TXD_W0_ACK,
181d6902 1278 test_bit(ENTRY_TXD_ACK, &txdesc->flags));
95ea3627 1279 rt2x00_set_field32(&word, TXD_W0_TIMESTAMP,
181d6902 1280 test_bit(ENTRY_TXD_REQ_TIMESTAMP, &txdesc->flags));
95ea3627 1281 rt2x00_set_field32(&word, TXD_W0_OFDM,
181d6902
ID		 1282 test_bit(ENTRY_TXD_OFDM_RATE, &txdesc->flags));
1283 rt2x00_set_field32(&word, TXD_W0_IFS, txdesc->ifs);
95ea3627
ID		 1284 rt2x00_set_field32(&word, TXD_W0_RETRY_MODE,
1285 !!(control->flags &
1286 IEEE80211_TXCTL_LONG_RETRY_LIMIT));
1287 rt2x00_set_field32(&word, TXD_W0_TKIP_MIC, 0);
dd3193e1 1288 rt2x00_set_field32(&word, TXD_W0_DATABYTE_COUNT, skbdesc->data_len);
95ea3627 1289 rt2x00_set_field32(&word, TXD_W0_BURST2,
181d6902 1290 test_bit(ENTRY_TXD_BURST, &txdesc->flags));
95ea3627
ID		 1291 rt2x00_set_field32(&word, TXD_W0_CIPHER_ALG, CIPHER_NONE);
1292 rt2x00_desc_write(txd, 0, word);
1293}
1294
dd9fa2d2 1295static int rt73usb_get_tx_data_len(struct rt2x00_dev *rt2x00dev,
b242e891 1296 struct sk_buff *skb)
dd9fa2d2
ID		 1297{
1298 int length;
1299
1300 /*
1301 * The length _must_ be a multiple of 4,
1302 * but it must _not_ be a multiple of the USB packet size.
1303 */
1304 length = roundup(skb->len, 4);
b242e891 1305 length += (4 * !(length % rt2x00dev->usb_maxpacket));
dd9fa2d2
ID		 1306
1307 return length;
1308}
1309
95ea3627
ID		 1310/*
1311 * TX data initialization
1312 */
1313static void rt73usb_kick_tx_queue(struct rt2x00_dev *rt2x00dev,
5957da4c 1314 const unsigned int queue)
95ea3627
ID		 1315{
1316 u32 reg;
1317
5957da4c 1318 if (queue != RT2X00_BCN_QUEUE_BEACON)
95ea3627
ID		 1319 return;
1320
1321 /*
1322 * For Wi-Fi faily generated beacons between participating stations.
1323 * Set TBTT phase adaptive adjustment step to 8us (default 16us)
1324 */
1325 rt73usb_register_write(rt2x00dev, TXRX_CSR10, 0x00001008);
1326
1327 rt73usb_register_read(rt2x00dev, TXRX_CSR9, &reg);
1328 if (!rt2x00_get_field32(reg, TXRX_CSR9_BEACON_GEN)) {
8af244cc
ID		 1329 rt2x00_set_field32(&reg, TXRX_CSR9_TSF_TICKING, 1);
1330 rt2x00_set_field32(&reg, TXRX_CSR9_TBTT_ENABLE, 1);
95ea3627
ID		 1331 rt2x00_set_field32(&reg, TXRX_CSR9_BEACON_GEN, 1);
1332 rt73usb_register_write(rt2x00dev, TXRX_CSR9, reg);
1333 }
1334}
1335
1336/*
1337 * RX control handlers
1338 */
1339static int rt73usb_agc_to_rssi(struct rt2x00_dev *rt2x00dev, int rxd_w1)
1340{
1341 u16 eeprom;
1342 u8 offset;
1343 u8 lna;
1344
1345 lna = rt2x00_get_field32(rxd_w1, RXD_W1_RSSI_LNA);
1346 switch (lna) {
1347 case 3:
1348 offset = 90;
1349 break;
1350 case 2:
1351 offset = 74;
1352 break;
1353 case 1:
1354 offset = 64;
1355 break;
1356 default:
1357 return 0;
1358 }
1359
8318d78a 1360 if (rt2x00dev->rx_status.band == IEEE80211_BAND_5GHZ) {
95ea3627
ID		 1361 if (test_bit(CONFIG_EXTERNAL_LNA_A, &rt2x00dev->flags)) {
1362 if (lna == 3 || lna == 2)
1363 offset += 10;
1364 } else {
1365 if (lna == 3)
1366 offset += 6;
1367 else if (lna == 2)
1368 offset += 8;
1369 }
1370
1371 rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_OFFSET_A, &eeprom);
1372 offset -= rt2x00_get_field16(eeprom, EEPROM_RSSI_OFFSET_A_1);
1373 } else {
1374 if (test_bit(CONFIG_EXTERNAL_LNA_BG, &rt2x00dev->flags))
1375 offset += 14;
1376
1377 rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_OFFSET_BG, &eeprom);
1378 offset -= rt2x00_get_field16(eeprom, EEPROM_RSSI_OFFSET_BG_1);
1379 }
1380
1381 return rt2x00_get_field32(rxd_w1, RXD_W1_RSSI_AGC) * 2 - offset;
1382}
1383
181d6902
ID		 1384static void rt73usb_fill_rxdone(struct queue_entry *entry,
1385 struct rxdone_entry_desc *rxdesc)
95ea3627 1386{
181d6902 1387 struct skb_frame_desc *skbdesc = get_skb_frame_desc(entry->skb);
4bd7c452 1388 __le32 *rxd = (__le32 *)entry->skb->data;
f855c10b 1389 unsigned int offset = entry->queue->desc_size + 2;
95ea3627
ID		 1390 u32 word0;
1391 u32 word1;
1392
f855c10b
ID		 1393 /*
1394 * Copy descriptor to the available headroom inside the skbuffer.
f855c10b
ID		 1395 */
1396 skb_push(entry->skb, offset);
1397 memcpy(entry->skb->data, rxd, entry->queue->desc_size);
1398 rxd = (__le32 *)entry->skb->data;
f855c10b
ID		 1399
1400 /*
1401 * The descriptor is now aligned to 4 bytes and thus it is
1402 * now safe to read it on all architectures.
1403 */
95ea3627
ID		 1404 rt2x00_desc_read(rxd, 0, &word0);
1405 rt2x00_desc_read(rxd, 1, &word1);
1406
181d6902 1407 rxdesc->flags = 0;
4150c572 1408 if (rt2x00_get_field32(word0, RXD_W0_CRC_ERROR))
181d6902 1409 rxdesc->flags |= RX_FLAG_FAILED_FCS_CRC;
95ea3627
ID		 1410
1411 /*
1412 * Obtain the status about this packet.
1413 */
181d6902
ID		 1414 rxdesc->signal = rt2x00_get_field32(word1, RXD_W1_SIGNAL);
1415 rxdesc->rssi = rt73usb_agc_to_rssi(entry->queue->rt2x00dev, word1);
1416 rxdesc->ofdm = rt2x00_get_field32(word0, RXD_W0_OFDM);
1417 rxdesc->size = rt2x00_get_field32(word0, RXD_W0_DATABYTE_COUNT);
1418 rxdesc->my_bss = !!rt2x00_get_field32(word0, RXD_W0_MY_BSS);
1419
2ae23854
MN		 1420 /*
1421 * Adjust the skb memory window to the frame boundaries.
1422 */
1423 skb_pull(entry->skb, offset + entry->queue->desc_size);
1424 skb_trim(entry->skb, rxdesc->size);
1425
7d1de806
ID		 1426 /*
1427 * Set descriptor and data pointer.
1428 */
f855c10b 1429 skbdesc->data = entry->skb->data;
647d0ca9 1430 skbdesc->data_len = rxdesc->size;
2ae23854 1431 skbdesc->desc = rxd;
181d6902 1432 skbdesc->desc_len = entry->queue->desc_size;
95ea3627
ID		 1433}
1434
1435/*
1436 * Device probe functions.
1437 */
1438static int rt73usb_validate_eeprom(struct rt2x00_dev *rt2x00dev)
1439{
1440 u16 word;
1441 u8 *mac;
1442 s8 value;
1443
1444 rt2x00usb_eeprom_read(rt2x00dev, rt2x00dev->eeprom, EEPROM_SIZE);
1445
1446 /*
1447 * Start validation of the data that has been read.
1448 */
1449 mac = rt2x00_eeprom_addr(rt2x00dev, EEPROM_MAC_ADDR_0);
1450 if (!is_valid_ether_addr(mac)) {
0795af57
JP		 1451 DECLARE_MAC_BUF(macbuf);
1452
95ea3627 1453 random_ether_addr(mac);
0795af57 1454 EEPROM(rt2x00dev, "MAC: %s\n", print_mac(macbuf, mac));
95ea3627
ID		 1455 }
1456
1457 rt2x00_eeprom_read(rt2x00dev, EEPROM_ANTENNA, &word);
1458 if (word == 0xffff) {
1459 rt2x00_set_field16(&word, EEPROM_ANTENNA_NUM, 2);
362f3b6b
ID		 1460 rt2x00_set_field16(&word, EEPROM_ANTENNA_TX_DEFAULT,
1461 ANTENNA_B);
1462 rt2x00_set_field16(&word, EEPROM_ANTENNA_RX_DEFAULT,
1463 ANTENNA_B);
95ea3627
ID		 1464 rt2x00_set_field16(&word, EEPROM_ANTENNA_FRAME_TYPE, 0);
1465 rt2x00_set_field16(&word, EEPROM_ANTENNA_DYN_TXAGC, 0);
1466 rt2x00_set_field16(&word, EEPROM_ANTENNA_HARDWARE_RADIO, 0);
1467 rt2x00_set_field16(&word, EEPROM_ANTENNA_RF_TYPE, RF5226);
1468 rt2x00_eeprom_write(rt2x00dev, EEPROM_ANTENNA, word);
1469 EEPROM(rt2x00dev, "Antenna: 0x%04x\n", word);
1470 }
1471
1472 rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC, &word);
1473 if (word == 0xffff) {
1474 rt2x00_set_field16(&word, EEPROM_NIC_EXTERNAL_LNA, 0);
1475 rt2x00_eeprom_write(rt2x00dev, EEPROM_NIC, word);
1476 EEPROM(rt2x00dev, "NIC: 0x%04x\n", word);
1477 }
1478
1479 rt2x00_eeprom_read(rt2x00dev, EEPROM_LED, &word);
1480 if (word == 0xffff) {
1481 rt2x00_set_field16(&word, EEPROM_LED_POLARITY_RDY_G, 0);
1482 rt2x00_set_field16(&word, EEPROM_LED_POLARITY_RDY_A, 0);
1483 rt2x00_set_field16(&word, EEPROM_LED_POLARITY_ACT, 0);
1484 rt2x00_set_field16(&word, EEPROM_LED_POLARITY_GPIO_0, 0);
1485 rt2x00_set_field16(&word, EEPROM_LED_POLARITY_GPIO_1, 0);
1486 rt2x00_set_field16(&word, EEPROM_LED_POLARITY_GPIO_2, 0);
1487 rt2x00_set_field16(&word, EEPROM_LED_POLARITY_GPIO_3, 0);
1488 rt2x00_set_field16(&word, EEPROM_LED_POLARITY_GPIO_4, 0);
1489 rt2x00_set_field16(&word, EEPROM_LED_LED_MODE,
1490 LED_MODE_DEFAULT);
1491 rt2x00_eeprom_write(rt2x00dev, EEPROM_LED, word);
1492 EEPROM(rt2x00dev, "Led: 0x%04x\n", word);
1493 }
1494
1495 rt2x00_eeprom_read(rt2x00dev, EEPROM_FREQ, &word);
1496 if (word == 0xffff) {
1497 rt2x00_set_field16(&word, EEPROM_FREQ_OFFSET, 0);
1498 rt2x00_set_field16(&word, EEPROM_FREQ_SEQ, 0);
1499 rt2x00_eeprom_write(rt2x00dev, EEPROM_FREQ, word);
1500 EEPROM(rt2x00dev, "Freq: 0x%04x\n", word);
1501 }
1502
1503 rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_OFFSET_BG, &word);
1504 if (word == 0xffff) {
1505 rt2x00_set_field16(&word, EEPROM_RSSI_OFFSET_BG_1, 0);
1506 rt2x00_set_field16(&word, EEPROM_RSSI_OFFSET_BG_2, 0);
1507 rt2x00_eeprom_write(rt2x00dev, EEPROM_RSSI_OFFSET_BG, word);
1508 EEPROM(rt2x00dev, "RSSI OFFSET BG: 0x%04x\n", word);
1509 } else {
1510 value = rt2x00_get_field16(word, EEPROM_RSSI_OFFSET_BG_1);
1511 if (value < -10 || value > 10)
1512 rt2x00_set_field16(&word, EEPROM_RSSI_OFFSET_BG_1, 0);
1513 value = rt2x00_get_field16(word, EEPROM_RSSI_OFFSET_BG_2);
1514 if (value < -10 || value > 10)
1515 rt2x00_set_field16(&word, EEPROM_RSSI_OFFSET_BG_2, 0);
1516 rt2x00_eeprom_write(rt2x00dev, EEPROM_RSSI_OFFSET_BG, word);
1517 }
1518
1519 rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_OFFSET_A, &word);
1520 if (word == 0xffff) {
1521 rt2x00_set_field16(&word, EEPROM_RSSI_OFFSET_A_1, 0);
1522 rt2x00_set_field16(&word, EEPROM_RSSI_OFFSET_A_2, 0);
1523 rt2x00_eeprom_write(rt2x00dev, EEPROM_RSSI_OFFSET_A, word);
417f412f 1524 EEPROM(rt2x00dev, "RSSI OFFSET A: 0x%04x\n", word);
95ea3627
ID		 1525 } else {
1526 value = rt2x00_get_field16(word, EEPROM_RSSI_OFFSET_A_1);
1527 if (value < -10 || value > 10)
1528 rt2x00_set_field16(&word, EEPROM_RSSI_OFFSET_A_1, 0);
1529 value = rt2x00_get_field16(word, EEPROM_RSSI_OFFSET_A_2);
1530 if (value < -10 || value > 10)
1531 rt2x00_set_field16(&word, EEPROM_RSSI_OFFSET_A_2, 0);
1532 rt2x00_eeprom_write(rt2x00dev, EEPROM_RSSI_OFFSET_A, word);
1533 }
1534
1535 return 0;
1536}
1537
1538static int rt73usb_init_eeprom(struct rt2x00_dev *rt2x00dev)
1539{
1540 u32 reg;
1541 u16 value;
1542 u16 eeprom;
1543
1544 /*
1545 * Read EEPROM word for configuration.
1546 */
1547 rt2x00_eeprom_read(rt2x00dev, EEPROM_ANTENNA, &eeprom);
1548
1549 /*
1550 * Identify RF chipset.
1551 */
1552 value = rt2x00_get_field16(eeprom, EEPROM_ANTENNA_RF_TYPE);
1553 rt73usb_register_read(rt2x00dev, MAC_CSR0, &reg);
1554 rt2x00_set_chip(rt2x00dev, RT2571, value, reg);
1555
755a957d 1556 if (!rt2x00_check_rev(&rt2x00dev->chip, 0x25730)) {
95ea3627
ID		 1557 ERROR(rt2x00dev, "Invalid RT chipset detected.\n");
1558 return -ENODEV;
1559 }
1560
1561 if (!rt2x00_rf(&rt2x00dev->chip, RF5226) &&
1562 !rt2x00_rf(&rt2x00dev->chip, RF2528) &&
1563 !rt2x00_rf(&rt2x00dev->chip, RF5225) &&
1564 !rt2x00_rf(&rt2x00dev->chip, RF2527)) {
1565 ERROR(rt2x00dev, "Invalid RF chipset detected.\n");
1566 return -ENODEV;
1567 }
1568
1569 /*
1570 * Identify default antenna configuration.
1571 */
addc81bd 1572 rt2x00dev->default_ant.tx =
95ea3627 1573 rt2x00_get_field16(eeprom, EEPROM_ANTENNA_TX_DEFAULT);
addc81bd 1574 rt2x00dev->default_ant.rx =
95ea3627
ID		 1575 rt2x00_get_field16(eeprom, EEPROM_ANTENNA_RX_DEFAULT);
1576
1577 /*
1578 * Read the Frame type.
1579 */
1580 if (rt2x00_get_field16(eeprom, EEPROM_ANTENNA_FRAME_TYPE))
1581 __set_bit(CONFIG_FRAME_TYPE, &rt2x00dev->flags);
1582
1583 /*
1584 * Read frequency offset.
1585 */
1586 rt2x00_eeprom_read(rt2x00dev, EEPROM_FREQ, &eeprom);
1587 rt2x00dev->freq_offset = rt2x00_get_field16(eeprom, EEPROM_FREQ_OFFSET);
1588
1589 /*
1590 * Read external LNA informations.
1591 */
1592 rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC, &eeprom);
1593
1594 if (rt2x00_get_field16(eeprom, EEPROM_NIC_EXTERNAL_LNA)) {
1595 __set_bit(CONFIG_EXTERNAL_LNA_A, &rt2x00dev->flags);
1596 __set_bit(CONFIG_EXTERNAL_LNA_BG, &rt2x00dev->flags);
1597 }
1598
1599 /*
1600 * Store led settings, for correct led behaviour.
1601 */
a9450b70 1602#ifdef CONFIG_RT73USB_LEDS
95ea3627
ID		 1603 rt2x00_eeprom_read(rt2x00dev, EEPROM_LED, &eeprom);
1604
a9450b70
ID		 1605 switch (value) {
1606 case LED_MODE_TXRX_ACTIVITY:
1607 case LED_MODE_ASUS:
1608 case LED_MODE_ALPHA:
1609 case LED_MODE_DEFAULT:
1610 rt2x00dev->led_flags =
1611 LED_SUPPORT_RADIO | LED_SUPPORT_ASSOC;
1612 break;
1613 case LED_MODE_SIGNAL_STRENGTH:
1614 rt2x00dev->led_flags =
1615 LED_SUPPORT_RADIO | LED_SUPPORT_ASSOC |
1616 LED_SUPPORT_QUALITY;
1617 break;
1618 }
1619
1620 rt2x00_set_field16(&rt2x00dev->led_mcu_reg, MCU_LEDCS_LED_MODE, value);
1621 rt2x00_set_field16(&rt2x00dev->led_mcu_reg, MCU_LEDCS_POLARITY_GPIO_0,
95ea3627
ID		 1622 rt2x00_get_field16(eeprom,
1623 EEPROM_LED_POLARITY_GPIO_0));
a9450b70 1624 rt2x00_set_field16(&rt2x00dev->led_mcu_reg, MCU_LEDCS_POLARITY_GPIO_1,
95ea3627
ID		 1625 rt2x00_get_field16(eeprom,
1626 EEPROM_LED_POLARITY_GPIO_1));
a9450b70 1627 rt2x00_set_field16(&rt2x00dev->led_mcu_reg, MCU_LEDCS_POLARITY_GPIO_2,
95ea3627
ID		 1628 rt2x00_get_field16(eeprom,
1629 EEPROM_LED_POLARITY_GPIO_2));
a9450b70 1630 rt2x00_set_field16(&rt2x00dev->led_mcu_reg, MCU_LEDCS_POLARITY_GPIO_3,
95ea3627
ID		 1631 rt2x00_get_field16(eeprom,
1632 EEPROM_LED_POLARITY_GPIO_3));
a9450b70 1633 rt2x00_set_field16(&rt2x00dev->led_mcu_reg, MCU_LEDCS_POLARITY_GPIO_4,
95ea3627
ID		 1634 rt2x00_get_field16(eeprom,
1635 EEPROM_LED_POLARITY_GPIO_4));
a9450b70 1636 rt2x00_set_field16(&rt2x00dev->led_mcu_reg, MCU_LEDCS_POLARITY_ACT,
95ea3627 1637 rt2x00_get_field16(eeprom, EEPROM_LED_POLARITY_ACT));
a9450b70 1638 rt2x00_set_field16(&rt2x00dev->led_mcu_reg, MCU_LEDCS_POLARITY_READY_BG,
95ea3627
ID		 1639 rt2x00_get_field16(eeprom,
1640 EEPROM_LED_POLARITY_RDY_G));
a9450b70 1641 rt2x00_set_field16(&rt2x00dev->led_mcu_reg, MCU_LEDCS_POLARITY_READY_A,
95ea3627
ID		 1642 rt2x00_get_field16(eeprom,
1643 EEPROM_LED_POLARITY_RDY_A));
a9450b70 1644#endif /* CONFIG_RT73USB_LEDS */
95ea3627
ID		 1645
1646 return 0;
1647}
1648
1649/*
1650 * RF value list for RF2528
1651 * Supports: 2.4 GHz
1652 */
1653static const struct rf_channel rf_vals_bg_2528[] = {
1654 { 1, 0x00002c0c, 0x00000786, 0x00068255, 0x000fea0b },
1655 { 2, 0x00002c0c, 0x00000786, 0x00068255, 0x000fea1f },
1656 { 3, 0x00002c0c, 0x0000078a, 0x00068255, 0x000fea0b },
1657 { 4, 0x00002c0c, 0x0000078a, 0x00068255, 0x000fea1f },
1658 { 5, 0x00002c0c, 0x0000078e, 0x00068255, 0x000fea0b },
1659 { 6, 0x00002c0c, 0x0000078e, 0x00068255, 0x000fea1f },
1660 { 7, 0x00002c0c, 0x00000792, 0x00068255, 0x000fea0b },
1661 { 8, 0x00002c0c, 0x00000792, 0x00068255, 0x000fea1f },
1662 { 9, 0x00002c0c, 0x00000796, 0x00068255, 0x000fea0b },
1663 { 10, 0x00002c0c, 0x00000796, 0x00068255, 0x000fea1f },
1664 { 11, 0x00002c0c, 0x0000079a, 0x00068255, 0x000fea0b },
1665 { 12, 0x00002c0c, 0x0000079a, 0x00068255, 0x000fea1f },
1666 { 13, 0x00002c0c, 0x0000079e, 0x00068255, 0x000fea0b },
1667 { 14, 0x00002c0c, 0x000007a2, 0x00068255, 0x000fea13 },
1668};
1669
1670/*
1671 * RF value list for RF5226
1672 * Supports: 2.4 GHz & 5.2 GHz
1673 */
1674static const struct rf_channel rf_vals_5226[] = {
1675 { 1, 0x00002c0c, 0x00000786, 0x00068255, 0x000fea0b },
1676 { 2, 0x00002c0c, 0x00000786, 0x00068255, 0x000fea1f },
1677 { 3, 0x00002c0c, 0x0000078a, 0x00068255, 0x000fea0b },
1678 { 4, 0x00002c0c, 0x0000078a, 0x00068255, 0x000fea1f },
1679 { 5, 0x00002c0c, 0x0000078e, 0x00068255, 0x000fea0b },
1680 { 6, 0x00002c0c, 0x0000078e, 0x00068255, 0x000fea1f },
1681 { 7, 0x00002c0c, 0x00000792, 0x00068255, 0x000fea0b },
1682 { 8, 0x00002c0c, 0x00000792, 0x00068255, 0x000fea1f },
1683 { 9, 0x00002c0c, 0x00000796, 0x00068255, 0x000fea0b },
1684 { 10, 0x00002c0c, 0x00000796, 0x00068255, 0x000fea1f },
1685 { 11, 0x00002c0c, 0x0000079a, 0x00068255, 0x000fea0b },
1686 { 12, 0x00002c0c, 0x0000079a, 0x00068255, 0x000fea1f },
1687 { 13, 0x00002c0c, 0x0000079e, 0x00068255, 0x000fea0b },
1688 { 14, 0x00002c0c, 0x000007a2, 0x00068255, 0x000fea13 },
1689
1690 /* 802.11 UNI / HyperLan 2 */
1691 { 36, 0x00002c0c, 0x0000099a, 0x00098255, 0x000fea23 },
1692 { 40, 0x00002c0c, 0x000009a2, 0x00098255, 0x000fea03 },
1693 { 44, 0x00002c0c, 0x000009a6, 0x00098255, 0x000fea0b },
1694 { 48, 0x00002c0c, 0x000009aa, 0x00098255, 0x000fea13 },
1695 { 52, 0x00002c0c, 0x000009ae, 0x00098255, 0x000fea1b },
1696 { 56, 0x00002c0c, 0x000009b2, 0x00098255, 0x000fea23 },
1697 { 60, 0x00002c0c, 0x000009ba, 0x00098255, 0x000fea03 },
1698 { 64, 0x00002c0c, 0x000009be, 0x00098255, 0x000fea0b },
1699
1700 /* 802.11 HyperLan 2 */
1701 { 100, 0x00002c0c, 0x00000a2a, 0x000b8255, 0x000fea03 },
1702 { 104, 0x00002c0c, 0x00000a2e, 0x000b8255, 0x000fea0b },
1703 { 108, 0x00002c0c, 0x00000a32, 0x000b8255, 0x000fea13 },
1704 { 112, 0x00002c0c, 0x00000a36, 0x000b8255, 0x000fea1b },
1705 { 116, 0x00002c0c, 0x00000a3a, 0x000b8255, 0x000fea23 },
1706 { 120, 0x00002c0c, 0x00000a82, 0x000b8255, 0x000fea03 },
1707 { 124, 0x00002c0c, 0x00000a86, 0x000b8255, 0x000fea0b },
1708 { 128, 0x00002c0c, 0x00000a8a, 0x000b8255, 0x000fea13 },
1709 { 132, 0x00002c0c, 0x00000a8e, 0x000b8255, 0x000fea1b },
1710 { 136, 0x00002c0c, 0x00000a92, 0x000b8255, 0x000fea23 },
1711
1712 /* 802.11 UNII */
1713 { 140, 0x00002c0c, 0x00000a9a, 0x000b8255, 0x000fea03 },
1714 { 149, 0x00002c0c, 0x00000aa2, 0x000b8255, 0x000fea1f },
1715 { 153, 0x00002c0c, 0x00000aa6, 0x000b8255, 0x000fea27 },
1716 { 157, 0x00002c0c, 0x00000aae, 0x000b8255, 0x000fea07 },
1717 { 161, 0x00002c0c, 0x00000ab2, 0x000b8255, 0x000fea0f },
1718 { 165, 0x00002c0c, 0x00000ab6, 0x000b8255, 0x000fea17 },
1719
1720 /* MMAC(Japan)J52 ch 34,38,42,46 */
1721 { 34, 0x00002c0c, 0x0008099a, 0x000da255, 0x000d3a0b },
1722 { 38, 0x00002c0c, 0x0008099e, 0x000da255, 0x000d3a13 },
1723 { 42, 0x00002c0c, 0x000809a2, 0x000da255, 0x000d3a1b },
1724 { 46, 0x00002c0c, 0x000809a6, 0x000da255, 0x000d3a23 },
1725};
1726
1727/*
1728 * RF value list for RF5225 & RF2527
1729 * Supports: 2.4 GHz & 5.2 GHz
1730 */
1731static const struct rf_channel rf_vals_5225_2527[] = {
1732 { 1, 0x00002ccc, 0x00004786, 0x00068455, 0x000ffa0b },
1733 { 2, 0x00002ccc, 0x00004786, 0x00068455, 0x000ffa1f },
1734 { 3, 0x00002ccc, 0x0000478a, 0x00068455, 0x000ffa0b },
1735 { 4, 0x00002ccc, 0x0000478a, 0x00068455, 0x000ffa1f },
1736 { 5, 0x00002ccc, 0x0000478e, 0x00068455, 0x000ffa0b },
1737 { 6, 0x00002ccc, 0x0000478e, 0x00068455, 0x000ffa1f },
1738 { 7, 0x00002ccc, 0x00004792, 0x00068455, 0x000ffa0b },
1739 { 8, 0x00002ccc, 0x00004792, 0x00068455, 0x000ffa1f },
1740 { 9, 0x00002ccc, 0x00004796, 0x00068455, 0x000ffa0b },
1741 { 10, 0x00002ccc, 0x00004796, 0x00068455, 0x000ffa1f },
1742 { 11, 0x00002ccc, 0x0000479a, 0x00068455, 0x000ffa0b },
1743 { 12, 0x00002ccc, 0x0000479a, 0x00068455, 0x000ffa1f },
1744 { 13, 0x00002ccc, 0x0000479e, 0x00068455, 0x000ffa0b },
1745 { 14, 0x00002ccc, 0x000047a2, 0x00068455, 0x000ffa13 },
1746
1747 /* 802.11 UNI / HyperLan 2 */
1748 { 36, 0x00002ccc, 0x0000499a, 0x0009be55, 0x000ffa23 },
1749 { 40, 0x00002ccc, 0x000049a2, 0x0009be55, 0x000ffa03 },
1750 { 44, 0x00002ccc, 0x000049a6, 0x0009be55, 0x000ffa0b },
1751 { 48, 0x00002ccc, 0x000049aa, 0x0009be55, 0x000ffa13 },
1752 { 52, 0x00002ccc, 0x000049ae, 0x0009ae55, 0x000ffa1b },
1753 { 56, 0x00002ccc, 0x000049b2, 0x0009ae55, 0x000ffa23 },
1754 { 60, 0x00002ccc, 0x000049ba, 0x0009ae55, 0x000ffa03 },
1755 { 64, 0x00002ccc, 0x000049be, 0x0009ae55, 0x000ffa0b },
1756
1757 /* 802.11 HyperLan 2 */
1758 { 100, 0x00002ccc, 0x00004a2a, 0x000bae55, 0x000ffa03 },
1759 { 104, 0x00002ccc, 0x00004a2e, 0x000bae55, 0x000ffa0b },
1760 { 108, 0x00002ccc, 0x00004a32, 0x000bae55, 0x000ffa13 },
1761 { 112, 0x00002ccc, 0x00004a36, 0x000bae55, 0x000ffa1b },
1762 { 116, 0x00002ccc, 0x00004a3a, 0x000bbe55, 0x000ffa23 },
1763 { 120, 0x00002ccc, 0x00004a82, 0x000bbe55, 0x000ffa03 },
1764 { 124, 0x00002ccc, 0x00004a86, 0x000bbe55, 0x000ffa0b },
1765 { 128, 0x00002ccc, 0x00004a8a, 0x000bbe55, 0x000ffa13 },
1766 { 132, 0x00002ccc, 0x00004a8e, 0x000bbe55, 0x000ffa1b },
1767 { 136, 0x00002ccc, 0x00004a92, 0x000bbe55, 0x000ffa23 },
1768
1769 /* 802.11 UNII */
1770 { 140, 0x00002ccc, 0x00004a9a, 0x000bbe55, 0x000ffa03 },
1771 { 149, 0x00002ccc, 0x00004aa2, 0x000bbe55, 0x000ffa1f },
1772 { 153, 0x00002ccc, 0x00004aa6, 0x000bbe55, 0x000ffa27 },
1773 { 157, 0x00002ccc, 0x00004aae, 0x000bbe55, 0x000ffa07 },
1774 { 161, 0x00002ccc, 0x00004ab2, 0x000bbe55, 0x000ffa0f },
1775 { 165, 0x00002ccc, 0x00004ab6, 0x000bbe55, 0x000ffa17 },
1776
1777 /* MMAC(Japan)J52 ch 34,38,42,46 */
1778 { 34, 0x00002ccc, 0x0000499a, 0x0009be55, 0x000ffa0b },
1779 { 38, 0x00002ccc, 0x0000499e, 0x0009be55, 0x000ffa13 },
1780 { 42, 0x00002ccc, 0x000049a2, 0x0009be55, 0x000ffa1b },
1781 { 46, 0x00002ccc, 0x000049a6, 0x0009be55, 0x000ffa23 },
1782};
1783
1784
1785static void rt73usb_probe_hw_mode(struct rt2x00_dev *rt2x00dev)
1786{
1787 struct hw_mode_spec *spec = &rt2x00dev->spec;
1788 u8 *txpower;
1789 unsigned int i;
1790
1791 /*
1792 * Initialize all hw fields.
1793 */
1794 rt2x00dev->hw->flags =
1795 IEEE80211_HW_HOST_GEN_BEACON_TEMPLATE |
4150c572 1796 IEEE80211_HW_HOST_BROADCAST_PS_BUFFERING;
95ea3627
ID		 1797 rt2x00dev->hw->extra_tx_headroom = TXD_DESC_SIZE;
1798 rt2x00dev->hw->max_signal = MAX_SIGNAL;
1799 rt2x00dev->hw->max_rssi = MAX_RX_SSI;
871ff6ed 1800 rt2x00dev->hw->queues = 4;
95ea3627
ID		 1801
1802 SET_IEEE80211_DEV(rt2x00dev->hw, &rt2x00dev_usb(rt2x00dev)->dev);
1803 SET_IEEE80211_PERM_ADDR(rt2x00dev->hw,
1804 rt2x00_eeprom_addr(rt2x00dev,
1805 EEPROM_MAC_ADDR_0));
1806
1807 /*
1808 * Convert tx_power array in eeprom.
1809 */
1810 txpower = rt2x00_eeprom_addr(rt2x00dev, EEPROM_TXPOWER_G_START);
1811 for (i = 0; i < 14; i++)
1812 txpower[i] = TXPOWER_FROM_DEV(txpower[i]);
1813
1814 /*
1815 * Initialize hw_mode information.
1816 */
31562e80
ID		 1817 spec->supported_bands = SUPPORT_BAND_2GHZ;
1818 spec->supported_rates = SUPPORT_RATE_CCK | SUPPORT_RATE_OFDM;
95ea3627
ID		 1819 spec->tx_power_a = NULL;
1820 spec->tx_power_bg = txpower;
1821 spec->tx_power_default = DEFAULT_TXPOWER;
1822
1823 if (rt2x00_rf(&rt2x00dev->chip, RF2528)) {
1824 spec->num_channels = ARRAY_SIZE(rf_vals_bg_2528);
1825 spec->channels = rf_vals_bg_2528;
1826 } else if (rt2x00_rf(&rt2x00dev->chip, RF5226)) {
31562e80 1827 spec->supported_bands |= SUPPORT_BAND_5GHZ;
95ea3627
ID		 1828 spec->num_channels = ARRAY_SIZE(rf_vals_5226);
1829 spec->channels = rf_vals_5226;
1830 } else if (rt2x00_rf(&rt2x00dev->chip, RF2527)) {
1831 spec->num_channels = 14;
1832 spec->channels = rf_vals_5225_2527;
1833 } else if (rt2x00_rf(&rt2x00dev->chip, RF5225)) {
31562e80 1834 spec->supported_bands |= SUPPORT_BAND_5GHZ;
95ea3627
ID		 1835 spec->num_channels = ARRAY_SIZE(rf_vals_5225_2527);
1836 spec->channels = rf_vals_5225_2527;
1837 }
1838
1839 if (rt2x00_rf(&rt2x00dev->chip, RF5225) ||
1840 rt2x00_rf(&rt2x00dev->chip, RF5226)) {
95ea3627
ID		 1841 txpower = rt2x00_eeprom_addr(rt2x00dev, EEPROM_TXPOWER_A_START);
1842 for (i = 0; i < 14; i++)
1843 txpower[i] = TXPOWER_FROM_DEV(txpower[i]);
1844
1845 spec->tx_power_a = txpower;
1846 }
1847}
1848
1849static int rt73usb_probe_hw(struct rt2x00_dev *rt2x00dev)
1850{
1851 int retval;
1852
1853 /*
1854 * Allocate eeprom data.
1855 */
1856 retval = rt73usb_validate_eeprom(rt2x00dev);
1857 if (retval)
1858 return retval;
1859
1860 retval = rt73usb_init_eeprom(rt2x00dev);
1861 if (retval)
1862 return retval;
1863
1864 /*
1865 * Initialize hw specifications.
1866 */
1867 rt73usb_probe_hw_mode(rt2x00dev);
1868
1869 /*
9404ef34 1870 * This device requires firmware.
95ea3627 1871 */
066cb637 1872 __set_bit(DRIVER_REQUIRE_FIRMWARE, &rt2x00dev->flags);
95ea3627
ID		 1873
1874 /*
1875 * Set the rssi offset.
1876 */
1877 rt2x00dev->rssi_offset = DEFAULT_RSSI_OFFSET;
1878
1879 return 0;
1880}
1881
1882/*
1883 * IEEE80211 stack callback functions.
1884 */
4150c572
JB		 1885static void rt73usb_configure_filter(struct ieee80211_hw *hw,
1886 unsigned int changed_flags,
1887 unsigned int *total_flags,
1888 int mc_count,
1889 struct dev_addr_list *mc_list)
1890{
1891 struct rt2x00_dev *rt2x00dev = hw->priv;
4150c572
JB		 1892 u32 reg;
1893
1894 /*
1895 * Mask off any flags we are going to ignore from
1896 * the total_flags field.
1897 */
1898 *total_flags &=
1899 FIF_ALLMULTI |
1900 FIF_FCSFAIL |
1901 FIF_PLCPFAIL |
1902 FIF_CONTROL |
1903 FIF_OTHER_BSS |
1904 FIF_PROMISC_IN_BSS;
1905
1906 /*
1907 * Apply some rules to the filters:
1908 * - Some filters imply different filters to be set.
1909 * - Some things we can't filter out at all.
4150c572
JB		 1910 */
1911 if (mc_count)
1912 *total_flags |= FIF_ALLMULTI;
5886d0db
ID		 1913 if (*total_flags & FIF_OTHER_BSS ||
1914 *total_flags & FIF_PROMISC_IN_BSS)
4150c572 1915 *total_flags |= FIF_PROMISC_IN_BSS | FIF_OTHER_BSS;
4150c572
JB		 1916
1917 /*
1918 * Check if there is any work left for us.
1919 */
3c4f2085 1920 if (rt2x00dev->packet_filter == *total_flags)
4150c572 1921 return;
3c4f2085 1922 rt2x00dev->packet_filter = *total_flags;
4150c572
JB		 1923
1924 /*
1925 * When in atomic context, reschedule and let rt2x00lib
1926 * call this function again.
1927 */
1928 if (in_atomic()) {
1929 queue_work(rt2x00dev->hw->workqueue, &rt2x00dev->filter_work);
1930 return;
1931 }
1932
1933 /*
1934 * Start configuration steps.
1935 * Note that the version error will always be dropped
1936 * and broadcast frames will always be accepted since
1937 * there is no filter for it at this time.
1938 */
1939 rt73usb_register_read(rt2x00dev, TXRX_CSR0, &reg);
1940 rt2x00_set_field32(&reg, TXRX_CSR0_DROP_CRC,
1941 !(*total_flags & FIF_FCSFAIL));
1942 rt2x00_set_field32(&reg, TXRX_CSR0_DROP_PHYSICAL,
1943 !(*total_flags & FIF_PLCPFAIL));
1944 rt2x00_set_field32(&reg, TXRX_CSR0_DROP_CONTROL,
1945 !(*total_flags & FIF_CONTROL));
1946 rt2x00_set_field32(&reg, TXRX_CSR0_DROP_NOT_TO_ME,
1947 !(*total_flags & FIF_PROMISC_IN_BSS));
1948 rt2x00_set_field32(&reg, TXRX_CSR0_DROP_TO_DS,
1949 !(*total_flags & FIF_PROMISC_IN_BSS));
1950 rt2x00_set_field32(&reg, TXRX_CSR0_DROP_VERSION_ERROR, 1);
1951 rt2x00_set_field32(&reg, TXRX_CSR0_DROP_MULTICAST,
1952 !(*total_flags & FIF_ALLMULTI));
1953 rt2x00_set_field32(&reg, TXRX_CSR0_DROP_BROADCAST, 0);
e542239f
ID		 1954 rt2x00_set_field32(&reg, TXRX_CSR0_DROP_ACK_CTS,
1955 !(*total_flags & FIF_CONTROL));
4150c572
JB		 1956 rt73usb_register_write(rt2x00dev, TXRX_CSR0, reg);
1957}
1958
95ea3627
ID		 1959static int rt73usb_set_retry_limit(struct ieee80211_hw *hw,
1960 u32 short_retry, u32 long_retry)
1961{
1962 struct rt2x00_dev *rt2x00dev = hw->priv;
1963 u32 reg;
1964
1965 rt73usb_register_read(rt2x00dev, TXRX_CSR4, &reg);
1966 rt2x00_set_field32(&reg, TXRX_CSR4_LONG_RETRY_LIMIT, long_retry);
1967 rt2x00_set_field32(&reg, TXRX_CSR4_SHORT_RETRY_LIMIT, short_retry);
1968 rt73usb_register_write(rt2x00dev, TXRX_CSR4, reg);
1969
1970 return 0;
1971}
1972
1973#if 0
1974/*
1975 * Mac80211 demands get_tsf must be atomic.
1976 * This is not possible for rt73usb since all register access
1977 * functions require sleeping. Untill mac80211 no longer needs
1978 * get_tsf to be atomic, this function should be disabled.
1979 */
1980static u64 rt73usb_get_tsf(struct ieee80211_hw *hw)
1981{
1982 struct rt2x00_dev *rt2x00dev = hw->priv;
1983 u64 tsf;
1984 u32 reg;
1985
1986 rt73usb_register_read(rt2x00dev, TXRX_CSR13, &reg);
1987 tsf = (u64) rt2x00_get_field32(reg, TXRX_CSR13_HIGH_TSFTIMER) << 32;
1988 rt73usb_register_read(rt2x00dev, TXRX_CSR12, &reg);
1989 tsf |= rt2x00_get_field32(reg, TXRX_CSR12_LOW_TSFTIMER);
1990
1991 return tsf;
1992}
37894473
ID		 1993#else
1994#define rt73usb_get_tsf NULL
95ea3627
ID		 1995#endif
1996
24845910 1997static int rt73usb_beacon_update(struct ieee80211_hw *hw, struct sk_buff *skb,
6bb40dd1 1998 struct ieee80211_tx_control *control)
95ea3627
ID		 1999{
2000 struct rt2x00_dev *rt2x00dev = hw->priv;
6bb40dd1 2001 struct rt2x00_intf *intf = vif_to_intf(control->vif);
181d6902 2002 struct skb_frame_desc *skbdesc;
6bb40dd1
ID		 2003 unsigned int beacon_base;
2004 unsigned int timeout;
8af244cc 2005 u32 reg;
95ea3627 2006
6bb40dd1
ID		 2007 if (unlikely(!intf->beacon))
2008 return -ENOBUFS;
95ea3627
ID		 2009
2010 /*
08992f7f 2011 * Add the descriptor in front of the skb.
95ea3627 2012 */
6bb40dd1
ID		 2013 skb_push(skb, intf->beacon->queue->desc_size);
2014 memset(skb->data, 0, intf->beacon->queue->desc_size);
c22eb87b 2015
08992f7f
ID		 2016 /*
2017 * Fill in skb descriptor
2018 */
181d6902
ID		 2019 skbdesc = get_skb_frame_desc(skb);
2020 memset(skbdesc, 0, sizeof(*skbdesc));
baf26a7e 2021 skbdesc->flags |= FRAME_DESC_DRIVER_GENERATED;
6bb40dd1
ID		 2022 skbdesc->data = skb->data + intf->beacon->queue->desc_size;
2023 skbdesc->data_len = skb->len - intf->beacon->queue->desc_size;
181d6902 2024 skbdesc->desc = skb->data;
6bb40dd1
ID		 2025 skbdesc->desc_len = intf->beacon->queue->desc_size;
2026 skbdesc->entry = intf->beacon;
08992f7f 2027
8af244cc
ID		 2028 /*
2029 * Disable beaconing while we are reloading the beacon data,
2030 * otherwise we might be sending out invalid data.
2031 */
2032 rt73usb_register_read(rt2x00dev, TXRX_CSR9, &reg);
2033 rt2x00_set_field32(&reg, TXRX_CSR9_TSF_TICKING, 0);
2034 rt2x00_set_field32(&reg, TXRX_CSR9_TBTT_ENABLE, 0);
2035 rt2x00_set_field32(&reg, TXRX_CSR9_BEACON_GEN, 0);
2036 rt73usb_register_write(rt2x00dev, TXRX_CSR9, reg);
2037
6bb40dd1 2038 /*
5957da4c
ID		 2039 * mac80211 doesn't provide the control->queue variable
2040 * for beacons. Set our own queue identification so
2041 * it can be used during descriptor initialization.
6bb40dd1 2042 */
5957da4c 2043 control->queue = RT2X00_BCN_QUEUE_BEACON;
08992f7f 2044 rt2x00lib_write_tx_desc(rt2x00dev, skb, control);
95ea3627
ID		 2045
2046 /*
2047 * Write entire beacon with descriptor to register,
2048 * and kick the beacon generator.
2049 */
6bb40dd1 2050 beacon_base = HW_BEACON_OFFSET(intf->beacon->entry_idx);
95ea3627
ID		 2051 timeout = REGISTER_TIMEOUT * (skb->len / sizeof(u32));
2052 rt2x00usb_vendor_request(rt2x00dev, USB_MULTI_WRITE,
6bb40dd1 2053 USB_VENDOR_REQUEST_OUT, beacon_base, 0,
95ea3627 2054 skb->data, skb->len, timeout);
6bb40dd1 2055 rt73usb_kick_tx_queue(rt2x00dev, control->queue);
95ea3627
ID		 2056
2057 return 0;
2058}
2059
2060static const struct ieee80211_ops rt73usb_mac80211_ops = {
2061 .tx = rt2x00mac_tx,
4150c572
JB		 2062 .start = rt2x00mac_start,
2063 .stop = rt2x00mac_stop,
95ea3627
ID		 2064 .add_interface = rt2x00mac_add_interface,
2065 .remove_interface = rt2x00mac_remove_interface,
2066 .config = rt2x00mac_config,
2067 .config_interface = rt2x00mac_config_interface,
4150c572 2068 .configure_filter = rt73usb_configure_filter,
95ea3627
ID		 2069 .get_stats = rt2x00mac_get_stats,
2070 .set_retry_limit = rt73usb_set_retry_limit,
471b3efd 2071 .bss_info_changed = rt2x00mac_bss_info_changed,
95ea3627
ID		 2072 .conf_tx = rt2x00mac_conf_tx,
2073 .get_tx_stats = rt2x00mac_get_tx_stats,
95ea3627 2074 .get_tsf = rt73usb_get_tsf,
95ea3627
ID		 2075 .beacon_update = rt73usb_beacon_update,
2076};
2077
2078static const struct rt2x00lib_ops rt73usb_rt2x00_ops = {
2079 .probe_hw = rt73usb_probe_hw,
2080 .get_firmware_name = rt73usb_get_firmware_name,
a7f3a06c 2081 .get_firmware_crc = rt73usb_get_firmware_crc,
95ea3627
ID		 2082 .load_firmware = rt73usb_load_firmware,
2083 .initialize = rt2x00usb_initialize,
2084 .uninitialize = rt2x00usb_uninitialize,
837e7f24
ID		 2085 .init_rxentry = rt2x00usb_init_rxentry,
2086 .init_txentry = rt2x00usb_init_txentry,
95ea3627
ID		 2087 .set_device_state = rt73usb_set_device_state,
2088 .link_stats = rt73usb_link_stats,
2089 .reset_tuner = rt73usb_reset_tuner,
2090 .link_tuner = rt73usb_link_tuner,
a9450b70 2091 .led_brightness = rt73usb_led_brightness,
95ea3627
ID		 2092 .write_tx_desc = rt73usb_write_tx_desc,
2093 .write_tx_data = rt2x00usb_write_tx_data,
dd9fa2d2 2094 .get_tx_data_len = rt73usb_get_tx_data_len,
95ea3627
ID		 2095 .kick_tx_queue = rt73usb_kick_tx_queue,
2096 .fill_rxdone = rt73usb_fill_rxdone,
6bb40dd1 2097 .config_intf = rt73usb_config_intf,
5c58ee51 2098 .config_preamble = rt73usb_config_preamble,
95ea3627
ID		 2099 .config = rt73usb_config,
2100};
2101
181d6902
ID		 2102static const struct data_queue_desc rt73usb_queue_rx = {
2103 .entry_num = RX_ENTRIES,
2104 .data_size = DATA_FRAME_SIZE,
2105 .desc_size = RXD_DESC_SIZE,
2106 .priv_size = sizeof(struct queue_entry_priv_usb_rx),
2107};
2108
2109static const struct data_queue_desc rt73usb_queue_tx = {
2110 .entry_num = TX_ENTRIES,
2111 .data_size = DATA_FRAME_SIZE,
2112 .desc_size = TXD_DESC_SIZE,
2113 .priv_size = sizeof(struct queue_entry_priv_usb_tx),
2114};
2115
2116static const struct data_queue_desc rt73usb_queue_bcn = {
6bb40dd1 2117 .entry_num = 4 * BEACON_ENTRIES,
181d6902
ID		 2118 .data_size = MGMT_FRAME_SIZE,
2119 .desc_size = TXINFO_SIZE,
2120 .priv_size = sizeof(struct queue_entry_priv_usb_tx),
2121};
2122
95ea3627 2123static const struct rt2x00_ops rt73usb_ops = {
2360157c 2124 .name = KBUILD_MODNAME,
6bb40dd1
ID		 2125 .max_sta_intf = 1,
2126 .max_ap_intf = 4,
95ea3627
ID		 2127 .eeprom_size = EEPROM_SIZE,
2128 .rf_size = RF_SIZE,
181d6902
ID		 2129 .rx = &rt73usb_queue_rx,
2130 .tx = &rt73usb_queue_tx,
2131 .bcn = &rt73usb_queue_bcn,
95ea3627
ID		 2132 .lib = &rt73usb_rt2x00_ops,
2133 .hw = &rt73usb_mac80211_ops,
2134#ifdef CONFIG_RT2X00_LIB_DEBUGFS
2135 .debugfs = &rt73usb_rt2x00debug,
2136#endif /* CONFIG_RT2X00_LIB_DEBUGFS */
2137};
2138
2139/*
2140 * rt73usb module information.
2141 */
2142static struct usb_device_id rt73usb_device_table[] = {
2143 /* AboCom */
2144 { USB_DEVICE(0x07b8, 0xb21d), USB_DEVICE_DATA(&rt73usb_ops) },
2145 /* Askey */
2146 { USB_DEVICE(0x1690, 0x0722), USB_DEVICE_DATA(&rt73usb_ops) },
2147 /* ASUS */
2148 { USB_DEVICE(0x0b05, 0x1723), USB_DEVICE_DATA(&rt73usb_ops) },
2149 { USB_DEVICE(0x0b05, 0x1724), USB_DEVICE_DATA(&rt73usb_ops) },
2150 /* Belkin */
2151 { USB_DEVICE(0x050d, 0x7050), USB_DEVICE_DATA(&rt73usb_ops) },
2152 { USB_DEVICE(0x050d, 0x705a), USB_DEVICE_DATA(&rt73usb_ops) },
2153 { USB_DEVICE(0x050d, 0x905b), USB_DEVICE_DATA(&rt73usb_ops) },
1f06862e 2154 { USB_DEVICE(0x050d, 0x905c), USB_DEVICE_DATA(&rt73usb_ops) },
95ea3627
ID		 2155 /* Billionton */
2156 { USB_DEVICE(0x1631, 0xc019), USB_DEVICE_DATA(&rt73usb_ops) },
2157 /* Buffalo */
2158 { USB_DEVICE(0x0411, 0x00f4), USB_DEVICE_DATA(&rt73usb_ops) },
2159 /* CNet */
2160 { USB_DEVICE(0x1371, 0x9022), USB_DEVICE_DATA(&rt73usb_ops) },
2161 { USB_DEVICE(0x1371, 0x9032), USB_DEVICE_DATA(&rt73usb_ops) },
2162 /* Conceptronic */
2163 { USB_DEVICE(0x14b2, 0x3c22), USB_DEVICE_DATA(&rt73usb_ops) },
2164 /* D-Link */
2165 { USB_DEVICE(0x07d1, 0x3c03), USB_DEVICE_DATA(&rt73usb_ops) },
2166 { USB_DEVICE(0x07d1, 0x3c04), USB_DEVICE_DATA(&rt73usb_ops) },
2167 /* Gemtek */
2168 { USB_DEVICE(0x15a9, 0x0004), USB_DEVICE_DATA(&rt73usb_ops) },
2169 /* Gigabyte */
2170 { USB_DEVICE(0x1044, 0x8008), USB_DEVICE_DATA(&rt73usb_ops) },
2171 { USB_DEVICE(0x1044, 0x800a), USB_DEVICE_DATA(&rt73usb_ops) },
2172 /* Huawei-3Com */
2173 { USB_DEVICE(0x1472, 0x0009), USB_DEVICE_DATA(&rt73usb_ops) },
2174 /* Hercules */
2175 { USB_DEVICE(0x06f8, 0xe010), USB_DEVICE_DATA(&rt73usb_ops) },
2176 { USB_DEVICE(0x06f8, 0xe020), USB_DEVICE_DATA(&rt73usb_ops) },
2177 /* Linksys */
2178 { USB_DEVICE(0x13b1, 0x0020), USB_DEVICE_DATA(&rt73usb_ops) },
2179 { USB_DEVICE(0x13b1, 0x0023), USB_DEVICE_DATA(&rt73usb_ops) },
2180 /* MSI */
2181 { USB_DEVICE(0x0db0, 0x6877), USB_DEVICE_DATA(&rt73usb_ops) },
2182 { USB_DEVICE(0x0db0, 0x6874), USB_DEVICE_DATA(&rt73usb_ops) },
2183 { USB_DEVICE(0x0db0, 0xa861), USB_DEVICE_DATA(&rt73usb_ops) },
2184 { USB_DEVICE(0x0db0, 0xa874), USB_DEVICE_DATA(&rt73usb_ops) },
2185 /* Ralink */
2186 { USB_DEVICE(0x148f, 0x2573), USB_DEVICE_DATA(&rt73usb_ops) },
2187 { USB_DEVICE(0x148f, 0x2671), USB_DEVICE_DATA(&rt73usb_ops) },
2188 /* Qcom */
2189 { USB_DEVICE(0x18e8, 0x6196), USB_DEVICE_DATA(&rt73usb_ops) },
2190 { USB_DEVICE(0x18e8, 0x6229), USB_DEVICE_DATA(&rt73usb_ops) },
2191 { USB_DEVICE(0x18e8, 0x6238), USB_DEVICE_DATA(&rt73usb_ops) },
2192 /* Senao */
2193 { USB_DEVICE(0x1740, 0x7100), USB_DEVICE_DATA(&rt73usb_ops) },
2194 /* Sitecom */
2195 { USB_DEVICE(0x0df6, 0x9712), USB_DEVICE_DATA(&rt73usb_ops) },
2196 { USB_DEVICE(0x0df6, 0x90ac), USB_DEVICE_DATA(&rt73usb_ops) },
2197 /* Surecom */
2198 { USB_DEVICE(0x0769, 0x31f3), USB_DEVICE_DATA(&rt73usb_ops) },
2199 /* Planex */
2200 { USB_DEVICE(0x2019, 0xab01), USB_DEVICE_DATA(&rt73usb_ops) },
2201 { USB_DEVICE(0x2019, 0xab50), USB_DEVICE_DATA(&rt73usb_ops) },
2202 { 0, }
2203};
2204
2205MODULE_AUTHOR(DRV_PROJECT);
2206MODULE_VERSION(DRV_VERSION);
2207MODULE_DESCRIPTION("Ralink RT73 USB Wireless LAN driver.");
2208MODULE_SUPPORTED_DEVICE("Ralink RT2571W & RT2671 USB chipset based cards");
2209MODULE_DEVICE_TABLE(usb, rt73usb_device_table);
2210MODULE_FIRMWARE(FIRMWARE_RT2571);
2211MODULE_LICENSE("GPL");
2212
2213static struct usb_driver rt73usb_driver = {
2360157c 2214 .name = KBUILD_MODNAME,
95ea3627
ID		 2215 .id_table = rt73usb_device_table,
2216 .probe = rt2x00usb_probe,
2217 .disconnect = rt2x00usb_disconnect,
2218 .suspend = rt2x00usb_suspend,
2219 .resume = rt2x00usb_resume,
2220};
2221
2222static int __init rt73usb_init(void)
2223{
2224 return usb_register(&rt73usb_driver);
2225}
2226
2227static void __exit rt73usb_exit(void)
2228{
2229 usb_deregister(&rt73usb_driver);
2230}
2231
2232module_init(rt73usb_init);
2233module_exit(rt73usb_exit);
Linux kernel - Deliverables
This page took 0.232607 seconds and 5 git commands to generate.