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iwlwifi: fix aggregation limit
[deliverable/linux.git] / drivers / net / wireless / rt2x00 / rt73usb.c
CommitLineData
95ea3627 1/*
4e54c711 2 Copyright (C) 2004 - 2009 rt2x00 SourceForge Project
95ea3627
ID		 3 <http://rt2x00.serialmonkey.com>
4
5 This program is free software; you can redistribute it and/or modify
6 it under the terms of the GNU General Public License as published by
7 the Free Software Foundation; either version 2 of the License, or
8 (at your option) any later version.
9
10 This program is distributed in the hope that it will be useful,
11 but WITHOUT ANY WARRANTY; without even the implied warranty of
12 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 GNU General Public License for more details.
14
15 You should have received a copy of the GNU General Public License
16 along with this program; if not, write to the
17 Free Software Foundation, Inc.,
18 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
19 */
20
21/*
22 Module: rt73usb
23 Abstract: rt73usb device specific routines.
24 Supported chipsets: rt2571W & rt2671.
25 */
26
a7f3a06c 27#include <linux/crc-itu-t.h>
95ea3627
ID		 28#include <linux/delay.h>
29#include <linux/etherdevice.h>
30#include <linux/init.h>
31#include <linux/kernel.h>
32#include <linux/module.h>
33#include <linux/usb.h>
34
35#include "rt2x00.h"
36#include "rt2x00usb.h"
37#include "rt73usb.h"
38
008c4482
ID		 39/*
40 * Allow hardware encryption to be disabled.
41 */
42static int modparam_nohwcrypt = 0;
43module_param_named(nohwcrypt, modparam_nohwcrypt, bool, S_IRUGO);
44MODULE_PARM_DESC(nohwcrypt, "Disable hardware encryption.");
45
95ea3627
ID		 46/*
47 * Register access.
48 * All access to the CSR registers will go through the methods
0f829b1d 49 * rt2x00usb_register_read and rt2x00usb_register_write.
95ea3627
ID		 50 * BBP and RF register require indirect register access,
51 * and use the CSR registers BBPCSR and RFCSR to achieve this.
52 * These indirect registers work with busy bits,
53 * and we will try maximal REGISTER_BUSY_COUNT times to access
54 * the register while taking a REGISTER_BUSY_DELAY us delay
55 * between each attampt. When the busy bit is still set at that time,
56 * the access attempt is considered to have failed,
57 * and we will print an error.
8ff48a8b 58 * The _lock versions must be used if you already hold the csr_mutex
95ea3627 59 */
c9c3b1a5 60#define WAIT_FOR_BBP(__dev, __reg) \
0f829b1d 61 rt2x00usb_regbusy_read((__dev), PHY_CSR3, PHY_CSR3_BUSY, (__reg))
c9c3b1a5 62#define WAIT_FOR_RF(__dev, __reg) \
0f829b1d 63 rt2x00usb_regbusy_read((__dev), PHY_CSR4, PHY_CSR4_BUSY, (__reg))
c9c3b1a5 64
0e14f6d3 65static void rt73usb_bbp_write(struct rt2x00_dev *rt2x00dev,
95ea3627
ID		 66 const unsigned int word, const u8 value)
67{
68 u32 reg;
69
8ff48a8b 70 mutex_lock(&rt2x00dev->csr_mutex);
3d82346c 71
95ea3627 72 /*
c9c3b1a5
ID		 73 * Wait until the BBP becomes available, afterwards we
74 * can safely write the new data into the register.
95ea3627 75 */
c9c3b1a5
ID		 76 if (WAIT_FOR_BBP(rt2x00dev, &reg)) {
77 reg = 0;
78 rt2x00_set_field32(&reg, PHY_CSR3_VALUE, value);
79 rt2x00_set_field32(&reg, PHY_CSR3_REGNUM, word);
80 rt2x00_set_field32(&reg, PHY_CSR3_BUSY, 1);
81 rt2x00_set_field32(&reg, PHY_CSR3_READ_CONTROL, 0);
82
0f829b1d 83 rt2x00usb_register_write_lock(rt2x00dev, PHY_CSR3, reg);
c9c3b1a5 84 }
99ade259 85
8ff48a8b 86 mutex_unlock(&rt2x00dev->csr_mutex);
95ea3627
ID		 87}
88
0e14f6d3 89static void rt73usb_bbp_read(struct rt2x00_dev *rt2x00dev,
95ea3627
ID		 90 const unsigned int word, u8 *value)
91{
92 u32 reg;
93
8ff48a8b 94 mutex_lock(&rt2x00dev->csr_mutex);
3d82346c 95
95ea3627 96 /*
c9c3b1a5
ID		 97 * Wait until the BBP becomes available, afterwards we
98 * can safely write the read request into the register.
99 * After the data has been written, we wait until hardware
100 * returns the correct value, if at any time the register
101 * doesn't become available in time, reg will be 0xffffffff
102 * which means we return 0xff to the caller.
95ea3627 103 */
c9c3b1a5
ID		 104 if (WAIT_FOR_BBP(rt2x00dev, &reg)) {
105 reg = 0;
106 rt2x00_set_field32(&reg, PHY_CSR3_REGNUM, word);
107 rt2x00_set_field32(&reg, PHY_CSR3_BUSY, 1);
108 rt2x00_set_field32(&reg, PHY_CSR3_READ_CONTROL, 1);
95ea3627 109
0f829b1d 110 rt2x00usb_register_write_lock(rt2x00dev, PHY_CSR3, reg);
95ea3627 111
c9c3b1a5
ID		 112 WAIT_FOR_BBP(rt2x00dev, &reg);
113 }
95ea3627
ID		 114
115 *value = rt2x00_get_field32(reg, PHY_CSR3_VALUE);
99ade259 116
8ff48a8b 117 mutex_unlock(&rt2x00dev->csr_mutex);
95ea3627
ID		 118}
119
0e14f6d3 120static void rt73usb_rf_write(struct rt2x00_dev *rt2x00dev,
95ea3627
ID		 121 const unsigned int word, const u32 value)
122{
123 u32 reg;
95ea3627 124
8ff48a8b 125 mutex_lock(&rt2x00dev->csr_mutex);
3d82346c 126
4f5af6eb 127 /*
c9c3b1a5
ID		 128 * Wait until the RF becomes available, afterwards we
129 * can safely write the new data into the register.
4f5af6eb 130 */
c9c3b1a5
ID		 131 if (WAIT_FOR_RF(rt2x00dev, &reg)) {
132 reg = 0;
133 rt2x00_set_field32(&reg, PHY_CSR4_VALUE, value);
134 /*
135 * RF5225 and RF2527 contain 21 bits per RF register value,
136 * all others contain 20 bits.
137 */
138 rt2x00_set_field32(&reg, PHY_CSR4_NUMBER_OF_BITS,
139 20 + (rt2x00_rf(&rt2x00dev->chip, RF5225) ||
140 rt2x00_rf(&rt2x00dev->chip, RF2527)));
141 rt2x00_set_field32(&reg, PHY_CSR4_IF_SELECT, 0);
142 rt2x00_set_field32(&reg, PHY_CSR4_BUSY, 1);
143
0f829b1d 144 rt2x00usb_register_write_lock(rt2x00dev, PHY_CSR4, reg);
c9c3b1a5
ID		 145 rt2x00_rf_write(rt2x00dev, word, value);
146 }
8ff48a8b
ID		 147
148 mutex_unlock(&rt2x00dev->csr_mutex);
95ea3627
ID		 149}
150
151#ifdef CONFIG_RT2X00_LIB_DEBUGFS
95ea3627
ID		 152static const struct rt2x00debug rt73usb_rt2x00debug = {
153 .owner = THIS_MODULE,
154 .csr = {
0f829b1d
ID		 155 .read = rt2x00usb_register_read,
156 .write = rt2x00usb_register_write,
743b97ca
ID		 157 .flags = RT2X00DEBUGFS_OFFSET,
158 .word_base = CSR_REG_BASE,
95ea3627
ID		 159 .word_size = sizeof(u32),
160 .word_count = CSR_REG_SIZE / sizeof(u32),
161 },
162 .eeprom = {
163 .read = rt2x00_eeprom_read,
164 .write = rt2x00_eeprom_write,
743b97ca 165 .word_base = EEPROM_BASE,
95ea3627
ID		 166 .word_size = sizeof(u16),
167 .word_count = EEPROM_SIZE / sizeof(u16),
168 },
169 .bbp = {
170 .read = rt73usb_bbp_read,
171 .write = rt73usb_bbp_write,
743b97ca 172 .word_base = BBP_BASE,
95ea3627
ID		 173 .word_size = sizeof(u8),
174 .word_count = BBP_SIZE / sizeof(u8),
175 },
176 .rf = {
177 .read = rt2x00_rf_read,
178 .write = rt73usb_rf_write,
743b97ca 179 .word_base = RF_BASE,
95ea3627
ID		 180 .word_size = sizeof(u32),
181 .word_count = RF_SIZE / sizeof(u32),
182 },
183};
184#endif /* CONFIG_RT2X00_LIB_DEBUGFS */
185
7396faf4
ID		 186#ifdef CONFIG_RT2X00_LIB_RFKILL
187static int rt73usb_rfkill_poll(struct rt2x00_dev *rt2x00dev)
188{
189 u32 reg;
190
191 rt2x00usb_register_read(rt2x00dev, MAC_CSR13, &reg);
192 return rt2x00_get_field32(reg, MAC_CSR13_BIT7);
193}
194#else
195#define rt73usb_rfkill_poll NULL
196#endif /* CONFIG_RT2X00_LIB_RFKILL */
197
771fd565 198#ifdef CONFIG_RT2X00_LIB_LEDS
a2e1d52a 199static void rt73usb_brightness_set(struct led_classdev *led_cdev,
a9450b70
ID		 200 enum led_brightness brightness)
201{
202 struct rt2x00_led *led =
203 container_of(led_cdev, struct rt2x00_led, led_dev);
204 unsigned int enabled = brightness != LED_OFF;
205 unsigned int a_mode =
206 (enabled && led->rt2x00dev->curr_band == IEEE80211_BAND_5GHZ);
207 unsigned int bg_mode =
208 (enabled && led->rt2x00dev->curr_band == IEEE80211_BAND_2GHZ);
209
210 if (led->type == LED_TYPE_RADIO) {
211 rt2x00_set_field16(&led->rt2x00dev->led_mcu_reg,
212 MCU_LEDCS_RADIO_STATUS, enabled);
213
47b10cd1
ID		 214 rt2x00usb_vendor_request_sw(led->rt2x00dev, USB_LED_CONTROL,
215 0, led->rt2x00dev->led_mcu_reg,
216 REGISTER_TIMEOUT);
a9450b70
ID		 217 } else if (led->type == LED_TYPE_ASSOC) {
218 rt2x00_set_field16(&led->rt2x00dev->led_mcu_reg,
219 MCU_LEDCS_LINK_BG_STATUS, bg_mode);
220 rt2x00_set_field16(&led->rt2x00dev->led_mcu_reg,
221 MCU_LEDCS_LINK_A_STATUS, a_mode);
222
47b10cd1
ID		 223 rt2x00usb_vendor_request_sw(led->rt2x00dev, USB_LED_CONTROL,
224 0, led->rt2x00dev->led_mcu_reg,
225 REGISTER_TIMEOUT);
a9450b70
ID		 226 } else if (led->type == LED_TYPE_QUALITY) {
227 /*
228 * The brightness is divided into 6 levels (0 - 5),
229 * this means we need to convert the brightness
230 * argument into the matching level within that range.
231 */
47b10cd1
ID		 232 rt2x00usb_vendor_request_sw(led->rt2x00dev, USB_LED_CONTROL,
233 brightness / (LED_FULL / 6),
234 led->rt2x00dev->led_mcu_reg,
235 REGISTER_TIMEOUT);
a9450b70
ID		 236 }
237}
a2e1d52a
ID		 238
239static int rt73usb_blink_set(struct led_classdev *led_cdev,
240 unsigned long *delay_on,
241 unsigned long *delay_off)
242{
243 struct rt2x00_led *led =
244 container_of(led_cdev, struct rt2x00_led, led_dev);
245 u32 reg;
246
0f829b1d 247 rt2x00usb_register_read(led->rt2x00dev, MAC_CSR14, &reg);
a2e1d52a
ID		 248 rt2x00_set_field32(&reg, MAC_CSR14_ON_PERIOD, *delay_on);
249 rt2x00_set_field32(&reg, MAC_CSR14_OFF_PERIOD, *delay_off);
0f829b1d 250 rt2x00usb_register_write(led->rt2x00dev, MAC_CSR14, reg);
a2e1d52a
ID		 251
252 return 0;
253}
475433be
ID		 254
255static void rt73usb_init_led(struct rt2x00_dev *rt2x00dev,
256 struct rt2x00_led *led,
257 enum led_type type)
258{
259 led->rt2x00dev = rt2x00dev;
260 led->type = type;
261 led->led_dev.brightness_set = rt73usb_brightness_set;
262 led->led_dev.blink_set = rt73usb_blink_set;
263 led->flags = LED_INITIALIZED;
264}
771fd565 265#endif /* CONFIG_RT2X00_LIB_LEDS */
a9450b70 266
95ea3627
ID		 267/*
268 * Configuration handlers.
269 */
906c110f
ID		 270static int rt73usb_config_shared_key(struct rt2x00_dev *rt2x00dev,
271 struct rt2x00lib_crypto *crypto,
272 struct ieee80211_key_conf *key)
273{
274 struct hw_key_entry key_entry;
275 struct rt2x00_field32 field;
276 int timeout;
277 u32 mask;
278 u32 reg;
279
280 if (crypto->cmd == SET_KEY) {
281 /*
282 * rt2x00lib can't determine the correct free
283 * key_idx for shared keys. We have 1 register
284 * with key valid bits. The goal is simple, read
285 * the register, if that is full we have no slots
286 * left.
287 * Note that each BSS is allowed to have up to 4
288 * shared keys, so put a mask over the allowed
289 * entries.
290 */
291 mask = (0xf << crypto->bssidx);
292
0f829b1d 293 rt2x00usb_register_read(rt2x00dev, SEC_CSR0, &reg);
906c110f
ID		 294 reg &= mask;
295
296 if (reg && reg == mask)
297 return -ENOSPC;
298
acaf908d 299 key->hw_key_idx += reg ? ffz(reg) : 0;
906c110f
ID		 300
301 /*
302 * Upload key to hardware
303 */
304 memcpy(key_entry.key, crypto->key,
305 sizeof(key_entry.key));
306 memcpy(key_entry.tx_mic, crypto->tx_mic,
307 sizeof(key_entry.tx_mic));
308 memcpy(key_entry.rx_mic, crypto->rx_mic,
309 sizeof(key_entry.rx_mic));
310
311 reg = SHARED_KEY_ENTRY(key->hw_key_idx);
312 timeout = REGISTER_TIMEOUT32(sizeof(key_entry));
313 rt2x00usb_vendor_request_large_buff(rt2x00dev, USB_MULTI_WRITE,
314 USB_VENDOR_REQUEST_OUT, reg,
315 &key_entry,
316 sizeof(key_entry),
317 timeout);
318
319 /*
320 * The cipher types are stored over 2 registers.
321 * bssidx 0 and 1 keys are stored in SEC_CSR1 and
322 * bssidx 1 and 2 keys are stored in SEC_CSR5.
323 * Using the correct defines correctly will cause overhead,
324 * so just calculate the correct offset.
325 */
326 if (key->hw_key_idx < 8) {
327 field.bit_offset = (3 * key->hw_key_idx);
328 field.bit_mask = 0x7 << field.bit_offset;
329
0f829b1d 330 rt2x00usb_register_read(rt2x00dev, SEC_CSR1, &reg);
906c110f 331 rt2x00_set_field32(&reg, field, crypto->cipher);
0f829b1d 332 rt2x00usb_register_write(rt2x00dev, SEC_CSR1, reg);
906c110f
ID		 333 } else {
334 field.bit_offset = (3 * (key->hw_key_idx - 8));
335 field.bit_mask = 0x7 << field.bit_offset;
336
0f829b1d 337 rt2x00usb_register_read(rt2x00dev, SEC_CSR5, &reg);
906c110f 338 rt2x00_set_field32(&reg, field, crypto->cipher);
0f829b1d 339 rt2x00usb_register_write(rt2x00dev, SEC_CSR5, reg);
906c110f
ID		 340 }
341
342 /*
343 * The driver does not support the IV/EIV generation
344 * in hardware. However it doesn't support the IV/EIV
345 * inside the ieee80211 frame either, but requires it
346 * to be provided seperately for the descriptor.
347 * rt2x00lib will cut the IV/EIV data out of all frames
348 * given to us by mac80211, but we must tell mac80211
349 * to generate the IV/EIV data.
350 */
351 key->flags |= IEEE80211_KEY_FLAG_GENERATE_IV;
352 }
353
354 /*
355 * SEC_CSR0 contains only single-bit fields to indicate
356 * a particular key is valid. Because using the FIELD32()
357 * defines directly will cause a lot of overhead we use
358 * a calculation to determine the correct bit directly.
359 */
360 mask = 1 << key->hw_key_idx;
361
0f829b1d 362 rt2x00usb_register_read(rt2x00dev, SEC_CSR0, &reg);
906c110f
ID		 363 if (crypto->cmd == SET_KEY)
364 reg |= mask;
365 else if (crypto->cmd == DISABLE_KEY)
366 reg &= ~mask;
0f829b1d 367 rt2x00usb_register_write(rt2x00dev, SEC_CSR0, reg);
906c110f
ID		 368
369 return 0;
370}
371
372static int rt73usb_config_pairwise_key(struct rt2x00_dev *rt2x00dev,
373 struct rt2x00lib_crypto *crypto,
374 struct ieee80211_key_conf *key)
375{
376 struct hw_pairwise_ta_entry addr_entry;
377 struct hw_key_entry key_entry;
378 int timeout;
379 u32 mask;
380 u32 reg;
381
382 if (crypto->cmd == SET_KEY) {
383 /*
384 * rt2x00lib can't determine the correct free
385 * key_idx for pairwise keys. We have 2 registers
386 * with key valid bits. The goal is simple, read
387 * the first register, if that is full move to
388 * the next register.
389 * When both registers are full, we drop the key,
390 * otherwise we use the first invalid entry.
391 */
0f829b1d 392 rt2x00usb_register_read(rt2x00dev, SEC_CSR2, &reg);
906c110f
ID		 393 if (reg && reg == ~0) {
394 key->hw_key_idx = 32;
0f829b1d 395 rt2x00usb_register_read(rt2x00dev, SEC_CSR3, &reg);
906c110f
ID		 396 if (reg && reg == ~0)
397 return -ENOSPC;
398 }
399
acaf908d 400 key->hw_key_idx += reg ? ffz(reg) : 0;
906c110f
ID		 401
402 /*
403 * Upload key to hardware
404 */
405 memcpy(key_entry.key, crypto->key,
406 sizeof(key_entry.key));
407 memcpy(key_entry.tx_mic, crypto->tx_mic,
408 sizeof(key_entry.tx_mic));
409 memcpy(key_entry.rx_mic, crypto->rx_mic,
410 sizeof(key_entry.rx_mic));
411
412 reg = PAIRWISE_KEY_ENTRY(key->hw_key_idx);
413 timeout = REGISTER_TIMEOUT32(sizeof(key_entry));
414 rt2x00usb_vendor_request_large_buff(rt2x00dev, USB_MULTI_WRITE,
415 USB_VENDOR_REQUEST_OUT, reg,
416 &key_entry,
417 sizeof(key_entry),
418 timeout);
419
420 /*
421 * Send the address and cipher type to the hardware register.
422 * This data fits within the CSR cache size, so we can use
0f829b1d 423 * rt2x00usb_register_multiwrite() directly.
906c110f
ID		 424 */
425 memset(&addr_entry, 0, sizeof(addr_entry));
426 memcpy(&addr_entry, crypto->address, ETH_ALEN);
427 addr_entry.cipher = crypto->cipher;
428
429 reg = PAIRWISE_TA_ENTRY(key->hw_key_idx);
0f829b1d 430 rt2x00usb_register_multiwrite(rt2x00dev, reg,
906c110f
ID		 431 &addr_entry, sizeof(addr_entry));
432
433 /*
434 * Enable pairwise lookup table for given BSS idx,
435 * without this received frames will not be decrypted
436 * by the hardware.
437 */
0f829b1d 438 rt2x00usb_register_read(rt2x00dev, SEC_CSR4, &reg);
906c110f 439 reg |= (1 << crypto->bssidx);
0f829b1d 440 rt2x00usb_register_write(rt2x00dev, SEC_CSR4, reg);
906c110f
ID		 441
442 /*
443 * The driver does not support the IV/EIV generation
444 * in hardware. However it doesn't support the IV/EIV
445 * inside the ieee80211 frame either, but requires it
446 * to be provided seperately for the descriptor.
447 * rt2x00lib will cut the IV/EIV data out of all frames
448 * given to us by mac80211, but we must tell mac80211
449 * to generate the IV/EIV data.
450 */
451 key->flags |= IEEE80211_KEY_FLAG_GENERATE_IV;
452 }
453
454 /*
455 * SEC_CSR2 and SEC_CSR3 contain only single-bit fields to indicate
456 * a particular key is valid. Because using the FIELD32()
457 * defines directly will cause a lot of overhead we use
458 * a calculation to determine the correct bit directly.
459 */
460 if (key->hw_key_idx < 32) {
461 mask = 1 << key->hw_key_idx;
462
0f829b1d 463 rt2x00usb_register_read(rt2x00dev, SEC_CSR2, &reg);
906c110f
ID		 464 if (crypto->cmd == SET_KEY)
465 reg |= mask;
466 else if (crypto->cmd == DISABLE_KEY)
467 reg &= ~mask;
0f829b1d 468 rt2x00usb_register_write(rt2x00dev, SEC_CSR2, reg);
906c110f
ID		 469 } else {
470 mask = 1 << (key->hw_key_idx - 32);
471
0f829b1d 472 rt2x00usb_register_read(rt2x00dev, SEC_CSR3, &reg);
906c110f
ID		 473 if (crypto->cmd == SET_KEY)
474 reg |= mask;
475 else if (crypto->cmd == DISABLE_KEY)
476 reg &= ~mask;
0f829b1d 477 rt2x00usb_register_write(rt2x00dev, SEC_CSR3, reg);
906c110f
ID		 478 }
479
480 return 0;
481}
482
3a643d24
ID		 483static void rt73usb_config_filter(struct rt2x00_dev *rt2x00dev,
484 const unsigned int filter_flags)
485{
486 u32 reg;
487
488 /*
489 * Start configuration steps.
490 * Note that the version error will always be dropped
491 * and broadcast frames will always be accepted since
492 * there is no filter for it at this time.
493 */
0f829b1d 494 rt2x00usb_register_read(rt2x00dev, TXRX_CSR0, &reg);
3a643d24
ID		 495 rt2x00_set_field32(&reg, TXRX_CSR0_DROP_CRC,
496 !(filter_flags & FIF_FCSFAIL));
497 rt2x00_set_field32(&reg, TXRX_CSR0_DROP_PHYSICAL,
498 !(filter_flags & FIF_PLCPFAIL));
499 rt2x00_set_field32(&reg, TXRX_CSR0_DROP_CONTROL,
500 !(filter_flags & FIF_CONTROL));
501 rt2x00_set_field32(&reg, TXRX_CSR0_DROP_NOT_TO_ME,
502 !(filter_flags & FIF_PROMISC_IN_BSS));
503 rt2x00_set_field32(&reg, TXRX_CSR0_DROP_TO_DS,
e0b005fa
ID		 504 !(filter_flags & FIF_PROMISC_IN_BSS) &&
505 !rt2x00dev->intf_ap_count);
3a643d24
ID		 506 rt2x00_set_field32(&reg, TXRX_CSR0_DROP_VERSION_ERROR, 1);
507 rt2x00_set_field32(&reg, TXRX_CSR0_DROP_MULTICAST,
508 !(filter_flags & FIF_ALLMULTI));
509 rt2x00_set_field32(&reg, TXRX_CSR0_DROP_BROADCAST, 0);
510 rt2x00_set_field32(&reg, TXRX_CSR0_DROP_ACK_CTS,
511 !(filter_flags & FIF_CONTROL));
0f829b1d 512 rt2x00usb_register_write(rt2x00dev, TXRX_CSR0, reg);
3a643d24
ID		 513}
514
6bb40dd1
ID		 515static void rt73usb_config_intf(struct rt2x00_dev *rt2x00dev,
516 struct rt2x00_intf *intf,
517 struct rt2x00intf_conf *conf,
518 const unsigned int flags)
95ea3627 519{
6bb40dd1
ID		 520 unsigned int beacon_base;
521 u32 reg;
95ea3627 522
6bb40dd1
ID		 523 if (flags & CONFIG_UPDATE_TYPE) {
524 /*
525 * Clear current synchronisation setup.
526 * For the Beacon base registers we only need to clear
527 * the first byte since that byte contains the VALID and OWNER
528 * bits which (when set to 0) will invalidate the entire beacon.
529 */
530 beacon_base = HW_BEACON_OFFSET(intf->beacon->entry_idx);
0f829b1d 531 rt2x00usb_register_write(rt2x00dev, beacon_base, 0);
95ea3627 532
6bb40dd1
ID		 533 /*
534 * Enable synchronisation.
535 */
0f829b1d 536 rt2x00usb_register_read(rt2x00dev, TXRX_CSR9, &reg);
fd3c91c5 537 rt2x00_set_field32(&reg, TXRX_CSR9_TSF_TICKING, 1);
6bb40dd1 538 rt2x00_set_field32(&reg, TXRX_CSR9_TSF_SYNC, conf->sync);
fd3c91c5 539 rt2x00_set_field32(&reg, TXRX_CSR9_TBTT_ENABLE, 1);
0f829b1d 540 rt2x00usb_register_write(rt2x00dev, TXRX_CSR9, reg);
6bb40dd1 541 }
95ea3627 542
6bb40dd1
ID		 543 if (flags & CONFIG_UPDATE_MAC) {
544 reg = le32_to_cpu(conf->mac[1]);
545 rt2x00_set_field32(&reg, MAC_CSR3_UNICAST_TO_ME_MASK, 0xff);
546 conf->mac[1] = cpu_to_le32(reg);
95ea3627 547
0f829b1d 548 rt2x00usb_register_multiwrite(rt2x00dev, MAC_CSR2,
6bb40dd1
ID		 549 conf->mac, sizeof(conf->mac));
550 }
95ea3627 551
6bb40dd1
ID		 552 if (flags & CONFIG_UPDATE_BSSID) {
553 reg = le32_to_cpu(conf->bssid[1]);
554 rt2x00_set_field32(&reg, MAC_CSR5_BSS_ID_MASK, 3);
555 conf->bssid[1] = cpu_to_le32(reg);
95ea3627 556
0f829b1d 557 rt2x00usb_register_multiwrite(rt2x00dev, MAC_CSR4,
6bb40dd1
ID		 558 conf->bssid, sizeof(conf->bssid));
559 }
95ea3627
ID		 560}
561
3a643d24
ID		 562static void rt73usb_config_erp(struct rt2x00_dev *rt2x00dev,
563 struct rt2x00lib_erp *erp)
95ea3627 564{
95ea3627 565 u32 reg;
95ea3627 566
0f829b1d 567 rt2x00usb_register_read(rt2x00dev, TXRX_CSR0, &reg);
72810379 568 rt2x00_set_field32(&reg, TXRX_CSR0_RX_ACK_TIMEOUT, erp->ack_timeout);
8a566afe 569 rt2x00_set_field32(&reg, TXRX_CSR0_TSF_OFFSET, IEEE80211_HEADER);
0f829b1d 570 rt2x00usb_register_write(rt2x00dev, TXRX_CSR0, reg);
95ea3627 571
0f829b1d 572 rt2x00usb_register_read(rt2x00dev, TXRX_CSR4, &reg);
8a566afe 573 rt2x00_set_field32(&reg, TXRX_CSR4_AUTORESPOND_ENABLE, 1);
4f5af6eb 574 rt2x00_set_field32(&reg, TXRX_CSR4_AUTORESPOND_PREAMBLE,
72810379 575 !!erp->short_preamble);
0f829b1d 576 rt2x00usb_register_write(rt2x00dev, TXRX_CSR4, reg);
95ea3627 577
0f829b1d 578 rt2x00usb_register_write(rt2x00dev, TXRX_CSR5, erp->basic_rates);
95ea3627 579
8a566afe
ID		 580 rt2x00usb_register_read(rt2x00dev, TXRX_CSR9, &reg);
581 rt2x00_set_field32(&reg, TXRX_CSR9_BEACON_INTERVAL,
582 erp->beacon_int * 16);
583 rt2x00usb_register_write(rt2x00dev, TXRX_CSR9, reg);
584
0f829b1d 585 rt2x00usb_register_read(rt2x00dev, MAC_CSR9, &reg);
e4ea1c40 586 rt2x00_set_field32(&reg, MAC_CSR9_SLOT_TIME, erp->slot_time);
0f829b1d 587 rt2x00usb_register_write(rt2x00dev, MAC_CSR9, reg);
95ea3627 588
0f829b1d 589 rt2x00usb_register_read(rt2x00dev, MAC_CSR8, &reg);
e4ea1c40
ID		 590 rt2x00_set_field32(&reg, MAC_CSR8_SIFS, erp->sifs);
591 rt2x00_set_field32(&reg, MAC_CSR8_SIFS_AFTER_RX_OFDM, 3);
592 rt2x00_set_field32(&reg, MAC_CSR8_EIFS, erp->eifs);
0f829b1d 593 rt2x00usb_register_write(rt2x00dev, MAC_CSR8, reg);
95ea3627
ID		 594}
595
596static void rt73usb_config_antenna_5x(struct rt2x00_dev *rt2x00dev,
addc81bd 597 struct antenna_setup *ant)
95ea3627
ID		 598{
599 u8 r3;
600 u8 r4;
601 u8 r77;
2676c94d 602 u8 temp;
95ea3627
ID		 603
604 rt73usb_bbp_read(rt2x00dev, 3, &r3);
605 rt73usb_bbp_read(rt2x00dev, 4, &r4);
606 rt73usb_bbp_read(rt2x00dev, 77, &r77);
607
608 rt2x00_set_field8(&r3, BBP_R3_SMART_MODE, 0);
609
e4cd2ff8
ID		 610 /*
611 * Configure the RX antenna.
612 */
addc81bd 613 switch (ant->rx) {
95ea3627 614 case ANTENNA_HW_DIVERSITY:
2676c94d
MN		 615 rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA_CONTROL, 2);
616 temp = !test_bit(CONFIG_FRAME_TYPE, &rt2x00dev->flags)
8318d78a 617 && (rt2x00dev->curr_band != IEEE80211_BAND_5GHZ);
2676c94d 618 rt2x00_set_field8(&r4, BBP_R4_RX_FRAME_END, temp);
95ea3627
ID		 619 break;
620 case ANTENNA_A:
2676c94d 621 rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA_CONTROL, 1);
95ea3627 622 rt2x00_set_field8(&r4, BBP_R4_RX_FRAME_END, 0);
8318d78a 623 if (rt2x00dev->curr_band == IEEE80211_BAND_5GHZ)
2676c94d
MN		 624 rt2x00_set_field8(&r77, BBP_R77_RX_ANTENNA, 0);
625 else
626 rt2x00_set_field8(&r77, BBP_R77_RX_ANTENNA, 3);
95ea3627
ID		 627 break;
628 case ANTENNA_B:
a4fe07d9 629 default:
2676c94d 630 rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA_CONTROL, 1);
95ea3627 631 rt2x00_set_field8(&r4, BBP_R4_RX_FRAME_END, 0);
8318d78a 632 if (rt2x00dev->curr_band == IEEE80211_BAND_5GHZ)
2676c94d
MN		 633 rt2x00_set_field8(&r77, BBP_R77_RX_ANTENNA, 3);
634 else
635 rt2x00_set_field8(&r77, BBP_R77_RX_ANTENNA, 0);
95ea3627
ID		 636 break;
637 }
638
639 rt73usb_bbp_write(rt2x00dev, 77, r77);
640 rt73usb_bbp_write(rt2x00dev, 3, r3);
641 rt73usb_bbp_write(rt2x00dev, 4, r4);
642}
643
644static void rt73usb_config_antenna_2x(struct rt2x00_dev *rt2x00dev,
addc81bd 645 struct antenna_setup *ant)
95ea3627
ID		 646{
647 u8 r3;
648 u8 r4;
649 u8 r77;
650
651 rt73usb_bbp_read(rt2x00dev, 3, &r3);
652 rt73usb_bbp_read(rt2x00dev, 4, &r4);
653 rt73usb_bbp_read(rt2x00dev, 77, &r77);
654
655 rt2x00_set_field8(&r3, BBP_R3_SMART_MODE, 0);
656 rt2x00_set_field8(&r4, BBP_R4_RX_FRAME_END,
657 !test_bit(CONFIG_FRAME_TYPE, &rt2x00dev->flags));
658
e4cd2ff8
ID		 659 /*
660 * Configure the RX antenna.
661 */
addc81bd 662 switch (ant->rx) {
95ea3627 663 case ANTENNA_HW_DIVERSITY:
2676c94d 664 rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA_CONTROL, 2);
95ea3627
ID		 665 break;
666 case ANTENNA_A:
2676c94d
MN		 667 rt2x00_set_field8(&r77, BBP_R77_RX_ANTENNA, 3);
668 rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA_CONTROL, 1);
95ea3627
ID		 669 break;
670 case ANTENNA_B:
a4fe07d9 671 default:
2676c94d
MN		 672 rt2x00_set_field8(&r77, BBP_R77_RX_ANTENNA, 0);
673 rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA_CONTROL, 1);
95ea3627
ID		 674 break;
675 }
676
677 rt73usb_bbp_write(rt2x00dev, 77, r77);
678 rt73usb_bbp_write(rt2x00dev, 3, r3);
679 rt73usb_bbp_write(rt2x00dev, 4, r4);
680}
681
682struct antenna_sel {
683 u8 word;
684 /*
685 * value[0] -> non-LNA
686 * value[1] -> LNA
687 */
688 u8 value[2];
689};
690
691static const struct antenna_sel antenna_sel_a[] = {
692 { 96, { 0x58, 0x78 } },
693 { 104, { 0x38, 0x48 } },
694 { 75, { 0xfe, 0x80 } },
695 { 86, { 0xfe, 0x80 } },
696 { 88, { 0xfe, 0x80 } },
697 { 35, { 0x60, 0x60 } },
698 { 97, { 0x58, 0x58 } },
699 { 98, { 0x58, 0x58 } },
700};
701
702static const struct antenna_sel antenna_sel_bg[] = {
703 { 96, { 0x48, 0x68 } },
704 { 104, { 0x2c, 0x3c } },
705 { 75, { 0xfe, 0x80 } },
706 { 86, { 0xfe, 0x80 } },
707 { 88, { 0xfe, 0x80 } },
708 { 35, { 0x50, 0x50 } },
709 { 97, { 0x48, 0x48 } },
710 { 98, { 0x48, 0x48 } },
711};
712
e4ea1c40
ID		 713static void rt73usb_config_ant(struct rt2x00_dev *rt2x00dev,
714 struct antenna_setup *ant)
95ea3627
ID		 715{
716 const struct antenna_sel *sel;
717 unsigned int lna;
718 unsigned int i;
719 u32 reg;
720
a4fe07d9
ID		 721 /*
722 * We should never come here because rt2x00lib is supposed
723 * to catch this and send us the correct antenna explicitely.
724 */
725 BUG_ON(ant->rx == ANTENNA_SW_DIVERSITY ||
726 ant->tx == ANTENNA_SW_DIVERSITY);
727
8318d78a 728 if (rt2x00dev->curr_band == IEEE80211_BAND_5GHZ) {
95ea3627
ID		 729 sel = antenna_sel_a;
730 lna = test_bit(CONFIG_EXTERNAL_LNA_A, &rt2x00dev->flags);
95ea3627
ID		 731 } else {
732 sel = antenna_sel_bg;
733 lna = test_bit(CONFIG_EXTERNAL_LNA_BG, &rt2x00dev->flags);
95ea3627
ID		 734 }
735
2676c94d
MN		 736 for (i = 0; i < ARRAY_SIZE(antenna_sel_a); i++)
737 rt73usb_bbp_write(rt2x00dev, sel[i].word, sel[i].value[lna]);
738
0f829b1d 739 rt2x00usb_register_read(rt2x00dev, PHY_CSR0, &reg);
2676c94d 740
ddc827f9 741 rt2x00_set_field32(&reg, PHY_CSR0_PA_PE_BG,
8318d78a 742 (rt2x00dev->curr_band == IEEE80211_BAND_2GHZ));
ddc827f9 743 rt2x00_set_field32(&reg, PHY_CSR0_PA_PE_A,
8318d78a 744 (rt2x00dev->curr_band == IEEE80211_BAND_5GHZ));
ddc827f9 745
0f829b1d 746 rt2x00usb_register_write(rt2x00dev, PHY_CSR0, reg);
95ea3627
ID		 747
748 if (rt2x00_rf(&rt2x00dev->chip, RF5226) ||
749 rt2x00_rf(&rt2x00dev->chip, RF5225))
addc81bd 750 rt73usb_config_antenna_5x(rt2x00dev, ant);
95ea3627
ID		 751 else if (rt2x00_rf(&rt2x00dev->chip, RF2528) ||
752 rt2x00_rf(&rt2x00dev->chip, RF2527))
addc81bd 753 rt73usb_config_antenna_2x(rt2x00dev, ant);
95ea3627
ID		 754}
755
e4ea1c40 756static void rt73usb_config_lna_gain(struct rt2x00_dev *rt2x00dev,
5c58ee51 757 struct rt2x00lib_conf *libconf)
e4ea1c40
ID		 758{
759 u16 eeprom;
760 short lna_gain = 0;
761
762 if (libconf->conf->channel->band == IEEE80211_BAND_2GHZ) {
763 if (test_bit(CONFIG_EXTERNAL_LNA_BG, &rt2x00dev->flags))
764 lna_gain += 14;
765
766 rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_OFFSET_BG, &eeprom);
767 lna_gain -= rt2x00_get_field16(eeprom, EEPROM_RSSI_OFFSET_BG_1);
768 } else {
769 rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_OFFSET_A, &eeprom);
770 lna_gain -= rt2x00_get_field16(eeprom, EEPROM_RSSI_OFFSET_A_1);
771 }
772
773 rt2x00dev->lna_gain = lna_gain;
774}
775
776static void rt73usb_config_channel(struct rt2x00_dev *rt2x00dev,
777 struct rf_channel *rf, const int txpower)
778{
779 u8 r3;
780 u8 r94;
781 u8 smart;
782
783 rt2x00_set_field32(&rf->rf3, RF3_TXPOWER, TXPOWER_TO_DEV(txpower));
784 rt2x00_set_field32(&rf->rf4, RF4_FREQ_OFFSET, rt2x00dev->freq_offset);
785
786 smart = !(rt2x00_rf(&rt2x00dev->chip, RF5225) ||
787 rt2x00_rf(&rt2x00dev->chip, RF2527));
788
789 rt73usb_bbp_read(rt2x00dev, 3, &r3);
790 rt2x00_set_field8(&r3, BBP_R3_SMART_MODE, smart);
791 rt73usb_bbp_write(rt2x00dev, 3, r3);
792
793 r94 = 6;
794 if (txpower > MAX_TXPOWER && txpower <= (MAX_TXPOWER + r94))
795 r94 += txpower - MAX_TXPOWER;
796 else if (txpower < MIN_TXPOWER && txpower >= (MIN_TXPOWER - r94))
797 r94 += txpower;
798 rt73usb_bbp_write(rt2x00dev, 94, r94);
799
800 rt73usb_rf_write(rt2x00dev, 1, rf->rf1);
801 rt73usb_rf_write(rt2x00dev, 2, rf->rf2);
802 rt73usb_rf_write(rt2x00dev, 3, rf->rf3 & ~0x00000004);
803 rt73usb_rf_write(rt2x00dev, 4, rf->rf4);
804
805 rt73usb_rf_write(rt2x00dev, 1, rf->rf1);
806 rt73usb_rf_write(rt2x00dev, 2, rf->rf2);
807 rt73usb_rf_write(rt2x00dev, 3, rf->rf3 | 0x00000004);
808 rt73usb_rf_write(rt2x00dev, 4, rf->rf4);
809
810 rt73usb_rf_write(rt2x00dev, 1, rf->rf1);
811 rt73usb_rf_write(rt2x00dev, 2, rf->rf2);
812 rt73usb_rf_write(rt2x00dev, 3, rf->rf3 & ~0x00000004);
813 rt73usb_rf_write(rt2x00dev, 4, rf->rf4);
814
815 udelay(10);
816}
817
818static void rt73usb_config_txpower(struct rt2x00_dev *rt2x00dev,
819 const int txpower)
820{
821 struct rf_channel rf;
822
823 rt2x00_rf_read(rt2x00dev, 1, &rf.rf1);
824 rt2x00_rf_read(rt2x00dev, 2, &rf.rf2);
825 rt2x00_rf_read(rt2x00dev, 3, &rf.rf3);
826 rt2x00_rf_read(rt2x00dev, 4, &rf.rf4);
827
828 rt73usb_config_channel(rt2x00dev, &rf, txpower);
829}
830
831static void rt73usb_config_retry_limit(struct rt2x00_dev *rt2x00dev,
832 struct rt2x00lib_conf *libconf)
95ea3627
ID		 833{
834 u32 reg;
835
0f829b1d 836 rt2x00usb_register_read(rt2x00dev, TXRX_CSR4, &reg);
e4ea1c40
ID		 837 rt2x00_set_field32(&reg, TXRX_CSR4_LONG_RETRY_LIMIT,
838 libconf->conf->long_frame_max_tx_count);
839 rt2x00_set_field32(&reg, TXRX_CSR4_SHORT_RETRY_LIMIT,
840 libconf->conf->short_frame_max_tx_count);
0f829b1d 841 rt2x00usb_register_write(rt2x00dev, TXRX_CSR4, reg);
e4ea1c40 842}
95ea3627 843
7d7f19cc
ID		 844static void rt73usb_config_ps(struct rt2x00_dev *rt2x00dev,
845 struct rt2x00lib_conf *libconf)
846{
847 enum dev_state state =
848 (libconf->conf->flags & IEEE80211_CONF_PS) ?
849 STATE_SLEEP : STATE_AWAKE;
850 u32 reg;
851
852 if (state == STATE_SLEEP) {
853 rt2x00usb_register_read(rt2x00dev, MAC_CSR11, &reg);
854 rt2x00_set_field32(&reg, MAC_CSR11_DELAY_AFTER_TBCN,
6b347bff 855 rt2x00dev->beacon_int - 10);
7d7f19cc
ID		 856 rt2x00_set_field32(&reg, MAC_CSR11_TBCN_BEFORE_WAKEUP,
857 libconf->conf->listen_interval - 1);
858 rt2x00_set_field32(&reg, MAC_CSR11_WAKEUP_LATENCY, 5);
859
860 /* We must first disable autowake before it can be enabled */
861 rt2x00_set_field32(&reg, MAC_CSR11_AUTOWAKE, 0);
862 rt2x00usb_register_write(rt2x00dev, MAC_CSR11, reg);
863
864 rt2x00_set_field32(&reg, MAC_CSR11_AUTOWAKE, 1);
865 rt2x00usb_register_write(rt2x00dev, MAC_CSR11, reg);
866
867 rt2x00usb_vendor_request_sw(rt2x00dev, USB_DEVICE_MODE, 0,
868 USB_MODE_SLEEP, REGISTER_TIMEOUT);
869 } else {
870 rt2x00usb_vendor_request_sw(rt2x00dev, USB_DEVICE_MODE, 0,
871 USB_MODE_WAKEUP, REGISTER_TIMEOUT);
872
873 rt2x00usb_register_read(rt2x00dev, MAC_CSR11, &reg);
874 rt2x00_set_field32(&reg, MAC_CSR11_DELAY_AFTER_TBCN, 0);
875 rt2x00_set_field32(&reg, MAC_CSR11_TBCN_BEFORE_WAKEUP, 0);
876 rt2x00_set_field32(&reg, MAC_CSR11_AUTOWAKE, 0);
877 rt2x00_set_field32(&reg, MAC_CSR11_WAKEUP_LATENCY, 0);
878 rt2x00usb_register_write(rt2x00dev, MAC_CSR11, reg);
879 }
880}
881
95ea3627 882static void rt73usb_config(struct rt2x00_dev *rt2x00dev,
6bb40dd1
ID		 883 struct rt2x00lib_conf *libconf,
884 const unsigned int flags)
95ea3627 885{
ba2ab471
ID		 886 /* Always recalculate LNA gain before changing configuration */
887 rt73usb_config_lna_gain(rt2x00dev, libconf);
888
e4ea1c40 889 if (flags & IEEE80211_CONF_CHANGE_CHANNEL)
5c58ee51
ID		 890 rt73usb_config_channel(rt2x00dev, &libconf->rf,
891 libconf->conf->power_level);
e4ea1c40
ID		 892 if ((flags & IEEE80211_CONF_CHANGE_POWER) &&
893 !(flags & IEEE80211_CONF_CHANGE_CHANNEL))
5c58ee51 894 rt73usb_config_txpower(rt2x00dev, libconf->conf->power_level);
e4ea1c40
ID		 895 if (flags & IEEE80211_CONF_CHANGE_RETRY_LIMITS)
896 rt73usb_config_retry_limit(rt2x00dev, libconf);
7d7f19cc
ID		 897 if (flags & IEEE80211_CONF_CHANGE_PS)
898 rt73usb_config_ps(rt2x00dev, libconf);
95ea3627
ID		 899}
900
95ea3627
ID		 901/*
902 * Link tuning
903 */
ebcf26da
ID		 904static void rt73usb_link_stats(struct rt2x00_dev *rt2x00dev,
905 struct link_qual *qual)
95ea3627
ID		 906{
907 u32 reg;
908
909 /*
910 * Update FCS error count from register.
911 */
0f829b1d 912 rt2x00usb_register_read(rt2x00dev, STA_CSR0, &reg);
ebcf26da 913 qual->rx_failed = rt2x00_get_field32(reg, STA_CSR0_FCS_ERROR);
95ea3627
ID		 914
915 /*
916 * Update False CCA count from register.
917 */
0f829b1d 918 rt2x00usb_register_read(rt2x00dev, STA_CSR1, &reg);
ebcf26da 919 qual->false_cca = rt2x00_get_field32(reg, STA_CSR1_FALSE_CCA_ERROR);
95ea3627
ID		 920}
921
5352ff65
ID		 922static inline void rt73usb_set_vgc(struct rt2x00_dev *rt2x00dev,
923 struct link_qual *qual, u8 vgc_level)
eb20b4e8 924{
5352ff65 925 if (qual->vgc_level != vgc_level) {
eb20b4e8 926 rt73usb_bbp_write(rt2x00dev, 17, vgc_level);
5352ff65
ID		 927 qual->vgc_level = vgc_level;
928 qual->vgc_level_reg = vgc_level;
eb20b4e8
ID		 929 }
930}
931
5352ff65
ID		 932static void rt73usb_reset_tuner(struct rt2x00_dev *rt2x00dev,
933 struct link_qual *qual)
95ea3627 934{
5352ff65 935 rt73usb_set_vgc(rt2x00dev, qual, 0x20);
95ea3627
ID		 936}
937
5352ff65
ID		 938static void rt73usb_link_tuner(struct rt2x00_dev *rt2x00dev,
939 struct link_qual *qual, const u32 count)
95ea3627 940{
95ea3627
ID		 941 u8 up_bound;
942 u8 low_bound;
943
95ea3627
ID		 944 /*
945 * Determine r17 bounds.
946 */
8318d78a 947 if (rt2x00dev->rx_status.band == IEEE80211_BAND_5GHZ) {
95ea3627
ID		 948 low_bound = 0x28;
949 up_bound = 0x48;
950
951 if (test_bit(CONFIG_EXTERNAL_LNA_A, &rt2x00dev->flags)) {
952 low_bound += 0x10;
953 up_bound += 0x10;
954 }
955 } else {
5352ff65 956 if (qual->rssi > -82) {
95ea3627
ID		 957 low_bound = 0x1c;
958 up_bound = 0x40;
5352ff65 959 } else if (qual->rssi > -84) {
95ea3627
ID		 960 low_bound = 0x1c;
961 up_bound = 0x20;
962 } else {
963 low_bound = 0x1c;
964 up_bound = 0x1c;
965 }
966
967 if (test_bit(CONFIG_EXTERNAL_LNA_BG, &rt2x00dev->flags)) {
968 low_bound += 0x14;
969 up_bound += 0x10;
970 }
971 }
972
6bb40dd1
ID		 973 /*
974 * If we are not associated, we should go straight to the
975 * dynamic CCA tuning.
976 */
977 if (!rt2x00dev->intf_associated)
978 goto dynamic_cca_tune;
979
95ea3627
ID		 980 /*
981 * Special big-R17 for very short distance
982 */
5352ff65
ID		 983 if (qual->rssi > -35) {
984 rt73usb_set_vgc(rt2x00dev, qual, 0x60);
95ea3627
ID		 985 return;
986 }
987
988 /*
989 * Special big-R17 for short distance
990 */
5352ff65
ID		 991 if (qual->rssi >= -58) {
992 rt73usb_set_vgc(rt2x00dev, qual, up_bound);
95ea3627
ID		 993 return;
994 }
995
996 /*
997 * Special big-R17 for middle-short distance
998 */
5352ff65
ID		 999 if (qual->rssi >= -66) {
1000 rt73usb_set_vgc(rt2x00dev, qual, low_bound + 0x10);
95ea3627
ID		 1001 return;
1002 }
1003
1004 /*
1005 * Special mid-R17 for middle distance
1006 */
5352ff65
ID		 1007 if (qual->rssi >= -74) {
1008 rt73usb_set_vgc(rt2x00dev, qual, low_bound + 0x08);
95ea3627
ID		 1009 return;
1010 }
1011
1012 /*
1013 * Special case: Change up_bound based on the rssi.
1014 * Lower up_bound when rssi is weaker then -74 dBm.
1015 */
5352ff65 1016 up_bound -= 2 * (-74 - qual->rssi);
95ea3627
ID		 1017 if (low_bound > up_bound)
1018 up_bound = low_bound;
1019
5352ff65
ID		 1020 if (qual->vgc_level > up_bound) {
1021 rt73usb_set_vgc(rt2x00dev, qual, up_bound);
95ea3627
ID		 1022 return;
1023 }
1024
6bb40dd1
ID		 1025dynamic_cca_tune:
1026
95ea3627
ID		 1027 /*
1028 * r17 does not yet exceed upper limit, continue and base
1029 * the r17 tuning on the false CCA count.
1030 */
5352ff65
ID		 1031 if ((qual->false_cca > 512) && (qual->vgc_level < up_bound))
1032 rt73usb_set_vgc(rt2x00dev, qual,
1033 min_t(u8, qual->vgc_level + 4, up_bound));
1034 else if ((qual->false_cca < 100) && (qual->vgc_level > low_bound))
1035 rt73usb_set_vgc(rt2x00dev, qual,
1036 max_t(u8, qual->vgc_level - 4, low_bound));
95ea3627
ID		 1037}
1038
1039/*
a7f3a06c 1040 * Firmware functions
95ea3627
ID		 1041 */
1042static char *rt73usb_get_firmware_name(struct rt2x00_dev *rt2x00dev)
1043{
1044 return FIRMWARE_RT2571;
1045}
1046
0cbe0064
ID		 1047static int rt73usb_check_firmware(struct rt2x00_dev *rt2x00dev,
1048 const u8 *data, const size_t len)
a7f3a06c 1049{
0cbe0064 1050 u16 fw_crc;
a7f3a06c
ID		 1051 u16 crc;
1052
1053 /*
0cbe0064
ID		 1054 * Only support 2kb firmware files.
1055 */
1056 if (len != 2048)
1057 return FW_BAD_LENGTH;
1058
1059 /*
a7f3a06c
ID		 1060 * The last 2 bytes in the firmware array are the crc checksum itself,
1061 * this means that we should never pass those 2 bytes to the crc
1062 * algorithm.
1063 */
0cbe0064
ID		 1064 fw_crc = (data[len - 2] << 8 | data[len - 1]);
1065
1066 /*
1067 * Use the crc itu-t algorithm.
1068 */
a7f3a06c
ID		 1069 crc = crc_itu_t(0, data, len - 2);
1070 crc = crc_itu_t_byte(crc, 0);
1071 crc = crc_itu_t_byte(crc, 0);
1072
0cbe0064 1073 return (fw_crc == crc) ? FW_OK : FW_BAD_CRC;
a7f3a06c
ID		 1074}
1075
0cbe0064
ID		 1076static int rt73usb_load_firmware(struct rt2x00_dev *rt2x00dev,
1077 const u8 *data, const size_t len)
95ea3627
ID		 1078{
1079 unsigned int i;
1080 int status;
1081 u32 reg;
95ea3627
ID		 1082
1083 /*
1084 * Wait for stable hardware.
1085 */
1086 for (i = 0; i < 100; i++) {
0f829b1d 1087 rt2x00usb_register_read(rt2x00dev, MAC_CSR0, &reg);
95ea3627
ID		 1088 if (reg)
1089 break;
1090 msleep(1);
1091 }
1092
1093 if (!reg) {
1094 ERROR(rt2x00dev, "Unstable hardware.\n");
1095 return -EBUSY;
1096 }
1097
1098 /*
1099 * Write firmware to device.
95ea3627 1100 */
3e0c1abe
IM		 1101 rt2x00usb_vendor_request_large_buff(rt2x00dev, USB_MULTI_WRITE,
1102 USB_VENDOR_REQUEST_OUT,
1103 FIRMWARE_IMAGE_BASE,
1104 data, len,
1105 REGISTER_TIMEOUT32(len));
95ea3627
ID		 1106
1107 /*
1108 * Send firmware request to device to load firmware,
1109 * we need to specify a long timeout time.
1110 */
1111 status = rt2x00usb_vendor_request_sw(rt2x00dev, USB_DEVICE_MODE,
3b640f21 1112 0, USB_MODE_FIRMWARE,
95ea3627
ID		 1113 REGISTER_TIMEOUT_FIRMWARE);
1114 if (status < 0) {
1115 ERROR(rt2x00dev, "Failed to write Firmware to device.\n");
1116 return status;
1117 }
1118
95ea3627
ID		 1119 return 0;
1120}
1121
a7f3a06c
ID		 1122/*
1123 * Initialization functions.
1124 */
95ea3627
ID		 1125static int rt73usb_init_registers(struct rt2x00_dev *rt2x00dev)
1126{
1127 u32 reg;
1128
0f829b1d 1129 rt2x00usb_register_read(rt2x00dev, TXRX_CSR0, &reg);
95ea3627
ID		 1130 rt2x00_set_field32(&reg, TXRX_CSR0_AUTO_TX_SEQ, 1);
1131 rt2x00_set_field32(&reg, TXRX_CSR0_DISABLE_RX, 0);
1132 rt2x00_set_field32(&reg, TXRX_CSR0_TX_WITHOUT_WAITING, 0);
0f829b1d 1133 rt2x00usb_register_write(rt2x00dev, TXRX_CSR0, reg);
95ea3627 1134
0f829b1d 1135 rt2x00usb_register_read(rt2x00dev, TXRX_CSR1, &reg);
95ea3627
ID		 1136 rt2x00_set_field32(&reg, TXRX_CSR1_BBP_ID0, 47); /* CCK Signal */
1137 rt2x00_set_field32(&reg, TXRX_CSR1_BBP_ID0_VALID, 1);
1138 rt2x00_set_field32(&reg, TXRX_CSR1_BBP_ID1, 30); /* Rssi */
1139 rt2x00_set_field32(&reg, TXRX_CSR1_BBP_ID1_VALID, 1);
1140 rt2x00_set_field32(&reg, TXRX_CSR1_BBP_ID2, 42); /* OFDM Rate */
1141 rt2x00_set_field32(&reg, TXRX_CSR1_BBP_ID2_VALID, 1);
1142 rt2x00_set_field32(&reg, TXRX_CSR1_BBP_ID3, 30); /* Rssi */
1143 rt2x00_set_field32(&reg, TXRX_CSR1_BBP_ID3_VALID, 1);
0f829b1d 1144 rt2x00usb_register_write(rt2x00dev, TXRX_CSR1, reg);
95ea3627
ID		 1145
1146 /*
1147 * CCK TXD BBP registers
1148 */
0f829b1d 1149 rt2x00usb_register_read(rt2x00dev, TXRX_CSR2, &reg);
95ea3627
ID		 1150 rt2x00_set_field32(&reg, TXRX_CSR2_BBP_ID0, 13);
1151 rt2x00_set_field32(&reg, TXRX_CSR2_BBP_ID0_VALID, 1);
1152 rt2x00_set_field32(&reg, TXRX_CSR2_BBP_ID1, 12);
1153 rt2x00_set_field32(&reg, TXRX_CSR2_BBP_ID1_VALID, 1);
1154 rt2x00_set_field32(&reg, TXRX_CSR2_BBP_ID2, 11);
1155 rt2x00_set_field32(&reg, TXRX_CSR2_BBP_ID2_VALID, 1);
1156 rt2x00_set_field32(&reg, TXRX_CSR2_BBP_ID3, 10);
1157 rt2x00_set_field32(&reg, TXRX_CSR2_BBP_ID3_VALID, 1);
0f829b1d 1158 rt2x00usb_register_write(rt2x00dev, TXRX_CSR2, reg);
95ea3627
ID		 1159
1160 /*
1161 * OFDM TXD BBP registers
1162 */
0f829b1d 1163 rt2x00usb_register_read(rt2x00dev, TXRX_CSR3, &reg);
95ea3627
ID		 1164 rt2x00_set_field32(&reg, TXRX_CSR3_BBP_ID0, 7);
1165 rt2x00_set_field32(&reg, TXRX_CSR3_BBP_ID0_VALID, 1);
1166 rt2x00_set_field32(&reg, TXRX_CSR3_BBP_ID1, 6);
1167 rt2x00_set_field32(&reg, TXRX_CSR3_BBP_ID1_VALID, 1);
1168 rt2x00_set_field32(&reg, TXRX_CSR3_BBP_ID2, 5);
1169 rt2x00_set_field32(&reg, TXRX_CSR3_BBP_ID2_VALID, 1);
0f829b1d 1170 rt2x00usb_register_write(rt2x00dev, TXRX_CSR3, reg);
95ea3627 1171
0f829b1d 1172 rt2x00usb_register_read(rt2x00dev, TXRX_CSR7, &reg);
95ea3627
ID		 1173 rt2x00_set_field32(&reg, TXRX_CSR7_ACK_CTS_6MBS, 59);
1174 rt2x00_set_field32(&reg, TXRX_CSR7_ACK_CTS_9MBS, 53);
1175 rt2x00_set_field32(&reg, TXRX_CSR7_ACK_CTS_12MBS, 49);
1176 rt2x00_set_field32(&reg, TXRX_CSR7_ACK_CTS_18MBS, 46);
0f829b1d 1177 rt2x00usb_register_write(rt2x00dev, TXRX_CSR7, reg);
95ea3627 1178
0f829b1d 1179 rt2x00usb_register_read(rt2x00dev, TXRX_CSR8, &reg);
95ea3627
ID		 1180 rt2x00_set_field32(&reg, TXRX_CSR8_ACK_CTS_24MBS, 44);
1181 rt2x00_set_field32(&reg, TXRX_CSR8_ACK_CTS_36MBS, 42);
1182 rt2x00_set_field32(&reg, TXRX_CSR8_ACK_CTS_48MBS, 42);
1183 rt2x00_set_field32(&reg, TXRX_CSR8_ACK_CTS_54MBS, 42);
0f829b1d 1184 rt2x00usb_register_write(rt2x00dev, TXRX_CSR8, reg);
95ea3627 1185
0f829b1d 1186 rt2x00usb_register_read(rt2x00dev, TXRX_CSR9, &reg);
1f909162
ID		 1187 rt2x00_set_field32(&reg, TXRX_CSR9_BEACON_INTERVAL, 0);
1188 rt2x00_set_field32(&reg, TXRX_CSR9_TSF_TICKING, 0);
1189 rt2x00_set_field32(&reg, TXRX_CSR9_TSF_SYNC, 0);
1190 rt2x00_set_field32(&reg, TXRX_CSR9_TBTT_ENABLE, 0);
1191 rt2x00_set_field32(&reg, TXRX_CSR9_BEACON_GEN, 0);
1192 rt2x00_set_field32(&reg, TXRX_CSR9_TIMESTAMP_COMPENSATE, 0);
0f829b1d 1193 rt2x00usb_register_write(rt2x00dev, TXRX_CSR9, reg);
1f909162 1194
0f829b1d 1195 rt2x00usb_register_write(rt2x00dev, TXRX_CSR15, 0x0000000f);
95ea3627 1196
0f829b1d 1197 rt2x00usb_register_read(rt2x00dev, MAC_CSR6, &reg);
95ea3627 1198 rt2x00_set_field32(&reg, MAC_CSR6_MAX_FRAME_UNIT, 0xfff);
0f829b1d 1199 rt2x00usb_register_write(rt2x00dev, MAC_CSR6, reg);
95ea3627 1200
0f829b1d 1201 rt2x00usb_register_write(rt2x00dev, MAC_CSR10, 0x00000718);
95ea3627
ID		 1202
1203 if (rt2x00dev->ops->lib->set_device_state(rt2x00dev, STATE_AWAKE))
1204 return -EBUSY;
1205
0f829b1d 1206 rt2x00usb_register_write(rt2x00dev, MAC_CSR13, 0x00007f00);
95ea3627
ID		 1207
1208 /*
1209 * Invalidate all Shared Keys (SEC_CSR0),
1210 * and clear the Shared key Cipher algorithms (SEC_CSR1 & SEC_CSR5)
1211 */
0f829b1d
ID		 1212 rt2x00usb_register_write(rt2x00dev, SEC_CSR0, 0x00000000);
1213 rt2x00usb_register_write(rt2x00dev, SEC_CSR1, 0x00000000);
1214 rt2x00usb_register_write(rt2x00dev, SEC_CSR5, 0x00000000);
95ea3627
ID		 1215
1216 reg = 0x000023b0;
1217 if (rt2x00_rf(&rt2x00dev->chip, RF5225) ||
1218 rt2x00_rf(&rt2x00dev->chip, RF2527))
1219 rt2x00_set_field32(&reg, PHY_CSR1_RF_RPI, 1);
0f829b1d 1220 rt2x00usb_register_write(rt2x00dev, PHY_CSR1, reg);
95ea3627 1221
0f829b1d
ID		 1222 rt2x00usb_register_write(rt2x00dev, PHY_CSR5, 0x00040a06);
1223 rt2x00usb_register_write(rt2x00dev, PHY_CSR6, 0x00080606);
1224 rt2x00usb_register_write(rt2x00dev, PHY_CSR7, 0x00000408);
95ea3627 1225
0f829b1d 1226 rt2x00usb_register_read(rt2x00dev, MAC_CSR9, &reg);
95ea3627 1227 rt2x00_set_field32(&reg, MAC_CSR9_CW_SELECT, 0);
0f829b1d 1228 rt2x00usb_register_write(rt2x00dev, MAC_CSR9, reg);
95ea3627 1229
6bb40dd1
ID		 1230 /*
1231 * Clear all beacons
1232 * For the Beacon base registers we only need to clear
1233 * the first byte since that byte contains the VALID and OWNER
1234 * bits which (when set to 0) will invalidate the entire beacon.
1235 */
0f829b1d
ID		 1236 rt2x00usb_register_write(rt2x00dev, HW_BEACON_BASE0, 0);
1237 rt2x00usb_register_write(rt2x00dev, HW_BEACON_BASE1, 0);
1238 rt2x00usb_register_write(rt2x00dev, HW_BEACON_BASE2, 0);
1239 rt2x00usb_register_write(rt2x00dev, HW_BEACON_BASE3, 0);
6bb40dd1 1240
95ea3627
ID		 1241 /*
1242 * We must clear the error counters.
1243 * These registers are cleared on read,
1244 * so we may pass a useless variable to store the value.
1245 */
0f829b1d
ID		 1246 rt2x00usb_register_read(rt2x00dev, STA_CSR0, &reg);
1247 rt2x00usb_register_read(rt2x00dev, STA_CSR1, &reg);
1248 rt2x00usb_register_read(rt2x00dev, STA_CSR2, &reg);
95ea3627
ID		 1249
1250 /*
1251 * Reset MAC and BBP registers.
1252 */
0f829b1d 1253 rt2x00usb_register_read(rt2x00dev, MAC_CSR1, &reg);
95ea3627
ID		 1254 rt2x00_set_field32(&reg, MAC_CSR1_SOFT_RESET, 1);
1255 rt2x00_set_field32(&reg, MAC_CSR1_BBP_RESET, 1);
0f829b1d 1256 rt2x00usb_register_write(rt2x00dev, MAC_CSR1, reg);
95ea3627 1257
0f829b1d 1258 rt2x00usb_register_read(rt2x00dev, MAC_CSR1, &reg);
95ea3627
ID		 1259 rt2x00_set_field32(&reg, MAC_CSR1_SOFT_RESET, 0);
1260 rt2x00_set_field32(&reg, MAC_CSR1_BBP_RESET, 0);
0f829b1d 1261 rt2x00usb_register_write(rt2x00dev, MAC_CSR1, reg);
95ea3627 1262
0f829b1d 1263 rt2x00usb_register_read(rt2x00dev, MAC_CSR1, &reg);
95ea3627 1264 rt2x00_set_field32(&reg, MAC_CSR1_HOST_READY, 1);
0f829b1d 1265 rt2x00usb_register_write(rt2x00dev, MAC_CSR1, reg);
95ea3627
ID		 1266
1267 return 0;
1268}
1269
2b08da3f 1270static int rt73usb_wait_bbp_ready(struct rt2x00_dev *rt2x00dev)
95ea3627
ID		 1271{
1272 unsigned int i;
95ea3627
ID		 1273 u8 value;
1274
1275 for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
1276 rt73usb_bbp_read(rt2x00dev, 0, &value);
1277 if ((value != 0xff) && (value != 0x00))
2b08da3f 1278 return 0;
95ea3627
ID		 1279 udelay(REGISTER_BUSY_DELAY);
1280 }
1281
1282 ERROR(rt2x00dev, "BBP register access failed, aborting.\n");
1283 return -EACCES;
2b08da3f
ID		 1284}
1285
1286static int rt73usb_init_bbp(struct rt2x00_dev *rt2x00dev)
1287{
1288 unsigned int i;
1289 u16 eeprom;
1290 u8 reg_id;
1291 u8 value;
1292
1293 if (unlikely(rt73usb_wait_bbp_ready(rt2x00dev)))
1294 return -EACCES;
95ea3627 1295
95ea3627
ID		 1296 rt73usb_bbp_write(rt2x00dev, 3, 0x80);
1297 rt73usb_bbp_write(rt2x00dev, 15, 0x30);
1298 rt73usb_bbp_write(rt2x00dev, 21, 0xc8);
1299 rt73usb_bbp_write(rt2x00dev, 22, 0x38);
1300 rt73usb_bbp_write(rt2x00dev, 23, 0x06);
1301 rt73usb_bbp_write(rt2x00dev, 24, 0xfe);
1302 rt73usb_bbp_write(rt2x00dev, 25, 0x0a);
1303 rt73usb_bbp_write(rt2x00dev, 26, 0x0d);
1304 rt73usb_bbp_write(rt2x00dev, 32, 0x0b);
1305 rt73usb_bbp_write(rt2x00dev, 34, 0x12);
1306 rt73usb_bbp_write(rt2x00dev, 37, 0x07);
1307 rt73usb_bbp_write(rt2x00dev, 39, 0xf8);
1308 rt73usb_bbp_write(rt2x00dev, 41, 0x60);
1309 rt73usb_bbp_write(rt2x00dev, 53, 0x10);
1310 rt73usb_bbp_write(rt2x00dev, 54, 0x18);
1311 rt73usb_bbp_write(rt2x00dev, 60, 0x10);
1312 rt73usb_bbp_write(rt2x00dev, 61, 0x04);
1313 rt73usb_bbp_write(rt2x00dev, 62, 0x04);
1314 rt73usb_bbp_write(rt2x00dev, 75, 0xfe);
1315 rt73usb_bbp_write(rt2x00dev, 86, 0xfe);
1316 rt73usb_bbp_write(rt2x00dev, 88, 0xfe);
1317 rt73usb_bbp_write(rt2x00dev, 90, 0x0f);
1318 rt73usb_bbp_write(rt2x00dev, 99, 0x00);
1319 rt73usb_bbp_write(rt2x00dev, 102, 0x16);
1320 rt73usb_bbp_write(rt2x00dev, 107, 0x04);
1321
95ea3627
ID		 1322 for (i = 0; i < EEPROM_BBP_SIZE; i++) {
1323 rt2x00_eeprom_read(rt2x00dev, EEPROM_BBP_START + i, &eeprom);
1324
1325 if (eeprom != 0xffff && eeprom != 0x0000) {
1326 reg_id = rt2x00_get_field16(eeprom, EEPROM_BBP_REG_ID);
1327 value = rt2x00_get_field16(eeprom, EEPROM_BBP_VALUE);
95ea3627
ID		 1328 rt73usb_bbp_write(rt2x00dev, reg_id, value);
1329 }
1330 }
95ea3627
ID		 1331
1332 return 0;
1333}
1334
1335/*
1336 * Device state switch handlers.
1337 */
1338static void rt73usb_toggle_rx(struct rt2x00_dev *rt2x00dev,
1339 enum dev_state state)
1340{
1341 u32 reg;
1342
0f829b1d 1343 rt2x00usb_register_read(rt2x00dev, TXRX_CSR0, &reg);
95ea3627 1344 rt2x00_set_field32(&reg, TXRX_CSR0_DISABLE_RX,
2b08da3f
ID		 1345 (state == STATE_RADIO_RX_OFF) ||
1346 (state == STATE_RADIO_RX_OFF_LINK));
0f829b1d 1347 rt2x00usb_register_write(rt2x00dev, TXRX_CSR0, reg);
95ea3627
ID		 1348}
1349
1350static int rt73usb_enable_radio(struct rt2x00_dev *rt2x00dev)
1351{
1352 /*
1353 * Initialize all registers.
1354 */
2b08da3f
ID		 1355 if (unlikely(rt73usb_init_registers(rt2x00dev) ||
1356 rt73usb_init_bbp(rt2x00dev)))
95ea3627 1357 return -EIO;
95ea3627 1358
95ea3627
ID		 1359 return 0;
1360}
1361
1362static void rt73usb_disable_radio(struct rt2x00_dev *rt2x00dev)
1363{
0f829b1d 1364 rt2x00usb_register_write(rt2x00dev, MAC_CSR10, 0x00001818);
95ea3627
ID		 1365
1366 /*
1367 * Disable synchronisation.
1368 */
0f829b1d 1369 rt2x00usb_register_write(rt2x00dev, TXRX_CSR9, 0);
95ea3627
ID		 1370
1371 rt2x00usb_disable_radio(rt2x00dev);
1372}
1373
1374static int rt73usb_set_state(struct rt2x00_dev *rt2x00dev, enum dev_state state)
1375{
1376 u32 reg;
1377 unsigned int i;
1378 char put_to_sleep;
95ea3627
ID		 1379
1380 put_to_sleep = (state != STATE_AWAKE);
1381
0f829b1d 1382 rt2x00usb_register_read(rt2x00dev, MAC_CSR12, &reg);
95ea3627
ID		 1383 rt2x00_set_field32(&reg, MAC_CSR12_FORCE_WAKEUP, !put_to_sleep);
1384 rt2x00_set_field32(&reg, MAC_CSR12_PUT_TO_SLEEP, put_to_sleep);
0f829b1d 1385 rt2x00usb_register_write(rt2x00dev, MAC_CSR12, reg);
95ea3627
ID		 1386
1387 /*
1388 * Device is not guaranteed to be in the requested state yet.
1389 * We must wait until the register indicates that the
1390 * device has entered the correct state.
1391 */
1392 for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
0f829b1d 1393 rt2x00usb_register_read(rt2x00dev, MAC_CSR12, &reg);
2b08da3f
ID		 1394 state = rt2x00_get_field32(reg, MAC_CSR12_BBP_CURRENT_STATE);
1395 if (state == !put_to_sleep)
95ea3627
ID		 1396 return 0;
1397 msleep(10);
1398 }
1399
95ea3627
ID		 1400 return -EBUSY;
1401}
1402
1403static int rt73usb_set_device_state(struct rt2x00_dev *rt2x00dev,
1404 enum dev_state state)
1405{
1406 int retval = 0;
1407
1408 switch (state) {
1409 case STATE_RADIO_ON:
1410 retval = rt73usb_enable_radio(rt2x00dev);
1411 break;
1412 case STATE_RADIO_OFF:
1413 rt73usb_disable_radio(rt2x00dev);
1414 break;
1415 case STATE_RADIO_RX_ON:
61667d8d 1416 case STATE_RADIO_RX_ON_LINK:
95ea3627 1417 case STATE_RADIO_RX_OFF:
61667d8d 1418 case STATE_RADIO_RX_OFF_LINK:
2b08da3f
ID		 1419 rt73usb_toggle_rx(rt2x00dev, state);
1420 break;
1421 case STATE_RADIO_IRQ_ON:
1422 case STATE_RADIO_IRQ_OFF:
1423 /* No support, but no error either */
95ea3627
ID		 1424 break;
1425 case STATE_DEEP_SLEEP:
1426 case STATE_SLEEP:
1427 case STATE_STANDBY:
1428 case STATE_AWAKE:
1429 retval = rt73usb_set_state(rt2x00dev, state);
1430 break;
1431 default:
1432 retval = -ENOTSUPP;
1433 break;
1434 }
1435
2b08da3f
ID		 1436 if (unlikely(retval))
1437 ERROR(rt2x00dev, "Device failed to enter state %d (%d).\n",
1438 state, retval);
1439
95ea3627
ID		 1440 return retval;
1441}
1442
1443/*
1444 * TX descriptor initialization
1445 */
1446static void rt73usb_write_tx_desc(struct rt2x00_dev *rt2x00dev,
906c110f
ID		 1447 struct sk_buff *skb,
1448 struct txentry_desc *txdesc)
95ea3627 1449{
181d6902 1450 struct skb_frame_desc *skbdesc = get_skb_frame_desc(skb);
dd3193e1 1451 __le32 *txd = skbdesc->desc;
95ea3627
ID		 1452 u32 word;
1453
1454 /*
1455 * Start writing the descriptor words.
1456 */
1457 rt2x00_desc_read(txd, 1, &word);
181d6902
ID		 1458 rt2x00_set_field32(&word, TXD_W1_HOST_Q_ID, txdesc->queue);
1459 rt2x00_set_field32(&word, TXD_W1_AIFSN, txdesc->aifs);
1460 rt2x00_set_field32(&word, TXD_W1_CWMIN, txdesc->cw_min);
1461 rt2x00_set_field32(&word, TXD_W1_CWMAX, txdesc->cw_max);
906c110f 1462 rt2x00_set_field32(&word, TXD_W1_IV_OFFSET, txdesc->iv_offset);
5adf6d63
ID		 1463 rt2x00_set_field32(&word, TXD_W1_HW_SEQUENCE,
1464 test_bit(ENTRY_TXD_GENERATE_SEQ, &txdesc->flags));
95ea3627
ID		 1465 rt2x00_desc_write(txd, 1, word);
1466
1467 rt2x00_desc_read(txd, 2, &word);
181d6902
ID		 1468 rt2x00_set_field32(&word, TXD_W2_PLCP_SIGNAL, txdesc->signal);
1469 rt2x00_set_field32(&word, TXD_W2_PLCP_SERVICE, txdesc->service);
1470 rt2x00_set_field32(&word, TXD_W2_PLCP_LENGTH_LOW, txdesc->length_low);
1471 rt2x00_set_field32(&word, TXD_W2_PLCP_LENGTH_HIGH, txdesc->length_high);
95ea3627
ID		 1472 rt2x00_desc_write(txd, 2, word);
1473
906c110f 1474 if (test_bit(ENTRY_TXD_ENCRYPT, &txdesc->flags)) {
1ce9cdac
ID		 1475 _rt2x00_desc_write(txd, 3, skbdesc->iv[0]);
1476 _rt2x00_desc_write(txd, 4, skbdesc->iv[1]);
906c110f
ID		 1477 }
1478
95ea3627
ID		 1479 rt2x00_desc_read(txd, 5, &word);
1480 rt2x00_set_field32(&word, TXD_W5_TX_POWER,
ac1aa7e4 1481 TXPOWER_TO_DEV(rt2x00dev->tx_power));
95ea3627
ID		 1482 rt2x00_set_field32(&word, TXD_W5_WAITING_DMA_DONE_INT, 1);
1483 rt2x00_desc_write(txd, 5, word);
1484
1485 rt2x00_desc_read(txd, 0, &word);
1486 rt2x00_set_field32(&word, TXD_W0_BURST,
181d6902 1487 test_bit(ENTRY_TXD_BURST, &txdesc->flags));
95ea3627
ID		 1488 rt2x00_set_field32(&word, TXD_W0_VALID, 1);
1489 rt2x00_set_field32(&word, TXD_W0_MORE_FRAG,
181d6902 1490 test_bit(ENTRY_TXD_MORE_FRAG, &txdesc->flags));
95ea3627 1491 rt2x00_set_field32(&word, TXD_W0_ACK,
181d6902 1492 test_bit(ENTRY_TXD_ACK, &txdesc->flags));
95ea3627 1493 rt2x00_set_field32(&word, TXD_W0_TIMESTAMP,
181d6902 1494 test_bit(ENTRY_TXD_REQ_TIMESTAMP, &txdesc->flags));
95ea3627 1495 rt2x00_set_field32(&word, TXD_W0_OFDM,
076f9582 1496 (txdesc->rate_mode == RATE_MODE_OFDM));
181d6902 1497 rt2x00_set_field32(&word, TXD_W0_IFS, txdesc->ifs);
95ea3627 1498 rt2x00_set_field32(&word, TXD_W0_RETRY_MODE,
61486e0f 1499 test_bit(ENTRY_TXD_RETRY_MODE, &txdesc->flags));
906c110f
ID		 1500 rt2x00_set_field32(&word, TXD_W0_TKIP_MIC,
1501 test_bit(ENTRY_TXD_ENCRYPT_MMIC, &txdesc->flags));
1502 rt2x00_set_field32(&word, TXD_W0_KEY_TABLE,
1503 test_bit(ENTRY_TXD_ENCRYPT_PAIRWISE, &txdesc->flags));
1504 rt2x00_set_field32(&word, TXD_W0_KEY_INDEX, txdesc->key_idx);
1abc3656 1505 rt2x00_set_field32(&word, TXD_W0_DATABYTE_COUNT, skb->len);
95ea3627 1506 rt2x00_set_field32(&word, TXD_W0_BURST2,
181d6902 1507 test_bit(ENTRY_TXD_BURST, &txdesc->flags));
906c110f 1508 rt2x00_set_field32(&word, TXD_W0_CIPHER_ALG, txdesc->cipher);
95ea3627
ID		 1509 rt2x00_desc_write(txd, 0, word);
1510}
1511
bd88a781
ID		 1512/*
1513 * TX data initialization
1514 */
1515static void rt73usb_write_beacon(struct queue_entry *entry)
1516{
1517 struct rt2x00_dev *rt2x00dev = entry->queue->rt2x00dev;
1518 struct skb_frame_desc *skbdesc = get_skb_frame_desc(entry->skb);
1519 unsigned int beacon_base;
1520 u32 reg;
1521
1522 /*
1523 * Add the descriptor in front of the skb.
1524 */
1525 skb_push(entry->skb, entry->queue->desc_size);
1526 memcpy(entry->skb->data, skbdesc->desc, skbdesc->desc_len);
1527 skbdesc->desc = entry->skb->data;
1528
1529 /*
1530 * Disable beaconing while we are reloading the beacon data,
1531 * otherwise we might be sending out invalid data.
1532 */
0f829b1d 1533 rt2x00usb_register_read(rt2x00dev, TXRX_CSR9, &reg);
bd88a781
ID		 1534 rt2x00_set_field32(&reg, TXRX_CSR9_TSF_TICKING, 0);
1535 rt2x00_set_field32(&reg, TXRX_CSR9_TBTT_ENABLE, 0);
1536 rt2x00_set_field32(&reg, TXRX_CSR9_BEACON_GEN, 0);
0f829b1d 1537 rt2x00usb_register_write(rt2x00dev, TXRX_CSR9, reg);
bd88a781
ID		 1538
1539 /*
1540 * Write entire beacon with descriptor to register.
1541 */
1542 beacon_base = HW_BEACON_OFFSET(entry->entry_idx);
3e0c1abe
IM		 1543 rt2x00usb_vendor_request_large_buff(rt2x00dev, USB_MULTI_WRITE,
1544 USB_VENDOR_REQUEST_OUT, beacon_base,
1545 entry->skb->data, entry->skb->len,
1546 REGISTER_TIMEOUT32(entry->skb->len));
bd88a781
ID		 1547
1548 /*
1549 * Clean up the beacon skb.
1550 */
1551 dev_kfree_skb(entry->skb);
1552 entry->skb = NULL;
1553}
1554
f1ca2167 1555static int rt73usb_get_tx_data_len(struct queue_entry *entry)
dd9fa2d2
ID		 1556{
1557 int length;
1558
1559 /*
1560 * The length _must_ be a multiple of 4,
1561 * but it must _not_ be a multiple of the USB packet size.
1562 */
f1ca2167
ID		 1563 length = roundup(entry->skb->len, 4);
1564 length += (4 * !(length % entry->queue->usb_maxpacket));
dd9fa2d2
ID		 1565
1566 return length;
1567}
1568
95ea3627 1569static void rt73usb_kick_tx_queue(struct rt2x00_dev *rt2x00dev,
e58c6aca 1570 const enum data_queue_qid queue)
95ea3627
ID		 1571{
1572 u32 reg;
1573
f019d514
ID		 1574 if (queue != QID_BEACON) {
1575 rt2x00usb_kick_tx_queue(rt2x00dev, queue);
95ea3627 1576 return;
f019d514 1577 }
95ea3627
ID		 1578
1579 /*
1580 * For Wi-Fi faily generated beacons between participating stations.
1581 * Set TBTT phase adaptive adjustment step to 8us (default 16us)
1582 */
0f829b1d 1583 rt2x00usb_register_write(rt2x00dev, TXRX_CSR10, 0x00001008);
95ea3627 1584
0f829b1d 1585 rt2x00usb_register_read(rt2x00dev, TXRX_CSR9, &reg);
95ea3627 1586 if (!rt2x00_get_field32(reg, TXRX_CSR9_BEACON_GEN)) {
8af244cc
ID		 1587 rt2x00_set_field32(&reg, TXRX_CSR9_TSF_TICKING, 1);
1588 rt2x00_set_field32(&reg, TXRX_CSR9_TBTT_ENABLE, 1);
95ea3627 1589 rt2x00_set_field32(&reg, TXRX_CSR9_BEACON_GEN, 1);
0f829b1d 1590 rt2x00usb_register_write(rt2x00dev, TXRX_CSR9, reg);
95ea3627
ID		 1591 }
1592}
1593
1594/*
1595 * RX control handlers
1596 */
1597static int rt73usb_agc_to_rssi(struct rt2x00_dev *rt2x00dev, int rxd_w1)
1598{
ba2ab471 1599 u8 offset = rt2x00dev->lna_gain;
95ea3627
ID		 1600 u8 lna;
1601
1602 lna = rt2x00_get_field32(rxd_w1, RXD_W1_RSSI_LNA);
1603 switch (lna) {
1604 case 3:
ba2ab471 1605 offset += 90;
95ea3627
ID		 1606 break;
1607 case 2:
ba2ab471 1608 offset += 74;
95ea3627
ID		 1609 break;
1610 case 1:
ba2ab471 1611 offset += 64;
95ea3627
ID		 1612 break;
1613 default:
1614 return 0;
1615 }
1616
8318d78a 1617 if (rt2x00dev->rx_status.band == IEEE80211_BAND_5GHZ) {
95ea3627
ID		 1618 if (test_bit(CONFIG_EXTERNAL_LNA_A, &rt2x00dev->flags)) {
1619 if (lna == 3 || lna == 2)
1620 offset += 10;
1621 } else {
1622 if (lna == 3)
1623 offset += 6;
1624 else if (lna == 2)
1625 offset += 8;
1626 }
95ea3627
ID		 1627 }
1628
1629 return rt2x00_get_field32(rxd_w1, RXD_W1_RSSI_AGC) * 2 - offset;
1630}
1631
181d6902 1632static void rt73usb_fill_rxdone(struct queue_entry *entry,
55887511 1633 struct rxdone_entry_desc *rxdesc)
95ea3627 1634{
906c110f 1635 struct rt2x00_dev *rt2x00dev = entry->queue->rt2x00dev;
181d6902 1636 struct skb_frame_desc *skbdesc = get_skb_frame_desc(entry->skb);
4bd7c452 1637 __le32 *rxd = (__le32 *)entry->skb->data;
95ea3627
ID		 1638 u32 word0;
1639 u32 word1;
1640
f855c10b 1641 /*
a26cbc65
GW		 1642 * Copy descriptor to the skbdesc->desc buffer, making it safe from moving of
1643 * frame data in rt2x00usb.
f855c10b 1644 */
a26cbc65 1645 memcpy(skbdesc->desc, rxd, skbdesc->desc_len);
70a96109 1646 rxd = (__le32 *)skbdesc->desc;
f855c10b
ID		 1647
1648 /*
70a96109 1649 * It is now safe to read the descriptor on all architectures.
f855c10b 1650 */
95ea3627
ID		 1651 rt2x00_desc_read(rxd, 0, &word0);
1652 rt2x00_desc_read(rxd, 1, &word1);
1653
4150c572 1654 if (rt2x00_get_field32(word0, RXD_W0_CRC_ERROR))
181d6902 1655 rxdesc->flags |= RX_FLAG_FAILED_FCS_CRC;
95ea3627 1656
906c110f
ID		 1657 if (test_bit(CONFIG_SUPPORT_HW_CRYPTO, &rt2x00dev->flags)) {
1658 rxdesc->cipher =
1659 rt2x00_get_field32(word0, RXD_W0_CIPHER_ALG);
1660 rxdesc->cipher_status =
1661 rt2x00_get_field32(word0, RXD_W0_CIPHER_ERROR);
1662 }
1663
1664 if (rxdesc->cipher != CIPHER_NONE) {
1ce9cdac
ID		 1665 _rt2x00_desc_read(rxd, 2, &rxdesc->iv[0]);
1666 _rt2x00_desc_read(rxd, 3, &rxdesc->iv[1]);
74415edb
ID		 1667 rxdesc->dev_flags |= RXDONE_CRYPTO_IV;
1668
906c110f 1669 _rt2x00_desc_read(rxd, 4, &rxdesc->icv);
74415edb 1670 rxdesc->dev_flags |= RXDONE_CRYPTO_ICV;
906c110f
ID		 1671
1672 /*
1673 * Hardware has stripped IV/EIV data from 802.11 frame during
1674 * decryption. It has provided the data seperately but rt2x00lib
1675 * should decide if it should be reinserted.
1676 */
1677 rxdesc->flags |= RX_FLAG_IV_STRIPPED;
1678
1679 /*
1680 * FIXME: Legacy driver indicates that the frame does
1681 * contain the Michael Mic. Unfortunately, in rt2x00
1682 * the MIC seems to be missing completely...
1683 */
1684 rxdesc->flags |= RX_FLAG_MMIC_STRIPPED;
1685
1686 if (rxdesc->cipher_status == RX_CRYPTO_SUCCESS)
1687 rxdesc->flags |= RX_FLAG_DECRYPTED;
1688 else if (rxdesc->cipher_status == RX_CRYPTO_FAIL_MIC)
1689 rxdesc->flags |= RX_FLAG_MMIC_ERROR;
1690 }
1691
95ea3627
ID		 1692 /*
1693 * Obtain the status about this packet.
89993890
ID		 1694 * When frame was received with an OFDM bitrate,
1695 * the signal is the PLCP value. If it was received with
1696 * a CCK bitrate the signal is the rate in 100kbit/s.
95ea3627 1697 */
181d6902 1698 rxdesc->signal = rt2x00_get_field32(word1, RXD_W1_SIGNAL);
906c110f 1699 rxdesc->rssi = rt73usb_agc_to_rssi(rt2x00dev, word1);
181d6902 1700 rxdesc->size = rt2x00_get_field32(word0, RXD_W0_DATABYTE_COUNT);
19d30e02 1701
19d30e02
ID		 1702 if (rt2x00_get_field32(word0, RXD_W0_OFDM))
1703 rxdesc->dev_flags |= RXDONE_SIGNAL_PLCP;
6c6aa3c0
ID		 1704 else
1705 rxdesc->dev_flags |= RXDONE_SIGNAL_BITRATE;
19d30e02
ID		 1706 if (rt2x00_get_field32(word0, RXD_W0_MY_BSS))
1707 rxdesc->dev_flags |= RXDONE_MY_BSS;
181d6902 1708
2ae23854 1709 /*
70a96109 1710 * Set skb pointers, and update frame information.
2ae23854 1711 */
70a96109 1712 skb_pull(entry->skb, entry->queue->desc_size);
2ae23854 1713 skb_trim(entry->skb, rxdesc->size);
95ea3627
ID		 1714}
1715
1716/*
1717 * Device probe functions.
1718 */
1719static int rt73usb_validate_eeprom(struct rt2x00_dev *rt2x00dev)
1720{
1721 u16 word;
1722 u8 *mac;
1723 s8 value;
1724
1725 rt2x00usb_eeprom_read(rt2x00dev, rt2x00dev->eeprom, EEPROM_SIZE);
1726
1727 /*
1728 * Start validation of the data that has been read.
1729 */
1730 mac = rt2x00_eeprom_addr(rt2x00dev, EEPROM_MAC_ADDR_0);
1731 if (!is_valid_ether_addr(mac)) {
1732 random_ether_addr(mac);
e174961c 1733 EEPROM(rt2x00dev, "MAC: %pM\n", mac);
95ea3627
ID		 1734 }
1735
1736 rt2x00_eeprom_read(rt2x00dev, EEPROM_ANTENNA, &word);
1737 if (word == 0xffff) {
1738 rt2x00_set_field16(&word, EEPROM_ANTENNA_NUM, 2);
362f3b6b
ID		 1739 rt2x00_set_field16(&word, EEPROM_ANTENNA_TX_DEFAULT,
1740 ANTENNA_B);
1741 rt2x00_set_field16(&word, EEPROM_ANTENNA_RX_DEFAULT,
1742 ANTENNA_B);
95ea3627
ID		 1743 rt2x00_set_field16(&word, EEPROM_ANTENNA_FRAME_TYPE, 0);
1744 rt2x00_set_field16(&word, EEPROM_ANTENNA_DYN_TXAGC, 0);
1745 rt2x00_set_field16(&word, EEPROM_ANTENNA_HARDWARE_RADIO, 0);
1746 rt2x00_set_field16(&word, EEPROM_ANTENNA_RF_TYPE, RF5226);
1747 rt2x00_eeprom_write(rt2x00dev, EEPROM_ANTENNA, word);
1748 EEPROM(rt2x00dev, "Antenna: 0x%04x\n", word);
1749 }
1750
1751 rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC, &word);
1752 if (word == 0xffff) {
1753 rt2x00_set_field16(&word, EEPROM_NIC_EXTERNAL_LNA, 0);
1754 rt2x00_eeprom_write(rt2x00dev, EEPROM_NIC, word);
1755 EEPROM(rt2x00dev, "NIC: 0x%04x\n", word);
1756 }
1757
1758 rt2x00_eeprom_read(rt2x00dev, EEPROM_LED, &word);
1759 if (word == 0xffff) {
1760 rt2x00_set_field16(&word, EEPROM_LED_POLARITY_RDY_G, 0);
1761 rt2x00_set_field16(&word, EEPROM_LED_POLARITY_RDY_A, 0);
1762 rt2x00_set_field16(&word, EEPROM_LED_POLARITY_ACT, 0);
1763 rt2x00_set_field16(&word, EEPROM_LED_POLARITY_GPIO_0, 0);
1764 rt2x00_set_field16(&word, EEPROM_LED_POLARITY_GPIO_1, 0);
1765 rt2x00_set_field16(&word, EEPROM_LED_POLARITY_GPIO_2, 0);
1766 rt2x00_set_field16(&word, EEPROM_LED_POLARITY_GPIO_3, 0);
1767 rt2x00_set_field16(&word, EEPROM_LED_POLARITY_GPIO_4, 0);
1768 rt2x00_set_field16(&word, EEPROM_LED_LED_MODE,
1769 LED_MODE_DEFAULT);
1770 rt2x00_eeprom_write(rt2x00dev, EEPROM_LED, word);
1771 EEPROM(rt2x00dev, "Led: 0x%04x\n", word);
1772 }
1773
1774 rt2x00_eeprom_read(rt2x00dev, EEPROM_FREQ, &word);
1775 if (word == 0xffff) {
1776 rt2x00_set_field16(&word, EEPROM_FREQ_OFFSET, 0);
1777 rt2x00_set_field16(&word, EEPROM_FREQ_SEQ, 0);
1778 rt2x00_eeprom_write(rt2x00dev, EEPROM_FREQ, word);
1779 EEPROM(rt2x00dev, "Freq: 0x%04x\n", word);
1780 }
1781
1782 rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_OFFSET_BG, &word);
1783 if (word == 0xffff) {
1784 rt2x00_set_field16(&word, EEPROM_RSSI_OFFSET_BG_1, 0);
1785 rt2x00_set_field16(&word, EEPROM_RSSI_OFFSET_BG_2, 0);
1786 rt2x00_eeprom_write(rt2x00dev, EEPROM_RSSI_OFFSET_BG, word);
1787 EEPROM(rt2x00dev, "RSSI OFFSET BG: 0x%04x\n", word);
1788 } else {
1789 value = rt2x00_get_field16(word, EEPROM_RSSI_OFFSET_BG_1);
1790 if (value < -10 || value > 10)
1791 rt2x00_set_field16(&word, EEPROM_RSSI_OFFSET_BG_1, 0);
1792 value = rt2x00_get_field16(word, EEPROM_RSSI_OFFSET_BG_2);
1793 if (value < -10 || value > 10)
1794 rt2x00_set_field16(&word, EEPROM_RSSI_OFFSET_BG_2, 0);
1795 rt2x00_eeprom_write(rt2x00dev, EEPROM_RSSI_OFFSET_BG, word);
1796 }
1797
1798 rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_OFFSET_A, &word);
1799 if (word == 0xffff) {
1800 rt2x00_set_field16(&word, EEPROM_RSSI_OFFSET_A_1, 0);
1801 rt2x00_set_field16(&word, EEPROM_RSSI_OFFSET_A_2, 0);
1802 rt2x00_eeprom_write(rt2x00dev, EEPROM_RSSI_OFFSET_A, word);
417f412f 1803 EEPROM(rt2x00dev, "RSSI OFFSET A: 0x%04x\n", word);
95ea3627
ID		 1804 } else {
1805 value = rt2x00_get_field16(word, EEPROM_RSSI_OFFSET_A_1);
1806 if (value < -10 || value > 10)
1807 rt2x00_set_field16(&word, EEPROM_RSSI_OFFSET_A_1, 0);
1808 value = rt2x00_get_field16(word, EEPROM_RSSI_OFFSET_A_2);
1809 if (value < -10 || value > 10)
1810 rt2x00_set_field16(&word, EEPROM_RSSI_OFFSET_A_2, 0);
1811 rt2x00_eeprom_write(rt2x00dev, EEPROM_RSSI_OFFSET_A, word);
1812 }
1813
1814 return 0;
1815}
1816
1817static int rt73usb_init_eeprom(struct rt2x00_dev *rt2x00dev)
1818{
1819 u32 reg;
1820 u16 value;
1821 u16 eeprom;
1822
1823 /*
1824 * Read EEPROM word for configuration.
1825 */
1826 rt2x00_eeprom_read(rt2x00dev, EEPROM_ANTENNA, &eeprom);
1827
1828 /*
1829 * Identify RF chipset.
1830 */
1831 value = rt2x00_get_field16(eeprom, EEPROM_ANTENNA_RF_TYPE);
0f829b1d 1832 rt2x00usb_register_read(rt2x00dev, MAC_CSR0, &reg);
95ea3627
ID		 1833 rt2x00_set_chip(rt2x00dev, RT2571, value, reg);
1834
358623c2 1835 if (!rt2x00_check_rev(&rt2x00dev->chip, 0x000ffff0, 0x25730) ||
5a994011 1836 rt2x00_check_rev(&rt2x00dev->chip, 0x0000000f, 0)) {
95ea3627
ID		 1837 ERROR(rt2x00dev, "Invalid RT chipset detected.\n");
1838 return -ENODEV;
1839 }
1840
1841 if (!rt2x00_rf(&rt2x00dev->chip, RF5226) &&
1842 !rt2x00_rf(&rt2x00dev->chip, RF2528) &&
1843 !rt2x00_rf(&rt2x00dev->chip, RF5225) &&
1844 !rt2x00_rf(&rt2x00dev->chip, RF2527)) {
1845 ERROR(rt2x00dev, "Invalid RF chipset detected.\n");
1846 return -ENODEV;
1847 }
1848
1849 /*
1850 * Identify default antenna configuration.
1851 */
addc81bd 1852 rt2x00dev->default_ant.tx =
95ea3627 1853 rt2x00_get_field16(eeprom, EEPROM_ANTENNA_TX_DEFAULT);
addc81bd 1854 rt2x00dev->default_ant.rx =
95ea3627
ID		 1855 rt2x00_get_field16(eeprom, EEPROM_ANTENNA_RX_DEFAULT);
1856
1857 /*
1858 * Read the Frame type.
1859 */
1860 if (rt2x00_get_field16(eeprom, EEPROM_ANTENNA_FRAME_TYPE))
1861 __set_bit(CONFIG_FRAME_TYPE, &rt2x00dev->flags);
1862
7396faf4
ID		 1863 /*
1864 * Detect if this device has an hardware controlled radio.
1865 */
1866#ifdef CONFIG_RT2X00_LIB_RFKILL
1867 if (rt2x00_get_field16(eeprom, EEPROM_ANTENNA_HARDWARE_RADIO))
1868 __set_bit(CONFIG_SUPPORT_HW_BUTTON, &rt2x00dev->flags);
1869#endif /* CONFIG_RT2X00_LIB_RFKILL */
1870
95ea3627
ID		 1871 /*
1872 * Read frequency offset.
1873 */
1874 rt2x00_eeprom_read(rt2x00dev, EEPROM_FREQ, &eeprom);
1875 rt2x00dev->freq_offset = rt2x00_get_field16(eeprom, EEPROM_FREQ_OFFSET);
1876
1877 /*
1878 * Read external LNA informations.
1879 */
1880 rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC, &eeprom);
1881
1882 if (rt2x00_get_field16(eeprom, EEPROM_NIC_EXTERNAL_LNA)) {
1883 __set_bit(CONFIG_EXTERNAL_LNA_A, &rt2x00dev->flags);
1884 __set_bit(CONFIG_EXTERNAL_LNA_BG, &rt2x00dev->flags);
1885 }
1886
1887 /*
1888 * Store led settings, for correct led behaviour.
1889 */
771fd565 1890#ifdef CONFIG_RT2X00_LIB_LEDS
95ea3627
ID		 1891 rt2x00_eeprom_read(rt2x00dev, EEPROM_LED, &eeprom);
1892
475433be
ID		 1893 rt73usb_init_led(rt2x00dev, &rt2x00dev->led_radio, LED_TYPE_RADIO);
1894 rt73usb_init_led(rt2x00dev, &rt2x00dev->led_assoc, LED_TYPE_ASSOC);
1895 if (value == LED_MODE_SIGNAL_STRENGTH)
1896 rt73usb_init_led(rt2x00dev, &rt2x00dev->led_qual,
1897 LED_TYPE_QUALITY);
a9450b70
ID		 1898
1899 rt2x00_set_field16(&rt2x00dev->led_mcu_reg, MCU_LEDCS_LED_MODE, value);
1900 rt2x00_set_field16(&rt2x00dev->led_mcu_reg, MCU_LEDCS_POLARITY_GPIO_0,
95ea3627
ID		 1901 rt2x00_get_field16(eeprom,
1902 EEPROM_LED_POLARITY_GPIO_0));
a9450b70 1903 rt2x00_set_field16(&rt2x00dev->led_mcu_reg, MCU_LEDCS_POLARITY_GPIO_1,
95ea3627
ID		 1904 rt2x00_get_field16(eeprom,
1905 EEPROM_LED_POLARITY_GPIO_1));
a9450b70 1906 rt2x00_set_field16(&rt2x00dev->led_mcu_reg, MCU_LEDCS_POLARITY_GPIO_2,
95ea3627
ID		 1907 rt2x00_get_field16(eeprom,
1908 EEPROM_LED_POLARITY_GPIO_2));
a9450b70 1909 rt2x00_set_field16(&rt2x00dev->led_mcu_reg, MCU_LEDCS_POLARITY_GPIO_3,
95ea3627
ID		 1910 rt2x00_get_field16(eeprom,
1911 EEPROM_LED_POLARITY_GPIO_3));
a9450b70 1912 rt2x00_set_field16(&rt2x00dev->led_mcu_reg, MCU_LEDCS_POLARITY_GPIO_4,
95ea3627
ID		 1913 rt2x00_get_field16(eeprom,
1914 EEPROM_LED_POLARITY_GPIO_4));
a9450b70 1915 rt2x00_set_field16(&rt2x00dev->led_mcu_reg, MCU_LEDCS_POLARITY_ACT,
95ea3627 1916 rt2x00_get_field16(eeprom, EEPROM_LED_POLARITY_ACT));
a9450b70 1917 rt2x00_set_field16(&rt2x00dev->led_mcu_reg, MCU_LEDCS_POLARITY_READY_BG,
95ea3627
ID		 1918 rt2x00_get_field16(eeprom,
1919 EEPROM_LED_POLARITY_RDY_G));
a9450b70 1920 rt2x00_set_field16(&rt2x00dev->led_mcu_reg, MCU_LEDCS_POLARITY_READY_A,
95ea3627
ID		 1921 rt2x00_get_field16(eeprom,
1922 EEPROM_LED_POLARITY_RDY_A));
771fd565 1923#endif /* CONFIG_RT2X00_LIB_LEDS */
95ea3627
ID		 1924
1925 return 0;
1926}
1927
1928/*
1929 * RF value list for RF2528
1930 * Supports: 2.4 GHz
1931 */
1932static const struct rf_channel rf_vals_bg_2528[] = {
1933 { 1, 0x00002c0c, 0x00000786, 0x00068255, 0x000fea0b },
1934 { 2, 0x00002c0c, 0x00000786, 0x00068255, 0x000fea1f },
1935 { 3, 0x00002c0c, 0x0000078a, 0x00068255, 0x000fea0b },
1936 { 4, 0x00002c0c, 0x0000078a, 0x00068255, 0x000fea1f },
1937 { 5, 0x00002c0c, 0x0000078e, 0x00068255, 0x000fea0b },
1938 { 6, 0x00002c0c, 0x0000078e, 0x00068255, 0x000fea1f },
1939 { 7, 0x00002c0c, 0x00000792, 0x00068255, 0x000fea0b },
1940 { 8, 0x00002c0c, 0x00000792, 0x00068255, 0x000fea1f },
1941 { 9, 0x00002c0c, 0x00000796, 0x00068255, 0x000fea0b },
1942 { 10, 0x00002c0c, 0x00000796, 0x00068255, 0x000fea1f },
1943 { 11, 0x00002c0c, 0x0000079a, 0x00068255, 0x000fea0b },
1944 { 12, 0x00002c0c, 0x0000079a, 0x00068255, 0x000fea1f },
1945 { 13, 0x00002c0c, 0x0000079e, 0x00068255, 0x000fea0b },
1946 { 14, 0x00002c0c, 0x000007a2, 0x00068255, 0x000fea13 },
1947};
1948
1949/*
1950 * RF value list for RF5226
1951 * Supports: 2.4 GHz & 5.2 GHz
1952 */
1953static const struct rf_channel rf_vals_5226[] = {
1954 { 1, 0x00002c0c, 0x00000786, 0x00068255, 0x000fea0b },
1955 { 2, 0x00002c0c, 0x00000786, 0x00068255, 0x000fea1f },
1956 { 3, 0x00002c0c, 0x0000078a, 0x00068255, 0x000fea0b },
1957 { 4, 0x00002c0c, 0x0000078a, 0x00068255, 0x000fea1f },
1958 { 5, 0x00002c0c, 0x0000078e, 0x00068255, 0x000fea0b },
1959 { 6, 0x00002c0c, 0x0000078e, 0x00068255, 0x000fea1f },
1960 { 7, 0x00002c0c, 0x00000792, 0x00068255, 0x000fea0b },
1961 { 8, 0x00002c0c, 0x00000792, 0x00068255, 0x000fea1f },
1962 { 9, 0x00002c0c, 0x00000796, 0x00068255, 0x000fea0b },
1963 { 10, 0x00002c0c, 0x00000796, 0x00068255, 0x000fea1f },
1964 { 11, 0x00002c0c, 0x0000079a, 0x00068255, 0x000fea0b },
1965 { 12, 0x00002c0c, 0x0000079a, 0x00068255, 0x000fea1f },
1966 { 13, 0x00002c0c, 0x0000079e, 0x00068255, 0x000fea0b },
1967 { 14, 0x00002c0c, 0x000007a2, 0x00068255, 0x000fea13 },
1968
1969 /* 802.11 UNI / HyperLan 2 */
1970 { 36, 0x00002c0c, 0x0000099a, 0x00098255, 0x000fea23 },
1971 { 40, 0x00002c0c, 0x000009a2, 0x00098255, 0x000fea03 },
1972 { 44, 0x00002c0c, 0x000009a6, 0x00098255, 0x000fea0b },
1973 { 48, 0x00002c0c, 0x000009aa, 0x00098255, 0x000fea13 },
1974 { 52, 0x00002c0c, 0x000009ae, 0x00098255, 0x000fea1b },
1975 { 56, 0x00002c0c, 0x000009b2, 0x00098255, 0x000fea23 },
1976 { 60, 0x00002c0c, 0x000009ba, 0x00098255, 0x000fea03 },
1977 { 64, 0x00002c0c, 0x000009be, 0x00098255, 0x000fea0b },
1978
1979 /* 802.11 HyperLan 2 */
1980 { 100, 0x00002c0c, 0x00000a2a, 0x000b8255, 0x000fea03 },
1981 { 104, 0x00002c0c, 0x00000a2e, 0x000b8255, 0x000fea0b },
1982 { 108, 0x00002c0c, 0x00000a32, 0x000b8255, 0x000fea13 },
1983 { 112, 0x00002c0c, 0x00000a36, 0x000b8255, 0x000fea1b },
1984 { 116, 0x00002c0c, 0x00000a3a, 0x000b8255, 0x000fea23 },
1985 { 120, 0x00002c0c, 0x00000a82, 0x000b8255, 0x000fea03 },
1986 { 124, 0x00002c0c, 0x00000a86, 0x000b8255, 0x000fea0b },
1987 { 128, 0x00002c0c, 0x00000a8a, 0x000b8255, 0x000fea13 },
1988 { 132, 0x00002c0c, 0x00000a8e, 0x000b8255, 0x000fea1b },
1989 { 136, 0x00002c0c, 0x00000a92, 0x000b8255, 0x000fea23 },
1990
1991 /* 802.11 UNII */
1992 { 140, 0x00002c0c, 0x00000a9a, 0x000b8255, 0x000fea03 },
1993 { 149, 0x00002c0c, 0x00000aa2, 0x000b8255, 0x000fea1f },
1994 { 153, 0x00002c0c, 0x00000aa6, 0x000b8255, 0x000fea27 },
1995 { 157, 0x00002c0c, 0x00000aae, 0x000b8255, 0x000fea07 },
1996 { 161, 0x00002c0c, 0x00000ab2, 0x000b8255, 0x000fea0f },
1997 { 165, 0x00002c0c, 0x00000ab6, 0x000b8255, 0x000fea17 },
1998
1999 /* MMAC(Japan)J52 ch 34,38,42,46 */
2000 { 34, 0x00002c0c, 0x0008099a, 0x000da255, 0x000d3a0b },
2001 { 38, 0x00002c0c, 0x0008099e, 0x000da255, 0x000d3a13 },
2002 { 42, 0x00002c0c, 0x000809a2, 0x000da255, 0x000d3a1b },
2003 { 46, 0x00002c0c, 0x000809a6, 0x000da255, 0x000d3a23 },
2004};
2005
2006/*
2007 * RF value list for RF5225 & RF2527
2008 * Supports: 2.4 GHz & 5.2 GHz
2009 */
2010static const struct rf_channel rf_vals_5225_2527[] = {
2011 { 1, 0x00002ccc, 0x00004786, 0x00068455, 0x000ffa0b },
2012 { 2, 0x00002ccc, 0x00004786, 0x00068455, 0x000ffa1f },
2013 { 3, 0x00002ccc, 0x0000478a, 0x00068455, 0x000ffa0b },
2014 { 4, 0x00002ccc, 0x0000478a, 0x00068455, 0x000ffa1f },
2015 { 5, 0x00002ccc, 0x0000478e, 0x00068455, 0x000ffa0b },
2016 { 6, 0x00002ccc, 0x0000478e, 0x00068455, 0x000ffa1f },
2017 { 7, 0x00002ccc, 0x00004792, 0x00068455, 0x000ffa0b },
2018 { 8, 0x00002ccc, 0x00004792, 0x00068455, 0x000ffa1f },
2019 { 9, 0x00002ccc, 0x00004796, 0x00068455, 0x000ffa0b },
2020 { 10, 0x00002ccc, 0x00004796, 0x00068455, 0x000ffa1f },
2021 { 11, 0x00002ccc, 0x0000479a, 0x00068455, 0x000ffa0b },
2022 { 12, 0x00002ccc, 0x0000479a, 0x00068455, 0x000ffa1f },
2023 { 13, 0x00002ccc, 0x0000479e, 0x00068455, 0x000ffa0b },
2024 { 14, 0x00002ccc, 0x000047a2, 0x00068455, 0x000ffa13 },
2025
2026 /* 802.11 UNI / HyperLan 2 */
2027 { 36, 0x00002ccc, 0x0000499a, 0x0009be55, 0x000ffa23 },
2028 { 40, 0x00002ccc, 0x000049a2, 0x0009be55, 0x000ffa03 },
2029 { 44, 0x00002ccc, 0x000049a6, 0x0009be55, 0x000ffa0b },
2030 { 48, 0x00002ccc, 0x000049aa, 0x0009be55, 0x000ffa13 },
2031 { 52, 0x00002ccc, 0x000049ae, 0x0009ae55, 0x000ffa1b },
2032 { 56, 0x00002ccc, 0x000049b2, 0x0009ae55, 0x000ffa23 },
2033 { 60, 0x00002ccc, 0x000049ba, 0x0009ae55, 0x000ffa03 },
2034 { 64, 0x00002ccc, 0x000049be, 0x0009ae55, 0x000ffa0b },
2035
2036 /* 802.11 HyperLan 2 */
2037 { 100, 0x00002ccc, 0x00004a2a, 0x000bae55, 0x000ffa03 },
2038 { 104, 0x00002ccc, 0x00004a2e, 0x000bae55, 0x000ffa0b },
2039 { 108, 0x00002ccc, 0x00004a32, 0x000bae55, 0x000ffa13 },
2040 { 112, 0x00002ccc, 0x00004a36, 0x000bae55, 0x000ffa1b },
2041 { 116, 0x00002ccc, 0x00004a3a, 0x000bbe55, 0x000ffa23 },
2042 { 120, 0x00002ccc, 0x00004a82, 0x000bbe55, 0x000ffa03 },
2043 { 124, 0x00002ccc, 0x00004a86, 0x000bbe55, 0x000ffa0b },
2044 { 128, 0x00002ccc, 0x00004a8a, 0x000bbe55, 0x000ffa13 },
2045 { 132, 0x00002ccc, 0x00004a8e, 0x000bbe55, 0x000ffa1b },
2046 { 136, 0x00002ccc, 0x00004a92, 0x000bbe55, 0x000ffa23 },
2047
2048 /* 802.11 UNII */
2049 { 140, 0x00002ccc, 0x00004a9a, 0x000bbe55, 0x000ffa03 },
2050 { 149, 0x00002ccc, 0x00004aa2, 0x000bbe55, 0x000ffa1f },
2051 { 153, 0x00002ccc, 0x00004aa6, 0x000bbe55, 0x000ffa27 },
2052 { 157, 0x00002ccc, 0x00004aae, 0x000bbe55, 0x000ffa07 },
2053 { 161, 0x00002ccc, 0x00004ab2, 0x000bbe55, 0x000ffa0f },
2054 { 165, 0x00002ccc, 0x00004ab6, 0x000bbe55, 0x000ffa17 },
2055
2056 /* MMAC(Japan)J52 ch 34,38,42,46 */
2057 { 34, 0x00002ccc, 0x0000499a, 0x0009be55, 0x000ffa0b },
2058 { 38, 0x00002ccc, 0x0000499e, 0x0009be55, 0x000ffa13 },
2059 { 42, 0x00002ccc, 0x000049a2, 0x0009be55, 0x000ffa1b },
2060 { 46, 0x00002ccc, 0x000049a6, 0x0009be55, 0x000ffa23 },
2061};
2062
2063
8c5e7a5f 2064static int rt73usb_probe_hw_mode(struct rt2x00_dev *rt2x00dev)
95ea3627
ID		 2065{
2066 struct hw_mode_spec *spec = &rt2x00dev->spec;
8c5e7a5f
ID		 2067 struct channel_info *info;
2068 char *tx_power;
95ea3627
ID		 2069 unsigned int i;
2070
2071 /*
2072 * Initialize all hw fields.
2073 */
2074 rt2x00dev->hw->flags =
566bfe5a 2075 IEEE80211_HW_HOST_BROADCAST_PS_BUFFERING |
4be8c387
JB		 2076 IEEE80211_HW_SIGNAL_DBM |
2077 IEEE80211_HW_SUPPORTS_PS |
2078 IEEE80211_HW_PS_NULLFUNC_STACK;
95ea3627 2079 rt2x00dev->hw->extra_tx_headroom = TXD_DESC_SIZE;
95ea3627 2080
14a3bf89 2081 SET_IEEE80211_DEV(rt2x00dev->hw, rt2x00dev->dev);
95ea3627
ID		 2082 SET_IEEE80211_PERM_ADDR(rt2x00dev->hw,
2083 rt2x00_eeprom_addr(rt2x00dev,
2084 EEPROM_MAC_ADDR_0));
2085
95ea3627
ID		 2086 /*
2087 * Initialize hw_mode information.
2088 */
31562e80
ID		 2089 spec->supported_bands = SUPPORT_BAND_2GHZ;
2090 spec->supported_rates = SUPPORT_RATE_CCK | SUPPORT_RATE_OFDM;
95ea3627
ID		 2091
2092 if (rt2x00_rf(&rt2x00dev->chip, RF2528)) {
2093 spec->num_channels = ARRAY_SIZE(rf_vals_bg_2528);
2094 spec->channels = rf_vals_bg_2528;
2095 } else if (rt2x00_rf(&rt2x00dev->chip, RF5226)) {
31562e80 2096 spec->supported_bands |= SUPPORT_BAND_5GHZ;
95ea3627
ID		 2097 spec->num_channels = ARRAY_SIZE(rf_vals_5226);
2098 spec->channels = rf_vals_5226;
2099 } else if (rt2x00_rf(&rt2x00dev->chip, RF2527)) {
2100 spec->num_channels = 14;
2101 spec->channels = rf_vals_5225_2527;
2102 } else if (rt2x00_rf(&rt2x00dev->chip, RF5225)) {
31562e80 2103 spec->supported_bands |= SUPPORT_BAND_5GHZ;
95ea3627
ID		 2104 spec->num_channels = ARRAY_SIZE(rf_vals_5225_2527);
2105 spec->channels = rf_vals_5225_2527;
2106 }
2107
8c5e7a5f
ID		 2108 /*
2109 * Create channel information array
2110 */
2111 info = kzalloc(spec->num_channels * sizeof(*info), GFP_KERNEL);
2112 if (!info)
2113 return -ENOMEM;
95ea3627 2114
8c5e7a5f
ID		 2115 spec->channels_info = info;
2116
2117 tx_power = rt2x00_eeprom_addr(rt2x00dev, EEPROM_TXPOWER_G_START);
2118 for (i = 0; i < 14; i++)
2119 info[i].tx_power1 = TXPOWER_FROM_DEV(tx_power[i]);
2120
2121 if (spec->num_channels > 14) {
2122 tx_power = rt2x00_eeprom_addr(rt2x00dev, EEPROM_TXPOWER_A_START);
2123 for (i = 14; i < spec->num_channels; i++)
2124 info[i].tx_power1 = TXPOWER_FROM_DEV(tx_power[i]);
95ea3627 2125 }
8c5e7a5f
ID		 2126
2127 return 0;
95ea3627
ID		 2128}
2129
2130static int rt73usb_probe_hw(struct rt2x00_dev *rt2x00dev)
2131{
2132 int retval;
2133
2134 /*
2135 * Allocate eeprom data.
2136 */
2137 retval = rt73usb_validate_eeprom(rt2x00dev);
2138 if (retval)
2139 return retval;
2140
2141 retval = rt73usb_init_eeprom(rt2x00dev);
2142 if (retval)
2143 return retval;
2144
2145 /*
2146 * Initialize hw specifications.
2147 */
8c5e7a5f
ID		 2148 retval = rt73usb_probe_hw_mode(rt2x00dev);
2149 if (retval)
2150 return retval;
95ea3627
ID		 2151
2152 /*
9404ef34 2153 * This device requires firmware.
95ea3627 2154 */
066cb637 2155 __set_bit(DRIVER_REQUIRE_FIRMWARE, &rt2x00dev->flags);
3a643d24 2156 __set_bit(DRIVER_REQUIRE_SCHEDULED, &rt2x00dev->flags);
008c4482
ID		 2157 if (!modparam_nohwcrypt)
2158 __set_bit(CONFIG_SUPPORT_HW_CRYPTO, &rt2x00dev->flags);
95ea3627
ID		 2159
2160 /*
2161 * Set the rssi offset.
2162 */
2163 rt2x00dev->rssi_offset = DEFAULT_RSSI_OFFSET;
2164
2165 return 0;
2166}
2167
2168/*
2169 * IEEE80211 stack callback functions.
2170 */
2af0a570
ID		 2171static int rt73usb_conf_tx(struct ieee80211_hw *hw, u16 queue_idx,
2172 const struct ieee80211_tx_queue_params *params)
2173{
2174 struct rt2x00_dev *rt2x00dev = hw->priv;
2175 struct data_queue *queue;
2176 struct rt2x00_field32 field;
2177 int retval;
2178 u32 reg;
5e790023 2179 u32 offset;
2af0a570
ID		 2180
2181 /*
2182 * First pass the configuration through rt2x00lib, that will
2183 * update the queue settings and validate the input. After that
2184 * we are free to update the registers based on the value
2185 * in the queue parameter.
2186 */
2187 retval = rt2x00mac_conf_tx(hw, queue_idx, params);
2188 if (retval)
2189 return retval;
2190
5e790023
ID		 2191 /*
2192 * We only need to perform additional register initialization
2193 * for WMM queues/
2194 */
2195 if (queue_idx >= 4)
2196 return 0;
2197
2af0a570
ID		 2198 queue = rt2x00queue_get_queue(rt2x00dev, queue_idx);
2199
2200 /* Update WMM TXOP register */
5e790023
ID		 2201 offset = AC_TXOP_CSR0 + (sizeof(u32) * (!!(queue_idx & 2)));
2202 field.bit_offset = (queue_idx & 1) * 16;
2203 field.bit_mask = 0xffff << field.bit_offset;
2204
2205 rt2x00usb_register_read(rt2x00dev, offset, &reg);
2206 rt2x00_set_field32(&reg, field, queue->txop);
2207 rt2x00usb_register_write(rt2x00dev, offset, reg);
2af0a570
ID		 2208
2209 /* Update WMM registers */
2210 field.bit_offset = queue_idx * 4;
2211 field.bit_mask = 0xf << field.bit_offset;
2212
0f829b1d 2213 rt2x00usb_register_read(rt2x00dev, AIFSN_CSR, &reg);
2af0a570 2214 rt2x00_set_field32(&reg, field, queue->aifs);
0f829b1d 2215 rt2x00usb_register_write(rt2x00dev, AIFSN_CSR, reg);
2af0a570 2216
0f829b1d 2217 rt2x00usb_register_read(rt2x00dev, CWMIN_CSR, &reg);
2af0a570 2218 rt2x00_set_field32(&reg, field, queue->cw_min);
0f829b1d 2219 rt2x00usb_register_write(rt2x00dev, CWMIN_CSR, reg);
2af0a570 2220
0f829b1d 2221 rt2x00usb_register_read(rt2x00dev, CWMAX_CSR, &reg);
2af0a570 2222 rt2x00_set_field32(&reg, field, queue->cw_max);
0f829b1d 2223 rt2x00usb_register_write(rt2x00dev, CWMAX_CSR, reg);
2af0a570
ID		 2224
2225 return 0;
2226}
2227
95ea3627
ID		 2228static u64 rt73usb_get_tsf(struct ieee80211_hw *hw)
2229{
2230 struct rt2x00_dev *rt2x00dev = hw->priv;
2231 u64 tsf;
2232 u32 reg;
2233
0f829b1d 2234 rt2x00usb_register_read(rt2x00dev, TXRX_CSR13, &reg);
95ea3627 2235 tsf = (u64) rt2x00_get_field32(reg, TXRX_CSR13_HIGH_TSFTIMER) << 32;
0f829b1d 2236 rt2x00usb_register_read(rt2x00dev, TXRX_CSR12, &reg);
95ea3627
ID		 2237 tsf |= rt2x00_get_field32(reg, TXRX_CSR12_LOW_TSFTIMER);
2238
2239 return tsf;
2240}
95ea3627 2241
95ea3627
ID		 2242static const struct ieee80211_ops rt73usb_mac80211_ops = {
2243 .tx = rt2x00mac_tx,
4150c572
JB		 2244 .start = rt2x00mac_start,
2245 .stop = rt2x00mac_stop,
95ea3627
ID		 2246 .add_interface = rt2x00mac_add_interface,
2247 .remove_interface = rt2x00mac_remove_interface,
2248 .config = rt2x00mac_config,
3a643d24 2249 .configure_filter = rt2x00mac_configure_filter,
906c110f 2250 .set_key = rt2x00mac_set_key,
95ea3627 2251 .get_stats = rt2x00mac_get_stats,
471b3efd 2252 .bss_info_changed = rt2x00mac_bss_info_changed,
2af0a570 2253 .conf_tx = rt73usb_conf_tx,
95ea3627 2254 .get_tx_stats = rt2x00mac_get_tx_stats,
95ea3627 2255 .get_tsf = rt73usb_get_tsf,
95ea3627
ID		 2256};
2257
2258static const struct rt2x00lib_ops rt73usb_rt2x00_ops = {
2259 .probe_hw = rt73usb_probe_hw,
2260 .get_firmware_name = rt73usb_get_firmware_name,
0cbe0064 2261 .check_firmware = rt73usb_check_firmware,
95ea3627
ID		 2262 .load_firmware = rt73usb_load_firmware,
2263 .initialize = rt2x00usb_initialize,
2264 .uninitialize = rt2x00usb_uninitialize,
798b7adb 2265 .clear_entry = rt2x00usb_clear_entry,
95ea3627 2266 .set_device_state = rt73usb_set_device_state,
7396faf4 2267 .rfkill_poll = rt73usb_rfkill_poll,
95ea3627
ID		 2268 .link_stats = rt73usb_link_stats,
2269 .reset_tuner = rt73usb_reset_tuner,
2270 .link_tuner = rt73usb_link_tuner,
2271 .write_tx_desc = rt73usb_write_tx_desc,
2272 .write_tx_data = rt2x00usb_write_tx_data,
bd88a781 2273 .write_beacon = rt73usb_write_beacon,
dd9fa2d2 2274 .get_tx_data_len = rt73usb_get_tx_data_len,
95ea3627 2275 .kick_tx_queue = rt73usb_kick_tx_queue,
a2c9b652 2276 .kill_tx_queue = rt2x00usb_kill_tx_queue,
95ea3627 2277 .fill_rxdone = rt73usb_fill_rxdone,
906c110f
ID		 2278 .config_shared_key = rt73usb_config_shared_key,
2279 .config_pairwise_key = rt73usb_config_pairwise_key,
3a643d24 2280 .config_filter = rt73usb_config_filter,
6bb40dd1 2281 .config_intf = rt73usb_config_intf,
72810379 2282 .config_erp = rt73usb_config_erp,
e4ea1c40 2283 .config_ant = rt73usb_config_ant,
95ea3627
ID		 2284 .config = rt73usb_config,
2285};
2286
181d6902
ID		 2287static const struct data_queue_desc rt73usb_queue_rx = {
2288 .entry_num = RX_ENTRIES,
2289 .data_size = DATA_FRAME_SIZE,
2290 .desc_size = RXD_DESC_SIZE,
b8be63ff 2291 .priv_size = sizeof(struct queue_entry_priv_usb),
181d6902
ID		 2292};
2293
2294static const struct data_queue_desc rt73usb_queue_tx = {
2295 .entry_num = TX_ENTRIES,
2296 .data_size = DATA_FRAME_SIZE,
2297 .desc_size = TXD_DESC_SIZE,
b8be63ff 2298 .priv_size = sizeof(struct queue_entry_priv_usb),
181d6902
ID		 2299};
2300
2301static const struct data_queue_desc rt73usb_queue_bcn = {
6bb40dd1 2302 .entry_num = 4 * BEACON_ENTRIES,
181d6902
ID		 2303 .data_size = MGMT_FRAME_SIZE,
2304 .desc_size = TXINFO_SIZE,
b8be63ff 2305 .priv_size = sizeof(struct queue_entry_priv_usb),
181d6902
ID		 2306};
2307
95ea3627 2308static const struct rt2x00_ops rt73usb_ops = {
2360157c 2309 .name = KBUILD_MODNAME,
6bb40dd1
ID		 2310 .max_sta_intf = 1,
2311 .max_ap_intf = 4,
95ea3627
ID		 2312 .eeprom_size = EEPROM_SIZE,
2313 .rf_size = RF_SIZE,
61448f88 2314 .tx_queues = NUM_TX_QUEUES,
181d6902
ID		 2315 .rx = &rt73usb_queue_rx,
2316 .tx = &rt73usb_queue_tx,
2317 .bcn = &rt73usb_queue_bcn,
95ea3627
ID		 2318 .lib = &rt73usb_rt2x00_ops,
2319 .hw = &rt73usb_mac80211_ops,
2320#ifdef CONFIG_RT2X00_LIB_DEBUGFS
2321 .debugfs = &rt73usb_rt2x00debug,
2322#endif /* CONFIG_RT2X00_LIB_DEBUGFS */
2323};
2324
2325/*
2326 * rt73usb module information.
2327 */
2328static struct usb_device_id rt73usb_device_table[] = {
2329 /* AboCom */
ef4bb70d
XVP		 2330 { USB_DEVICE(0x07b8, 0xb21b), USB_DEVICE_DATA(&rt73usb_ops) },
2331 { USB_DEVICE(0x07b8, 0xb21c), USB_DEVICE_DATA(&rt73usb_ops) },
95ea3627 2332 { USB_DEVICE(0x07b8, 0xb21d), USB_DEVICE_DATA(&rt73usb_ops) },
ef4bb70d
XVP		 2333 { USB_DEVICE(0x07b8, 0xb21e), USB_DEVICE_DATA(&rt73usb_ops) },
2334 { USB_DEVICE(0x07b8, 0xb21f), USB_DEVICE_DATA(&rt73usb_ops) },
2335 /* AL */
2336 { USB_DEVICE(0x14b2, 0x3c10), USB_DEVICE_DATA(&rt73usb_ops) },
144d9ad9
ID		 2337 /* Amigo */
2338 { USB_DEVICE(0x148f, 0x9021), USB_DEVICE_DATA(&rt73usb_ops) },
2339 { USB_DEVICE(0x0eb0, 0x9021), USB_DEVICE_DATA(&rt73usb_ops) },
ef4bb70d
XVP		 2340 /* AMIT */
2341 { USB_DEVICE(0x18c5, 0x0002), USB_DEVICE_DATA(&rt73usb_ops) },
95ea3627
ID		 2342 /* Askey */
2343 { USB_DEVICE(0x1690, 0x0722), USB_DEVICE_DATA(&rt73usb_ops) },
2344 /* ASUS */
2345 { USB_DEVICE(0x0b05, 0x1723), USB_DEVICE_DATA(&rt73usb_ops) },
2346 { USB_DEVICE(0x0b05, 0x1724), USB_DEVICE_DATA(&rt73usb_ops) },
2347 /* Belkin */
2348 { USB_DEVICE(0x050d, 0x7050), USB_DEVICE_DATA(&rt73usb_ops) },
2349 { USB_DEVICE(0x050d, 0x705a), USB_DEVICE_DATA(&rt73usb_ops) },
2350 { USB_DEVICE(0x050d, 0x905b), USB_DEVICE_DATA(&rt73usb_ops) },
1f06862e 2351 { USB_DEVICE(0x050d, 0x905c), USB_DEVICE_DATA(&rt73usb_ops) },
95ea3627
ID		 2352 /* Billionton */
2353 { USB_DEVICE(0x1631, 0xc019), USB_DEVICE_DATA(&rt73usb_ops) },
ef4bb70d 2354 { USB_DEVICE(0x08dd, 0x0120), USB_DEVICE_DATA(&rt73usb_ops) },
95ea3627 2355 /* Buffalo */
964d6ad9 2356 { USB_DEVICE(0x0411, 0x00d8), USB_DEVICE_DATA(&rt73usb_ops) },
95ea3627 2357 { USB_DEVICE(0x0411, 0x00f4), USB_DEVICE_DATA(&rt73usb_ops) },
6aabd4c4
ID		 2358 { USB_DEVICE(0x0411, 0x0116), USB_DEVICE_DATA(&rt73usb_ops) },
2359 { USB_DEVICE(0x0411, 0x0119), USB_DEVICE_DATA(&rt73usb_ops) },
95ea3627
ID		 2360 /* CNet */
2361 { USB_DEVICE(0x1371, 0x9022), USB_DEVICE_DATA(&rt73usb_ops) },
2362 { USB_DEVICE(0x1371, 0x9032), USB_DEVICE_DATA(&rt73usb_ops) },
2363 /* Conceptronic */
2364 { USB_DEVICE(0x14b2, 0x3c22), USB_DEVICE_DATA(&rt73usb_ops) },
0a74892b
MM		 2365 /* Corega */
2366 { USB_DEVICE(0x07aa, 0x002e), USB_DEVICE_DATA(&rt73usb_ops) },
95ea3627
ID		 2367 /* D-Link */
2368 { USB_DEVICE(0x07d1, 0x3c03), USB_DEVICE_DATA(&rt73usb_ops) },
2369 { USB_DEVICE(0x07d1, 0x3c04), USB_DEVICE_DATA(&rt73usb_ops) },
cb62eccd 2370 { USB_DEVICE(0x07d1, 0x3c06), USB_DEVICE_DATA(&rt73usb_ops) },
445815d7 2371 { USB_DEVICE(0x07d1, 0x3c07), USB_DEVICE_DATA(&rt73usb_ops) },
ef4bb70d
XVP		 2372 /* Edimax */
2373 { USB_DEVICE(0x7392, 0x7318), USB_DEVICE_DATA(&rt73usb_ops) },
2374 { USB_DEVICE(0x7392, 0x7618), USB_DEVICE_DATA(&rt73usb_ops) },
2375 /* EnGenius */
2376 { USB_DEVICE(0x1740, 0x3701), USB_DEVICE_DATA(&rt73usb_ops) },
95ea3627
ID		 2377 /* Gemtek */
2378 { USB_DEVICE(0x15a9, 0x0004), USB_DEVICE_DATA(&rt73usb_ops) },
2379 /* Gigabyte */
2380 { USB_DEVICE(0x1044, 0x8008), USB_DEVICE_DATA(&rt73usb_ops) },
2381 { USB_DEVICE(0x1044, 0x800a), USB_DEVICE_DATA(&rt73usb_ops) },
2382 /* Huawei-3Com */
2383 { USB_DEVICE(0x1472, 0x0009), USB_DEVICE_DATA(&rt73usb_ops) },
2384 /* Hercules */
2385 { USB_DEVICE(0x06f8, 0xe010), USB_DEVICE_DATA(&rt73usb_ops) },
2386 { USB_DEVICE(0x06f8, 0xe020), USB_DEVICE_DATA(&rt73usb_ops) },
2387 /* Linksys */
2388 { USB_DEVICE(0x13b1, 0x0020), USB_DEVICE_DATA(&rt73usb_ops) },
2389 { USB_DEVICE(0x13b1, 0x0023), USB_DEVICE_DATA(&rt73usb_ops) },
3be36ae2 2390 { USB_DEVICE(0x13b1, 0x0028), USB_DEVICE_DATA(&rt73usb_ops) },
95ea3627
ID		 2391 /* MSI */
2392 { USB_DEVICE(0x0db0, 0x6877), USB_DEVICE_DATA(&rt73usb_ops) },
2393 { USB_DEVICE(0x0db0, 0x6874), USB_DEVICE_DATA(&rt73usb_ops) },
2394 { USB_DEVICE(0x0db0, 0xa861), USB_DEVICE_DATA(&rt73usb_ops) },
2395 { USB_DEVICE(0x0db0, 0xa874), USB_DEVICE_DATA(&rt73usb_ops) },
2396 /* Ralink */
144d9ad9 2397 { USB_DEVICE(0x04bb, 0x093d), USB_DEVICE_DATA(&rt73usb_ops) },
95ea3627
ID		 2398 { USB_DEVICE(0x148f, 0x2573), USB_DEVICE_DATA(&rt73usb_ops) },
2399 { USB_DEVICE(0x148f, 0x2671), USB_DEVICE_DATA(&rt73usb_ops) },
2400 /* Qcom */
2401 { USB_DEVICE(0x18e8, 0x6196), USB_DEVICE_DATA(&rt73usb_ops) },
2402 { USB_DEVICE(0x18e8, 0x6229), USB_DEVICE_DATA(&rt73usb_ops) },
2403 { USB_DEVICE(0x18e8, 0x6238), USB_DEVICE_DATA(&rt73usb_ops) },
ef4bb70d
XVP		 2404 /* Samsung */
2405 { USB_DEVICE(0x04e8, 0x4471), USB_DEVICE_DATA(&rt73usb_ops) },
95ea3627
ID		 2406 /* Senao */
2407 { USB_DEVICE(0x1740, 0x7100), USB_DEVICE_DATA(&rt73usb_ops) },
2408 /* Sitecom */
ef4bb70d
XVP		 2409 { USB_DEVICE(0x0df6, 0x0024), USB_DEVICE_DATA(&rt73usb_ops) },
2410 { USB_DEVICE(0x0df6, 0x0027), USB_DEVICE_DATA(&rt73usb_ops) },
2411 { USB_DEVICE(0x0df6, 0x002f), USB_DEVICE_DATA(&rt73usb_ops) },
95ea3627 2412 { USB_DEVICE(0x0df6, 0x90ac), USB_DEVICE_DATA(&rt73usb_ops) },
ef4bb70d 2413 { USB_DEVICE(0x0df6, 0x9712), USB_DEVICE_DATA(&rt73usb_ops) },
95ea3627
ID		 2414 /* Surecom */
2415 { USB_DEVICE(0x0769, 0x31f3), USB_DEVICE_DATA(&rt73usb_ops) },
14344b81
ID		 2416 /* Tilgin */
2417 { USB_DEVICE(0x6933, 0x5001), USB_DEVICE_DATA(&rt73usb_ops) },
ef4bb70d
XVP		 2418 /* Philips */
2419 { USB_DEVICE(0x0471, 0x200a), USB_DEVICE_DATA(&rt73usb_ops) },
95ea3627
ID		 2420 /* Planex */
2421 { USB_DEVICE(0x2019, 0xab01), USB_DEVICE_DATA(&rt73usb_ops) },
2422 { USB_DEVICE(0x2019, 0xab50), USB_DEVICE_DATA(&rt73usb_ops) },
ef4bb70d
XVP		 2423 /* Zcom */
2424 { USB_DEVICE(0x0cde, 0x001c), USB_DEVICE_DATA(&rt73usb_ops) },
144d9ad9
ID		 2425 /* ZyXEL */
2426 { USB_DEVICE(0x0586, 0x3415), USB_DEVICE_DATA(&rt73usb_ops) },
95ea3627
ID		 2427 { 0, }
2428};
2429
2430MODULE_AUTHOR(DRV_PROJECT);
2431MODULE_VERSION(DRV_VERSION);
2432MODULE_DESCRIPTION("Ralink RT73 USB Wireless LAN driver.");
2433MODULE_SUPPORTED_DEVICE("Ralink RT2571W & RT2671 USB chipset based cards");
2434MODULE_DEVICE_TABLE(usb, rt73usb_device_table);
2435MODULE_FIRMWARE(FIRMWARE_RT2571);
2436MODULE_LICENSE("GPL");
2437
2438static struct usb_driver rt73usb_driver = {
2360157c 2439 .name = KBUILD_MODNAME,
95ea3627
ID		 2440 .id_table = rt73usb_device_table,
2441 .probe = rt2x00usb_probe,
2442 .disconnect = rt2x00usb_disconnect,
2443 .suspend = rt2x00usb_suspend,
2444 .resume = rt2x00usb_resume,
2445};
2446
2447static int __init rt73usb_init(void)
2448{
2449 return usb_register(&rt73usb_driver);
2450}
2451
2452static void __exit rt73usb_exit(void)
2453{
2454 usb_deregister(&rt73usb_driver);
2455}
2456
2457module_init(rt73usb_init);
2458module_exit(rt73usb_exit);
Linux kernel - Deliverables
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