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rt2x00: Support for large vendor requests
[deliverable/linux.git] / drivers / net / wireless / rt2x00 / rt73usb.c
CommitLineData
95ea3627 1/*
811aa9ca 2 Copyright (C) 2004 - 2008 rt2x00 SourceForge Project
95ea3627
ID		 3 <http://rt2x00.serialmonkey.com>
4
5 This program is free software; you can redistribute it and/or modify
6 it under the terms of the GNU General Public License as published by
7 the Free Software Foundation; either version 2 of the License, or
8 (at your option) any later version.
9
10 This program is distributed in the hope that it will be useful,
11 but WITHOUT ANY WARRANTY; without even the implied warranty of
12 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 GNU General Public License for more details.
14
15 You should have received a copy of the GNU General Public License
16 along with this program; if not, write to the
17 Free Software Foundation, Inc.,
18 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
19 */
20
21/*
22 Module: rt73usb
23 Abstract: rt73usb device specific routines.
24 Supported chipsets: rt2571W & rt2671.
25 */
26
a7f3a06c 27#include <linux/crc-itu-t.h>
95ea3627
ID		 28#include <linux/delay.h>
29#include <linux/etherdevice.h>
30#include <linux/init.h>
31#include <linux/kernel.h>
32#include <linux/module.h>
33#include <linux/usb.h>
34
35#include "rt2x00.h"
36#include "rt2x00usb.h"
37#include "rt73usb.h"
38
39/*
40 * Register access.
41 * All access to the CSR registers will go through the methods
42 * rt73usb_register_read and rt73usb_register_write.
43 * BBP and RF register require indirect register access,
44 * and use the CSR registers BBPCSR and RFCSR to achieve this.
45 * These indirect registers work with busy bits,
46 * and we will try maximal REGISTER_BUSY_COUNT times to access
47 * the register while taking a REGISTER_BUSY_DELAY us delay
48 * between each attampt. When the busy bit is still set at that time,
49 * the access attempt is considered to have failed,
50 * and we will print an error.
3d82346c 51 * The _lock versions must be used if you already hold the usb_cache_mutex
95ea3627 52 */
0e14f6d3 53static inline void rt73usb_register_read(struct rt2x00_dev *rt2x00dev,
95ea3627
ID		 54 const unsigned int offset, u32 *value)
55{
56 __le32 reg;
57 rt2x00usb_vendor_request_buff(rt2x00dev, USB_MULTI_READ,
58 USB_VENDOR_REQUEST_IN, offset,
59 &reg, sizeof(u32), REGISTER_TIMEOUT);
60 *value = le32_to_cpu(reg);
61}
62
3d82346c
AB		 63static inline void rt73usb_register_read_lock(struct rt2x00_dev *rt2x00dev,
64 const unsigned int offset, u32 *value)
65{
66 __le32 reg;
67 rt2x00usb_vendor_req_buff_lock(rt2x00dev, USB_MULTI_READ,
68 USB_VENDOR_REQUEST_IN, offset,
69 &reg, sizeof(u32), REGISTER_TIMEOUT);
70 *value = le32_to_cpu(reg);
71}
72
0e14f6d3 73static inline void rt73usb_register_multiread(struct rt2x00_dev *rt2x00dev,
95ea3627
ID		 74 const unsigned int offset,
75 void *value, const u32 length)
76{
95ea3627
ID		 77 rt2x00usb_vendor_request_buff(rt2x00dev, USB_MULTI_READ,
78 USB_VENDOR_REQUEST_IN, offset,
bd394a74
ID		 79 value, length,
80 REGISTER_TIMEOUT32(length));
95ea3627
ID		 81}
82
0e14f6d3 83static inline void rt73usb_register_write(struct rt2x00_dev *rt2x00dev,
95ea3627
ID		 84 const unsigned int offset, u32 value)
85{
86 __le32 reg = cpu_to_le32(value);
87 rt2x00usb_vendor_request_buff(rt2x00dev, USB_MULTI_WRITE,
88 USB_VENDOR_REQUEST_OUT, offset,
89 &reg, sizeof(u32), REGISTER_TIMEOUT);
90}
91
3d82346c
AB		 92static inline void rt73usb_register_write_lock(struct rt2x00_dev *rt2x00dev,
93 const unsigned int offset, u32 value)
94{
95 __le32 reg = cpu_to_le32(value);
96 rt2x00usb_vendor_req_buff_lock(rt2x00dev, USB_MULTI_WRITE,
97 USB_VENDOR_REQUEST_OUT, offset,
98 &reg, sizeof(u32), REGISTER_TIMEOUT);
99}
100
0e14f6d3 101static inline void rt73usb_register_multiwrite(struct rt2x00_dev *rt2x00dev,
95ea3627
ID		 102 const unsigned int offset,
103 void *value, const u32 length)
104{
95ea3627
ID		 105 rt2x00usb_vendor_request_buff(rt2x00dev, USB_MULTI_WRITE,
106 USB_VENDOR_REQUEST_OUT, offset,
bd394a74
ID		 107 value, length,
108 REGISTER_TIMEOUT32(length));
95ea3627
ID		 109}
110
0e14f6d3 111static u32 rt73usb_bbp_check(struct rt2x00_dev *rt2x00dev)
95ea3627
ID		 112{
113 u32 reg;
114 unsigned int i;
115
116 for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
3d82346c 117 rt73usb_register_read_lock(rt2x00dev, PHY_CSR3, &reg);
95ea3627
ID		 118 if (!rt2x00_get_field32(reg, PHY_CSR3_BUSY))
119 break;
120 udelay(REGISTER_BUSY_DELAY);
121 }
122
123 return reg;
124}
125
0e14f6d3 126static void rt73usb_bbp_write(struct rt2x00_dev *rt2x00dev,
95ea3627
ID		 127 const unsigned int word, const u8 value)
128{
129 u32 reg;
130
3d82346c
AB		 131 mutex_lock(&rt2x00dev->usb_cache_mutex);
132
95ea3627
ID		 133 /*
134 * Wait until the BBP becomes ready.
135 */
136 reg = rt73usb_bbp_check(rt2x00dev);
99ade259
ID		 137 if (rt2x00_get_field32(reg, PHY_CSR3_BUSY))
138 goto exit_fail;
95ea3627
ID		 139
140 /*
141 * Write the data into the BBP.
142 */
143 reg = 0;
144 rt2x00_set_field32(&reg, PHY_CSR3_VALUE, value);
145 rt2x00_set_field32(&reg, PHY_CSR3_REGNUM, word);
146 rt2x00_set_field32(&reg, PHY_CSR3_BUSY, 1);
147 rt2x00_set_field32(&reg, PHY_CSR3_READ_CONTROL, 0);
148
3d82346c
AB		 149 rt73usb_register_write_lock(rt2x00dev, PHY_CSR3, reg);
150 mutex_unlock(&rt2x00dev->usb_cache_mutex);
99ade259
ID		 151
152 return;
153
154exit_fail:
155 mutex_unlock(&rt2x00dev->usb_cache_mutex);
156
157 ERROR(rt2x00dev, "PHY_CSR3 register busy. Write failed.\n");
95ea3627
ID		 158}
159
0e14f6d3 160static void rt73usb_bbp_read(struct rt2x00_dev *rt2x00dev,
95ea3627
ID		 161 const unsigned int word, u8 *value)
162{
163 u32 reg;
164
3d82346c
AB		 165 mutex_lock(&rt2x00dev->usb_cache_mutex);
166
95ea3627
ID		 167 /*
168 * Wait until the BBP becomes ready.
169 */
170 reg = rt73usb_bbp_check(rt2x00dev);
99ade259
ID		 171 if (rt2x00_get_field32(reg, PHY_CSR3_BUSY))
172 goto exit_fail;
95ea3627
ID		 173
174 /*
175 * Write the request into the BBP.
176 */
177 reg = 0;
178 rt2x00_set_field32(&reg, PHY_CSR3_REGNUM, word);
179 rt2x00_set_field32(&reg, PHY_CSR3_BUSY, 1);
180 rt2x00_set_field32(&reg, PHY_CSR3_READ_CONTROL, 1);
181
3d82346c 182 rt73usb_register_write_lock(rt2x00dev, PHY_CSR3, reg);
95ea3627
ID		 183
184 /*
185 * Wait until the BBP becomes ready.
186 */
187 reg = rt73usb_bbp_check(rt2x00dev);
99ade259
ID		 188 if (rt2x00_get_field32(reg, PHY_CSR3_BUSY))
189 goto exit_fail;
95ea3627
ID		 190
191 *value = rt2x00_get_field32(reg, PHY_CSR3_VALUE);
3d82346c 192 mutex_unlock(&rt2x00dev->usb_cache_mutex);
99ade259
ID		 193
194 return;
195
196exit_fail:
197 mutex_unlock(&rt2x00dev->usb_cache_mutex);
198
199 ERROR(rt2x00dev, "PHY_CSR3 register busy. Read failed.\n");
200 *value = 0xff;
95ea3627
ID		 201}
202
0e14f6d3 203static void rt73usb_rf_write(struct rt2x00_dev *rt2x00dev,
95ea3627
ID		 204 const unsigned int word, const u32 value)
205{
206 u32 reg;
207 unsigned int i;
208
209 if (!word)
210 return;
211
3d82346c
AB		 212 mutex_lock(&rt2x00dev->usb_cache_mutex);
213
95ea3627 214 for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
3d82346c 215 rt73usb_register_read_lock(rt2x00dev, PHY_CSR4, &reg);
95ea3627
ID		 216 if (!rt2x00_get_field32(reg, PHY_CSR4_BUSY))
217 goto rf_write;
218 udelay(REGISTER_BUSY_DELAY);
219 }
220
3d82346c 221 mutex_unlock(&rt2x00dev->usb_cache_mutex);
95ea3627
ID		 222 ERROR(rt2x00dev, "PHY_CSR4 register busy. Write failed.\n");
223 return;
224
225rf_write:
226 reg = 0;
227 rt2x00_set_field32(&reg, PHY_CSR4_VALUE, value);
228
4f5af6eb
ID		 229 /*
230 * RF5225 and RF2527 contain 21 bits per RF register value,
231 * all others contain 20 bits.
232 */
233 rt2x00_set_field32(&reg, PHY_CSR4_NUMBER_OF_BITS,
ddc827f9
ID		 234 20 + (rt2x00_rf(&rt2x00dev->chip, RF5225) ||
235 rt2x00_rf(&rt2x00dev->chip, RF2527)));
95ea3627
ID		 236 rt2x00_set_field32(&reg, PHY_CSR4_IF_SELECT, 0);
237 rt2x00_set_field32(&reg, PHY_CSR4_BUSY, 1);
238
3d82346c 239 rt73usb_register_write_lock(rt2x00dev, PHY_CSR4, reg);
95ea3627 240 rt2x00_rf_write(rt2x00dev, word, value);
3d82346c 241 mutex_unlock(&rt2x00dev->usb_cache_mutex);
95ea3627
ID		 242}
243
244#ifdef CONFIG_RT2X00_LIB_DEBUGFS
245#define CSR_OFFSET(__word) ( CSR_REG_BASE + ((__word) * sizeof(u32)) )
246
0e14f6d3 247static void rt73usb_read_csr(struct rt2x00_dev *rt2x00dev,
95ea3627
ID		 248 const unsigned int word, u32 *data)
249{
250 rt73usb_register_read(rt2x00dev, CSR_OFFSET(word), data);
251}
252
0e14f6d3 253static void rt73usb_write_csr(struct rt2x00_dev *rt2x00dev,
95ea3627
ID		 254 const unsigned int word, u32 data)
255{
256 rt73usb_register_write(rt2x00dev, CSR_OFFSET(word), data);
257}
258
259static const struct rt2x00debug rt73usb_rt2x00debug = {
260 .owner = THIS_MODULE,
261 .csr = {
262 .read = rt73usb_read_csr,
263 .write = rt73usb_write_csr,
264 .word_size = sizeof(u32),
265 .word_count = CSR_REG_SIZE / sizeof(u32),
266 },
267 .eeprom = {
268 .read = rt2x00_eeprom_read,
269 .write = rt2x00_eeprom_write,
270 .word_size = sizeof(u16),
271 .word_count = EEPROM_SIZE / sizeof(u16),
272 },
273 .bbp = {
274 .read = rt73usb_bbp_read,
275 .write = rt73usb_bbp_write,
276 .word_size = sizeof(u8),
277 .word_count = BBP_SIZE / sizeof(u8),
278 },
279 .rf = {
280 .read = rt2x00_rf_read,
281 .write = rt73usb_rf_write,
282 .word_size = sizeof(u32),
283 .word_count = RF_SIZE / sizeof(u32),
284 },
285};
286#endif /* CONFIG_RT2X00_LIB_DEBUGFS */
287
a9450b70 288#ifdef CONFIG_RT73USB_LEDS
a2e1d52a 289static void rt73usb_brightness_set(struct led_classdev *led_cdev,
a9450b70
ID		 290 enum led_brightness brightness)
291{
292 struct rt2x00_led *led =
293 container_of(led_cdev, struct rt2x00_led, led_dev);
294 unsigned int enabled = brightness != LED_OFF;
295 unsigned int a_mode =
296 (enabled && led->rt2x00dev->curr_band == IEEE80211_BAND_5GHZ);
297 unsigned int bg_mode =
298 (enabled && led->rt2x00dev->curr_band == IEEE80211_BAND_2GHZ);
299
300 if (led->type == LED_TYPE_RADIO) {
301 rt2x00_set_field16(&led->rt2x00dev->led_mcu_reg,
302 MCU_LEDCS_RADIO_STATUS, enabled);
303
47b10cd1
ID		 304 rt2x00usb_vendor_request_sw(led->rt2x00dev, USB_LED_CONTROL,
305 0, led->rt2x00dev->led_mcu_reg,
306 REGISTER_TIMEOUT);
a9450b70
ID		 307 } else if (led->type == LED_TYPE_ASSOC) {
308 rt2x00_set_field16(&led->rt2x00dev->led_mcu_reg,
309 MCU_LEDCS_LINK_BG_STATUS, bg_mode);
310 rt2x00_set_field16(&led->rt2x00dev->led_mcu_reg,
311 MCU_LEDCS_LINK_A_STATUS, a_mode);
312
47b10cd1
ID		 313 rt2x00usb_vendor_request_sw(led->rt2x00dev, USB_LED_CONTROL,
314 0, led->rt2x00dev->led_mcu_reg,
315 REGISTER_TIMEOUT);
a9450b70
ID		 316 } else if (led->type == LED_TYPE_QUALITY) {
317 /*
318 * The brightness is divided into 6 levels (0 - 5),
319 * this means we need to convert the brightness
320 * argument into the matching level within that range.
321 */
47b10cd1
ID		 322 rt2x00usb_vendor_request_sw(led->rt2x00dev, USB_LED_CONTROL,
323 brightness / (LED_FULL / 6),
324 led->rt2x00dev->led_mcu_reg,
325 REGISTER_TIMEOUT);
a9450b70
ID		 326 }
327}
a2e1d52a
ID		 328
329static int rt73usb_blink_set(struct led_classdev *led_cdev,
330 unsigned long *delay_on,
331 unsigned long *delay_off)
332{
333 struct rt2x00_led *led =
334 container_of(led_cdev, struct rt2x00_led, led_dev);
335 u32 reg;
336
337 rt73usb_register_read(led->rt2x00dev, MAC_CSR14, &reg);
338 rt2x00_set_field32(&reg, MAC_CSR14_ON_PERIOD, *delay_on);
339 rt2x00_set_field32(&reg, MAC_CSR14_OFF_PERIOD, *delay_off);
340 rt73usb_register_write(led->rt2x00dev, MAC_CSR14, reg);
341
342 return 0;
343}
475433be
ID		 344
345static void rt73usb_init_led(struct rt2x00_dev *rt2x00dev,
346 struct rt2x00_led *led,
347 enum led_type type)
348{
349 led->rt2x00dev = rt2x00dev;
350 led->type = type;
351 led->led_dev.brightness_set = rt73usb_brightness_set;
352 led->led_dev.blink_set = rt73usb_blink_set;
353 led->flags = LED_INITIALIZED;
354}
a9450b70
ID		 355#endif /* CONFIG_RT73USB_LEDS */
356
95ea3627
ID		 357/*
358 * Configuration handlers.
359 */
3a643d24
ID		 360static void rt73usb_config_filter(struct rt2x00_dev *rt2x00dev,
361 const unsigned int filter_flags)
362{
363 u32 reg;
364
365 /*
366 * Start configuration steps.
367 * Note that the version error will always be dropped
368 * and broadcast frames will always be accepted since
369 * there is no filter for it at this time.
370 */
371 rt73usb_register_read(rt2x00dev, TXRX_CSR0, &reg);
372 rt2x00_set_field32(&reg, TXRX_CSR0_DROP_CRC,
373 !(filter_flags & FIF_FCSFAIL));
374 rt2x00_set_field32(&reg, TXRX_CSR0_DROP_PHYSICAL,
375 !(filter_flags & FIF_PLCPFAIL));
376 rt2x00_set_field32(&reg, TXRX_CSR0_DROP_CONTROL,
377 !(filter_flags & FIF_CONTROL));
378 rt2x00_set_field32(&reg, TXRX_CSR0_DROP_NOT_TO_ME,
379 !(filter_flags & FIF_PROMISC_IN_BSS));
380 rt2x00_set_field32(&reg, TXRX_CSR0_DROP_TO_DS,
e0b005fa
ID		 381 !(filter_flags & FIF_PROMISC_IN_BSS) &&
382 !rt2x00dev->intf_ap_count);
3a643d24
ID		 383 rt2x00_set_field32(&reg, TXRX_CSR0_DROP_VERSION_ERROR, 1);
384 rt2x00_set_field32(&reg, TXRX_CSR0_DROP_MULTICAST,
385 !(filter_flags & FIF_ALLMULTI));
386 rt2x00_set_field32(&reg, TXRX_CSR0_DROP_BROADCAST, 0);
387 rt2x00_set_field32(&reg, TXRX_CSR0_DROP_ACK_CTS,
388 !(filter_flags & FIF_CONTROL));
389 rt73usb_register_write(rt2x00dev, TXRX_CSR0, reg);
390}
391
6bb40dd1
ID		 392static void rt73usb_config_intf(struct rt2x00_dev *rt2x00dev,
393 struct rt2x00_intf *intf,
394 struct rt2x00intf_conf *conf,
395 const unsigned int flags)
95ea3627 396{
6bb40dd1
ID		 397 unsigned int beacon_base;
398 u32 reg;
95ea3627 399
6bb40dd1
ID		 400 if (flags & CONFIG_UPDATE_TYPE) {
401 /*
402 * Clear current synchronisation setup.
403 * For the Beacon base registers we only need to clear
404 * the first byte since that byte contains the VALID and OWNER
405 * bits which (when set to 0) will invalidate the entire beacon.
406 */
407 beacon_base = HW_BEACON_OFFSET(intf->beacon->entry_idx);
6bb40dd1 408 rt73usb_register_write(rt2x00dev, beacon_base, 0);
95ea3627 409
6bb40dd1
ID		 410 /*
411 * Enable synchronisation.
412 */
413 rt73usb_register_read(rt2x00dev, TXRX_CSR9, &reg);
fd3c91c5 414 rt2x00_set_field32(&reg, TXRX_CSR9_TSF_TICKING, 1);
6bb40dd1 415 rt2x00_set_field32(&reg, TXRX_CSR9_TSF_SYNC, conf->sync);
fd3c91c5 416 rt2x00_set_field32(&reg, TXRX_CSR9_TBTT_ENABLE, 1);
6bb40dd1
ID		 417 rt73usb_register_write(rt2x00dev, TXRX_CSR9, reg);
418 }
95ea3627 419
6bb40dd1
ID		 420 if (flags & CONFIG_UPDATE_MAC) {
421 reg = le32_to_cpu(conf->mac[1]);
422 rt2x00_set_field32(&reg, MAC_CSR3_UNICAST_TO_ME_MASK, 0xff);
423 conf->mac[1] = cpu_to_le32(reg);
95ea3627 424
6bb40dd1
ID		 425 rt73usb_register_multiwrite(rt2x00dev, MAC_CSR2,
426 conf->mac, sizeof(conf->mac));
427 }
95ea3627 428
6bb40dd1
ID		 429 if (flags & CONFIG_UPDATE_BSSID) {
430 reg = le32_to_cpu(conf->bssid[1]);
431 rt2x00_set_field32(&reg, MAC_CSR5_BSS_ID_MASK, 3);
432 conf->bssid[1] = cpu_to_le32(reg);
95ea3627 433
6bb40dd1
ID		 434 rt73usb_register_multiwrite(rt2x00dev, MAC_CSR4,
435 conf->bssid, sizeof(conf->bssid));
436 }
95ea3627
ID		 437}
438
3a643d24
ID		 439static void rt73usb_config_erp(struct rt2x00_dev *rt2x00dev,
440 struct rt2x00lib_erp *erp)
95ea3627 441{
95ea3627 442 u32 reg;
95ea3627 443
95ea3627 444 rt73usb_register_read(rt2x00dev, TXRX_CSR0, &reg);
72810379 445 rt2x00_set_field32(&reg, TXRX_CSR0_RX_ACK_TIMEOUT, erp->ack_timeout);
95ea3627
ID		 446 rt73usb_register_write(rt2x00dev, TXRX_CSR0, reg);
447
448 rt73usb_register_read(rt2x00dev, TXRX_CSR4, &reg);
4f5af6eb 449 rt2x00_set_field32(&reg, TXRX_CSR4_AUTORESPOND_PREAMBLE,
72810379 450 !!erp->short_preamble);
95ea3627
ID		 451 rt73usb_register_write(rt2x00dev, TXRX_CSR4, reg);
452}
453
454static void rt73usb_config_phymode(struct rt2x00_dev *rt2x00dev,
5c58ee51 455 const int basic_rate_mask)
95ea3627 456{
5c58ee51 457 rt73usb_register_write(rt2x00dev, TXRX_CSR5, basic_rate_mask);
95ea3627
ID		 458}
459
5c58ee51
ID		 460static void rt73usb_config_channel(struct rt2x00_dev *rt2x00dev,
461 struct rf_channel *rf, const int txpower)
95ea3627
ID		 462{
463 u8 r3;
464 u8 r94;
465 u8 smart;
466
467 rt2x00_set_field32(&rf->rf3, RF3_TXPOWER, TXPOWER_TO_DEV(txpower));
468 rt2x00_set_field32(&rf->rf4, RF4_FREQ_OFFSET, rt2x00dev->freq_offset);
469
470 smart = !(rt2x00_rf(&rt2x00dev->chip, RF5225) ||
471 rt2x00_rf(&rt2x00dev->chip, RF2527));
472
473 rt73usb_bbp_read(rt2x00dev, 3, &r3);
474 rt2x00_set_field8(&r3, BBP_R3_SMART_MODE, smart);
475 rt73usb_bbp_write(rt2x00dev, 3, r3);
476
477 r94 = 6;
478 if (txpower > MAX_TXPOWER && txpower <= (MAX_TXPOWER + r94))
479 r94 += txpower - MAX_TXPOWER;
480 else if (txpower < MIN_TXPOWER && txpower >= (MIN_TXPOWER - r94))
481 r94 += txpower;
482 rt73usb_bbp_write(rt2x00dev, 94, r94);
483
484 rt73usb_rf_write(rt2x00dev, 1, rf->rf1);
485 rt73usb_rf_write(rt2x00dev, 2, rf->rf2);
486 rt73usb_rf_write(rt2x00dev, 3, rf->rf3 & ~0x00000004);
487 rt73usb_rf_write(rt2x00dev, 4, rf->rf4);
488
489 rt73usb_rf_write(rt2x00dev, 1, rf->rf1);
490 rt73usb_rf_write(rt2x00dev, 2, rf->rf2);
491 rt73usb_rf_write(rt2x00dev, 3, rf->rf3 | 0x00000004);
492 rt73usb_rf_write(rt2x00dev, 4, rf->rf4);
493
494 rt73usb_rf_write(rt2x00dev, 1, rf->rf1);
495 rt73usb_rf_write(rt2x00dev, 2, rf->rf2);
496 rt73usb_rf_write(rt2x00dev, 3, rf->rf3 & ~0x00000004);
497 rt73usb_rf_write(rt2x00dev, 4, rf->rf4);
498
499 udelay(10);
500}
501
95ea3627
ID		 502static void rt73usb_config_txpower(struct rt2x00_dev *rt2x00dev,
503 const int txpower)
504{
505 struct rf_channel rf;
506
507 rt2x00_rf_read(rt2x00dev, 1, &rf.rf1);
508 rt2x00_rf_read(rt2x00dev, 2, &rf.rf2);
509 rt2x00_rf_read(rt2x00dev, 3, &rf.rf3);
510 rt2x00_rf_read(rt2x00dev, 4, &rf.rf4);
511
5c58ee51 512 rt73usb_config_channel(rt2x00dev, &rf, txpower);
95ea3627
ID		 513}
514
515static void rt73usb_config_antenna_5x(struct rt2x00_dev *rt2x00dev,
addc81bd 516 struct antenna_setup *ant)
95ea3627
ID		 517{
518 u8 r3;
519 u8 r4;
520 u8 r77;
2676c94d 521 u8 temp;
95ea3627
ID		 522
523 rt73usb_bbp_read(rt2x00dev, 3, &r3);
524 rt73usb_bbp_read(rt2x00dev, 4, &r4);
525 rt73usb_bbp_read(rt2x00dev, 77, &r77);
526
527 rt2x00_set_field8(&r3, BBP_R3_SMART_MODE, 0);
528
e4cd2ff8
ID		 529 /*
530 * Configure the RX antenna.
531 */
addc81bd 532 switch (ant->rx) {
95ea3627 533 case ANTENNA_HW_DIVERSITY:
2676c94d
MN		 534 rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA_CONTROL, 2);
535 temp = !test_bit(CONFIG_FRAME_TYPE, &rt2x00dev->flags)
8318d78a 536 && (rt2x00dev->curr_band != IEEE80211_BAND_5GHZ);
2676c94d 537 rt2x00_set_field8(&r4, BBP_R4_RX_FRAME_END, temp);
95ea3627
ID		 538 break;
539 case ANTENNA_A:
2676c94d 540 rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA_CONTROL, 1);
95ea3627 541 rt2x00_set_field8(&r4, BBP_R4_RX_FRAME_END, 0);
8318d78a 542 if (rt2x00dev->curr_band == IEEE80211_BAND_5GHZ)
2676c94d
MN		 543 rt2x00_set_field8(&r77, BBP_R77_RX_ANTENNA, 0);
544 else
545 rt2x00_set_field8(&r77, BBP_R77_RX_ANTENNA, 3);
95ea3627
ID		 546 break;
547 case ANTENNA_B:
a4fe07d9 548 default:
2676c94d 549 rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA_CONTROL, 1);
95ea3627 550 rt2x00_set_field8(&r4, BBP_R4_RX_FRAME_END, 0);
8318d78a 551 if (rt2x00dev->curr_band == IEEE80211_BAND_5GHZ)
2676c94d
MN		 552 rt2x00_set_field8(&r77, BBP_R77_RX_ANTENNA, 3);
553 else
554 rt2x00_set_field8(&r77, BBP_R77_RX_ANTENNA, 0);
95ea3627
ID		 555 break;
556 }
557
558 rt73usb_bbp_write(rt2x00dev, 77, r77);
559 rt73usb_bbp_write(rt2x00dev, 3, r3);
560 rt73usb_bbp_write(rt2x00dev, 4, r4);
561}
562
563static void rt73usb_config_antenna_2x(struct rt2x00_dev *rt2x00dev,
addc81bd 564 struct antenna_setup *ant)
95ea3627
ID		 565{
566 u8 r3;
567 u8 r4;
568 u8 r77;
569
570 rt73usb_bbp_read(rt2x00dev, 3, &r3);
571 rt73usb_bbp_read(rt2x00dev, 4, &r4);
572 rt73usb_bbp_read(rt2x00dev, 77, &r77);
573
574 rt2x00_set_field8(&r3, BBP_R3_SMART_MODE, 0);
575 rt2x00_set_field8(&r4, BBP_R4_RX_FRAME_END,
576 !test_bit(CONFIG_FRAME_TYPE, &rt2x00dev->flags));
577
e4cd2ff8
ID		 578 /*
579 * Configure the RX antenna.
580 */
addc81bd 581 switch (ant->rx) {
95ea3627 582 case ANTENNA_HW_DIVERSITY:
2676c94d 583 rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA_CONTROL, 2);
95ea3627
ID		 584 break;
585 case ANTENNA_A:
2676c94d
MN		 586 rt2x00_set_field8(&r77, BBP_R77_RX_ANTENNA, 3);
587 rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA_CONTROL, 1);
95ea3627
ID		 588 break;
589 case ANTENNA_B:
a4fe07d9 590 default:
2676c94d
MN		 591 rt2x00_set_field8(&r77, BBP_R77_RX_ANTENNA, 0);
592 rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA_CONTROL, 1);
95ea3627
ID		 593 break;
594 }
595
596 rt73usb_bbp_write(rt2x00dev, 77, r77);
597 rt73usb_bbp_write(rt2x00dev, 3, r3);
598 rt73usb_bbp_write(rt2x00dev, 4, r4);
599}
600
601struct antenna_sel {
602 u8 word;
603 /*
604 * value[0] -> non-LNA
605 * value[1] -> LNA
606 */
607 u8 value[2];
608};
609
610static const struct antenna_sel antenna_sel_a[] = {
611 { 96, { 0x58, 0x78 } },
612 { 104, { 0x38, 0x48 } },
613 { 75, { 0xfe, 0x80 } },
614 { 86, { 0xfe, 0x80 } },
615 { 88, { 0xfe, 0x80 } },
616 { 35, { 0x60, 0x60 } },
617 { 97, { 0x58, 0x58 } },
618 { 98, { 0x58, 0x58 } },
619};
620
621static const struct antenna_sel antenna_sel_bg[] = {
622 { 96, { 0x48, 0x68 } },
623 { 104, { 0x2c, 0x3c } },
624 { 75, { 0xfe, 0x80 } },
625 { 86, { 0xfe, 0x80 } },
626 { 88, { 0xfe, 0x80 } },
627 { 35, { 0x50, 0x50 } },
628 { 97, { 0x48, 0x48 } },
629 { 98, { 0x48, 0x48 } },
630};
631
632static void rt73usb_config_antenna(struct rt2x00_dev *rt2x00dev,
addc81bd 633 struct antenna_setup *ant)
95ea3627
ID		 634{
635 const struct antenna_sel *sel;
636 unsigned int lna;
637 unsigned int i;
638 u32 reg;
639
a4fe07d9
ID		 640 /*
641 * We should never come here because rt2x00lib is supposed
642 * to catch this and send us the correct antenna explicitely.
643 */
644 BUG_ON(ant->rx == ANTENNA_SW_DIVERSITY ||
645 ant->tx == ANTENNA_SW_DIVERSITY);
646
8318d78a 647 if (rt2x00dev->curr_band == IEEE80211_BAND_5GHZ) {
95ea3627
ID		 648 sel = antenna_sel_a;
649 lna = test_bit(CONFIG_EXTERNAL_LNA_A, &rt2x00dev->flags);
95ea3627
ID		 650 } else {
651 sel = antenna_sel_bg;
652 lna = test_bit(CONFIG_EXTERNAL_LNA_BG, &rt2x00dev->flags);
95ea3627
ID		 653 }
654
2676c94d
MN		 655 for (i = 0; i < ARRAY_SIZE(antenna_sel_a); i++)
656 rt73usb_bbp_write(rt2x00dev, sel[i].word, sel[i].value[lna]);
657
658 rt73usb_register_read(rt2x00dev, PHY_CSR0, &reg);
659
ddc827f9 660 rt2x00_set_field32(&reg, PHY_CSR0_PA_PE_BG,
8318d78a 661 (rt2x00dev->curr_band == IEEE80211_BAND_2GHZ));
ddc827f9 662 rt2x00_set_field32(&reg, PHY_CSR0_PA_PE_A,
8318d78a 663 (rt2x00dev->curr_band == IEEE80211_BAND_5GHZ));
ddc827f9 664
95ea3627
ID		 665 rt73usb_register_write(rt2x00dev, PHY_CSR0, reg);
666
667 if (rt2x00_rf(&rt2x00dev->chip, RF5226) ||
668 rt2x00_rf(&rt2x00dev->chip, RF5225))
addc81bd 669 rt73usb_config_antenna_5x(rt2x00dev, ant);
95ea3627
ID		 670 else if (rt2x00_rf(&rt2x00dev->chip, RF2528) ||
671 rt2x00_rf(&rt2x00dev->chip, RF2527))
addc81bd 672 rt73usb_config_antenna_2x(rt2x00dev, ant);
95ea3627
ID		 673}
674
675static void rt73usb_config_duration(struct rt2x00_dev *rt2x00dev,
5c58ee51 676 struct rt2x00lib_conf *libconf)
95ea3627
ID		 677{
678 u32 reg;
679
680 rt73usb_register_read(rt2x00dev, MAC_CSR9, &reg);
5c58ee51 681 rt2x00_set_field32(&reg, MAC_CSR9_SLOT_TIME, libconf->slot_time);
95ea3627
ID		 682 rt73usb_register_write(rt2x00dev, MAC_CSR9, reg);
683
684 rt73usb_register_read(rt2x00dev, MAC_CSR8, &reg);
5c58ee51 685 rt2x00_set_field32(&reg, MAC_CSR8_SIFS, libconf->sifs);
95ea3627 686 rt2x00_set_field32(&reg, MAC_CSR8_SIFS_AFTER_RX_OFDM, 3);
5c58ee51 687 rt2x00_set_field32(&reg, MAC_CSR8_EIFS, libconf->eifs);
95ea3627
ID		 688 rt73usb_register_write(rt2x00dev, MAC_CSR8, reg);
689
690 rt73usb_register_read(rt2x00dev, TXRX_CSR0, &reg);
691 rt2x00_set_field32(&reg, TXRX_CSR0_TSF_OFFSET, IEEE80211_HEADER);
692 rt73usb_register_write(rt2x00dev, TXRX_CSR0, reg);
693
694 rt73usb_register_read(rt2x00dev, TXRX_CSR4, &reg);
695 rt2x00_set_field32(&reg, TXRX_CSR4_AUTORESPOND_ENABLE, 1);
696 rt73usb_register_write(rt2x00dev, TXRX_CSR4, reg);
697
698 rt73usb_register_read(rt2x00dev, TXRX_CSR9, &reg);
5c58ee51
ID		 699 rt2x00_set_field32(&reg, TXRX_CSR9_BEACON_INTERVAL,
700 libconf->conf->beacon_int * 16);
95ea3627
ID		 701 rt73usb_register_write(rt2x00dev, TXRX_CSR9, reg);
702}
703
704static void rt73usb_config(struct rt2x00_dev *rt2x00dev,
6bb40dd1
ID		 705 struct rt2x00lib_conf *libconf,
706 const unsigned int flags)
95ea3627 707{
95ea3627 708 if (flags & CONFIG_UPDATE_PHYMODE)
5c58ee51 709 rt73usb_config_phymode(rt2x00dev, libconf->basic_rates);
95ea3627 710 if (flags & CONFIG_UPDATE_CHANNEL)
5c58ee51
ID		 711 rt73usb_config_channel(rt2x00dev, &libconf->rf,
712 libconf->conf->power_level);
95ea3627 713 if ((flags & CONFIG_UPDATE_TXPOWER) && !(flags & CONFIG_UPDATE_CHANNEL))
5c58ee51 714 rt73usb_config_txpower(rt2x00dev, libconf->conf->power_level);
95ea3627 715 if (flags & CONFIG_UPDATE_ANTENNA)
addc81bd 716 rt73usb_config_antenna(rt2x00dev, &libconf->ant);
95ea3627 717 if (flags & (CONFIG_UPDATE_SLOT_TIME | CONFIG_UPDATE_BEACON_INT))
5c58ee51 718 rt73usb_config_duration(rt2x00dev, libconf);
95ea3627
ID		 719}
720
95ea3627
ID		 721/*
722 * Link tuning
723 */
ebcf26da
ID		 724static void rt73usb_link_stats(struct rt2x00_dev *rt2x00dev,
725 struct link_qual *qual)
95ea3627
ID		 726{
727 u32 reg;
728
729 /*
730 * Update FCS error count from register.
731 */
732 rt73usb_register_read(rt2x00dev, STA_CSR0, &reg);
ebcf26da 733 qual->rx_failed = rt2x00_get_field32(reg, STA_CSR0_FCS_ERROR);
95ea3627
ID		 734
735 /*
736 * Update False CCA count from register.
737 */
738 rt73usb_register_read(rt2x00dev, STA_CSR1, &reg);
ebcf26da 739 qual->false_cca = rt2x00_get_field32(reg, STA_CSR1_FALSE_CCA_ERROR);
95ea3627
ID		 740}
741
742static void rt73usb_reset_tuner(struct rt2x00_dev *rt2x00dev)
743{
744 rt73usb_bbp_write(rt2x00dev, 17, 0x20);
745 rt2x00dev->link.vgc_level = 0x20;
746}
747
748static void rt73usb_link_tuner(struct rt2x00_dev *rt2x00dev)
749{
750 int rssi = rt2x00_get_link_rssi(&rt2x00dev->link);
751 u8 r17;
752 u8 up_bound;
753 u8 low_bound;
754
95ea3627
ID		 755 rt73usb_bbp_read(rt2x00dev, 17, &r17);
756
757 /*
758 * Determine r17 bounds.
759 */
8318d78a 760 if (rt2x00dev->rx_status.band == IEEE80211_BAND_5GHZ) {
95ea3627
ID		 761 low_bound = 0x28;
762 up_bound = 0x48;
763
764 if (test_bit(CONFIG_EXTERNAL_LNA_A, &rt2x00dev->flags)) {
765 low_bound += 0x10;
766 up_bound += 0x10;
767 }
768 } else {
769 if (rssi > -82) {
770 low_bound = 0x1c;
771 up_bound = 0x40;
772 } else if (rssi > -84) {
773 low_bound = 0x1c;
774 up_bound = 0x20;
775 } else {
776 low_bound = 0x1c;
777 up_bound = 0x1c;
778 }
779
780 if (test_bit(CONFIG_EXTERNAL_LNA_BG, &rt2x00dev->flags)) {
781 low_bound += 0x14;
782 up_bound += 0x10;
783 }
784 }
785
6bb40dd1
ID		 786 /*
787 * If we are not associated, we should go straight to the
788 * dynamic CCA tuning.
789 */
790 if (!rt2x00dev->intf_associated)
791 goto dynamic_cca_tune;
792
95ea3627
ID		 793 /*
794 * Special big-R17 for very short distance
795 */
796 if (rssi > -35) {
797 if (r17 != 0x60)
798 rt73usb_bbp_write(rt2x00dev, 17, 0x60);
799 return;
800 }
801
802 /*
803 * Special big-R17 for short distance
804 */
805 if (rssi >= -58) {
806 if (r17 != up_bound)
807 rt73usb_bbp_write(rt2x00dev, 17, up_bound);
808 return;
809 }
810
811 /*
812 * Special big-R17 for middle-short distance
813 */
814 if (rssi >= -66) {
815 low_bound += 0x10;
816 if (r17 != low_bound)
817 rt73usb_bbp_write(rt2x00dev, 17, low_bound);
818 return;
819 }
820
821 /*
822 * Special mid-R17 for middle distance
823 */
824 if (rssi >= -74) {
825 if (r17 != (low_bound + 0x10))
826 rt73usb_bbp_write(rt2x00dev, 17, low_bound + 0x08);
827 return;
828 }
829
830 /*
831 * Special case: Change up_bound based on the rssi.
832 * Lower up_bound when rssi is weaker then -74 dBm.
833 */
834 up_bound -= 2 * (-74 - rssi);
835 if (low_bound > up_bound)
836 up_bound = low_bound;
837
838 if (r17 > up_bound) {
839 rt73usb_bbp_write(rt2x00dev, 17, up_bound);
840 return;
841 }
842
6bb40dd1
ID		 843dynamic_cca_tune:
844
95ea3627
ID		 845 /*
846 * r17 does not yet exceed upper limit, continue and base
847 * the r17 tuning on the false CCA count.
848 */
ebcf26da 849 if (rt2x00dev->link.qual.false_cca > 512 && r17 < up_bound) {
95ea3627
ID		 850 r17 += 4;
851 if (r17 > up_bound)
852 r17 = up_bound;
853 rt73usb_bbp_write(rt2x00dev, 17, r17);
ebcf26da 854 } else if (rt2x00dev->link.qual.false_cca < 100 && r17 > low_bound) {
95ea3627
ID		 855 r17 -= 4;
856 if (r17 < low_bound)
857 r17 = low_bound;
858 rt73usb_bbp_write(rt2x00dev, 17, r17);
859 }
860}
861
862/*
a7f3a06c 863 * Firmware functions
95ea3627
ID		 864 */
865static char *rt73usb_get_firmware_name(struct rt2x00_dev *rt2x00dev)
866{
867 return FIRMWARE_RT2571;
868}
869
f160ebcb 870static u16 rt73usb_get_firmware_crc(const void *data, const size_t len)
a7f3a06c
ID		 871{
872 u16 crc;
873
874 /*
875 * Use the crc itu-t algorithm.
876 * The last 2 bytes in the firmware array are the crc checksum itself,
877 * this means that we should never pass those 2 bytes to the crc
878 * algorithm.
879 */
880 crc = crc_itu_t(0, data, len - 2);
881 crc = crc_itu_t_byte(crc, 0);
882 crc = crc_itu_t_byte(crc, 0);
883
884 return crc;
885}
886
f160ebcb 887static int rt73usb_load_firmware(struct rt2x00_dev *rt2x00dev, const void *data,
95ea3627
ID		 888 const size_t len)
889{
890 unsigned int i;
891 int status;
892 u32 reg;
f160ebcb 893 const char *ptr = data;
95ea3627
ID		 894 char *cache;
895 int buflen;
95ea3627
ID		 896
897 /*
898 * Wait for stable hardware.
899 */
900 for (i = 0; i < 100; i++) {
901 rt73usb_register_read(rt2x00dev, MAC_CSR0, &reg);
902 if (reg)
903 break;
904 msleep(1);
905 }
906
907 if (!reg) {
908 ERROR(rt2x00dev, "Unstable hardware.\n");
909 return -EBUSY;
910 }
911
912 /*
913 * Write firmware to device.
914 * We setup a seperate cache for this action,
915 * since we are going to write larger chunks of data
916 * then normally used cache size.
917 */
918 cache = kmalloc(CSR_CACHE_SIZE_FIRMWARE, GFP_KERNEL);
919 if (!cache) {
920 ERROR(rt2x00dev, "Failed to allocate firmware cache.\n");
921 return -ENOMEM;
922 }
923
924 for (i = 0; i < len; i += CSR_CACHE_SIZE_FIRMWARE) {
925 buflen = min_t(int, len - i, CSR_CACHE_SIZE_FIRMWARE);
95ea3627
ID		 926
927 memcpy(cache, ptr, buflen);
928
929 rt2x00usb_vendor_request(rt2x00dev, USB_MULTI_WRITE,
930 USB_VENDOR_REQUEST_OUT,
3b640f21 931 FIRMWARE_IMAGE_BASE + i, 0,
bd394a74
ID		 932 cache, buflen,
933 REGISTER_TIMEOUT32(buflen));
95ea3627
ID		 934
935 ptr += buflen;
936 }
937
938 kfree(cache);
939
940 /*
941 * Send firmware request to device to load firmware,
942 * we need to specify a long timeout time.
943 */
944 status = rt2x00usb_vendor_request_sw(rt2x00dev, USB_DEVICE_MODE,
3b640f21 945 0, USB_MODE_FIRMWARE,
95ea3627
ID		 946 REGISTER_TIMEOUT_FIRMWARE);
947 if (status < 0) {
948 ERROR(rt2x00dev, "Failed to write Firmware to device.\n");
949 return status;
950 }
951
95ea3627
ID		 952 return 0;
953}
954
a7f3a06c
ID		 955/*
956 * Initialization functions.
957 */
95ea3627
ID		 958static int rt73usb_init_registers(struct rt2x00_dev *rt2x00dev)
959{
960 u32 reg;
961
962 rt73usb_register_read(rt2x00dev, TXRX_CSR0, &reg);
963 rt2x00_set_field32(&reg, TXRX_CSR0_AUTO_TX_SEQ, 1);
964 rt2x00_set_field32(&reg, TXRX_CSR0_DISABLE_RX, 0);
965 rt2x00_set_field32(&reg, TXRX_CSR0_TX_WITHOUT_WAITING, 0);
966 rt73usb_register_write(rt2x00dev, TXRX_CSR0, reg);
967
968 rt73usb_register_read(rt2x00dev, TXRX_CSR1, &reg);
969 rt2x00_set_field32(&reg, TXRX_CSR1_BBP_ID0, 47); /* CCK Signal */
970 rt2x00_set_field32(&reg, TXRX_CSR1_BBP_ID0_VALID, 1);
971 rt2x00_set_field32(&reg, TXRX_CSR1_BBP_ID1, 30); /* Rssi */
972 rt2x00_set_field32(&reg, TXRX_CSR1_BBP_ID1_VALID, 1);
973 rt2x00_set_field32(&reg, TXRX_CSR1_BBP_ID2, 42); /* OFDM Rate */
974 rt2x00_set_field32(&reg, TXRX_CSR1_BBP_ID2_VALID, 1);
975 rt2x00_set_field32(&reg, TXRX_CSR1_BBP_ID3, 30); /* Rssi */
976 rt2x00_set_field32(&reg, TXRX_CSR1_BBP_ID3_VALID, 1);
977 rt73usb_register_write(rt2x00dev, TXRX_CSR1, reg);
978
979 /*
980 * CCK TXD BBP registers
981 */
982 rt73usb_register_read(rt2x00dev, TXRX_CSR2, &reg);
983 rt2x00_set_field32(&reg, TXRX_CSR2_BBP_ID0, 13);
984 rt2x00_set_field32(&reg, TXRX_CSR2_BBP_ID0_VALID, 1);
985 rt2x00_set_field32(&reg, TXRX_CSR2_BBP_ID1, 12);
986 rt2x00_set_field32(&reg, TXRX_CSR2_BBP_ID1_VALID, 1);
987 rt2x00_set_field32(&reg, TXRX_CSR2_BBP_ID2, 11);
988 rt2x00_set_field32(&reg, TXRX_CSR2_BBP_ID2_VALID, 1);
989 rt2x00_set_field32(&reg, TXRX_CSR2_BBP_ID3, 10);
990 rt2x00_set_field32(&reg, TXRX_CSR2_BBP_ID3_VALID, 1);
991 rt73usb_register_write(rt2x00dev, TXRX_CSR2, reg);
992
993 /*
994 * OFDM TXD BBP registers
995 */
996 rt73usb_register_read(rt2x00dev, TXRX_CSR3, &reg);
997 rt2x00_set_field32(&reg, TXRX_CSR3_BBP_ID0, 7);
998 rt2x00_set_field32(&reg, TXRX_CSR3_BBP_ID0_VALID, 1);
999 rt2x00_set_field32(&reg, TXRX_CSR3_BBP_ID1, 6);
1000 rt2x00_set_field32(&reg, TXRX_CSR3_BBP_ID1_VALID, 1);
1001 rt2x00_set_field32(&reg, TXRX_CSR3_BBP_ID2, 5);
1002 rt2x00_set_field32(&reg, TXRX_CSR3_BBP_ID2_VALID, 1);
1003 rt73usb_register_write(rt2x00dev, TXRX_CSR3, reg);
1004
1005 rt73usb_register_read(rt2x00dev, TXRX_CSR7, &reg);
1006 rt2x00_set_field32(&reg, TXRX_CSR7_ACK_CTS_6MBS, 59);
1007 rt2x00_set_field32(&reg, TXRX_CSR7_ACK_CTS_9MBS, 53);
1008 rt2x00_set_field32(&reg, TXRX_CSR7_ACK_CTS_12MBS, 49);
1009 rt2x00_set_field32(&reg, TXRX_CSR7_ACK_CTS_18MBS, 46);
1010 rt73usb_register_write(rt2x00dev, TXRX_CSR7, reg);
1011
1012 rt73usb_register_read(rt2x00dev, TXRX_CSR8, &reg);
1013 rt2x00_set_field32(&reg, TXRX_CSR8_ACK_CTS_24MBS, 44);
1014 rt2x00_set_field32(&reg, TXRX_CSR8_ACK_CTS_36MBS, 42);
1015 rt2x00_set_field32(&reg, TXRX_CSR8_ACK_CTS_48MBS, 42);
1016 rt2x00_set_field32(&reg, TXRX_CSR8_ACK_CTS_54MBS, 42);
1017 rt73usb_register_write(rt2x00dev, TXRX_CSR8, reg);
1018
1f909162
ID		 1019 rt73usb_register_read(rt2x00dev, TXRX_CSR9, &reg);
1020 rt2x00_set_field32(&reg, TXRX_CSR9_BEACON_INTERVAL, 0);
1021 rt2x00_set_field32(&reg, TXRX_CSR9_TSF_TICKING, 0);
1022 rt2x00_set_field32(&reg, TXRX_CSR9_TSF_SYNC, 0);
1023 rt2x00_set_field32(&reg, TXRX_CSR9_TBTT_ENABLE, 0);
1024 rt2x00_set_field32(&reg, TXRX_CSR9_BEACON_GEN, 0);
1025 rt2x00_set_field32(&reg, TXRX_CSR9_TIMESTAMP_COMPENSATE, 0);
1026 rt73usb_register_write(rt2x00dev, TXRX_CSR9, reg);
1027
95ea3627
ID		 1028 rt73usb_register_write(rt2x00dev, TXRX_CSR15, 0x0000000f);
1029
1030 rt73usb_register_read(rt2x00dev, MAC_CSR6, &reg);
1031 rt2x00_set_field32(&reg, MAC_CSR6_MAX_FRAME_UNIT, 0xfff);
1032 rt73usb_register_write(rt2x00dev, MAC_CSR6, reg);
1033
1034 rt73usb_register_write(rt2x00dev, MAC_CSR10, 0x00000718);
1035
1036 if (rt2x00dev->ops->lib->set_device_state(rt2x00dev, STATE_AWAKE))
1037 return -EBUSY;
1038
1039 rt73usb_register_write(rt2x00dev, MAC_CSR13, 0x00007f00);
1040
1041 /*
1042 * Invalidate all Shared Keys (SEC_CSR0),
1043 * and clear the Shared key Cipher algorithms (SEC_CSR1 & SEC_CSR5)
1044 */
1045 rt73usb_register_write(rt2x00dev, SEC_CSR0, 0x00000000);
1046 rt73usb_register_write(rt2x00dev, SEC_CSR1, 0x00000000);
1047 rt73usb_register_write(rt2x00dev, SEC_CSR5, 0x00000000);
1048
1049 reg = 0x000023b0;
1050 if (rt2x00_rf(&rt2x00dev->chip, RF5225) ||
1051 rt2x00_rf(&rt2x00dev->chip, RF2527))
1052 rt2x00_set_field32(&reg, PHY_CSR1_RF_RPI, 1);
1053 rt73usb_register_write(rt2x00dev, PHY_CSR1, reg);
1054
1055 rt73usb_register_write(rt2x00dev, PHY_CSR5, 0x00040a06);
1056 rt73usb_register_write(rt2x00dev, PHY_CSR6, 0x00080606);
1057 rt73usb_register_write(rt2x00dev, PHY_CSR7, 0x00000408);
1058
1059 rt73usb_register_read(rt2x00dev, AC_TXOP_CSR0, &reg);
1060 rt2x00_set_field32(&reg, AC_TXOP_CSR0_AC0_TX_OP, 0);
1061 rt2x00_set_field32(&reg, AC_TXOP_CSR0_AC1_TX_OP, 0);
1062 rt73usb_register_write(rt2x00dev, AC_TXOP_CSR0, reg);
1063
1064 rt73usb_register_read(rt2x00dev, AC_TXOP_CSR1, &reg);
1065 rt2x00_set_field32(&reg, AC_TXOP_CSR1_AC2_TX_OP, 192);
1066 rt2x00_set_field32(&reg, AC_TXOP_CSR1_AC3_TX_OP, 48);
1067 rt73usb_register_write(rt2x00dev, AC_TXOP_CSR1, reg);
1068
1069 rt73usb_register_read(rt2x00dev, MAC_CSR9, &reg);
1070 rt2x00_set_field32(&reg, MAC_CSR9_CW_SELECT, 0);
1071 rt73usb_register_write(rt2x00dev, MAC_CSR9, reg);
1072
6bb40dd1
ID		 1073 /*
1074 * Clear all beacons
1075 * For the Beacon base registers we only need to clear
1076 * the first byte since that byte contains the VALID and OWNER
1077 * bits which (when set to 0) will invalidate the entire beacon.
1078 */
1079 rt73usb_register_write(rt2x00dev, HW_BEACON_BASE0, 0);
1080 rt73usb_register_write(rt2x00dev, HW_BEACON_BASE1, 0);
1081 rt73usb_register_write(rt2x00dev, HW_BEACON_BASE2, 0);
1082 rt73usb_register_write(rt2x00dev, HW_BEACON_BASE3, 0);
1083
95ea3627
ID		 1084 /*
1085 * We must clear the error counters.
1086 * These registers are cleared on read,
1087 * so we may pass a useless variable to store the value.
1088 */
1089 rt73usb_register_read(rt2x00dev, STA_CSR0, &reg);
1090 rt73usb_register_read(rt2x00dev, STA_CSR1, &reg);
1091 rt73usb_register_read(rt2x00dev, STA_CSR2, &reg);
1092
1093 /*
1094 * Reset MAC and BBP registers.
1095 */
1096 rt73usb_register_read(rt2x00dev, MAC_CSR1, &reg);
1097 rt2x00_set_field32(&reg, MAC_CSR1_SOFT_RESET, 1);
1098 rt2x00_set_field32(&reg, MAC_CSR1_BBP_RESET, 1);
1099 rt73usb_register_write(rt2x00dev, MAC_CSR1, reg);
1100
1101 rt73usb_register_read(rt2x00dev, MAC_CSR1, &reg);
1102 rt2x00_set_field32(&reg, MAC_CSR1_SOFT_RESET, 0);
1103 rt2x00_set_field32(&reg, MAC_CSR1_BBP_RESET, 0);
1104 rt73usb_register_write(rt2x00dev, MAC_CSR1, reg);
1105
1106 rt73usb_register_read(rt2x00dev, MAC_CSR1, &reg);
1107 rt2x00_set_field32(&reg, MAC_CSR1_HOST_READY, 1);
1108 rt73usb_register_write(rt2x00dev, MAC_CSR1, reg);
1109
1110 return 0;
1111}
1112
2b08da3f 1113static int rt73usb_wait_bbp_ready(struct rt2x00_dev *rt2x00dev)
95ea3627
ID		 1114{
1115 unsigned int i;
95ea3627
ID		 1116 u8 value;
1117
1118 for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
1119 rt73usb_bbp_read(rt2x00dev, 0, &value);
1120 if ((value != 0xff) && (value != 0x00))
2b08da3f 1121 return 0;
95ea3627
ID		 1122 udelay(REGISTER_BUSY_DELAY);
1123 }
1124
1125 ERROR(rt2x00dev, "BBP register access failed, aborting.\n");
1126 return -EACCES;
2b08da3f
ID		 1127}
1128
1129static int rt73usb_init_bbp(struct rt2x00_dev *rt2x00dev)
1130{
1131 unsigned int i;
1132 u16 eeprom;
1133 u8 reg_id;
1134 u8 value;
1135
1136 if (unlikely(rt73usb_wait_bbp_ready(rt2x00dev)))
1137 return -EACCES;
95ea3627 1138
95ea3627
ID		 1139 rt73usb_bbp_write(rt2x00dev, 3, 0x80);
1140 rt73usb_bbp_write(rt2x00dev, 15, 0x30);
1141 rt73usb_bbp_write(rt2x00dev, 21, 0xc8);
1142 rt73usb_bbp_write(rt2x00dev, 22, 0x38);
1143 rt73usb_bbp_write(rt2x00dev, 23, 0x06);
1144 rt73usb_bbp_write(rt2x00dev, 24, 0xfe);
1145 rt73usb_bbp_write(rt2x00dev, 25, 0x0a);
1146 rt73usb_bbp_write(rt2x00dev, 26, 0x0d);
1147 rt73usb_bbp_write(rt2x00dev, 32, 0x0b);
1148 rt73usb_bbp_write(rt2x00dev, 34, 0x12);
1149 rt73usb_bbp_write(rt2x00dev, 37, 0x07);
1150 rt73usb_bbp_write(rt2x00dev, 39, 0xf8);
1151 rt73usb_bbp_write(rt2x00dev, 41, 0x60);
1152 rt73usb_bbp_write(rt2x00dev, 53, 0x10);
1153 rt73usb_bbp_write(rt2x00dev, 54, 0x18);
1154 rt73usb_bbp_write(rt2x00dev, 60, 0x10);
1155 rt73usb_bbp_write(rt2x00dev, 61, 0x04);
1156 rt73usb_bbp_write(rt2x00dev, 62, 0x04);
1157 rt73usb_bbp_write(rt2x00dev, 75, 0xfe);
1158 rt73usb_bbp_write(rt2x00dev, 86, 0xfe);
1159 rt73usb_bbp_write(rt2x00dev, 88, 0xfe);
1160 rt73usb_bbp_write(rt2x00dev, 90, 0x0f);
1161 rt73usb_bbp_write(rt2x00dev, 99, 0x00);
1162 rt73usb_bbp_write(rt2x00dev, 102, 0x16);
1163 rt73usb_bbp_write(rt2x00dev, 107, 0x04);
1164
95ea3627
ID		 1165 for (i = 0; i < EEPROM_BBP_SIZE; i++) {
1166 rt2x00_eeprom_read(rt2x00dev, EEPROM_BBP_START + i, &eeprom);
1167
1168 if (eeprom != 0xffff && eeprom != 0x0000) {
1169 reg_id = rt2x00_get_field16(eeprom, EEPROM_BBP_REG_ID);
1170 value = rt2x00_get_field16(eeprom, EEPROM_BBP_VALUE);
95ea3627
ID		 1171 rt73usb_bbp_write(rt2x00dev, reg_id, value);
1172 }
1173 }
95ea3627
ID		 1174
1175 return 0;
1176}
1177
1178/*
1179 * Device state switch handlers.
1180 */
1181static void rt73usb_toggle_rx(struct rt2x00_dev *rt2x00dev,
1182 enum dev_state state)
1183{
1184 u32 reg;
1185
1186 rt73usb_register_read(rt2x00dev, TXRX_CSR0, &reg);
1187 rt2x00_set_field32(&reg, TXRX_CSR0_DISABLE_RX,
2b08da3f
ID		 1188 (state == STATE_RADIO_RX_OFF) ||
1189 (state == STATE_RADIO_RX_OFF_LINK));
95ea3627
ID		 1190 rt73usb_register_write(rt2x00dev, TXRX_CSR0, reg);
1191}
1192
1193static int rt73usb_enable_radio(struct rt2x00_dev *rt2x00dev)
1194{
1195 /*
1196 * Initialize all registers.
1197 */
2b08da3f
ID		 1198 if (unlikely(rt73usb_init_registers(rt2x00dev) ||
1199 rt73usb_init_bbp(rt2x00dev)))
95ea3627 1200 return -EIO;
95ea3627 1201
95ea3627
ID		 1202 return 0;
1203}
1204
1205static void rt73usb_disable_radio(struct rt2x00_dev *rt2x00dev)
1206{
95ea3627
ID		 1207 rt73usb_register_write(rt2x00dev, MAC_CSR10, 0x00001818);
1208
1209 /*
1210 * Disable synchronisation.
1211 */
1212 rt73usb_register_write(rt2x00dev, TXRX_CSR9, 0);
1213
1214 rt2x00usb_disable_radio(rt2x00dev);
1215}
1216
1217static int rt73usb_set_state(struct rt2x00_dev *rt2x00dev, enum dev_state state)
1218{
1219 u32 reg;
1220 unsigned int i;
1221 char put_to_sleep;
95ea3627
ID		 1222
1223 put_to_sleep = (state != STATE_AWAKE);
1224
1225 rt73usb_register_read(rt2x00dev, MAC_CSR12, &reg);
1226 rt2x00_set_field32(&reg, MAC_CSR12_FORCE_WAKEUP, !put_to_sleep);
1227 rt2x00_set_field32(&reg, MAC_CSR12_PUT_TO_SLEEP, put_to_sleep);
1228 rt73usb_register_write(rt2x00dev, MAC_CSR12, reg);
1229
1230 /*
1231 * Device is not guaranteed to be in the requested state yet.
1232 * We must wait until the register indicates that the
1233 * device has entered the correct state.
1234 */
1235 for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
1236 rt73usb_register_read(rt2x00dev, MAC_CSR12, &reg);
2b08da3f
ID		 1237 state = rt2x00_get_field32(reg, MAC_CSR12_BBP_CURRENT_STATE);
1238 if (state == !put_to_sleep)
95ea3627
ID		 1239 return 0;
1240 msleep(10);
1241 }
1242
95ea3627
ID		 1243 return -EBUSY;
1244}
1245
1246static int rt73usb_set_device_state(struct rt2x00_dev *rt2x00dev,
1247 enum dev_state state)
1248{
1249 int retval = 0;
1250
1251 switch (state) {
1252 case STATE_RADIO_ON:
1253 retval = rt73usb_enable_radio(rt2x00dev);
1254 break;
1255 case STATE_RADIO_OFF:
1256 rt73usb_disable_radio(rt2x00dev);
1257 break;
1258 case STATE_RADIO_RX_ON:
61667d8d 1259 case STATE_RADIO_RX_ON_LINK:
95ea3627 1260 case STATE_RADIO_RX_OFF:
61667d8d 1261 case STATE_RADIO_RX_OFF_LINK:
2b08da3f
ID		 1262 rt73usb_toggle_rx(rt2x00dev, state);
1263 break;
1264 case STATE_RADIO_IRQ_ON:
1265 case STATE_RADIO_IRQ_OFF:
1266 /* No support, but no error either */
95ea3627
ID		 1267 break;
1268 case STATE_DEEP_SLEEP:
1269 case STATE_SLEEP:
1270 case STATE_STANDBY:
1271 case STATE_AWAKE:
1272 retval = rt73usb_set_state(rt2x00dev, state);
1273 break;
1274 default:
1275 retval = -ENOTSUPP;
1276 break;
1277 }
1278
2b08da3f
ID		 1279 if (unlikely(retval))
1280 ERROR(rt2x00dev, "Device failed to enter state %d (%d).\n",
1281 state, retval);
1282
95ea3627
ID		 1283 return retval;
1284}
1285
1286/*
1287 * TX descriptor initialization
1288 */
1289static void rt73usb_write_tx_desc(struct rt2x00_dev *rt2x00dev,
dd3193e1 1290 struct sk_buff *skb,
61486e0f 1291 struct txentry_desc *txdesc)
95ea3627 1292{
181d6902 1293 struct skb_frame_desc *skbdesc = get_skb_frame_desc(skb);
dd3193e1 1294 __le32 *txd = skbdesc->desc;
95ea3627
ID		 1295 u32 word;
1296
1297 /*
1298 * Start writing the descriptor words.
1299 */
1300 rt2x00_desc_read(txd, 1, &word);
181d6902
ID		 1301 rt2x00_set_field32(&word, TXD_W1_HOST_Q_ID, txdesc->queue);
1302 rt2x00_set_field32(&word, TXD_W1_AIFSN, txdesc->aifs);
1303 rt2x00_set_field32(&word, TXD_W1_CWMIN, txdesc->cw_min);
1304 rt2x00_set_field32(&word, TXD_W1_CWMAX, txdesc->cw_max);
95ea3627
ID		 1305 rt2x00_set_field32(&word, TXD_W1_IV_OFFSET, IEEE80211_HEADER);
1306 rt2x00_set_field32(&word, TXD_W1_HW_SEQUENCE, 1);
1307 rt2x00_desc_write(txd, 1, word);
1308
1309 rt2x00_desc_read(txd, 2, &word);
181d6902
ID		 1310 rt2x00_set_field32(&word, TXD_W2_PLCP_SIGNAL, txdesc->signal);
1311 rt2x00_set_field32(&word, TXD_W2_PLCP_SERVICE, txdesc->service);
1312 rt2x00_set_field32(&word, TXD_W2_PLCP_LENGTH_LOW, txdesc->length_low);
1313 rt2x00_set_field32(&word, TXD_W2_PLCP_LENGTH_HIGH, txdesc->length_high);
95ea3627
ID		 1314 rt2x00_desc_write(txd, 2, word);
1315
1316 rt2x00_desc_read(txd, 5, &word);
1317 rt2x00_set_field32(&word, TXD_W5_TX_POWER,
ac1aa7e4 1318 TXPOWER_TO_DEV(rt2x00dev->tx_power));
95ea3627
ID		 1319 rt2x00_set_field32(&word, TXD_W5_WAITING_DMA_DONE_INT, 1);
1320 rt2x00_desc_write(txd, 5, word);
1321
1322 rt2x00_desc_read(txd, 0, &word);
1323 rt2x00_set_field32(&word, TXD_W0_BURST,
181d6902 1324 test_bit(ENTRY_TXD_BURST, &txdesc->flags));
95ea3627
ID		 1325 rt2x00_set_field32(&word, TXD_W0_VALID, 1);
1326 rt2x00_set_field32(&word, TXD_W0_MORE_FRAG,
181d6902 1327 test_bit(ENTRY_TXD_MORE_FRAG, &txdesc->flags));
95ea3627 1328 rt2x00_set_field32(&word, TXD_W0_ACK,
181d6902 1329 test_bit(ENTRY_TXD_ACK, &txdesc->flags));
95ea3627 1330 rt2x00_set_field32(&word, TXD_W0_TIMESTAMP,
181d6902 1331 test_bit(ENTRY_TXD_REQ_TIMESTAMP, &txdesc->flags));
95ea3627 1332 rt2x00_set_field32(&word, TXD_W0_OFDM,
181d6902
ID		 1333 test_bit(ENTRY_TXD_OFDM_RATE, &txdesc->flags));
1334 rt2x00_set_field32(&word, TXD_W0_IFS, txdesc->ifs);
95ea3627 1335 rt2x00_set_field32(&word, TXD_W0_RETRY_MODE,
61486e0f 1336 test_bit(ENTRY_TXD_RETRY_MODE, &txdesc->flags));
95ea3627 1337 rt2x00_set_field32(&word, TXD_W0_TKIP_MIC, 0);
d56d453a
GW		 1338 rt2x00_set_field32(&word, TXD_W0_DATABYTE_COUNT,
1339 skb->len - skbdesc->desc_len);
95ea3627 1340 rt2x00_set_field32(&word, TXD_W0_BURST2,
181d6902 1341 test_bit(ENTRY_TXD_BURST, &txdesc->flags));
95ea3627
ID		 1342 rt2x00_set_field32(&word, TXD_W0_CIPHER_ALG, CIPHER_NONE);
1343 rt2x00_desc_write(txd, 0, word);
1344}
1345
bd88a781
ID		 1346/*
1347 * TX data initialization
1348 */
1349static void rt73usb_write_beacon(struct queue_entry *entry)
1350{
1351 struct rt2x00_dev *rt2x00dev = entry->queue->rt2x00dev;
1352 struct skb_frame_desc *skbdesc = get_skb_frame_desc(entry->skb);
1353 unsigned int beacon_base;
1354 u32 reg;
1355
1356 /*
1357 * Add the descriptor in front of the skb.
1358 */
1359 skb_push(entry->skb, entry->queue->desc_size);
1360 memcpy(entry->skb->data, skbdesc->desc, skbdesc->desc_len);
1361 skbdesc->desc = entry->skb->data;
1362
1363 /*
1364 * Disable beaconing while we are reloading the beacon data,
1365 * otherwise we might be sending out invalid data.
1366 */
1367 rt73usb_register_read(rt2x00dev, TXRX_CSR9, &reg);
1368 rt2x00_set_field32(&reg, TXRX_CSR9_TSF_TICKING, 0);
1369 rt2x00_set_field32(&reg, TXRX_CSR9_TBTT_ENABLE, 0);
1370 rt2x00_set_field32(&reg, TXRX_CSR9_BEACON_GEN, 0);
1371 rt73usb_register_write(rt2x00dev, TXRX_CSR9, reg);
1372
1373 /*
1374 * Write entire beacon with descriptor to register.
1375 */
1376 beacon_base = HW_BEACON_OFFSET(entry->entry_idx);
1377 rt2x00usb_vendor_request(rt2x00dev, USB_MULTI_WRITE,
1378 USB_VENDOR_REQUEST_OUT, beacon_base, 0,
1379 entry->skb->data, entry->skb->len,
1380 REGISTER_TIMEOUT32(entry->skb->len));
1381
1382 /*
1383 * Clean up the beacon skb.
1384 */
1385 dev_kfree_skb(entry->skb);
1386 entry->skb = NULL;
1387}
1388
dd9fa2d2 1389static int rt73usb_get_tx_data_len(struct rt2x00_dev *rt2x00dev,
b242e891 1390 struct sk_buff *skb)
dd9fa2d2
ID		 1391{
1392 int length;
1393
1394 /*
1395 * The length _must_ be a multiple of 4,
1396 * but it must _not_ be a multiple of the USB packet size.
1397 */
1398 length = roundup(skb->len, 4);
b242e891 1399 length += (4 * !(length % rt2x00dev->usb_maxpacket));
dd9fa2d2
ID		 1400
1401 return length;
1402}
1403
95ea3627 1404static void rt73usb_kick_tx_queue(struct rt2x00_dev *rt2x00dev,
e58c6aca 1405 const enum data_queue_qid queue)
95ea3627
ID		 1406{
1407 u32 reg;
1408
f019d514
ID		 1409 if (queue != QID_BEACON) {
1410 rt2x00usb_kick_tx_queue(rt2x00dev, queue);
95ea3627 1411 return;
f019d514 1412 }
95ea3627
ID		 1413
1414 /*
1415 * For Wi-Fi faily generated beacons between participating stations.
1416 * Set TBTT phase adaptive adjustment step to 8us (default 16us)
1417 */
1418 rt73usb_register_write(rt2x00dev, TXRX_CSR10, 0x00001008);
1419
1420 rt73usb_register_read(rt2x00dev, TXRX_CSR9, &reg);
1421 if (!rt2x00_get_field32(reg, TXRX_CSR9_BEACON_GEN)) {
8af244cc
ID		 1422 rt2x00_set_field32(&reg, TXRX_CSR9_TSF_TICKING, 1);
1423 rt2x00_set_field32(&reg, TXRX_CSR9_TBTT_ENABLE, 1);
95ea3627
ID		 1424 rt2x00_set_field32(&reg, TXRX_CSR9_BEACON_GEN, 1);
1425 rt73usb_register_write(rt2x00dev, TXRX_CSR9, reg);
1426 }
1427}
1428
1429/*
1430 * RX control handlers
1431 */
1432static int rt73usb_agc_to_rssi(struct rt2x00_dev *rt2x00dev, int rxd_w1)
1433{
1434 u16 eeprom;
1435 u8 offset;
1436 u8 lna;
1437
1438 lna = rt2x00_get_field32(rxd_w1, RXD_W1_RSSI_LNA);
1439 switch (lna) {
1440 case 3:
1441 offset = 90;
1442 break;
1443 case 2:
1444 offset = 74;
1445 break;
1446 case 1:
1447 offset = 64;
1448 break;
1449 default:
1450 return 0;
1451 }
1452
8318d78a 1453 if (rt2x00dev->rx_status.band == IEEE80211_BAND_5GHZ) {
95ea3627
ID		 1454 if (test_bit(CONFIG_EXTERNAL_LNA_A, &rt2x00dev->flags)) {
1455 if (lna == 3 || lna == 2)
1456 offset += 10;
1457 } else {
1458 if (lna == 3)
1459 offset += 6;
1460 else if (lna == 2)
1461 offset += 8;
1462 }
1463
1464 rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_OFFSET_A, &eeprom);
1465 offset -= rt2x00_get_field16(eeprom, EEPROM_RSSI_OFFSET_A_1);
1466 } else {
1467 if (test_bit(CONFIG_EXTERNAL_LNA_BG, &rt2x00dev->flags))
1468 offset += 14;
1469
1470 rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_OFFSET_BG, &eeprom);
1471 offset -= rt2x00_get_field16(eeprom, EEPROM_RSSI_OFFSET_BG_1);
1472 }
1473
1474 return rt2x00_get_field32(rxd_w1, RXD_W1_RSSI_AGC) * 2 - offset;
1475}
1476
181d6902
ID		 1477static void rt73usb_fill_rxdone(struct queue_entry *entry,
1478 struct rxdone_entry_desc *rxdesc)
95ea3627 1479{
181d6902 1480 struct skb_frame_desc *skbdesc = get_skb_frame_desc(entry->skb);
4bd7c452 1481 __le32 *rxd = (__le32 *)entry->skb->data;
95ea3627
ID		 1482 u32 word0;
1483 u32 word1;
1484
f855c10b 1485 /*
a26cbc65
GW		 1486 * Copy descriptor to the skbdesc->desc buffer, making it safe from moving of
1487 * frame data in rt2x00usb.
f855c10b 1488 */
a26cbc65 1489 memcpy(skbdesc->desc, rxd, skbdesc->desc_len);
70a96109 1490 rxd = (__le32 *)skbdesc->desc;
f855c10b
ID		 1491
1492 /*
70a96109 1493 * It is now safe to read the descriptor on all architectures.
f855c10b 1494 */
95ea3627
ID		 1495 rt2x00_desc_read(rxd, 0, &word0);
1496 rt2x00_desc_read(rxd, 1, &word1);
1497
4150c572 1498 if (rt2x00_get_field32(word0, RXD_W0_CRC_ERROR))
181d6902 1499 rxdesc->flags |= RX_FLAG_FAILED_FCS_CRC;
95ea3627
ID		 1500
1501 /*
1502 * Obtain the status about this packet.
89993890
ID		 1503 * When frame was received with an OFDM bitrate,
1504 * the signal is the PLCP value. If it was received with
1505 * a CCK bitrate the signal is the rate in 100kbit/s.
95ea3627 1506 */
181d6902
ID		 1507 rxdesc->signal = rt2x00_get_field32(word1, RXD_W1_SIGNAL);
1508 rxdesc->rssi = rt73usb_agc_to_rssi(entry->queue->rt2x00dev, word1);
181d6902 1509 rxdesc->size = rt2x00_get_field32(word0, RXD_W0_DATABYTE_COUNT);
19d30e02 1510
19d30e02
ID		 1511 if (rt2x00_get_field32(word0, RXD_W0_OFDM))
1512 rxdesc->dev_flags |= RXDONE_SIGNAL_PLCP;
1513 if (rt2x00_get_field32(word0, RXD_W0_MY_BSS))
1514 rxdesc->dev_flags |= RXDONE_MY_BSS;
181d6902 1515
2ae23854 1516 /*
70a96109 1517 * Set skb pointers, and update frame information.
2ae23854 1518 */
70a96109 1519 skb_pull(entry->skb, entry->queue->desc_size);
2ae23854 1520 skb_trim(entry->skb, rxdesc->size);
95ea3627
ID		 1521}
1522
1523/*
1524 * Device probe functions.
1525 */
1526static int rt73usb_validate_eeprom(struct rt2x00_dev *rt2x00dev)
1527{
1528 u16 word;
1529 u8 *mac;
1530 s8 value;
1531
1532 rt2x00usb_eeprom_read(rt2x00dev, rt2x00dev->eeprom, EEPROM_SIZE);
1533
1534 /*
1535 * Start validation of the data that has been read.
1536 */
1537 mac = rt2x00_eeprom_addr(rt2x00dev, EEPROM_MAC_ADDR_0);
1538 if (!is_valid_ether_addr(mac)) {
0795af57
JP		 1539 DECLARE_MAC_BUF(macbuf);
1540
95ea3627 1541 random_ether_addr(mac);
0795af57 1542 EEPROM(rt2x00dev, "MAC: %s\n", print_mac(macbuf, mac));
95ea3627
ID		 1543 }
1544
1545 rt2x00_eeprom_read(rt2x00dev, EEPROM_ANTENNA, &word);
1546 if (word == 0xffff) {
1547 rt2x00_set_field16(&word, EEPROM_ANTENNA_NUM, 2);
362f3b6b
ID		 1548 rt2x00_set_field16(&word, EEPROM_ANTENNA_TX_DEFAULT,
1549 ANTENNA_B);
1550 rt2x00_set_field16(&word, EEPROM_ANTENNA_RX_DEFAULT,
1551 ANTENNA_B);
95ea3627
ID		 1552 rt2x00_set_field16(&word, EEPROM_ANTENNA_FRAME_TYPE, 0);
1553 rt2x00_set_field16(&word, EEPROM_ANTENNA_DYN_TXAGC, 0);
1554 rt2x00_set_field16(&word, EEPROM_ANTENNA_HARDWARE_RADIO, 0);
1555 rt2x00_set_field16(&word, EEPROM_ANTENNA_RF_TYPE, RF5226);
1556 rt2x00_eeprom_write(rt2x00dev, EEPROM_ANTENNA, word);
1557 EEPROM(rt2x00dev, "Antenna: 0x%04x\n", word);
1558 }
1559
1560 rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC, &word);
1561 if (word == 0xffff) {
1562 rt2x00_set_field16(&word, EEPROM_NIC_EXTERNAL_LNA, 0);
1563 rt2x00_eeprom_write(rt2x00dev, EEPROM_NIC, word);
1564 EEPROM(rt2x00dev, "NIC: 0x%04x\n", word);
1565 }
1566
1567 rt2x00_eeprom_read(rt2x00dev, EEPROM_LED, &word);
1568 if (word == 0xffff) {
1569 rt2x00_set_field16(&word, EEPROM_LED_POLARITY_RDY_G, 0);
1570 rt2x00_set_field16(&word, EEPROM_LED_POLARITY_RDY_A, 0);
1571 rt2x00_set_field16(&word, EEPROM_LED_POLARITY_ACT, 0);
1572 rt2x00_set_field16(&word, EEPROM_LED_POLARITY_GPIO_0, 0);
1573 rt2x00_set_field16(&word, EEPROM_LED_POLARITY_GPIO_1, 0);
1574 rt2x00_set_field16(&word, EEPROM_LED_POLARITY_GPIO_2, 0);
1575 rt2x00_set_field16(&word, EEPROM_LED_POLARITY_GPIO_3, 0);
1576 rt2x00_set_field16(&word, EEPROM_LED_POLARITY_GPIO_4, 0);
1577 rt2x00_set_field16(&word, EEPROM_LED_LED_MODE,
1578 LED_MODE_DEFAULT);
1579 rt2x00_eeprom_write(rt2x00dev, EEPROM_LED, word);
1580 EEPROM(rt2x00dev, "Led: 0x%04x\n", word);
1581 }
1582
1583 rt2x00_eeprom_read(rt2x00dev, EEPROM_FREQ, &word);
1584 if (word == 0xffff) {
1585 rt2x00_set_field16(&word, EEPROM_FREQ_OFFSET, 0);
1586 rt2x00_set_field16(&word, EEPROM_FREQ_SEQ, 0);
1587 rt2x00_eeprom_write(rt2x00dev, EEPROM_FREQ, word);
1588 EEPROM(rt2x00dev, "Freq: 0x%04x\n", word);
1589 }
1590
1591 rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_OFFSET_BG, &word);
1592 if (word == 0xffff) {
1593 rt2x00_set_field16(&word, EEPROM_RSSI_OFFSET_BG_1, 0);
1594 rt2x00_set_field16(&word, EEPROM_RSSI_OFFSET_BG_2, 0);
1595 rt2x00_eeprom_write(rt2x00dev, EEPROM_RSSI_OFFSET_BG, word);
1596 EEPROM(rt2x00dev, "RSSI OFFSET BG: 0x%04x\n", word);
1597 } else {
1598 value = rt2x00_get_field16(word, EEPROM_RSSI_OFFSET_BG_1);
1599 if (value < -10 || value > 10)
1600 rt2x00_set_field16(&word, EEPROM_RSSI_OFFSET_BG_1, 0);
1601 value = rt2x00_get_field16(word, EEPROM_RSSI_OFFSET_BG_2);
1602 if (value < -10 || value > 10)
1603 rt2x00_set_field16(&word, EEPROM_RSSI_OFFSET_BG_2, 0);
1604 rt2x00_eeprom_write(rt2x00dev, EEPROM_RSSI_OFFSET_BG, word);
1605 }
1606
1607 rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_OFFSET_A, &word);
1608 if (word == 0xffff) {
1609 rt2x00_set_field16(&word, EEPROM_RSSI_OFFSET_A_1, 0);
1610 rt2x00_set_field16(&word, EEPROM_RSSI_OFFSET_A_2, 0);
1611 rt2x00_eeprom_write(rt2x00dev, EEPROM_RSSI_OFFSET_A, word);
417f412f 1612 EEPROM(rt2x00dev, "RSSI OFFSET A: 0x%04x\n", word);
95ea3627
ID		 1613 } else {
1614 value = rt2x00_get_field16(word, EEPROM_RSSI_OFFSET_A_1);
1615 if (value < -10 || value > 10)
1616 rt2x00_set_field16(&word, EEPROM_RSSI_OFFSET_A_1, 0);
1617 value = rt2x00_get_field16(word, EEPROM_RSSI_OFFSET_A_2);
1618 if (value < -10 || value > 10)
1619 rt2x00_set_field16(&word, EEPROM_RSSI_OFFSET_A_2, 0);
1620 rt2x00_eeprom_write(rt2x00dev, EEPROM_RSSI_OFFSET_A, word);
1621 }
1622
1623 return 0;
1624}
1625
1626static int rt73usb_init_eeprom(struct rt2x00_dev *rt2x00dev)
1627{
1628 u32 reg;
1629 u16 value;
1630 u16 eeprom;
1631
1632 /*
1633 * Read EEPROM word for configuration.
1634 */
1635 rt2x00_eeprom_read(rt2x00dev, EEPROM_ANTENNA, &eeprom);
1636
1637 /*
1638 * Identify RF chipset.
1639 */
1640 value = rt2x00_get_field16(eeprom, EEPROM_ANTENNA_RF_TYPE);
1641 rt73usb_register_read(rt2x00dev, MAC_CSR0, &reg);
1642 rt2x00_set_chip(rt2x00dev, RT2571, value, reg);
1643
755a957d 1644 if (!rt2x00_check_rev(&rt2x00dev->chip, 0x25730)) {
95ea3627
ID		 1645 ERROR(rt2x00dev, "Invalid RT chipset detected.\n");
1646 return -ENODEV;
1647 }
1648
1649 if (!rt2x00_rf(&rt2x00dev->chip, RF5226) &&
1650 !rt2x00_rf(&rt2x00dev->chip, RF2528) &&
1651 !rt2x00_rf(&rt2x00dev->chip, RF5225) &&
1652 !rt2x00_rf(&rt2x00dev->chip, RF2527)) {
1653 ERROR(rt2x00dev, "Invalid RF chipset detected.\n");
1654 return -ENODEV;
1655 }
1656
1657 /*
1658 * Identify default antenna configuration.
1659 */
addc81bd 1660 rt2x00dev->default_ant.tx =
95ea3627 1661 rt2x00_get_field16(eeprom, EEPROM_ANTENNA_TX_DEFAULT);
addc81bd 1662 rt2x00dev->default_ant.rx =
95ea3627
ID		 1663 rt2x00_get_field16(eeprom, EEPROM_ANTENNA_RX_DEFAULT);
1664
1665 /*
1666 * Read the Frame type.
1667 */
1668 if (rt2x00_get_field16(eeprom, EEPROM_ANTENNA_FRAME_TYPE))
1669 __set_bit(CONFIG_FRAME_TYPE, &rt2x00dev->flags);
1670
1671 /*
1672 * Read frequency offset.
1673 */
1674 rt2x00_eeprom_read(rt2x00dev, EEPROM_FREQ, &eeprom);
1675 rt2x00dev->freq_offset = rt2x00_get_field16(eeprom, EEPROM_FREQ_OFFSET);
1676
1677 /*
1678 * Read external LNA informations.
1679 */
1680 rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC, &eeprom);
1681
1682 if (rt2x00_get_field16(eeprom, EEPROM_NIC_EXTERNAL_LNA)) {
1683 __set_bit(CONFIG_EXTERNAL_LNA_A, &rt2x00dev->flags);
1684 __set_bit(CONFIG_EXTERNAL_LNA_BG, &rt2x00dev->flags);
1685 }
1686
1687 /*
1688 * Store led settings, for correct led behaviour.
1689 */
a9450b70 1690#ifdef CONFIG_RT73USB_LEDS
95ea3627
ID		 1691 rt2x00_eeprom_read(rt2x00dev, EEPROM_LED, &eeprom);
1692
475433be
ID		 1693 rt73usb_init_led(rt2x00dev, &rt2x00dev->led_radio, LED_TYPE_RADIO);
1694 rt73usb_init_led(rt2x00dev, &rt2x00dev->led_assoc, LED_TYPE_ASSOC);
1695 if (value == LED_MODE_SIGNAL_STRENGTH)
1696 rt73usb_init_led(rt2x00dev, &rt2x00dev->led_qual,
1697 LED_TYPE_QUALITY);
a9450b70
ID		 1698
1699 rt2x00_set_field16(&rt2x00dev->led_mcu_reg, MCU_LEDCS_LED_MODE, value);
1700 rt2x00_set_field16(&rt2x00dev->led_mcu_reg, MCU_LEDCS_POLARITY_GPIO_0,
95ea3627
ID		 1701 rt2x00_get_field16(eeprom,
1702 EEPROM_LED_POLARITY_GPIO_0));
a9450b70 1703 rt2x00_set_field16(&rt2x00dev->led_mcu_reg, MCU_LEDCS_POLARITY_GPIO_1,
95ea3627
ID		 1704 rt2x00_get_field16(eeprom,
1705 EEPROM_LED_POLARITY_GPIO_1));
a9450b70 1706 rt2x00_set_field16(&rt2x00dev->led_mcu_reg, MCU_LEDCS_POLARITY_GPIO_2,
95ea3627
ID		 1707 rt2x00_get_field16(eeprom,
1708 EEPROM_LED_POLARITY_GPIO_2));
a9450b70 1709 rt2x00_set_field16(&rt2x00dev->led_mcu_reg, MCU_LEDCS_POLARITY_GPIO_3,
95ea3627
ID		 1710 rt2x00_get_field16(eeprom,
1711 EEPROM_LED_POLARITY_GPIO_3));
a9450b70 1712 rt2x00_set_field16(&rt2x00dev->led_mcu_reg, MCU_LEDCS_POLARITY_GPIO_4,
95ea3627
ID		 1713 rt2x00_get_field16(eeprom,
1714 EEPROM_LED_POLARITY_GPIO_4));
a9450b70 1715 rt2x00_set_field16(&rt2x00dev->led_mcu_reg, MCU_LEDCS_POLARITY_ACT,
95ea3627 1716 rt2x00_get_field16(eeprom, EEPROM_LED_POLARITY_ACT));
a9450b70 1717 rt2x00_set_field16(&rt2x00dev->led_mcu_reg, MCU_LEDCS_POLARITY_READY_BG,
95ea3627
ID		 1718 rt2x00_get_field16(eeprom,
1719 EEPROM_LED_POLARITY_RDY_G));
a9450b70 1720 rt2x00_set_field16(&rt2x00dev->led_mcu_reg, MCU_LEDCS_POLARITY_READY_A,
95ea3627
ID		 1721 rt2x00_get_field16(eeprom,
1722 EEPROM_LED_POLARITY_RDY_A));
a9450b70 1723#endif /* CONFIG_RT73USB_LEDS */
95ea3627
ID		 1724
1725 return 0;
1726}
1727
1728/*
1729 * RF value list for RF2528
1730 * Supports: 2.4 GHz
1731 */
1732static const struct rf_channel rf_vals_bg_2528[] = {
1733 { 1, 0x00002c0c, 0x00000786, 0x00068255, 0x000fea0b },
1734 { 2, 0x00002c0c, 0x00000786, 0x00068255, 0x000fea1f },
1735 { 3, 0x00002c0c, 0x0000078a, 0x00068255, 0x000fea0b },
1736 { 4, 0x00002c0c, 0x0000078a, 0x00068255, 0x000fea1f },
1737 { 5, 0x00002c0c, 0x0000078e, 0x00068255, 0x000fea0b },
1738 { 6, 0x00002c0c, 0x0000078e, 0x00068255, 0x000fea1f },
1739 { 7, 0x00002c0c, 0x00000792, 0x00068255, 0x000fea0b },
1740 { 8, 0x00002c0c, 0x00000792, 0x00068255, 0x000fea1f },
1741 { 9, 0x00002c0c, 0x00000796, 0x00068255, 0x000fea0b },
1742 { 10, 0x00002c0c, 0x00000796, 0x00068255, 0x000fea1f },
1743 { 11, 0x00002c0c, 0x0000079a, 0x00068255, 0x000fea0b },
1744 { 12, 0x00002c0c, 0x0000079a, 0x00068255, 0x000fea1f },
1745 { 13, 0x00002c0c, 0x0000079e, 0x00068255, 0x000fea0b },
1746 { 14, 0x00002c0c, 0x000007a2, 0x00068255, 0x000fea13 },
1747};
1748
1749/*
1750 * RF value list for RF5226
1751 * Supports: 2.4 GHz & 5.2 GHz
1752 */
1753static const struct rf_channel rf_vals_5226[] = {
1754 { 1, 0x00002c0c, 0x00000786, 0x00068255, 0x000fea0b },
1755 { 2, 0x00002c0c, 0x00000786, 0x00068255, 0x000fea1f },
1756 { 3, 0x00002c0c, 0x0000078a, 0x00068255, 0x000fea0b },
1757 { 4, 0x00002c0c, 0x0000078a, 0x00068255, 0x000fea1f },
1758 { 5, 0x00002c0c, 0x0000078e, 0x00068255, 0x000fea0b },
1759 { 6, 0x00002c0c, 0x0000078e, 0x00068255, 0x000fea1f },
1760 { 7, 0x00002c0c, 0x00000792, 0x00068255, 0x000fea0b },
1761 { 8, 0x00002c0c, 0x00000792, 0x00068255, 0x000fea1f },
1762 { 9, 0x00002c0c, 0x00000796, 0x00068255, 0x000fea0b },
1763 { 10, 0x00002c0c, 0x00000796, 0x00068255, 0x000fea1f },
1764 { 11, 0x00002c0c, 0x0000079a, 0x00068255, 0x000fea0b },
1765 { 12, 0x00002c0c, 0x0000079a, 0x00068255, 0x000fea1f },
1766 { 13, 0x00002c0c, 0x0000079e, 0x00068255, 0x000fea0b },
1767 { 14, 0x00002c0c, 0x000007a2, 0x00068255, 0x000fea13 },
1768
1769 /* 802.11 UNI / HyperLan 2 */
1770 { 36, 0x00002c0c, 0x0000099a, 0x00098255, 0x000fea23 },
1771 { 40, 0x00002c0c, 0x000009a2, 0x00098255, 0x000fea03 },
1772 { 44, 0x00002c0c, 0x000009a6, 0x00098255, 0x000fea0b },
1773 { 48, 0x00002c0c, 0x000009aa, 0x00098255, 0x000fea13 },
1774 { 52, 0x00002c0c, 0x000009ae, 0x00098255, 0x000fea1b },
1775 { 56, 0x00002c0c, 0x000009b2, 0x00098255, 0x000fea23 },
1776 { 60, 0x00002c0c, 0x000009ba, 0x00098255, 0x000fea03 },
1777 { 64, 0x00002c0c, 0x000009be, 0x00098255, 0x000fea0b },
1778
1779 /* 802.11 HyperLan 2 */
1780 { 100, 0x00002c0c, 0x00000a2a, 0x000b8255, 0x000fea03 },
1781 { 104, 0x00002c0c, 0x00000a2e, 0x000b8255, 0x000fea0b },
1782 { 108, 0x00002c0c, 0x00000a32, 0x000b8255, 0x000fea13 },
1783 { 112, 0x00002c0c, 0x00000a36, 0x000b8255, 0x000fea1b },
1784 { 116, 0x00002c0c, 0x00000a3a, 0x000b8255, 0x000fea23 },
1785 { 120, 0x00002c0c, 0x00000a82, 0x000b8255, 0x000fea03 },
1786 { 124, 0x00002c0c, 0x00000a86, 0x000b8255, 0x000fea0b },
1787 { 128, 0x00002c0c, 0x00000a8a, 0x000b8255, 0x000fea13 },
1788 { 132, 0x00002c0c, 0x00000a8e, 0x000b8255, 0x000fea1b },
1789 { 136, 0x00002c0c, 0x00000a92, 0x000b8255, 0x000fea23 },
1790
1791 /* 802.11 UNII */
1792 { 140, 0x00002c0c, 0x00000a9a, 0x000b8255, 0x000fea03 },
1793 { 149, 0x00002c0c, 0x00000aa2, 0x000b8255, 0x000fea1f },
1794 { 153, 0x00002c0c, 0x00000aa6, 0x000b8255, 0x000fea27 },
1795 { 157, 0x00002c0c, 0x00000aae, 0x000b8255, 0x000fea07 },
1796 { 161, 0x00002c0c, 0x00000ab2, 0x000b8255, 0x000fea0f },
1797 { 165, 0x00002c0c, 0x00000ab6, 0x000b8255, 0x000fea17 },
1798
1799 /* MMAC(Japan)J52 ch 34,38,42,46 */
1800 { 34, 0x00002c0c, 0x0008099a, 0x000da255, 0x000d3a0b },
1801 { 38, 0x00002c0c, 0x0008099e, 0x000da255, 0x000d3a13 },
1802 { 42, 0x00002c0c, 0x000809a2, 0x000da255, 0x000d3a1b },
1803 { 46, 0x00002c0c, 0x000809a6, 0x000da255, 0x000d3a23 },
1804};
1805
1806/*
1807 * RF value list for RF5225 & RF2527
1808 * Supports: 2.4 GHz & 5.2 GHz
1809 */
1810static const struct rf_channel rf_vals_5225_2527[] = {
1811 { 1, 0x00002ccc, 0x00004786, 0x00068455, 0x000ffa0b },
1812 { 2, 0x00002ccc, 0x00004786, 0x00068455, 0x000ffa1f },
1813 { 3, 0x00002ccc, 0x0000478a, 0x00068455, 0x000ffa0b },
1814 { 4, 0x00002ccc, 0x0000478a, 0x00068455, 0x000ffa1f },
1815 { 5, 0x00002ccc, 0x0000478e, 0x00068455, 0x000ffa0b },
1816 { 6, 0x00002ccc, 0x0000478e, 0x00068455, 0x000ffa1f },
1817 { 7, 0x00002ccc, 0x00004792, 0x00068455, 0x000ffa0b },
1818 { 8, 0x00002ccc, 0x00004792, 0x00068455, 0x000ffa1f },
1819 { 9, 0x00002ccc, 0x00004796, 0x00068455, 0x000ffa0b },
1820 { 10, 0x00002ccc, 0x00004796, 0x00068455, 0x000ffa1f },
1821 { 11, 0x00002ccc, 0x0000479a, 0x00068455, 0x000ffa0b },
1822 { 12, 0x00002ccc, 0x0000479a, 0x00068455, 0x000ffa1f },
1823 { 13, 0x00002ccc, 0x0000479e, 0x00068455, 0x000ffa0b },
1824 { 14, 0x00002ccc, 0x000047a2, 0x00068455, 0x000ffa13 },
1825
1826 /* 802.11 UNI / HyperLan 2 */
1827 { 36, 0x00002ccc, 0x0000499a, 0x0009be55, 0x000ffa23 },
1828 { 40, 0x00002ccc, 0x000049a2, 0x0009be55, 0x000ffa03 },
1829 { 44, 0x00002ccc, 0x000049a6, 0x0009be55, 0x000ffa0b },
1830 { 48, 0x00002ccc, 0x000049aa, 0x0009be55, 0x000ffa13 },
1831 { 52, 0x00002ccc, 0x000049ae, 0x0009ae55, 0x000ffa1b },
1832 { 56, 0x00002ccc, 0x000049b2, 0x0009ae55, 0x000ffa23 },
1833 { 60, 0x00002ccc, 0x000049ba, 0x0009ae55, 0x000ffa03 },
1834 { 64, 0x00002ccc, 0x000049be, 0x0009ae55, 0x000ffa0b },
1835
1836 /* 802.11 HyperLan 2 */
1837 { 100, 0x00002ccc, 0x00004a2a, 0x000bae55, 0x000ffa03 },
1838 { 104, 0x00002ccc, 0x00004a2e, 0x000bae55, 0x000ffa0b },
1839 { 108, 0x00002ccc, 0x00004a32, 0x000bae55, 0x000ffa13 },
1840 { 112, 0x00002ccc, 0x00004a36, 0x000bae55, 0x000ffa1b },
1841 { 116, 0x00002ccc, 0x00004a3a, 0x000bbe55, 0x000ffa23 },
1842 { 120, 0x00002ccc, 0x00004a82, 0x000bbe55, 0x000ffa03 },
1843 { 124, 0x00002ccc, 0x00004a86, 0x000bbe55, 0x000ffa0b },
1844 { 128, 0x00002ccc, 0x00004a8a, 0x000bbe55, 0x000ffa13 },
1845 { 132, 0x00002ccc, 0x00004a8e, 0x000bbe55, 0x000ffa1b },
1846 { 136, 0x00002ccc, 0x00004a92, 0x000bbe55, 0x000ffa23 },
1847
1848 /* 802.11 UNII */
1849 { 140, 0x00002ccc, 0x00004a9a, 0x000bbe55, 0x000ffa03 },
1850 { 149, 0x00002ccc, 0x00004aa2, 0x000bbe55, 0x000ffa1f },
1851 { 153, 0x00002ccc, 0x00004aa6, 0x000bbe55, 0x000ffa27 },
1852 { 157, 0x00002ccc, 0x00004aae, 0x000bbe55, 0x000ffa07 },
1853 { 161, 0x00002ccc, 0x00004ab2, 0x000bbe55, 0x000ffa0f },
1854 { 165, 0x00002ccc, 0x00004ab6, 0x000bbe55, 0x000ffa17 },
1855
1856 /* MMAC(Japan)J52 ch 34,38,42,46 */
1857 { 34, 0x00002ccc, 0x0000499a, 0x0009be55, 0x000ffa0b },
1858 { 38, 0x00002ccc, 0x0000499e, 0x0009be55, 0x000ffa13 },
1859 { 42, 0x00002ccc, 0x000049a2, 0x0009be55, 0x000ffa1b },
1860 { 46, 0x00002ccc, 0x000049a6, 0x0009be55, 0x000ffa23 },
1861};
1862
1863
1864static void rt73usb_probe_hw_mode(struct rt2x00_dev *rt2x00dev)
1865{
1866 struct hw_mode_spec *spec = &rt2x00dev->spec;
1867 u8 *txpower;
1868 unsigned int i;
1869
1870 /*
1871 * Initialize all hw fields.
1872 */
1873 rt2x00dev->hw->flags =
566bfe5a
BR		 1874 IEEE80211_HW_HOST_BROADCAST_PS_BUFFERING |
1875 IEEE80211_HW_SIGNAL_DBM;
95ea3627 1876 rt2x00dev->hw->extra_tx_headroom = TXD_DESC_SIZE;
95ea3627 1877
14a3bf89 1878 SET_IEEE80211_DEV(rt2x00dev->hw, rt2x00dev->dev);
95ea3627
ID		 1879 SET_IEEE80211_PERM_ADDR(rt2x00dev->hw,
1880 rt2x00_eeprom_addr(rt2x00dev,
1881 EEPROM_MAC_ADDR_0));
1882
1883 /*
1884 * Convert tx_power array in eeprom.
1885 */
1886 txpower = rt2x00_eeprom_addr(rt2x00dev, EEPROM_TXPOWER_G_START);
1887 for (i = 0; i < 14; i++)
1888 txpower[i] = TXPOWER_FROM_DEV(txpower[i]);
1889
1890 /*
1891 * Initialize hw_mode information.
1892 */
31562e80
ID		 1893 spec->supported_bands = SUPPORT_BAND_2GHZ;
1894 spec->supported_rates = SUPPORT_RATE_CCK | SUPPORT_RATE_OFDM;
95ea3627
ID		 1895 spec->tx_power_a = NULL;
1896 spec->tx_power_bg = txpower;
1897 spec->tx_power_default = DEFAULT_TXPOWER;
1898
1899 if (rt2x00_rf(&rt2x00dev->chip, RF2528)) {
1900 spec->num_channels = ARRAY_SIZE(rf_vals_bg_2528);
1901 spec->channels = rf_vals_bg_2528;
1902 } else if (rt2x00_rf(&rt2x00dev->chip, RF5226)) {
31562e80 1903 spec->supported_bands |= SUPPORT_BAND_5GHZ;
95ea3627
ID		 1904 spec->num_channels = ARRAY_SIZE(rf_vals_5226);
1905 spec->channels = rf_vals_5226;
1906 } else if (rt2x00_rf(&rt2x00dev->chip, RF2527)) {
1907 spec->num_channels = 14;
1908 spec->channels = rf_vals_5225_2527;
1909 } else if (rt2x00_rf(&rt2x00dev->chip, RF5225)) {
31562e80 1910 spec->supported_bands |= SUPPORT_BAND_5GHZ;
95ea3627
ID		 1911 spec->num_channels = ARRAY_SIZE(rf_vals_5225_2527);
1912 spec->channels = rf_vals_5225_2527;
1913 }
1914
1915 if (rt2x00_rf(&rt2x00dev->chip, RF5225) ||
1916 rt2x00_rf(&rt2x00dev->chip, RF5226)) {
95ea3627
ID		 1917 txpower = rt2x00_eeprom_addr(rt2x00dev, EEPROM_TXPOWER_A_START);
1918 for (i = 0; i < 14; i++)
1919 txpower[i] = TXPOWER_FROM_DEV(txpower[i]);
1920
1921 spec->tx_power_a = txpower;
1922 }
1923}
1924
1925static int rt73usb_probe_hw(struct rt2x00_dev *rt2x00dev)
1926{
1927 int retval;
1928
1929 /*
1930 * Allocate eeprom data.
1931 */
1932 retval = rt73usb_validate_eeprom(rt2x00dev);
1933 if (retval)
1934 return retval;
1935
1936 retval = rt73usb_init_eeprom(rt2x00dev);
1937 if (retval)
1938 return retval;
1939
1940 /*
1941 * Initialize hw specifications.
1942 */
1943 rt73usb_probe_hw_mode(rt2x00dev);
1944
1945 /*
9404ef34 1946 * This device requires firmware.
95ea3627 1947 */
066cb637 1948 __set_bit(DRIVER_REQUIRE_FIRMWARE, &rt2x00dev->flags);
3a643d24 1949 __set_bit(DRIVER_REQUIRE_SCHEDULED, &rt2x00dev->flags);
95ea3627
ID		 1950
1951 /*
1952 * Set the rssi offset.
1953 */
1954 rt2x00dev->rssi_offset = DEFAULT_RSSI_OFFSET;
1955
1956 return 0;
1957}
1958
1959/*
1960 * IEEE80211 stack callback functions.
1961 */
1962static int rt73usb_set_retry_limit(struct ieee80211_hw *hw,
1963 u32 short_retry, u32 long_retry)
1964{
1965 struct rt2x00_dev *rt2x00dev = hw->priv;
1966 u32 reg;
1967
1968 rt73usb_register_read(rt2x00dev, TXRX_CSR4, &reg);
1969 rt2x00_set_field32(&reg, TXRX_CSR4_LONG_RETRY_LIMIT, long_retry);
1970 rt2x00_set_field32(&reg, TXRX_CSR4_SHORT_RETRY_LIMIT, short_retry);
1971 rt73usb_register_write(rt2x00dev, TXRX_CSR4, reg);
1972
1973 return 0;
1974}
1975
1976#if 0
1977/*
1978 * Mac80211 demands get_tsf must be atomic.
1979 * This is not possible for rt73usb since all register access
1980 * functions require sleeping. Untill mac80211 no longer needs
1981 * get_tsf to be atomic, this function should be disabled.
1982 */
1983static u64 rt73usb_get_tsf(struct ieee80211_hw *hw)
1984{
1985 struct rt2x00_dev *rt2x00dev = hw->priv;
1986 u64 tsf;
1987 u32 reg;
1988
1989 rt73usb_register_read(rt2x00dev, TXRX_CSR13, &reg);
1990 tsf = (u64) rt2x00_get_field32(reg, TXRX_CSR13_HIGH_TSFTIMER) << 32;
1991 rt73usb_register_read(rt2x00dev, TXRX_CSR12, &reg);
1992 tsf |= rt2x00_get_field32(reg, TXRX_CSR12_LOW_TSFTIMER);
1993
1994 return tsf;
1995}
37894473
ID		 1996#else
1997#define rt73usb_get_tsf NULL
95ea3627
ID		 1998#endif
1999
95ea3627
ID		 2000static const struct ieee80211_ops rt73usb_mac80211_ops = {
2001 .tx = rt2x00mac_tx,
4150c572
JB		 2002 .start = rt2x00mac_start,
2003 .stop = rt2x00mac_stop,
95ea3627
ID		 2004 .add_interface = rt2x00mac_add_interface,
2005 .remove_interface = rt2x00mac_remove_interface,
2006 .config = rt2x00mac_config,
2007 .config_interface = rt2x00mac_config_interface,
3a643d24 2008 .configure_filter = rt2x00mac_configure_filter,
95ea3627
ID		 2009 .get_stats = rt2x00mac_get_stats,
2010 .set_retry_limit = rt73usb_set_retry_limit,
471b3efd 2011 .bss_info_changed = rt2x00mac_bss_info_changed,
95ea3627
ID		 2012 .conf_tx = rt2x00mac_conf_tx,
2013 .get_tx_stats = rt2x00mac_get_tx_stats,
95ea3627 2014 .get_tsf = rt73usb_get_tsf,
95ea3627
ID		 2015};
2016
2017static const struct rt2x00lib_ops rt73usb_rt2x00_ops = {
2018 .probe_hw = rt73usb_probe_hw,
2019 .get_firmware_name = rt73usb_get_firmware_name,
a7f3a06c 2020 .get_firmware_crc = rt73usb_get_firmware_crc,
95ea3627
ID		 2021 .load_firmware = rt73usb_load_firmware,
2022 .initialize = rt2x00usb_initialize,
2023 .uninitialize = rt2x00usb_uninitialize,
837e7f24
ID		 2024 .init_rxentry = rt2x00usb_init_rxentry,
2025 .init_txentry = rt2x00usb_init_txentry,
95ea3627
ID		 2026 .set_device_state = rt73usb_set_device_state,
2027 .link_stats = rt73usb_link_stats,
2028 .reset_tuner = rt73usb_reset_tuner,
2029 .link_tuner = rt73usb_link_tuner,
2030 .write_tx_desc = rt73usb_write_tx_desc,
2031 .write_tx_data = rt2x00usb_write_tx_data,
bd88a781 2032 .write_beacon = rt73usb_write_beacon,
dd9fa2d2 2033 .get_tx_data_len = rt73usb_get_tx_data_len,
95ea3627
ID		 2034 .kick_tx_queue = rt73usb_kick_tx_queue,
2035 .fill_rxdone = rt73usb_fill_rxdone,
3a643d24 2036 .config_filter = rt73usb_config_filter,
6bb40dd1 2037 .config_intf = rt73usb_config_intf,
72810379 2038 .config_erp = rt73usb_config_erp,
95ea3627
ID		 2039 .config = rt73usb_config,
2040};
2041
181d6902
ID		 2042static const struct data_queue_desc rt73usb_queue_rx = {
2043 .entry_num = RX_ENTRIES,
2044 .data_size = DATA_FRAME_SIZE,
2045 .desc_size = RXD_DESC_SIZE,
b8be63ff 2046 .priv_size = sizeof(struct queue_entry_priv_usb),
181d6902
ID		 2047};
2048
2049static const struct data_queue_desc rt73usb_queue_tx = {
2050 .entry_num = TX_ENTRIES,
2051 .data_size = DATA_FRAME_SIZE,
2052 .desc_size = TXD_DESC_SIZE,
b8be63ff 2053 .priv_size = sizeof(struct queue_entry_priv_usb),
181d6902
ID		 2054};
2055
2056static const struct data_queue_desc rt73usb_queue_bcn = {
6bb40dd1 2057 .entry_num = 4 * BEACON_ENTRIES,
181d6902
ID		 2058 .data_size = MGMT_FRAME_SIZE,
2059 .desc_size = TXINFO_SIZE,
b8be63ff 2060 .priv_size = sizeof(struct queue_entry_priv_usb),
181d6902
ID		 2061};
2062
95ea3627 2063static const struct rt2x00_ops rt73usb_ops = {
2360157c 2064 .name = KBUILD_MODNAME,
6bb40dd1
ID		 2065 .max_sta_intf = 1,
2066 .max_ap_intf = 4,
95ea3627
ID		 2067 .eeprom_size = EEPROM_SIZE,
2068 .rf_size = RF_SIZE,
61448f88 2069 .tx_queues = NUM_TX_QUEUES,
181d6902
ID		 2070 .rx = &rt73usb_queue_rx,
2071 .tx = &rt73usb_queue_tx,
2072 .bcn = &rt73usb_queue_bcn,
95ea3627
ID		 2073 .lib = &rt73usb_rt2x00_ops,
2074 .hw = &rt73usb_mac80211_ops,
2075#ifdef CONFIG_RT2X00_LIB_DEBUGFS
2076 .debugfs = &rt73usb_rt2x00debug,
2077#endif /* CONFIG_RT2X00_LIB_DEBUGFS */
2078};
2079
2080/*
2081 * rt73usb module information.
2082 */
2083static struct usb_device_id rt73usb_device_table[] = {
2084 /* AboCom */
2085 { USB_DEVICE(0x07b8, 0xb21d), USB_DEVICE_DATA(&rt73usb_ops) },
2086 /* Askey */
2087 { USB_DEVICE(0x1690, 0x0722), USB_DEVICE_DATA(&rt73usb_ops) },
2088 /* ASUS */
2089 { USB_DEVICE(0x0b05, 0x1723), USB_DEVICE_DATA(&rt73usb_ops) },
2090 { USB_DEVICE(0x0b05, 0x1724), USB_DEVICE_DATA(&rt73usb_ops) },
2091 /* Belkin */
2092 { USB_DEVICE(0x050d, 0x7050), USB_DEVICE_DATA(&rt73usb_ops) },
2093 { USB_DEVICE(0x050d, 0x705a), USB_DEVICE_DATA(&rt73usb_ops) },
2094 { USB_DEVICE(0x050d, 0x905b), USB_DEVICE_DATA(&rt73usb_ops) },
1f06862e 2095 { USB_DEVICE(0x050d, 0x905c), USB_DEVICE_DATA(&rt73usb_ops) },
95ea3627
ID		 2096 /* Billionton */
2097 { USB_DEVICE(0x1631, 0xc019), USB_DEVICE_DATA(&rt73usb_ops) },
2098 /* Buffalo */
2099 { USB_DEVICE(0x0411, 0x00f4), USB_DEVICE_DATA(&rt73usb_ops) },
2100 /* CNet */
2101 { USB_DEVICE(0x1371, 0x9022), USB_DEVICE_DATA(&rt73usb_ops) },
2102 { USB_DEVICE(0x1371, 0x9032), USB_DEVICE_DATA(&rt73usb_ops) },
2103 /* Conceptronic */
2104 { USB_DEVICE(0x14b2, 0x3c22), USB_DEVICE_DATA(&rt73usb_ops) },
0a74892b
MM		 2105 /* Corega */
2106 { USB_DEVICE(0x07aa, 0x002e), USB_DEVICE_DATA(&rt73usb_ops) },
95ea3627
ID		 2107 /* D-Link */
2108 { USB_DEVICE(0x07d1, 0x3c03), USB_DEVICE_DATA(&rt73usb_ops) },
2109 { USB_DEVICE(0x07d1, 0x3c04), USB_DEVICE_DATA(&rt73usb_ops) },
cb62eccd 2110 { USB_DEVICE(0x07d1, 0x3c06), USB_DEVICE_DATA(&rt73usb_ops) },
445815d7 2111 { USB_DEVICE(0x07d1, 0x3c07), USB_DEVICE_DATA(&rt73usb_ops) },
95ea3627
ID		 2112 /* Gemtek */
2113 { USB_DEVICE(0x15a9, 0x0004), USB_DEVICE_DATA(&rt73usb_ops) },
2114 /* Gigabyte */
2115 { USB_DEVICE(0x1044, 0x8008), USB_DEVICE_DATA(&rt73usb_ops) },
2116 { USB_DEVICE(0x1044, 0x800a), USB_DEVICE_DATA(&rt73usb_ops) },
2117 /* Huawei-3Com */
2118 { USB_DEVICE(0x1472, 0x0009), USB_DEVICE_DATA(&rt73usb_ops) },
2119 /* Hercules */
2120 { USB_DEVICE(0x06f8, 0xe010), USB_DEVICE_DATA(&rt73usb_ops) },
2121 { USB_DEVICE(0x06f8, 0xe020), USB_DEVICE_DATA(&rt73usb_ops) },
2122 /* Linksys */
2123 { USB_DEVICE(0x13b1, 0x0020), USB_DEVICE_DATA(&rt73usb_ops) },
2124 { USB_DEVICE(0x13b1, 0x0023), USB_DEVICE_DATA(&rt73usb_ops) },
2125 /* MSI */
2126 { USB_DEVICE(0x0db0, 0x6877), USB_DEVICE_DATA(&rt73usb_ops) },
2127 { USB_DEVICE(0x0db0, 0x6874), USB_DEVICE_DATA(&rt73usb_ops) },
2128 { USB_DEVICE(0x0db0, 0xa861), USB_DEVICE_DATA(&rt73usb_ops) },
2129 { USB_DEVICE(0x0db0, 0xa874), USB_DEVICE_DATA(&rt73usb_ops) },
2130 /* Ralink */
2131 { USB_DEVICE(0x148f, 0x2573), USB_DEVICE_DATA(&rt73usb_ops) },
2132 { USB_DEVICE(0x148f, 0x2671), USB_DEVICE_DATA(&rt73usb_ops) },
2133 /* Qcom */
2134 { USB_DEVICE(0x18e8, 0x6196), USB_DEVICE_DATA(&rt73usb_ops) },
2135 { USB_DEVICE(0x18e8, 0x6229), USB_DEVICE_DATA(&rt73usb_ops) },
2136 { USB_DEVICE(0x18e8, 0x6238), USB_DEVICE_DATA(&rt73usb_ops) },
2137 /* Senao */
2138 { USB_DEVICE(0x1740, 0x7100), USB_DEVICE_DATA(&rt73usb_ops) },
2139 /* Sitecom */
2140 { USB_DEVICE(0x0df6, 0x9712), USB_DEVICE_DATA(&rt73usb_ops) },
2141 { USB_DEVICE(0x0df6, 0x90ac), USB_DEVICE_DATA(&rt73usb_ops) },
2142 /* Surecom */
2143 { USB_DEVICE(0x0769, 0x31f3), USB_DEVICE_DATA(&rt73usb_ops) },
2144 /* Planex */
2145 { USB_DEVICE(0x2019, 0xab01), USB_DEVICE_DATA(&rt73usb_ops) },
2146 { USB_DEVICE(0x2019, 0xab50), USB_DEVICE_DATA(&rt73usb_ops) },
2147 { 0, }
2148};
2149
2150MODULE_AUTHOR(DRV_PROJECT);
2151MODULE_VERSION(DRV_VERSION);
2152MODULE_DESCRIPTION("Ralink RT73 USB Wireless LAN driver.");
2153MODULE_SUPPORTED_DEVICE("Ralink RT2571W & RT2671 USB chipset based cards");
2154MODULE_DEVICE_TABLE(usb, rt73usb_device_table);
2155MODULE_FIRMWARE(FIRMWARE_RT2571);
2156MODULE_LICENSE("GPL");
2157
2158static struct usb_driver rt73usb_driver = {
2360157c 2159 .name = KBUILD_MODNAME,
95ea3627
ID		 2160 .id_table = rt73usb_device_table,
2161 .probe = rt2x00usb_probe,
2162 .disconnect = rt2x00usb_disconnect,
2163 .suspend = rt2x00usb_suspend,
2164 .resume = rt2x00usb_resume,
2165};
2166
2167static int __init rt73usb_init(void)
2168{
2169 return usb_register(&rt73usb_driver);
2170}
2171
2172static void __exit rt73usb_exit(void)
2173{
2174 usb_deregister(&rt73usb_driver);
2175}
2176
2177module_init(rt73usb_init);
2178module_exit(rt73usb_exit);
Linux kernel - Deliverables
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