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rtl8187: Fix for TX sequence number problem
[deliverable/linux.git] / drivers / net / wireless / rtl8187_dev.c
CommitLineData
605bebe2
MW		 1/*
2 * Linux device driver for RTL8187
3 *
4 * Copyright 2007 Michael Wu <flamingice@sourmilk.net>
5 * Copyright 2007 Andrea Merello <andreamrl@tiscali.it>
6 *
7 * Based on the r8187 driver, which is:
8 * Copyright 2005 Andrea Merello <andreamrl@tiscali.it>, et al.
9 *
0aec00ae
JL		 10 * Magic delays and register offsets below are taken from the original
11 * r8187 driver sources. Thanks to Realtek for their support!
605bebe2
MW		 12 *
13 * This program is free software; you can redistribute it and/or modify
14 * it under the terms of the GNU General Public License version 2 as
15 * published by the Free Software Foundation.
16 */
17
18#include <linux/init.h>
19#include <linux/usb.h>
20#include <linux/delay.h>
21#include <linux/etherdevice.h>
22#include <linux/eeprom_93cx6.h>
23#include <net/mac80211.h>
24
25#include "rtl8187.h"
26#include "rtl8187_rtl8225.h"
27
28MODULE_AUTHOR("Michael Wu <flamingice@sourmilk.net>");
29MODULE_AUTHOR("Andrea Merello <andreamrl@tiscali.it>");
f8a08c34 30MODULE_DESCRIPTION("RTL8187/RTL8187B USB wireless driver");
605bebe2
MW		 31MODULE_LICENSE("GPL");
32
33static struct usb_device_id rtl8187_table[] __devinitdata = {
34 /* Realtek */
f8a08c34
HTL		 35 {USB_DEVICE(0x0bda, 0x8187), .driver_info = DEVICE_RTL8187},
36 {USB_DEVICE(0x0bda, 0x8189), .driver_info = DEVICE_RTL8187B},
37 {USB_DEVICE(0x0bda, 0x8197), .driver_info = DEVICE_RTL8187B},
605bebe2 38 /* Netgear */
f8a08c34
HTL		 39 {USB_DEVICE(0x0846, 0x6100), .driver_info = DEVICE_RTL8187},
40 {USB_DEVICE(0x0846, 0x6a00), .driver_info = DEVICE_RTL8187},
c3cf60a9 41 /* HP */
f8a08c34 42 {USB_DEVICE(0x03f0, 0xca02), .driver_info = DEVICE_RTL8187},
9934550d 43 /* Sitecom */
f8a08c34 44 {USB_DEVICE(0x0df6, 0x000d), .driver_info = DEVICE_RTL8187},
605bebe2
MW		 45 {}
46};
47
48MODULE_DEVICE_TABLE(usb, rtl8187_table);
49
8318d78a
JB		 50static const struct ieee80211_rate rtl818x_rates[] = {
51 { .bitrate = 10, .hw_value = 0, },
52 { .bitrate = 20, .hw_value = 1, },
53 { .bitrate = 55, .hw_value = 2, },
54 { .bitrate = 110, .hw_value = 3, },
55 { .bitrate = 60, .hw_value = 4, },
56 { .bitrate = 90, .hw_value = 5, },
57 { .bitrate = 120, .hw_value = 6, },
58 { .bitrate = 180, .hw_value = 7, },
59 { .bitrate = 240, .hw_value = 8, },
60 { .bitrate = 360, .hw_value = 9, },
61 { .bitrate = 480, .hw_value = 10, },
62 { .bitrate = 540, .hw_value = 11, },
63};
64
65static const struct ieee80211_channel rtl818x_channels[] = {
66 { .center_freq = 2412 },
67 { .center_freq = 2417 },
68 { .center_freq = 2422 },
69 { .center_freq = 2427 },
70 { .center_freq = 2432 },
71 { .center_freq = 2437 },
72 { .center_freq = 2442 },
73 { .center_freq = 2447 },
74 { .center_freq = 2452 },
75 { .center_freq = 2457 },
76 { .center_freq = 2462 },
77 { .center_freq = 2467 },
78 { .center_freq = 2472 },
79 { .center_freq = 2484 },
80};
81
4150c572
JB		 82static void rtl8187_iowrite_async_cb(struct urb *urb)
83{
84 kfree(urb->context);
85 usb_free_urb(urb);
86}
87
88static void rtl8187_iowrite_async(struct rtl8187_priv *priv, __le16 addr,
89 void *data, u16 len)
90{
91 struct usb_ctrlrequest *dr;
92 struct urb *urb;
93 struct rtl8187_async_write_data {
94 u8 data[4];
95 struct usb_ctrlrequest dr;
96 } *buf;
ea8ee240 97 int rc;
4150c572
JB		 98
99 buf = kmalloc(sizeof(*buf), GFP_ATOMIC);
100 if (!buf)
101 return;
102
103 urb = usb_alloc_urb(0, GFP_ATOMIC);
104 if (!urb) {
105 kfree(buf);
106 return;
107 }
108
109 dr = &buf->dr;
110
111 dr->bRequestType = RTL8187_REQT_WRITE;
112 dr->bRequest = RTL8187_REQ_SET_REG;
113 dr->wValue = addr;
114 dr->wIndex = 0;
115 dr->wLength = cpu_to_le16(len);
116
117 memcpy(buf, data, len);
118
119 usb_fill_control_urb(urb, priv->udev, usb_sndctrlpipe(priv->udev, 0),
120 (unsigned char *)dr, buf, len,
121 rtl8187_iowrite_async_cb, buf);
ea8ee240
ON		 122 rc = usb_submit_urb(urb, GFP_ATOMIC);
123 if (rc < 0) {
124 kfree(buf);
125 usb_free_urb(urb);
126 }
4150c572
JB		 127}
128
129static inline void rtl818x_iowrite32_async(struct rtl8187_priv *priv,
130 __le32 *addr, u32 val)
131{
132 __le32 buf = cpu_to_le32(val);
133
134 rtl8187_iowrite_async(priv, cpu_to_le16((unsigned long)addr),
135 &buf, sizeof(buf));
136}
137
605bebe2
MW		 138void rtl8187_write_phy(struct ieee80211_hw *dev, u8 addr, u32 data)
139{
140 struct rtl8187_priv *priv = dev->priv;
141
142 data <<= 8;
143 data |= addr | 0x80;
144
145 rtl818x_iowrite8(priv, &priv->map->PHY[3], (data >> 24) & 0xFF);
146 rtl818x_iowrite8(priv, &priv->map->PHY[2], (data >> 16) & 0xFF);
147 rtl818x_iowrite8(priv, &priv->map->PHY[1], (data >> 8) & 0xFF);
148 rtl818x_iowrite8(priv, &priv->map->PHY[0], data & 0xFF);
149
150 msleep(1);
151}
152
153static void rtl8187_tx_cb(struct urb *urb)
154{
605bebe2 155 struct sk_buff *skb = (struct sk_buff *)urb->context;
e039fa4a
JB		 156 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
157 struct ieee80211_hw *hw = info->driver_data[0];
6f7853f3 158 struct rtl8187_priv *priv = hw->priv;
605bebe2 159
e039fa4a 160 usb_free_urb(info->driver_data[1]);
6f7853f3
HTL		 161 skb_pull(skb, priv->is_rtl8187b ? sizeof(struct rtl8187b_tx_hdr) :
162 sizeof(struct rtl8187_tx_hdr));
e039fa4a
JB		 163 memset(&info->status, 0, sizeof(info->status));
164 info->flags |= IEEE80211_TX_STAT_ACK;
165 ieee80211_tx_status_irqsafe(hw, skb);
605bebe2
MW		 166}
167
e039fa4a 168static int rtl8187_tx(struct ieee80211_hw *dev, struct sk_buff *skb)
605bebe2
MW		 169{
170 struct rtl8187_priv *priv = dev->priv;
e039fa4a 171 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
1f690d7b 172 struct ieee80211_hdr *ieee80211hdr = (struct ieee80211_hdr *)skb->data;
6f7853f3
HTL		 173 unsigned int ep;
174 void *buf;
605bebe2 175 struct urb *urb;
98798f48
MW		 176 __le16 rts_dur = 0;
177 u32 flags;
ea8ee240 178 int rc;
605bebe2
MW		 179
180 urb = usb_alloc_urb(0, GFP_ATOMIC);
181 if (!urb) {
182 kfree_skb(skb);
183 return 0;
184 }
185
98798f48
MW		 186 flags = skb->len;
187 flags |= RTL8187_TX_FLAG_NO_ENCRYPT;
aa68cbfb 188
e039fa4a 189 flags |= ieee80211_get_tx_rate(dev, info)->hw_value << 24;
8b7b1e05 190 if (ieee80211_has_morefrags(((struct ieee80211_hdr *)skb->data)->frame_control))
98798f48 191 flags |= RTL8187_TX_FLAG_MORE_FRAG;
e039fa4a 192 if (info->flags & IEEE80211_TX_CTL_USE_RTS_CTS) {
98798f48 193 flags |= RTL8187_TX_FLAG_RTS;
e039fa4a 194 flags |= ieee80211_get_rts_cts_rate(dev, info)->hw_value << 19;
32bfd35d 195 rts_dur = ieee80211_rts_duration(dev, priv->vif,
e039fa4a
JB		 196 skb->len, info);
197 } else if (info->flags & IEEE80211_TX_CTL_USE_CTS_PROTECT) {
98798f48 198 flags |= RTL8187_TX_FLAG_CTS;
e039fa4a 199 flags |= ieee80211_get_rts_cts_rate(dev, info)->hw_value << 19;
aa68cbfb 200 }
98798f48 201
6f7853f3
HTL		 202 if (!priv->is_rtl8187b) {
203 struct rtl8187_tx_hdr *hdr =
204 (struct rtl8187_tx_hdr *)skb_push(skb, sizeof(*hdr));
205 hdr->flags = cpu_to_le32(flags);
206 hdr->len = 0;
207 hdr->rts_duration = rts_dur;
208 hdr->retry = cpu_to_le32(info->control.retry_limit << 8);
209 buf = hdr;
210
211 ep = 2;
212 } else {
213 /* fc needs to be calculated before skb_push() */
214 unsigned int epmap[4] = { 6, 7, 5, 4 };
215 struct ieee80211_hdr *tx_hdr =
216 (struct ieee80211_hdr *)(skb->data);
217 u16 fc = le16_to_cpu(tx_hdr->frame_control);
218
219 struct rtl8187b_tx_hdr *hdr =
220 (struct rtl8187b_tx_hdr *)skb_push(skb, sizeof(*hdr));
221 struct ieee80211_rate *txrate =
222 ieee80211_get_tx_rate(dev, info);
223 memset(hdr, 0, sizeof(*hdr));
224 hdr->flags = cpu_to_le32(flags);
225 hdr->rts_duration = rts_dur;
226 hdr->retry = cpu_to_le32(info->control.retry_limit << 8);
227 hdr->tx_duration =
228 ieee80211_generic_frame_duration(dev, priv->vif,
229 skb->len, txrate);
230 buf = hdr;
231
232 if ((fc & IEEE80211_FCTL_FTYPE) == IEEE80211_FTYPE_MGMT)
233 ep = 12;
234 else
235 ep = epmap[skb_get_queue_mapping(skb)];
236 }
605bebe2 237
1f690d7b
LF		 238 /* FIXME: The sequence that follows is needed for this driver to
239 * work with mac80211 since "mac80211: fix TX sequence numbers".
240 * As with the temporary code in rt2x00, changes will be needed
241 * to get proper sequence numbers on beacons. In addition, this
242 * patch places the sequence number in the hardware state, which
243 * limits us to a single virtual state.
244 */
245 if (info->flags & IEEE80211_TX_CTL_ASSIGN_SEQ) {
246 if (info->flags & IEEE80211_TX_CTL_FIRST_FRAGMENT)
247 priv->seqno += 0x10;
248 ieee80211hdr->seq_ctrl &= cpu_to_le16(IEEE80211_SCTL_FRAG);
249 ieee80211hdr->seq_ctrl |= cpu_to_le16(priv->seqno);
250 }
251
e039fa4a
JB		 252 info->driver_data[0] = dev;
253 info->driver_data[1] = urb;
6f7853f3
HTL		 254
255 usb_fill_bulk_urb(urb, priv->udev, usb_sndbulkpipe(priv->udev, ep),
256 buf, skb->len, rtl8187_tx_cb, skb);
ea8ee240
ON		 257 rc = usb_submit_urb(urb, GFP_ATOMIC);
258 if (rc < 0) {
259 usb_free_urb(urb);
260 kfree_skb(skb);
261 }
605bebe2
MW		 262
263 return 0;
264}
265
266static void rtl8187_rx_cb(struct urb *urb)
267{
268 struct sk_buff *skb = (struct sk_buff *)urb->context;
269 struct rtl8187_rx_info *info = (struct rtl8187_rx_info *)skb->cb;
270 struct ieee80211_hw *dev = info->dev;
271 struct rtl8187_priv *priv = dev->priv;
605bebe2
MW		 272 struct ieee80211_rx_status rx_status = { 0 };
273 int rate, signal;
4150c572 274 u32 flags;
605bebe2
MW		 275
276 spin_lock(&priv->rx_queue.lock);
277 if (skb->next)
278 __skb_unlink(skb, &priv->rx_queue);
279 else {
280 spin_unlock(&priv->rx_queue.lock);
281 return;
282 }
283 spin_unlock(&priv->rx_queue.lock);
284
285 if (unlikely(urb->status)) {
286 usb_free_urb(urb);
287 dev_kfree_skb_irq(skb);
288 return;
289 }
290
291 skb_put(skb, urb->actual_length);
6f7853f3
HTL		 292 if (!priv->is_rtl8187b) {
293 struct rtl8187_rx_hdr *hdr =
294 (typeof(hdr))(skb_tail_pointer(skb) - sizeof(*hdr));
295 flags = le32_to_cpu(hdr->flags);
296 signal = hdr->signal & 0x7f;
297 rx_status.antenna = (hdr->signal >> 7) & 1;
298 rx_status.signal = signal;
299 rx_status.noise = hdr->noise;
300 rx_status.mactime = le64_to_cpu(hdr->mac_time);
301 priv->signal = signal;
302 priv->quality = signal;
303 priv->noise = hdr->noise;
304 } else {
305 struct rtl8187b_rx_hdr *hdr =
306 (typeof(hdr))(skb_tail_pointer(skb) - sizeof(*hdr));
307 flags = le32_to_cpu(hdr->flags);
308 signal = hdr->agc >> 1;
309 rx_status.antenna = (hdr->signal >> 7) & 1;
310 rx_status.signal = 64 - min(hdr->noise, (u8)64);
311 rx_status.noise = hdr->noise;
312 rx_status.mactime = le64_to_cpu(hdr->mac_time);
313 priv->signal = hdr->signal;
314 priv->quality = hdr->agc >> 1;
315 priv->noise = hdr->noise;
316 }
605bebe2 317
6f7853f3 318 skb_trim(skb, flags & 0x0FFF);
4150c572 319 rate = (flags >> 20) & 0xF;
605bebe2
MW		 320 if (rate > 3) { /* OFDM rate */
321 if (signal > 90)
322 signal = 90;
323 else if (signal < 25)
324 signal = 25;
325 signal = 90 - signal;
326 } else { /* CCK rate */
327 if (signal > 95)
328 signal = 95;
329 else if (signal < 30)
330 signal = 30;
331 signal = 95 - signal;
332 }
333
6f7853f3 334 rx_status.qual = priv->quality;
566bfe5a 335 rx_status.signal = signal;
8318d78a
JB		 336 rx_status.rate_idx = rate;
337 rx_status.freq = dev->conf.channel->center_freq;
338 rx_status.band = dev->conf.channel->band;
03bffc13 339 rx_status.flag |= RX_FLAG_TSFT;
4150c572
JB		 340 if (flags & (1 << 13))
341 rx_status.flag |= RX_FLAG_FAILED_FCS_CRC;
605bebe2
MW		 342 ieee80211_rx_irqsafe(dev, skb, &rx_status);
343
344 skb = dev_alloc_skb(RTL8187_MAX_RX);
345 if (unlikely(!skb)) {
346 usb_free_urb(urb);
347 /* TODO check rx queue length and refill *somewhere* */
348 return;
349 }
350
351 info = (struct rtl8187_rx_info *)skb->cb;
352 info->urb = urb;
353 info->dev = dev;
354 urb->transfer_buffer = skb_tail_pointer(skb);
355 urb->context = skb;
356 skb_queue_tail(&priv->rx_queue, skb);
357
358 usb_submit_urb(urb, GFP_ATOMIC);
359}
360
361static int rtl8187_init_urbs(struct ieee80211_hw *dev)
362{
363 struct rtl8187_priv *priv = dev->priv;
364 struct urb *entry;
365 struct sk_buff *skb;
366 struct rtl8187_rx_info *info;
367
368 while (skb_queue_len(&priv->rx_queue) < 8) {
369 skb = __dev_alloc_skb(RTL8187_MAX_RX, GFP_KERNEL);
370 if (!skb)
371 break;
372 entry = usb_alloc_urb(0, GFP_KERNEL);
373 if (!entry) {
374 kfree_skb(skb);
375 break;
376 }
377 usb_fill_bulk_urb(entry, priv->udev,
6f7853f3
HTL		 378 usb_rcvbulkpipe(priv->udev,
379 priv->is_rtl8187b ? 3 : 1),
605bebe2
MW		 380 skb_tail_pointer(skb),
381 RTL8187_MAX_RX, rtl8187_rx_cb, skb);
382 info = (struct rtl8187_rx_info *)skb->cb;
383 info->urb = entry;
384 info->dev = dev;
385 skb_queue_tail(&priv->rx_queue, skb);
386 usb_submit_urb(entry, GFP_KERNEL);
387 }
388
389 return 0;
390}
391
f8a08c34 392static int rtl8187_cmd_reset(struct ieee80211_hw *dev)
605bebe2
MW		 393{
394 struct rtl8187_priv *priv = dev->priv;
395 u8 reg;
396 int i;
397
605bebe2
MW		 398 reg = rtl818x_ioread8(priv, &priv->map->CMD);
399 reg &= (1 << 1);
400 reg |= RTL818X_CMD_RESET;
401 rtl818x_iowrite8(priv, &priv->map->CMD, reg);
402
403 i = 10;
404 do {
405 msleep(2);
406 if (!(rtl818x_ioread8(priv, &priv->map->CMD) &
407 RTL818X_CMD_RESET))
408 break;
409 } while (--i);
410
411 if (!i) {
412 printk(KERN_ERR "%s: Reset timeout!\n", wiphy_name(dev->wiphy));
413 return -ETIMEDOUT;
414 }
415
416 /* reload registers from eeprom */
417 rtl818x_iowrite8(priv, &priv->map->EEPROM_CMD, RTL818X_EEPROM_CMD_LOAD);
418
419 i = 10;
420 do {
421 msleep(4);
422 if (!(rtl818x_ioread8(priv, &priv->map->EEPROM_CMD) &
423 RTL818X_EEPROM_CMD_CONFIG))
424 break;
425 } while (--i);
426
427 if (!i) {
428 printk(KERN_ERR "%s: eeprom reset timeout!\n",
429 wiphy_name(dev->wiphy));
430 return -ETIMEDOUT;
431 }
432
f8a08c34
HTL		 433 return 0;
434}
435
436static int rtl8187_init_hw(struct ieee80211_hw *dev)
437{
438 struct rtl8187_priv *priv = dev->priv;
439 u8 reg;
440 int res;
441
442 /* reset */
443 rtl818x_iowrite8(priv, &priv->map->EEPROM_CMD,
444 RTL818X_EEPROM_CMD_CONFIG);
445 reg = rtl818x_ioread8(priv, &priv->map->CONFIG3);
446 rtl818x_iowrite8(priv, &priv->map->CONFIG3, reg |
447 RTL818X_CONFIG3_ANAPARAM_WRITE);
4ece16a1
HRK		 448 rtl818x_iowrite32(priv, &priv->map->ANAPARAM,
449 RTL8187_RTL8225_ANAPARAM_ON);
450 rtl818x_iowrite32(priv, &priv->map->ANAPARAM2,
451 RTL8187_RTL8225_ANAPARAM2_ON);
f8a08c34
HTL		 452 rtl818x_iowrite8(priv, &priv->map->CONFIG3, reg &
453 ~RTL818X_CONFIG3_ANAPARAM_WRITE);
454 rtl818x_iowrite8(priv, &priv->map->EEPROM_CMD,
455 RTL818X_EEPROM_CMD_NORMAL);
456
457 rtl818x_iowrite16(priv, &priv->map->INT_MASK, 0);
458
459 msleep(200);
460 rtl818x_iowrite8(priv, (u8 *)0xFE18, 0x10);
461 rtl818x_iowrite8(priv, (u8 *)0xFE18, 0x11);
462 rtl818x_iowrite8(priv, (u8 *)0xFE18, 0x00);
463 msleep(200);
464
465 res = rtl8187_cmd_reset(dev);
466 if (res)
467 return res;
468
605bebe2
MW		 469 rtl818x_iowrite8(priv, &priv->map->EEPROM_CMD, RTL818X_EEPROM_CMD_CONFIG);
470 reg = rtl818x_ioread8(priv, &priv->map->CONFIG3);
f8a08c34
HTL		 471 rtl818x_iowrite8(priv, &priv->map->CONFIG3,
472 reg | RTL818X_CONFIG3_ANAPARAM_WRITE);
4ece16a1
HRK		 473 rtl818x_iowrite32(priv, &priv->map->ANAPARAM,
474 RTL8187_RTL8225_ANAPARAM_ON);
475 rtl818x_iowrite32(priv, &priv->map->ANAPARAM2,
476 RTL8187_RTL8225_ANAPARAM2_ON);
f8a08c34
HTL		 477 rtl818x_iowrite8(priv, &priv->map->CONFIG3,
478 reg & ~RTL818X_CONFIG3_ANAPARAM_WRITE);
605bebe2
MW		 479 rtl818x_iowrite8(priv, &priv->map->EEPROM_CMD, RTL818X_EEPROM_CMD_NORMAL);
480
481 /* setup card */
482 rtl818x_iowrite16(priv, &priv->map->RFPinsSelect, 0);
483 rtl818x_iowrite8(priv, &priv->map->GPIO, 0);
484
485 rtl818x_iowrite16(priv, &priv->map->RFPinsSelect, (4 << 8));
486 rtl818x_iowrite8(priv, &priv->map->GPIO, 1);
487 rtl818x_iowrite8(priv, &priv->map->GP_ENABLE, 0);
488
489 rtl818x_iowrite8(priv, &priv->map->EEPROM_CMD, RTL818X_EEPROM_CMD_CONFIG);
605bebe2
MW		 490
491 rtl818x_iowrite16(priv, (__le16 *)0xFFF4, 0xFFFF);
492 reg = rtl818x_ioread8(priv, &priv->map->CONFIG1);
493 reg &= 0x3F;
494 reg |= 0x80;
495 rtl818x_iowrite8(priv, &priv->map->CONFIG1, reg);
496
497 rtl818x_iowrite8(priv, &priv->map->EEPROM_CMD, RTL818X_EEPROM_CMD_NORMAL);
498
499 rtl818x_iowrite32(priv, &priv->map->INT_TIMEOUT, 0);
500 rtl818x_iowrite8(priv, &priv->map->WPA_CONF, 0);
501 rtl818x_iowrite8(priv, &priv->map->RATE_FALLBACK, 0x81);
502
503 // TODO: set RESP_RATE and BRSR properly
504 rtl818x_iowrite8(priv, &priv->map->RESP_RATE, (8 << 4) | 0);
505 rtl818x_iowrite16(priv, &priv->map->BRSR, 0x01F3);
506
507 /* host_usb_init */
508 rtl818x_iowrite16(priv, &priv->map->RFPinsSelect, 0);
509 rtl818x_iowrite8(priv, &priv->map->GPIO, 0);
510 reg = rtl818x_ioread8(priv, (u8 *)0xFE53);
511 rtl818x_iowrite8(priv, (u8 *)0xFE53, reg | (1 << 7));
512 rtl818x_iowrite16(priv, &priv->map->RFPinsSelect, (4 << 8));
513 rtl818x_iowrite8(priv, &priv->map->GPIO, 0x20);
514 rtl818x_iowrite8(priv, &priv->map->GP_ENABLE, 0);
515 rtl818x_iowrite16(priv, &priv->map->RFPinsOutput, 0x80);
516 rtl818x_iowrite16(priv, &priv->map->RFPinsSelect, 0x80);
517 rtl818x_iowrite16(priv, &priv->map->RFPinsEnable, 0x80);
518 msleep(100);
519
520 rtl818x_iowrite32(priv, &priv->map->RF_TIMING, 0x000a8008);
521 rtl818x_iowrite16(priv, &priv->map->BRSR, 0xFFFF);
522 rtl818x_iowrite32(priv, &priv->map->RF_PARA, 0x00100044);
f8a08c34
HTL		 523 rtl818x_iowrite8(priv, &priv->map->EEPROM_CMD,
524 RTL818X_EEPROM_CMD_CONFIG);
605bebe2 525 rtl818x_iowrite8(priv, &priv->map->CONFIG3, 0x44);
f8a08c34
HTL		 526 rtl818x_iowrite8(priv, &priv->map->EEPROM_CMD,
527 RTL818X_EEPROM_CMD_NORMAL);
605bebe2
MW		 528 rtl818x_iowrite16(priv, &priv->map->RFPinsEnable, 0x1FF7);
529 msleep(100);
530
f6532111 531 priv->rf->init(dev);
605bebe2
MW		 532
533 rtl818x_iowrite16(priv, &priv->map->BRSR, 0x01F3);
f6532111
MW		 534 reg = rtl818x_ioread8(priv, &priv->map->PGSELECT) & ~1;
535 rtl818x_iowrite8(priv, &priv->map->PGSELECT, reg | 1);
605bebe2
MW		 536 rtl818x_iowrite16(priv, (__le16 *)0xFFFE, 0x10);
537 rtl818x_iowrite8(priv, &priv->map->TALLY_SEL, 0x80);
538 rtl818x_iowrite8(priv, (u8 *)0xFFFF, 0x60);
f6532111 539 rtl818x_iowrite8(priv, &priv->map->PGSELECT, reg);
605bebe2
MW		 540
541 return 0;
542}
543
f8a08c34
HTL		 544static const u8 rtl8187b_reg_table[][3] = {
545 {0xF0, 0x32, 0}, {0xF1, 0x32, 0}, {0xF2, 0x00, 0}, {0xF3, 0x00, 0},
546 {0xF4, 0x32, 0}, {0xF5, 0x43, 0}, {0xF6, 0x00, 0}, {0xF7, 0x00, 0},
547 {0xF8, 0x46, 0}, {0xF9, 0xA4, 0}, {0xFA, 0x00, 0}, {0xFB, 0x00, 0},
548 {0xFC, 0x96, 0}, {0xFD, 0xA4, 0}, {0xFE, 0x00, 0}, {0xFF, 0x00, 0},
549
550 {0x58, 0x4B, 1}, {0x59, 0x00, 1}, {0x5A, 0x4B, 1}, {0x5B, 0x00, 1},
551 {0x60, 0x4B, 1}, {0x61, 0x09, 1}, {0x62, 0x4B, 1}, {0x63, 0x09, 1},
552 {0xCE, 0x0F, 1}, {0xCF, 0x00, 1}, {0xE0, 0xFF, 1}, {0xE1, 0x0F, 1},
553 {0xE2, 0x00, 1}, {0xF0, 0x4E, 1}, {0xF1, 0x01, 1}, {0xF2, 0x02, 1},
554 {0xF3, 0x03, 1}, {0xF4, 0x04, 1}, {0xF5, 0x05, 1}, {0xF6, 0x06, 1},
555 {0xF7, 0x07, 1}, {0xF8, 0x08, 1},
556
557 {0x4E, 0x00, 2}, {0x0C, 0x04, 2}, {0x21, 0x61, 2}, {0x22, 0x68, 2},
558 {0x23, 0x6F, 2}, {0x24, 0x76, 2}, {0x25, 0x7D, 2}, {0x26, 0x84, 2},
559 {0x27, 0x8D, 2}, {0x4D, 0x08, 2}, {0x50, 0x05, 2}, {0x51, 0xF5, 2},
560 {0x52, 0x04, 2}, {0x53, 0xA0, 2}, {0x54, 0x1F, 2}, {0x55, 0x23, 2},
561 {0x56, 0x45, 2}, {0x57, 0x67, 2}, {0x58, 0x08, 2}, {0x59, 0x08, 2},
562 {0x5A, 0x08, 2}, {0x5B, 0x08, 2}, {0x60, 0x08, 2}, {0x61, 0x08, 2},
563 {0x62, 0x08, 2}, {0x63, 0x08, 2}, {0x64, 0xCF, 2}, {0x72, 0x56, 2},
564 {0x73, 0x9A, 2},
565
566 {0x34, 0xF0, 0}, {0x35, 0x0F, 0}, {0x5B, 0x40, 0}, {0x84, 0x88, 0},
567 {0x85, 0x24, 0}, {0x88, 0x54, 0}, {0x8B, 0xB8, 0}, {0x8C, 0x07, 0},
568 {0x8D, 0x00, 0}, {0x94, 0x1B, 0}, {0x95, 0x12, 0}, {0x96, 0x00, 0},
569 {0x97, 0x06, 0}, {0x9D, 0x1A, 0}, {0x9F, 0x10, 0}, {0xB4, 0x22, 0},
570 {0xBE, 0x80, 0}, {0xDB, 0x00, 0}, {0xEE, 0x00, 0}, {0x91, 0x03, 0},
571
572 {0x4C, 0x00, 2}, {0x9F, 0x00, 3}, {0x8C, 0x01, 0}, {0x8D, 0x10, 0},
573 {0x8E, 0x08, 0}, {0x8F, 0x00, 0}
574};
575
576static int rtl8187b_init_hw(struct ieee80211_hw *dev)
577{
578 struct rtl8187_priv *priv = dev->priv;
579 int res, i;
580 u8 reg;
581
582 rtl818x_iowrite8(priv, &priv->map->EEPROM_CMD,
583 RTL818X_EEPROM_CMD_CONFIG);
584
585 reg = rtl818x_ioread8(priv, &priv->map->CONFIG3);
586 reg |= RTL818X_CONFIG3_ANAPARAM_WRITE | RTL818X_CONFIG3_GNT_SELECT;
587 rtl818x_iowrite8(priv, &priv->map->CONFIG3, reg);
4ece16a1
HRK		 588 rtl818x_iowrite32(priv, &priv->map->ANAPARAM2,
589 RTL8187B_RTL8225_ANAPARAM2_ON);
590 rtl818x_iowrite32(priv, &priv->map->ANAPARAM,
591 RTL8187B_RTL8225_ANAPARAM_ON);
592 rtl818x_iowrite8(priv, &priv->map->ANAPARAM3,
593 RTL8187B_RTL8225_ANAPARAM3_ON);
f8a08c34
HTL		 594
595 rtl818x_iowrite8(priv, (u8 *)0xFF61, 0x10);
596 reg = rtl818x_ioread8(priv, (u8 *)0xFF62);
597 rtl818x_iowrite8(priv, (u8 *)0xFF62, reg & ~(1 << 5));
598 rtl818x_iowrite8(priv, (u8 *)0xFF62, reg | (1 << 5));
599
600 reg = rtl818x_ioread8(priv, &priv->map->CONFIG3);
601 reg &= ~RTL818X_CONFIG3_ANAPARAM_WRITE;
602 rtl818x_iowrite8(priv, &priv->map->CONFIG3, reg);
603
604 rtl818x_iowrite8(priv, &priv->map->EEPROM_CMD,
605 RTL818X_EEPROM_CMD_NORMAL);
606
607 res = rtl8187_cmd_reset(dev);
608 if (res)
609 return res;
610
611 rtl818x_iowrite16(priv, (__le16 *)0xFF2D, 0x0FFF);
612 reg = rtl818x_ioread8(priv, &priv->map->CW_CONF);
613 reg |= RTL818X_CW_CONF_PERPACKET_RETRY_SHIFT;
614 rtl818x_iowrite8(priv, &priv->map->CW_CONF, reg);
615 reg = rtl818x_ioread8(priv, &priv->map->TX_AGC_CTL);
616 reg |= RTL818X_TX_AGC_CTL_PERPACKET_GAIN_SHIFT |
617 RTL818X_TX_AGC_CTL_PERPACKET_ANTSEL_SHIFT;
618 rtl818x_iowrite8(priv, &priv->map->TX_AGC_CTL, reg);
619
620 rtl818x_iowrite16_idx(priv, (__le16 *)0xFFE0, 0x0FFF, 1);
621 reg = rtl818x_ioread8(priv, &priv->map->RATE_FALLBACK);
622 reg |= RTL818X_RATE_FALLBACK_ENABLE;
623 rtl818x_iowrite8(priv, &priv->map->RATE_FALLBACK, reg);
624
625 rtl818x_iowrite16(priv, &priv->map->BEACON_INTERVAL, 100);
626 rtl818x_iowrite16(priv, &priv->map->ATIM_WND, 2);
627 rtl818x_iowrite16_idx(priv, (__le16 *)0xFFD4, 0xFFFF, 1);
628
629 rtl818x_iowrite8(priv, &priv->map->EEPROM_CMD,
630 RTL818X_EEPROM_CMD_CONFIG);
631 reg = rtl818x_ioread8(priv, &priv->map->CONFIG1);
632 rtl818x_iowrite8(priv, &priv->map->CONFIG1, (reg & 0x3F) | 0x80);
633 rtl818x_iowrite8(priv, &priv->map->EEPROM_CMD,
634 RTL818X_EEPROM_CMD_NORMAL);
635
636 rtl818x_iowrite8(priv, &priv->map->WPA_CONF, 0);
637 for (i = 0; i < ARRAY_SIZE(rtl8187b_reg_table); i++) {
638 rtl818x_iowrite8_idx(priv,
639 (u8 *)(uintptr_t)
640 (rtl8187b_reg_table[i][0] | 0xFF00),
641 rtl8187b_reg_table[i][1],
642 rtl8187b_reg_table[i][2]);
643 }
644
645 rtl818x_iowrite16(priv, &priv->map->TID_AC_MAP, 0xFA50);
646 rtl818x_iowrite16(priv, &priv->map->INT_MIG, 0);
647
648 rtl818x_iowrite32_idx(priv, (__le32 *)0xFFF0, 0, 1);
649 rtl818x_iowrite32_idx(priv, (__le32 *)0xFFF4, 0, 1);
650 rtl818x_iowrite8_idx(priv, (u8 *)0xFFF8, 0, 1);
651
652 rtl818x_iowrite32(priv, &priv->map->RF_TIMING, 0x00004001);
653
654 rtl818x_iowrite16_idx(priv, (__le16 *)0xFF72, 0x569A, 2);
655
656 rtl818x_iowrite8(priv, &priv->map->EEPROM_CMD,
657 RTL818X_EEPROM_CMD_CONFIG);
658 reg = rtl818x_ioread8(priv, &priv->map->CONFIG3);
659 reg |= RTL818X_CONFIG3_ANAPARAM_WRITE;
660 rtl818x_iowrite8(priv, &priv->map->CONFIG3, reg);
661 rtl818x_iowrite8(priv, &priv->map->EEPROM_CMD,
662 RTL818X_EEPROM_CMD_NORMAL);
663
664 rtl818x_iowrite16(priv, &priv->map->RFPinsOutput, 0x0480);
665 rtl818x_iowrite16(priv, &priv->map->RFPinsSelect, 0x2488);
666 rtl818x_iowrite16(priv, &priv->map->RFPinsEnable, 0x1FFF);
667 msleep(1100);
668
669 priv->rf->init(dev);
670
671 reg = RTL818X_CMD_TX_ENABLE | RTL818X_CMD_RX_ENABLE;
672 rtl818x_iowrite8(priv, &priv->map->CMD, reg);
673 rtl818x_iowrite16(priv, &priv->map->INT_MASK, 0xFFFF);
674
675 rtl818x_iowrite8(priv, (u8 *)0xFE41, 0xF4);
676 rtl818x_iowrite8(priv, (u8 *)0xFE40, 0x00);
677 rtl818x_iowrite8(priv, (u8 *)0xFE42, 0x00);
678 rtl818x_iowrite8(priv, (u8 *)0xFE42, 0x01);
679 rtl818x_iowrite8(priv, (u8 *)0xFE40, 0x0F);
680 rtl818x_iowrite8(priv, (u8 *)0xFE42, 0x00);
681 rtl818x_iowrite8(priv, (u8 *)0xFE42, 0x01);
682
683 reg = rtl818x_ioread8(priv, (u8 *)0xFFDB);
684 rtl818x_iowrite8(priv, (u8 *)0xFFDB, reg | (1 << 2));
685 rtl818x_iowrite16_idx(priv, (__le16 *)0xFF72, 0x59FA, 3);
686 rtl818x_iowrite16_idx(priv, (__le16 *)0xFF74, 0x59D2, 3);
687 rtl818x_iowrite16_idx(priv, (__le16 *)0xFF76, 0x59D2, 3);
688 rtl818x_iowrite16_idx(priv, (__le16 *)0xFF78, 0x19FA, 3);
689 rtl818x_iowrite16_idx(priv, (__le16 *)0xFF7A, 0x19FA, 3);
690 rtl818x_iowrite16_idx(priv, (__le16 *)0xFF7C, 0x00D0, 3);
691 rtl818x_iowrite8(priv, (u8 *)0xFF61, 0);
692 rtl818x_iowrite8_idx(priv, (u8 *)0xFF80, 0x0F, 1);
693 rtl818x_iowrite8_idx(priv, (u8 *)0xFF83, 0x03, 1);
694 rtl818x_iowrite8(priv, (u8 *)0xFFDA, 0x10);
695 rtl818x_iowrite8_idx(priv, (u8 *)0xFF4D, 0x08, 2);
696
697 rtl818x_iowrite32(priv, &priv->map->HSSI_PARA, 0x0600321B);
698
699 rtl818x_iowrite16_idx(priv, (__le16 *)0xFFEC, 0x0800, 1);
700
701 return 0;
702}
703
4150c572 704static int rtl8187_start(struct ieee80211_hw *dev)
605bebe2
MW		 705{
706 struct rtl8187_priv *priv = dev->priv;
707 u32 reg;
708 int ret;
709
f8a08c34
HTL		 710 ret = (!priv->is_rtl8187b) ? rtl8187_init_hw(dev) :
711 rtl8187b_init_hw(dev);
605bebe2
MW		 712 if (ret)
713 return ret;
714
f8a08c34
HTL		 715 if (priv->is_rtl8187b) {
716 reg = RTL818X_RX_CONF_MGMT |
717 RTL818X_RX_CONF_DATA |
718 RTL818X_RX_CONF_BROADCAST |
719 RTL818X_RX_CONF_NICMAC |
720 RTL818X_RX_CONF_BSSID |
721 (7 << 13 /* RX FIFO threshold NONE */) |
722 (7 << 10 /* MAX RX DMA */) |
723 RTL818X_RX_CONF_RX_AUTORESETPHY |
724 RTL818X_RX_CONF_ONLYERLPKT |
725 RTL818X_RX_CONF_MULTICAST;
726 priv->rx_conf = reg;
727 rtl818x_iowrite32(priv, &priv->map->RX_CONF, reg);
728
729 rtl818x_iowrite32(priv, &priv->map->TX_CONF,
730 RTL818X_TX_CONF_HW_SEQNUM |
731 RTL818X_TX_CONF_DISREQQSIZE |
732 (7 << 8 /* short retry limit */) |
733 (7 << 0 /* long retry limit */) |
734 (7 << 21 /* MAX TX DMA */));
735 rtl8187_init_urbs(dev);
736 return 0;
737 }
738
605bebe2
MW		 739 rtl818x_iowrite16(priv, &priv->map->INT_MASK, 0xFFFF);
740
2fe14263
MW		 741 rtl818x_iowrite32(priv, &priv->map->MAR[0], ~0);
742 rtl818x_iowrite32(priv, &priv->map->MAR[1], ~0);
743
605bebe2
MW		 744 rtl8187_init_urbs(dev);
745
746 reg = RTL818X_RX_CONF_ONLYERLPKT |
747 RTL818X_RX_CONF_RX_AUTORESETPHY |
748 RTL818X_RX_CONF_BSSID |
749 RTL818X_RX_CONF_MGMT |
605bebe2
MW		 750 RTL818X_RX_CONF_DATA |
751 (7 << 13 /* RX FIFO threshold NONE */) |
752 (7 << 10 /* MAX RX DMA */) |
753 RTL818X_RX_CONF_BROADCAST |
605bebe2 754 RTL818X_RX_CONF_NICMAC;
605bebe2 755
4150c572 756 priv->rx_conf = reg;
605bebe2
MW		 757 rtl818x_iowrite32(priv, &priv->map->RX_CONF, reg);
758
759 reg = rtl818x_ioread8(priv, &priv->map->CW_CONF);
760 reg &= ~RTL818X_CW_CONF_PERPACKET_CW_SHIFT;
761 reg |= RTL818X_CW_CONF_PERPACKET_RETRY_SHIFT;
762 rtl818x_iowrite8(priv, &priv->map->CW_CONF, reg);
763
764 reg = rtl818x_ioread8(priv, &priv->map->TX_AGC_CTL);
765 reg &= ~RTL818X_TX_AGC_CTL_PERPACKET_GAIN_SHIFT;
766 reg &= ~RTL818X_TX_AGC_CTL_PERPACKET_ANTSEL_SHIFT;
767 reg &= ~RTL818X_TX_AGC_CTL_FEEDBACK_ANT;
768 rtl818x_iowrite8(priv, &priv->map->TX_AGC_CTL, reg);
769
770 reg = RTL818X_TX_CONF_CW_MIN |
771 (7 << 21 /* MAX TX DMA */) |
772 RTL818X_TX_CONF_NO_ICV;
773 rtl818x_iowrite32(priv, &priv->map->TX_CONF, reg);
774
775 reg = rtl818x_ioread8(priv, &priv->map->CMD);
776 reg |= RTL818X_CMD_TX_ENABLE;
777 reg |= RTL818X_CMD_RX_ENABLE;
778 rtl818x_iowrite8(priv, &priv->map->CMD, reg);
779
780 return 0;
781}
782
4150c572 783static void rtl8187_stop(struct ieee80211_hw *dev)
605bebe2
MW		 784{
785 struct rtl8187_priv *priv = dev->priv;
786 struct rtl8187_rx_info *info;
787 struct sk_buff *skb;
788 u32 reg;
789
790 rtl818x_iowrite16(priv, &priv->map->INT_MASK, 0);
791
792 reg = rtl818x_ioread8(priv, &priv->map->CMD);
793 reg &= ~RTL818X_CMD_TX_ENABLE;
794 reg &= ~RTL818X_CMD_RX_ENABLE;
795 rtl818x_iowrite8(priv, &priv->map->CMD, reg);
796
f6532111 797 priv->rf->stop(dev);
605bebe2
MW		 798
799 rtl818x_iowrite8(priv, &priv->map->EEPROM_CMD, RTL818X_EEPROM_CMD_CONFIG);
800 reg = rtl818x_ioread8(priv, &priv->map->CONFIG4);
801 rtl818x_iowrite8(priv, &priv->map->CONFIG4, reg | RTL818X_CONFIG4_VCOOFF);
802 rtl818x_iowrite8(priv, &priv->map->EEPROM_CMD, RTL818X_EEPROM_CMD_NORMAL);
803
804 while ((skb = skb_dequeue(&priv->rx_queue))) {
805 info = (struct rtl8187_rx_info *)skb->cb;
806 usb_kill_urb(info->urb);
807 kfree_skb(skb);
808 }
4150c572 809 return;
605bebe2
MW		 810}
811
812static int rtl8187_add_interface(struct ieee80211_hw *dev,
813 struct ieee80211_if_init_conf *conf)
814{
815 struct rtl8187_priv *priv = dev->priv;
4150c572 816 int i;
605bebe2 817
4150c572
JB		 818 if (priv->mode != IEEE80211_IF_TYPE_MNTR)
819 return -EOPNOTSUPP;
605bebe2
MW		 820
821 switch (conf->type) {
822 case IEEE80211_IF_TYPE_STA:
605bebe2
MW		 823 priv->mode = conf->type;
824 break;
825 default:
826 return -EOPNOTSUPP;
827 }
828
aa979a6a
HRK		 829 priv->vif = conf->vif;
830
4150c572
JB		 831 rtl818x_iowrite8(priv, &priv->map->EEPROM_CMD, RTL818X_EEPROM_CMD_CONFIG);
832 for (i = 0; i < ETH_ALEN; i++)
833 rtl818x_iowrite8(priv, &priv->map->MAC[i],
834 ((u8 *)conf->mac_addr)[i]);
835 rtl818x_iowrite8(priv, &priv->map->EEPROM_CMD, RTL818X_EEPROM_CMD_NORMAL);
605bebe2
MW		 836
837 return 0;
838}
839
840static void rtl8187_remove_interface(struct ieee80211_hw *dev,
841 struct ieee80211_if_init_conf *conf)
842{
843 struct rtl8187_priv *priv = dev->priv;
4150c572 844 priv->mode = IEEE80211_IF_TYPE_MNTR;
aa979a6a 845 priv->vif = NULL;
605bebe2
MW		 846}
847
848static int rtl8187_config(struct ieee80211_hw *dev, struct ieee80211_conf *conf)
849{
850 struct rtl8187_priv *priv = dev->priv;
f6532111
MW		 851 u32 reg;
852
853 reg = rtl818x_ioread32(priv, &priv->map->TX_CONF);
854 /* Enable TX loopback on MAC level to avoid TX during channel
855 * changes, as this has be seen to causes problems and the
856 * card will stop work until next reset
857 */
858 rtl818x_iowrite32(priv, &priv->map->TX_CONF,
859 reg | RTL818X_TX_CONF_LOOPBACK_MAC);
860 msleep(10);
861 priv->rf->set_chan(dev, conf);
862 msleep(10);
863 rtl818x_iowrite32(priv, &priv->map->TX_CONF, reg);
605bebe2 864
6f7853f3
HTL		 865 if (!priv->is_rtl8187b) {
866 rtl818x_iowrite8(priv, &priv->map->SIFS, 0x22);
867
868 if (conf->flags & IEEE80211_CONF_SHORT_SLOT_TIME) {
869 rtl818x_iowrite8(priv, &priv->map->SLOT, 0x9);
870 rtl818x_iowrite8(priv, &priv->map->DIFS, 0x14);
871 rtl818x_iowrite8(priv, &priv->map->EIFS, 91 - 0x14);
872 rtl818x_iowrite8(priv, &priv->map->CW_VAL, 0x73);
873 } else {
874 rtl818x_iowrite8(priv, &priv->map->SLOT, 0x14);
875 rtl818x_iowrite8(priv, &priv->map->DIFS, 0x24);
876 rtl818x_iowrite8(priv, &priv->map->EIFS, 91 - 0x24);
877 rtl818x_iowrite8(priv, &priv->map->CW_VAL, 0xa5);
878 }
605bebe2
MW		 879 }
880
881 rtl818x_iowrite16(priv, &priv->map->ATIM_WND, 2);
882 rtl818x_iowrite16(priv, &priv->map->ATIMTR_INTERVAL, 100);
883 rtl818x_iowrite16(priv, &priv->map->BEACON_INTERVAL, 100);
884 rtl818x_iowrite16(priv, &priv->map->BEACON_INTERVAL_TIME, 100);
885 return 0;
886}
887
32bfd35d
JB		 888static int rtl8187_config_interface(struct ieee80211_hw *dev,
889 struct ieee80211_vif *vif,
605bebe2
MW		 890 struct ieee80211_if_conf *conf)
891{
892 struct rtl8187_priv *priv = dev->priv;
893 int i;
6f7853f3 894 u8 reg;
605bebe2
MW		 895
896 for (i = 0; i < ETH_ALEN; i++)
897 rtl818x_iowrite8(priv, &priv->map->BSSID[i], conf->bssid[i]);
898
6f7853f3
HTL		 899 if (is_valid_ether_addr(conf->bssid)) {
900 reg = RTL818X_MSR_INFRA;
901 if (priv->is_rtl8187b)
902 reg |= RTL818X_MSR_ENEDCA;
903 rtl818x_iowrite8(priv, &priv->map->MSR, reg);
904 } else {
905 reg = RTL818X_MSR_NO_LINK;
906 rtl818x_iowrite8(priv, &priv->map->MSR, reg);
907 }
605bebe2
MW		 908
909 return 0;
910}
911
4150c572
JB		 912static void rtl8187_configure_filter(struct ieee80211_hw *dev,
913 unsigned int changed_flags,
914 unsigned int *total_flags,
2fe14263 915 int mc_count, struct dev_addr_list *mclist)
4150c572
JB		 916{
917 struct rtl8187_priv *priv = dev->priv;
918
4150c572
JB		 919 if (changed_flags & FIF_FCSFAIL)
920 priv->rx_conf ^= RTL818X_RX_CONF_FCS;
921 if (changed_flags & FIF_CONTROL)
922 priv->rx_conf ^= RTL818X_RX_CONF_CTRL;
923 if (changed_flags & FIF_OTHER_BSS)
924 priv->rx_conf ^= RTL818X_RX_CONF_MONITOR;
2fe14263 925 if (*total_flags & FIF_ALLMULTI || mc_count > 0)
4150c572 926 priv->rx_conf |= RTL818X_RX_CONF_MULTICAST;
2fe14263
MW		 927 else
928 priv->rx_conf &= ~RTL818X_RX_CONF_MULTICAST;
929
930 *total_flags = 0;
4150c572 931
4150c572
JB		 932 if (priv->rx_conf & RTL818X_RX_CONF_FCS)
933 *total_flags |= FIF_FCSFAIL;
934 if (priv->rx_conf & RTL818X_RX_CONF_CTRL)
935 *total_flags |= FIF_CONTROL;
936 if (priv->rx_conf & RTL818X_RX_CONF_MONITOR)
937 *total_flags |= FIF_OTHER_BSS;
2fe14263
MW		 938 if (priv->rx_conf & RTL818X_RX_CONF_MULTICAST)
939 *total_flags |= FIF_ALLMULTI;
4150c572
JB		 940
941 rtl818x_iowrite32_async(priv, &priv->map->RX_CONF, priv->rx_conf);
942}
943
605bebe2
MW		 944static const struct ieee80211_ops rtl8187_ops = {
945 .tx = rtl8187_tx,
4150c572 946 .start = rtl8187_start,
605bebe2
MW		 947 .stop = rtl8187_stop,
948 .add_interface = rtl8187_add_interface,
949 .remove_interface = rtl8187_remove_interface,
950 .config = rtl8187_config,
951 .config_interface = rtl8187_config_interface,
4150c572 952 .configure_filter = rtl8187_configure_filter,
605bebe2
MW		 953};
954
955static void rtl8187_eeprom_register_read(struct eeprom_93cx6 *eeprom)
956{
957 struct ieee80211_hw *dev = eeprom->data;
958 struct rtl8187_priv *priv = dev->priv;
959 u8 reg = rtl818x_ioread8(priv, &priv->map->EEPROM_CMD);
960
961 eeprom->reg_data_in = reg & RTL818X_EEPROM_CMD_WRITE;
962 eeprom->reg_data_out = reg & RTL818X_EEPROM_CMD_READ;
963 eeprom->reg_data_clock = reg & RTL818X_EEPROM_CMD_CK;
964 eeprom->reg_chip_select = reg & RTL818X_EEPROM_CMD_CS;
965}
966
967static void rtl8187_eeprom_register_write(struct eeprom_93cx6 *eeprom)
968{
969 struct ieee80211_hw *dev = eeprom->data;
970 struct rtl8187_priv *priv = dev->priv;
971 u8 reg = RTL818X_EEPROM_CMD_PROGRAM;
972
973 if (eeprom->reg_data_in)
974 reg |= RTL818X_EEPROM_CMD_WRITE;
975 if (eeprom->reg_data_out)
976 reg |= RTL818X_EEPROM_CMD_READ;
977 if (eeprom->reg_data_clock)
978 reg |= RTL818X_EEPROM_CMD_CK;
979 if (eeprom->reg_chip_select)
980 reg |= RTL818X_EEPROM_CMD_CS;
981
982 rtl818x_iowrite8(priv, &priv->map->EEPROM_CMD, reg);
983 udelay(10);
984}
985
986static int __devinit rtl8187_probe(struct usb_interface *intf,
987 const struct usb_device_id *id)
988{
989 struct usb_device *udev = interface_to_usbdev(intf);
990 struct ieee80211_hw *dev;
991 struct rtl8187_priv *priv;
992 struct eeprom_93cx6 eeprom;
993 struct ieee80211_channel *channel;
6f7853f3 994 const char *chip_name;
605bebe2
MW		 995 u16 txpwr, reg;
996 int err, i;
0795af57 997 DECLARE_MAC_BUF(mac);
605bebe2
MW		 998
999 dev = ieee80211_alloc_hw(sizeof(*priv), &rtl8187_ops);
1000 if (!dev) {
1001 printk(KERN_ERR "rtl8187: ieee80211 alloc failed\n");
1002 return -ENOMEM;
1003 }
1004
1005 priv = dev->priv;
0e25b4ef 1006 priv->is_rtl8187b = (id->driver_info == DEVICE_RTL8187B);
605bebe2
MW		 1007
1008 SET_IEEE80211_DEV(dev, &intf->dev);
1009 usb_set_intfdata(intf, dev);
1010 priv->udev = udev;
1011
1012 usb_get_dev(udev);
1013
1014 skb_queue_head_init(&priv->rx_queue);
8318d78a
JB		 1015
1016 BUILD_BUG_ON(sizeof(priv->channels) != sizeof(rtl818x_channels));
1017 BUILD_BUG_ON(sizeof(priv->rates) != sizeof(rtl818x_rates));
1018
605bebe2
MW		 1019 memcpy(priv->channels, rtl818x_channels, sizeof(rtl818x_channels));
1020 memcpy(priv->rates, rtl818x_rates, sizeof(rtl818x_rates));
1021 priv->map = (struct rtl818x_csr *)0xFF00;
8318d78a
JB		 1022
1023 priv->band.band = IEEE80211_BAND_2GHZ;
1024 priv->band.channels = priv->channels;
1025 priv->band.n_channels = ARRAY_SIZE(rtl818x_channels);
1026 priv->band.bitrates = priv->rates;
1027 priv->band.n_bitrates = ARRAY_SIZE(rtl818x_rates);
1028 dev->wiphy->bands[IEEE80211_BAND_2GHZ] = &priv->band;
1029
1030
4150c572 1031 priv->mode = IEEE80211_IF_TYPE_MNTR;
605bebe2 1032 dev->flags = IEEE80211_HW_HOST_BROADCAST_PS_BUFFERING |
566bfe5a
BR		 1033 IEEE80211_HW_RX_INCLUDES_FCS |
1034 IEEE80211_HW_SIGNAL_UNSPEC;
566bfe5a 1035 dev->max_signal = 65;
605bebe2 1036
605bebe2
MW		 1037 eeprom.data = dev;
1038 eeprom.register_read = rtl8187_eeprom_register_read;
1039 eeprom.register_write = rtl8187_eeprom_register_write;
1040 if (rtl818x_ioread32(priv, &priv->map->RX_CONF) & (1 << 6))
1041 eeprom.width = PCI_EEPROM_WIDTH_93C66;
1042 else
1043 eeprom.width = PCI_EEPROM_WIDTH_93C46;
1044
1045 rtl818x_iowrite8(priv, &priv->map->EEPROM_CMD, RTL818X_EEPROM_CMD_CONFIG);
1046 udelay(10);
1047
1048 eeprom_93cx6_multiread(&eeprom, RTL8187_EEPROM_MAC_ADDR,
1049 (__le16 __force *)dev->wiphy->perm_addr, 3);
1050 if (!is_valid_ether_addr(dev->wiphy->perm_addr)) {
1051 printk(KERN_WARNING "rtl8187: Invalid hwaddr! Using randomly "
1052 "generated MAC address\n");
1053 random_ether_addr(dev->wiphy->perm_addr);
1054 }
1055
1056 channel = priv->channels;
1057 for (i = 0; i < 3; i++) {
1058 eeprom_93cx6_read(&eeprom, RTL8187_EEPROM_TXPWR_CHAN_1 + i,
1059 &txpwr);
8318d78a
JB		 1060 (*channel++).hw_value = txpwr & 0xFF;
1061 (*channel++).hw_value = txpwr >> 8;
605bebe2
MW		 1062 }
1063 for (i = 0; i < 2; i++) {
1064 eeprom_93cx6_read(&eeprom, RTL8187_EEPROM_TXPWR_CHAN_4 + i,
1065 &txpwr);
8318d78a
JB		 1066 (*channel++).hw_value = txpwr & 0xFF;
1067 (*channel++).hw_value = txpwr >> 8;
605bebe2 1068 }
605bebe2
MW		 1069
1070 eeprom_93cx6_read(&eeprom, RTL8187_EEPROM_TXPWR_BASE,
1071 &priv->txpwr_base);
1072
f6532111
MW		 1073 reg = rtl818x_ioread8(priv, &priv->map->PGSELECT) & ~1;
1074 rtl818x_iowrite8(priv, &priv->map->PGSELECT, reg | 1);
605bebe2
MW		 1075 /* 0 means asic B-cut, we should use SW 3 wire
1076 * bit-by-bit banging for radio. 1 means we can use
1077 * USB specific request to write radio registers */
1078 priv->asic_rev = rtl818x_ioread8(priv, (u8 *)0xFFFE) & 0x3;
f6532111 1079 rtl818x_iowrite8(priv, &priv->map->PGSELECT, reg);
605bebe2
MW		 1080 rtl818x_iowrite8(priv, &priv->map->EEPROM_CMD, RTL818X_EEPROM_CMD_NORMAL);
1081
6f7853f3
HTL		 1082 if (!priv->is_rtl8187b) {
1083 u32 reg32;
1084 reg32 = rtl818x_ioread32(priv, &priv->map->TX_CONF);
1085 reg32 &= RTL818X_TX_CONF_HWVER_MASK;
1086 switch (reg32) {
0e25b4ef
LF		 1087 case RTL818X_TX_CONF_R8187vD_B:
1088 /* Some RTL8187B devices have a USB ID of 0x8187
1089 * detect them here */
1090 chip_name = "RTL8187BvB(early)";
1091 priv->is_rtl8187b = 1;
1092 priv->hw_rev = RTL8187BvB;
1093 break;
1094 case RTL818X_TX_CONF_R8187vD:
6f7853f3
HTL		 1095 chip_name = "RTL8187vD";
1096 break;
1097 default:
1098 chip_name = "RTL8187vB (default)";
1099 }
1100 } else {
6f7853f3
HTL		 1101 /*
1102 * Force USB request to write radio registers for 8187B, Realtek
1103 * only uses it in their sources
1104 */
1105 /*if (priv->asic_rev == 0) {
1106 printk(KERN_WARNING "rtl8187: Forcing use of USB "
1107 "requests to write to radio registers\n");
1108 priv->asic_rev = 1;
1109 }*/
1110 switch (rtl818x_ioread8(priv, (u8 *)0xFFE1)) {
1111 case RTL818X_R8187B_B:
1112 chip_name = "RTL8187BvB";
1113 priv->hw_rev = RTL8187BvB;
1114 break;
1115 case RTL818X_R8187B_D:
1116 chip_name = "RTL8187BvD";
1117 priv->hw_rev = RTL8187BvD;
1118 break;
1119 case RTL818X_R8187B_E:
1120 chip_name = "RTL8187BvE";
1121 priv->hw_rev = RTL8187BvE;
1122 break;
1123 default:
1124 chip_name = "RTL8187BvB (default)";
1125 priv->hw_rev = RTL8187BvB;
1126 }
1127 }
1128
0e25b4ef
LF		 1129 if (!priv->is_rtl8187b) {
1130 for (i = 0; i < 2; i++) {
1131 eeprom_93cx6_read(&eeprom,
1132 RTL8187_EEPROM_TXPWR_CHAN_6 + i,
1133 &txpwr);
1134 (*channel++).hw_value = txpwr & 0xFF;
1135 (*channel++).hw_value = txpwr >> 8;
1136 }
1137 } else {
1138 eeprom_93cx6_read(&eeprom, RTL8187_EEPROM_TXPWR_CHAN_6,
1139 &txpwr);
1140 (*channel++).hw_value = txpwr & 0xFF;
1141
1142 eeprom_93cx6_read(&eeprom, 0x0A, &txpwr);
1143 (*channel++).hw_value = txpwr & 0xFF;
1144
1145 eeprom_93cx6_read(&eeprom, 0x1C, &txpwr);
1146 (*channel++).hw_value = txpwr & 0xFF;
1147 (*channel++).hw_value = txpwr >> 8;
1148 }
1149
1150 if (priv->is_rtl8187b)
1151 printk(KERN_WARNING "rtl8187: 8187B chip detected. Support "
1152 "is EXPERIMENTAL, and could damage your\n"
1153 " hardware, use at your own risk\n");
1154 if ((id->driver_info == DEVICE_RTL8187) && priv->is_rtl8187b)
1155 printk(KERN_INFO "rtl8187: inconsistency between id with OEM"
1156 " info!\n");
1157
f6532111 1158 priv->rf = rtl8187_detect_rf(dev);
0e25b4ef
LF		 1159 dev->extra_tx_headroom = (!priv->is_rtl8187b) ?
1160 sizeof(struct rtl8187_tx_hdr) :
1161 sizeof(struct rtl8187b_tx_hdr);
1162 if (!priv->is_rtl8187b)
1163 dev->queues = 1;
1164 else
1165 dev->queues = 4;
605bebe2
MW		 1166
1167 err = ieee80211_register_hw(dev);
1168 if (err) {
1169 printk(KERN_ERR "rtl8187: Cannot register device\n");
1170 goto err_free_dev;
1171 }
1172
6f7853f3 1173 printk(KERN_INFO "%s: hwaddr %s, %s V%d + %s\n",
0795af57 1174 wiphy_name(dev->wiphy), print_mac(mac, dev->wiphy->perm_addr),
6f7853f3 1175 chip_name, priv->asic_rev, priv->rf->name);
605bebe2
MW		 1176
1177 return 0;
1178
1179 err_free_dev:
1180 ieee80211_free_hw(dev);
1181 usb_set_intfdata(intf, NULL);
1182 usb_put_dev(udev);
1183 return err;
1184}
1185
1186static void __devexit rtl8187_disconnect(struct usb_interface *intf)
1187{
1188 struct ieee80211_hw *dev = usb_get_intfdata(intf);
1189 struct rtl8187_priv *priv;
1190
1191 if (!dev)
1192 return;
1193
1194 ieee80211_unregister_hw(dev);
1195
1196 priv = dev->priv;
1197 usb_put_dev(interface_to_usbdev(intf));
1198 ieee80211_free_hw(dev);
1199}
1200
1201static struct usb_driver rtl8187_driver = {
1202 .name = KBUILD_MODNAME,
1203 .id_table = rtl8187_table,
1204 .probe = rtl8187_probe,
500c1197 1205 .disconnect = __devexit_p(rtl8187_disconnect),
605bebe2
MW		 1206};
1207
1208static int __init rtl8187_init(void)
1209{
1210 return usb_register(&rtl8187_driver);
1211}
1212
1213static void __exit rtl8187_exit(void)
1214{
1215 usb_deregister(&rtl8187_driver);
1216}
1217
1218module_init(rtl8187_init);
1219module_exit(rtl8187_exit);
Linux kernel - Deliverables
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