Commit | Line | Data |
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605bebe2 MW |
1 | /* |
2 | * Linux device driver for RTL8187 | |
3 | * | |
4 | * Copyright 2007 Michael Wu <flamingice@sourmilk.net> | |
5 | * Copyright 2007 Andrea Merello <andreamrl@tiscali.it> | |
6 | * | |
7 | * Based on the r8187 driver, which is: | |
8 | * Copyright 2005 Andrea Merello <andreamrl@tiscali.it>, et al. | |
9 | * | |
0aec00ae JL |
10 | * Magic delays and register offsets below are taken from the original |
11 | * r8187 driver sources. Thanks to Realtek for their support! | |
605bebe2 MW |
12 | * |
13 | * This program is free software; you can redistribute it and/or modify | |
14 | * it under the terms of the GNU General Public License version 2 as | |
15 | * published by the Free Software Foundation. | |
16 | */ | |
17 | ||
18 | #include <linux/init.h> | |
19 | #include <linux/usb.h> | |
20 | #include <linux/delay.h> | |
21 | #include <linux/etherdevice.h> | |
22 | #include <linux/eeprom_93cx6.h> | |
23 | #include <net/mac80211.h> | |
24 | ||
25 | #include "rtl8187.h" | |
26 | #include "rtl8187_rtl8225.h" | |
27 | ||
28 | MODULE_AUTHOR("Michael Wu <flamingice@sourmilk.net>"); | |
29 | MODULE_AUTHOR("Andrea Merello <andreamrl@tiscali.it>"); | |
f8a08c34 | 30 | MODULE_DESCRIPTION("RTL8187/RTL8187B USB wireless driver"); |
605bebe2 MW |
31 | MODULE_LICENSE("GPL"); |
32 | ||
33 | static struct usb_device_id rtl8187_table[] __devinitdata = { | |
34 | /* Realtek */ | |
f8a08c34 HTL |
35 | {USB_DEVICE(0x0bda, 0x8187), .driver_info = DEVICE_RTL8187}, |
36 | {USB_DEVICE(0x0bda, 0x8189), .driver_info = DEVICE_RTL8187B}, | |
37 | {USB_DEVICE(0x0bda, 0x8197), .driver_info = DEVICE_RTL8187B}, | |
605bebe2 | 38 | /* Netgear */ |
f8a08c34 HTL |
39 | {USB_DEVICE(0x0846, 0x6100), .driver_info = DEVICE_RTL8187}, |
40 | {USB_DEVICE(0x0846, 0x6a00), .driver_info = DEVICE_RTL8187}, | |
c3cf60a9 | 41 | /* HP */ |
f8a08c34 | 42 | {USB_DEVICE(0x03f0, 0xca02), .driver_info = DEVICE_RTL8187}, |
9934550d | 43 | /* Sitecom */ |
f8a08c34 | 44 | {USB_DEVICE(0x0df6, 0x000d), .driver_info = DEVICE_RTL8187}, |
605bebe2 MW |
45 | {} |
46 | }; | |
47 | ||
48 | MODULE_DEVICE_TABLE(usb, rtl8187_table); | |
49 | ||
8318d78a JB |
50 | static const struct ieee80211_rate rtl818x_rates[] = { |
51 | { .bitrate = 10, .hw_value = 0, }, | |
52 | { .bitrate = 20, .hw_value = 1, }, | |
53 | { .bitrate = 55, .hw_value = 2, }, | |
54 | { .bitrate = 110, .hw_value = 3, }, | |
55 | { .bitrate = 60, .hw_value = 4, }, | |
56 | { .bitrate = 90, .hw_value = 5, }, | |
57 | { .bitrate = 120, .hw_value = 6, }, | |
58 | { .bitrate = 180, .hw_value = 7, }, | |
59 | { .bitrate = 240, .hw_value = 8, }, | |
60 | { .bitrate = 360, .hw_value = 9, }, | |
61 | { .bitrate = 480, .hw_value = 10, }, | |
62 | { .bitrate = 540, .hw_value = 11, }, | |
63 | }; | |
64 | ||
65 | static const struct ieee80211_channel rtl818x_channels[] = { | |
66 | { .center_freq = 2412 }, | |
67 | { .center_freq = 2417 }, | |
68 | { .center_freq = 2422 }, | |
69 | { .center_freq = 2427 }, | |
70 | { .center_freq = 2432 }, | |
71 | { .center_freq = 2437 }, | |
72 | { .center_freq = 2442 }, | |
73 | { .center_freq = 2447 }, | |
74 | { .center_freq = 2452 }, | |
75 | { .center_freq = 2457 }, | |
76 | { .center_freq = 2462 }, | |
77 | { .center_freq = 2467 }, | |
78 | { .center_freq = 2472 }, | |
79 | { .center_freq = 2484 }, | |
80 | }; | |
81 | ||
4150c572 JB |
82 | static void rtl8187_iowrite_async_cb(struct urb *urb) |
83 | { | |
84 | kfree(urb->context); | |
85 | usb_free_urb(urb); | |
86 | } | |
87 | ||
88 | static void rtl8187_iowrite_async(struct rtl8187_priv *priv, __le16 addr, | |
89 | void *data, u16 len) | |
90 | { | |
91 | struct usb_ctrlrequest *dr; | |
92 | struct urb *urb; | |
93 | struct rtl8187_async_write_data { | |
94 | u8 data[4]; | |
95 | struct usb_ctrlrequest dr; | |
96 | } *buf; | |
ea8ee240 | 97 | int rc; |
4150c572 JB |
98 | |
99 | buf = kmalloc(sizeof(*buf), GFP_ATOMIC); | |
100 | if (!buf) | |
101 | return; | |
102 | ||
103 | urb = usb_alloc_urb(0, GFP_ATOMIC); | |
104 | if (!urb) { | |
105 | kfree(buf); | |
106 | return; | |
107 | } | |
108 | ||
109 | dr = &buf->dr; | |
110 | ||
111 | dr->bRequestType = RTL8187_REQT_WRITE; | |
112 | dr->bRequest = RTL8187_REQ_SET_REG; | |
113 | dr->wValue = addr; | |
114 | dr->wIndex = 0; | |
115 | dr->wLength = cpu_to_le16(len); | |
116 | ||
117 | memcpy(buf, data, len); | |
118 | ||
119 | usb_fill_control_urb(urb, priv->udev, usb_sndctrlpipe(priv->udev, 0), | |
120 | (unsigned char *)dr, buf, len, | |
121 | rtl8187_iowrite_async_cb, buf); | |
ea8ee240 ON |
122 | rc = usb_submit_urb(urb, GFP_ATOMIC); |
123 | if (rc < 0) { | |
124 | kfree(buf); | |
125 | usb_free_urb(urb); | |
126 | } | |
4150c572 JB |
127 | } |
128 | ||
129 | static inline void rtl818x_iowrite32_async(struct rtl8187_priv *priv, | |
130 | __le32 *addr, u32 val) | |
131 | { | |
132 | __le32 buf = cpu_to_le32(val); | |
133 | ||
134 | rtl8187_iowrite_async(priv, cpu_to_le16((unsigned long)addr), | |
135 | &buf, sizeof(buf)); | |
136 | } | |
137 | ||
605bebe2 MW |
138 | void rtl8187_write_phy(struct ieee80211_hw *dev, u8 addr, u32 data) |
139 | { | |
140 | struct rtl8187_priv *priv = dev->priv; | |
141 | ||
142 | data <<= 8; | |
143 | data |= addr | 0x80; | |
144 | ||
145 | rtl818x_iowrite8(priv, &priv->map->PHY[3], (data >> 24) & 0xFF); | |
146 | rtl818x_iowrite8(priv, &priv->map->PHY[2], (data >> 16) & 0xFF); | |
147 | rtl818x_iowrite8(priv, &priv->map->PHY[1], (data >> 8) & 0xFF); | |
148 | rtl818x_iowrite8(priv, &priv->map->PHY[0], data & 0xFF); | |
149 | ||
150 | msleep(1); | |
151 | } | |
152 | ||
153 | static void rtl8187_tx_cb(struct urb *urb) | |
154 | { | |
605bebe2 | 155 | struct sk_buff *skb = (struct sk_buff *)urb->context; |
e039fa4a JB |
156 | struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb); |
157 | struct ieee80211_hw *hw = info->driver_data[0]; | |
6f7853f3 | 158 | struct rtl8187_priv *priv = hw->priv; |
605bebe2 | 159 | |
e039fa4a | 160 | usb_free_urb(info->driver_data[1]); |
6f7853f3 HTL |
161 | skb_pull(skb, priv->is_rtl8187b ? sizeof(struct rtl8187b_tx_hdr) : |
162 | sizeof(struct rtl8187_tx_hdr)); | |
e039fa4a JB |
163 | memset(&info->status, 0, sizeof(info->status)); |
164 | info->flags |= IEEE80211_TX_STAT_ACK; | |
165 | ieee80211_tx_status_irqsafe(hw, skb); | |
605bebe2 MW |
166 | } |
167 | ||
e039fa4a | 168 | static int rtl8187_tx(struct ieee80211_hw *dev, struct sk_buff *skb) |
605bebe2 MW |
169 | { |
170 | struct rtl8187_priv *priv = dev->priv; | |
e039fa4a | 171 | struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb); |
6f7853f3 HTL |
172 | unsigned int ep; |
173 | void *buf; | |
605bebe2 | 174 | struct urb *urb; |
98798f48 MW |
175 | __le16 rts_dur = 0; |
176 | u32 flags; | |
ea8ee240 | 177 | int rc; |
605bebe2 MW |
178 | |
179 | urb = usb_alloc_urb(0, GFP_ATOMIC); | |
180 | if (!urb) { | |
181 | kfree_skb(skb); | |
182 | return 0; | |
183 | } | |
184 | ||
98798f48 MW |
185 | flags = skb->len; |
186 | flags |= RTL8187_TX_FLAG_NO_ENCRYPT; | |
aa68cbfb | 187 | |
e039fa4a | 188 | flags |= ieee80211_get_tx_rate(dev, info)->hw_value << 24; |
8b7b1e05 | 189 | if (ieee80211_has_morefrags(((struct ieee80211_hdr *)skb->data)->frame_control)) |
98798f48 | 190 | flags |= RTL8187_TX_FLAG_MORE_FRAG; |
e039fa4a | 191 | if (info->flags & IEEE80211_TX_CTL_USE_RTS_CTS) { |
98798f48 | 192 | flags |= RTL8187_TX_FLAG_RTS; |
e039fa4a | 193 | flags |= ieee80211_get_rts_cts_rate(dev, info)->hw_value << 19; |
32bfd35d | 194 | rts_dur = ieee80211_rts_duration(dev, priv->vif, |
e039fa4a JB |
195 | skb->len, info); |
196 | } else if (info->flags & IEEE80211_TX_CTL_USE_CTS_PROTECT) { | |
98798f48 | 197 | flags |= RTL8187_TX_FLAG_CTS; |
e039fa4a | 198 | flags |= ieee80211_get_rts_cts_rate(dev, info)->hw_value << 19; |
aa68cbfb | 199 | } |
98798f48 | 200 | |
6f7853f3 HTL |
201 | if (!priv->is_rtl8187b) { |
202 | struct rtl8187_tx_hdr *hdr = | |
203 | (struct rtl8187_tx_hdr *)skb_push(skb, sizeof(*hdr)); | |
204 | hdr->flags = cpu_to_le32(flags); | |
205 | hdr->len = 0; | |
206 | hdr->rts_duration = rts_dur; | |
207 | hdr->retry = cpu_to_le32(info->control.retry_limit << 8); | |
208 | buf = hdr; | |
209 | ||
210 | ep = 2; | |
211 | } else { | |
212 | /* fc needs to be calculated before skb_push() */ | |
213 | unsigned int epmap[4] = { 6, 7, 5, 4 }; | |
214 | struct ieee80211_hdr *tx_hdr = | |
215 | (struct ieee80211_hdr *)(skb->data); | |
216 | u16 fc = le16_to_cpu(tx_hdr->frame_control); | |
217 | ||
218 | struct rtl8187b_tx_hdr *hdr = | |
219 | (struct rtl8187b_tx_hdr *)skb_push(skb, sizeof(*hdr)); | |
220 | struct ieee80211_rate *txrate = | |
221 | ieee80211_get_tx_rate(dev, info); | |
222 | memset(hdr, 0, sizeof(*hdr)); | |
223 | hdr->flags = cpu_to_le32(flags); | |
224 | hdr->rts_duration = rts_dur; | |
225 | hdr->retry = cpu_to_le32(info->control.retry_limit << 8); | |
226 | hdr->tx_duration = | |
227 | ieee80211_generic_frame_duration(dev, priv->vif, | |
228 | skb->len, txrate); | |
229 | buf = hdr; | |
230 | ||
231 | if ((fc & IEEE80211_FCTL_FTYPE) == IEEE80211_FTYPE_MGMT) | |
232 | ep = 12; | |
233 | else | |
234 | ep = epmap[skb_get_queue_mapping(skb)]; | |
235 | } | |
605bebe2 | 236 | |
e039fa4a JB |
237 | info->driver_data[0] = dev; |
238 | info->driver_data[1] = urb; | |
6f7853f3 HTL |
239 | |
240 | usb_fill_bulk_urb(urb, priv->udev, usb_sndbulkpipe(priv->udev, ep), | |
241 | buf, skb->len, rtl8187_tx_cb, skb); | |
ea8ee240 ON |
242 | rc = usb_submit_urb(urb, GFP_ATOMIC); |
243 | if (rc < 0) { | |
244 | usb_free_urb(urb); | |
245 | kfree_skb(skb); | |
246 | } | |
605bebe2 MW |
247 | |
248 | return 0; | |
249 | } | |
250 | ||
251 | static void rtl8187_rx_cb(struct urb *urb) | |
252 | { | |
253 | struct sk_buff *skb = (struct sk_buff *)urb->context; | |
254 | struct rtl8187_rx_info *info = (struct rtl8187_rx_info *)skb->cb; | |
255 | struct ieee80211_hw *dev = info->dev; | |
256 | struct rtl8187_priv *priv = dev->priv; | |
605bebe2 MW |
257 | struct ieee80211_rx_status rx_status = { 0 }; |
258 | int rate, signal; | |
4150c572 | 259 | u32 flags; |
605bebe2 MW |
260 | |
261 | spin_lock(&priv->rx_queue.lock); | |
262 | if (skb->next) | |
263 | __skb_unlink(skb, &priv->rx_queue); | |
264 | else { | |
265 | spin_unlock(&priv->rx_queue.lock); | |
266 | return; | |
267 | } | |
268 | spin_unlock(&priv->rx_queue.lock); | |
269 | ||
270 | if (unlikely(urb->status)) { | |
271 | usb_free_urb(urb); | |
272 | dev_kfree_skb_irq(skb); | |
273 | return; | |
274 | } | |
275 | ||
276 | skb_put(skb, urb->actual_length); | |
6f7853f3 HTL |
277 | if (!priv->is_rtl8187b) { |
278 | struct rtl8187_rx_hdr *hdr = | |
279 | (typeof(hdr))(skb_tail_pointer(skb) - sizeof(*hdr)); | |
280 | flags = le32_to_cpu(hdr->flags); | |
281 | signal = hdr->signal & 0x7f; | |
282 | rx_status.antenna = (hdr->signal >> 7) & 1; | |
283 | rx_status.signal = signal; | |
284 | rx_status.noise = hdr->noise; | |
285 | rx_status.mactime = le64_to_cpu(hdr->mac_time); | |
286 | priv->signal = signal; | |
287 | priv->quality = signal; | |
288 | priv->noise = hdr->noise; | |
289 | } else { | |
290 | struct rtl8187b_rx_hdr *hdr = | |
291 | (typeof(hdr))(skb_tail_pointer(skb) - sizeof(*hdr)); | |
292 | flags = le32_to_cpu(hdr->flags); | |
293 | signal = hdr->agc >> 1; | |
294 | rx_status.antenna = (hdr->signal >> 7) & 1; | |
295 | rx_status.signal = 64 - min(hdr->noise, (u8)64); | |
296 | rx_status.noise = hdr->noise; | |
297 | rx_status.mactime = le64_to_cpu(hdr->mac_time); | |
298 | priv->signal = hdr->signal; | |
299 | priv->quality = hdr->agc >> 1; | |
300 | priv->noise = hdr->noise; | |
301 | } | |
605bebe2 | 302 | |
6f7853f3 | 303 | skb_trim(skb, flags & 0x0FFF); |
4150c572 | 304 | rate = (flags >> 20) & 0xF; |
605bebe2 MW |
305 | if (rate > 3) { /* OFDM rate */ |
306 | if (signal > 90) | |
307 | signal = 90; | |
308 | else if (signal < 25) | |
309 | signal = 25; | |
310 | signal = 90 - signal; | |
311 | } else { /* CCK rate */ | |
312 | if (signal > 95) | |
313 | signal = 95; | |
314 | else if (signal < 30) | |
315 | signal = 30; | |
316 | signal = 95 - signal; | |
317 | } | |
318 | ||
6f7853f3 | 319 | rx_status.qual = priv->quality; |
566bfe5a | 320 | rx_status.signal = signal; |
8318d78a JB |
321 | rx_status.rate_idx = rate; |
322 | rx_status.freq = dev->conf.channel->center_freq; | |
323 | rx_status.band = dev->conf.channel->band; | |
03bffc13 | 324 | rx_status.flag |= RX_FLAG_TSFT; |
4150c572 JB |
325 | if (flags & (1 << 13)) |
326 | rx_status.flag |= RX_FLAG_FAILED_FCS_CRC; | |
605bebe2 MW |
327 | ieee80211_rx_irqsafe(dev, skb, &rx_status); |
328 | ||
329 | skb = dev_alloc_skb(RTL8187_MAX_RX); | |
330 | if (unlikely(!skb)) { | |
331 | usb_free_urb(urb); | |
332 | /* TODO check rx queue length and refill *somewhere* */ | |
333 | return; | |
334 | } | |
335 | ||
336 | info = (struct rtl8187_rx_info *)skb->cb; | |
337 | info->urb = urb; | |
338 | info->dev = dev; | |
339 | urb->transfer_buffer = skb_tail_pointer(skb); | |
340 | urb->context = skb; | |
341 | skb_queue_tail(&priv->rx_queue, skb); | |
342 | ||
343 | usb_submit_urb(urb, GFP_ATOMIC); | |
344 | } | |
345 | ||
346 | static int rtl8187_init_urbs(struct ieee80211_hw *dev) | |
347 | { | |
348 | struct rtl8187_priv *priv = dev->priv; | |
349 | struct urb *entry; | |
350 | struct sk_buff *skb; | |
351 | struct rtl8187_rx_info *info; | |
352 | ||
353 | while (skb_queue_len(&priv->rx_queue) < 8) { | |
354 | skb = __dev_alloc_skb(RTL8187_MAX_RX, GFP_KERNEL); | |
355 | if (!skb) | |
356 | break; | |
357 | entry = usb_alloc_urb(0, GFP_KERNEL); | |
358 | if (!entry) { | |
359 | kfree_skb(skb); | |
360 | break; | |
361 | } | |
362 | usb_fill_bulk_urb(entry, priv->udev, | |
6f7853f3 HTL |
363 | usb_rcvbulkpipe(priv->udev, |
364 | priv->is_rtl8187b ? 3 : 1), | |
605bebe2 MW |
365 | skb_tail_pointer(skb), |
366 | RTL8187_MAX_RX, rtl8187_rx_cb, skb); | |
367 | info = (struct rtl8187_rx_info *)skb->cb; | |
368 | info->urb = entry; | |
369 | info->dev = dev; | |
370 | skb_queue_tail(&priv->rx_queue, skb); | |
371 | usb_submit_urb(entry, GFP_KERNEL); | |
372 | } | |
373 | ||
374 | return 0; | |
375 | } | |
376 | ||
f8a08c34 | 377 | static int rtl8187_cmd_reset(struct ieee80211_hw *dev) |
605bebe2 MW |
378 | { |
379 | struct rtl8187_priv *priv = dev->priv; | |
380 | u8 reg; | |
381 | int i; | |
382 | ||
605bebe2 MW |
383 | reg = rtl818x_ioread8(priv, &priv->map->CMD); |
384 | reg &= (1 << 1); | |
385 | reg |= RTL818X_CMD_RESET; | |
386 | rtl818x_iowrite8(priv, &priv->map->CMD, reg); | |
387 | ||
388 | i = 10; | |
389 | do { | |
390 | msleep(2); | |
391 | if (!(rtl818x_ioread8(priv, &priv->map->CMD) & | |
392 | RTL818X_CMD_RESET)) | |
393 | break; | |
394 | } while (--i); | |
395 | ||
396 | if (!i) { | |
397 | printk(KERN_ERR "%s: Reset timeout!\n", wiphy_name(dev->wiphy)); | |
398 | return -ETIMEDOUT; | |
399 | } | |
400 | ||
401 | /* reload registers from eeprom */ | |
402 | rtl818x_iowrite8(priv, &priv->map->EEPROM_CMD, RTL818X_EEPROM_CMD_LOAD); | |
403 | ||
404 | i = 10; | |
405 | do { | |
406 | msleep(4); | |
407 | if (!(rtl818x_ioread8(priv, &priv->map->EEPROM_CMD) & | |
408 | RTL818X_EEPROM_CMD_CONFIG)) | |
409 | break; | |
410 | } while (--i); | |
411 | ||
412 | if (!i) { | |
413 | printk(KERN_ERR "%s: eeprom reset timeout!\n", | |
414 | wiphy_name(dev->wiphy)); | |
415 | return -ETIMEDOUT; | |
416 | } | |
417 | ||
f8a08c34 HTL |
418 | return 0; |
419 | } | |
420 | ||
421 | static int rtl8187_init_hw(struct ieee80211_hw *dev) | |
422 | { | |
423 | struct rtl8187_priv *priv = dev->priv; | |
424 | u8 reg; | |
425 | int res; | |
426 | ||
427 | /* reset */ | |
428 | rtl818x_iowrite8(priv, &priv->map->EEPROM_CMD, | |
429 | RTL818X_EEPROM_CMD_CONFIG); | |
430 | reg = rtl818x_ioread8(priv, &priv->map->CONFIG3); | |
431 | rtl818x_iowrite8(priv, &priv->map->CONFIG3, reg | | |
432 | RTL818X_CONFIG3_ANAPARAM_WRITE); | |
433 | rtl818x_iowrite32(priv, &priv->map->ANAPARAM, RTL8225_ANAPARAM_ON); | |
434 | rtl818x_iowrite32(priv, &priv->map->ANAPARAM2, RTL8225_ANAPARAM2_ON); | |
435 | rtl818x_iowrite8(priv, &priv->map->CONFIG3, reg & | |
436 | ~RTL818X_CONFIG3_ANAPARAM_WRITE); | |
437 | rtl818x_iowrite8(priv, &priv->map->EEPROM_CMD, | |
438 | RTL818X_EEPROM_CMD_NORMAL); | |
439 | ||
440 | rtl818x_iowrite16(priv, &priv->map->INT_MASK, 0); | |
441 | ||
442 | msleep(200); | |
443 | rtl818x_iowrite8(priv, (u8 *)0xFE18, 0x10); | |
444 | rtl818x_iowrite8(priv, (u8 *)0xFE18, 0x11); | |
445 | rtl818x_iowrite8(priv, (u8 *)0xFE18, 0x00); | |
446 | msleep(200); | |
447 | ||
448 | res = rtl8187_cmd_reset(dev); | |
449 | if (res) | |
450 | return res; | |
451 | ||
605bebe2 MW |
452 | rtl818x_iowrite8(priv, &priv->map->EEPROM_CMD, RTL818X_EEPROM_CMD_CONFIG); |
453 | reg = rtl818x_ioread8(priv, &priv->map->CONFIG3); | |
f8a08c34 HTL |
454 | rtl818x_iowrite8(priv, &priv->map->CONFIG3, |
455 | reg | RTL818X_CONFIG3_ANAPARAM_WRITE); | |
605bebe2 MW |
456 | rtl818x_iowrite32(priv, &priv->map->ANAPARAM, RTL8225_ANAPARAM_ON); |
457 | rtl818x_iowrite32(priv, &priv->map->ANAPARAM2, RTL8225_ANAPARAM2_ON); | |
f8a08c34 HTL |
458 | rtl818x_iowrite8(priv, &priv->map->CONFIG3, |
459 | reg & ~RTL818X_CONFIG3_ANAPARAM_WRITE); | |
605bebe2 MW |
460 | rtl818x_iowrite8(priv, &priv->map->EEPROM_CMD, RTL818X_EEPROM_CMD_NORMAL); |
461 | ||
462 | /* setup card */ | |
463 | rtl818x_iowrite16(priv, &priv->map->RFPinsSelect, 0); | |
464 | rtl818x_iowrite8(priv, &priv->map->GPIO, 0); | |
465 | ||
466 | rtl818x_iowrite16(priv, &priv->map->RFPinsSelect, (4 << 8)); | |
467 | rtl818x_iowrite8(priv, &priv->map->GPIO, 1); | |
468 | rtl818x_iowrite8(priv, &priv->map->GP_ENABLE, 0); | |
469 | ||
470 | rtl818x_iowrite8(priv, &priv->map->EEPROM_CMD, RTL818X_EEPROM_CMD_CONFIG); | |
605bebe2 MW |
471 | |
472 | rtl818x_iowrite16(priv, (__le16 *)0xFFF4, 0xFFFF); | |
473 | reg = rtl818x_ioread8(priv, &priv->map->CONFIG1); | |
474 | reg &= 0x3F; | |
475 | reg |= 0x80; | |
476 | rtl818x_iowrite8(priv, &priv->map->CONFIG1, reg); | |
477 | ||
478 | rtl818x_iowrite8(priv, &priv->map->EEPROM_CMD, RTL818X_EEPROM_CMD_NORMAL); | |
479 | ||
480 | rtl818x_iowrite32(priv, &priv->map->INT_TIMEOUT, 0); | |
481 | rtl818x_iowrite8(priv, &priv->map->WPA_CONF, 0); | |
482 | rtl818x_iowrite8(priv, &priv->map->RATE_FALLBACK, 0x81); | |
483 | ||
484 | // TODO: set RESP_RATE and BRSR properly | |
485 | rtl818x_iowrite8(priv, &priv->map->RESP_RATE, (8 << 4) | 0); | |
486 | rtl818x_iowrite16(priv, &priv->map->BRSR, 0x01F3); | |
487 | ||
488 | /* host_usb_init */ | |
489 | rtl818x_iowrite16(priv, &priv->map->RFPinsSelect, 0); | |
490 | rtl818x_iowrite8(priv, &priv->map->GPIO, 0); | |
491 | reg = rtl818x_ioread8(priv, (u8 *)0xFE53); | |
492 | rtl818x_iowrite8(priv, (u8 *)0xFE53, reg | (1 << 7)); | |
493 | rtl818x_iowrite16(priv, &priv->map->RFPinsSelect, (4 << 8)); | |
494 | rtl818x_iowrite8(priv, &priv->map->GPIO, 0x20); | |
495 | rtl818x_iowrite8(priv, &priv->map->GP_ENABLE, 0); | |
496 | rtl818x_iowrite16(priv, &priv->map->RFPinsOutput, 0x80); | |
497 | rtl818x_iowrite16(priv, &priv->map->RFPinsSelect, 0x80); | |
498 | rtl818x_iowrite16(priv, &priv->map->RFPinsEnable, 0x80); | |
499 | msleep(100); | |
500 | ||
501 | rtl818x_iowrite32(priv, &priv->map->RF_TIMING, 0x000a8008); | |
502 | rtl818x_iowrite16(priv, &priv->map->BRSR, 0xFFFF); | |
503 | rtl818x_iowrite32(priv, &priv->map->RF_PARA, 0x00100044); | |
f8a08c34 HTL |
504 | rtl818x_iowrite8(priv, &priv->map->EEPROM_CMD, |
505 | RTL818X_EEPROM_CMD_CONFIG); | |
605bebe2 | 506 | rtl818x_iowrite8(priv, &priv->map->CONFIG3, 0x44); |
f8a08c34 HTL |
507 | rtl818x_iowrite8(priv, &priv->map->EEPROM_CMD, |
508 | RTL818X_EEPROM_CMD_NORMAL); | |
605bebe2 MW |
509 | rtl818x_iowrite16(priv, &priv->map->RFPinsEnable, 0x1FF7); |
510 | msleep(100); | |
511 | ||
f6532111 | 512 | priv->rf->init(dev); |
605bebe2 MW |
513 | |
514 | rtl818x_iowrite16(priv, &priv->map->BRSR, 0x01F3); | |
f6532111 MW |
515 | reg = rtl818x_ioread8(priv, &priv->map->PGSELECT) & ~1; |
516 | rtl818x_iowrite8(priv, &priv->map->PGSELECT, reg | 1); | |
605bebe2 MW |
517 | rtl818x_iowrite16(priv, (__le16 *)0xFFFE, 0x10); |
518 | rtl818x_iowrite8(priv, &priv->map->TALLY_SEL, 0x80); | |
519 | rtl818x_iowrite8(priv, (u8 *)0xFFFF, 0x60); | |
f6532111 | 520 | rtl818x_iowrite8(priv, &priv->map->PGSELECT, reg); |
605bebe2 MW |
521 | |
522 | return 0; | |
523 | } | |
524 | ||
f8a08c34 HTL |
525 | static const u8 rtl8187b_reg_table[][3] = { |
526 | {0xF0, 0x32, 0}, {0xF1, 0x32, 0}, {0xF2, 0x00, 0}, {0xF3, 0x00, 0}, | |
527 | {0xF4, 0x32, 0}, {0xF5, 0x43, 0}, {0xF6, 0x00, 0}, {0xF7, 0x00, 0}, | |
528 | {0xF8, 0x46, 0}, {0xF9, 0xA4, 0}, {0xFA, 0x00, 0}, {0xFB, 0x00, 0}, | |
529 | {0xFC, 0x96, 0}, {0xFD, 0xA4, 0}, {0xFE, 0x00, 0}, {0xFF, 0x00, 0}, | |
530 | ||
531 | {0x58, 0x4B, 1}, {0x59, 0x00, 1}, {0x5A, 0x4B, 1}, {0x5B, 0x00, 1}, | |
532 | {0x60, 0x4B, 1}, {0x61, 0x09, 1}, {0x62, 0x4B, 1}, {0x63, 0x09, 1}, | |
533 | {0xCE, 0x0F, 1}, {0xCF, 0x00, 1}, {0xE0, 0xFF, 1}, {0xE1, 0x0F, 1}, | |
534 | {0xE2, 0x00, 1}, {0xF0, 0x4E, 1}, {0xF1, 0x01, 1}, {0xF2, 0x02, 1}, | |
535 | {0xF3, 0x03, 1}, {0xF4, 0x04, 1}, {0xF5, 0x05, 1}, {0xF6, 0x06, 1}, | |
536 | {0xF7, 0x07, 1}, {0xF8, 0x08, 1}, | |
537 | ||
538 | {0x4E, 0x00, 2}, {0x0C, 0x04, 2}, {0x21, 0x61, 2}, {0x22, 0x68, 2}, | |
539 | {0x23, 0x6F, 2}, {0x24, 0x76, 2}, {0x25, 0x7D, 2}, {0x26, 0x84, 2}, | |
540 | {0x27, 0x8D, 2}, {0x4D, 0x08, 2}, {0x50, 0x05, 2}, {0x51, 0xF5, 2}, | |
541 | {0x52, 0x04, 2}, {0x53, 0xA0, 2}, {0x54, 0x1F, 2}, {0x55, 0x23, 2}, | |
542 | {0x56, 0x45, 2}, {0x57, 0x67, 2}, {0x58, 0x08, 2}, {0x59, 0x08, 2}, | |
543 | {0x5A, 0x08, 2}, {0x5B, 0x08, 2}, {0x60, 0x08, 2}, {0x61, 0x08, 2}, | |
544 | {0x62, 0x08, 2}, {0x63, 0x08, 2}, {0x64, 0xCF, 2}, {0x72, 0x56, 2}, | |
545 | {0x73, 0x9A, 2}, | |
546 | ||
547 | {0x34, 0xF0, 0}, {0x35, 0x0F, 0}, {0x5B, 0x40, 0}, {0x84, 0x88, 0}, | |
548 | {0x85, 0x24, 0}, {0x88, 0x54, 0}, {0x8B, 0xB8, 0}, {0x8C, 0x07, 0}, | |
549 | {0x8D, 0x00, 0}, {0x94, 0x1B, 0}, {0x95, 0x12, 0}, {0x96, 0x00, 0}, | |
550 | {0x97, 0x06, 0}, {0x9D, 0x1A, 0}, {0x9F, 0x10, 0}, {0xB4, 0x22, 0}, | |
551 | {0xBE, 0x80, 0}, {0xDB, 0x00, 0}, {0xEE, 0x00, 0}, {0x91, 0x03, 0}, | |
552 | ||
553 | {0x4C, 0x00, 2}, {0x9F, 0x00, 3}, {0x8C, 0x01, 0}, {0x8D, 0x10, 0}, | |
554 | {0x8E, 0x08, 0}, {0x8F, 0x00, 0} | |
555 | }; | |
556 | ||
557 | static int rtl8187b_init_hw(struct ieee80211_hw *dev) | |
558 | { | |
559 | struct rtl8187_priv *priv = dev->priv; | |
560 | int res, i; | |
561 | u8 reg; | |
562 | ||
563 | rtl818x_iowrite8(priv, &priv->map->EEPROM_CMD, | |
564 | RTL818X_EEPROM_CMD_CONFIG); | |
565 | ||
566 | reg = rtl818x_ioread8(priv, &priv->map->CONFIG3); | |
567 | reg |= RTL818X_CONFIG3_ANAPARAM_WRITE | RTL818X_CONFIG3_GNT_SELECT; | |
568 | rtl818x_iowrite8(priv, &priv->map->CONFIG3, reg); | |
569 | rtl818x_iowrite32(priv, &priv->map->ANAPARAM2, 0x727f3f52); | |
570 | rtl818x_iowrite32(priv, &priv->map->ANAPARAM, 0x45090658); | |
571 | rtl818x_iowrite8(priv, &priv->map->ANAPARAM3, 0); | |
572 | ||
573 | rtl818x_iowrite8(priv, (u8 *)0xFF61, 0x10); | |
574 | reg = rtl818x_ioread8(priv, (u8 *)0xFF62); | |
575 | rtl818x_iowrite8(priv, (u8 *)0xFF62, reg & ~(1 << 5)); | |
576 | rtl818x_iowrite8(priv, (u8 *)0xFF62, reg | (1 << 5)); | |
577 | ||
578 | reg = rtl818x_ioread8(priv, &priv->map->CONFIG3); | |
579 | reg &= ~RTL818X_CONFIG3_ANAPARAM_WRITE; | |
580 | rtl818x_iowrite8(priv, &priv->map->CONFIG3, reg); | |
581 | ||
582 | rtl818x_iowrite8(priv, &priv->map->EEPROM_CMD, | |
583 | RTL818X_EEPROM_CMD_NORMAL); | |
584 | ||
585 | res = rtl8187_cmd_reset(dev); | |
586 | if (res) | |
587 | return res; | |
588 | ||
589 | rtl818x_iowrite16(priv, (__le16 *)0xFF2D, 0x0FFF); | |
590 | reg = rtl818x_ioread8(priv, &priv->map->CW_CONF); | |
591 | reg |= RTL818X_CW_CONF_PERPACKET_RETRY_SHIFT; | |
592 | rtl818x_iowrite8(priv, &priv->map->CW_CONF, reg); | |
593 | reg = rtl818x_ioread8(priv, &priv->map->TX_AGC_CTL); | |
594 | reg |= RTL818X_TX_AGC_CTL_PERPACKET_GAIN_SHIFT | | |
595 | RTL818X_TX_AGC_CTL_PERPACKET_ANTSEL_SHIFT; | |
596 | rtl818x_iowrite8(priv, &priv->map->TX_AGC_CTL, reg); | |
597 | ||
598 | rtl818x_iowrite16_idx(priv, (__le16 *)0xFFE0, 0x0FFF, 1); | |
599 | reg = rtl818x_ioread8(priv, &priv->map->RATE_FALLBACK); | |
600 | reg |= RTL818X_RATE_FALLBACK_ENABLE; | |
601 | rtl818x_iowrite8(priv, &priv->map->RATE_FALLBACK, reg); | |
602 | ||
603 | rtl818x_iowrite16(priv, &priv->map->BEACON_INTERVAL, 100); | |
604 | rtl818x_iowrite16(priv, &priv->map->ATIM_WND, 2); | |
605 | rtl818x_iowrite16_idx(priv, (__le16 *)0xFFD4, 0xFFFF, 1); | |
606 | ||
607 | rtl818x_iowrite8(priv, &priv->map->EEPROM_CMD, | |
608 | RTL818X_EEPROM_CMD_CONFIG); | |
609 | reg = rtl818x_ioread8(priv, &priv->map->CONFIG1); | |
610 | rtl818x_iowrite8(priv, &priv->map->CONFIG1, (reg & 0x3F) | 0x80); | |
611 | rtl818x_iowrite8(priv, &priv->map->EEPROM_CMD, | |
612 | RTL818X_EEPROM_CMD_NORMAL); | |
613 | ||
614 | rtl818x_iowrite8(priv, &priv->map->WPA_CONF, 0); | |
615 | for (i = 0; i < ARRAY_SIZE(rtl8187b_reg_table); i++) { | |
616 | rtl818x_iowrite8_idx(priv, | |
617 | (u8 *)(uintptr_t) | |
618 | (rtl8187b_reg_table[i][0] | 0xFF00), | |
619 | rtl8187b_reg_table[i][1], | |
620 | rtl8187b_reg_table[i][2]); | |
621 | } | |
622 | ||
623 | rtl818x_iowrite16(priv, &priv->map->TID_AC_MAP, 0xFA50); | |
624 | rtl818x_iowrite16(priv, &priv->map->INT_MIG, 0); | |
625 | ||
626 | rtl818x_iowrite32_idx(priv, (__le32 *)0xFFF0, 0, 1); | |
627 | rtl818x_iowrite32_idx(priv, (__le32 *)0xFFF4, 0, 1); | |
628 | rtl818x_iowrite8_idx(priv, (u8 *)0xFFF8, 0, 1); | |
629 | ||
630 | rtl818x_iowrite32(priv, &priv->map->RF_TIMING, 0x00004001); | |
631 | ||
632 | rtl818x_iowrite16_idx(priv, (__le16 *)0xFF72, 0x569A, 2); | |
633 | ||
634 | rtl818x_iowrite8(priv, &priv->map->EEPROM_CMD, | |
635 | RTL818X_EEPROM_CMD_CONFIG); | |
636 | reg = rtl818x_ioread8(priv, &priv->map->CONFIG3); | |
637 | reg |= RTL818X_CONFIG3_ANAPARAM_WRITE; | |
638 | rtl818x_iowrite8(priv, &priv->map->CONFIG3, reg); | |
639 | rtl818x_iowrite8(priv, &priv->map->EEPROM_CMD, | |
640 | RTL818X_EEPROM_CMD_NORMAL); | |
641 | ||
642 | rtl818x_iowrite16(priv, &priv->map->RFPinsOutput, 0x0480); | |
643 | rtl818x_iowrite16(priv, &priv->map->RFPinsSelect, 0x2488); | |
644 | rtl818x_iowrite16(priv, &priv->map->RFPinsEnable, 0x1FFF); | |
645 | msleep(1100); | |
646 | ||
647 | priv->rf->init(dev); | |
648 | ||
649 | reg = RTL818X_CMD_TX_ENABLE | RTL818X_CMD_RX_ENABLE; | |
650 | rtl818x_iowrite8(priv, &priv->map->CMD, reg); | |
651 | rtl818x_iowrite16(priv, &priv->map->INT_MASK, 0xFFFF); | |
652 | ||
653 | rtl818x_iowrite8(priv, (u8 *)0xFE41, 0xF4); | |
654 | rtl818x_iowrite8(priv, (u8 *)0xFE40, 0x00); | |
655 | rtl818x_iowrite8(priv, (u8 *)0xFE42, 0x00); | |
656 | rtl818x_iowrite8(priv, (u8 *)0xFE42, 0x01); | |
657 | rtl818x_iowrite8(priv, (u8 *)0xFE40, 0x0F); | |
658 | rtl818x_iowrite8(priv, (u8 *)0xFE42, 0x00); | |
659 | rtl818x_iowrite8(priv, (u8 *)0xFE42, 0x01); | |
660 | ||
661 | reg = rtl818x_ioread8(priv, (u8 *)0xFFDB); | |
662 | rtl818x_iowrite8(priv, (u8 *)0xFFDB, reg | (1 << 2)); | |
663 | rtl818x_iowrite16_idx(priv, (__le16 *)0xFF72, 0x59FA, 3); | |
664 | rtl818x_iowrite16_idx(priv, (__le16 *)0xFF74, 0x59D2, 3); | |
665 | rtl818x_iowrite16_idx(priv, (__le16 *)0xFF76, 0x59D2, 3); | |
666 | rtl818x_iowrite16_idx(priv, (__le16 *)0xFF78, 0x19FA, 3); | |
667 | rtl818x_iowrite16_idx(priv, (__le16 *)0xFF7A, 0x19FA, 3); | |
668 | rtl818x_iowrite16_idx(priv, (__le16 *)0xFF7C, 0x00D0, 3); | |
669 | rtl818x_iowrite8(priv, (u8 *)0xFF61, 0); | |
670 | rtl818x_iowrite8_idx(priv, (u8 *)0xFF80, 0x0F, 1); | |
671 | rtl818x_iowrite8_idx(priv, (u8 *)0xFF83, 0x03, 1); | |
672 | rtl818x_iowrite8(priv, (u8 *)0xFFDA, 0x10); | |
673 | rtl818x_iowrite8_idx(priv, (u8 *)0xFF4D, 0x08, 2); | |
674 | ||
675 | rtl818x_iowrite32(priv, &priv->map->HSSI_PARA, 0x0600321B); | |
676 | ||
677 | rtl818x_iowrite16_idx(priv, (__le16 *)0xFFEC, 0x0800, 1); | |
678 | ||
679 | return 0; | |
680 | } | |
681 | ||
4150c572 | 682 | static int rtl8187_start(struct ieee80211_hw *dev) |
605bebe2 MW |
683 | { |
684 | struct rtl8187_priv *priv = dev->priv; | |
685 | u32 reg; | |
686 | int ret; | |
687 | ||
f8a08c34 HTL |
688 | ret = (!priv->is_rtl8187b) ? rtl8187_init_hw(dev) : |
689 | rtl8187b_init_hw(dev); | |
605bebe2 MW |
690 | if (ret) |
691 | return ret; | |
692 | ||
f8a08c34 HTL |
693 | if (priv->is_rtl8187b) { |
694 | reg = RTL818X_RX_CONF_MGMT | | |
695 | RTL818X_RX_CONF_DATA | | |
696 | RTL818X_RX_CONF_BROADCAST | | |
697 | RTL818X_RX_CONF_NICMAC | | |
698 | RTL818X_RX_CONF_BSSID | | |
699 | (7 << 13 /* RX FIFO threshold NONE */) | | |
700 | (7 << 10 /* MAX RX DMA */) | | |
701 | RTL818X_RX_CONF_RX_AUTORESETPHY | | |
702 | RTL818X_RX_CONF_ONLYERLPKT | | |
703 | RTL818X_RX_CONF_MULTICAST; | |
704 | priv->rx_conf = reg; | |
705 | rtl818x_iowrite32(priv, &priv->map->RX_CONF, reg); | |
706 | ||
707 | rtl818x_iowrite32(priv, &priv->map->TX_CONF, | |
708 | RTL818X_TX_CONF_HW_SEQNUM | | |
709 | RTL818X_TX_CONF_DISREQQSIZE | | |
710 | (7 << 8 /* short retry limit */) | | |
711 | (7 << 0 /* long retry limit */) | | |
712 | (7 << 21 /* MAX TX DMA */)); | |
713 | rtl8187_init_urbs(dev); | |
714 | return 0; | |
715 | } | |
716 | ||
605bebe2 MW |
717 | rtl818x_iowrite16(priv, &priv->map->INT_MASK, 0xFFFF); |
718 | ||
2fe14263 MW |
719 | rtl818x_iowrite32(priv, &priv->map->MAR[0], ~0); |
720 | rtl818x_iowrite32(priv, &priv->map->MAR[1], ~0); | |
721 | ||
605bebe2 MW |
722 | rtl8187_init_urbs(dev); |
723 | ||
724 | reg = RTL818X_RX_CONF_ONLYERLPKT | | |
725 | RTL818X_RX_CONF_RX_AUTORESETPHY | | |
726 | RTL818X_RX_CONF_BSSID | | |
727 | RTL818X_RX_CONF_MGMT | | |
605bebe2 MW |
728 | RTL818X_RX_CONF_DATA | |
729 | (7 << 13 /* RX FIFO threshold NONE */) | | |
730 | (7 << 10 /* MAX RX DMA */) | | |
731 | RTL818X_RX_CONF_BROADCAST | | |
605bebe2 | 732 | RTL818X_RX_CONF_NICMAC; |
605bebe2 | 733 | |
4150c572 | 734 | priv->rx_conf = reg; |
605bebe2 MW |
735 | rtl818x_iowrite32(priv, &priv->map->RX_CONF, reg); |
736 | ||
737 | reg = rtl818x_ioread8(priv, &priv->map->CW_CONF); | |
738 | reg &= ~RTL818X_CW_CONF_PERPACKET_CW_SHIFT; | |
739 | reg |= RTL818X_CW_CONF_PERPACKET_RETRY_SHIFT; | |
740 | rtl818x_iowrite8(priv, &priv->map->CW_CONF, reg); | |
741 | ||
742 | reg = rtl818x_ioread8(priv, &priv->map->TX_AGC_CTL); | |
743 | reg &= ~RTL818X_TX_AGC_CTL_PERPACKET_GAIN_SHIFT; | |
744 | reg &= ~RTL818X_TX_AGC_CTL_PERPACKET_ANTSEL_SHIFT; | |
745 | reg &= ~RTL818X_TX_AGC_CTL_FEEDBACK_ANT; | |
746 | rtl818x_iowrite8(priv, &priv->map->TX_AGC_CTL, reg); | |
747 | ||
748 | reg = RTL818X_TX_CONF_CW_MIN | | |
749 | (7 << 21 /* MAX TX DMA */) | | |
750 | RTL818X_TX_CONF_NO_ICV; | |
751 | rtl818x_iowrite32(priv, &priv->map->TX_CONF, reg); | |
752 | ||
753 | reg = rtl818x_ioread8(priv, &priv->map->CMD); | |
754 | reg |= RTL818X_CMD_TX_ENABLE; | |
755 | reg |= RTL818X_CMD_RX_ENABLE; | |
756 | rtl818x_iowrite8(priv, &priv->map->CMD, reg); | |
757 | ||
758 | return 0; | |
759 | } | |
760 | ||
4150c572 | 761 | static void rtl8187_stop(struct ieee80211_hw *dev) |
605bebe2 MW |
762 | { |
763 | struct rtl8187_priv *priv = dev->priv; | |
764 | struct rtl8187_rx_info *info; | |
765 | struct sk_buff *skb; | |
766 | u32 reg; | |
767 | ||
768 | rtl818x_iowrite16(priv, &priv->map->INT_MASK, 0); | |
769 | ||
770 | reg = rtl818x_ioread8(priv, &priv->map->CMD); | |
771 | reg &= ~RTL818X_CMD_TX_ENABLE; | |
772 | reg &= ~RTL818X_CMD_RX_ENABLE; | |
773 | rtl818x_iowrite8(priv, &priv->map->CMD, reg); | |
774 | ||
f6532111 | 775 | priv->rf->stop(dev); |
605bebe2 MW |
776 | |
777 | rtl818x_iowrite8(priv, &priv->map->EEPROM_CMD, RTL818X_EEPROM_CMD_CONFIG); | |
778 | reg = rtl818x_ioread8(priv, &priv->map->CONFIG4); | |
779 | rtl818x_iowrite8(priv, &priv->map->CONFIG4, reg | RTL818X_CONFIG4_VCOOFF); | |
780 | rtl818x_iowrite8(priv, &priv->map->EEPROM_CMD, RTL818X_EEPROM_CMD_NORMAL); | |
781 | ||
782 | while ((skb = skb_dequeue(&priv->rx_queue))) { | |
783 | info = (struct rtl8187_rx_info *)skb->cb; | |
784 | usb_kill_urb(info->urb); | |
785 | kfree_skb(skb); | |
786 | } | |
4150c572 | 787 | return; |
605bebe2 MW |
788 | } |
789 | ||
790 | static int rtl8187_add_interface(struct ieee80211_hw *dev, | |
791 | struct ieee80211_if_init_conf *conf) | |
792 | { | |
793 | struct rtl8187_priv *priv = dev->priv; | |
4150c572 | 794 | int i; |
605bebe2 | 795 | |
4150c572 JB |
796 | if (priv->mode != IEEE80211_IF_TYPE_MNTR) |
797 | return -EOPNOTSUPP; | |
605bebe2 MW |
798 | |
799 | switch (conf->type) { | |
800 | case IEEE80211_IF_TYPE_STA: | |
605bebe2 MW |
801 | priv->mode = conf->type; |
802 | break; | |
803 | default: | |
804 | return -EOPNOTSUPP; | |
805 | } | |
806 | ||
aa979a6a HRK |
807 | priv->vif = conf->vif; |
808 | ||
4150c572 JB |
809 | rtl818x_iowrite8(priv, &priv->map->EEPROM_CMD, RTL818X_EEPROM_CMD_CONFIG); |
810 | for (i = 0; i < ETH_ALEN; i++) | |
811 | rtl818x_iowrite8(priv, &priv->map->MAC[i], | |
812 | ((u8 *)conf->mac_addr)[i]); | |
813 | rtl818x_iowrite8(priv, &priv->map->EEPROM_CMD, RTL818X_EEPROM_CMD_NORMAL); | |
605bebe2 MW |
814 | |
815 | return 0; | |
816 | } | |
817 | ||
818 | static void rtl8187_remove_interface(struct ieee80211_hw *dev, | |
819 | struct ieee80211_if_init_conf *conf) | |
820 | { | |
821 | struct rtl8187_priv *priv = dev->priv; | |
4150c572 | 822 | priv->mode = IEEE80211_IF_TYPE_MNTR; |
aa979a6a | 823 | priv->vif = NULL; |
605bebe2 MW |
824 | } |
825 | ||
826 | static int rtl8187_config(struct ieee80211_hw *dev, struct ieee80211_conf *conf) | |
827 | { | |
828 | struct rtl8187_priv *priv = dev->priv; | |
f6532111 MW |
829 | u32 reg; |
830 | ||
831 | reg = rtl818x_ioread32(priv, &priv->map->TX_CONF); | |
832 | /* Enable TX loopback on MAC level to avoid TX during channel | |
833 | * changes, as this has be seen to causes problems and the | |
834 | * card will stop work until next reset | |
835 | */ | |
836 | rtl818x_iowrite32(priv, &priv->map->TX_CONF, | |
837 | reg | RTL818X_TX_CONF_LOOPBACK_MAC); | |
838 | msleep(10); | |
839 | priv->rf->set_chan(dev, conf); | |
840 | msleep(10); | |
841 | rtl818x_iowrite32(priv, &priv->map->TX_CONF, reg); | |
605bebe2 | 842 | |
6f7853f3 HTL |
843 | if (!priv->is_rtl8187b) { |
844 | rtl818x_iowrite8(priv, &priv->map->SIFS, 0x22); | |
845 | ||
846 | if (conf->flags & IEEE80211_CONF_SHORT_SLOT_TIME) { | |
847 | rtl818x_iowrite8(priv, &priv->map->SLOT, 0x9); | |
848 | rtl818x_iowrite8(priv, &priv->map->DIFS, 0x14); | |
849 | rtl818x_iowrite8(priv, &priv->map->EIFS, 91 - 0x14); | |
850 | rtl818x_iowrite8(priv, &priv->map->CW_VAL, 0x73); | |
851 | } else { | |
852 | rtl818x_iowrite8(priv, &priv->map->SLOT, 0x14); | |
853 | rtl818x_iowrite8(priv, &priv->map->DIFS, 0x24); | |
854 | rtl818x_iowrite8(priv, &priv->map->EIFS, 91 - 0x24); | |
855 | rtl818x_iowrite8(priv, &priv->map->CW_VAL, 0xa5); | |
856 | } | |
605bebe2 MW |
857 | } |
858 | ||
859 | rtl818x_iowrite16(priv, &priv->map->ATIM_WND, 2); | |
860 | rtl818x_iowrite16(priv, &priv->map->ATIMTR_INTERVAL, 100); | |
861 | rtl818x_iowrite16(priv, &priv->map->BEACON_INTERVAL, 100); | |
862 | rtl818x_iowrite16(priv, &priv->map->BEACON_INTERVAL_TIME, 100); | |
863 | return 0; | |
864 | } | |
865 | ||
32bfd35d JB |
866 | static int rtl8187_config_interface(struct ieee80211_hw *dev, |
867 | struct ieee80211_vif *vif, | |
605bebe2 MW |
868 | struct ieee80211_if_conf *conf) |
869 | { | |
870 | struct rtl8187_priv *priv = dev->priv; | |
871 | int i; | |
6f7853f3 | 872 | u8 reg; |
605bebe2 MW |
873 | |
874 | for (i = 0; i < ETH_ALEN; i++) | |
875 | rtl818x_iowrite8(priv, &priv->map->BSSID[i], conf->bssid[i]); | |
876 | ||
6f7853f3 HTL |
877 | if (is_valid_ether_addr(conf->bssid)) { |
878 | reg = RTL818X_MSR_INFRA; | |
879 | if (priv->is_rtl8187b) | |
880 | reg |= RTL818X_MSR_ENEDCA; | |
881 | rtl818x_iowrite8(priv, &priv->map->MSR, reg); | |
882 | } else { | |
883 | reg = RTL818X_MSR_NO_LINK; | |
884 | rtl818x_iowrite8(priv, &priv->map->MSR, reg); | |
885 | } | |
605bebe2 MW |
886 | |
887 | return 0; | |
888 | } | |
889 | ||
4150c572 JB |
890 | static void rtl8187_configure_filter(struct ieee80211_hw *dev, |
891 | unsigned int changed_flags, | |
892 | unsigned int *total_flags, | |
2fe14263 | 893 | int mc_count, struct dev_addr_list *mclist) |
4150c572 JB |
894 | { |
895 | struct rtl8187_priv *priv = dev->priv; | |
896 | ||
4150c572 JB |
897 | if (changed_flags & FIF_FCSFAIL) |
898 | priv->rx_conf ^= RTL818X_RX_CONF_FCS; | |
899 | if (changed_flags & FIF_CONTROL) | |
900 | priv->rx_conf ^= RTL818X_RX_CONF_CTRL; | |
901 | if (changed_flags & FIF_OTHER_BSS) | |
902 | priv->rx_conf ^= RTL818X_RX_CONF_MONITOR; | |
2fe14263 | 903 | if (*total_flags & FIF_ALLMULTI || mc_count > 0) |
4150c572 | 904 | priv->rx_conf |= RTL818X_RX_CONF_MULTICAST; |
2fe14263 MW |
905 | else |
906 | priv->rx_conf &= ~RTL818X_RX_CONF_MULTICAST; | |
907 | ||
908 | *total_flags = 0; | |
4150c572 | 909 | |
4150c572 JB |
910 | if (priv->rx_conf & RTL818X_RX_CONF_FCS) |
911 | *total_flags |= FIF_FCSFAIL; | |
912 | if (priv->rx_conf & RTL818X_RX_CONF_CTRL) | |
913 | *total_flags |= FIF_CONTROL; | |
914 | if (priv->rx_conf & RTL818X_RX_CONF_MONITOR) | |
915 | *total_flags |= FIF_OTHER_BSS; | |
2fe14263 MW |
916 | if (priv->rx_conf & RTL818X_RX_CONF_MULTICAST) |
917 | *total_flags |= FIF_ALLMULTI; | |
4150c572 JB |
918 | |
919 | rtl818x_iowrite32_async(priv, &priv->map->RX_CONF, priv->rx_conf); | |
920 | } | |
921 | ||
605bebe2 MW |
922 | static const struct ieee80211_ops rtl8187_ops = { |
923 | .tx = rtl8187_tx, | |
4150c572 | 924 | .start = rtl8187_start, |
605bebe2 MW |
925 | .stop = rtl8187_stop, |
926 | .add_interface = rtl8187_add_interface, | |
927 | .remove_interface = rtl8187_remove_interface, | |
928 | .config = rtl8187_config, | |
929 | .config_interface = rtl8187_config_interface, | |
4150c572 | 930 | .configure_filter = rtl8187_configure_filter, |
605bebe2 MW |
931 | }; |
932 | ||
933 | static void rtl8187_eeprom_register_read(struct eeprom_93cx6 *eeprom) | |
934 | { | |
935 | struct ieee80211_hw *dev = eeprom->data; | |
936 | struct rtl8187_priv *priv = dev->priv; | |
937 | u8 reg = rtl818x_ioread8(priv, &priv->map->EEPROM_CMD); | |
938 | ||
939 | eeprom->reg_data_in = reg & RTL818X_EEPROM_CMD_WRITE; | |
940 | eeprom->reg_data_out = reg & RTL818X_EEPROM_CMD_READ; | |
941 | eeprom->reg_data_clock = reg & RTL818X_EEPROM_CMD_CK; | |
942 | eeprom->reg_chip_select = reg & RTL818X_EEPROM_CMD_CS; | |
943 | } | |
944 | ||
945 | static void rtl8187_eeprom_register_write(struct eeprom_93cx6 *eeprom) | |
946 | { | |
947 | struct ieee80211_hw *dev = eeprom->data; | |
948 | struct rtl8187_priv *priv = dev->priv; | |
949 | u8 reg = RTL818X_EEPROM_CMD_PROGRAM; | |
950 | ||
951 | if (eeprom->reg_data_in) | |
952 | reg |= RTL818X_EEPROM_CMD_WRITE; | |
953 | if (eeprom->reg_data_out) | |
954 | reg |= RTL818X_EEPROM_CMD_READ; | |
955 | if (eeprom->reg_data_clock) | |
956 | reg |= RTL818X_EEPROM_CMD_CK; | |
957 | if (eeprom->reg_chip_select) | |
958 | reg |= RTL818X_EEPROM_CMD_CS; | |
959 | ||
960 | rtl818x_iowrite8(priv, &priv->map->EEPROM_CMD, reg); | |
961 | udelay(10); | |
962 | } | |
963 | ||
964 | static int __devinit rtl8187_probe(struct usb_interface *intf, | |
965 | const struct usb_device_id *id) | |
966 | { | |
967 | struct usb_device *udev = interface_to_usbdev(intf); | |
968 | struct ieee80211_hw *dev; | |
969 | struct rtl8187_priv *priv; | |
970 | struct eeprom_93cx6 eeprom; | |
971 | struct ieee80211_channel *channel; | |
6f7853f3 | 972 | const char *chip_name; |
605bebe2 MW |
973 | u16 txpwr, reg; |
974 | int err, i; | |
0795af57 | 975 | DECLARE_MAC_BUF(mac); |
605bebe2 MW |
976 | |
977 | dev = ieee80211_alloc_hw(sizeof(*priv), &rtl8187_ops); | |
978 | if (!dev) { | |
979 | printk(KERN_ERR "rtl8187: ieee80211 alloc failed\n"); | |
980 | return -ENOMEM; | |
981 | } | |
982 | ||
983 | priv = dev->priv; | |
6f7853f3 HTL |
984 | priv->is_rtl8187b = (id->driver_info == DEVICE_RTL8187B) || |
985 | !memcmp(udev->product, "RTL8187B", 8); | |
605bebe2 MW |
986 | |
987 | SET_IEEE80211_DEV(dev, &intf->dev); | |
988 | usb_set_intfdata(intf, dev); | |
989 | priv->udev = udev; | |
990 | ||
991 | usb_get_dev(udev); | |
992 | ||
993 | skb_queue_head_init(&priv->rx_queue); | |
8318d78a JB |
994 | |
995 | BUILD_BUG_ON(sizeof(priv->channels) != sizeof(rtl818x_channels)); | |
996 | BUILD_BUG_ON(sizeof(priv->rates) != sizeof(rtl818x_rates)); | |
997 | ||
605bebe2 MW |
998 | memcpy(priv->channels, rtl818x_channels, sizeof(rtl818x_channels)); |
999 | memcpy(priv->rates, rtl818x_rates, sizeof(rtl818x_rates)); | |
1000 | priv->map = (struct rtl818x_csr *)0xFF00; | |
8318d78a JB |
1001 | |
1002 | priv->band.band = IEEE80211_BAND_2GHZ; | |
1003 | priv->band.channels = priv->channels; | |
1004 | priv->band.n_channels = ARRAY_SIZE(rtl818x_channels); | |
1005 | priv->band.bitrates = priv->rates; | |
1006 | priv->band.n_bitrates = ARRAY_SIZE(rtl818x_rates); | |
1007 | dev->wiphy->bands[IEEE80211_BAND_2GHZ] = &priv->band; | |
1008 | ||
1009 | ||
4150c572 | 1010 | priv->mode = IEEE80211_IF_TYPE_MNTR; |
605bebe2 | 1011 | dev->flags = IEEE80211_HW_HOST_BROADCAST_PS_BUFFERING | |
566bfe5a BR |
1012 | IEEE80211_HW_RX_INCLUDES_FCS | |
1013 | IEEE80211_HW_SIGNAL_UNSPEC; | |
6f7853f3 HTL |
1014 | dev->extra_tx_headroom = (!priv->is_rtl8187b) ? |
1015 | sizeof(struct rtl8187_tx_hdr) : | |
1016 | sizeof(struct rtl8187b_tx_hdr); | |
1017 | if (!priv->is_rtl8187b) | |
1018 | dev->queues = 1; | |
1019 | else | |
1020 | dev->queues = 4; | |
566bfe5a | 1021 | dev->max_signal = 65; |
605bebe2 | 1022 | |
605bebe2 MW |
1023 | eeprom.data = dev; |
1024 | eeprom.register_read = rtl8187_eeprom_register_read; | |
1025 | eeprom.register_write = rtl8187_eeprom_register_write; | |
1026 | if (rtl818x_ioread32(priv, &priv->map->RX_CONF) & (1 << 6)) | |
1027 | eeprom.width = PCI_EEPROM_WIDTH_93C66; | |
1028 | else | |
1029 | eeprom.width = PCI_EEPROM_WIDTH_93C46; | |
1030 | ||
1031 | rtl818x_iowrite8(priv, &priv->map->EEPROM_CMD, RTL818X_EEPROM_CMD_CONFIG); | |
1032 | udelay(10); | |
1033 | ||
1034 | eeprom_93cx6_multiread(&eeprom, RTL8187_EEPROM_MAC_ADDR, | |
1035 | (__le16 __force *)dev->wiphy->perm_addr, 3); | |
1036 | if (!is_valid_ether_addr(dev->wiphy->perm_addr)) { | |
1037 | printk(KERN_WARNING "rtl8187: Invalid hwaddr! Using randomly " | |
1038 | "generated MAC address\n"); | |
1039 | random_ether_addr(dev->wiphy->perm_addr); | |
1040 | } | |
1041 | ||
1042 | channel = priv->channels; | |
1043 | for (i = 0; i < 3; i++) { | |
1044 | eeprom_93cx6_read(&eeprom, RTL8187_EEPROM_TXPWR_CHAN_1 + i, | |
1045 | &txpwr); | |
8318d78a JB |
1046 | (*channel++).hw_value = txpwr & 0xFF; |
1047 | (*channel++).hw_value = txpwr >> 8; | |
605bebe2 MW |
1048 | } |
1049 | for (i = 0; i < 2; i++) { | |
1050 | eeprom_93cx6_read(&eeprom, RTL8187_EEPROM_TXPWR_CHAN_4 + i, | |
1051 | &txpwr); | |
8318d78a JB |
1052 | (*channel++).hw_value = txpwr & 0xFF; |
1053 | (*channel++).hw_value = txpwr >> 8; | |
605bebe2 | 1054 | } |
6f7853f3 HTL |
1055 | if (!priv->is_rtl8187b) { |
1056 | for (i = 0; i < 2; i++) { | |
1057 | eeprom_93cx6_read(&eeprom, | |
1058 | RTL8187_EEPROM_TXPWR_CHAN_6 + i, | |
1059 | &txpwr); | |
1060 | (*channel++).hw_value = txpwr & 0xFF; | |
1061 | (*channel++).hw_value = txpwr >> 8; | |
1062 | } | |
1063 | } else { | |
1064 | eeprom_93cx6_read(&eeprom, RTL8187_EEPROM_TXPWR_CHAN_6, | |
605bebe2 | 1065 | &txpwr); |
8318d78a | 1066 | (*channel++).hw_value = txpwr & 0xFF; |
6f7853f3 HTL |
1067 | |
1068 | eeprom_93cx6_read(&eeprom, 0x0A, &txpwr); | |
1069 | (*channel++).hw_value = txpwr & 0xFF; | |
1070 | ||
1071 | eeprom_93cx6_read(&eeprom, 0x1C, &txpwr); | |
1072 | (*channel++).hw_value = txpwr & 0xFF; | |
8318d78a | 1073 | (*channel++).hw_value = txpwr >> 8; |
605bebe2 MW |
1074 | } |
1075 | ||
1076 | eeprom_93cx6_read(&eeprom, RTL8187_EEPROM_TXPWR_BASE, | |
1077 | &priv->txpwr_base); | |
1078 | ||
f6532111 MW |
1079 | reg = rtl818x_ioread8(priv, &priv->map->PGSELECT) & ~1; |
1080 | rtl818x_iowrite8(priv, &priv->map->PGSELECT, reg | 1); | |
605bebe2 MW |
1081 | /* 0 means asic B-cut, we should use SW 3 wire |
1082 | * bit-by-bit banging for radio. 1 means we can use | |
1083 | * USB specific request to write radio registers */ | |
1084 | priv->asic_rev = rtl818x_ioread8(priv, (u8 *)0xFFFE) & 0x3; | |
f6532111 | 1085 | rtl818x_iowrite8(priv, &priv->map->PGSELECT, reg); |
605bebe2 MW |
1086 | rtl818x_iowrite8(priv, &priv->map->EEPROM_CMD, RTL818X_EEPROM_CMD_NORMAL); |
1087 | ||
6f7853f3 HTL |
1088 | if (!priv->is_rtl8187b) { |
1089 | u32 reg32; | |
1090 | reg32 = rtl818x_ioread32(priv, &priv->map->TX_CONF); | |
1091 | reg32 &= RTL818X_TX_CONF_HWVER_MASK; | |
1092 | switch (reg32) { | |
1093 | case RTL818X_TX_CONF_R8187vD_1: | |
1094 | case RTL818X_TX_CONF_R8187vD_2: | |
1095 | chip_name = "RTL8187vD"; | |
1096 | break; | |
1097 | default: | |
1098 | chip_name = "RTL8187vB (default)"; | |
1099 | } | |
1100 | } else { | |
1101 | printk(KERN_WARNING "rtl8187: 8187B chip detected. Support " | |
1102 | "is EXPERIMENTAL, and could damage your\n" | |
1103 | " hardware, use at your own risk\n"); | |
1104 | /* | |
1105 | * Force USB request to write radio registers for 8187B, Realtek | |
1106 | * only uses it in their sources | |
1107 | */ | |
1108 | /*if (priv->asic_rev == 0) { | |
1109 | printk(KERN_WARNING "rtl8187: Forcing use of USB " | |
1110 | "requests to write to radio registers\n"); | |
1111 | priv->asic_rev = 1; | |
1112 | }*/ | |
1113 | switch (rtl818x_ioread8(priv, (u8 *)0xFFE1)) { | |
1114 | case RTL818X_R8187B_B: | |
1115 | chip_name = "RTL8187BvB"; | |
1116 | priv->hw_rev = RTL8187BvB; | |
1117 | break; | |
1118 | case RTL818X_R8187B_D: | |
1119 | chip_name = "RTL8187BvD"; | |
1120 | priv->hw_rev = RTL8187BvD; | |
1121 | break; | |
1122 | case RTL818X_R8187B_E: | |
1123 | chip_name = "RTL8187BvE"; | |
1124 | priv->hw_rev = RTL8187BvE; | |
1125 | break; | |
1126 | default: | |
1127 | chip_name = "RTL8187BvB (default)"; | |
1128 | priv->hw_rev = RTL8187BvB; | |
1129 | } | |
1130 | } | |
1131 | ||
f6532111 | 1132 | priv->rf = rtl8187_detect_rf(dev); |
605bebe2 MW |
1133 | |
1134 | err = ieee80211_register_hw(dev); | |
1135 | if (err) { | |
1136 | printk(KERN_ERR "rtl8187: Cannot register device\n"); | |
1137 | goto err_free_dev; | |
1138 | } | |
1139 | ||
6f7853f3 | 1140 | printk(KERN_INFO "%s: hwaddr %s, %s V%d + %s\n", |
0795af57 | 1141 | wiphy_name(dev->wiphy), print_mac(mac, dev->wiphy->perm_addr), |
6f7853f3 | 1142 | chip_name, priv->asic_rev, priv->rf->name); |
605bebe2 MW |
1143 | |
1144 | return 0; | |
1145 | ||
1146 | err_free_dev: | |
1147 | ieee80211_free_hw(dev); | |
1148 | usb_set_intfdata(intf, NULL); | |
1149 | usb_put_dev(udev); | |
1150 | return err; | |
1151 | } | |
1152 | ||
1153 | static void __devexit rtl8187_disconnect(struct usb_interface *intf) | |
1154 | { | |
1155 | struct ieee80211_hw *dev = usb_get_intfdata(intf); | |
1156 | struct rtl8187_priv *priv; | |
1157 | ||
1158 | if (!dev) | |
1159 | return; | |
1160 | ||
1161 | ieee80211_unregister_hw(dev); | |
1162 | ||
1163 | priv = dev->priv; | |
1164 | usb_put_dev(interface_to_usbdev(intf)); | |
1165 | ieee80211_free_hw(dev); | |
1166 | } | |
1167 | ||
1168 | static struct usb_driver rtl8187_driver = { | |
1169 | .name = KBUILD_MODNAME, | |
1170 | .id_table = rtl8187_table, | |
1171 | .probe = rtl8187_probe, | |
1172 | .disconnect = rtl8187_disconnect, | |
1173 | }; | |
1174 | ||
1175 | static int __init rtl8187_init(void) | |
1176 | { | |
1177 | return usb_register(&rtl8187_driver); | |
1178 | } | |
1179 | ||
1180 | static void __exit rtl8187_exit(void) | |
1181 | { | |
1182 | usb_deregister(&rtl8187_driver); | |
1183 | } | |
1184 | ||
1185 | module_init(rtl8187_init); | |
1186 | module_exit(rtl8187_exit); |