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mac80211: allow drivers to set default uAPSD parameters
[deliverable/linux.git] / drivers / net / wireless / rtl818x / rtl8187 / dev.c
CommitLineData
605bebe2
MW		 1/*
2 * Linux device driver for RTL8187
3 *
4 * Copyright 2007 Michael Wu <flamingice@sourmilk.net>
5 * Copyright 2007 Andrea Merello <andreamrl@tiscali.it>
6 *
7 * Based on the r8187 driver, which is:
8 * Copyright 2005 Andrea Merello <andreamrl@tiscali.it>, et al.
9 *
3461fc12 10 * The driver was extended to the RTL8187B in 2008 by:
41b58f18 11 * Herton Ronaldo Krzesinski <herton@mandriva.com.br>
3461fc12
LF		 12 * Hin-Tak Leung <htl10@users.sourceforge.net>
13 * Larry Finger <Larry.Finger@lwfinger.net>
14 *
0aec00ae
JL		 15 * Magic delays and register offsets below are taken from the original
16 * r8187 driver sources. Thanks to Realtek for their support!
605bebe2
MW		 17 *
18 * This program is free software; you can redistribute it and/or modify
19 * it under the terms of the GNU General Public License version 2 as
20 * published by the Free Software Foundation.
21 */
22
23#include <linux/init.h>
24#include <linux/usb.h>
5a0e3ad6 25#include <linux/slab.h>
605bebe2
MW		 26#include <linux/delay.h>
27#include <linux/etherdevice.h>
28#include <linux/eeprom_93cx6.h>
9d9779e7 29#include <linux/module.h>
605bebe2
MW		 30#include <net/mac80211.h>
31
32#include "rtl8187.h"
3cfeb0c3 33#include "rtl8225.h"
a027087a 34#ifdef CONFIG_RTL8187_LEDS
3cfeb0c3 35#include "leds.h"
a027087a 36#endif
3cfeb0c3 37#include "rfkill.h"
605bebe2
MW		 38
39MODULE_AUTHOR("Michael Wu <flamingice@sourmilk.net>");
40MODULE_AUTHOR("Andrea Merello <andreamrl@tiscali.it>");
3461fc12
LF		 41MODULE_AUTHOR("Herton Ronaldo Krzesinski <herton@mandriva.com.br>");
42MODULE_AUTHOR("Hin-Tak Leung <htl10@users.sourceforge.net>");
43MODULE_AUTHOR("Larry Finger <Larry.Finger@lwfinger.net>");
f8a08c34 44MODULE_DESCRIPTION("RTL8187/RTL8187B USB wireless driver");
605bebe2
MW		 45MODULE_LICENSE("GPL");
46
a3433179 47static struct usb_device_id rtl8187_table[] = {
7c7e6af3
AM		 48 /* Asus */
49 {USB_DEVICE(0x0b05, 0x171d), .driver_info = DEVICE_RTL8187},
eaca90da
FF		 50 /* Belkin */
51 {USB_DEVICE(0x050d, 0x705e), .driver_info = DEVICE_RTL8187B},
605bebe2 52 /* Realtek */
f8a08c34
HTL		 53 {USB_DEVICE(0x0bda, 0x8187), .driver_info = DEVICE_RTL8187},
54 {USB_DEVICE(0x0bda, 0x8189), .driver_info = DEVICE_RTL8187B},
55 {USB_DEVICE(0x0bda, 0x8197), .driver_info = DEVICE_RTL8187B},
746db510 56 {USB_DEVICE(0x0bda, 0x8198), .driver_info = DEVICE_RTL8187B},
046ee5d2
LF		 57 /* Surecom */
58 {USB_DEVICE(0x0769, 0x11F2), .driver_info = DEVICE_RTL8187},
59 /* Logitech */
60 {USB_DEVICE(0x0789, 0x010C), .driver_info = DEVICE_RTL8187},
605bebe2 61 /* Netgear */
f8a08c34
HTL		 62 {USB_DEVICE(0x0846, 0x6100), .driver_info = DEVICE_RTL8187},
63 {USB_DEVICE(0x0846, 0x6a00), .driver_info = DEVICE_RTL8187},
fcd7cc14 64 {USB_DEVICE(0x0846, 0x4260), .driver_info = DEVICE_RTL8187B},
c3cf60a9 65 /* HP */
f8a08c34 66 {USB_DEVICE(0x03f0, 0xca02), .driver_info = DEVICE_RTL8187},
9934550d 67 /* Sitecom */
f8a08c34 68 {USB_DEVICE(0x0df6, 0x000d), .driver_info = DEVICE_RTL8187},
f3c76918 69 {USB_DEVICE(0x0df6, 0x0028), .driver_info = DEVICE_RTL8187B},
174b2496 70 {USB_DEVICE(0x0df6, 0x0029), .driver_info = DEVICE_RTL8187B},
046ee5d2
LF		 71 /* Sphairon Access Systems GmbH */
72 {USB_DEVICE(0x114B, 0x0150), .driver_info = DEVICE_RTL8187},
73 /* Dick Smith Electronics */
74 {USB_DEVICE(0x1371, 0x9401), .driver_info = DEVICE_RTL8187},
8f7c41d4
IK		 75 /* Abocom */
76 {USB_DEVICE(0x13d1, 0xabe6), .driver_info = DEVICE_RTL8187},
046ee5d2
LF		 77 /* Qcom */
78 {USB_DEVICE(0x18E8, 0x6232), .driver_info = DEVICE_RTL8187},
79 /* AirLive */
80 {USB_DEVICE(0x1b75, 0x8187), .driver_info = DEVICE_RTL8187},
aeeab4ff
JL		 81 /* Linksys */
82 {USB_DEVICE(0x1737, 0x0073), .driver_info = DEVICE_RTL8187B},
605bebe2
MW		 83 {}
84};
85
86MODULE_DEVICE_TABLE(usb, rtl8187_table);
87
8318d78a
JB		 88static const struct ieee80211_rate rtl818x_rates[] = {
89 { .bitrate = 10, .hw_value = 0, },
90 { .bitrate = 20, .hw_value = 1, },
91 { .bitrate = 55, .hw_value = 2, },
92 { .bitrate = 110, .hw_value = 3, },
93 { .bitrate = 60, .hw_value = 4, },
94 { .bitrate = 90, .hw_value = 5, },
95 { .bitrate = 120, .hw_value = 6, },
96 { .bitrate = 180, .hw_value = 7, },
97 { .bitrate = 240, .hw_value = 8, },
98 { .bitrate = 360, .hw_value = 9, },
99 { .bitrate = 480, .hw_value = 10, },
100 { .bitrate = 540, .hw_value = 11, },
101};
102
103static const struct ieee80211_channel rtl818x_channels[] = {
104 { .center_freq = 2412 },
105 { .center_freq = 2417 },
106 { .center_freq = 2422 },
107 { .center_freq = 2427 },
108 { .center_freq = 2432 },
109 { .center_freq = 2437 },
110 { .center_freq = 2442 },
111 { .center_freq = 2447 },
112 { .center_freq = 2452 },
113 { .center_freq = 2457 },
114 { .center_freq = 2462 },
115 { .center_freq = 2467 },
116 { .center_freq = 2472 },
117 { .center_freq = 2484 },
118};
119
4150c572
JB		 120static void rtl8187_iowrite_async_cb(struct urb *urb)
121{
122 kfree(urb->context);
4150c572
JB		 123}
124
125static void rtl8187_iowrite_async(struct rtl8187_priv *priv, __le16 addr,
126 void *data, u16 len)
127{
128 struct usb_ctrlrequest *dr;
129 struct urb *urb;
130 struct rtl8187_async_write_data {
131 u8 data[4];
132 struct usb_ctrlrequest dr;
133 } *buf;
ea8ee240 134 int rc;
4150c572
JB		 135
136 buf = kmalloc(sizeof(*buf), GFP_ATOMIC);
137 if (!buf)
138 return;
139
140 urb = usb_alloc_urb(0, GFP_ATOMIC);
141 if (!urb) {
142 kfree(buf);
143 return;
144 }
145
146 dr = &buf->dr;
147
148 dr->bRequestType = RTL8187_REQT_WRITE;
149 dr->bRequest = RTL8187_REQ_SET_REG;
150 dr->wValue = addr;
151 dr->wIndex = 0;
152 dr->wLength = cpu_to_le16(len);
153
154 memcpy(buf, data, len);
155
156 usb_fill_control_urb(urb, priv->udev, usb_sndctrlpipe(priv->udev, 0),
157 (unsigned char *)dr, buf, len,
158 rtl8187_iowrite_async_cb, buf);
c1db52b9 159 usb_anchor_urb(urb, &priv->anchored);
ea8ee240
ON		 160 rc = usb_submit_urb(urb, GFP_ATOMIC);
161 if (rc < 0) {
162 kfree(buf);
c1db52b9 163 usb_unanchor_urb(urb);
ea8ee240 164 }
c1db52b9 165 usb_free_urb(urb);
4150c572
JB		 166}
167
168static inline void rtl818x_iowrite32_async(struct rtl8187_priv *priv,
169 __le32 *addr, u32 val)
170{
171 __le32 buf = cpu_to_le32(val);
172
173 rtl8187_iowrite_async(priv, cpu_to_le16((unsigned long)addr),
174 &buf, sizeof(buf));
175}
176
605bebe2
MW		 177void rtl8187_write_phy(struct ieee80211_hw *dev, u8 addr, u32 data)
178{
179 struct rtl8187_priv *priv = dev->priv;
180
181 data <<= 8;
182 data |= addr | 0x80;
183
184 rtl818x_iowrite8(priv, &priv->map->PHY[3], (data >> 24) & 0xFF);
185 rtl818x_iowrite8(priv, &priv->map->PHY[2], (data >> 16) & 0xFF);
186 rtl818x_iowrite8(priv, &priv->map->PHY[1], (data >> 8) & 0xFF);
187 rtl818x_iowrite8(priv, &priv->map->PHY[0], data & 0xFF);
605bebe2
MW		 188}
189
190static void rtl8187_tx_cb(struct urb *urb)
191{
605bebe2 192 struct sk_buff *skb = (struct sk_buff *)urb->context;
e039fa4a 193 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
e6a9854b 194 struct ieee80211_hw *hw = info->rate_driver_data[0];
6f7853f3 195 struct rtl8187_priv *priv = hw->priv;
605bebe2 196
6f7853f3
HTL		 197 skb_pull(skb, priv->is_rtl8187b ? sizeof(struct rtl8187b_tx_hdr) :
198 sizeof(struct rtl8187_tx_hdr));
e6a9854b 199 ieee80211_tx_info_clear_status(info);
3517afde 200
2f47690e
LF		 201 if (!(urb->status) && !(info->flags & IEEE80211_TX_CTL_NO_ACK)) {
202 if (priv->is_rtl8187b) {
203 skb_queue_tail(&priv->b_tx_status.queue, skb);
204
205 /* queue is "full", discard last items */
206 while (skb_queue_len(&priv->b_tx_status.queue) > 5) {
207 struct sk_buff *old_skb;
208
209 dev_dbg(&priv->udev->dev,
210 "transmit status queue full\n");
211
212 old_skb = skb_dequeue(&priv->b_tx_status.queue);
213 ieee80211_tx_status_irqsafe(hw, old_skb);
214 }
215 return;
216 } else {
3517afde 217 info->flags |= IEEE80211_TX_STAT_ACK;
2f47690e
LF		 218 }
219 }
220 if (priv->is_rtl8187b)
3517afde 221 ieee80211_tx_status_irqsafe(hw, skb);
2f47690e
LF		 222 else {
223 /* Retry information for the RTI8187 is only available by
224 * reading a register in the device. We are in interrupt mode
225 * here, thus queue the skb and finish on a work queue. */
226 skb_queue_tail(&priv->b_tx_status.queue, skb);
42935eca 227 ieee80211_queue_delayed_work(hw, &priv->work, 0);
3517afde 228 }
605bebe2
MW		 229}
230
36323f81
TH		 231static void rtl8187_tx(struct ieee80211_hw *dev,
232 struct ieee80211_tx_control *control,
233 struct sk_buff *skb)
605bebe2
MW		 234{
235 struct rtl8187_priv *priv = dev->priv;
e039fa4a 236 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
41b58f18 237 struct ieee80211_hdr *tx_hdr = (struct ieee80211_hdr *)(skb->data);
6f7853f3
HTL		 238 unsigned int ep;
239 void *buf;
605bebe2 240 struct urb *urb;
98798f48
MW		 241 __le16 rts_dur = 0;
242 u32 flags;
ea8ee240 243 int rc;
605bebe2
MW		 244
245 urb = usb_alloc_urb(0, GFP_ATOMIC);
246 if (!urb) {
247 kfree_skb(skb);
7bb45683 248 return;
605bebe2
MW		 249 }
250
98798f48 251 flags = skb->len;
38e3b0d8 252 flags |= RTL818X_TX_DESC_FLAG_NO_ENC;
aa68cbfb 253
e039fa4a 254 flags |= ieee80211_get_tx_rate(dev, info)->hw_value << 24;
41b58f18 255 if (ieee80211_has_morefrags(tx_hdr->frame_control))
38e3b0d8 256 flags |= RTL818X_TX_DESC_FLAG_MOREFRAG;
e6a9854b 257 if (info->control.rates[0].flags & IEEE80211_TX_RC_USE_RTS_CTS) {
38e3b0d8 258 flags |= RTL818X_TX_DESC_FLAG_RTS;
e039fa4a 259 flags |= ieee80211_get_rts_cts_rate(dev, info)->hw_value << 19;
32bfd35d 260 rts_dur = ieee80211_rts_duration(dev, priv->vif,
e039fa4a 261 skb->len, info);
e6a9854b 262 } else if (info->control.rates[0].flags & IEEE80211_TX_RC_USE_CTS_PROTECT) {
38e3b0d8 263 flags |= RTL818X_TX_DESC_FLAG_CTS;
e039fa4a 264 flags |= ieee80211_get_rts_cts_rate(dev, info)->hw_value << 19;
aa68cbfb 265 }
98798f48 266
41b58f18
AF		 267 if (info->flags & IEEE80211_TX_CTL_ASSIGN_SEQ) {
268 if (info->flags & IEEE80211_TX_CTL_FIRST_FRAGMENT)
269 priv->seqno += 0x10;
270 tx_hdr->seq_ctrl &= cpu_to_le16(IEEE80211_SCTL_FRAG);
271 tx_hdr->seq_ctrl |= cpu_to_le16(priv->seqno);
272 }
273
6f7853f3
HTL		 274 if (!priv->is_rtl8187b) {
275 struct rtl8187_tx_hdr *hdr =
276 (struct rtl8187_tx_hdr *)skb_push(skb, sizeof(*hdr));
277 hdr->flags = cpu_to_le32(flags);
278 hdr->len = 0;
279 hdr->rts_duration = rts_dur;
d9a1f486 280 hdr->retry = cpu_to_le32((info->control.rates[0].count - 1) << 8);
6f7853f3
HTL		 281 buf = hdr;
282
283 ep = 2;
284 } else {
285 /* fc needs to be calculated before skb_push() */
286 unsigned int epmap[4] = { 6, 7, 5, 4 };
6f7853f3
HTL		 287 u16 fc = le16_to_cpu(tx_hdr->frame_control);
288
289 struct rtl8187b_tx_hdr *hdr =
290 (struct rtl8187b_tx_hdr *)skb_push(skb, sizeof(*hdr));
291 struct ieee80211_rate *txrate =
292 ieee80211_get_tx_rate(dev, info);
293 memset(hdr, 0, sizeof(*hdr));
294 hdr->flags = cpu_to_le32(flags);
295 hdr->rts_duration = rts_dur;
d9a1f486 296 hdr->retry = cpu_to_le32((info->control.rates[0].count - 1) << 8);
6f7853f3
HTL		 297 hdr->tx_duration =
298 ieee80211_generic_frame_duration(dev, priv->vif,
4ee73f33 299 info->band,
6f7853f3
HTL		 300 skb->len, txrate);
301 buf = hdr;
302
303 if ((fc & IEEE80211_FCTL_FTYPE) == IEEE80211_FTYPE_MGMT)
304 ep = 12;
305 else
306 ep = epmap[skb_get_queue_mapping(skb)];
307 }
605bebe2 308
e6a9854b
JB		 309 info->rate_driver_data[0] = dev;
310 info->rate_driver_data[1] = urb;
6f7853f3
HTL		 311
312 usb_fill_bulk_urb(urb, priv->udev, usb_sndbulkpipe(priv->udev, ep),
313 buf, skb->len, rtl8187_tx_cb, skb);
2fcbab04 314 urb->transfer_flags |= URB_ZERO_PACKET;
c1db52b9 315 usb_anchor_urb(urb, &priv->anchored);
ea8ee240
ON		 316 rc = usb_submit_urb(urb, GFP_ATOMIC);
317 if (rc < 0) {
c1db52b9 318 usb_unanchor_urb(urb);
ea8ee240
ON		 319 kfree_skb(skb);
320 }
c1db52b9 321 usb_free_urb(urb);
605bebe2
MW		 322}
323
324static void rtl8187_rx_cb(struct urb *urb)
325{
326 struct sk_buff *skb = (struct sk_buff *)urb->context;
327 struct rtl8187_rx_info *info = (struct rtl8187_rx_info *)skb->cb;
328 struct ieee80211_hw *dev = info->dev;
329 struct rtl8187_priv *priv = dev->priv;
605bebe2
MW		 330 struct ieee80211_rx_status rx_status = { 0 };
331 int rate, signal;
4150c572 332 u32 flags;
d8588227 333 unsigned long f;
605bebe2 334
d8588227 335 spin_lock_irqsave(&priv->rx_queue.lock, f);
46c37672 336 __skb_unlink(skb, &priv->rx_queue);
d8588227 337 spin_unlock_irqrestore(&priv->rx_queue.lock, f);
c1db52b9 338 skb_put(skb, urb->actual_length);
605bebe2
MW		 339
340 if (unlikely(urb->status)) {
605bebe2
MW		 341 dev_kfree_skb_irq(skb);
342 return;
343 }
344
6f7853f3
HTL		 345 if (!priv->is_rtl8187b) {
346 struct rtl8187_rx_hdr *hdr =
347 (typeof(hdr))(skb_tail_pointer(skb) - sizeof(*hdr));
348 flags = le32_to_cpu(hdr->flags);
a7db74f4 349 /* As with the RTL8187B below, the AGC is used to calculate
70d9f405 350 * signal strength. In this case, the scaling
a7db74f4
LF		 351 * constants are derived from the output of p54usb.
352 */
a7db74f4 353 signal = -4 - ((27 * hdr->agc) >> 6);
6f7853f3 354 rx_status.antenna = (hdr->signal >> 7) & 1;
6f7853f3 355 rx_status.mactime = le64_to_cpu(hdr->mac_time);
6f7853f3
HTL		 356 } else {
357 struct rtl8187b_rx_hdr *hdr =
358 (typeof(hdr))(skb_tail_pointer(skb) - sizeof(*hdr));
0ccd58fc
LF		 359 /* The Realtek datasheet for the RTL8187B shows that the RX
360 * header contains the following quantities: signal quality,
361 * RSSI, AGC, the received power in dB, and the measured SNR.
362 * In testing, none of these quantities show qualitative
363 * agreement with AP signal strength, except for the AGC,
364 * which is inversely proportional to the strength of the
70d9f405
LF		 365 * signal. In the following, the signal strength
366 * is derived from the AGC. The arbitrary scaling constants
0ccd58fc
LF		 367 * are chosen to make the results close to the values obtained
368 * for a BCM4312 using b43 as the driver. The noise is ignored
369 * for now.
370 */
6f7853f3 371 flags = le32_to_cpu(hdr->flags);
0ccd58fc 372 signal = 14 - hdr->agc / 2;
0ccd58fc 373 rx_status.antenna = (hdr->rssi >> 7) & 1;
6f7853f3 374 rx_status.mactime = le64_to_cpu(hdr->mac_time);
6f7853f3 375 }
605bebe2 376
a7db74f4
LF		 377 rx_status.signal = signal;
378 priv->signal = signal;
379 rate = (flags >> 20) & 0xF;
6f7853f3 380 skb_trim(skb, flags & 0x0FFF);
8318d78a
JB		 381 rx_status.rate_idx = rate;
382 rx_status.freq = dev->conf.channel->center_freq;
383 rx_status.band = dev->conf.channel->band;
f4bda337 384 rx_status.flag |= RX_FLAG_MACTIME_START;
38e3b0d8 385 if (flags & RTL818X_RX_DESC_FLAG_CRC32_ERR)
4150c572 386 rx_status.flag |= RX_FLAG_FAILED_FCS_CRC;
f1d58c25
JB		 387 memcpy(IEEE80211_SKB_RXCB(skb), &rx_status, sizeof(rx_status));
388 ieee80211_rx_irqsafe(dev, skb);
605bebe2
MW		 389
390 skb = dev_alloc_skb(RTL8187_MAX_RX);
391 if (unlikely(!skb)) {
605bebe2
MW		 392 /* TODO check rx queue length and refill *somewhere* */
393 return;
394 }
395
396 info = (struct rtl8187_rx_info *)skb->cb;
397 info->urb = urb;
398 info->dev = dev;
399 urb->transfer_buffer = skb_tail_pointer(skb);
400 urb->context = skb;
401 skb_queue_tail(&priv->rx_queue, skb);
402
c1db52b9
LF		 403 usb_anchor_urb(urb, &priv->anchored);
404 if (usb_submit_urb(urb, GFP_ATOMIC)) {
405 usb_unanchor_urb(urb);
406 skb_unlink(skb, &priv->rx_queue);
407 dev_kfree_skb_irq(skb);
408 }
605bebe2
MW		 409}
410
411static int rtl8187_init_urbs(struct ieee80211_hw *dev)
412{
413 struct rtl8187_priv *priv = dev->priv;
c1db52b9 414 struct urb *entry = NULL;
605bebe2
MW		 415 struct sk_buff *skb;
416 struct rtl8187_rx_info *info;
c1db52b9 417 int ret = 0;
605bebe2 418
2a57cf3e 419 while (skb_queue_len(&priv->rx_queue) < 16) {
605bebe2 420 skb = __dev_alloc_skb(RTL8187_MAX_RX, GFP_KERNEL);
c1db52b9
LF		 421 if (!skb) {
422 ret = -ENOMEM;
423 goto err;
424 }
605bebe2
MW		 425 entry = usb_alloc_urb(0, GFP_KERNEL);
426 if (!entry) {
c1db52b9
LF		 427 ret = -ENOMEM;
428 goto err;
605bebe2
MW		 429 }
430 usb_fill_bulk_urb(entry, priv->udev,
6f7853f3
HTL		 431 usb_rcvbulkpipe(priv->udev,
432 priv->is_rtl8187b ? 3 : 1),
605bebe2
MW		 433 skb_tail_pointer(skb),
434 RTL8187_MAX_RX, rtl8187_rx_cb, skb);
435 info = (struct rtl8187_rx_info *)skb->cb;
436 info->urb = entry;
437 info->dev = dev;
438 skb_queue_tail(&priv->rx_queue, skb);
c1db52b9
LF		 439 usb_anchor_urb(entry, &priv->anchored);
440 ret = usb_submit_urb(entry, GFP_KERNEL);
441 if (ret) {
442 skb_unlink(skb, &priv->rx_queue);
443 usb_unanchor_urb(entry);
444 goto err;
445 }
446 usb_free_urb(entry);
605bebe2 447 }
c1db52b9 448 return ret;
605bebe2 449
c1db52b9
LF		 450err:
451 usb_free_urb(entry);
452 kfree_skb(skb);
453 usb_kill_anchored_urbs(&priv->anchored);
454 return ret;
605bebe2
MW		 455}
456
3517afde
HRK		 457static void rtl8187b_status_cb(struct urb *urb)
458{
459 struct ieee80211_hw *hw = (struct ieee80211_hw *)urb->context;
460 struct rtl8187_priv *priv = hw->priv;
461 u64 val;
462 unsigned int cmd_type;
463
c1db52b9 464 if (unlikely(urb->status))
3517afde 465 return;
3517afde
HRK		 466
467 /*
468 * Read from status buffer:
469 *
470 * bits [30:31] = cmd type:
471 * - 0 indicates tx beacon interrupt
472 * - 1 indicates tx close descriptor
473 *
474 * In the case of tx beacon interrupt:
475 * [0:9] = Last Beacon CW
476 * [10:29] = reserved
477 * [30:31] = 00b
478 * [32:63] = Last Beacon TSF
479 *
480 * If it's tx close descriptor:
481 * [0:7] = Packet Retry Count
482 * [8:14] = RTS Retry Count
483 * [15] = TOK
484 * [16:27] = Sequence No
485 * [28] = LS
486 * [29] = FS
487 * [30:31] = 01b
488 * [32:47] = unused (reserved?)
489 * [48:63] = MAC Used Time
490 */
491 val = le64_to_cpu(priv->b_tx_status.buf);
492
493 cmd_type = (val >> 30) & 0x3;
494 if (cmd_type == 1) {
495 unsigned int pkt_rc, seq_no;
496 bool tok;
497 struct sk_buff *skb;
498 struct ieee80211_hdr *ieee80211hdr;
499 unsigned long flags;
500
501 pkt_rc = val & 0xFF;
502 tok = val & (1 << 15);
503 seq_no = (val >> 16) & 0xFFF;
504
505 spin_lock_irqsave(&priv->b_tx_status.queue.lock, flags);
506 skb_queue_reverse_walk(&priv->b_tx_status.queue, skb) {
507 ieee80211hdr = (struct ieee80211_hdr *)skb->data;
508
509 /*
510 * While testing, it was discovered that the seq_no
511 * doesn't actually contains the sequence number.
512 * Instead of returning just the 12 bits of sequence
513 * number, hardware is returning entire sequence control
514 * (fragment number plus sequence number) in a 12 bit
515 * only field overflowing after some time. As a
516 * workaround, just consider the lower bits, and expect
517 * it's unlikely we wrongly ack some sent data
518 */
519 if ((le16_to_cpu(ieee80211hdr->seq_ctrl)
520 & 0xFFF) == seq_no)
521 break;
522 }
523 if (skb != (struct sk_buff *) &priv->b_tx_status.queue) {
524 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
525
526 __skb_unlink(skb, &priv->b_tx_status.queue);
527 if (tok)
528 info->flags |= IEEE80211_TX_STAT_ACK;
1548c86a 529 info->status.rates[0].count = pkt_rc + 1;
3517afde
HRK		 530
531 ieee80211_tx_status_irqsafe(hw, skb);
532 }
533 spin_unlock_irqrestore(&priv->b_tx_status.queue.lock, flags);
534 }
535
c1db52b9
LF		 536 usb_anchor_urb(urb, &priv->anchored);
537 if (usb_submit_urb(urb, GFP_ATOMIC))
538 usb_unanchor_urb(urb);
3517afde
HRK		 539}
540
541static int rtl8187b_init_status_urb(struct ieee80211_hw *dev)
542{
543 struct rtl8187_priv *priv = dev->priv;
544 struct urb *entry;
c1db52b9 545 int ret = 0;
3517afde
HRK		 546
547 entry = usb_alloc_urb(0, GFP_KERNEL);
548 if (!entry)
549 return -ENOMEM;
3517afde
HRK		 550
551 usb_fill_bulk_urb(entry, priv->udev, usb_rcvbulkpipe(priv->udev, 9),
552 &priv->b_tx_status.buf, sizeof(priv->b_tx_status.buf),
553 rtl8187b_status_cb, dev);
554
c1db52b9
LF		 555 usb_anchor_urb(entry, &priv->anchored);
556 ret = usb_submit_urb(entry, GFP_KERNEL);
557 if (ret)
558 usb_unanchor_urb(entry);
559 usb_free_urb(entry);
3517afde 560
c1db52b9 561 return ret;
3517afde
HRK		 562}
563
0bf198eb
HRK		 564static void rtl8187_set_anaparam(struct rtl8187_priv *priv, bool rfon)
565{
566 u32 anaparam, anaparam2;
567 u8 anaparam3, reg;
568
569 if (!priv->is_rtl8187b) {
570 if (rfon) {
571 anaparam = RTL8187_RTL8225_ANAPARAM_ON;
572 anaparam2 = RTL8187_RTL8225_ANAPARAM2_ON;
573 } else {
574 anaparam = RTL8187_RTL8225_ANAPARAM_OFF;
575 anaparam2 = RTL8187_RTL8225_ANAPARAM2_OFF;
576 }
577 } else {
578 if (rfon) {
579 anaparam = RTL8187B_RTL8225_ANAPARAM_ON;
580 anaparam2 = RTL8187B_RTL8225_ANAPARAM2_ON;
581 anaparam3 = RTL8187B_RTL8225_ANAPARAM3_ON;
582 } else {
583 anaparam = RTL8187B_RTL8225_ANAPARAM_OFF;
584 anaparam2 = RTL8187B_RTL8225_ANAPARAM2_OFF;
585 anaparam3 = RTL8187B_RTL8225_ANAPARAM3_OFF;
586 }
587 }
588
589 rtl818x_iowrite8(priv, &priv->map->EEPROM_CMD,
590 RTL818X_EEPROM_CMD_CONFIG);
591 reg = rtl818x_ioread8(priv, &priv->map->CONFIG3);
592 reg |= RTL818X_CONFIG3_ANAPARAM_WRITE;
593 rtl818x_iowrite8(priv, &priv->map->CONFIG3, reg);
594 rtl818x_iowrite32(priv, &priv->map->ANAPARAM, anaparam);
595 rtl818x_iowrite32(priv, &priv->map->ANAPARAM2, anaparam2);
596 if (priv->is_rtl8187b)
597 rtl818x_iowrite8(priv, &priv->map->ANAPARAM3, anaparam3);
598 reg &= ~RTL818X_CONFIG3_ANAPARAM_WRITE;
599 rtl818x_iowrite8(priv, &priv->map->CONFIG3, reg);
600 rtl818x_iowrite8(priv, &priv->map->EEPROM_CMD,
601 RTL818X_EEPROM_CMD_NORMAL);
602}
603
f8a08c34 604static int rtl8187_cmd_reset(struct ieee80211_hw *dev)
605bebe2
MW		 605{
606 struct rtl8187_priv *priv = dev->priv;
607 u8 reg;
608 int i;
609
605bebe2
MW		 610 reg = rtl818x_ioread8(priv, &priv->map->CMD);
611 reg &= (1 << 1);
612 reg |= RTL818X_CMD_RESET;
613 rtl818x_iowrite8(priv, &priv->map->CMD, reg);
614
615 i = 10;
616 do {
617 msleep(2);
618 if (!(rtl818x_ioread8(priv, &priv->map->CMD) &
619 RTL818X_CMD_RESET))
620 break;
621 } while (--i);
622
623 if (!i) {
5db55844 624 wiphy_err(dev->wiphy, "Reset timeout!\n");
605bebe2
MW		 625 return -ETIMEDOUT;
626 }
627
628 /* reload registers from eeprom */
629 rtl818x_iowrite8(priv, &priv->map->EEPROM_CMD, RTL818X_EEPROM_CMD_LOAD);
630
631 i = 10;
632 do {
633 msleep(4);
634 if (!(rtl818x_ioread8(priv, &priv->map->EEPROM_CMD) &
635 RTL818X_EEPROM_CMD_CONFIG))
636 break;
637 } while (--i);
638
639 if (!i) {
c96c31e4 640 wiphy_err(dev->wiphy, "eeprom reset timeout!\n");
605bebe2
MW		 641 return -ETIMEDOUT;
642 }
643
f8a08c34
HTL		 644 return 0;
645}
646
647static int rtl8187_init_hw(struct ieee80211_hw *dev)
648{
649 struct rtl8187_priv *priv = dev->priv;
650 u8 reg;
651 int res;
652
653 /* reset */
0bf198eb 654 rtl8187_set_anaparam(priv, true);
f8a08c34
HTL		 655
656 rtl818x_iowrite16(priv, &priv->map->INT_MASK, 0);
657
658 msleep(200);
659 rtl818x_iowrite8(priv, (u8 *)0xFE18, 0x10);
660 rtl818x_iowrite8(priv, (u8 *)0xFE18, 0x11);
661 rtl818x_iowrite8(priv, (u8 *)0xFE18, 0x00);
662 msleep(200);
663
664 res = rtl8187_cmd_reset(dev);
665 if (res)
666 return res;
667
0bf198eb 668 rtl8187_set_anaparam(priv, true);
605bebe2
MW		 669
670 /* setup card */
671 rtl818x_iowrite16(priv, &priv->map->RFPinsSelect, 0);
ca9152e3 672 rtl818x_iowrite8(priv, &priv->map->GPIO0, 0);
605bebe2
MW		 673
674 rtl818x_iowrite16(priv, &priv->map->RFPinsSelect, (4 << 8));
ca9152e3 675 rtl818x_iowrite8(priv, &priv->map->GPIO0, 1);
605bebe2
MW		 676 rtl818x_iowrite8(priv, &priv->map->GP_ENABLE, 0);
677
678 rtl818x_iowrite8(priv, &priv->map->EEPROM_CMD, RTL818X_EEPROM_CMD_CONFIG);
605bebe2
MW		 679
680 rtl818x_iowrite16(priv, (__le16 *)0xFFF4, 0xFFFF);
681 reg = rtl818x_ioread8(priv, &priv->map->CONFIG1);
682 reg &= 0x3F;
683 reg |= 0x80;
684 rtl818x_iowrite8(priv, &priv->map->CONFIG1, reg);
685
686 rtl818x_iowrite8(priv, &priv->map->EEPROM_CMD, RTL818X_EEPROM_CMD_NORMAL);
687
688 rtl818x_iowrite32(priv, &priv->map->INT_TIMEOUT, 0);
689 rtl818x_iowrite8(priv, &priv->map->WPA_CONF, 0);
2f47690e 690 rtl818x_iowrite8(priv, &priv->map->RATE_FALLBACK, 0);
605bebe2
MW		 691
692 // TODO: set RESP_RATE and BRSR properly
693 rtl818x_iowrite8(priv, &priv->map->RESP_RATE, (8 << 4) | 0);
694 rtl818x_iowrite16(priv, &priv->map->BRSR, 0x01F3);
695
696 /* host_usb_init */
697 rtl818x_iowrite16(priv, &priv->map->RFPinsSelect, 0);
ca9152e3 698 rtl818x_iowrite8(priv, &priv->map->GPIO0, 0);
605bebe2
MW		 699 reg = rtl818x_ioread8(priv, (u8 *)0xFE53);
700 rtl818x_iowrite8(priv, (u8 *)0xFE53, reg | (1 << 7));
701 rtl818x_iowrite16(priv, &priv->map->RFPinsSelect, (4 << 8));
ca9152e3 702 rtl818x_iowrite8(priv, &priv->map->GPIO0, 0x20);
605bebe2
MW		 703 rtl818x_iowrite8(priv, &priv->map->GP_ENABLE, 0);
704 rtl818x_iowrite16(priv, &priv->map->RFPinsOutput, 0x80);
705 rtl818x_iowrite16(priv, &priv->map->RFPinsSelect, 0x80);
706 rtl818x_iowrite16(priv, &priv->map->RFPinsEnable, 0x80);
707 msleep(100);
708
709 rtl818x_iowrite32(priv, &priv->map->RF_TIMING, 0x000a8008);
710 rtl818x_iowrite16(priv, &priv->map->BRSR, 0xFFFF);
711 rtl818x_iowrite32(priv, &priv->map->RF_PARA, 0x00100044);
f8a08c34
HTL		 712 rtl818x_iowrite8(priv, &priv->map->EEPROM_CMD,
713 RTL818X_EEPROM_CMD_CONFIG);
605bebe2 714 rtl818x_iowrite8(priv, &priv->map->CONFIG3, 0x44);
f8a08c34
HTL		 715 rtl818x_iowrite8(priv, &priv->map->EEPROM_CMD,
716 RTL818X_EEPROM_CMD_NORMAL);
605bebe2
MW		 717 rtl818x_iowrite16(priv, &priv->map->RFPinsEnable, 0x1FF7);
718 msleep(100);
719
f6532111 720 priv->rf->init(dev);
605bebe2
MW		 721
722 rtl818x_iowrite16(priv, &priv->map->BRSR, 0x01F3);
f6532111
MW		 723 reg = rtl818x_ioread8(priv, &priv->map->PGSELECT) & ~1;
724 rtl818x_iowrite8(priv, &priv->map->PGSELECT, reg | 1);
605bebe2
MW		 725 rtl818x_iowrite16(priv, (__le16 *)0xFFFE, 0x10);
726 rtl818x_iowrite8(priv, &priv->map->TALLY_SEL, 0x80);
727 rtl818x_iowrite8(priv, (u8 *)0xFFFF, 0x60);
f6532111 728 rtl818x_iowrite8(priv, &priv->map->PGSELECT, reg);
605bebe2
MW		 729
730 return 0;
731}
732
f8a08c34
HTL		 733static const u8 rtl8187b_reg_table[][3] = {
734 {0xF0, 0x32, 0}, {0xF1, 0x32, 0}, {0xF2, 0x00, 0}, {0xF3, 0x00, 0},
735 {0xF4, 0x32, 0}, {0xF5, 0x43, 0}, {0xF6, 0x00, 0}, {0xF7, 0x00, 0},
736 {0xF8, 0x46, 0}, {0xF9, 0xA4, 0}, {0xFA, 0x00, 0}, {0xFB, 0x00, 0},
737 {0xFC, 0x96, 0}, {0xFD, 0xA4, 0}, {0xFE, 0x00, 0}, {0xFF, 0x00, 0},
738
739 {0x58, 0x4B, 1}, {0x59, 0x00, 1}, {0x5A, 0x4B, 1}, {0x5B, 0x00, 1},
740 {0x60, 0x4B, 1}, {0x61, 0x09, 1}, {0x62, 0x4B, 1}, {0x63, 0x09, 1},
327571ea
HRK		 741 {0xCE, 0x0F, 1}, {0xCF, 0x00, 1}, {0xF0, 0x4E, 1}, {0xF1, 0x01, 1},
742 {0xF2, 0x02, 1}, {0xF3, 0x03, 1}, {0xF4, 0x04, 1}, {0xF5, 0x05, 1},
743 {0xF6, 0x06, 1}, {0xF7, 0x07, 1}, {0xF8, 0x08, 1},
f8a08c34
HTL		 744
745 {0x4E, 0x00, 2}, {0x0C, 0x04, 2}, {0x21, 0x61, 2}, {0x22, 0x68, 2},
746 {0x23, 0x6F, 2}, {0x24, 0x76, 2}, {0x25, 0x7D, 2}, {0x26, 0x84, 2},
747 {0x27, 0x8D, 2}, {0x4D, 0x08, 2}, {0x50, 0x05, 2}, {0x51, 0xF5, 2},
748 {0x52, 0x04, 2}, {0x53, 0xA0, 2}, {0x54, 0x1F, 2}, {0x55, 0x23, 2},
749 {0x56, 0x45, 2}, {0x57, 0x67, 2}, {0x58, 0x08, 2}, {0x59, 0x08, 2},
750 {0x5A, 0x08, 2}, {0x5B, 0x08, 2}, {0x60, 0x08, 2}, {0x61, 0x08, 2},
a8ff34e3 751 {0x62, 0x08, 2}, {0x63, 0x08, 2}, {0x64, 0xCF, 2},
f8a08c34 752
60f58914
HRK		 753 {0x5B, 0x40, 0}, {0x84, 0x88, 0}, {0x85, 0x24, 0}, {0x88, 0x54, 0},
754 {0x8B, 0xB8, 0}, {0x8C, 0x07, 0}, {0x8D, 0x00, 0}, {0x94, 0x1B, 0},
755 {0x95, 0x12, 0}, {0x96, 0x00, 0}, {0x97, 0x06, 0}, {0x9D, 0x1A, 0},
756 {0x9F, 0x10, 0}, {0xB4, 0x22, 0}, {0xBE, 0x80, 0}, {0xDB, 0x00, 0},
757 {0xEE, 0x00, 0}, {0x4C, 0x00, 2},
f8a08c34 758
a027087a
LF		 759 {0x9F, 0x00, 3}, {0x8C, 0x01, 0}, {0x8D, 0x10, 0}, {0x8E, 0x08, 0},
760 {0x8F, 0x00, 0}
f8a08c34
HTL		 761};
762
763static int rtl8187b_init_hw(struct ieee80211_hw *dev)
764{
765 struct rtl8187_priv *priv = dev->priv;
766 int res, i;
767 u8 reg;
768
0bf198eb 769 rtl8187_set_anaparam(priv, true);
f8a08c34 770
896cae65
HRK		 771 /* Reset PLL sequence on 8187B. Realtek note: reduces power
772 * consumption about 30 mA */
773 rtl818x_iowrite8(priv, (u8 *)0xFF61, 0x10);
774 reg = rtl818x_ioread8(priv, (u8 *)0xFF62);
775 rtl818x_iowrite8(priv, (u8 *)0xFF62, reg & ~(1 << 5));
776 rtl818x_iowrite8(priv, (u8 *)0xFF62, reg | (1 << 5));
777
f8a08c34
HTL		 778 res = rtl8187_cmd_reset(dev);
779 if (res)
780 return res;
781
daeeb074
HRK		 782 rtl8187_set_anaparam(priv, true);
783
60f58914
HRK		 784 /* BRSR (Basic Rate Set Register) on 8187B looks to be the same as
785 * RESP_RATE on 8187L in Realtek sources: each bit should be each
786 * one of the 12 rates, all are enabled */
787 rtl818x_iowrite16(priv, (__le16 *)0xFF34, 0x0FFF);
788
f8a08c34
HTL		 789 reg = rtl818x_ioread8(priv, &priv->map->CW_CONF);
790 reg |= RTL818X_CW_CONF_PERPACKET_RETRY_SHIFT;
791 rtl818x_iowrite8(priv, &priv->map->CW_CONF, reg);
f8a08c34 792
327571ea 793 /* Auto Rate Fallback Register (ARFR): 1M-54M setting */
f8a08c34 794 rtl818x_iowrite16_idx(priv, (__le16 *)0xFFE0, 0x0FFF, 1);
327571ea 795 rtl818x_iowrite8_idx(priv, (u8 *)0xFFE2, 0x00, 1);
f8a08c34 796
f8a08c34
HTL		 797 rtl818x_iowrite16_idx(priv, (__le16 *)0xFFD4, 0xFFFF, 1);
798
799 rtl818x_iowrite8(priv, &priv->map->EEPROM_CMD,
800 RTL818X_EEPROM_CMD_CONFIG);
801 reg = rtl818x_ioread8(priv, &priv->map->CONFIG1);
802 rtl818x_iowrite8(priv, &priv->map->CONFIG1, (reg & 0x3F) | 0x80);
803 rtl818x_iowrite8(priv, &priv->map->EEPROM_CMD,
804 RTL818X_EEPROM_CMD_NORMAL);
805
806 rtl818x_iowrite8(priv, &priv->map->WPA_CONF, 0);
807 for (i = 0; i < ARRAY_SIZE(rtl8187b_reg_table); i++) {
808 rtl818x_iowrite8_idx(priv,
809 (u8 *)(uintptr_t)
810 (rtl8187b_reg_table[i][0] | 0xFF00),
811 rtl8187b_reg_table[i][1],
812 rtl8187b_reg_table[i][2]);
813 }
814
815 rtl818x_iowrite16(priv, &priv->map->TID_AC_MAP, 0xFA50);
816 rtl818x_iowrite16(priv, &priv->map->INT_MIG, 0);
817
818 rtl818x_iowrite32_idx(priv, (__le32 *)0xFFF0, 0, 1);
819 rtl818x_iowrite32_idx(priv, (__le32 *)0xFFF4, 0, 1);
820 rtl818x_iowrite8_idx(priv, (u8 *)0xFFF8, 0, 1);
821
822 rtl818x_iowrite32(priv, &priv->map->RF_TIMING, 0x00004001);
823
a8ff34e3 824 /* RFSW_CTRL register */
f8a08c34
HTL		 825 rtl818x_iowrite16_idx(priv, (__le16 *)0xFF72, 0x569A, 2);
826
f8a08c34
HTL		 827 rtl818x_iowrite16(priv, &priv->map->RFPinsOutput, 0x0480);
828 rtl818x_iowrite16(priv, &priv->map->RFPinsSelect, 0x2488);
829 rtl818x_iowrite16(priv, &priv->map->RFPinsEnable, 0x1FFF);
2f20596b 830 msleep(100);
f8a08c34
HTL		 831
832 priv->rf->init(dev);
833
834 reg = RTL818X_CMD_TX_ENABLE | RTL818X_CMD_RX_ENABLE;
835 rtl818x_iowrite8(priv, &priv->map->CMD, reg);
836 rtl818x_iowrite16(priv, &priv->map->INT_MASK, 0xFFFF);
837
838 rtl818x_iowrite8(priv, (u8 *)0xFE41, 0xF4);
839 rtl818x_iowrite8(priv, (u8 *)0xFE40, 0x00);
840 rtl818x_iowrite8(priv, (u8 *)0xFE42, 0x00);
841 rtl818x_iowrite8(priv, (u8 *)0xFE42, 0x01);
842 rtl818x_iowrite8(priv, (u8 *)0xFE40, 0x0F);
843 rtl818x_iowrite8(priv, (u8 *)0xFE42, 0x00);
844 rtl818x_iowrite8(priv, (u8 *)0xFE42, 0x01);
845
846 reg = rtl818x_ioread8(priv, (u8 *)0xFFDB);
847 rtl818x_iowrite8(priv, (u8 *)0xFFDB, reg | (1 << 2));
848 rtl818x_iowrite16_idx(priv, (__le16 *)0xFF72, 0x59FA, 3);
849 rtl818x_iowrite16_idx(priv, (__le16 *)0xFF74, 0x59D2, 3);
850 rtl818x_iowrite16_idx(priv, (__le16 *)0xFF76, 0x59D2, 3);
851 rtl818x_iowrite16_idx(priv, (__le16 *)0xFF78, 0x19FA, 3);
852 rtl818x_iowrite16_idx(priv, (__le16 *)0xFF7A, 0x19FA, 3);
853 rtl818x_iowrite16_idx(priv, (__le16 *)0xFF7C, 0x00D0, 3);
854 rtl818x_iowrite8(priv, (u8 *)0xFF61, 0);
855 rtl818x_iowrite8_idx(priv, (u8 *)0xFF80, 0x0F, 1);
856 rtl818x_iowrite8_idx(priv, (u8 *)0xFF83, 0x03, 1);
857 rtl818x_iowrite8(priv, (u8 *)0xFFDA, 0x10);
858 rtl818x_iowrite8_idx(priv, (u8 *)0xFF4D, 0x08, 2);
859
860 rtl818x_iowrite32(priv, &priv->map->HSSI_PARA, 0x0600321B);
861
862 rtl818x_iowrite16_idx(priv, (__le16 *)0xFFEC, 0x0800, 1);
863
b4572a92
HRK		 864 priv->slot_time = 0x9;
865 priv->aifsn[0] = 2; /* AIFSN[AC_VO] */
866 priv->aifsn[1] = 2; /* AIFSN[AC_VI] */
867 priv->aifsn[2] = 7; /* AIFSN[AC_BK] */
868 priv->aifsn[3] = 3; /* AIFSN[AC_BE] */
869 rtl818x_iowrite8(priv, &priv->map->ACM_CONTROL, 0);
870
1a9937b7
HRK		 871 /* ENEDCA flag must always be set, transmit issues? */
872 rtl818x_iowrite8(priv, &priv->map->MSR, RTL818X_MSR_ENEDCA);
873
f8a08c34
HTL		 874 return 0;
875}
876
2f47690e
LF		 877static void rtl8187_work(struct work_struct *work)
878{
879 /* The RTL8187 returns the retry count through register 0xFFFA. In
880 * addition, it appears to be a cumulative retry count, not the
881 * value for the current TX packet. When multiple TX entries are
6410db59
LF		 882 * waiting in the queue, the retry count will be the total for all.
883 * The "error" may matter for purposes of rate setting, but there is
884 * no other choice with this hardware.
885 */
2f47690e
LF		 886 struct rtl8187_priv *priv = container_of(work, struct rtl8187_priv,
887 work.work);
888 struct ieee80211_tx_info *info;
889 struct ieee80211_hw *dev = priv->dev;
890 static u16 retry;
891 u16 tmp;
6410db59
LF		 892 u16 avg_retry;
893 int length;
2f47690e
LF		 894
895 mutex_lock(&priv->conf_mutex);
896 tmp = rtl818x_ioread16(priv, (__le16 *)0xFFFA);
6410db59
LF		 897 length = skb_queue_len(&priv->b_tx_status.queue);
898 if (unlikely(!length))
899 length = 1;
900 if (unlikely(tmp < retry))
901 tmp = retry;
902 avg_retry = (tmp - retry) / length;
2f47690e
LF		 903 while (skb_queue_len(&priv->b_tx_status.queue) > 0) {
904 struct sk_buff *old_skb;
905
906 old_skb = skb_dequeue(&priv->b_tx_status.queue);
907 info = IEEE80211_SKB_CB(old_skb);
6410db59
LF		 908 info->status.rates[0].count = avg_retry + 1;
909 if (info->status.rates[0].count > RETRY_COUNT)
910 info->flags &= ~IEEE80211_TX_STAT_ACK;
2f47690e
LF		 911 ieee80211_tx_status_irqsafe(dev, old_skb);
912 }
913 retry = tmp;
914 mutex_unlock(&priv->conf_mutex);
915}
916
4150c572 917static int rtl8187_start(struct ieee80211_hw *dev)
605bebe2
MW		 918{
919 struct rtl8187_priv *priv = dev->priv;
920 u32 reg;
921 int ret;
922
ca9152e3
HRK		 923 mutex_lock(&priv->conf_mutex);
924
f8a08c34
HTL		 925 ret = (!priv->is_rtl8187b) ? rtl8187_init_hw(dev) :
926 rtl8187b_init_hw(dev);
605bebe2 927 if (ret)
ca9152e3 928 goto rtl8187_start_exit;
c1db52b9
LF		 929
930 init_usb_anchor(&priv->anchored);
2f47690e 931 priv->dev = dev;
c1db52b9 932
f8a08c34
HTL		 933 if (priv->is_rtl8187b) {
934 reg = RTL818X_RX_CONF_MGMT |
935 RTL818X_RX_CONF_DATA |
936 RTL818X_RX_CONF_BROADCAST |
937 RTL818X_RX_CONF_NICMAC |
938 RTL818X_RX_CONF_BSSID |
939 (7 << 13 /* RX FIFO threshold NONE */) |
940 (7 << 10 /* MAX RX DMA */) |
941 RTL818X_RX_CONF_RX_AUTORESETPHY |
942 RTL818X_RX_CONF_ONLYERLPKT |
943 RTL818X_RX_CONF_MULTICAST;
944 priv->rx_conf = reg;
945 rtl818x_iowrite32(priv, &priv->map->RX_CONF, reg);
946
19999792
TLSC		 947 reg = rtl818x_ioread8(priv, &priv->map->TX_AGC_CTL);
948 reg &= ~RTL818X_TX_AGC_CTL_PERPACKET_GAIN_SHIFT;
949 reg &= ~RTL818X_TX_AGC_CTL_PERPACKET_ANTSEL_SHIFT;
950 reg &= ~RTL818X_TX_AGC_CTL_FEEDBACK_ANT;
951 rtl818x_iowrite8(priv, &priv->map->TX_AGC_CTL, reg);
952
f8a08c34
HTL		 953 rtl818x_iowrite32(priv, &priv->map->TX_CONF,
954 RTL818X_TX_CONF_HW_SEQNUM |
955 RTL818X_TX_CONF_DISREQQSIZE |
6410db59
LF		 956 (RETRY_COUNT << 8 /* short retry limit */) |
957 (RETRY_COUNT << 0 /* long retry limit */) |
f8a08c34
HTL		 958 (7 << 21 /* MAX TX DMA */));
959 rtl8187_init_urbs(dev);
3517afde 960 rtl8187b_init_status_urb(dev);
ca9152e3 961 goto rtl8187_start_exit;
f8a08c34
HTL		 962 }
963
605bebe2
MW		 964 rtl818x_iowrite16(priv, &priv->map->INT_MASK, 0xFFFF);
965
2fe14263
MW		 966 rtl818x_iowrite32(priv, &priv->map->MAR[0], ~0);
967 rtl818x_iowrite32(priv, &priv->map->MAR[1], ~0);
968
605bebe2
MW		 969 rtl8187_init_urbs(dev);
970
971 reg = RTL818X_RX_CONF_ONLYERLPKT |
972 RTL818X_RX_CONF_RX_AUTORESETPHY |
973 RTL818X_RX_CONF_BSSID |
974 RTL818X_RX_CONF_MGMT |
605bebe2
MW		 975 RTL818X_RX_CONF_DATA |
976 (7 << 13 /* RX FIFO threshold NONE */) |
977 (7 << 10 /* MAX RX DMA */) |
978 RTL818X_RX_CONF_BROADCAST |
605bebe2 979 RTL818X_RX_CONF_NICMAC;
605bebe2 980
4150c572 981 priv->rx_conf = reg;
605bebe2
MW		 982 rtl818x_iowrite32(priv, &priv->map->RX_CONF, reg);
983
984 reg = rtl818x_ioread8(priv, &priv->map->CW_CONF);
985 reg &= ~RTL818X_CW_CONF_PERPACKET_CW_SHIFT;
986 reg |= RTL818X_CW_CONF_PERPACKET_RETRY_SHIFT;
987 rtl818x_iowrite8(priv, &priv->map->CW_CONF, reg);
988
989 reg = rtl818x_ioread8(priv, &priv->map->TX_AGC_CTL);
990 reg &= ~RTL818X_TX_AGC_CTL_PERPACKET_GAIN_SHIFT;
991 reg &= ~RTL818X_TX_AGC_CTL_PERPACKET_ANTSEL_SHIFT;
992 reg &= ~RTL818X_TX_AGC_CTL_FEEDBACK_ANT;
993 rtl818x_iowrite8(priv, &priv->map->TX_AGC_CTL, reg);
994
995 reg = RTL818X_TX_CONF_CW_MIN |
996 (7 << 21 /* MAX TX DMA */) |
997 RTL818X_TX_CONF_NO_ICV;
998 rtl818x_iowrite32(priv, &priv->map->TX_CONF, reg);
999
1000 reg = rtl818x_ioread8(priv, &priv->map->CMD);
1001 reg |= RTL818X_CMD_TX_ENABLE;
1002 reg |= RTL818X_CMD_RX_ENABLE;
1003 rtl818x_iowrite8(priv, &priv->map->CMD, reg);
2f47690e 1004 INIT_DELAYED_WORK(&priv->work, rtl8187_work);
605bebe2 1005
ca9152e3
HRK		 1006rtl8187_start_exit:
1007 mutex_unlock(&priv->conf_mutex);
1008 return ret;
605bebe2
MW		 1009}
1010
4150c572 1011static void rtl8187_stop(struct ieee80211_hw *dev)
605bebe2
MW		 1012{
1013 struct rtl8187_priv *priv = dev->priv;
605bebe2
MW		 1014 struct sk_buff *skb;
1015 u32 reg;
1016
7dcdd073 1017 mutex_lock(&priv->conf_mutex);
605bebe2
MW		 1018 rtl818x_iowrite16(priv, &priv->map->INT_MASK, 0);
1019
1020 reg = rtl818x_ioread8(priv, &priv->map->CMD);
1021 reg &= ~RTL818X_CMD_TX_ENABLE;
1022 reg &= ~RTL818X_CMD_RX_ENABLE;
1023 rtl818x_iowrite8(priv, &priv->map->CMD, reg);
1024
f6532111 1025 priv->rf->stop(dev);
0bf198eb 1026 rtl8187_set_anaparam(priv, false);
605bebe2
MW		 1027
1028 rtl818x_iowrite8(priv, &priv->map->EEPROM_CMD, RTL818X_EEPROM_CMD_CONFIG);
1029 reg = rtl818x_ioread8(priv, &priv->map->CONFIG4);
1030 rtl818x_iowrite8(priv, &priv->map->CONFIG4, reg | RTL818X_CONFIG4_VCOOFF);
1031 rtl818x_iowrite8(priv, &priv->map->EEPROM_CMD, RTL818X_EEPROM_CMD_NORMAL);
1032
3517afde
HRK		 1033 while ((skb = skb_dequeue(&priv->b_tx_status.queue)))
1034 dev_kfree_skb_any(skb);
c1db52b9
LF		 1035
1036 usb_kill_anchored_urbs(&priv->anchored);
6a8171f2
HRK		 1037 mutex_unlock(&priv->conf_mutex);
1038
2f47690e
LF		 1039 if (!priv->is_rtl8187b)
1040 cancel_delayed_work_sync(&priv->work);
605bebe2
MW		 1041}
1042
41b58f18
AF		 1043static u64 rtl8187_get_tsf(struct ieee80211_hw *dev, struct ieee80211_vif *vif)
1044{
1045 struct rtl8187_priv *priv = dev->priv;
1046
1047 return rtl818x_ioread32(priv, &priv->map->TSFT[0]) |
1048 (u64)(rtl818x_ioread32(priv, &priv->map->TSFT[1])) << 32;
1049}
1050
1051
1052static void rtl8187_beacon_work(struct work_struct *work)
1053{
1054 struct rtl8187_vif *vif_priv =
1055 container_of(work, struct rtl8187_vif, beacon_work.work);
1056 struct ieee80211_vif *vif =
1057 container_of((void *)vif_priv, struct ieee80211_vif, drv_priv);
1058 struct ieee80211_hw *dev = vif_priv->dev;
1059 struct ieee80211_mgmt *mgmt;
1060 struct sk_buff *skb;
1061
1062 /* don't overflow the tx ring */
1063 if (ieee80211_queue_stopped(dev, 0))
1064 goto resched;
1065
1066 /* grab a fresh beacon */
1067 skb = ieee80211_beacon_get(dev, vif);
1068 if (!skb)
1069 goto resched;
1070
1071 /*
1072 * update beacon timestamp w/ TSF value
1073 * TODO: make hardware update beacon timestamp
1074 */
1075 mgmt = (struct ieee80211_mgmt *)skb->data;
1076 mgmt->u.beacon.timestamp = cpu_to_le64(rtl8187_get_tsf(dev, vif));
1077
1078 /* TODO: use actual beacon queue */
1079 skb_set_queue_mapping(skb, 0);
1080
36323f81 1081 rtl8187_tx(dev, NULL, skb);
41b58f18
AF		 1082
1083resched:
1084 /*
1085 * schedule next beacon
1086 * TODO: use hardware support for beacon timing
1087 */
1088 schedule_delayed_work(&vif_priv->beacon_work,
1089 usecs_to_jiffies(1024 * vif->bss_conf.beacon_int));
1090}
1091
1092
605bebe2 1093static int rtl8187_add_interface(struct ieee80211_hw *dev,
1ed32e4f 1094 struct ieee80211_vif *vif)
605bebe2
MW		 1095{
1096 struct rtl8187_priv *priv = dev->priv;
41b58f18 1097 struct rtl8187_vif *vif_priv;
4150c572 1098 int i;
66aafd9a 1099 int ret = -EOPNOTSUPP;
605bebe2 1100
66aafd9a 1101 mutex_lock(&priv->conf_mutex);
d30506e0 1102 if (priv->vif)
66aafd9a 1103 goto exit;
605bebe2 1104
1ed32e4f 1105 switch (vif->type) {
05c914fe 1106 case NL80211_IFTYPE_STATION:
41b58f18 1107 case NL80211_IFTYPE_ADHOC:
605bebe2
MW		 1108 break;
1109 default:
66aafd9a 1110 goto exit;
605bebe2
MW		 1111 }
1112
66aafd9a 1113 ret = 0;
1ed32e4f 1114 priv->vif = vif;
aa979a6a 1115
41b58f18
AF		 1116 /* Initialize driver private area */
1117 vif_priv = (struct rtl8187_vif *)&vif->drv_priv;
1118 vif_priv->dev = dev;
1119 INIT_DELAYED_WORK(&vif_priv->beacon_work, rtl8187_beacon_work);
1120 vif_priv->enable_beacon = false;
1121
1122
4150c572
JB		 1123 rtl818x_iowrite8(priv, &priv->map->EEPROM_CMD, RTL818X_EEPROM_CMD_CONFIG);
1124 for (i = 0; i < ETH_ALEN; i++)
1125 rtl818x_iowrite8(priv, &priv->map->MAC[i],
1ed32e4f 1126 ((u8 *)vif->addr)[i]);
4150c572 1127 rtl818x_iowrite8(priv, &priv->map->EEPROM_CMD, RTL818X_EEPROM_CMD_NORMAL);
605bebe2 1128
66aafd9a 1129exit:
7dcdd073 1130 mutex_unlock(&priv->conf_mutex);
66aafd9a 1131 return ret;
605bebe2
MW		 1132}
1133
1134static void rtl8187_remove_interface(struct ieee80211_hw *dev,
1ed32e4f 1135 struct ieee80211_vif *vif)
605bebe2
MW		 1136{
1137 struct rtl8187_priv *priv = dev->priv;
7dcdd073 1138 mutex_lock(&priv->conf_mutex);
aa979a6a 1139 priv->vif = NULL;
7dcdd073 1140 mutex_unlock(&priv->conf_mutex);
605bebe2
MW		 1141}
1142
e8975581 1143static int rtl8187_config(struct ieee80211_hw *dev, u32 changed)
605bebe2
MW		 1144{
1145 struct rtl8187_priv *priv = dev->priv;
e8975581 1146 struct ieee80211_conf *conf = &dev->conf;
f6532111
MW		 1147 u32 reg;
1148
7dcdd073 1149 mutex_lock(&priv->conf_mutex);
f6532111
MW		 1150 reg = rtl818x_ioread32(priv, &priv->map->TX_CONF);
1151 /* Enable TX loopback on MAC level to avoid TX during channel
1152 * changes, as this has be seen to causes problems and the
1153 * card will stop work until next reset
1154 */
1155 rtl818x_iowrite32(priv, &priv->map->TX_CONF,
1156 reg | RTL818X_TX_CONF_LOOPBACK_MAC);
f6532111
MW		 1157 priv->rf->set_chan(dev, conf);
1158 msleep(10);
1159 rtl818x_iowrite32(priv, &priv->map->TX_CONF, reg);
605bebe2 1160
605bebe2
MW		 1161 rtl818x_iowrite16(priv, &priv->map->ATIM_WND, 2);
1162 rtl818x_iowrite16(priv, &priv->map->ATIMTR_INTERVAL, 100);
1163 rtl818x_iowrite16(priv, &priv->map->BEACON_INTERVAL, 100);
1164 rtl818x_iowrite16(priv, &priv->map->BEACON_INTERVAL_TIME, 100);
7dcdd073 1165 mutex_unlock(&priv->conf_mutex);
605bebe2
MW		 1166 return 0;
1167}
1168
b4572a92
HRK		 1169/*
1170 * With 8187B, AC_*_PARAM clashes with FEMR definition in struct rtl818x_csr for
1171 * example. Thus we have to use raw values for AC_*_PARAM register addresses.
1172 */
1173static __le32 *rtl8187b_ac_addr[4] = {
1174 (__le32 *) 0xFFF0, /* AC_VO */
1175 (__le32 *) 0xFFF4, /* AC_VI */
1176 (__le32 *) 0xFFFC, /* AC_BK */
1177 (__le32 *) 0xFFF8, /* AC_BE */
1178};
1179
1180#define SIFS_TIME 0xa
1181
f8288317
HRK		 1182static void rtl8187_conf_erp(struct rtl8187_priv *priv, bool use_short_slot,
1183 bool use_short_preamble)
64761077 1184{
f8288317 1185 if (priv->is_rtl8187b) {
b4572a92 1186 u8 difs, eifs;
f8288317 1187 u16 ack_timeout;
b4572a92 1188 int queue;
f8288317
HRK		 1189
1190 if (use_short_slot) {
b4572a92 1191 priv->slot_time = 0x9;
f8288317
HRK		 1192 difs = 0x1c;
1193 eifs = 0x53;
1194 } else {
b4572a92 1195 priv->slot_time = 0x14;
f8288317
HRK		 1196 difs = 0x32;
1197 eifs = 0x5b;
1198 }
54ac218a 1199 rtl818x_iowrite8(priv, &priv->map->SIFS, 0x22);
b4572a92 1200 rtl818x_iowrite8(priv, &priv->map->SLOT, priv->slot_time);
f8288317
HRK		 1201 rtl818x_iowrite8(priv, &priv->map->DIFS, difs);
1202
1203 /*
1204 * BRSR+1 on 8187B is in fact EIFS register
1205 * Value in units of 4 us
1206 */
1207 rtl818x_iowrite8(priv, (u8 *)&priv->map->BRSR + 1, eifs);
1208
1209 /*
1210 * For 8187B, CARRIER_SENSE_COUNTER is in fact ack timeout
1211 * register. In units of 4 us like eifs register
1212 * ack_timeout = ack duration + plcp + difs + preamble
1213 */
1214 ack_timeout = 112 + 48 + difs;
1215 if (use_short_preamble)
1216 ack_timeout += 72;
1217 else
1218 ack_timeout += 144;
1219 rtl818x_iowrite8(priv, &priv->map->CARRIER_SENSE_COUNTER,
1220 DIV_ROUND_UP(ack_timeout, 4));
b4572a92
HRK		 1221
1222 for (queue = 0; queue < 4; queue++)
1223 rtl818x_iowrite8(priv, (u8 *) rtl8187b_ac_addr[queue],
1224 priv->aifsn[queue] * priv->slot_time +
1225 SIFS_TIME);
f8288317 1226 } else {
64761077
HRK		 1227 rtl818x_iowrite8(priv, &priv->map->SIFS, 0x22);
1228 if (use_short_slot) {
1229 rtl818x_iowrite8(priv, &priv->map->SLOT, 0x9);
1230 rtl818x_iowrite8(priv, &priv->map->DIFS, 0x14);
1231 rtl818x_iowrite8(priv, &priv->map->EIFS, 91 - 0x14);
64761077
HRK		 1232 } else {
1233 rtl818x_iowrite8(priv, &priv->map->SLOT, 0x14);
1234 rtl818x_iowrite8(priv, &priv->map->DIFS, 0x24);
1235 rtl818x_iowrite8(priv, &priv->map->EIFS, 91 - 0x24);
64761077
HRK		 1236 }
1237 }
1238}
1239
1240static void rtl8187_bss_info_changed(struct ieee80211_hw *dev,
1241 struct ieee80211_vif *vif,
1242 struct ieee80211_bss_conf *info,
1243 u32 changed)
1244{
1245 struct rtl8187_priv *priv = dev->priv;
41b58f18 1246 struct rtl8187_vif *vif_priv;
2d0ddec5
JB		 1247 int i;
1248 u8 reg;
1249
41b58f18
AF		 1250 vif_priv = (struct rtl8187_vif *)&vif->drv_priv;
1251
2d0ddec5
JB		 1252 if (changed & BSS_CHANGED_BSSID) {
1253 mutex_lock(&priv->conf_mutex);
1254 for (i = 0; i < ETH_ALEN; i++)
1255 rtl818x_iowrite8(priv, &priv->map->BSSID[i],
1256 info->bssid[i]);
1257
1a9937b7
HRK		 1258 if (priv->is_rtl8187b)
1259 reg = RTL818X_MSR_ENEDCA;
1260 else
1261 reg = 0;
1262
41b58f18
AF		 1263 if (is_valid_ether_addr(info->bssid)) {
1264 if (vif->type == NL80211_IFTYPE_ADHOC)
1265 reg |= RTL818X_MSR_ADHOC;
1266 else
1267 reg |= RTL818X_MSR_INFRA;
1268 }
31a5cdda 1269 else
1a9937b7 1270 reg |= RTL818X_MSR_NO_LINK;
31a5cdda
JL		 1271
1272 rtl818x_iowrite8(priv, &priv->map->MSR, reg);
2d0ddec5
JB		 1273
1274 mutex_unlock(&priv->conf_mutex);
1275 }
64761077 1276
f8288317
HRK		 1277 if (changed & (BSS_CHANGED_ERP_SLOT | BSS_CHANGED_ERP_PREAMBLE))
1278 rtl8187_conf_erp(priv, info->use_short_slot,
1279 info->use_short_preamble);
41b58f18
AF		 1280
1281 if (changed & BSS_CHANGED_BEACON_ENABLED)
1282 vif_priv->enable_beacon = info->enable_beacon;
1283
1284 if (changed & (BSS_CHANGED_BEACON_ENABLED | BSS_CHANGED_BEACON)) {
1285 cancel_delayed_work_sync(&vif_priv->beacon_work);
1286 if (vif_priv->enable_beacon)
1287 schedule_work(&vif_priv->beacon_work.work);
1288 }
1289
64761077
HRK		 1290}
1291
3ac64bee 1292static u64 rtl8187_prepare_multicast(struct ieee80211_hw *dev,
22bedad3 1293 struct netdev_hw_addr_list *mc_list)
3ac64bee 1294{
22bedad3 1295 return netdev_hw_addr_list_count(mc_list);
3ac64bee
JB		 1296}
1297
4150c572
JB		 1298static void rtl8187_configure_filter(struct ieee80211_hw *dev,
1299 unsigned int changed_flags,
1300 unsigned int *total_flags,
3ac64bee 1301 u64 multicast)
4150c572
JB		 1302{
1303 struct rtl8187_priv *priv = dev->priv;
1304
4150c572
JB		 1305 if (changed_flags & FIF_FCSFAIL)
1306 priv->rx_conf ^= RTL818X_RX_CONF_FCS;
1307 if (changed_flags & FIF_CONTROL)
1308 priv->rx_conf ^= RTL818X_RX_CONF_CTRL;
1309 if (changed_flags & FIF_OTHER_BSS)
1310 priv->rx_conf ^= RTL818X_RX_CONF_MONITOR;
3ac64bee 1311 if (*total_flags & FIF_ALLMULTI || multicast > 0)
4150c572 1312 priv->rx_conf |= RTL818X_RX_CONF_MULTICAST;
2fe14263
MW		 1313 else
1314 priv->rx_conf &= ~RTL818X_RX_CONF_MULTICAST;
1315
1316 *total_flags = 0;
4150c572 1317
4150c572
JB		 1318 if (priv->rx_conf & RTL818X_RX_CONF_FCS)
1319 *total_flags |= FIF_FCSFAIL;
1320 if (priv->rx_conf & RTL818X_RX_CONF_CTRL)
1321 *total_flags |= FIF_CONTROL;
1322 if (priv->rx_conf & RTL818X_RX_CONF_MONITOR)
1323 *total_flags |= FIF_OTHER_BSS;
2fe14263
MW		 1324 if (priv->rx_conf & RTL818X_RX_CONF_MULTICAST)
1325 *total_flags |= FIF_ALLMULTI;
4150c572
JB		 1326
1327 rtl818x_iowrite32_async(priv, &priv->map->RX_CONF, priv->rx_conf);
1328}
1329
8a3a3c85
EP		 1330static int rtl8187_conf_tx(struct ieee80211_hw *dev,
1331 struct ieee80211_vif *vif, u16 queue,
b4572a92
HRK		 1332 const struct ieee80211_tx_queue_params *params)
1333{
1334 struct rtl8187_priv *priv = dev->priv;
1335 u8 cw_min, cw_max;
1336
1337 if (queue > 3)
1338 return -EINVAL;
1339
1340 cw_min = fls(params->cw_min);
1341 cw_max = fls(params->cw_max);
1342
1343 if (priv->is_rtl8187b) {
1344 priv->aifsn[queue] = params->aifs;
1345
1346 /*
1347 * This is the structure of AC_*_PARAM registers in 8187B:
1348 * - TXOP limit field, bit offset = 16
1349 * - ECWmax, bit offset = 12
1350 * - ECWmin, bit offset = 8
1351 * - AIFS, bit offset = 0
1352 */
1353 rtl818x_iowrite32(priv, rtl8187b_ac_addr[queue],
1354 (params->txop << 16) | (cw_max << 12) |
1355 (cw_min << 8) | (params->aifs *
1356 priv->slot_time + SIFS_TIME));
1357 } else {
1358 if (queue != 0)
1359 return -EINVAL;
1360
1361 rtl818x_iowrite8(priv, &priv->map->CW_VAL,
1362 cw_min | (cw_max << 4));
1363 }
1364 return 0;
1365}
1366
22e16e55 1367
605bebe2
MW		 1368static const struct ieee80211_ops rtl8187_ops = {
1369 .tx = rtl8187_tx,
4150c572 1370 .start = rtl8187_start,
605bebe2
MW		 1371 .stop = rtl8187_stop,
1372 .add_interface = rtl8187_add_interface,
1373 .remove_interface = rtl8187_remove_interface,
1374 .config = rtl8187_config,
64761077 1375 .bss_info_changed = rtl8187_bss_info_changed,
3ac64bee 1376 .prepare_multicast = rtl8187_prepare_multicast,
4150c572 1377 .configure_filter = rtl8187_configure_filter,
ca9152e3 1378 .conf_tx = rtl8187_conf_tx,
22e16e55
LF		 1379 .rfkill_poll = rtl8187_rfkill_poll,
1380 .get_tsf = rtl8187_get_tsf,
605bebe2
MW		 1381};
1382
1383static void rtl8187_eeprom_register_read(struct eeprom_93cx6 *eeprom)
1384{
1385 struct ieee80211_hw *dev = eeprom->data;
1386 struct rtl8187_priv *priv = dev->priv;
1387 u8 reg = rtl818x_ioread8(priv, &priv->map->EEPROM_CMD);
1388
1389 eeprom->reg_data_in = reg & RTL818X_EEPROM_CMD_WRITE;
1390 eeprom->reg_data_out = reg & RTL818X_EEPROM_CMD_READ;
1391 eeprom->reg_data_clock = reg & RTL818X_EEPROM_CMD_CK;
1392 eeprom->reg_chip_select = reg & RTL818X_EEPROM_CMD_CS;
1393}
1394
1395static void rtl8187_eeprom_register_write(struct eeprom_93cx6 *eeprom)
1396{
1397 struct ieee80211_hw *dev = eeprom->data;
1398 struct rtl8187_priv *priv = dev->priv;
1399 u8 reg = RTL818X_EEPROM_CMD_PROGRAM;
1400
1401 if (eeprom->reg_data_in)
1402 reg |= RTL818X_EEPROM_CMD_WRITE;
1403 if (eeprom->reg_data_out)
1404 reg |= RTL818X_EEPROM_CMD_READ;
1405 if (eeprom->reg_data_clock)
1406 reg |= RTL818X_EEPROM_CMD_CK;
1407 if (eeprom->reg_chip_select)
1408 reg |= RTL818X_EEPROM_CMD_CS;
1409
1410 rtl818x_iowrite8(priv, &priv->map->EEPROM_CMD, reg);
1411 udelay(10);
1412}
1413
fd549f13 1414static int rtl8187_probe(struct usb_interface *intf,
605bebe2
MW		 1415 const struct usb_device_id *id)
1416{
1417 struct usb_device *udev = interface_to_usbdev(intf);
1418 struct ieee80211_hw *dev;
1419 struct rtl8187_priv *priv;
1420 struct eeprom_93cx6 eeprom;
1421 struct ieee80211_channel *channel;
6f7853f3 1422 const char *chip_name;
605bebe2 1423 u16 txpwr, reg;
70d57139 1424 u16 product_id = le16_to_cpu(udev->descriptor.idProduct);
605bebe2 1425 int err, i;
f2c98382 1426 u8 mac_addr[ETH_ALEN];
605bebe2
MW		 1427
1428 dev = ieee80211_alloc_hw(sizeof(*priv), &rtl8187_ops);
1429 if (!dev) {
1430 printk(KERN_ERR "rtl8187: ieee80211 alloc failed\n");
1431 return -ENOMEM;
1432 }
1433
1434 priv = dev->priv;
0e25b4ef 1435 priv->is_rtl8187b = (id->driver_info == DEVICE_RTL8187B);
605bebe2 1436
9be6f0d4
JL		 1437 /* allocate "DMA aware" buffer for register accesses */
1438 priv->io_dmabuf = kmalloc(sizeof(*priv->io_dmabuf), GFP_KERNEL);
1439 if (!priv->io_dmabuf) {
1440 err = -ENOMEM;
1441 goto err_free_dev;
1442 }
1443 mutex_init(&priv->io_mutex);
1444
605bebe2
MW		 1445 SET_IEEE80211_DEV(dev, &intf->dev);
1446 usb_set_intfdata(intf, dev);
1447 priv->udev = udev;
1448
1449 usb_get_dev(udev);
1450
1451 skb_queue_head_init(&priv->rx_queue);
8318d78a
JB		 1452
1453 BUILD_BUG_ON(sizeof(priv->channels) != sizeof(rtl818x_channels));
1454 BUILD_BUG_ON(sizeof(priv->rates) != sizeof(rtl818x_rates));
1455
605bebe2
MW		 1456 memcpy(priv->channels, rtl818x_channels, sizeof(rtl818x_channels));
1457 memcpy(priv->rates, rtl818x_rates, sizeof(rtl818x_rates));
1458 priv->map = (struct rtl818x_csr *)0xFF00;
8318d78a
JB		 1459
1460 priv->band.band = IEEE80211_BAND_2GHZ;
1461 priv->band.channels = priv->channels;
1462 priv->band.n_channels = ARRAY_SIZE(rtl818x_channels);
1463 priv->band.bitrates = priv->rates;
1464 priv->band.n_bitrates = ARRAY_SIZE(rtl818x_rates);
1465 dev->wiphy->bands[IEEE80211_BAND_2GHZ] = &priv->band;
1466
1467
605bebe2 1468 dev->flags = IEEE80211_HW_HOST_BROADCAST_PS_BUFFERING |
a7db74f4 1469 IEEE80211_HW_SIGNAL_DBM |
0ccd58fc 1470 IEEE80211_HW_RX_INCLUDES_FCS;
6410db59
LF		 1471 /* Initialize rate-control variables */
1472 dev->max_rates = 1;
1473 dev->max_rate_tries = RETRY_COUNT;
605bebe2 1474
605bebe2
MW		 1475 eeprom.data = dev;
1476 eeprom.register_read = rtl8187_eeprom_register_read;
1477 eeprom.register_write = rtl8187_eeprom_register_write;
1478 if (rtl818x_ioread32(priv, &priv->map->RX_CONF) & (1 << 6))
1479 eeprom.width = PCI_EEPROM_WIDTH_93C66;
1480 else
1481 eeprom.width = PCI_EEPROM_WIDTH_93C46;
1482
1483 rtl818x_iowrite8(priv, &priv->map->EEPROM_CMD, RTL818X_EEPROM_CMD_CONFIG);
1484 udelay(10);
1485
1486 eeprom_93cx6_multiread(&eeprom, RTL8187_EEPROM_MAC_ADDR,
f2c98382
JL		 1487 (__le16 __force *)mac_addr, 3);
1488 if (!is_valid_ether_addr(mac_addr)) {
605bebe2
MW		 1489 printk(KERN_WARNING "rtl8187: Invalid hwaddr! Using randomly "
1490 "generated MAC address\n");
f4f7f414 1491 eth_random_addr(mac_addr);
605bebe2 1492 }
f2c98382 1493 SET_IEEE80211_PERM_ADDR(dev, mac_addr);
605bebe2
MW		 1494
1495 channel = priv->channels;
1496 for (i = 0; i < 3; i++) {
1497 eeprom_93cx6_read(&eeprom, RTL8187_EEPROM_TXPWR_CHAN_1 + i,
1498 &txpwr);
8318d78a
JB		 1499 (*channel++).hw_value = txpwr & 0xFF;
1500 (*channel++).hw_value = txpwr >> 8;
605bebe2
MW		 1501 }
1502 for (i = 0; i < 2; i++) {
1503 eeprom_93cx6_read(&eeprom, RTL8187_EEPROM_TXPWR_CHAN_4 + i,
1504 &txpwr);
8318d78a
JB		 1505 (*channel++).hw_value = txpwr & 0xFF;
1506 (*channel++).hw_value = txpwr >> 8;
605bebe2 1507 }
605bebe2
MW		 1508
1509 eeprom_93cx6_read(&eeprom, RTL8187_EEPROM_TXPWR_BASE,
1510 &priv->txpwr_base);
1511
f6532111
MW		 1512 reg = rtl818x_ioread8(priv, &priv->map->PGSELECT) & ~1;
1513 rtl818x_iowrite8(priv, &priv->map->PGSELECT, reg | 1);
605bebe2
MW		 1514 /* 0 means asic B-cut, we should use SW 3 wire
1515 * bit-by-bit banging for radio. 1 means we can use
1516 * USB specific request to write radio registers */
1517 priv->asic_rev = rtl818x_ioread8(priv, (u8 *)0xFFFE) & 0x3;
f6532111 1518 rtl818x_iowrite8(priv, &priv->map->PGSELECT, reg);
605bebe2
MW		 1519 rtl818x_iowrite8(priv, &priv->map->EEPROM_CMD, RTL818X_EEPROM_CMD_NORMAL);
1520
6f7853f3
HTL		 1521 if (!priv->is_rtl8187b) {
1522 u32 reg32;
1523 reg32 = rtl818x_ioread32(priv, &priv->map->TX_CONF);
1524 reg32 &= RTL818X_TX_CONF_HWVER_MASK;
1525 switch (reg32) {
0e25b4ef
LF		 1526 case RTL818X_TX_CONF_R8187vD_B:
1527 /* Some RTL8187B devices have a USB ID of 0x8187
1528 * detect them here */
1529 chip_name = "RTL8187BvB(early)";
1530 priv->is_rtl8187b = 1;
1531 priv->hw_rev = RTL8187BvB;
1532 break;
1533 case RTL818X_TX_CONF_R8187vD:
6f7853f3
HTL		 1534 chip_name = "RTL8187vD";
1535 break;
1536 default:
1537 chip_name = "RTL8187vB (default)";
1538 }
1539 } else {
6f7853f3
HTL		 1540 /*
1541 * Force USB request to write radio registers for 8187B, Realtek
1542 * only uses it in their sources
1543 */
1544 /*if (priv->asic_rev == 0) {
1545 printk(KERN_WARNING "rtl8187: Forcing use of USB "
1546 "requests to write to radio registers\n");
1547 priv->asic_rev = 1;
1548 }*/
1549 switch (rtl818x_ioread8(priv, (u8 *)0xFFE1)) {
1550 case RTL818X_R8187B_B:
1551 chip_name = "RTL8187BvB";
1552 priv->hw_rev = RTL8187BvB;
1553 break;
1554 case RTL818X_R8187B_D:
1555 chip_name = "RTL8187BvD";
1556 priv->hw_rev = RTL8187BvD;
1557 break;
1558 case RTL818X_R8187B_E:
1559 chip_name = "RTL8187BvE";
1560 priv->hw_rev = RTL8187BvE;
1561 break;
1562 default:
1563 chip_name = "RTL8187BvB (default)";
1564 priv->hw_rev = RTL8187BvB;
1565 }
1566 }
1567
0e25b4ef
LF		 1568 if (!priv->is_rtl8187b) {
1569 for (i = 0; i < 2; i++) {
1570 eeprom_93cx6_read(&eeprom,
1571 RTL8187_EEPROM_TXPWR_CHAN_6 + i,
1572 &txpwr);
1573 (*channel++).hw_value = txpwr & 0xFF;
1574 (*channel++).hw_value = txpwr >> 8;
1575 }
1576 } else {
1577 eeprom_93cx6_read(&eeprom, RTL8187_EEPROM_TXPWR_CHAN_6,
1578 &txpwr);
1579 (*channel++).hw_value = txpwr & 0xFF;
1580
1581 eeprom_93cx6_read(&eeprom, 0x0A, &txpwr);
1582 (*channel++).hw_value = txpwr & 0xFF;
1583
1584 eeprom_93cx6_read(&eeprom, 0x1C, &txpwr);
1585 (*channel++).hw_value = txpwr & 0xFF;
1586 (*channel++).hw_value = txpwr >> 8;
1587 }
70d57139
LF		 1588 /* Handle the differing rfkill GPIO bit in different models */
1589 priv->rfkill_mask = RFKILL_MASK_8187_89_97;
1590 if (product_id == 0x8197 || product_id == 0x8198) {
1591 eeprom_93cx6_read(&eeprom, RTL8187_EEPROM_SELECT_GPIO, &reg);
1592 if (reg & 0xFF00)
1593 priv->rfkill_mask = RFKILL_MASK_8198;
1594 }
41b58f18
AF		 1595 dev->vif_data_size = sizeof(struct rtl8187_vif);
1596 dev->wiphy->interface_modes = BIT(NL80211_IFTYPE_STATION) |
1597 BIT(NL80211_IFTYPE_ADHOC) ;
f59ac048 1598
0e25b4ef
LF		 1599 if ((id->driver_info == DEVICE_RTL8187) && priv->is_rtl8187b)
1600 printk(KERN_INFO "rtl8187: inconsistency between id with OEM"
1601 " info!\n");
1602
f6532111 1603 priv->rf = rtl8187_detect_rf(dev);
0e25b4ef
LF		 1604 dev->extra_tx_headroom = (!priv->is_rtl8187b) ?
1605 sizeof(struct rtl8187_tx_hdr) :
1606 sizeof(struct rtl8187b_tx_hdr);
1607 if (!priv->is_rtl8187b)
1608 dev->queues = 1;
1609 else
1610 dev->queues = 4;
605bebe2
MW		 1611
1612 err = ieee80211_register_hw(dev);
1613 if (err) {
1614 printk(KERN_ERR "rtl8187: Cannot register device\n");
9be6f0d4 1615 goto err_free_dmabuf;
605bebe2 1616 }
7dcdd073 1617 mutex_init(&priv->conf_mutex);
3517afde 1618 skb_queue_head_init(&priv->b_tx_status.queue);
605bebe2 1619
5db55844 1620 wiphy_info(dev->wiphy, "hwaddr %pM, %s V%d + %s, rfkill mask %d\n",
c96c31e4
JP		 1621 mac_addr, chip_name, priv->asic_rev, priv->rf->name,
1622 priv->rfkill_mask);
605bebe2 1623
a027087a
LF		 1624#ifdef CONFIG_RTL8187_LEDS
1625 eeprom_93cx6_read(&eeprom, 0x3F, &reg);
1626 reg &= 0xFF;
1627 rtl8187_leds_init(dev, reg);
1628#endif
ca9152e3 1629 rtl8187_rfkill_init(dev);
a027087a 1630
605bebe2
MW		 1631 return 0;
1632
9be6f0d4
JL		 1633 err_free_dmabuf:
1634 kfree(priv->io_dmabuf);
605bebe2
MW		 1635 err_free_dev:
1636 ieee80211_free_hw(dev);
1637 usb_set_intfdata(intf, NULL);
1638 usb_put_dev(udev);
1639 return err;
1640}
1641
fd549f13 1642static void rtl8187_disconnect(struct usb_interface *intf)
605bebe2
MW		 1643{
1644 struct ieee80211_hw *dev = usb_get_intfdata(intf);
1645 struct rtl8187_priv *priv;
1646
1647 if (!dev)
1648 return;
1649
a027087a
LF		 1650#ifdef CONFIG_RTL8187_LEDS
1651 rtl8187_leds_exit(dev);
1652#endif
ca9152e3 1653 rtl8187_rfkill_exit(dev);
605bebe2
MW		 1654 ieee80211_unregister_hw(dev);
1655
1656 priv = dev->priv;
d6e2be98 1657 usb_reset_device(priv->udev);
605bebe2 1658 usb_put_dev(interface_to_usbdev(intf));
9be6f0d4 1659 kfree(priv->io_dmabuf);
605bebe2
MW		 1660 ieee80211_free_hw(dev);
1661}
1662
1663static struct usb_driver rtl8187_driver = {
1664 .name = KBUILD_MODNAME,
1665 .id_table = rtl8187_table,
1666 .probe = rtl8187_probe,
fd549f13 1667 .disconnect = rtl8187_disconnect,
e1f12eb6 1668 .disable_hub_initiated_lpm = 1,
605bebe2
MW		 1669};
1670
d632eb1b 1671module_usb_driver(rtl8187_driver);
Linux kernel - Deliverables
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