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ath9k_hw: Remove BTCOEX initvals
[deliverable/linux.git] / drivers / net / wireless / rtl818x / rtl8187 / dev.c
CommitLineData
605bebe2
MW		 1/*
2 * Linux device driver for RTL8187
3 *
4 * Copyright 2007 Michael Wu <flamingice@sourmilk.net>
5 * Copyright 2007 Andrea Merello <andreamrl@tiscali.it>
6 *
7 * Based on the r8187 driver, which is:
8 * Copyright 2005 Andrea Merello <andreamrl@tiscali.it>, et al.
9 *
3461fc12 10 * The driver was extended to the RTL8187B in 2008 by:
41b58f18 11 * Herton Ronaldo Krzesinski <herton@mandriva.com.br>
3461fc12
LF		 12 * Hin-Tak Leung <htl10@users.sourceforge.net>
13 * Larry Finger <Larry.Finger@lwfinger.net>
14 *
0aec00ae
JL		 15 * Magic delays and register offsets below are taken from the original
16 * r8187 driver sources. Thanks to Realtek for their support!
605bebe2
MW		 17 *
18 * This program is free software; you can redistribute it and/or modify
19 * it under the terms of the GNU General Public License version 2 as
20 * published by the Free Software Foundation.
21 */
22
23#include <linux/init.h>
24#include <linux/usb.h>
5a0e3ad6 25#include <linux/slab.h>
605bebe2
MW		 26#include <linux/delay.h>
27#include <linux/etherdevice.h>
28#include <linux/eeprom_93cx6.h>
9d9779e7 29#include <linux/module.h>
605bebe2
MW		 30#include <net/mac80211.h>
31
32#include "rtl8187.h"
3cfeb0c3 33#include "rtl8225.h"
a027087a 34#ifdef CONFIG_RTL8187_LEDS
3cfeb0c3 35#include "leds.h"
a027087a 36#endif
3cfeb0c3 37#include "rfkill.h"
605bebe2
MW		 38
39MODULE_AUTHOR("Michael Wu <flamingice@sourmilk.net>");
40MODULE_AUTHOR("Andrea Merello <andreamrl@tiscali.it>");
3461fc12
LF		 41MODULE_AUTHOR("Herton Ronaldo Krzesinski <herton@mandriva.com.br>");
42MODULE_AUTHOR("Hin-Tak Leung <htl10@users.sourceforge.net>");
43MODULE_AUTHOR("Larry Finger <Larry.Finger@lwfinger.net>");
f8a08c34 44MODULE_DESCRIPTION("RTL8187/RTL8187B USB wireless driver");
605bebe2
MW		 45MODULE_LICENSE("GPL");
46
47static struct usb_device_id rtl8187_table[] __devinitdata = {
7c7e6af3
AM		 48 /* Asus */
49 {USB_DEVICE(0x0b05, 0x171d), .driver_info = DEVICE_RTL8187},
eaca90da
FF		 50 /* Belkin */
51 {USB_DEVICE(0x050d, 0x705e), .driver_info = DEVICE_RTL8187B},
605bebe2 52 /* Realtek */
f8a08c34
HTL		 53 {USB_DEVICE(0x0bda, 0x8187), .driver_info = DEVICE_RTL8187},
54 {USB_DEVICE(0x0bda, 0x8189), .driver_info = DEVICE_RTL8187B},
55 {USB_DEVICE(0x0bda, 0x8197), .driver_info = DEVICE_RTL8187B},
746db510 56 {USB_DEVICE(0x0bda, 0x8198), .driver_info = DEVICE_RTL8187B},
046ee5d2
LF		 57 /* Surecom */
58 {USB_DEVICE(0x0769, 0x11F2), .driver_info = DEVICE_RTL8187},
59 /* Logitech */
60 {USB_DEVICE(0x0789, 0x010C), .driver_info = DEVICE_RTL8187},
605bebe2 61 /* Netgear */
f8a08c34
HTL		 62 {USB_DEVICE(0x0846, 0x6100), .driver_info = DEVICE_RTL8187},
63 {USB_DEVICE(0x0846, 0x6a00), .driver_info = DEVICE_RTL8187},
fcd7cc14 64 {USB_DEVICE(0x0846, 0x4260), .driver_info = DEVICE_RTL8187B},
c3cf60a9 65 /* HP */
f8a08c34 66 {USB_DEVICE(0x03f0, 0xca02), .driver_info = DEVICE_RTL8187},
9934550d 67 /* Sitecom */
f8a08c34 68 {USB_DEVICE(0x0df6, 0x000d), .driver_info = DEVICE_RTL8187},
f3c76918 69 {USB_DEVICE(0x0df6, 0x0028), .driver_info = DEVICE_RTL8187B},
174b2496 70 {USB_DEVICE(0x0df6, 0x0029), .driver_info = DEVICE_RTL8187B},
046ee5d2
LF		 71 /* Sphairon Access Systems GmbH */
72 {USB_DEVICE(0x114B, 0x0150), .driver_info = DEVICE_RTL8187},
73 /* Dick Smith Electronics */
74 {USB_DEVICE(0x1371, 0x9401), .driver_info = DEVICE_RTL8187},
8f7c41d4
IK		 75 /* Abocom */
76 {USB_DEVICE(0x13d1, 0xabe6), .driver_info = DEVICE_RTL8187},
046ee5d2
LF		 77 /* Qcom */
78 {USB_DEVICE(0x18E8, 0x6232), .driver_info = DEVICE_RTL8187},
79 /* AirLive */
80 {USB_DEVICE(0x1b75, 0x8187), .driver_info = DEVICE_RTL8187},
aeeab4ff
JL		 81 /* Linksys */
82 {USB_DEVICE(0x1737, 0x0073), .driver_info = DEVICE_RTL8187B},
605bebe2
MW		 83 {}
84};
85
86MODULE_DEVICE_TABLE(usb, rtl8187_table);
87
8318d78a
JB		 88static const struct ieee80211_rate rtl818x_rates[] = {
89 { .bitrate = 10, .hw_value = 0, },
90 { .bitrate = 20, .hw_value = 1, },
91 { .bitrate = 55, .hw_value = 2, },
92 { .bitrate = 110, .hw_value = 3, },
93 { .bitrate = 60, .hw_value = 4, },
94 { .bitrate = 90, .hw_value = 5, },
95 { .bitrate = 120, .hw_value = 6, },
96 { .bitrate = 180, .hw_value = 7, },
97 { .bitrate = 240, .hw_value = 8, },
98 { .bitrate = 360, .hw_value = 9, },
99 { .bitrate = 480, .hw_value = 10, },
100 { .bitrate = 540, .hw_value = 11, },
101};
102
103static const struct ieee80211_channel rtl818x_channels[] = {
104 { .center_freq = 2412 },
105 { .center_freq = 2417 },
106 { .center_freq = 2422 },
107 { .center_freq = 2427 },
108 { .center_freq = 2432 },
109 { .center_freq = 2437 },
110 { .center_freq = 2442 },
111 { .center_freq = 2447 },
112 { .center_freq = 2452 },
113 { .center_freq = 2457 },
114 { .center_freq = 2462 },
115 { .center_freq = 2467 },
116 { .center_freq = 2472 },
117 { .center_freq = 2484 },
118};
119
4150c572
JB		 120static void rtl8187_iowrite_async_cb(struct urb *urb)
121{
122 kfree(urb->context);
4150c572
JB		 123}
124
125static void rtl8187_iowrite_async(struct rtl8187_priv *priv, __le16 addr,
126 void *data, u16 len)
127{
128 struct usb_ctrlrequest *dr;
129 struct urb *urb;
130 struct rtl8187_async_write_data {
131 u8 data[4];
132 struct usb_ctrlrequest dr;
133 } *buf;
ea8ee240 134 int rc;
4150c572
JB		 135
136 buf = kmalloc(sizeof(*buf), GFP_ATOMIC);
137 if (!buf)
138 return;
139
140 urb = usb_alloc_urb(0, GFP_ATOMIC);
141 if (!urb) {
142 kfree(buf);
143 return;
144 }
145
146 dr = &buf->dr;
147
148 dr->bRequestType = RTL8187_REQT_WRITE;
149 dr->bRequest = RTL8187_REQ_SET_REG;
150 dr->wValue = addr;
151 dr->wIndex = 0;
152 dr->wLength = cpu_to_le16(len);
153
154 memcpy(buf, data, len);
155
156 usb_fill_control_urb(urb, priv->udev, usb_sndctrlpipe(priv->udev, 0),
157 (unsigned char *)dr, buf, len,
158 rtl8187_iowrite_async_cb, buf);
c1db52b9 159 usb_anchor_urb(urb, &priv->anchored);
ea8ee240
ON		 160 rc = usb_submit_urb(urb, GFP_ATOMIC);
161 if (rc < 0) {
162 kfree(buf);
c1db52b9 163 usb_unanchor_urb(urb);
ea8ee240 164 }
c1db52b9 165 usb_free_urb(urb);
4150c572
JB		 166}
167
168static inline void rtl818x_iowrite32_async(struct rtl8187_priv *priv,
169 __le32 *addr, u32 val)
170{
171 __le32 buf = cpu_to_le32(val);
172
173 rtl8187_iowrite_async(priv, cpu_to_le16((unsigned long)addr),
174 &buf, sizeof(buf));
175}
176
605bebe2
MW		 177void rtl8187_write_phy(struct ieee80211_hw *dev, u8 addr, u32 data)
178{
179 struct rtl8187_priv *priv = dev->priv;
180
181 data <<= 8;
182 data |= addr | 0x80;
183
184 rtl818x_iowrite8(priv, &priv->map->PHY[3], (data >> 24) & 0xFF);
185 rtl818x_iowrite8(priv, &priv->map->PHY[2], (data >> 16) & 0xFF);
186 rtl818x_iowrite8(priv, &priv->map->PHY[1], (data >> 8) & 0xFF);
187 rtl818x_iowrite8(priv, &priv->map->PHY[0], data & 0xFF);
605bebe2
MW		 188}
189
190static void rtl8187_tx_cb(struct urb *urb)
191{
605bebe2 192 struct sk_buff *skb = (struct sk_buff *)urb->context;
e039fa4a 193 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
e6a9854b 194 struct ieee80211_hw *hw = info->rate_driver_data[0];
6f7853f3 195 struct rtl8187_priv *priv = hw->priv;
605bebe2 196
6f7853f3
HTL		 197 skb_pull(skb, priv->is_rtl8187b ? sizeof(struct rtl8187b_tx_hdr) :
198 sizeof(struct rtl8187_tx_hdr));
e6a9854b 199 ieee80211_tx_info_clear_status(info);
3517afde 200
2f47690e
LF		 201 if (!(urb->status) && !(info->flags & IEEE80211_TX_CTL_NO_ACK)) {
202 if (priv->is_rtl8187b) {
203 skb_queue_tail(&priv->b_tx_status.queue, skb);
204
205 /* queue is "full", discard last items */
206 while (skb_queue_len(&priv->b_tx_status.queue) > 5) {
207 struct sk_buff *old_skb;
208
209 dev_dbg(&priv->udev->dev,
210 "transmit status queue full\n");
211
212 old_skb = skb_dequeue(&priv->b_tx_status.queue);
213 ieee80211_tx_status_irqsafe(hw, old_skb);
214 }
215 return;
216 } else {
3517afde 217 info->flags |= IEEE80211_TX_STAT_ACK;
2f47690e
LF		 218 }
219 }
220 if (priv->is_rtl8187b)
3517afde 221 ieee80211_tx_status_irqsafe(hw, skb);
2f47690e
LF		 222 else {
223 /* Retry information for the RTI8187 is only available by
224 * reading a register in the device. We are in interrupt mode
225 * here, thus queue the skb and finish on a work queue. */
226 skb_queue_tail(&priv->b_tx_status.queue, skb);
42935eca 227 ieee80211_queue_delayed_work(hw, &priv->work, 0);
3517afde 228 }
605bebe2
MW		 229}
230
7bb45683 231static void rtl8187_tx(struct ieee80211_hw *dev, struct sk_buff *skb)
605bebe2
MW		 232{
233 struct rtl8187_priv *priv = dev->priv;
e039fa4a 234 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
41b58f18 235 struct ieee80211_hdr *tx_hdr = (struct ieee80211_hdr *)(skb->data);
6f7853f3
HTL		 236 unsigned int ep;
237 void *buf;
605bebe2 238 struct urb *urb;
98798f48
MW		 239 __le16 rts_dur = 0;
240 u32 flags;
ea8ee240 241 int rc;
605bebe2
MW		 242
243 urb = usb_alloc_urb(0, GFP_ATOMIC);
244 if (!urb) {
245 kfree_skb(skb);
7bb45683 246 return;
605bebe2
MW		 247 }
248
98798f48 249 flags = skb->len;
38e3b0d8 250 flags |= RTL818X_TX_DESC_FLAG_NO_ENC;
aa68cbfb 251
e039fa4a 252 flags |= ieee80211_get_tx_rate(dev, info)->hw_value << 24;
41b58f18 253 if (ieee80211_has_morefrags(tx_hdr->frame_control))
38e3b0d8 254 flags |= RTL818X_TX_DESC_FLAG_MOREFRAG;
e6a9854b 255 if (info->control.rates[0].flags & IEEE80211_TX_RC_USE_RTS_CTS) {
38e3b0d8 256 flags |= RTL818X_TX_DESC_FLAG_RTS;
e039fa4a 257 flags |= ieee80211_get_rts_cts_rate(dev, info)->hw_value << 19;
32bfd35d 258 rts_dur = ieee80211_rts_duration(dev, priv->vif,
e039fa4a 259 skb->len, info);
e6a9854b 260 } else if (info->control.rates[0].flags & IEEE80211_TX_RC_USE_CTS_PROTECT) {
38e3b0d8 261 flags |= RTL818X_TX_DESC_FLAG_CTS;
e039fa4a 262 flags |= ieee80211_get_rts_cts_rate(dev, info)->hw_value << 19;
aa68cbfb 263 }
98798f48 264
41b58f18
AF		 265 if (info->flags & IEEE80211_TX_CTL_ASSIGN_SEQ) {
266 if (info->flags & IEEE80211_TX_CTL_FIRST_FRAGMENT)
267 priv->seqno += 0x10;
268 tx_hdr->seq_ctrl &= cpu_to_le16(IEEE80211_SCTL_FRAG);
269 tx_hdr->seq_ctrl |= cpu_to_le16(priv->seqno);
270 }
271
6f7853f3
HTL		 272 if (!priv->is_rtl8187b) {
273 struct rtl8187_tx_hdr *hdr =
274 (struct rtl8187_tx_hdr *)skb_push(skb, sizeof(*hdr));
275 hdr->flags = cpu_to_le32(flags);
276 hdr->len = 0;
277 hdr->rts_duration = rts_dur;
d9a1f486 278 hdr->retry = cpu_to_le32((info->control.rates[0].count - 1) << 8);
6f7853f3
HTL		 279 buf = hdr;
280
281 ep = 2;
282 } else {
283 /* fc needs to be calculated before skb_push() */
284 unsigned int epmap[4] = { 6, 7, 5, 4 };
6f7853f3
HTL		 285 u16 fc = le16_to_cpu(tx_hdr->frame_control);
286
287 struct rtl8187b_tx_hdr *hdr =
288 (struct rtl8187b_tx_hdr *)skb_push(skb, sizeof(*hdr));
289 struct ieee80211_rate *txrate =
290 ieee80211_get_tx_rate(dev, info);
291 memset(hdr, 0, sizeof(*hdr));
292 hdr->flags = cpu_to_le32(flags);
293 hdr->rts_duration = rts_dur;
d9a1f486 294 hdr->retry = cpu_to_le32((info->control.rates[0].count - 1) << 8);
6f7853f3
HTL		 295 hdr->tx_duration =
296 ieee80211_generic_frame_duration(dev, priv->vif,
297 skb->len, txrate);
298 buf = hdr;
299
300 if ((fc & IEEE80211_FCTL_FTYPE) == IEEE80211_FTYPE_MGMT)
301 ep = 12;
302 else
303 ep = epmap[skb_get_queue_mapping(skb)];
304 }
605bebe2 305
e6a9854b
JB		 306 info->rate_driver_data[0] = dev;
307 info->rate_driver_data[1] = urb;
6f7853f3
HTL		 308
309 usb_fill_bulk_urb(urb, priv->udev, usb_sndbulkpipe(priv->udev, ep),
310 buf, skb->len, rtl8187_tx_cb, skb);
2fcbab04 311 urb->transfer_flags |= URB_ZERO_PACKET;
c1db52b9 312 usb_anchor_urb(urb, &priv->anchored);
ea8ee240
ON		 313 rc = usb_submit_urb(urb, GFP_ATOMIC);
314 if (rc < 0) {
c1db52b9 315 usb_unanchor_urb(urb);
ea8ee240
ON		 316 kfree_skb(skb);
317 }
c1db52b9 318 usb_free_urb(urb);
605bebe2
MW		 319}
320
321static void rtl8187_rx_cb(struct urb *urb)
322{
323 struct sk_buff *skb = (struct sk_buff *)urb->context;
324 struct rtl8187_rx_info *info = (struct rtl8187_rx_info *)skb->cb;
325 struct ieee80211_hw *dev = info->dev;
326 struct rtl8187_priv *priv = dev->priv;
605bebe2
MW		 327 struct ieee80211_rx_status rx_status = { 0 };
328 int rate, signal;
4150c572 329 u32 flags;
d8588227 330 unsigned long f;
605bebe2 331
d8588227 332 spin_lock_irqsave(&priv->rx_queue.lock, f);
46c37672 333 __skb_unlink(skb, &priv->rx_queue);
d8588227 334 spin_unlock_irqrestore(&priv->rx_queue.lock, f);
c1db52b9 335 skb_put(skb, urb->actual_length);
605bebe2
MW		 336
337 if (unlikely(urb->status)) {
605bebe2
MW		 338 dev_kfree_skb_irq(skb);
339 return;
340 }
341
6f7853f3
HTL		 342 if (!priv->is_rtl8187b) {
343 struct rtl8187_rx_hdr *hdr =
344 (typeof(hdr))(skb_tail_pointer(skb) - sizeof(*hdr));
345 flags = le32_to_cpu(hdr->flags);
a7db74f4 346 /* As with the RTL8187B below, the AGC is used to calculate
70d9f405 347 * signal strength. In this case, the scaling
a7db74f4
LF		 348 * constants are derived from the output of p54usb.
349 */
a7db74f4 350 signal = -4 - ((27 * hdr->agc) >> 6);
6f7853f3 351 rx_status.antenna = (hdr->signal >> 7) & 1;
6f7853f3 352 rx_status.mactime = le64_to_cpu(hdr->mac_time);
6f7853f3
HTL		 353 } else {
354 struct rtl8187b_rx_hdr *hdr =
355 (typeof(hdr))(skb_tail_pointer(skb) - sizeof(*hdr));
0ccd58fc
LF		 356 /* The Realtek datasheet for the RTL8187B shows that the RX
357 * header contains the following quantities: signal quality,
358 * RSSI, AGC, the received power in dB, and the measured SNR.
359 * In testing, none of these quantities show qualitative
360 * agreement with AP signal strength, except for the AGC,
361 * which is inversely proportional to the strength of the
70d9f405
LF		 362 * signal. In the following, the signal strength
363 * is derived from the AGC. The arbitrary scaling constants
0ccd58fc
LF		 364 * are chosen to make the results close to the values obtained
365 * for a BCM4312 using b43 as the driver. The noise is ignored
366 * for now.
367 */
6f7853f3 368 flags = le32_to_cpu(hdr->flags);
0ccd58fc 369 signal = 14 - hdr->agc / 2;
0ccd58fc 370 rx_status.antenna = (hdr->rssi >> 7) & 1;
6f7853f3 371 rx_status.mactime = le64_to_cpu(hdr->mac_time);
6f7853f3 372 }
605bebe2 373
a7db74f4
LF		 374 rx_status.signal = signal;
375 priv->signal = signal;
376 rate = (flags >> 20) & 0xF;
6f7853f3 377 skb_trim(skb, flags & 0x0FFF);
8318d78a
JB		 378 rx_status.rate_idx = rate;
379 rx_status.freq = dev->conf.channel->center_freq;
380 rx_status.band = dev->conf.channel->band;
6ebacbb7 381 rx_status.flag |= RX_FLAG_MACTIME_MPDU;
38e3b0d8 382 if (flags & RTL818X_RX_DESC_FLAG_CRC32_ERR)
4150c572 383 rx_status.flag |= RX_FLAG_FAILED_FCS_CRC;
f1d58c25
JB		 384 memcpy(IEEE80211_SKB_RXCB(skb), &rx_status, sizeof(rx_status));
385 ieee80211_rx_irqsafe(dev, skb);
605bebe2
MW		 386
387 skb = dev_alloc_skb(RTL8187_MAX_RX);
388 if (unlikely(!skb)) {
605bebe2
MW		 389 /* TODO check rx queue length and refill *somewhere* */
390 return;
391 }
392
393 info = (struct rtl8187_rx_info *)skb->cb;
394 info->urb = urb;
395 info->dev = dev;
396 urb->transfer_buffer = skb_tail_pointer(skb);
397 urb->context = skb;
398 skb_queue_tail(&priv->rx_queue, skb);
399
c1db52b9
LF		 400 usb_anchor_urb(urb, &priv->anchored);
401 if (usb_submit_urb(urb, GFP_ATOMIC)) {
402 usb_unanchor_urb(urb);
403 skb_unlink(skb, &priv->rx_queue);
404 dev_kfree_skb_irq(skb);
405 }
605bebe2
MW		 406}
407
408static int rtl8187_init_urbs(struct ieee80211_hw *dev)
409{
410 struct rtl8187_priv *priv = dev->priv;
c1db52b9 411 struct urb *entry = NULL;
605bebe2
MW		 412 struct sk_buff *skb;
413 struct rtl8187_rx_info *info;
c1db52b9 414 int ret = 0;
605bebe2 415
2a57cf3e 416 while (skb_queue_len(&priv->rx_queue) < 16) {
605bebe2 417 skb = __dev_alloc_skb(RTL8187_MAX_RX, GFP_KERNEL);
c1db52b9
LF		 418 if (!skb) {
419 ret = -ENOMEM;
420 goto err;
421 }
605bebe2
MW		 422 entry = usb_alloc_urb(0, GFP_KERNEL);
423 if (!entry) {
c1db52b9
LF		 424 ret = -ENOMEM;
425 goto err;
605bebe2
MW		 426 }
427 usb_fill_bulk_urb(entry, priv->udev,
6f7853f3
HTL		 428 usb_rcvbulkpipe(priv->udev,
429 priv->is_rtl8187b ? 3 : 1),
605bebe2
MW		 430 skb_tail_pointer(skb),
431 RTL8187_MAX_RX, rtl8187_rx_cb, skb);
432 info = (struct rtl8187_rx_info *)skb->cb;
433 info->urb = entry;
434 info->dev = dev;
435 skb_queue_tail(&priv->rx_queue, skb);
c1db52b9
LF		 436 usb_anchor_urb(entry, &priv->anchored);
437 ret = usb_submit_urb(entry, GFP_KERNEL);
438 if (ret) {
439 skb_unlink(skb, &priv->rx_queue);
440 usb_unanchor_urb(entry);
441 goto err;
442 }
443 usb_free_urb(entry);
605bebe2 444 }
c1db52b9 445 return ret;
605bebe2 446
c1db52b9
LF		 447err:
448 usb_free_urb(entry);
449 kfree_skb(skb);
450 usb_kill_anchored_urbs(&priv->anchored);
451 return ret;
605bebe2
MW		 452}
453
3517afde
HRK		 454static void rtl8187b_status_cb(struct urb *urb)
455{
456 struct ieee80211_hw *hw = (struct ieee80211_hw *)urb->context;
457 struct rtl8187_priv *priv = hw->priv;
458 u64 val;
459 unsigned int cmd_type;
460
c1db52b9 461 if (unlikely(urb->status))
3517afde 462 return;
3517afde
HRK		 463
464 /*
465 * Read from status buffer:
466 *
467 * bits [30:31] = cmd type:
468 * - 0 indicates tx beacon interrupt
469 * - 1 indicates tx close descriptor
470 *
471 * In the case of tx beacon interrupt:
472 * [0:9] = Last Beacon CW
473 * [10:29] = reserved
474 * [30:31] = 00b
475 * [32:63] = Last Beacon TSF
476 *
477 * If it's tx close descriptor:
478 * [0:7] = Packet Retry Count
479 * [8:14] = RTS Retry Count
480 * [15] = TOK
481 * [16:27] = Sequence No
482 * [28] = LS
483 * [29] = FS
484 * [30:31] = 01b
485 * [32:47] = unused (reserved?)
486 * [48:63] = MAC Used Time
487 */
488 val = le64_to_cpu(priv->b_tx_status.buf);
489
490 cmd_type = (val >> 30) & 0x3;
491 if (cmd_type == 1) {
492 unsigned int pkt_rc, seq_no;
493 bool tok;
494 struct sk_buff *skb;
495 struct ieee80211_hdr *ieee80211hdr;
496 unsigned long flags;
497
498 pkt_rc = val & 0xFF;
499 tok = val & (1 << 15);
500 seq_no = (val >> 16) & 0xFFF;
501
502 spin_lock_irqsave(&priv->b_tx_status.queue.lock, flags);
503 skb_queue_reverse_walk(&priv->b_tx_status.queue, skb) {
504 ieee80211hdr = (struct ieee80211_hdr *)skb->data;
505
506 /*
507 * While testing, it was discovered that the seq_no
508 * doesn't actually contains the sequence number.
509 * Instead of returning just the 12 bits of sequence
510 * number, hardware is returning entire sequence control
511 * (fragment number plus sequence number) in a 12 bit
512 * only field overflowing after some time. As a
513 * workaround, just consider the lower bits, and expect
514 * it's unlikely we wrongly ack some sent data
515 */
516 if ((le16_to_cpu(ieee80211hdr->seq_ctrl)
517 & 0xFFF) == seq_no)
518 break;
519 }
520 if (skb != (struct sk_buff *) &priv->b_tx_status.queue) {
521 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
522
523 __skb_unlink(skb, &priv->b_tx_status.queue);
524 if (tok)
525 info->flags |= IEEE80211_TX_STAT_ACK;
1548c86a 526 info->status.rates[0].count = pkt_rc + 1;
3517afde
HRK		 527
528 ieee80211_tx_status_irqsafe(hw, skb);
529 }
530 spin_unlock_irqrestore(&priv->b_tx_status.queue.lock, flags);
531 }
532
c1db52b9
LF		 533 usb_anchor_urb(urb, &priv->anchored);
534 if (usb_submit_urb(urb, GFP_ATOMIC))
535 usb_unanchor_urb(urb);
3517afde
HRK		 536}
537
538static int rtl8187b_init_status_urb(struct ieee80211_hw *dev)
539{
540 struct rtl8187_priv *priv = dev->priv;
541 struct urb *entry;
c1db52b9 542 int ret = 0;
3517afde
HRK		 543
544 entry = usb_alloc_urb(0, GFP_KERNEL);
545 if (!entry)
546 return -ENOMEM;
3517afde
HRK		 547
548 usb_fill_bulk_urb(entry, priv->udev, usb_rcvbulkpipe(priv->udev, 9),
549 &priv->b_tx_status.buf, sizeof(priv->b_tx_status.buf),
550 rtl8187b_status_cb, dev);
551
c1db52b9
LF		 552 usb_anchor_urb(entry, &priv->anchored);
553 ret = usb_submit_urb(entry, GFP_KERNEL);
554 if (ret)
555 usb_unanchor_urb(entry);
556 usb_free_urb(entry);
3517afde 557
c1db52b9 558 return ret;
3517afde
HRK		 559}
560
0bf198eb
HRK		 561static void rtl8187_set_anaparam(struct rtl8187_priv *priv, bool rfon)
562{
563 u32 anaparam, anaparam2;
564 u8 anaparam3, reg;
565
566 if (!priv->is_rtl8187b) {
567 if (rfon) {
568 anaparam = RTL8187_RTL8225_ANAPARAM_ON;
569 anaparam2 = RTL8187_RTL8225_ANAPARAM2_ON;
570 } else {
571 anaparam = RTL8187_RTL8225_ANAPARAM_OFF;
572 anaparam2 = RTL8187_RTL8225_ANAPARAM2_OFF;
573 }
574 } else {
575 if (rfon) {
576 anaparam = RTL8187B_RTL8225_ANAPARAM_ON;
577 anaparam2 = RTL8187B_RTL8225_ANAPARAM2_ON;
578 anaparam3 = RTL8187B_RTL8225_ANAPARAM3_ON;
579 } else {
580 anaparam = RTL8187B_RTL8225_ANAPARAM_OFF;
581 anaparam2 = RTL8187B_RTL8225_ANAPARAM2_OFF;
582 anaparam3 = RTL8187B_RTL8225_ANAPARAM3_OFF;
583 }
584 }
585
586 rtl818x_iowrite8(priv, &priv->map->EEPROM_CMD,
587 RTL818X_EEPROM_CMD_CONFIG);
588 reg = rtl818x_ioread8(priv, &priv->map->CONFIG3);
589 reg |= RTL818X_CONFIG3_ANAPARAM_WRITE;
590 rtl818x_iowrite8(priv, &priv->map->CONFIG3, reg);
591 rtl818x_iowrite32(priv, &priv->map->ANAPARAM, anaparam);
592 rtl818x_iowrite32(priv, &priv->map->ANAPARAM2, anaparam2);
593 if (priv->is_rtl8187b)
594 rtl818x_iowrite8(priv, &priv->map->ANAPARAM3, anaparam3);
595 reg &= ~RTL818X_CONFIG3_ANAPARAM_WRITE;
596 rtl818x_iowrite8(priv, &priv->map->CONFIG3, reg);
597 rtl818x_iowrite8(priv, &priv->map->EEPROM_CMD,
598 RTL818X_EEPROM_CMD_NORMAL);
599}
600
f8a08c34 601static int rtl8187_cmd_reset(struct ieee80211_hw *dev)
605bebe2
MW		 602{
603 struct rtl8187_priv *priv = dev->priv;
604 u8 reg;
605 int i;
606
605bebe2
MW		 607 reg = rtl818x_ioread8(priv, &priv->map->CMD);
608 reg &= (1 << 1);
609 reg |= RTL818X_CMD_RESET;
610 rtl818x_iowrite8(priv, &priv->map->CMD, reg);
611
612 i = 10;
613 do {
614 msleep(2);
615 if (!(rtl818x_ioread8(priv, &priv->map->CMD) &
616 RTL818X_CMD_RESET))
617 break;
618 } while (--i);
619
620 if (!i) {
5db55844 621 wiphy_err(dev->wiphy, "Reset timeout!\n");
605bebe2
MW		 622 return -ETIMEDOUT;
623 }
624
625 /* reload registers from eeprom */
626 rtl818x_iowrite8(priv, &priv->map->EEPROM_CMD, RTL818X_EEPROM_CMD_LOAD);
627
628 i = 10;
629 do {
630 msleep(4);
631 if (!(rtl818x_ioread8(priv, &priv->map->EEPROM_CMD) &
632 RTL818X_EEPROM_CMD_CONFIG))
633 break;
634 } while (--i);
635
636 if (!i) {
c96c31e4 637 wiphy_err(dev->wiphy, "eeprom reset timeout!\n");
605bebe2
MW		 638 return -ETIMEDOUT;
639 }
640
f8a08c34
HTL		 641 return 0;
642}
643
644static int rtl8187_init_hw(struct ieee80211_hw *dev)
645{
646 struct rtl8187_priv *priv = dev->priv;
647 u8 reg;
648 int res;
649
650 /* reset */
0bf198eb 651 rtl8187_set_anaparam(priv, true);
f8a08c34
HTL		 652
653 rtl818x_iowrite16(priv, &priv->map->INT_MASK, 0);
654
655 msleep(200);
656 rtl818x_iowrite8(priv, (u8 *)0xFE18, 0x10);
657 rtl818x_iowrite8(priv, (u8 *)0xFE18, 0x11);
658 rtl818x_iowrite8(priv, (u8 *)0xFE18, 0x00);
659 msleep(200);
660
661 res = rtl8187_cmd_reset(dev);
662 if (res)
663 return res;
664
0bf198eb 665 rtl8187_set_anaparam(priv, true);
605bebe2
MW		 666
667 /* setup card */
668 rtl818x_iowrite16(priv, &priv->map->RFPinsSelect, 0);
ca9152e3 669 rtl818x_iowrite8(priv, &priv->map->GPIO0, 0);
605bebe2
MW		 670
671 rtl818x_iowrite16(priv, &priv->map->RFPinsSelect, (4 << 8));
ca9152e3 672 rtl818x_iowrite8(priv, &priv->map->GPIO0, 1);
605bebe2
MW		 673 rtl818x_iowrite8(priv, &priv->map->GP_ENABLE, 0);
674
675 rtl818x_iowrite8(priv, &priv->map->EEPROM_CMD, RTL818X_EEPROM_CMD_CONFIG);
605bebe2
MW		 676
677 rtl818x_iowrite16(priv, (__le16 *)0xFFF4, 0xFFFF);
678 reg = rtl818x_ioread8(priv, &priv->map->CONFIG1);
679 reg &= 0x3F;
680 reg |= 0x80;
681 rtl818x_iowrite8(priv, &priv->map->CONFIG1, reg);
682
683 rtl818x_iowrite8(priv, &priv->map->EEPROM_CMD, RTL818X_EEPROM_CMD_NORMAL);
684
685 rtl818x_iowrite32(priv, &priv->map->INT_TIMEOUT, 0);
686 rtl818x_iowrite8(priv, &priv->map->WPA_CONF, 0);
2f47690e 687 rtl818x_iowrite8(priv, &priv->map->RATE_FALLBACK, 0);
605bebe2
MW		 688
689 // TODO: set RESP_RATE and BRSR properly
690 rtl818x_iowrite8(priv, &priv->map->RESP_RATE, (8 << 4) | 0);
691 rtl818x_iowrite16(priv, &priv->map->BRSR, 0x01F3);
692
693 /* host_usb_init */
694 rtl818x_iowrite16(priv, &priv->map->RFPinsSelect, 0);
ca9152e3 695 rtl818x_iowrite8(priv, &priv->map->GPIO0, 0);
605bebe2
MW		 696 reg = rtl818x_ioread8(priv, (u8 *)0xFE53);
697 rtl818x_iowrite8(priv, (u8 *)0xFE53, reg | (1 << 7));
698 rtl818x_iowrite16(priv, &priv->map->RFPinsSelect, (4 << 8));
ca9152e3 699 rtl818x_iowrite8(priv, &priv->map->GPIO0, 0x20);
605bebe2
MW		 700 rtl818x_iowrite8(priv, &priv->map->GP_ENABLE, 0);
701 rtl818x_iowrite16(priv, &priv->map->RFPinsOutput, 0x80);
702 rtl818x_iowrite16(priv, &priv->map->RFPinsSelect, 0x80);
703 rtl818x_iowrite16(priv, &priv->map->RFPinsEnable, 0x80);
704 msleep(100);
705
706 rtl818x_iowrite32(priv, &priv->map->RF_TIMING, 0x000a8008);
707 rtl818x_iowrite16(priv, &priv->map->BRSR, 0xFFFF);
708 rtl818x_iowrite32(priv, &priv->map->RF_PARA, 0x00100044);
f8a08c34
HTL		 709 rtl818x_iowrite8(priv, &priv->map->EEPROM_CMD,
710 RTL818X_EEPROM_CMD_CONFIG);
605bebe2 711 rtl818x_iowrite8(priv, &priv->map->CONFIG3, 0x44);
f8a08c34
HTL		 712 rtl818x_iowrite8(priv, &priv->map->EEPROM_CMD,
713 RTL818X_EEPROM_CMD_NORMAL);
605bebe2
MW		 714 rtl818x_iowrite16(priv, &priv->map->RFPinsEnable, 0x1FF7);
715 msleep(100);
716
f6532111 717 priv->rf->init(dev);
605bebe2
MW		 718
719 rtl818x_iowrite16(priv, &priv->map->BRSR, 0x01F3);
f6532111
MW		 720 reg = rtl818x_ioread8(priv, &priv->map->PGSELECT) & ~1;
721 rtl818x_iowrite8(priv, &priv->map->PGSELECT, reg | 1);
605bebe2
MW		 722 rtl818x_iowrite16(priv, (__le16 *)0xFFFE, 0x10);
723 rtl818x_iowrite8(priv, &priv->map->TALLY_SEL, 0x80);
724 rtl818x_iowrite8(priv, (u8 *)0xFFFF, 0x60);
f6532111 725 rtl818x_iowrite8(priv, &priv->map->PGSELECT, reg);
605bebe2
MW		 726
727 return 0;
728}
729
f8a08c34
HTL		 730static const u8 rtl8187b_reg_table[][3] = {
731 {0xF0, 0x32, 0}, {0xF1, 0x32, 0}, {0xF2, 0x00, 0}, {0xF3, 0x00, 0},
732 {0xF4, 0x32, 0}, {0xF5, 0x43, 0}, {0xF6, 0x00, 0}, {0xF7, 0x00, 0},
733 {0xF8, 0x46, 0}, {0xF9, 0xA4, 0}, {0xFA, 0x00, 0}, {0xFB, 0x00, 0},
734 {0xFC, 0x96, 0}, {0xFD, 0xA4, 0}, {0xFE, 0x00, 0}, {0xFF, 0x00, 0},
735
736 {0x58, 0x4B, 1}, {0x59, 0x00, 1}, {0x5A, 0x4B, 1}, {0x5B, 0x00, 1},
737 {0x60, 0x4B, 1}, {0x61, 0x09, 1}, {0x62, 0x4B, 1}, {0x63, 0x09, 1},
327571ea
HRK		 738 {0xCE, 0x0F, 1}, {0xCF, 0x00, 1}, {0xF0, 0x4E, 1}, {0xF1, 0x01, 1},
739 {0xF2, 0x02, 1}, {0xF3, 0x03, 1}, {0xF4, 0x04, 1}, {0xF5, 0x05, 1},
740 {0xF6, 0x06, 1}, {0xF7, 0x07, 1}, {0xF8, 0x08, 1},
f8a08c34
HTL		 741
742 {0x4E, 0x00, 2}, {0x0C, 0x04, 2}, {0x21, 0x61, 2}, {0x22, 0x68, 2},
743 {0x23, 0x6F, 2}, {0x24, 0x76, 2}, {0x25, 0x7D, 2}, {0x26, 0x84, 2},
744 {0x27, 0x8D, 2}, {0x4D, 0x08, 2}, {0x50, 0x05, 2}, {0x51, 0xF5, 2},
745 {0x52, 0x04, 2}, {0x53, 0xA0, 2}, {0x54, 0x1F, 2}, {0x55, 0x23, 2},
746 {0x56, 0x45, 2}, {0x57, 0x67, 2}, {0x58, 0x08, 2}, {0x59, 0x08, 2},
747 {0x5A, 0x08, 2}, {0x5B, 0x08, 2}, {0x60, 0x08, 2}, {0x61, 0x08, 2},
a8ff34e3 748 {0x62, 0x08, 2}, {0x63, 0x08, 2}, {0x64, 0xCF, 2},
f8a08c34 749
60f58914
HRK		 750 {0x5B, 0x40, 0}, {0x84, 0x88, 0}, {0x85, 0x24, 0}, {0x88, 0x54, 0},
751 {0x8B, 0xB8, 0}, {0x8C, 0x07, 0}, {0x8D, 0x00, 0}, {0x94, 0x1B, 0},
752 {0x95, 0x12, 0}, {0x96, 0x00, 0}, {0x97, 0x06, 0}, {0x9D, 0x1A, 0},
753 {0x9F, 0x10, 0}, {0xB4, 0x22, 0}, {0xBE, 0x80, 0}, {0xDB, 0x00, 0},
754 {0xEE, 0x00, 0}, {0x4C, 0x00, 2},
f8a08c34 755
a027087a
LF		 756 {0x9F, 0x00, 3}, {0x8C, 0x01, 0}, {0x8D, 0x10, 0}, {0x8E, 0x08, 0},
757 {0x8F, 0x00, 0}
f8a08c34
HTL		 758};
759
760static int rtl8187b_init_hw(struct ieee80211_hw *dev)
761{
762 struct rtl8187_priv *priv = dev->priv;
763 int res, i;
764 u8 reg;
765
0bf198eb 766 rtl8187_set_anaparam(priv, true);
f8a08c34 767
896cae65
HRK		 768 /* Reset PLL sequence on 8187B. Realtek note: reduces power
769 * consumption about 30 mA */
770 rtl818x_iowrite8(priv, (u8 *)0xFF61, 0x10);
771 reg = rtl818x_ioread8(priv, (u8 *)0xFF62);
772 rtl818x_iowrite8(priv, (u8 *)0xFF62, reg & ~(1 << 5));
773 rtl818x_iowrite8(priv, (u8 *)0xFF62, reg | (1 << 5));
774
f8a08c34
HTL		 775 res = rtl8187_cmd_reset(dev);
776 if (res)
777 return res;
778
daeeb074
HRK		 779 rtl8187_set_anaparam(priv, true);
780
60f58914
HRK		 781 /* BRSR (Basic Rate Set Register) on 8187B looks to be the same as
782 * RESP_RATE on 8187L in Realtek sources: each bit should be each
783 * one of the 12 rates, all are enabled */
784 rtl818x_iowrite16(priv, (__le16 *)0xFF34, 0x0FFF);
785
f8a08c34
HTL		 786 reg = rtl818x_ioread8(priv, &priv->map->CW_CONF);
787 reg |= RTL818X_CW_CONF_PERPACKET_RETRY_SHIFT;
788 rtl818x_iowrite8(priv, &priv->map->CW_CONF, reg);
f8a08c34 789
327571ea 790 /* Auto Rate Fallback Register (ARFR): 1M-54M setting */
f8a08c34 791 rtl818x_iowrite16_idx(priv, (__le16 *)0xFFE0, 0x0FFF, 1);
327571ea 792 rtl818x_iowrite8_idx(priv, (u8 *)0xFFE2, 0x00, 1);
f8a08c34 793
f8a08c34
HTL		 794 rtl818x_iowrite16_idx(priv, (__le16 *)0xFFD4, 0xFFFF, 1);
795
796 rtl818x_iowrite8(priv, &priv->map->EEPROM_CMD,
797 RTL818X_EEPROM_CMD_CONFIG);
798 reg = rtl818x_ioread8(priv, &priv->map->CONFIG1);
799 rtl818x_iowrite8(priv, &priv->map->CONFIG1, (reg & 0x3F) | 0x80);
800 rtl818x_iowrite8(priv, &priv->map->EEPROM_CMD,
801 RTL818X_EEPROM_CMD_NORMAL);
802
803 rtl818x_iowrite8(priv, &priv->map->WPA_CONF, 0);
804 for (i = 0; i < ARRAY_SIZE(rtl8187b_reg_table); i++) {
805 rtl818x_iowrite8_idx(priv,
806 (u8 *)(uintptr_t)
807 (rtl8187b_reg_table[i][0] | 0xFF00),
808 rtl8187b_reg_table[i][1],
809 rtl8187b_reg_table[i][2]);
810 }
811
812 rtl818x_iowrite16(priv, &priv->map->TID_AC_MAP, 0xFA50);
813 rtl818x_iowrite16(priv, &priv->map->INT_MIG, 0);
814
815 rtl818x_iowrite32_idx(priv, (__le32 *)0xFFF0, 0, 1);
816 rtl818x_iowrite32_idx(priv, (__le32 *)0xFFF4, 0, 1);
817 rtl818x_iowrite8_idx(priv, (u8 *)0xFFF8, 0, 1);
818
819 rtl818x_iowrite32(priv, &priv->map->RF_TIMING, 0x00004001);
820
a8ff34e3 821 /* RFSW_CTRL register */
f8a08c34
HTL		 822 rtl818x_iowrite16_idx(priv, (__le16 *)0xFF72, 0x569A, 2);
823
f8a08c34
HTL		 824 rtl818x_iowrite16(priv, &priv->map->RFPinsOutput, 0x0480);
825 rtl818x_iowrite16(priv, &priv->map->RFPinsSelect, 0x2488);
826 rtl818x_iowrite16(priv, &priv->map->RFPinsEnable, 0x1FFF);
2f20596b 827 msleep(100);
f8a08c34
HTL		 828
829 priv->rf->init(dev);
830
831 reg = RTL818X_CMD_TX_ENABLE | RTL818X_CMD_RX_ENABLE;
832 rtl818x_iowrite8(priv, &priv->map->CMD, reg);
833 rtl818x_iowrite16(priv, &priv->map->INT_MASK, 0xFFFF);
834
835 rtl818x_iowrite8(priv, (u8 *)0xFE41, 0xF4);
836 rtl818x_iowrite8(priv, (u8 *)0xFE40, 0x00);
837 rtl818x_iowrite8(priv, (u8 *)0xFE42, 0x00);
838 rtl818x_iowrite8(priv, (u8 *)0xFE42, 0x01);
839 rtl818x_iowrite8(priv, (u8 *)0xFE40, 0x0F);
840 rtl818x_iowrite8(priv, (u8 *)0xFE42, 0x00);
841 rtl818x_iowrite8(priv, (u8 *)0xFE42, 0x01);
842
843 reg = rtl818x_ioread8(priv, (u8 *)0xFFDB);
844 rtl818x_iowrite8(priv, (u8 *)0xFFDB, reg | (1 << 2));
845 rtl818x_iowrite16_idx(priv, (__le16 *)0xFF72, 0x59FA, 3);
846 rtl818x_iowrite16_idx(priv, (__le16 *)0xFF74, 0x59D2, 3);
847 rtl818x_iowrite16_idx(priv, (__le16 *)0xFF76, 0x59D2, 3);
848 rtl818x_iowrite16_idx(priv, (__le16 *)0xFF78, 0x19FA, 3);
849 rtl818x_iowrite16_idx(priv, (__le16 *)0xFF7A, 0x19FA, 3);
850 rtl818x_iowrite16_idx(priv, (__le16 *)0xFF7C, 0x00D0, 3);
851 rtl818x_iowrite8(priv, (u8 *)0xFF61, 0);
852 rtl818x_iowrite8_idx(priv, (u8 *)0xFF80, 0x0F, 1);
853 rtl818x_iowrite8_idx(priv, (u8 *)0xFF83, 0x03, 1);
854 rtl818x_iowrite8(priv, (u8 *)0xFFDA, 0x10);
855 rtl818x_iowrite8_idx(priv, (u8 *)0xFF4D, 0x08, 2);
856
857 rtl818x_iowrite32(priv, &priv->map->HSSI_PARA, 0x0600321B);
858
859 rtl818x_iowrite16_idx(priv, (__le16 *)0xFFEC, 0x0800, 1);
860
b4572a92
HRK		 861 priv->slot_time = 0x9;
862 priv->aifsn[0] = 2; /* AIFSN[AC_VO] */
863 priv->aifsn[1] = 2; /* AIFSN[AC_VI] */
864 priv->aifsn[2] = 7; /* AIFSN[AC_BK] */
865 priv->aifsn[3] = 3; /* AIFSN[AC_BE] */
866 rtl818x_iowrite8(priv, &priv->map->ACM_CONTROL, 0);
867
1a9937b7
HRK		 868 /* ENEDCA flag must always be set, transmit issues? */
869 rtl818x_iowrite8(priv, &priv->map->MSR, RTL818X_MSR_ENEDCA);
870
f8a08c34
HTL		 871 return 0;
872}
873
2f47690e
LF		 874static void rtl8187_work(struct work_struct *work)
875{
876 /* The RTL8187 returns the retry count through register 0xFFFA. In
877 * addition, it appears to be a cumulative retry count, not the
878 * value for the current TX packet. When multiple TX entries are
6410db59
LF		 879 * waiting in the queue, the retry count will be the total for all.
880 * The "error" may matter for purposes of rate setting, but there is
881 * no other choice with this hardware.
882 */
2f47690e
LF		 883 struct rtl8187_priv *priv = container_of(work, struct rtl8187_priv,
884 work.work);
885 struct ieee80211_tx_info *info;
886 struct ieee80211_hw *dev = priv->dev;
887 static u16 retry;
888 u16 tmp;
6410db59
LF		 889 u16 avg_retry;
890 int length;
2f47690e
LF		 891
892 mutex_lock(&priv->conf_mutex);
893 tmp = rtl818x_ioread16(priv, (__le16 *)0xFFFA);
6410db59
LF		 894 length = skb_queue_len(&priv->b_tx_status.queue);
895 if (unlikely(!length))
896 length = 1;
897 if (unlikely(tmp < retry))
898 tmp = retry;
899 avg_retry = (tmp - retry) / length;
2f47690e
LF		 900 while (skb_queue_len(&priv->b_tx_status.queue) > 0) {
901 struct sk_buff *old_skb;
902
903 old_skb = skb_dequeue(&priv->b_tx_status.queue);
904 info = IEEE80211_SKB_CB(old_skb);
6410db59
LF		 905 info->status.rates[0].count = avg_retry + 1;
906 if (info->status.rates[0].count > RETRY_COUNT)
907 info->flags &= ~IEEE80211_TX_STAT_ACK;
2f47690e
LF		 908 ieee80211_tx_status_irqsafe(dev, old_skb);
909 }
910 retry = tmp;
911 mutex_unlock(&priv->conf_mutex);
912}
913
4150c572 914static int rtl8187_start(struct ieee80211_hw *dev)
605bebe2
MW		 915{
916 struct rtl8187_priv *priv = dev->priv;
917 u32 reg;
918 int ret;
919
ca9152e3
HRK		 920 mutex_lock(&priv->conf_mutex);
921
f8a08c34
HTL		 922 ret = (!priv->is_rtl8187b) ? rtl8187_init_hw(dev) :
923 rtl8187b_init_hw(dev);
605bebe2 924 if (ret)
ca9152e3 925 goto rtl8187_start_exit;
c1db52b9
LF		 926
927 init_usb_anchor(&priv->anchored);
2f47690e 928 priv->dev = dev;
c1db52b9 929
f8a08c34
HTL		 930 if (priv->is_rtl8187b) {
931 reg = RTL818X_RX_CONF_MGMT |
932 RTL818X_RX_CONF_DATA |
933 RTL818X_RX_CONF_BROADCAST |
934 RTL818X_RX_CONF_NICMAC |
935 RTL818X_RX_CONF_BSSID |
936 (7 << 13 /* RX FIFO threshold NONE */) |
937 (7 << 10 /* MAX RX DMA */) |
938 RTL818X_RX_CONF_RX_AUTORESETPHY |
939 RTL818X_RX_CONF_ONLYERLPKT |
940 RTL818X_RX_CONF_MULTICAST;
941 priv->rx_conf = reg;
942 rtl818x_iowrite32(priv, &priv->map->RX_CONF, reg);
943
19999792
TLSC		 944 reg = rtl818x_ioread8(priv, &priv->map->TX_AGC_CTL);
945 reg &= ~RTL818X_TX_AGC_CTL_PERPACKET_GAIN_SHIFT;
946 reg &= ~RTL818X_TX_AGC_CTL_PERPACKET_ANTSEL_SHIFT;
947 reg &= ~RTL818X_TX_AGC_CTL_FEEDBACK_ANT;
948 rtl818x_iowrite8(priv, &priv->map->TX_AGC_CTL, reg);
949
f8a08c34
HTL		 950 rtl818x_iowrite32(priv, &priv->map->TX_CONF,
951 RTL818X_TX_CONF_HW_SEQNUM |
952 RTL818X_TX_CONF_DISREQQSIZE |
6410db59
LF		 953 (RETRY_COUNT << 8 /* short retry limit */) |
954 (RETRY_COUNT << 0 /* long retry limit */) |
f8a08c34
HTL		 955 (7 << 21 /* MAX TX DMA */));
956 rtl8187_init_urbs(dev);
3517afde 957 rtl8187b_init_status_urb(dev);
ca9152e3 958 goto rtl8187_start_exit;
f8a08c34
HTL		 959 }
960
605bebe2
MW		 961 rtl818x_iowrite16(priv, &priv->map->INT_MASK, 0xFFFF);
962
2fe14263
MW		 963 rtl818x_iowrite32(priv, &priv->map->MAR[0], ~0);
964 rtl818x_iowrite32(priv, &priv->map->MAR[1], ~0);
965
605bebe2
MW		 966 rtl8187_init_urbs(dev);
967
968 reg = RTL818X_RX_CONF_ONLYERLPKT |
969 RTL818X_RX_CONF_RX_AUTORESETPHY |
970 RTL818X_RX_CONF_BSSID |
971 RTL818X_RX_CONF_MGMT |
605bebe2
MW		 972 RTL818X_RX_CONF_DATA |
973 (7 << 13 /* RX FIFO threshold NONE */) |
974 (7 << 10 /* MAX RX DMA */) |
975 RTL818X_RX_CONF_BROADCAST |
605bebe2 976 RTL818X_RX_CONF_NICMAC;
605bebe2 977
4150c572 978 priv->rx_conf = reg;
605bebe2
MW		 979 rtl818x_iowrite32(priv, &priv->map->RX_CONF, reg);
980
981 reg = rtl818x_ioread8(priv, &priv->map->CW_CONF);
982 reg &= ~RTL818X_CW_CONF_PERPACKET_CW_SHIFT;
983 reg |= RTL818X_CW_CONF_PERPACKET_RETRY_SHIFT;
984 rtl818x_iowrite8(priv, &priv->map->CW_CONF, reg);
985
986 reg = rtl818x_ioread8(priv, &priv->map->TX_AGC_CTL);
987 reg &= ~RTL818X_TX_AGC_CTL_PERPACKET_GAIN_SHIFT;
988 reg &= ~RTL818X_TX_AGC_CTL_PERPACKET_ANTSEL_SHIFT;
989 reg &= ~RTL818X_TX_AGC_CTL_FEEDBACK_ANT;
990 rtl818x_iowrite8(priv, &priv->map->TX_AGC_CTL, reg);
991
992 reg = RTL818X_TX_CONF_CW_MIN |
993 (7 << 21 /* MAX TX DMA */) |
994 RTL818X_TX_CONF_NO_ICV;
995 rtl818x_iowrite32(priv, &priv->map->TX_CONF, reg);
996
997 reg = rtl818x_ioread8(priv, &priv->map->CMD);
998 reg |= RTL818X_CMD_TX_ENABLE;
999 reg |= RTL818X_CMD_RX_ENABLE;
1000 rtl818x_iowrite8(priv, &priv->map->CMD, reg);
2f47690e 1001 INIT_DELAYED_WORK(&priv->work, rtl8187_work);
605bebe2 1002
ca9152e3
HRK		 1003rtl8187_start_exit:
1004 mutex_unlock(&priv->conf_mutex);
1005 return ret;
605bebe2
MW		 1006}
1007
4150c572 1008static void rtl8187_stop(struct ieee80211_hw *dev)
605bebe2
MW		 1009{
1010 struct rtl8187_priv *priv = dev->priv;
605bebe2
MW		 1011 struct sk_buff *skb;
1012 u32 reg;
1013
7dcdd073 1014 mutex_lock(&priv->conf_mutex);
605bebe2
MW		 1015 rtl818x_iowrite16(priv, &priv->map->INT_MASK, 0);
1016
1017 reg = rtl818x_ioread8(priv, &priv->map->CMD);
1018 reg &= ~RTL818X_CMD_TX_ENABLE;
1019 reg &= ~RTL818X_CMD_RX_ENABLE;
1020 rtl818x_iowrite8(priv, &priv->map->CMD, reg);
1021
f6532111 1022 priv->rf->stop(dev);
0bf198eb 1023 rtl8187_set_anaparam(priv, false);
605bebe2
MW		 1024
1025 rtl818x_iowrite8(priv, &priv->map->EEPROM_CMD, RTL818X_EEPROM_CMD_CONFIG);
1026 reg = rtl818x_ioread8(priv, &priv->map->CONFIG4);
1027 rtl818x_iowrite8(priv, &priv->map->CONFIG4, reg | RTL818X_CONFIG4_VCOOFF);
1028 rtl818x_iowrite8(priv, &priv->map->EEPROM_CMD, RTL818X_EEPROM_CMD_NORMAL);
1029
3517afde
HRK		 1030 while ((skb = skb_dequeue(&priv->b_tx_status.queue)))
1031 dev_kfree_skb_any(skb);
c1db52b9
LF		 1032
1033 usb_kill_anchored_urbs(&priv->anchored);
6a8171f2
HRK		 1034 mutex_unlock(&priv->conf_mutex);
1035
2f47690e
LF		 1036 if (!priv->is_rtl8187b)
1037 cancel_delayed_work_sync(&priv->work);
605bebe2
MW		 1038}
1039
41b58f18
AF		 1040static u64 rtl8187_get_tsf(struct ieee80211_hw *dev, struct ieee80211_vif *vif)
1041{
1042 struct rtl8187_priv *priv = dev->priv;
1043
1044 return rtl818x_ioread32(priv, &priv->map->TSFT[0]) |
1045 (u64)(rtl818x_ioread32(priv, &priv->map->TSFT[1])) << 32;
1046}
1047
1048
1049static void rtl8187_beacon_work(struct work_struct *work)
1050{
1051 struct rtl8187_vif *vif_priv =
1052 container_of(work, struct rtl8187_vif, beacon_work.work);
1053 struct ieee80211_vif *vif =
1054 container_of((void *)vif_priv, struct ieee80211_vif, drv_priv);
1055 struct ieee80211_hw *dev = vif_priv->dev;
1056 struct ieee80211_mgmt *mgmt;
1057 struct sk_buff *skb;
1058
1059 /* don't overflow the tx ring */
1060 if (ieee80211_queue_stopped(dev, 0))
1061 goto resched;
1062
1063 /* grab a fresh beacon */
1064 skb = ieee80211_beacon_get(dev, vif);
1065 if (!skb)
1066 goto resched;
1067
1068 /*
1069 * update beacon timestamp w/ TSF value
1070 * TODO: make hardware update beacon timestamp
1071 */
1072 mgmt = (struct ieee80211_mgmt *)skb->data;
1073 mgmt->u.beacon.timestamp = cpu_to_le64(rtl8187_get_tsf(dev, vif));
1074
1075 /* TODO: use actual beacon queue */
1076 skb_set_queue_mapping(skb, 0);
1077
1078 rtl8187_tx(dev, skb);
1079
1080resched:
1081 /*
1082 * schedule next beacon
1083 * TODO: use hardware support for beacon timing
1084 */
1085 schedule_delayed_work(&vif_priv->beacon_work,
1086 usecs_to_jiffies(1024 * vif->bss_conf.beacon_int));
1087}
1088
1089
605bebe2 1090static int rtl8187_add_interface(struct ieee80211_hw *dev,
1ed32e4f 1091 struct ieee80211_vif *vif)
605bebe2
MW		 1092{
1093 struct rtl8187_priv *priv = dev->priv;
41b58f18 1094 struct rtl8187_vif *vif_priv;
4150c572 1095 int i;
66aafd9a 1096 int ret = -EOPNOTSUPP;
605bebe2 1097
66aafd9a 1098 mutex_lock(&priv->conf_mutex);
d30506e0 1099 if (priv->vif)
66aafd9a 1100 goto exit;
605bebe2 1101
1ed32e4f 1102 switch (vif->type) {
05c914fe 1103 case NL80211_IFTYPE_STATION:
41b58f18 1104 case NL80211_IFTYPE_ADHOC:
605bebe2
MW		 1105 break;
1106 default:
66aafd9a 1107 goto exit;
605bebe2
MW		 1108 }
1109
66aafd9a 1110 ret = 0;
1ed32e4f 1111 priv->vif = vif;
aa979a6a 1112
41b58f18
AF		 1113 /* Initialize driver private area */
1114 vif_priv = (struct rtl8187_vif *)&vif->drv_priv;
1115 vif_priv->dev = dev;
1116 INIT_DELAYED_WORK(&vif_priv->beacon_work, rtl8187_beacon_work);
1117 vif_priv->enable_beacon = false;
1118
1119
4150c572
JB		 1120 rtl818x_iowrite8(priv, &priv->map->EEPROM_CMD, RTL818X_EEPROM_CMD_CONFIG);
1121 for (i = 0; i < ETH_ALEN; i++)
1122 rtl818x_iowrite8(priv, &priv->map->MAC[i],
1ed32e4f 1123 ((u8 *)vif->addr)[i]);
4150c572 1124 rtl818x_iowrite8(priv, &priv->map->EEPROM_CMD, RTL818X_EEPROM_CMD_NORMAL);
605bebe2 1125
66aafd9a 1126exit:
7dcdd073 1127 mutex_unlock(&priv->conf_mutex);
66aafd9a 1128 return ret;
605bebe2
MW		 1129}
1130
1131static void rtl8187_remove_interface(struct ieee80211_hw *dev,
1ed32e4f 1132 struct ieee80211_vif *vif)
605bebe2
MW		 1133{
1134 struct rtl8187_priv *priv = dev->priv;
7dcdd073 1135 mutex_lock(&priv->conf_mutex);
aa979a6a 1136 priv->vif = NULL;
7dcdd073 1137 mutex_unlock(&priv->conf_mutex);
605bebe2
MW		 1138}
1139
e8975581 1140static int rtl8187_config(struct ieee80211_hw *dev, u32 changed)
605bebe2
MW		 1141{
1142 struct rtl8187_priv *priv = dev->priv;
e8975581 1143 struct ieee80211_conf *conf = &dev->conf;
f6532111
MW		 1144 u32 reg;
1145
7dcdd073 1146 mutex_lock(&priv->conf_mutex);
f6532111
MW		 1147 reg = rtl818x_ioread32(priv, &priv->map->TX_CONF);
1148 /* Enable TX loopback on MAC level to avoid TX during channel
1149 * changes, as this has be seen to causes problems and the
1150 * card will stop work until next reset
1151 */
1152 rtl818x_iowrite32(priv, &priv->map->TX_CONF,
1153 reg | RTL818X_TX_CONF_LOOPBACK_MAC);
f6532111
MW		 1154 priv->rf->set_chan(dev, conf);
1155 msleep(10);
1156 rtl818x_iowrite32(priv, &priv->map->TX_CONF, reg);
605bebe2 1157
605bebe2
MW		 1158 rtl818x_iowrite16(priv, &priv->map->ATIM_WND, 2);
1159 rtl818x_iowrite16(priv, &priv->map->ATIMTR_INTERVAL, 100);
1160 rtl818x_iowrite16(priv, &priv->map->BEACON_INTERVAL, 100);
1161 rtl818x_iowrite16(priv, &priv->map->BEACON_INTERVAL_TIME, 100);
7dcdd073 1162 mutex_unlock(&priv->conf_mutex);
605bebe2
MW		 1163 return 0;
1164}
1165
b4572a92
HRK		 1166/*
1167 * With 8187B, AC_*_PARAM clashes with FEMR definition in struct rtl818x_csr for
1168 * example. Thus we have to use raw values for AC_*_PARAM register addresses.
1169 */
1170static __le32 *rtl8187b_ac_addr[4] = {
1171 (__le32 *) 0xFFF0, /* AC_VO */
1172 (__le32 *) 0xFFF4, /* AC_VI */
1173 (__le32 *) 0xFFFC, /* AC_BK */
1174 (__le32 *) 0xFFF8, /* AC_BE */
1175};
1176
1177#define SIFS_TIME 0xa
1178
f8288317
HRK		 1179static void rtl8187_conf_erp(struct rtl8187_priv *priv, bool use_short_slot,
1180 bool use_short_preamble)
64761077 1181{
f8288317 1182 if (priv->is_rtl8187b) {
b4572a92 1183 u8 difs, eifs;
f8288317 1184 u16 ack_timeout;
b4572a92 1185 int queue;
f8288317
HRK		 1186
1187 if (use_short_slot) {
b4572a92 1188 priv->slot_time = 0x9;
f8288317
HRK		 1189 difs = 0x1c;
1190 eifs = 0x53;
1191 } else {
b4572a92 1192 priv->slot_time = 0x14;
f8288317
HRK		 1193 difs = 0x32;
1194 eifs = 0x5b;
1195 }
54ac218a 1196 rtl818x_iowrite8(priv, &priv->map->SIFS, 0x22);
b4572a92 1197 rtl818x_iowrite8(priv, &priv->map->SLOT, priv->slot_time);
f8288317
HRK		 1198 rtl818x_iowrite8(priv, &priv->map->DIFS, difs);
1199
1200 /*
1201 * BRSR+1 on 8187B is in fact EIFS register
1202 * Value in units of 4 us
1203 */
1204 rtl818x_iowrite8(priv, (u8 *)&priv->map->BRSR + 1, eifs);
1205
1206 /*
1207 * For 8187B, CARRIER_SENSE_COUNTER is in fact ack timeout
1208 * register. In units of 4 us like eifs register
1209 * ack_timeout = ack duration + plcp + difs + preamble
1210 */
1211 ack_timeout = 112 + 48 + difs;
1212 if (use_short_preamble)
1213 ack_timeout += 72;
1214 else
1215 ack_timeout += 144;
1216 rtl818x_iowrite8(priv, &priv->map->CARRIER_SENSE_COUNTER,
1217 DIV_ROUND_UP(ack_timeout, 4));
b4572a92
HRK		 1218
1219 for (queue = 0; queue < 4; queue++)
1220 rtl818x_iowrite8(priv, (u8 *) rtl8187b_ac_addr[queue],
1221 priv->aifsn[queue] * priv->slot_time +
1222 SIFS_TIME);
f8288317 1223 } else {
64761077
HRK		 1224 rtl818x_iowrite8(priv, &priv->map->SIFS, 0x22);
1225 if (use_short_slot) {
1226 rtl818x_iowrite8(priv, &priv->map->SLOT, 0x9);
1227 rtl818x_iowrite8(priv, &priv->map->DIFS, 0x14);
1228 rtl818x_iowrite8(priv, &priv->map->EIFS, 91 - 0x14);
64761077
HRK		 1229 } else {
1230 rtl818x_iowrite8(priv, &priv->map->SLOT, 0x14);
1231 rtl818x_iowrite8(priv, &priv->map->DIFS, 0x24);
1232 rtl818x_iowrite8(priv, &priv->map->EIFS, 91 - 0x24);
64761077
HRK		 1233 }
1234 }
1235}
1236
1237static void rtl8187_bss_info_changed(struct ieee80211_hw *dev,
1238 struct ieee80211_vif *vif,
1239 struct ieee80211_bss_conf *info,
1240 u32 changed)
1241{
1242 struct rtl8187_priv *priv = dev->priv;
41b58f18 1243 struct rtl8187_vif *vif_priv;
2d0ddec5
JB		 1244 int i;
1245 u8 reg;
1246
41b58f18
AF		 1247 vif_priv = (struct rtl8187_vif *)&vif->drv_priv;
1248
2d0ddec5
JB		 1249 if (changed & BSS_CHANGED_BSSID) {
1250 mutex_lock(&priv->conf_mutex);
1251 for (i = 0; i < ETH_ALEN; i++)
1252 rtl818x_iowrite8(priv, &priv->map->BSSID[i],
1253 info->bssid[i]);
1254
1a9937b7
HRK		 1255 if (priv->is_rtl8187b)
1256 reg = RTL818X_MSR_ENEDCA;
1257 else
1258 reg = 0;
1259
41b58f18
AF		 1260 if (is_valid_ether_addr(info->bssid)) {
1261 if (vif->type == NL80211_IFTYPE_ADHOC)
1262 reg |= RTL818X_MSR_ADHOC;
1263 else
1264 reg |= RTL818X_MSR_INFRA;
1265 }
31a5cdda 1266 else
1a9937b7 1267 reg |= RTL818X_MSR_NO_LINK;
31a5cdda
JL		 1268
1269 rtl818x_iowrite8(priv, &priv->map->MSR, reg);
2d0ddec5
JB		 1270
1271 mutex_unlock(&priv->conf_mutex);
1272 }
64761077 1273
f8288317
HRK		 1274 if (changed & (BSS_CHANGED_ERP_SLOT | BSS_CHANGED_ERP_PREAMBLE))
1275 rtl8187_conf_erp(priv, info->use_short_slot,
1276 info->use_short_preamble);
41b58f18
AF		 1277
1278 if (changed & BSS_CHANGED_BEACON_ENABLED)
1279 vif_priv->enable_beacon = info->enable_beacon;
1280
1281 if (changed & (BSS_CHANGED_BEACON_ENABLED | BSS_CHANGED_BEACON)) {
1282 cancel_delayed_work_sync(&vif_priv->beacon_work);
1283 if (vif_priv->enable_beacon)
1284 schedule_work(&vif_priv->beacon_work.work);
1285 }
1286
64761077
HRK		 1287}
1288
3ac64bee 1289static u64 rtl8187_prepare_multicast(struct ieee80211_hw *dev,
22bedad3 1290 struct netdev_hw_addr_list *mc_list)
3ac64bee 1291{
22bedad3 1292 return netdev_hw_addr_list_count(mc_list);
3ac64bee
JB		 1293}
1294
4150c572
JB		 1295static void rtl8187_configure_filter(struct ieee80211_hw *dev,
1296 unsigned int changed_flags,
1297 unsigned int *total_flags,
3ac64bee 1298 u64 multicast)
4150c572
JB		 1299{
1300 struct rtl8187_priv *priv = dev->priv;
1301
4150c572
JB		 1302 if (changed_flags & FIF_FCSFAIL)
1303 priv->rx_conf ^= RTL818X_RX_CONF_FCS;
1304 if (changed_flags & FIF_CONTROL)
1305 priv->rx_conf ^= RTL818X_RX_CONF_CTRL;
1306 if (changed_flags & FIF_OTHER_BSS)
1307 priv->rx_conf ^= RTL818X_RX_CONF_MONITOR;
3ac64bee 1308 if (*total_flags & FIF_ALLMULTI || multicast > 0)
4150c572 1309 priv->rx_conf |= RTL818X_RX_CONF_MULTICAST;
2fe14263
MW		 1310 else
1311 priv->rx_conf &= ~RTL818X_RX_CONF_MULTICAST;
1312
1313 *total_flags = 0;
4150c572 1314
4150c572
JB		 1315 if (priv->rx_conf & RTL818X_RX_CONF_FCS)
1316 *total_flags |= FIF_FCSFAIL;
1317 if (priv->rx_conf & RTL818X_RX_CONF_CTRL)
1318 *total_flags |= FIF_CONTROL;
1319 if (priv->rx_conf & RTL818X_RX_CONF_MONITOR)
1320 *total_flags |= FIF_OTHER_BSS;
2fe14263
MW		 1321 if (priv->rx_conf & RTL818X_RX_CONF_MULTICAST)
1322 *total_flags |= FIF_ALLMULTI;
4150c572
JB		 1323
1324 rtl818x_iowrite32_async(priv, &priv->map->RX_CONF, priv->rx_conf);
1325}
1326
8a3a3c85
EP		 1327static int rtl8187_conf_tx(struct ieee80211_hw *dev,
1328 struct ieee80211_vif *vif, u16 queue,
b4572a92
HRK		 1329 const struct ieee80211_tx_queue_params *params)
1330{
1331 struct rtl8187_priv *priv = dev->priv;
1332 u8 cw_min, cw_max;
1333
1334 if (queue > 3)
1335 return -EINVAL;
1336
1337 cw_min = fls(params->cw_min);
1338 cw_max = fls(params->cw_max);
1339
1340 if (priv->is_rtl8187b) {
1341 priv->aifsn[queue] = params->aifs;
1342
1343 /*
1344 * This is the structure of AC_*_PARAM registers in 8187B:
1345 * - TXOP limit field, bit offset = 16
1346 * - ECWmax, bit offset = 12
1347 * - ECWmin, bit offset = 8
1348 * - AIFS, bit offset = 0
1349 */
1350 rtl818x_iowrite32(priv, rtl8187b_ac_addr[queue],
1351 (params->txop << 16) | (cw_max << 12) |
1352 (cw_min << 8) | (params->aifs *
1353 priv->slot_time + SIFS_TIME));
1354 } else {
1355 if (queue != 0)
1356 return -EINVAL;
1357
1358 rtl818x_iowrite8(priv, &priv->map->CW_VAL,
1359 cw_min | (cw_max << 4));
1360 }
1361 return 0;
1362}
1363
22e16e55 1364
605bebe2
MW		 1365static const struct ieee80211_ops rtl8187_ops = {
1366 .tx = rtl8187_tx,
4150c572 1367 .start = rtl8187_start,
605bebe2
MW		 1368 .stop = rtl8187_stop,
1369 .add_interface = rtl8187_add_interface,
1370 .remove_interface = rtl8187_remove_interface,
1371 .config = rtl8187_config,
64761077 1372 .bss_info_changed = rtl8187_bss_info_changed,
3ac64bee 1373 .prepare_multicast = rtl8187_prepare_multicast,
4150c572 1374 .configure_filter = rtl8187_configure_filter,
ca9152e3 1375 .conf_tx = rtl8187_conf_tx,
22e16e55
LF		 1376 .rfkill_poll = rtl8187_rfkill_poll,
1377 .get_tsf = rtl8187_get_tsf,
605bebe2
MW		 1378};
1379
1380static void rtl8187_eeprom_register_read(struct eeprom_93cx6 *eeprom)
1381{
1382 struct ieee80211_hw *dev = eeprom->data;
1383 struct rtl8187_priv *priv = dev->priv;
1384 u8 reg = rtl818x_ioread8(priv, &priv->map->EEPROM_CMD);
1385
1386 eeprom->reg_data_in = reg & RTL818X_EEPROM_CMD_WRITE;
1387 eeprom->reg_data_out = reg & RTL818X_EEPROM_CMD_READ;
1388 eeprom->reg_data_clock = reg & RTL818X_EEPROM_CMD_CK;
1389 eeprom->reg_chip_select = reg & RTL818X_EEPROM_CMD_CS;
1390}
1391
1392static void rtl8187_eeprom_register_write(struct eeprom_93cx6 *eeprom)
1393{
1394 struct ieee80211_hw *dev = eeprom->data;
1395 struct rtl8187_priv *priv = dev->priv;
1396 u8 reg = RTL818X_EEPROM_CMD_PROGRAM;
1397
1398 if (eeprom->reg_data_in)
1399 reg |= RTL818X_EEPROM_CMD_WRITE;
1400 if (eeprom->reg_data_out)
1401 reg |= RTL818X_EEPROM_CMD_READ;
1402 if (eeprom->reg_data_clock)
1403 reg |= RTL818X_EEPROM_CMD_CK;
1404 if (eeprom->reg_chip_select)
1405 reg |= RTL818X_EEPROM_CMD_CS;
1406
1407 rtl818x_iowrite8(priv, &priv->map->EEPROM_CMD, reg);
1408 udelay(10);
1409}
1410
1411static int __devinit rtl8187_probe(struct usb_interface *intf,
1412 const struct usb_device_id *id)
1413{
1414 struct usb_device *udev = interface_to_usbdev(intf);
1415 struct ieee80211_hw *dev;
1416 struct rtl8187_priv *priv;
1417 struct eeprom_93cx6 eeprom;
1418 struct ieee80211_channel *channel;
6f7853f3 1419 const char *chip_name;
605bebe2 1420 u16 txpwr, reg;
70d57139 1421 u16 product_id = le16_to_cpu(udev->descriptor.idProduct);
605bebe2 1422 int err, i;
f2c98382 1423 u8 mac_addr[ETH_ALEN];
605bebe2
MW		 1424
1425 dev = ieee80211_alloc_hw(sizeof(*priv), &rtl8187_ops);
1426 if (!dev) {
1427 printk(KERN_ERR "rtl8187: ieee80211 alloc failed\n");
1428 return -ENOMEM;
1429 }
1430
1431 priv = dev->priv;
0e25b4ef 1432 priv->is_rtl8187b = (id->driver_info == DEVICE_RTL8187B);
605bebe2 1433
9be6f0d4
JL		 1434 /* allocate "DMA aware" buffer for register accesses */
1435 priv->io_dmabuf = kmalloc(sizeof(*priv->io_dmabuf), GFP_KERNEL);
1436 if (!priv->io_dmabuf) {
1437 err = -ENOMEM;
1438 goto err_free_dev;
1439 }
1440 mutex_init(&priv->io_mutex);
1441
605bebe2
MW		 1442 SET_IEEE80211_DEV(dev, &intf->dev);
1443 usb_set_intfdata(intf, dev);
1444 priv->udev = udev;
1445
1446 usb_get_dev(udev);
1447
1448 skb_queue_head_init(&priv->rx_queue);
8318d78a
JB		 1449
1450 BUILD_BUG_ON(sizeof(priv->channels) != sizeof(rtl818x_channels));
1451 BUILD_BUG_ON(sizeof(priv->rates) != sizeof(rtl818x_rates));
1452
605bebe2
MW		 1453 memcpy(priv->channels, rtl818x_channels, sizeof(rtl818x_channels));
1454 memcpy(priv->rates, rtl818x_rates, sizeof(rtl818x_rates));
1455 priv->map = (struct rtl818x_csr *)0xFF00;
8318d78a
JB		 1456
1457 priv->band.band = IEEE80211_BAND_2GHZ;
1458 priv->band.channels = priv->channels;
1459 priv->band.n_channels = ARRAY_SIZE(rtl818x_channels);
1460 priv->band.bitrates = priv->rates;
1461 priv->band.n_bitrates = ARRAY_SIZE(rtl818x_rates);
1462 dev->wiphy->bands[IEEE80211_BAND_2GHZ] = &priv->band;
1463
1464
605bebe2 1465 dev->flags = IEEE80211_HW_HOST_BROADCAST_PS_BUFFERING |
a7db74f4 1466 IEEE80211_HW_SIGNAL_DBM |
0ccd58fc 1467 IEEE80211_HW_RX_INCLUDES_FCS;
6410db59
LF		 1468 /* Initialize rate-control variables */
1469 dev->max_rates = 1;
1470 dev->max_rate_tries = RETRY_COUNT;
605bebe2 1471
605bebe2
MW		 1472 eeprom.data = dev;
1473 eeprom.register_read = rtl8187_eeprom_register_read;
1474 eeprom.register_write = rtl8187_eeprom_register_write;
1475 if (rtl818x_ioread32(priv, &priv->map->RX_CONF) & (1 << 6))
1476 eeprom.width = PCI_EEPROM_WIDTH_93C66;
1477 else
1478 eeprom.width = PCI_EEPROM_WIDTH_93C46;
1479
1480 rtl818x_iowrite8(priv, &priv->map->EEPROM_CMD, RTL818X_EEPROM_CMD_CONFIG);
1481 udelay(10);
1482
1483 eeprom_93cx6_multiread(&eeprom, RTL8187_EEPROM_MAC_ADDR,
f2c98382
JL		 1484 (__le16 __force *)mac_addr, 3);
1485 if (!is_valid_ether_addr(mac_addr)) {
605bebe2
MW		 1486 printk(KERN_WARNING "rtl8187: Invalid hwaddr! Using randomly "
1487 "generated MAC address\n");
f2c98382 1488 random_ether_addr(mac_addr);
605bebe2 1489 }
f2c98382 1490 SET_IEEE80211_PERM_ADDR(dev, mac_addr);
605bebe2
MW		 1491
1492 channel = priv->channels;
1493 for (i = 0; i < 3; i++) {
1494 eeprom_93cx6_read(&eeprom, RTL8187_EEPROM_TXPWR_CHAN_1 + i,
1495 &txpwr);
8318d78a
JB		 1496 (*channel++).hw_value = txpwr & 0xFF;
1497 (*channel++).hw_value = txpwr >> 8;
605bebe2
MW		 1498 }
1499 for (i = 0; i < 2; i++) {
1500 eeprom_93cx6_read(&eeprom, RTL8187_EEPROM_TXPWR_CHAN_4 + i,
1501 &txpwr);
8318d78a
JB		 1502 (*channel++).hw_value = txpwr & 0xFF;
1503 (*channel++).hw_value = txpwr >> 8;
605bebe2 1504 }
605bebe2
MW		 1505
1506 eeprom_93cx6_read(&eeprom, RTL8187_EEPROM_TXPWR_BASE,
1507 &priv->txpwr_base);
1508
f6532111
MW		 1509 reg = rtl818x_ioread8(priv, &priv->map->PGSELECT) & ~1;
1510 rtl818x_iowrite8(priv, &priv->map->PGSELECT, reg | 1);
605bebe2
MW		 1511 /* 0 means asic B-cut, we should use SW 3 wire
1512 * bit-by-bit banging for radio. 1 means we can use
1513 * USB specific request to write radio registers */
1514 priv->asic_rev = rtl818x_ioread8(priv, (u8 *)0xFFFE) & 0x3;
f6532111 1515 rtl818x_iowrite8(priv, &priv->map->PGSELECT, reg);
605bebe2
MW		 1516 rtl818x_iowrite8(priv, &priv->map->EEPROM_CMD, RTL818X_EEPROM_CMD_NORMAL);
1517
6f7853f3
HTL		 1518 if (!priv->is_rtl8187b) {
1519 u32 reg32;
1520 reg32 = rtl818x_ioread32(priv, &priv->map->TX_CONF);
1521 reg32 &= RTL818X_TX_CONF_HWVER_MASK;
1522 switch (reg32) {
0e25b4ef
LF		 1523 case RTL818X_TX_CONF_R8187vD_B:
1524 /* Some RTL8187B devices have a USB ID of 0x8187
1525 * detect them here */
1526 chip_name = "RTL8187BvB(early)";
1527 priv->is_rtl8187b = 1;
1528 priv->hw_rev = RTL8187BvB;
1529 break;
1530 case RTL818X_TX_CONF_R8187vD:
6f7853f3
HTL		 1531 chip_name = "RTL8187vD";
1532 break;
1533 default:
1534 chip_name = "RTL8187vB (default)";
1535 }
1536 } else {
6f7853f3
HTL		 1537 /*
1538 * Force USB request to write radio registers for 8187B, Realtek
1539 * only uses it in their sources
1540 */
1541 /*if (priv->asic_rev == 0) {
1542 printk(KERN_WARNING "rtl8187: Forcing use of USB "
1543 "requests to write to radio registers\n");
1544 priv->asic_rev = 1;
1545 }*/
1546 switch (rtl818x_ioread8(priv, (u8 *)0xFFE1)) {
1547 case RTL818X_R8187B_B:
1548 chip_name = "RTL8187BvB";
1549 priv->hw_rev = RTL8187BvB;
1550 break;
1551 case RTL818X_R8187B_D:
1552 chip_name = "RTL8187BvD";
1553 priv->hw_rev = RTL8187BvD;
1554 break;
1555 case RTL818X_R8187B_E:
1556 chip_name = "RTL8187BvE";
1557 priv->hw_rev = RTL8187BvE;
1558 break;
1559 default:
1560 chip_name = "RTL8187BvB (default)";
1561 priv->hw_rev = RTL8187BvB;
1562 }
1563 }
1564
0e25b4ef
LF		 1565 if (!priv->is_rtl8187b) {
1566 for (i = 0; i < 2; i++) {
1567 eeprom_93cx6_read(&eeprom,
1568 RTL8187_EEPROM_TXPWR_CHAN_6 + i,
1569 &txpwr);
1570 (*channel++).hw_value = txpwr & 0xFF;
1571 (*channel++).hw_value = txpwr >> 8;
1572 }
1573 } else {
1574 eeprom_93cx6_read(&eeprom, RTL8187_EEPROM_TXPWR_CHAN_6,
1575 &txpwr);
1576 (*channel++).hw_value = txpwr & 0xFF;
1577
1578 eeprom_93cx6_read(&eeprom, 0x0A, &txpwr);
1579 (*channel++).hw_value = txpwr & 0xFF;
1580
1581 eeprom_93cx6_read(&eeprom, 0x1C, &txpwr);
1582 (*channel++).hw_value = txpwr & 0xFF;
1583 (*channel++).hw_value = txpwr >> 8;
1584 }
70d57139
LF		 1585 /* Handle the differing rfkill GPIO bit in different models */
1586 priv->rfkill_mask = RFKILL_MASK_8187_89_97;
1587 if (product_id == 0x8197 || product_id == 0x8198) {
1588 eeprom_93cx6_read(&eeprom, RTL8187_EEPROM_SELECT_GPIO, &reg);
1589 if (reg & 0xFF00)
1590 priv->rfkill_mask = RFKILL_MASK_8198;
1591 }
41b58f18
AF		 1592 dev->vif_data_size = sizeof(struct rtl8187_vif);
1593 dev->wiphy->interface_modes = BIT(NL80211_IFTYPE_STATION) |
1594 BIT(NL80211_IFTYPE_ADHOC) ;
f59ac048 1595
0e25b4ef
LF		 1596 if ((id->driver_info == DEVICE_RTL8187) && priv->is_rtl8187b)
1597 printk(KERN_INFO "rtl8187: inconsistency between id with OEM"
1598 " info!\n");
1599
f6532111 1600 priv->rf = rtl8187_detect_rf(dev);
0e25b4ef
LF		 1601 dev->extra_tx_headroom = (!priv->is_rtl8187b) ?
1602 sizeof(struct rtl8187_tx_hdr) :
1603 sizeof(struct rtl8187b_tx_hdr);
1604 if (!priv->is_rtl8187b)
1605 dev->queues = 1;
1606 else
1607 dev->queues = 4;
605bebe2
MW		 1608
1609 err = ieee80211_register_hw(dev);
1610 if (err) {
1611 printk(KERN_ERR "rtl8187: Cannot register device\n");
9be6f0d4 1612 goto err_free_dmabuf;
605bebe2 1613 }
7dcdd073 1614 mutex_init(&priv->conf_mutex);
3517afde 1615 skb_queue_head_init(&priv->b_tx_status.queue);
605bebe2 1616
5db55844 1617 wiphy_info(dev->wiphy, "hwaddr %pM, %s V%d + %s, rfkill mask %d\n",
c96c31e4
JP		 1618 mac_addr, chip_name, priv->asic_rev, priv->rf->name,
1619 priv->rfkill_mask);
605bebe2 1620
a027087a
LF		 1621#ifdef CONFIG_RTL8187_LEDS
1622 eeprom_93cx6_read(&eeprom, 0x3F, &reg);
1623 reg &= 0xFF;
1624 rtl8187_leds_init(dev, reg);
1625#endif
ca9152e3 1626 rtl8187_rfkill_init(dev);
a027087a 1627
605bebe2
MW		 1628 return 0;
1629
9be6f0d4
JL		 1630 err_free_dmabuf:
1631 kfree(priv->io_dmabuf);
605bebe2
MW		 1632 err_free_dev:
1633 ieee80211_free_hw(dev);
1634 usb_set_intfdata(intf, NULL);
1635 usb_put_dev(udev);
1636 return err;
1637}
1638
1639static void __devexit rtl8187_disconnect(struct usb_interface *intf)
1640{
1641 struct ieee80211_hw *dev = usb_get_intfdata(intf);
1642 struct rtl8187_priv *priv;
1643
1644 if (!dev)
1645 return;
1646
a027087a
LF		 1647#ifdef CONFIG_RTL8187_LEDS
1648 rtl8187_leds_exit(dev);
1649#endif
ca9152e3 1650 rtl8187_rfkill_exit(dev);
605bebe2
MW		 1651 ieee80211_unregister_hw(dev);
1652
1653 priv = dev->priv;
d6e2be98 1654 usb_reset_device(priv->udev);
605bebe2 1655 usb_put_dev(interface_to_usbdev(intf));
9be6f0d4 1656 kfree(priv->io_dmabuf);
605bebe2
MW		 1657 ieee80211_free_hw(dev);
1658}
1659
1660static struct usb_driver rtl8187_driver = {
1661 .name = KBUILD_MODNAME,
1662 .id_table = rtl8187_table,
1663 .probe = rtl8187_probe,
500c1197 1664 .disconnect = __devexit_p(rtl8187_disconnect),
605bebe2
MW		 1665};
1666
d632eb1b 1667module_usb_driver(rtl8187_driver);
Linux kernel - Deliverables
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