projects / deliverable / linux.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
rt2x00: remove skb->do_not_encrypt usage
[deliverable/linux.git] / drivers / net / wireless / rtl818x / rtl8187_dev.c
CommitLineData
605bebe2
MW		 1/*
2 * Linux device driver for RTL8187
3 *
4 * Copyright 2007 Michael Wu <flamingice@sourmilk.net>
5 * Copyright 2007 Andrea Merello <andreamrl@tiscali.it>
6 *
7 * Based on the r8187 driver, which is:
8 * Copyright 2005 Andrea Merello <andreamrl@tiscali.it>, et al.
9 *
3461fc12
LF		 10 * The driver was extended to the RTL8187B in 2008 by:
11 * Herton Ronaldo Krzesinski <herton@mandriva.com.br>
12 * Hin-Tak Leung <htl10@users.sourceforge.net>
13 * Larry Finger <Larry.Finger@lwfinger.net>
14 *
0aec00ae
JL		 15 * Magic delays and register offsets below are taken from the original
16 * r8187 driver sources. Thanks to Realtek for their support!
605bebe2
MW		 17 *
18 * This program is free software; you can redistribute it and/or modify
19 * it under the terms of the GNU General Public License version 2 as
20 * published by the Free Software Foundation.
21 */
22
23#include <linux/init.h>
24#include <linux/usb.h>
25#include <linux/delay.h>
26#include <linux/etherdevice.h>
27#include <linux/eeprom_93cx6.h>
28#include <net/mac80211.h>
29
30#include "rtl8187.h"
31#include "rtl8187_rtl8225.h"
a027087a
LF		 32#ifdef CONFIG_RTL8187_LEDS
33#include "rtl8187_leds.h"
34#endif
605bebe2
MW		 35
36MODULE_AUTHOR("Michael Wu <flamingice@sourmilk.net>");
37MODULE_AUTHOR("Andrea Merello <andreamrl@tiscali.it>");
3461fc12
LF		 38MODULE_AUTHOR("Herton Ronaldo Krzesinski <herton@mandriva.com.br>");
39MODULE_AUTHOR("Hin-Tak Leung <htl10@users.sourceforge.net>");
40MODULE_AUTHOR("Larry Finger <Larry.Finger@lwfinger.net>");
f8a08c34 41MODULE_DESCRIPTION("RTL8187/RTL8187B USB wireless driver");
605bebe2
MW		 42MODULE_LICENSE("GPL");
43
44static struct usb_device_id rtl8187_table[] __devinitdata = {
7c7e6af3
AM		 45 /* Asus */
46 {USB_DEVICE(0x0b05, 0x171d), .driver_info = DEVICE_RTL8187},
eaca90da
FF		 47 /* Belkin */
48 {USB_DEVICE(0x050d, 0x705e), .driver_info = DEVICE_RTL8187B},
605bebe2 49 /* Realtek */
f8a08c34
HTL		 50 {USB_DEVICE(0x0bda, 0x8187), .driver_info = DEVICE_RTL8187},
51 {USB_DEVICE(0x0bda, 0x8189), .driver_info = DEVICE_RTL8187B},
52 {USB_DEVICE(0x0bda, 0x8197), .driver_info = DEVICE_RTL8187B},
746db510 53 {USB_DEVICE(0x0bda, 0x8198), .driver_info = DEVICE_RTL8187B},
046ee5d2
LF		 54 /* Surecom */
55 {USB_DEVICE(0x0769, 0x11F2), .driver_info = DEVICE_RTL8187},
56 /* Logitech */
57 {USB_DEVICE(0x0789, 0x010C), .driver_info = DEVICE_RTL8187},
605bebe2 58 /* Netgear */
f8a08c34
HTL		 59 {USB_DEVICE(0x0846, 0x6100), .driver_info = DEVICE_RTL8187},
60 {USB_DEVICE(0x0846, 0x6a00), .driver_info = DEVICE_RTL8187},
fcd7cc14 61 {USB_DEVICE(0x0846, 0x4260), .driver_info = DEVICE_RTL8187B},
c3cf60a9 62 /* HP */
f8a08c34 63 {USB_DEVICE(0x03f0, 0xca02), .driver_info = DEVICE_RTL8187},
9934550d 64 /* Sitecom */
f8a08c34 65 {USB_DEVICE(0x0df6, 0x000d), .driver_info = DEVICE_RTL8187},
f3c76918 66 {USB_DEVICE(0x0df6, 0x0028), .driver_info = DEVICE_RTL8187B},
046ee5d2
LF		 67 /* Sphairon Access Systems GmbH */
68 {USB_DEVICE(0x114B, 0x0150), .driver_info = DEVICE_RTL8187},
69 /* Dick Smith Electronics */
70 {USB_DEVICE(0x1371, 0x9401), .driver_info = DEVICE_RTL8187},
8f7c41d4
IK		 71 /* Abocom */
72 {USB_DEVICE(0x13d1, 0xabe6), .driver_info = DEVICE_RTL8187},
046ee5d2
LF		 73 /* Qcom */
74 {USB_DEVICE(0x18E8, 0x6232), .driver_info = DEVICE_RTL8187},
75 /* AirLive */
76 {USB_DEVICE(0x1b75, 0x8187), .driver_info = DEVICE_RTL8187},
aeeab4ff
JL		 77 /* Linksys */
78 {USB_DEVICE(0x1737, 0x0073), .driver_info = DEVICE_RTL8187B},
605bebe2
MW		 79 {}
80};
81
82MODULE_DEVICE_TABLE(usb, rtl8187_table);
83
8318d78a
JB		 84static const struct ieee80211_rate rtl818x_rates[] = {
85 { .bitrate = 10, .hw_value = 0, },
86 { .bitrate = 20, .hw_value = 1, },
87 { .bitrate = 55, .hw_value = 2, },
88 { .bitrate = 110, .hw_value = 3, },
89 { .bitrate = 60, .hw_value = 4, },
90 { .bitrate = 90, .hw_value = 5, },
91 { .bitrate = 120, .hw_value = 6, },
92 { .bitrate = 180, .hw_value = 7, },
93 { .bitrate = 240, .hw_value = 8, },
94 { .bitrate = 360, .hw_value = 9, },
95 { .bitrate = 480, .hw_value = 10, },
96 { .bitrate = 540, .hw_value = 11, },
97};
98
99static const struct ieee80211_channel rtl818x_channels[] = {
100 { .center_freq = 2412 },
101 { .center_freq = 2417 },
102 { .center_freq = 2422 },
103 { .center_freq = 2427 },
104 { .center_freq = 2432 },
105 { .center_freq = 2437 },
106 { .center_freq = 2442 },
107 { .center_freq = 2447 },
108 { .center_freq = 2452 },
109 { .center_freq = 2457 },
110 { .center_freq = 2462 },
111 { .center_freq = 2467 },
112 { .center_freq = 2472 },
113 { .center_freq = 2484 },
114};
115
4150c572
JB		 116static void rtl8187_iowrite_async_cb(struct urb *urb)
117{
118 kfree(urb->context);
4150c572
JB		 119}
120
121static void rtl8187_iowrite_async(struct rtl8187_priv *priv, __le16 addr,
122 void *data, u16 len)
123{
124 struct usb_ctrlrequest *dr;
125 struct urb *urb;
126 struct rtl8187_async_write_data {
127 u8 data[4];
128 struct usb_ctrlrequest dr;
129 } *buf;
ea8ee240 130 int rc;
4150c572
JB		 131
132 buf = kmalloc(sizeof(*buf), GFP_ATOMIC);
133 if (!buf)
134 return;
135
136 urb = usb_alloc_urb(0, GFP_ATOMIC);
137 if (!urb) {
138 kfree(buf);
139 return;
140 }
141
142 dr = &buf->dr;
143
144 dr->bRequestType = RTL8187_REQT_WRITE;
145 dr->bRequest = RTL8187_REQ_SET_REG;
146 dr->wValue = addr;
147 dr->wIndex = 0;
148 dr->wLength = cpu_to_le16(len);
149
150 memcpy(buf, data, len);
151
152 usb_fill_control_urb(urb, priv->udev, usb_sndctrlpipe(priv->udev, 0),
153 (unsigned char *)dr, buf, len,
154 rtl8187_iowrite_async_cb, buf);
c1db52b9 155 usb_anchor_urb(urb, &priv->anchored);
ea8ee240
ON		 156 rc = usb_submit_urb(urb, GFP_ATOMIC);
157 if (rc < 0) {
158 kfree(buf);
c1db52b9 159 usb_unanchor_urb(urb);
ea8ee240 160 }
c1db52b9 161 usb_free_urb(urb);
4150c572
JB		 162}
163
164static inline void rtl818x_iowrite32_async(struct rtl8187_priv *priv,
165 __le32 *addr, u32 val)
166{
167 __le32 buf = cpu_to_le32(val);
168
169 rtl8187_iowrite_async(priv, cpu_to_le16((unsigned long)addr),
170 &buf, sizeof(buf));
171}
172
605bebe2
MW		 173void rtl8187_write_phy(struct ieee80211_hw *dev, u8 addr, u32 data)
174{
175 struct rtl8187_priv *priv = dev->priv;
176
177 data <<= 8;
178 data |= addr | 0x80;
179
180 rtl818x_iowrite8(priv, &priv->map->PHY[3], (data >> 24) & 0xFF);
181 rtl818x_iowrite8(priv, &priv->map->PHY[2], (data >> 16) & 0xFF);
182 rtl818x_iowrite8(priv, &priv->map->PHY[1], (data >> 8) & 0xFF);
183 rtl818x_iowrite8(priv, &priv->map->PHY[0], data & 0xFF);
605bebe2
MW		 184}
185
186static void rtl8187_tx_cb(struct urb *urb)
187{
605bebe2 188 struct sk_buff *skb = (struct sk_buff *)urb->context;
e039fa4a 189 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
e6a9854b 190 struct ieee80211_hw *hw = info->rate_driver_data[0];
6f7853f3 191 struct rtl8187_priv *priv = hw->priv;
605bebe2 192
6f7853f3
HTL		 193 skb_pull(skb, priv->is_rtl8187b ? sizeof(struct rtl8187b_tx_hdr) :
194 sizeof(struct rtl8187_tx_hdr));
e6a9854b 195 ieee80211_tx_info_clear_status(info);
3517afde 196
2f47690e
LF		 197 if (!(urb->status) && !(info->flags & IEEE80211_TX_CTL_NO_ACK)) {
198 if (priv->is_rtl8187b) {
199 skb_queue_tail(&priv->b_tx_status.queue, skb);
200
201 /* queue is "full", discard last items */
202 while (skb_queue_len(&priv->b_tx_status.queue) > 5) {
203 struct sk_buff *old_skb;
204
205 dev_dbg(&priv->udev->dev,
206 "transmit status queue full\n");
207
208 old_skb = skb_dequeue(&priv->b_tx_status.queue);
209 ieee80211_tx_status_irqsafe(hw, old_skb);
210 }
211 return;
212 } else {
3517afde 213 info->flags |= IEEE80211_TX_STAT_ACK;
2f47690e
LF		 214 }
215 }
216 if (priv->is_rtl8187b)
3517afde 217 ieee80211_tx_status_irqsafe(hw, skb);
2f47690e
LF		 218 else {
219 /* Retry information for the RTI8187 is only available by
220 * reading a register in the device. We are in interrupt mode
221 * here, thus queue the skb and finish on a work queue. */
222 skb_queue_tail(&priv->b_tx_status.queue, skb);
223 queue_delayed_work(hw->workqueue, &priv->work, 0);
3517afde 224 }
605bebe2
MW		 225}
226
e039fa4a 227static int rtl8187_tx(struct ieee80211_hw *dev, struct sk_buff *skb)
605bebe2
MW		 228{
229 struct rtl8187_priv *priv = dev->priv;
e039fa4a 230 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
6f7853f3
HTL		 231 unsigned int ep;
232 void *buf;
605bebe2 233 struct urb *urb;
98798f48
MW		 234 __le16 rts_dur = 0;
235 u32 flags;
ea8ee240 236 int rc;
605bebe2
MW		 237
238 urb = usb_alloc_urb(0, GFP_ATOMIC);
239 if (!urb) {
240 kfree_skb(skb);
d6e2be98 241 return NETDEV_TX_OK;
605bebe2
MW		 242 }
243
98798f48 244 flags = skb->len;
38e3b0d8 245 flags |= RTL818X_TX_DESC_FLAG_NO_ENC;
aa68cbfb 246
e039fa4a 247 flags |= ieee80211_get_tx_rate(dev, info)->hw_value << 24;
8b7b1e05 248 if (ieee80211_has_morefrags(((struct ieee80211_hdr *)skb->data)->frame_control))
38e3b0d8 249 flags |= RTL818X_TX_DESC_FLAG_MOREFRAG;
e6a9854b 250 if (info->control.rates[0].flags & IEEE80211_TX_RC_USE_RTS_CTS) {
38e3b0d8 251 flags |= RTL818X_TX_DESC_FLAG_RTS;
e039fa4a 252 flags |= ieee80211_get_rts_cts_rate(dev, info)->hw_value << 19;
32bfd35d 253 rts_dur = ieee80211_rts_duration(dev, priv->vif,
e039fa4a 254 skb->len, info);
e6a9854b 255 } else if (info->control.rates[0].flags & IEEE80211_TX_RC_USE_CTS_PROTECT) {
38e3b0d8 256 flags |= RTL818X_TX_DESC_FLAG_CTS;
e039fa4a 257 flags |= ieee80211_get_rts_cts_rate(dev, info)->hw_value << 19;
aa68cbfb 258 }
98798f48 259
6f7853f3
HTL		 260 if (!priv->is_rtl8187b) {
261 struct rtl8187_tx_hdr *hdr =
262 (struct rtl8187_tx_hdr *)skb_push(skb, sizeof(*hdr));
263 hdr->flags = cpu_to_le32(flags);
264 hdr->len = 0;
265 hdr->rts_duration = rts_dur;
d9a1f486 266 hdr->retry = cpu_to_le32((info->control.rates[0].count - 1) << 8);
6f7853f3
HTL		 267 buf = hdr;
268
269 ep = 2;
270 } else {
271 /* fc needs to be calculated before skb_push() */
272 unsigned int epmap[4] = { 6, 7, 5, 4 };
273 struct ieee80211_hdr *tx_hdr =
274 (struct ieee80211_hdr *)(skb->data);
275 u16 fc = le16_to_cpu(tx_hdr->frame_control);
276
277 struct rtl8187b_tx_hdr *hdr =
278 (struct rtl8187b_tx_hdr *)skb_push(skb, sizeof(*hdr));
279 struct ieee80211_rate *txrate =
280 ieee80211_get_tx_rate(dev, info);
281 memset(hdr, 0, sizeof(*hdr));
282 hdr->flags = cpu_to_le32(flags);
283 hdr->rts_duration = rts_dur;
d9a1f486 284 hdr->retry = cpu_to_le32((info->control.rates[0].count - 1) << 8);
6f7853f3
HTL		 285 hdr->tx_duration =
286 ieee80211_generic_frame_duration(dev, priv->vif,
287 skb->len, txrate);
288 buf = hdr;
289
290 if ((fc & IEEE80211_FCTL_FTYPE) == IEEE80211_FTYPE_MGMT)
291 ep = 12;
292 else
293 ep = epmap[skb_get_queue_mapping(skb)];
294 }
605bebe2 295
e6a9854b
JB		 296 info->rate_driver_data[0] = dev;
297 info->rate_driver_data[1] = urb;
6f7853f3
HTL		 298
299 usb_fill_bulk_urb(urb, priv->udev, usb_sndbulkpipe(priv->udev, ep),
300 buf, skb->len, rtl8187_tx_cb, skb);
2fcbab04 301 urb->transfer_flags |= URB_ZERO_PACKET;
c1db52b9 302 usb_anchor_urb(urb, &priv->anchored);
ea8ee240
ON		 303 rc = usb_submit_urb(urb, GFP_ATOMIC);
304 if (rc < 0) {
c1db52b9 305 usb_unanchor_urb(urb);
ea8ee240
ON		 306 kfree_skb(skb);
307 }
c1db52b9 308 usb_free_urb(urb);
605bebe2 309
d6e2be98 310 return NETDEV_TX_OK;
605bebe2
MW		 311}
312
313static void rtl8187_rx_cb(struct urb *urb)
314{
315 struct sk_buff *skb = (struct sk_buff *)urb->context;
316 struct rtl8187_rx_info *info = (struct rtl8187_rx_info *)skb->cb;
317 struct ieee80211_hw *dev = info->dev;
318 struct rtl8187_priv *priv = dev->priv;
605bebe2
MW		 319 struct ieee80211_rx_status rx_status = { 0 };
320 int rate, signal;
4150c572 321 u32 flags;
0ccd58fc 322 u32 quality;
d8588227 323 unsigned long f;
605bebe2 324
d8588227 325 spin_lock_irqsave(&priv->rx_queue.lock, f);
46c37672 326 __skb_unlink(skb, &priv->rx_queue);
d8588227 327 spin_unlock_irqrestore(&priv->rx_queue.lock, f);
c1db52b9 328 skb_put(skb, urb->actual_length);
605bebe2
MW		 329
330 if (unlikely(urb->status)) {
605bebe2
MW		 331 dev_kfree_skb_irq(skb);
332 return;
333 }
334
6f7853f3
HTL		 335 if (!priv->is_rtl8187b) {
336 struct rtl8187_rx_hdr *hdr =
337 (typeof(hdr))(skb_tail_pointer(skb) - sizeof(*hdr));
338 flags = le32_to_cpu(hdr->flags);
a7db74f4
LF		 339 /* As with the RTL8187B below, the AGC is used to calculate
340 * signal strength and quality. In this case, the scaling
341 * constants are derived from the output of p54usb.
342 */
343 quality = 130 - ((41 * hdr->agc) >> 6);
344 signal = -4 - ((27 * hdr->agc) >> 6);
6f7853f3 345 rx_status.antenna = (hdr->signal >> 7) & 1;
6f7853f3 346 rx_status.mactime = le64_to_cpu(hdr->mac_time);
6f7853f3
HTL		 347 } else {
348 struct rtl8187b_rx_hdr *hdr =
349 (typeof(hdr))(skb_tail_pointer(skb) - sizeof(*hdr));
0ccd58fc
LF		 350 /* The Realtek datasheet for the RTL8187B shows that the RX
351 * header contains the following quantities: signal quality,
352 * RSSI, AGC, the received power in dB, and the measured SNR.
353 * In testing, none of these quantities show qualitative
354 * agreement with AP signal strength, except for the AGC,
355 * which is inversely proportional to the strength of the
356 * signal. In the following, the quality and signal strength
357 * are derived from the AGC. The arbitrary scaling constants
358 * are chosen to make the results close to the values obtained
359 * for a BCM4312 using b43 as the driver. The noise is ignored
360 * for now.
361 */
6f7853f3 362 flags = le32_to_cpu(hdr->flags);
0ccd58fc 363 quality = 170 - hdr->agc;
0ccd58fc 364 signal = 14 - hdr->agc / 2;
0ccd58fc 365 rx_status.antenna = (hdr->rssi >> 7) & 1;
6f7853f3 366 rx_status.mactime = le64_to_cpu(hdr->mac_time);
6f7853f3 367 }
605bebe2 368
a7db74f4
LF		 369 if (quality > 100)
370 quality = 100;
371 rx_status.qual = quality;
372 priv->quality = quality;
373 rx_status.signal = signal;
374 priv->signal = signal;
375 rate = (flags >> 20) & 0xF;
6f7853f3 376 skb_trim(skb, flags & 0x0FFF);
8318d78a
JB		 377 rx_status.rate_idx = rate;
378 rx_status.freq = dev->conf.channel->center_freq;
379 rx_status.band = dev->conf.channel->band;
03bffc13 380 rx_status.flag |= RX_FLAG_TSFT;
38e3b0d8 381 if (flags & RTL818X_RX_DESC_FLAG_CRC32_ERR)
4150c572 382 rx_status.flag |= RX_FLAG_FAILED_FCS_CRC;
605bebe2
MW		 383 ieee80211_rx_irqsafe(dev, skb, &rx_status);
384
385 skb = dev_alloc_skb(RTL8187_MAX_RX);
386 if (unlikely(!skb)) {
605bebe2
MW		 387 /* TODO check rx queue length and refill *somewhere* */
388 return;
389 }
390
391 info = (struct rtl8187_rx_info *)skb->cb;
392 info->urb = urb;
393 info->dev = dev;
394 urb->transfer_buffer = skb_tail_pointer(skb);
395 urb->context = skb;
396 skb_queue_tail(&priv->rx_queue, skb);
397
c1db52b9
LF		 398 usb_anchor_urb(urb, &priv->anchored);
399 if (usb_submit_urb(urb, GFP_ATOMIC)) {
400 usb_unanchor_urb(urb);
401 skb_unlink(skb, &priv->rx_queue);
402 dev_kfree_skb_irq(skb);
403 }
605bebe2
MW		 404}
405
406static int rtl8187_init_urbs(struct ieee80211_hw *dev)
407{
408 struct rtl8187_priv *priv = dev->priv;
c1db52b9 409 struct urb *entry = NULL;
605bebe2
MW		 410 struct sk_buff *skb;
411 struct rtl8187_rx_info *info;
c1db52b9 412 int ret = 0;
605bebe2 413
2a57cf3e 414 while (skb_queue_len(&priv->rx_queue) < 16) {
605bebe2 415 skb = __dev_alloc_skb(RTL8187_MAX_RX, GFP_KERNEL);
c1db52b9
LF		 416 if (!skb) {
417 ret = -ENOMEM;
418 goto err;
419 }
605bebe2
MW		 420 entry = usb_alloc_urb(0, GFP_KERNEL);
421 if (!entry) {
c1db52b9
LF		 422 ret = -ENOMEM;
423 goto err;
605bebe2
MW		 424 }
425 usb_fill_bulk_urb(entry, priv->udev,
6f7853f3
HTL		 426 usb_rcvbulkpipe(priv->udev,
427 priv->is_rtl8187b ? 3 : 1),
605bebe2
MW		 428 skb_tail_pointer(skb),
429 RTL8187_MAX_RX, rtl8187_rx_cb, skb);
430 info = (struct rtl8187_rx_info *)skb->cb;
431 info->urb = entry;
432 info->dev = dev;
433 skb_queue_tail(&priv->rx_queue, skb);
c1db52b9
LF		 434 usb_anchor_urb(entry, &priv->anchored);
435 ret = usb_submit_urb(entry, GFP_KERNEL);
436 if (ret) {
437 skb_unlink(skb, &priv->rx_queue);
438 usb_unanchor_urb(entry);
439 goto err;
440 }
441 usb_free_urb(entry);
605bebe2 442 }
c1db52b9 443 return ret;
605bebe2 444
c1db52b9
LF		 445err:
446 usb_free_urb(entry);
447 kfree_skb(skb);
448 usb_kill_anchored_urbs(&priv->anchored);
449 return ret;
605bebe2
MW		 450}
451
3517afde
HRK		 452static void rtl8187b_status_cb(struct urb *urb)
453{
454 struct ieee80211_hw *hw = (struct ieee80211_hw *)urb->context;
455 struct rtl8187_priv *priv = hw->priv;
456 u64 val;
457 unsigned int cmd_type;
458
c1db52b9 459 if (unlikely(urb->status))
3517afde 460 return;
3517afde
HRK		 461
462 /*
463 * Read from status buffer:
464 *
465 * bits [30:31] = cmd type:
466 * - 0 indicates tx beacon interrupt
467 * - 1 indicates tx close descriptor
468 *
469 * In the case of tx beacon interrupt:
470 * [0:9] = Last Beacon CW
471 * [10:29] = reserved
472 * [30:31] = 00b
473 * [32:63] = Last Beacon TSF
474 *
475 * If it's tx close descriptor:
476 * [0:7] = Packet Retry Count
477 * [8:14] = RTS Retry Count
478 * [15] = TOK
479 * [16:27] = Sequence No
480 * [28] = LS
481 * [29] = FS
482 * [30:31] = 01b
483 * [32:47] = unused (reserved?)
484 * [48:63] = MAC Used Time
485 */
486 val = le64_to_cpu(priv->b_tx_status.buf);
487
488 cmd_type = (val >> 30) & 0x3;
489 if (cmd_type == 1) {
490 unsigned int pkt_rc, seq_no;
491 bool tok;
492 struct sk_buff *skb;
493 struct ieee80211_hdr *ieee80211hdr;
494 unsigned long flags;
495
496 pkt_rc = val & 0xFF;
497 tok = val & (1 << 15);
498 seq_no = (val >> 16) & 0xFFF;
499
500 spin_lock_irqsave(&priv->b_tx_status.queue.lock, flags);
501 skb_queue_reverse_walk(&priv->b_tx_status.queue, skb) {
502 ieee80211hdr = (struct ieee80211_hdr *)skb->data;
503
504 /*
505 * While testing, it was discovered that the seq_no
506 * doesn't actually contains the sequence number.
507 * Instead of returning just the 12 bits of sequence
508 * number, hardware is returning entire sequence control
509 * (fragment number plus sequence number) in a 12 bit
510 * only field overflowing after some time. As a
511 * workaround, just consider the lower bits, and expect
512 * it's unlikely we wrongly ack some sent data
513 */
514 if ((le16_to_cpu(ieee80211hdr->seq_ctrl)
515 & 0xFFF) == seq_no)
516 break;
517 }
518 if (skb != (struct sk_buff *) &priv->b_tx_status.queue) {
519 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
520
521 __skb_unlink(skb, &priv->b_tx_status.queue);
522 if (tok)
523 info->flags |= IEEE80211_TX_STAT_ACK;
1548c86a 524 info->status.rates[0].count = pkt_rc + 1;
3517afde
HRK		 525
526 ieee80211_tx_status_irqsafe(hw, skb);
527 }
528 spin_unlock_irqrestore(&priv->b_tx_status.queue.lock, flags);
529 }
530
c1db52b9
LF		 531 usb_anchor_urb(urb, &priv->anchored);
532 if (usb_submit_urb(urb, GFP_ATOMIC))
533 usb_unanchor_urb(urb);
3517afde
HRK		 534}
535
536static int rtl8187b_init_status_urb(struct ieee80211_hw *dev)
537{
538 struct rtl8187_priv *priv = dev->priv;
539 struct urb *entry;
c1db52b9 540 int ret = 0;
3517afde
HRK		 541
542 entry = usb_alloc_urb(0, GFP_KERNEL);
543 if (!entry)
544 return -ENOMEM;
3517afde
HRK		 545
546 usb_fill_bulk_urb(entry, priv->udev, usb_rcvbulkpipe(priv->udev, 9),
547 &priv->b_tx_status.buf, sizeof(priv->b_tx_status.buf),
548 rtl8187b_status_cb, dev);
549
c1db52b9
LF		 550 usb_anchor_urb(entry, &priv->anchored);
551 ret = usb_submit_urb(entry, GFP_KERNEL);
552 if (ret)
553 usb_unanchor_urb(entry);
554 usb_free_urb(entry);
3517afde 555
c1db52b9 556 return ret;
3517afde
HRK		 557}
558
f8a08c34 559static int rtl8187_cmd_reset(struct ieee80211_hw *dev)
605bebe2
MW		 560{
561 struct rtl8187_priv *priv = dev->priv;
562 u8 reg;
563 int i;
564
605bebe2
MW		 565 reg = rtl818x_ioread8(priv, &priv->map->CMD);
566 reg &= (1 << 1);
567 reg |= RTL818X_CMD_RESET;
568 rtl818x_iowrite8(priv, &priv->map->CMD, reg);
569
570 i = 10;
571 do {
572 msleep(2);
573 if (!(rtl818x_ioread8(priv, &priv->map->CMD) &
574 RTL818X_CMD_RESET))
575 break;
576 } while (--i);
577
578 if (!i) {
579 printk(KERN_ERR "%s: Reset timeout!\n", wiphy_name(dev->wiphy));
580 return -ETIMEDOUT;
581 }
582
583 /* reload registers from eeprom */
584 rtl818x_iowrite8(priv, &priv->map->EEPROM_CMD, RTL818X_EEPROM_CMD_LOAD);
585
586 i = 10;
587 do {
588 msleep(4);
589 if (!(rtl818x_ioread8(priv, &priv->map->EEPROM_CMD) &
590 RTL818X_EEPROM_CMD_CONFIG))
591 break;
592 } while (--i);
593
594 if (!i) {
595 printk(KERN_ERR "%s: eeprom reset timeout!\n",
596 wiphy_name(dev->wiphy));
597 return -ETIMEDOUT;
598 }
599
f8a08c34
HTL		 600 return 0;
601}
602
603static int rtl8187_init_hw(struct ieee80211_hw *dev)
604{
605 struct rtl8187_priv *priv = dev->priv;
606 u8 reg;
607 int res;
608
609 /* reset */
610 rtl818x_iowrite8(priv, &priv->map->EEPROM_CMD,
611 RTL818X_EEPROM_CMD_CONFIG);
612 reg = rtl818x_ioread8(priv, &priv->map->CONFIG3);
613 rtl818x_iowrite8(priv, &priv->map->CONFIG3, reg |
614 RTL818X_CONFIG3_ANAPARAM_WRITE);
4ece16a1
HRK		 615 rtl818x_iowrite32(priv, &priv->map->ANAPARAM,
616 RTL8187_RTL8225_ANAPARAM_ON);
617 rtl818x_iowrite32(priv, &priv->map->ANAPARAM2,
618 RTL8187_RTL8225_ANAPARAM2_ON);
f8a08c34
HTL		 619 rtl818x_iowrite8(priv, &priv->map->CONFIG3, reg &
620 ~RTL818X_CONFIG3_ANAPARAM_WRITE);
621 rtl818x_iowrite8(priv, &priv->map->EEPROM_CMD,
622 RTL818X_EEPROM_CMD_NORMAL);
623
624 rtl818x_iowrite16(priv, &priv->map->INT_MASK, 0);
625
626 msleep(200);
627 rtl818x_iowrite8(priv, (u8 *)0xFE18, 0x10);
628 rtl818x_iowrite8(priv, (u8 *)0xFE18, 0x11);
629 rtl818x_iowrite8(priv, (u8 *)0xFE18, 0x00);
630 msleep(200);
631
632 res = rtl8187_cmd_reset(dev);
633 if (res)
634 return res;
635
605bebe2
MW		 636 rtl818x_iowrite8(priv, &priv->map->EEPROM_CMD, RTL818X_EEPROM_CMD_CONFIG);
637 reg = rtl818x_ioread8(priv, &priv->map->CONFIG3);
f8a08c34
HTL		 638 rtl818x_iowrite8(priv, &priv->map->CONFIG3,
639 reg | RTL818X_CONFIG3_ANAPARAM_WRITE);
4ece16a1
HRK		 640 rtl818x_iowrite32(priv, &priv->map->ANAPARAM,
641 RTL8187_RTL8225_ANAPARAM_ON);
642 rtl818x_iowrite32(priv, &priv->map->ANAPARAM2,
643 RTL8187_RTL8225_ANAPARAM2_ON);
f8a08c34
HTL		 644 rtl818x_iowrite8(priv, &priv->map->CONFIG3,
645 reg & ~RTL818X_CONFIG3_ANAPARAM_WRITE);
605bebe2
MW		 646 rtl818x_iowrite8(priv, &priv->map->EEPROM_CMD, RTL818X_EEPROM_CMD_NORMAL);
647
648 /* setup card */
649 rtl818x_iowrite16(priv, &priv->map->RFPinsSelect, 0);
650 rtl818x_iowrite8(priv, &priv->map->GPIO, 0);
651
652 rtl818x_iowrite16(priv, &priv->map->RFPinsSelect, (4 << 8));
653 rtl818x_iowrite8(priv, &priv->map->GPIO, 1);
654 rtl818x_iowrite8(priv, &priv->map->GP_ENABLE, 0);
655
656 rtl818x_iowrite8(priv, &priv->map->EEPROM_CMD, RTL818X_EEPROM_CMD_CONFIG);
605bebe2
MW		 657
658 rtl818x_iowrite16(priv, (__le16 *)0xFFF4, 0xFFFF);
659 reg = rtl818x_ioread8(priv, &priv->map->CONFIG1);
660 reg &= 0x3F;
661 reg |= 0x80;
662 rtl818x_iowrite8(priv, &priv->map->CONFIG1, reg);
663
664 rtl818x_iowrite8(priv, &priv->map->EEPROM_CMD, RTL818X_EEPROM_CMD_NORMAL);
665
666 rtl818x_iowrite32(priv, &priv->map->INT_TIMEOUT, 0);
667 rtl818x_iowrite8(priv, &priv->map->WPA_CONF, 0);
2f47690e 668 rtl818x_iowrite8(priv, &priv->map->RATE_FALLBACK, 0);
605bebe2
MW		 669
670 // TODO: set RESP_RATE and BRSR properly
671 rtl818x_iowrite8(priv, &priv->map->RESP_RATE, (8 << 4) | 0);
672 rtl818x_iowrite16(priv, &priv->map->BRSR, 0x01F3);
673
674 /* host_usb_init */
675 rtl818x_iowrite16(priv, &priv->map->RFPinsSelect, 0);
676 rtl818x_iowrite8(priv, &priv->map->GPIO, 0);
677 reg = rtl818x_ioread8(priv, (u8 *)0xFE53);
678 rtl818x_iowrite8(priv, (u8 *)0xFE53, reg | (1 << 7));
679 rtl818x_iowrite16(priv, &priv->map->RFPinsSelect, (4 << 8));
680 rtl818x_iowrite8(priv, &priv->map->GPIO, 0x20);
681 rtl818x_iowrite8(priv, &priv->map->GP_ENABLE, 0);
682 rtl818x_iowrite16(priv, &priv->map->RFPinsOutput, 0x80);
683 rtl818x_iowrite16(priv, &priv->map->RFPinsSelect, 0x80);
684 rtl818x_iowrite16(priv, &priv->map->RFPinsEnable, 0x80);
685 msleep(100);
686
687 rtl818x_iowrite32(priv, &priv->map->RF_TIMING, 0x000a8008);
688 rtl818x_iowrite16(priv, &priv->map->BRSR, 0xFFFF);
689 rtl818x_iowrite32(priv, &priv->map->RF_PARA, 0x00100044);
f8a08c34
HTL		 690 rtl818x_iowrite8(priv, &priv->map->EEPROM_CMD,
691 RTL818X_EEPROM_CMD_CONFIG);
605bebe2 692 rtl818x_iowrite8(priv, &priv->map->CONFIG3, 0x44);
f8a08c34
HTL		 693 rtl818x_iowrite8(priv, &priv->map->EEPROM_CMD,
694 RTL818X_EEPROM_CMD_NORMAL);
605bebe2
MW		 695 rtl818x_iowrite16(priv, &priv->map->RFPinsEnable, 0x1FF7);
696 msleep(100);
697
f6532111 698 priv->rf->init(dev);
605bebe2
MW		 699
700 rtl818x_iowrite16(priv, &priv->map->BRSR, 0x01F3);
f6532111
MW		 701 reg = rtl818x_ioread8(priv, &priv->map->PGSELECT) & ~1;
702 rtl818x_iowrite8(priv, &priv->map->PGSELECT, reg | 1);
605bebe2
MW		 703 rtl818x_iowrite16(priv, (__le16 *)0xFFFE, 0x10);
704 rtl818x_iowrite8(priv, &priv->map->TALLY_SEL, 0x80);
705 rtl818x_iowrite8(priv, (u8 *)0xFFFF, 0x60);
f6532111 706 rtl818x_iowrite8(priv, &priv->map->PGSELECT, reg);
605bebe2
MW		 707
708 return 0;
709}
710
f8a08c34
HTL		 711static const u8 rtl8187b_reg_table[][3] = {
712 {0xF0, 0x32, 0}, {0xF1, 0x32, 0}, {0xF2, 0x00, 0}, {0xF3, 0x00, 0},
713 {0xF4, 0x32, 0}, {0xF5, 0x43, 0}, {0xF6, 0x00, 0}, {0xF7, 0x00, 0},
714 {0xF8, 0x46, 0}, {0xF9, 0xA4, 0}, {0xFA, 0x00, 0}, {0xFB, 0x00, 0},
715 {0xFC, 0x96, 0}, {0xFD, 0xA4, 0}, {0xFE, 0x00, 0}, {0xFF, 0x00, 0},
716
717 {0x58, 0x4B, 1}, {0x59, 0x00, 1}, {0x5A, 0x4B, 1}, {0x5B, 0x00, 1},
718 {0x60, 0x4B, 1}, {0x61, 0x09, 1}, {0x62, 0x4B, 1}, {0x63, 0x09, 1},
719 {0xCE, 0x0F, 1}, {0xCF, 0x00, 1}, {0xE0, 0xFF, 1}, {0xE1, 0x0F, 1},
720 {0xE2, 0x00, 1}, {0xF0, 0x4E, 1}, {0xF1, 0x01, 1}, {0xF2, 0x02, 1},
721 {0xF3, 0x03, 1}, {0xF4, 0x04, 1}, {0xF5, 0x05, 1}, {0xF6, 0x06, 1},
722 {0xF7, 0x07, 1}, {0xF8, 0x08, 1},
723
724 {0x4E, 0x00, 2}, {0x0C, 0x04, 2}, {0x21, 0x61, 2}, {0x22, 0x68, 2},
725 {0x23, 0x6F, 2}, {0x24, 0x76, 2}, {0x25, 0x7D, 2}, {0x26, 0x84, 2},
726 {0x27, 0x8D, 2}, {0x4D, 0x08, 2}, {0x50, 0x05, 2}, {0x51, 0xF5, 2},
727 {0x52, 0x04, 2}, {0x53, 0xA0, 2}, {0x54, 0x1F, 2}, {0x55, 0x23, 2},
728 {0x56, 0x45, 2}, {0x57, 0x67, 2}, {0x58, 0x08, 2}, {0x59, 0x08, 2},
729 {0x5A, 0x08, 2}, {0x5B, 0x08, 2}, {0x60, 0x08, 2}, {0x61, 0x08, 2},
730 {0x62, 0x08, 2}, {0x63, 0x08, 2}, {0x64, 0xCF, 2}, {0x72, 0x56, 2},
731 {0x73, 0x9A, 2},
732
733 {0x34, 0xF0, 0}, {0x35, 0x0F, 0}, {0x5B, 0x40, 0}, {0x84, 0x88, 0},
734 {0x85, 0x24, 0}, {0x88, 0x54, 0}, {0x8B, 0xB8, 0}, {0x8C, 0x07, 0},
735 {0x8D, 0x00, 0}, {0x94, 0x1B, 0}, {0x95, 0x12, 0}, {0x96, 0x00, 0},
736 {0x97, 0x06, 0}, {0x9D, 0x1A, 0}, {0x9F, 0x10, 0}, {0xB4, 0x22, 0},
a027087a 737 {0xBE, 0x80, 0}, {0xDB, 0x00, 0}, {0xEE, 0x00, 0}, {0x4C, 0x00, 2},
f8a08c34 738
a027087a
LF		 739 {0x9F, 0x00, 3}, {0x8C, 0x01, 0}, {0x8D, 0x10, 0}, {0x8E, 0x08, 0},
740 {0x8F, 0x00, 0}
f8a08c34
HTL		 741};
742
743static int rtl8187b_init_hw(struct ieee80211_hw *dev)
744{
745 struct rtl8187_priv *priv = dev->priv;
746 int res, i;
747 u8 reg;
748
749 rtl818x_iowrite8(priv, &priv->map->EEPROM_CMD,
750 RTL818X_EEPROM_CMD_CONFIG);
751
752 reg = rtl818x_ioread8(priv, &priv->map->CONFIG3);
753 reg |= RTL818X_CONFIG3_ANAPARAM_WRITE | RTL818X_CONFIG3_GNT_SELECT;
754 rtl818x_iowrite8(priv, &priv->map->CONFIG3, reg);
4ece16a1
HRK		 755 rtl818x_iowrite32(priv, &priv->map->ANAPARAM2,
756 RTL8187B_RTL8225_ANAPARAM2_ON);
757 rtl818x_iowrite32(priv, &priv->map->ANAPARAM,
758 RTL8187B_RTL8225_ANAPARAM_ON);
759 rtl818x_iowrite8(priv, &priv->map->ANAPARAM3,
760 RTL8187B_RTL8225_ANAPARAM3_ON);
f8a08c34
HTL		 761
762 rtl818x_iowrite8(priv, (u8 *)0xFF61, 0x10);
763 reg = rtl818x_ioread8(priv, (u8 *)0xFF62);
764 rtl818x_iowrite8(priv, (u8 *)0xFF62, reg & ~(1 << 5));
765 rtl818x_iowrite8(priv, (u8 *)0xFF62, reg | (1 << 5));
766
767 reg = rtl818x_ioread8(priv, &priv->map->CONFIG3);
768 reg &= ~RTL818X_CONFIG3_ANAPARAM_WRITE;
769 rtl818x_iowrite8(priv, &priv->map->CONFIG3, reg);
770
771 rtl818x_iowrite8(priv, &priv->map->EEPROM_CMD,
772 RTL818X_EEPROM_CMD_NORMAL);
773
774 res = rtl8187_cmd_reset(dev);
775 if (res)
776 return res;
777
778 rtl818x_iowrite16(priv, (__le16 *)0xFF2D, 0x0FFF);
779 reg = rtl818x_ioread8(priv, &priv->map->CW_CONF);
780 reg |= RTL818X_CW_CONF_PERPACKET_RETRY_SHIFT;
781 rtl818x_iowrite8(priv, &priv->map->CW_CONF, reg);
782 reg = rtl818x_ioread8(priv, &priv->map->TX_AGC_CTL);
783 reg |= RTL818X_TX_AGC_CTL_PERPACKET_GAIN_SHIFT |
784 RTL818X_TX_AGC_CTL_PERPACKET_ANTSEL_SHIFT;
785 rtl818x_iowrite8(priv, &priv->map->TX_AGC_CTL, reg);
786
787 rtl818x_iowrite16_idx(priv, (__le16 *)0xFFE0, 0x0FFF, 1);
f8a08c34
HTL		 788
789 rtl818x_iowrite16(priv, &priv->map->BEACON_INTERVAL, 100);
790 rtl818x_iowrite16(priv, &priv->map->ATIM_WND, 2);
791 rtl818x_iowrite16_idx(priv, (__le16 *)0xFFD4, 0xFFFF, 1);
792
793 rtl818x_iowrite8(priv, &priv->map->EEPROM_CMD,
794 RTL818X_EEPROM_CMD_CONFIG);
795 reg = rtl818x_ioread8(priv, &priv->map->CONFIG1);
796 rtl818x_iowrite8(priv, &priv->map->CONFIG1, (reg & 0x3F) | 0x80);
797 rtl818x_iowrite8(priv, &priv->map->EEPROM_CMD,
798 RTL818X_EEPROM_CMD_NORMAL);
799
800 rtl818x_iowrite8(priv, &priv->map->WPA_CONF, 0);
801 for (i = 0; i < ARRAY_SIZE(rtl8187b_reg_table); i++) {
802 rtl818x_iowrite8_idx(priv,
803 (u8 *)(uintptr_t)
804 (rtl8187b_reg_table[i][0] | 0xFF00),
805 rtl8187b_reg_table[i][1],
806 rtl8187b_reg_table[i][2]);
807 }
808
809 rtl818x_iowrite16(priv, &priv->map->TID_AC_MAP, 0xFA50);
810 rtl818x_iowrite16(priv, &priv->map->INT_MIG, 0);
811
812 rtl818x_iowrite32_idx(priv, (__le32 *)0xFFF0, 0, 1);
813 rtl818x_iowrite32_idx(priv, (__le32 *)0xFFF4, 0, 1);
814 rtl818x_iowrite8_idx(priv, (u8 *)0xFFF8, 0, 1);
815
816 rtl818x_iowrite32(priv, &priv->map->RF_TIMING, 0x00004001);
817
818 rtl818x_iowrite16_idx(priv, (__le16 *)0xFF72, 0x569A, 2);
819
820 rtl818x_iowrite8(priv, &priv->map->EEPROM_CMD,
821 RTL818X_EEPROM_CMD_CONFIG);
822 reg = rtl818x_ioread8(priv, &priv->map->CONFIG3);
823 reg |= RTL818X_CONFIG3_ANAPARAM_WRITE;
824 rtl818x_iowrite8(priv, &priv->map->CONFIG3, reg);
825 rtl818x_iowrite8(priv, &priv->map->EEPROM_CMD,
826 RTL818X_EEPROM_CMD_NORMAL);
827
828 rtl818x_iowrite16(priv, &priv->map->RFPinsOutput, 0x0480);
829 rtl818x_iowrite16(priv, &priv->map->RFPinsSelect, 0x2488);
830 rtl818x_iowrite16(priv, &priv->map->RFPinsEnable, 0x1FFF);
2f20596b 831 msleep(100);
f8a08c34
HTL		 832
833 priv->rf->init(dev);
834
835 reg = RTL818X_CMD_TX_ENABLE | RTL818X_CMD_RX_ENABLE;
836 rtl818x_iowrite8(priv, &priv->map->CMD, reg);
837 rtl818x_iowrite16(priv, &priv->map->INT_MASK, 0xFFFF);
838
839 rtl818x_iowrite8(priv, (u8 *)0xFE41, 0xF4);
840 rtl818x_iowrite8(priv, (u8 *)0xFE40, 0x00);
841 rtl818x_iowrite8(priv, (u8 *)0xFE42, 0x00);
842 rtl818x_iowrite8(priv, (u8 *)0xFE42, 0x01);
843 rtl818x_iowrite8(priv, (u8 *)0xFE40, 0x0F);
844 rtl818x_iowrite8(priv, (u8 *)0xFE42, 0x00);
845 rtl818x_iowrite8(priv, (u8 *)0xFE42, 0x01);
846
847 reg = rtl818x_ioread8(priv, (u8 *)0xFFDB);
848 rtl818x_iowrite8(priv, (u8 *)0xFFDB, reg | (1 << 2));
849 rtl818x_iowrite16_idx(priv, (__le16 *)0xFF72, 0x59FA, 3);
850 rtl818x_iowrite16_idx(priv, (__le16 *)0xFF74, 0x59D2, 3);
851 rtl818x_iowrite16_idx(priv, (__le16 *)0xFF76, 0x59D2, 3);
852 rtl818x_iowrite16_idx(priv, (__le16 *)0xFF78, 0x19FA, 3);
853 rtl818x_iowrite16_idx(priv, (__le16 *)0xFF7A, 0x19FA, 3);
854 rtl818x_iowrite16_idx(priv, (__le16 *)0xFF7C, 0x00D0, 3);
855 rtl818x_iowrite8(priv, (u8 *)0xFF61, 0);
856 rtl818x_iowrite8_idx(priv, (u8 *)0xFF80, 0x0F, 1);
857 rtl818x_iowrite8_idx(priv, (u8 *)0xFF83, 0x03, 1);
858 rtl818x_iowrite8(priv, (u8 *)0xFFDA, 0x10);
859 rtl818x_iowrite8_idx(priv, (u8 *)0xFF4D, 0x08, 2);
860
861 rtl818x_iowrite32(priv, &priv->map->HSSI_PARA, 0x0600321B);
862
863 rtl818x_iowrite16_idx(priv, (__le16 *)0xFFEC, 0x0800, 1);
864
b4572a92
HRK		 865 priv->slot_time = 0x9;
866 priv->aifsn[0] = 2; /* AIFSN[AC_VO] */
867 priv->aifsn[1] = 2; /* AIFSN[AC_VI] */
868 priv->aifsn[2] = 7; /* AIFSN[AC_BK] */
869 priv->aifsn[3] = 3; /* AIFSN[AC_BE] */
870 rtl818x_iowrite8(priv, &priv->map->ACM_CONTROL, 0);
871
f8a08c34
HTL		 872 return 0;
873}
874
2f47690e
LF		 875static void rtl8187_work(struct work_struct *work)
876{
877 /* The RTL8187 returns the retry count through register 0xFFFA. In
878 * addition, it appears to be a cumulative retry count, not the
879 * value for the current TX packet. When multiple TX entries are
880 * queued, the retry count will be valid for the last one in the queue.
881 * The "error" should not matter for purposes of rate setting. */
882 struct rtl8187_priv *priv = container_of(work, struct rtl8187_priv,
883 work.work);
884 struct ieee80211_tx_info *info;
885 struct ieee80211_hw *dev = priv->dev;
886 static u16 retry;
887 u16 tmp;
888
889 mutex_lock(&priv->conf_mutex);
890 tmp = rtl818x_ioread16(priv, (__le16 *)0xFFFA);
891 while (skb_queue_len(&priv->b_tx_status.queue) > 0) {
892 struct sk_buff *old_skb;
893
894 old_skb = skb_dequeue(&priv->b_tx_status.queue);
895 info = IEEE80211_SKB_CB(old_skb);
896 info->status.rates[0].count = tmp - retry + 1;
897 ieee80211_tx_status_irqsafe(dev, old_skb);
898 }
899 retry = tmp;
900 mutex_unlock(&priv->conf_mutex);
901}
902
4150c572 903static int rtl8187_start(struct ieee80211_hw *dev)
605bebe2
MW		 904{
905 struct rtl8187_priv *priv = dev->priv;
906 u32 reg;
907 int ret;
908
f8a08c34
HTL		 909 ret = (!priv->is_rtl8187b) ? rtl8187_init_hw(dev) :
910 rtl8187b_init_hw(dev);
605bebe2
MW		 911 if (ret)
912 return ret;
913
7dcdd073 914 mutex_lock(&priv->conf_mutex);
c1db52b9
LF		 915
916 init_usb_anchor(&priv->anchored);
2f47690e 917 priv->dev = dev;
c1db52b9 918
f8a08c34
HTL		 919 if (priv->is_rtl8187b) {
920 reg = RTL818X_RX_CONF_MGMT |
921 RTL818X_RX_CONF_DATA |
922 RTL818X_RX_CONF_BROADCAST |
923 RTL818X_RX_CONF_NICMAC |
924 RTL818X_RX_CONF_BSSID |
925 (7 << 13 /* RX FIFO threshold NONE */) |
926 (7 << 10 /* MAX RX DMA */) |
927 RTL818X_RX_CONF_RX_AUTORESETPHY |
928 RTL818X_RX_CONF_ONLYERLPKT |
929 RTL818X_RX_CONF_MULTICAST;
930 priv->rx_conf = reg;
931 rtl818x_iowrite32(priv, &priv->map->RX_CONF, reg);
932
933 rtl818x_iowrite32(priv, &priv->map->TX_CONF,
934 RTL818X_TX_CONF_HW_SEQNUM |
935 RTL818X_TX_CONF_DISREQQSIZE |
936 (7 << 8 /* short retry limit */) |
937 (7 << 0 /* long retry limit */) |
938 (7 << 21 /* MAX TX DMA */));
939 rtl8187_init_urbs(dev);
3517afde 940 rtl8187b_init_status_urb(dev);
7dcdd073 941 mutex_unlock(&priv->conf_mutex);
f8a08c34
HTL		 942 return 0;
943 }
944
605bebe2
MW		 945 rtl818x_iowrite16(priv, &priv->map->INT_MASK, 0xFFFF);
946
2fe14263
MW		 947 rtl818x_iowrite32(priv, &priv->map->MAR[0], ~0);
948 rtl818x_iowrite32(priv, &priv->map->MAR[1], ~0);
949
605bebe2
MW		 950 rtl8187_init_urbs(dev);
951
952 reg = RTL818X_RX_CONF_ONLYERLPKT |
953 RTL818X_RX_CONF_RX_AUTORESETPHY |
954 RTL818X_RX_CONF_BSSID |
955 RTL818X_RX_CONF_MGMT |
605bebe2
MW		 956 RTL818X_RX_CONF_DATA |
957 (7 << 13 /* RX FIFO threshold NONE */) |
958 (7 << 10 /* MAX RX DMA */) |
959 RTL818X_RX_CONF_BROADCAST |
605bebe2 960 RTL818X_RX_CONF_NICMAC;
605bebe2 961
4150c572 962 priv->rx_conf = reg;
605bebe2
MW		 963 rtl818x_iowrite32(priv, &priv->map->RX_CONF, reg);
964
965 reg = rtl818x_ioread8(priv, &priv->map->CW_CONF);
966 reg &= ~RTL818X_CW_CONF_PERPACKET_CW_SHIFT;
967 reg |= RTL818X_CW_CONF_PERPACKET_RETRY_SHIFT;
968 rtl818x_iowrite8(priv, &priv->map->CW_CONF, reg);
969
970 reg = rtl818x_ioread8(priv, &priv->map->TX_AGC_CTL);
971 reg &= ~RTL818X_TX_AGC_CTL_PERPACKET_GAIN_SHIFT;
972 reg &= ~RTL818X_TX_AGC_CTL_PERPACKET_ANTSEL_SHIFT;
973 reg &= ~RTL818X_TX_AGC_CTL_FEEDBACK_ANT;
974 rtl818x_iowrite8(priv, &priv->map->TX_AGC_CTL, reg);
975
976 reg = RTL818X_TX_CONF_CW_MIN |
977 (7 << 21 /* MAX TX DMA */) |
978 RTL818X_TX_CONF_NO_ICV;
979 rtl818x_iowrite32(priv, &priv->map->TX_CONF, reg);
980
981 reg = rtl818x_ioread8(priv, &priv->map->CMD);
982 reg |= RTL818X_CMD_TX_ENABLE;
983 reg |= RTL818X_CMD_RX_ENABLE;
984 rtl818x_iowrite8(priv, &priv->map->CMD, reg);
2f47690e 985 INIT_DELAYED_WORK(&priv->work, rtl8187_work);
7dcdd073 986 mutex_unlock(&priv->conf_mutex);
605bebe2
MW		 987
988 return 0;
989}
990
4150c572 991static void rtl8187_stop(struct ieee80211_hw *dev)
605bebe2
MW		 992{
993 struct rtl8187_priv *priv = dev->priv;
605bebe2
MW		 994 struct sk_buff *skb;
995 u32 reg;
996
7dcdd073 997 mutex_lock(&priv->conf_mutex);
605bebe2
MW		 998 rtl818x_iowrite16(priv, &priv->map->INT_MASK, 0);
999
1000 reg = rtl818x_ioread8(priv, &priv->map->CMD);
1001 reg &= ~RTL818X_CMD_TX_ENABLE;
1002 reg &= ~RTL818X_CMD_RX_ENABLE;
1003 rtl818x_iowrite8(priv, &priv->map->CMD, reg);
1004
f6532111 1005 priv->rf->stop(dev);
605bebe2
MW		 1006
1007 rtl818x_iowrite8(priv, &priv->map->EEPROM_CMD, RTL818X_EEPROM_CMD_CONFIG);
1008 reg = rtl818x_ioread8(priv, &priv->map->CONFIG4);
1009 rtl818x_iowrite8(priv, &priv->map->CONFIG4, reg | RTL818X_CONFIG4_VCOOFF);
1010 rtl818x_iowrite8(priv, &priv->map->EEPROM_CMD, RTL818X_EEPROM_CMD_NORMAL);
1011
3517afde
HRK		 1012 while ((skb = skb_dequeue(&priv->b_tx_status.queue)))
1013 dev_kfree_skb_any(skb);
c1db52b9
LF		 1014
1015 usb_kill_anchored_urbs(&priv->anchored);
2f47690e
LF		 1016 if (!priv->is_rtl8187b)
1017 cancel_delayed_work_sync(&priv->work);
7dcdd073 1018 mutex_unlock(&priv->conf_mutex);
605bebe2
MW		 1019}
1020
1021static int rtl8187_add_interface(struct ieee80211_hw *dev,
1022 struct ieee80211_if_init_conf *conf)
1023{
1024 struct rtl8187_priv *priv = dev->priv;
4150c572 1025 int i;
66aafd9a 1026 int ret = -EOPNOTSUPP;
605bebe2 1027
66aafd9a 1028 mutex_lock(&priv->conf_mutex);
05c914fe 1029 if (priv->mode != NL80211_IFTYPE_MONITOR)
66aafd9a 1030 goto exit;
605bebe2
MW		 1031
1032 switch (conf->type) {
05c914fe 1033 case NL80211_IFTYPE_STATION:
605bebe2
MW		 1034 priv->mode = conf->type;
1035 break;
1036 default:
66aafd9a 1037 goto exit;
605bebe2
MW		 1038 }
1039
66aafd9a 1040 ret = 0;
aa979a6a
HRK		 1041 priv->vif = conf->vif;
1042
4150c572
JB		 1043 rtl818x_iowrite8(priv, &priv->map->EEPROM_CMD, RTL818X_EEPROM_CMD_CONFIG);
1044 for (i = 0; i < ETH_ALEN; i++)
1045 rtl818x_iowrite8(priv, &priv->map->MAC[i],
1046 ((u8 *)conf->mac_addr)[i]);
1047 rtl818x_iowrite8(priv, &priv->map->EEPROM_CMD, RTL818X_EEPROM_CMD_NORMAL);
605bebe2 1048
66aafd9a 1049exit:
7dcdd073 1050 mutex_unlock(&priv->conf_mutex);
66aafd9a 1051 return ret;
605bebe2
MW		 1052}
1053
1054static void rtl8187_remove_interface(struct ieee80211_hw *dev,
1055 struct ieee80211_if_init_conf *conf)
1056{
1057 struct rtl8187_priv *priv = dev->priv;
7dcdd073 1058 mutex_lock(&priv->conf_mutex);
05c914fe 1059 priv->mode = NL80211_IFTYPE_MONITOR;
aa979a6a 1060 priv->vif = NULL;
7dcdd073 1061 mutex_unlock(&priv->conf_mutex);
605bebe2
MW		 1062}
1063
e8975581 1064static int rtl8187_config(struct ieee80211_hw *dev, u32 changed)
605bebe2
MW		 1065{
1066 struct rtl8187_priv *priv = dev->priv;
e8975581 1067 struct ieee80211_conf *conf = &dev->conf;
f6532111
MW		 1068 u32 reg;
1069
7dcdd073 1070 mutex_lock(&priv->conf_mutex);
f6532111
MW		 1071 reg = rtl818x_ioread32(priv, &priv->map->TX_CONF);
1072 /* Enable TX loopback on MAC level to avoid TX during channel
1073 * changes, as this has be seen to causes problems and the
1074 * card will stop work until next reset
1075 */
1076 rtl818x_iowrite32(priv, &priv->map->TX_CONF,
1077 reg | RTL818X_TX_CONF_LOOPBACK_MAC);
f6532111
MW		 1078 priv->rf->set_chan(dev, conf);
1079 msleep(10);
1080 rtl818x_iowrite32(priv, &priv->map->TX_CONF, reg);
605bebe2 1081
605bebe2
MW		 1082 rtl818x_iowrite16(priv, &priv->map->ATIM_WND, 2);
1083 rtl818x_iowrite16(priv, &priv->map->ATIMTR_INTERVAL, 100);
1084 rtl818x_iowrite16(priv, &priv->map->BEACON_INTERVAL, 100);
1085 rtl818x_iowrite16(priv, &priv->map->BEACON_INTERVAL_TIME, 100);
7dcdd073 1086 mutex_unlock(&priv->conf_mutex);
605bebe2
MW		 1087 return 0;
1088}
1089
b4572a92
HRK		 1090/*
1091 * With 8187B, AC_*_PARAM clashes with FEMR definition in struct rtl818x_csr for
1092 * example. Thus we have to use raw values for AC_*_PARAM register addresses.
1093 */
1094static __le32 *rtl8187b_ac_addr[4] = {
1095 (__le32 *) 0xFFF0, /* AC_VO */
1096 (__le32 *) 0xFFF4, /* AC_VI */
1097 (__le32 *) 0xFFFC, /* AC_BK */
1098 (__le32 *) 0xFFF8, /* AC_BE */
1099};
1100
1101#define SIFS_TIME 0xa
1102
f8288317
HRK		 1103static void rtl8187_conf_erp(struct rtl8187_priv *priv, bool use_short_slot,
1104 bool use_short_preamble)
64761077 1105{
f8288317 1106 if (priv->is_rtl8187b) {
b4572a92 1107 u8 difs, eifs;
f8288317 1108 u16 ack_timeout;
b4572a92 1109 int queue;
f8288317
HRK		 1110
1111 if (use_short_slot) {
b4572a92 1112 priv->slot_time = 0x9;
f8288317
HRK		 1113 difs = 0x1c;
1114 eifs = 0x53;
1115 } else {
b4572a92 1116 priv->slot_time = 0x14;
f8288317
HRK		 1117 difs = 0x32;
1118 eifs = 0x5b;
1119 }
54ac218a 1120 rtl818x_iowrite8(priv, &priv->map->SIFS, 0x22);
b4572a92 1121 rtl818x_iowrite8(priv, &priv->map->SLOT, priv->slot_time);
f8288317
HRK		 1122 rtl818x_iowrite8(priv, &priv->map->DIFS, difs);
1123
1124 /*
1125 * BRSR+1 on 8187B is in fact EIFS register
1126 * Value in units of 4 us
1127 */
1128 rtl818x_iowrite8(priv, (u8 *)&priv->map->BRSR + 1, eifs);
1129
1130 /*
1131 * For 8187B, CARRIER_SENSE_COUNTER is in fact ack timeout
1132 * register. In units of 4 us like eifs register
1133 * ack_timeout = ack duration + plcp + difs + preamble
1134 */
1135 ack_timeout = 112 + 48 + difs;
1136 if (use_short_preamble)
1137 ack_timeout += 72;
1138 else
1139 ack_timeout += 144;
1140 rtl818x_iowrite8(priv, &priv->map->CARRIER_SENSE_COUNTER,
1141 DIV_ROUND_UP(ack_timeout, 4));
b4572a92
HRK		 1142
1143 for (queue = 0; queue < 4; queue++)
1144 rtl818x_iowrite8(priv, (u8 *) rtl8187b_ac_addr[queue],
1145 priv->aifsn[queue] * priv->slot_time +
1146 SIFS_TIME);
f8288317 1147 } else {
64761077
HRK		 1148 rtl818x_iowrite8(priv, &priv->map->SIFS, 0x22);
1149 if (use_short_slot) {
1150 rtl818x_iowrite8(priv, &priv->map->SLOT, 0x9);
1151 rtl818x_iowrite8(priv, &priv->map->DIFS, 0x14);
1152 rtl818x_iowrite8(priv, &priv->map->EIFS, 91 - 0x14);
64761077
HRK		 1153 } else {
1154 rtl818x_iowrite8(priv, &priv->map->SLOT, 0x14);
1155 rtl818x_iowrite8(priv, &priv->map->DIFS, 0x24);
1156 rtl818x_iowrite8(priv, &priv->map->EIFS, 91 - 0x24);
64761077
HRK		 1157 }
1158 }
1159}
1160
1161static void rtl8187_bss_info_changed(struct ieee80211_hw *dev,
1162 struct ieee80211_vif *vif,
1163 struct ieee80211_bss_conf *info,
1164 u32 changed)
1165{
1166 struct rtl8187_priv *priv = dev->priv;
2d0ddec5
JB		 1167 int i;
1168 u8 reg;
1169
1170 if (changed & BSS_CHANGED_BSSID) {
1171 mutex_lock(&priv->conf_mutex);
1172 for (i = 0; i < ETH_ALEN; i++)
1173 rtl818x_iowrite8(priv, &priv->map->BSSID[i],
1174 info->bssid[i]);
1175
1176 if (is_valid_ether_addr(info->bssid)) {
1177 reg = RTL818X_MSR_INFRA;
1178 if (priv->is_rtl8187b)
1179 reg |= RTL818X_MSR_ENEDCA;
1180 rtl818x_iowrite8(priv, &priv->map->MSR, reg);
1181 } else {
1182 reg = RTL818X_MSR_NO_LINK;
1183 rtl818x_iowrite8(priv, &priv->map->MSR, reg);
1184 }
1185
1186 mutex_unlock(&priv->conf_mutex);
1187 }
64761077 1188
f8288317
HRK		 1189 if (changed & (BSS_CHANGED_ERP_SLOT | BSS_CHANGED_ERP_PREAMBLE))
1190 rtl8187_conf_erp(priv, info->use_short_slot,
1191 info->use_short_preamble);
64761077
HRK		 1192}
1193
4150c572
JB		 1194static void rtl8187_configure_filter(struct ieee80211_hw *dev,
1195 unsigned int changed_flags,
1196 unsigned int *total_flags,
2fe14263 1197 int mc_count, struct dev_addr_list *mclist)
4150c572
JB		 1198{
1199 struct rtl8187_priv *priv = dev->priv;
1200
4150c572
JB		 1201 if (changed_flags & FIF_FCSFAIL)
1202 priv->rx_conf ^= RTL818X_RX_CONF_FCS;
1203 if (changed_flags & FIF_CONTROL)
1204 priv->rx_conf ^= RTL818X_RX_CONF_CTRL;
1205 if (changed_flags & FIF_OTHER_BSS)
1206 priv->rx_conf ^= RTL818X_RX_CONF_MONITOR;
2fe14263 1207 if (*total_flags & FIF_ALLMULTI || mc_count > 0)
4150c572 1208 priv->rx_conf |= RTL818X_RX_CONF_MULTICAST;
2fe14263
MW		 1209 else
1210 priv->rx_conf &= ~RTL818X_RX_CONF_MULTICAST;
1211
1212 *total_flags = 0;
4150c572 1213
4150c572
JB		 1214 if (priv->rx_conf & RTL818X_RX_CONF_FCS)
1215 *total_flags |= FIF_FCSFAIL;
1216 if (priv->rx_conf & RTL818X_RX_CONF_CTRL)
1217 *total_flags |= FIF_CONTROL;
1218 if (priv->rx_conf & RTL818X_RX_CONF_MONITOR)
1219 *total_flags |= FIF_OTHER_BSS;
2fe14263
MW		 1220 if (priv->rx_conf & RTL818X_RX_CONF_MULTICAST)
1221 *total_flags |= FIF_ALLMULTI;
4150c572
JB		 1222
1223 rtl818x_iowrite32_async(priv, &priv->map->RX_CONF, priv->rx_conf);
1224}
1225
b4572a92
HRK		 1226static int rtl8187_conf_tx(struct ieee80211_hw *dev, u16 queue,
1227 const struct ieee80211_tx_queue_params *params)
1228{
1229 struct rtl8187_priv *priv = dev->priv;
1230 u8 cw_min, cw_max;
1231
1232 if (queue > 3)
1233 return -EINVAL;
1234
1235 cw_min = fls(params->cw_min);
1236 cw_max = fls(params->cw_max);
1237
1238 if (priv->is_rtl8187b) {
1239 priv->aifsn[queue] = params->aifs;
1240
1241 /*
1242 * This is the structure of AC_*_PARAM registers in 8187B:
1243 * - TXOP limit field, bit offset = 16
1244 * - ECWmax, bit offset = 12
1245 * - ECWmin, bit offset = 8
1246 * - AIFS, bit offset = 0
1247 */
1248 rtl818x_iowrite32(priv, rtl8187b_ac_addr[queue],
1249 (params->txop << 16) | (cw_max << 12) |
1250 (cw_min << 8) | (params->aifs *
1251 priv->slot_time + SIFS_TIME));
1252 } else {
1253 if (queue != 0)
1254 return -EINVAL;
1255
1256 rtl818x_iowrite8(priv, &priv->map->CW_VAL,
1257 cw_min | (cw_max << 4));
1258 }
1259 return 0;
1260}
1261
605bebe2
MW		 1262static const struct ieee80211_ops rtl8187_ops = {
1263 .tx = rtl8187_tx,
4150c572 1264 .start = rtl8187_start,
605bebe2
MW		 1265 .stop = rtl8187_stop,
1266 .add_interface = rtl8187_add_interface,
1267 .remove_interface = rtl8187_remove_interface,
1268 .config = rtl8187_config,
64761077 1269 .bss_info_changed = rtl8187_bss_info_changed,
4150c572 1270 .configure_filter = rtl8187_configure_filter,
b4572a92 1271 .conf_tx = rtl8187_conf_tx
605bebe2
MW		 1272};
1273
1274static void rtl8187_eeprom_register_read(struct eeprom_93cx6 *eeprom)
1275{
1276 struct ieee80211_hw *dev = eeprom->data;
1277 struct rtl8187_priv *priv = dev->priv;
1278 u8 reg = rtl818x_ioread8(priv, &priv->map->EEPROM_CMD);
1279
1280 eeprom->reg_data_in = reg & RTL818X_EEPROM_CMD_WRITE;
1281 eeprom->reg_data_out = reg & RTL818X_EEPROM_CMD_READ;
1282 eeprom->reg_data_clock = reg & RTL818X_EEPROM_CMD_CK;
1283 eeprom->reg_chip_select = reg & RTL818X_EEPROM_CMD_CS;
1284}
1285
1286static void rtl8187_eeprom_register_write(struct eeprom_93cx6 *eeprom)
1287{
1288 struct ieee80211_hw *dev = eeprom->data;
1289 struct rtl8187_priv *priv = dev->priv;
1290 u8 reg = RTL818X_EEPROM_CMD_PROGRAM;
1291
1292 if (eeprom->reg_data_in)
1293 reg |= RTL818X_EEPROM_CMD_WRITE;
1294 if (eeprom->reg_data_out)
1295 reg |= RTL818X_EEPROM_CMD_READ;
1296 if (eeprom->reg_data_clock)
1297 reg |= RTL818X_EEPROM_CMD_CK;
1298 if (eeprom->reg_chip_select)
1299 reg |= RTL818X_EEPROM_CMD_CS;
1300
1301 rtl818x_iowrite8(priv, &priv->map->EEPROM_CMD, reg);
1302 udelay(10);
1303}
1304
1305static int __devinit rtl8187_probe(struct usb_interface *intf,
1306 const struct usb_device_id *id)
1307{
1308 struct usb_device *udev = interface_to_usbdev(intf);
1309 struct ieee80211_hw *dev;
1310 struct rtl8187_priv *priv;
1311 struct eeprom_93cx6 eeprom;
1312 struct ieee80211_channel *channel;
6f7853f3 1313 const char *chip_name;
605bebe2
MW		 1314 u16 txpwr, reg;
1315 int err, i;
1316
1317 dev = ieee80211_alloc_hw(sizeof(*priv), &rtl8187_ops);
1318 if (!dev) {
1319 printk(KERN_ERR "rtl8187: ieee80211 alloc failed\n");
1320 return -ENOMEM;
1321 }
1322
1323 priv = dev->priv;
0e25b4ef 1324 priv->is_rtl8187b = (id->driver_info == DEVICE_RTL8187B);
605bebe2 1325
9be6f0d4
JL		 1326 /* allocate "DMA aware" buffer for register accesses */
1327 priv->io_dmabuf = kmalloc(sizeof(*priv->io_dmabuf), GFP_KERNEL);
1328 if (!priv->io_dmabuf) {
1329 err = -ENOMEM;
1330 goto err_free_dev;
1331 }
1332 mutex_init(&priv->io_mutex);
1333
605bebe2
MW		 1334 SET_IEEE80211_DEV(dev, &intf->dev);
1335 usb_set_intfdata(intf, dev);
1336 priv->udev = udev;
1337
1338 usb_get_dev(udev);
1339
1340 skb_queue_head_init(&priv->rx_queue);
8318d78a
JB		 1341
1342 BUILD_BUG_ON(sizeof(priv->channels) != sizeof(rtl818x_channels));
1343 BUILD_BUG_ON(sizeof(priv->rates) != sizeof(rtl818x_rates));
1344
605bebe2
MW		 1345 memcpy(priv->channels, rtl818x_channels, sizeof(rtl818x_channels));
1346 memcpy(priv->rates, rtl818x_rates, sizeof(rtl818x_rates));
1347 priv->map = (struct rtl818x_csr *)0xFF00;
8318d78a
JB		 1348
1349 priv->band.band = IEEE80211_BAND_2GHZ;
1350 priv->band.channels = priv->channels;
1351 priv->band.n_channels = ARRAY_SIZE(rtl818x_channels);
1352 priv->band.bitrates = priv->rates;
1353 priv->band.n_bitrates = ARRAY_SIZE(rtl818x_rates);
1354 dev->wiphy->bands[IEEE80211_BAND_2GHZ] = &priv->band;
1355
1356
05c914fe 1357 priv->mode = NL80211_IFTYPE_MONITOR;
605bebe2 1358 dev->flags = IEEE80211_HW_HOST_BROADCAST_PS_BUFFERING |
a7db74f4 1359 IEEE80211_HW_SIGNAL_DBM |
0ccd58fc 1360 IEEE80211_HW_RX_INCLUDES_FCS;
605bebe2 1361
605bebe2
MW		 1362 eeprom.data = dev;
1363 eeprom.register_read = rtl8187_eeprom_register_read;
1364 eeprom.register_write = rtl8187_eeprom_register_write;
1365 if (rtl818x_ioread32(priv, &priv->map->RX_CONF) & (1 << 6))
1366 eeprom.width = PCI_EEPROM_WIDTH_93C66;
1367 else
1368 eeprom.width = PCI_EEPROM_WIDTH_93C46;
1369
1370 rtl818x_iowrite8(priv, &priv->map->EEPROM_CMD, RTL818X_EEPROM_CMD_CONFIG);
1371 udelay(10);
1372
1373 eeprom_93cx6_multiread(&eeprom, RTL8187_EEPROM_MAC_ADDR,
1374 (__le16 __force *)dev->wiphy->perm_addr, 3);
1375 if (!is_valid_ether_addr(dev->wiphy->perm_addr)) {
1376 printk(KERN_WARNING "rtl8187: Invalid hwaddr! Using randomly "
1377 "generated MAC address\n");
1378 random_ether_addr(dev->wiphy->perm_addr);
1379 }
1380
1381 channel = priv->channels;
1382 for (i = 0; i < 3; i++) {
1383 eeprom_93cx6_read(&eeprom, RTL8187_EEPROM_TXPWR_CHAN_1 + i,
1384 &txpwr);
8318d78a
JB		 1385 (*channel++).hw_value = txpwr & 0xFF;
1386 (*channel++).hw_value = txpwr >> 8;
605bebe2
MW		 1387 }
1388 for (i = 0; i < 2; i++) {
1389 eeprom_93cx6_read(&eeprom, RTL8187_EEPROM_TXPWR_CHAN_4 + i,
1390 &txpwr);
8318d78a
JB		 1391 (*channel++).hw_value = txpwr & 0xFF;
1392 (*channel++).hw_value = txpwr >> 8;
605bebe2 1393 }
605bebe2
MW		 1394
1395 eeprom_93cx6_read(&eeprom, RTL8187_EEPROM_TXPWR_BASE,
1396 &priv->txpwr_base);
1397
f6532111
MW		 1398 reg = rtl818x_ioread8(priv, &priv->map->PGSELECT) & ~1;
1399 rtl818x_iowrite8(priv, &priv->map->PGSELECT, reg | 1);
605bebe2
MW		 1400 /* 0 means asic B-cut, we should use SW 3 wire
1401 * bit-by-bit banging for radio. 1 means we can use
1402 * USB specific request to write radio registers */
1403 priv->asic_rev = rtl818x_ioread8(priv, (u8 *)0xFFFE) & 0x3;
f6532111 1404 rtl818x_iowrite8(priv, &priv->map->PGSELECT, reg);
605bebe2
MW		 1405 rtl818x_iowrite8(priv, &priv->map->EEPROM_CMD, RTL818X_EEPROM_CMD_NORMAL);
1406
6f7853f3
HTL		 1407 if (!priv->is_rtl8187b) {
1408 u32 reg32;
1409 reg32 = rtl818x_ioread32(priv, &priv->map->TX_CONF);
1410 reg32 &= RTL818X_TX_CONF_HWVER_MASK;
1411 switch (reg32) {
0e25b4ef
LF		 1412 case RTL818X_TX_CONF_R8187vD_B:
1413 /* Some RTL8187B devices have a USB ID of 0x8187
1414 * detect them here */
1415 chip_name = "RTL8187BvB(early)";
1416 priv->is_rtl8187b = 1;
1417 priv->hw_rev = RTL8187BvB;
1418 break;
1419 case RTL818X_TX_CONF_R8187vD:
6f7853f3
HTL		 1420 chip_name = "RTL8187vD";
1421 break;
1422 default:
1423 chip_name = "RTL8187vB (default)";
1424 }
1425 } else {
6f7853f3
HTL		 1426 /*
1427 * Force USB request to write radio registers for 8187B, Realtek
1428 * only uses it in their sources
1429 */
1430 /*if (priv->asic_rev == 0) {
1431 printk(KERN_WARNING "rtl8187: Forcing use of USB "
1432 "requests to write to radio registers\n");
1433 priv->asic_rev = 1;
1434 }*/
1435 switch (rtl818x_ioread8(priv, (u8 *)0xFFE1)) {
1436 case RTL818X_R8187B_B:
1437 chip_name = "RTL8187BvB";
1438 priv->hw_rev = RTL8187BvB;
1439 break;
1440 case RTL818X_R8187B_D:
1441 chip_name = "RTL8187BvD";
1442 priv->hw_rev = RTL8187BvD;
1443 break;
1444 case RTL818X_R8187B_E:
1445 chip_name = "RTL8187BvE";
1446 priv->hw_rev = RTL8187BvE;
1447 break;
1448 default:
1449 chip_name = "RTL8187BvB (default)";
1450 priv->hw_rev = RTL8187BvB;
1451 }
1452 }
1453
0e25b4ef
LF		 1454 if (!priv->is_rtl8187b) {
1455 for (i = 0; i < 2; i++) {
1456 eeprom_93cx6_read(&eeprom,
1457 RTL8187_EEPROM_TXPWR_CHAN_6 + i,
1458 &txpwr);
1459 (*channel++).hw_value = txpwr & 0xFF;
1460 (*channel++).hw_value = txpwr >> 8;
1461 }
1462 } else {
1463 eeprom_93cx6_read(&eeprom, RTL8187_EEPROM_TXPWR_CHAN_6,
1464 &txpwr);
1465 (*channel++).hw_value = txpwr & 0xFF;
1466
1467 eeprom_93cx6_read(&eeprom, 0x0A, &txpwr);
1468 (*channel++).hw_value = txpwr & 0xFF;
1469
1470 eeprom_93cx6_read(&eeprom, 0x1C, &txpwr);
1471 (*channel++).hw_value = txpwr & 0xFF;
1472 (*channel++).hw_value = txpwr >> 8;
1473 }
1474
94778280
JB		 1475 /*
1476 * XXX: Once this driver supports anything that requires
1477 * beacons it must implement IEEE80211_TX_CTL_ASSIGN_SEQ.
1478 */
f59ac048
LR		 1479 dev->wiphy->interface_modes = BIT(NL80211_IFTYPE_STATION);
1480
0e25b4ef
LF		 1481 if ((id->driver_info == DEVICE_RTL8187) && priv->is_rtl8187b)
1482 printk(KERN_INFO "rtl8187: inconsistency between id with OEM"
1483 " info!\n");
1484
f6532111 1485 priv->rf = rtl8187_detect_rf(dev);
0e25b4ef
LF		 1486 dev->extra_tx_headroom = (!priv->is_rtl8187b) ?
1487 sizeof(struct rtl8187_tx_hdr) :
1488 sizeof(struct rtl8187b_tx_hdr);
1489 if (!priv->is_rtl8187b)
1490 dev->queues = 1;
1491 else
1492 dev->queues = 4;
605bebe2
MW		 1493
1494 err = ieee80211_register_hw(dev);
1495 if (err) {
1496 printk(KERN_ERR "rtl8187: Cannot register device\n");
9be6f0d4 1497 goto err_free_dmabuf;
605bebe2 1498 }
7dcdd073 1499 mutex_init(&priv->conf_mutex);
3517afde 1500 skb_queue_head_init(&priv->b_tx_status.queue);
605bebe2 1501
e174961c
JB		 1502 printk(KERN_INFO "%s: hwaddr %pM, %s V%d + %s\n",
1503 wiphy_name(dev->wiphy), dev->wiphy->perm_addr,
6f7853f3 1504 chip_name, priv->asic_rev, priv->rf->name);
605bebe2 1505
a027087a
LF		 1506#ifdef CONFIG_RTL8187_LEDS
1507 eeprom_93cx6_read(&eeprom, 0x3F, &reg);
1508 reg &= 0xFF;
1509 rtl8187_leds_init(dev, reg);
1510#endif
1511
605bebe2
MW		 1512 return 0;
1513
9be6f0d4
JL		 1514 err_free_dmabuf:
1515 kfree(priv->io_dmabuf);
605bebe2
MW		 1516 err_free_dev:
1517 ieee80211_free_hw(dev);
1518 usb_set_intfdata(intf, NULL);
1519 usb_put_dev(udev);
1520 return err;
1521}
1522
1523static void __devexit rtl8187_disconnect(struct usb_interface *intf)
1524{
1525 struct ieee80211_hw *dev = usb_get_intfdata(intf);
1526 struct rtl8187_priv *priv;
1527
1528 if (!dev)
1529 return;
1530
a027087a
LF		 1531#ifdef CONFIG_RTL8187_LEDS
1532 rtl8187_leds_exit(dev);
1533#endif
605bebe2
MW		 1534 ieee80211_unregister_hw(dev);
1535
1536 priv = dev->priv;
d6e2be98 1537 usb_reset_device(priv->udev);
605bebe2 1538 usb_put_dev(interface_to_usbdev(intf));
9be6f0d4 1539 kfree(priv->io_dmabuf);
605bebe2
MW		 1540 ieee80211_free_hw(dev);
1541}
1542
1543static struct usb_driver rtl8187_driver = {
1544 .name = KBUILD_MODNAME,
1545 .id_table = rtl8187_table,
1546 .probe = rtl8187_probe,
500c1197 1547 .disconnect = __devexit_p(rtl8187_disconnect),
605bebe2
MW		 1548};
1549
1550static int __init rtl8187_init(void)
1551{
1552 return usb_register(&rtl8187_driver);
1553}
1554
1555static void __exit rtl8187_exit(void)
1556{
1557 usb_deregister(&rtl8187_driver);
1558}
1559
1560module_init(rtl8187_init);
1561module_exit(rtl8187_exit);
Linux kernel - Deliverables
This page took 0.507059 seconds and 5 git commands to generate.