projects / deliverable / linux.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
mac80211: allow configure_filter callback to sleep
[deliverable/linux.git] / drivers / net / wireless / rtl818x / rtl8187_dev.c
CommitLineData
605bebe2
MW		 1/*
2 * Linux device driver for RTL8187
3 *
4 * Copyright 2007 Michael Wu <flamingice@sourmilk.net>
5 * Copyright 2007 Andrea Merello <andreamrl@tiscali.it>
6 *
7 * Based on the r8187 driver, which is:
8 * Copyright 2005 Andrea Merello <andreamrl@tiscali.it>, et al.
9 *
3461fc12
LF		 10 * The driver was extended to the RTL8187B in 2008 by:
11 * Herton Ronaldo Krzesinski <herton@mandriva.com.br>
12 * Hin-Tak Leung <htl10@users.sourceforge.net>
13 * Larry Finger <Larry.Finger@lwfinger.net>
14 *
0aec00ae
JL		 15 * Magic delays and register offsets below are taken from the original
16 * r8187 driver sources. Thanks to Realtek for their support!
605bebe2
MW		 17 *
18 * This program is free software; you can redistribute it and/or modify
19 * it under the terms of the GNU General Public License version 2 as
20 * published by the Free Software Foundation.
21 */
22
23#include <linux/init.h>
24#include <linux/usb.h>
25#include <linux/delay.h>
26#include <linux/etherdevice.h>
27#include <linux/eeprom_93cx6.h>
28#include <net/mac80211.h>
29
30#include "rtl8187.h"
31#include "rtl8187_rtl8225.h"
a027087a
LF		 32#ifdef CONFIG_RTL8187_LEDS
33#include "rtl8187_leds.h"
34#endif
605bebe2
MW		 35
36MODULE_AUTHOR("Michael Wu <flamingice@sourmilk.net>");
37MODULE_AUTHOR("Andrea Merello <andreamrl@tiscali.it>");
3461fc12
LF		 38MODULE_AUTHOR("Herton Ronaldo Krzesinski <herton@mandriva.com.br>");
39MODULE_AUTHOR("Hin-Tak Leung <htl10@users.sourceforge.net>");
40MODULE_AUTHOR("Larry Finger <Larry.Finger@lwfinger.net>");
f8a08c34 41MODULE_DESCRIPTION("RTL8187/RTL8187B USB wireless driver");
605bebe2
MW		 42MODULE_LICENSE("GPL");
43
44static struct usb_device_id rtl8187_table[] __devinitdata = {
7c7e6af3
AM		 45 /* Asus */
46 {USB_DEVICE(0x0b05, 0x171d), .driver_info = DEVICE_RTL8187},
eaca90da
FF		 47 /* Belkin */
48 {USB_DEVICE(0x050d, 0x705e), .driver_info = DEVICE_RTL8187B},
605bebe2 49 /* Realtek */
f8a08c34
HTL		 50 {USB_DEVICE(0x0bda, 0x8187), .driver_info = DEVICE_RTL8187},
51 {USB_DEVICE(0x0bda, 0x8189), .driver_info = DEVICE_RTL8187B},
52 {USB_DEVICE(0x0bda, 0x8197), .driver_info = DEVICE_RTL8187B},
746db510 53 {USB_DEVICE(0x0bda, 0x8198), .driver_info = DEVICE_RTL8187B},
046ee5d2
LF		 54 /* Surecom */
55 {USB_DEVICE(0x0769, 0x11F2), .driver_info = DEVICE_RTL8187},
56 /* Logitech */
57 {USB_DEVICE(0x0789, 0x010C), .driver_info = DEVICE_RTL8187},
605bebe2 58 /* Netgear */
f8a08c34
HTL		 59 {USB_DEVICE(0x0846, 0x6100), .driver_info = DEVICE_RTL8187},
60 {USB_DEVICE(0x0846, 0x6a00), .driver_info = DEVICE_RTL8187},
fcd7cc14 61 {USB_DEVICE(0x0846, 0x4260), .driver_info = DEVICE_RTL8187B},
c3cf60a9 62 /* HP */
f8a08c34 63 {USB_DEVICE(0x03f0, 0xca02), .driver_info = DEVICE_RTL8187},
9934550d 64 /* Sitecom */
f8a08c34 65 {USB_DEVICE(0x0df6, 0x000d), .driver_info = DEVICE_RTL8187},
f3c76918 66 {USB_DEVICE(0x0df6, 0x0028), .driver_info = DEVICE_RTL8187B},
046ee5d2
LF		 67 /* Sphairon Access Systems GmbH */
68 {USB_DEVICE(0x114B, 0x0150), .driver_info = DEVICE_RTL8187},
69 /* Dick Smith Electronics */
70 {USB_DEVICE(0x1371, 0x9401), .driver_info = DEVICE_RTL8187},
8f7c41d4
IK		 71 /* Abocom */
72 {USB_DEVICE(0x13d1, 0xabe6), .driver_info = DEVICE_RTL8187},
046ee5d2
LF		 73 /* Qcom */
74 {USB_DEVICE(0x18E8, 0x6232), .driver_info = DEVICE_RTL8187},
75 /* AirLive */
76 {USB_DEVICE(0x1b75, 0x8187), .driver_info = DEVICE_RTL8187},
aeeab4ff
JL		 77 /* Linksys */
78 {USB_DEVICE(0x1737, 0x0073), .driver_info = DEVICE_RTL8187B},
605bebe2
MW		 79 {}
80};
81
82MODULE_DEVICE_TABLE(usb, rtl8187_table);
83
8318d78a
JB		 84static const struct ieee80211_rate rtl818x_rates[] = {
85 { .bitrate = 10, .hw_value = 0, },
86 { .bitrate = 20, .hw_value = 1, },
87 { .bitrate = 55, .hw_value = 2, },
88 { .bitrate = 110, .hw_value = 3, },
89 { .bitrate = 60, .hw_value = 4, },
90 { .bitrate = 90, .hw_value = 5, },
91 { .bitrate = 120, .hw_value = 6, },
92 { .bitrate = 180, .hw_value = 7, },
93 { .bitrate = 240, .hw_value = 8, },
94 { .bitrate = 360, .hw_value = 9, },
95 { .bitrate = 480, .hw_value = 10, },
96 { .bitrate = 540, .hw_value = 11, },
97};
98
99static const struct ieee80211_channel rtl818x_channels[] = {
100 { .center_freq = 2412 },
101 { .center_freq = 2417 },
102 { .center_freq = 2422 },
103 { .center_freq = 2427 },
104 { .center_freq = 2432 },
105 { .center_freq = 2437 },
106 { .center_freq = 2442 },
107 { .center_freq = 2447 },
108 { .center_freq = 2452 },
109 { .center_freq = 2457 },
110 { .center_freq = 2462 },
111 { .center_freq = 2467 },
112 { .center_freq = 2472 },
113 { .center_freq = 2484 },
114};
115
4150c572
JB		 116static void rtl8187_iowrite_async_cb(struct urb *urb)
117{
118 kfree(urb->context);
4150c572
JB		 119}
120
121static void rtl8187_iowrite_async(struct rtl8187_priv *priv, __le16 addr,
122 void *data, u16 len)
123{
124 struct usb_ctrlrequest *dr;
125 struct urb *urb;
126 struct rtl8187_async_write_data {
127 u8 data[4];
128 struct usb_ctrlrequest dr;
129 } *buf;
ea8ee240 130 int rc;
4150c572
JB		 131
132 buf = kmalloc(sizeof(*buf), GFP_ATOMIC);
133 if (!buf)
134 return;
135
136 urb = usb_alloc_urb(0, GFP_ATOMIC);
137 if (!urb) {
138 kfree(buf);
139 return;
140 }
141
142 dr = &buf->dr;
143
144 dr->bRequestType = RTL8187_REQT_WRITE;
145 dr->bRequest = RTL8187_REQ_SET_REG;
146 dr->wValue = addr;
147 dr->wIndex = 0;
148 dr->wLength = cpu_to_le16(len);
149
150 memcpy(buf, data, len);
151
152 usb_fill_control_urb(urb, priv->udev, usb_sndctrlpipe(priv->udev, 0),
153 (unsigned char *)dr, buf, len,
154 rtl8187_iowrite_async_cb, buf);
c1db52b9 155 usb_anchor_urb(urb, &priv->anchored);
ea8ee240
ON		 156 rc = usb_submit_urb(urb, GFP_ATOMIC);
157 if (rc < 0) {
158 kfree(buf);
c1db52b9 159 usb_unanchor_urb(urb);
ea8ee240 160 }
c1db52b9 161 usb_free_urb(urb);
4150c572
JB		 162}
163
164static inline void rtl818x_iowrite32_async(struct rtl8187_priv *priv,
165 __le32 *addr, u32 val)
166{
167 __le32 buf = cpu_to_le32(val);
168
169 rtl8187_iowrite_async(priv, cpu_to_le16((unsigned long)addr),
170 &buf, sizeof(buf));
171}
172
605bebe2
MW		 173void rtl8187_write_phy(struct ieee80211_hw *dev, u8 addr, u32 data)
174{
175 struct rtl8187_priv *priv = dev->priv;
176
177 data <<= 8;
178 data |= addr | 0x80;
179
180 rtl818x_iowrite8(priv, &priv->map->PHY[3], (data >> 24) & 0xFF);
181 rtl818x_iowrite8(priv, &priv->map->PHY[2], (data >> 16) & 0xFF);
182 rtl818x_iowrite8(priv, &priv->map->PHY[1], (data >> 8) & 0xFF);
183 rtl818x_iowrite8(priv, &priv->map->PHY[0], data & 0xFF);
605bebe2
MW		 184}
185
186static void rtl8187_tx_cb(struct urb *urb)
187{
605bebe2 188 struct sk_buff *skb = (struct sk_buff *)urb->context;
e039fa4a 189 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
e6a9854b 190 struct ieee80211_hw *hw = info->rate_driver_data[0];
6f7853f3 191 struct rtl8187_priv *priv = hw->priv;
605bebe2 192
6f7853f3
HTL		 193 skb_pull(skb, priv->is_rtl8187b ? sizeof(struct rtl8187b_tx_hdr) :
194 sizeof(struct rtl8187_tx_hdr));
e6a9854b 195 ieee80211_tx_info_clear_status(info);
3517afde 196
2f47690e
LF		 197 if (!(urb->status) && !(info->flags & IEEE80211_TX_CTL_NO_ACK)) {
198 if (priv->is_rtl8187b) {
199 skb_queue_tail(&priv->b_tx_status.queue, skb);
200
201 /* queue is "full", discard last items */
202 while (skb_queue_len(&priv->b_tx_status.queue) > 5) {
203 struct sk_buff *old_skb;
204
205 dev_dbg(&priv->udev->dev,
206 "transmit status queue full\n");
207
208 old_skb = skb_dequeue(&priv->b_tx_status.queue);
209 ieee80211_tx_status_irqsafe(hw, old_skb);
210 }
211 return;
212 } else {
3517afde 213 info->flags |= IEEE80211_TX_STAT_ACK;
2f47690e
LF		 214 }
215 }
216 if (priv->is_rtl8187b)
3517afde 217 ieee80211_tx_status_irqsafe(hw, skb);
2f47690e
LF		 218 else {
219 /* Retry information for the RTI8187 is only available by
220 * reading a register in the device. We are in interrupt mode
221 * here, thus queue the skb and finish on a work queue. */
222 skb_queue_tail(&priv->b_tx_status.queue, skb);
42935eca 223 ieee80211_queue_delayed_work(hw, &priv->work, 0);
3517afde 224 }
605bebe2
MW		 225}
226
e039fa4a 227static int rtl8187_tx(struct ieee80211_hw *dev, struct sk_buff *skb)
605bebe2
MW		 228{
229 struct rtl8187_priv *priv = dev->priv;
e039fa4a 230 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
6f7853f3
HTL		 231 unsigned int ep;
232 void *buf;
605bebe2 233 struct urb *urb;
98798f48
MW		 234 __le16 rts_dur = 0;
235 u32 flags;
ea8ee240 236 int rc;
605bebe2
MW		 237
238 urb = usb_alloc_urb(0, GFP_ATOMIC);
239 if (!urb) {
240 kfree_skb(skb);
d6e2be98 241 return NETDEV_TX_OK;
605bebe2
MW		 242 }
243
98798f48 244 flags = skb->len;
38e3b0d8 245 flags |= RTL818X_TX_DESC_FLAG_NO_ENC;
aa68cbfb 246
e039fa4a 247 flags |= ieee80211_get_tx_rate(dev, info)->hw_value << 24;
8b7b1e05 248 if (ieee80211_has_morefrags(((struct ieee80211_hdr *)skb->data)->frame_control))
38e3b0d8 249 flags |= RTL818X_TX_DESC_FLAG_MOREFRAG;
e6a9854b 250 if (info->control.rates[0].flags & IEEE80211_TX_RC_USE_RTS_CTS) {
38e3b0d8 251 flags |= RTL818X_TX_DESC_FLAG_RTS;
e039fa4a 252 flags |= ieee80211_get_rts_cts_rate(dev, info)->hw_value << 19;
32bfd35d 253 rts_dur = ieee80211_rts_duration(dev, priv->vif,
e039fa4a 254 skb->len, info);
e6a9854b 255 } else if (info->control.rates[0].flags & IEEE80211_TX_RC_USE_CTS_PROTECT) {
38e3b0d8 256 flags |= RTL818X_TX_DESC_FLAG_CTS;
e039fa4a 257 flags |= ieee80211_get_rts_cts_rate(dev, info)->hw_value << 19;
aa68cbfb 258 }
98798f48 259
6f7853f3
HTL		 260 if (!priv->is_rtl8187b) {
261 struct rtl8187_tx_hdr *hdr =
262 (struct rtl8187_tx_hdr *)skb_push(skb, sizeof(*hdr));
263 hdr->flags = cpu_to_le32(flags);
264 hdr->len = 0;
265 hdr->rts_duration = rts_dur;
d9a1f486 266 hdr->retry = cpu_to_le32((info->control.rates[0].count - 1) << 8);
6f7853f3
HTL		 267 buf = hdr;
268
269 ep = 2;
270 } else {
271 /* fc needs to be calculated before skb_push() */
272 unsigned int epmap[4] = { 6, 7, 5, 4 };
273 struct ieee80211_hdr *tx_hdr =
274 (struct ieee80211_hdr *)(skb->data);
275 u16 fc = le16_to_cpu(tx_hdr->frame_control);
276
277 struct rtl8187b_tx_hdr *hdr =
278 (struct rtl8187b_tx_hdr *)skb_push(skb, sizeof(*hdr));
279 struct ieee80211_rate *txrate =
280 ieee80211_get_tx_rate(dev, info);
281 memset(hdr, 0, sizeof(*hdr));
282 hdr->flags = cpu_to_le32(flags);
283 hdr->rts_duration = rts_dur;
d9a1f486 284 hdr->retry = cpu_to_le32((info->control.rates[0].count - 1) << 8);
6f7853f3
HTL		 285 hdr->tx_duration =
286 ieee80211_generic_frame_duration(dev, priv->vif,
287 skb->len, txrate);
288 buf = hdr;
289
290 if ((fc & IEEE80211_FCTL_FTYPE) == IEEE80211_FTYPE_MGMT)
291 ep = 12;
292 else
293 ep = epmap[skb_get_queue_mapping(skb)];
294 }
605bebe2 295
e6a9854b
JB		 296 info->rate_driver_data[0] = dev;
297 info->rate_driver_data[1] = urb;
6f7853f3
HTL		 298
299 usb_fill_bulk_urb(urb, priv->udev, usb_sndbulkpipe(priv->udev, ep),
300 buf, skb->len, rtl8187_tx_cb, skb);
2fcbab04 301 urb->transfer_flags |= URB_ZERO_PACKET;
c1db52b9 302 usb_anchor_urb(urb, &priv->anchored);
ea8ee240
ON		 303 rc = usb_submit_urb(urb, GFP_ATOMIC);
304 if (rc < 0) {
c1db52b9 305 usb_unanchor_urb(urb);
ea8ee240
ON		 306 kfree_skb(skb);
307 }
c1db52b9 308 usb_free_urb(urb);
605bebe2 309
d6e2be98 310 return NETDEV_TX_OK;
605bebe2
MW		 311}
312
313static void rtl8187_rx_cb(struct urb *urb)
314{
315 struct sk_buff *skb = (struct sk_buff *)urb->context;
316 struct rtl8187_rx_info *info = (struct rtl8187_rx_info *)skb->cb;
317 struct ieee80211_hw *dev = info->dev;
318 struct rtl8187_priv *priv = dev->priv;
605bebe2
MW		 319 struct ieee80211_rx_status rx_status = { 0 };
320 int rate, signal;
4150c572 321 u32 flags;
0ccd58fc 322 u32 quality;
d8588227 323 unsigned long f;
605bebe2 324
d8588227 325 spin_lock_irqsave(&priv->rx_queue.lock, f);
46c37672 326 __skb_unlink(skb, &priv->rx_queue);
d8588227 327 spin_unlock_irqrestore(&priv->rx_queue.lock, f);
c1db52b9 328 skb_put(skb, urb->actual_length);
605bebe2
MW		 329
330 if (unlikely(urb->status)) {
605bebe2
MW		 331 dev_kfree_skb_irq(skb);
332 return;
333 }
334
6f7853f3
HTL		 335 if (!priv->is_rtl8187b) {
336 struct rtl8187_rx_hdr *hdr =
337 (typeof(hdr))(skb_tail_pointer(skb) - sizeof(*hdr));
338 flags = le32_to_cpu(hdr->flags);
a7db74f4
LF		 339 /* As with the RTL8187B below, the AGC is used to calculate
340 * signal strength and quality. In this case, the scaling
341 * constants are derived from the output of p54usb.
342 */
343 quality = 130 - ((41 * hdr->agc) >> 6);
344 signal = -4 - ((27 * hdr->agc) >> 6);
6f7853f3 345 rx_status.antenna = (hdr->signal >> 7) & 1;
6f7853f3 346 rx_status.mactime = le64_to_cpu(hdr->mac_time);
6f7853f3
HTL		 347 } else {
348 struct rtl8187b_rx_hdr *hdr =
349 (typeof(hdr))(skb_tail_pointer(skb) - sizeof(*hdr));
0ccd58fc
LF		 350 /* The Realtek datasheet for the RTL8187B shows that the RX
351 * header contains the following quantities: signal quality,
352 * RSSI, AGC, the received power in dB, and the measured SNR.
353 * In testing, none of these quantities show qualitative
354 * agreement with AP signal strength, except for the AGC,
355 * which is inversely proportional to the strength of the
356 * signal. In the following, the quality and signal strength
357 * are derived from the AGC. The arbitrary scaling constants
358 * are chosen to make the results close to the values obtained
359 * for a BCM4312 using b43 as the driver. The noise is ignored
360 * for now.
361 */
6f7853f3 362 flags = le32_to_cpu(hdr->flags);
0ccd58fc 363 quality = 170 - hdr->agc;
0ccd58fc 364 signal = 14 - hdr->agc / 2;
0ccd58fc 365 rx_status.antenna = (hdr->rssi >> 7) & 1;
6f7853f3 366 rx_status.mactime = le64_to_cpu(hdr->mac_time);
6f7853f3 367 }
605bebe2 368
a7db74f4
LF		 369 if (quality > 100)
370 quality = 100;
371 rx_status.qual = quality;
372 priv->quality = quality;
373 rx_status.signal = signal;
374 priv->signal = signal;
375 rate = (flags >> 20) & 0xF;
6f7853f3 376 skb_trim(skb, flags & 0x0FFF);
8318d78a
JB		 377 rx_status.rate_idx = rate;
378 rx_status.freq = dev->conf.channel->center_freq;
379 rx_status.band = dev->conf.channel->band;
03bffc13 380 rx_status.flag |= RX_FLAG_TSFT;
38e3b0d8 381 if (flags & RTL818X_RX_DESC_FLAG_CRC32_ERR)
4150c572 382 rx_status.flag |= RX_FLAG_FAILED_FCS_CRC;
f1d58c25
JB		 383 memcpy(IEEE80211_SKB_RXCB(skb), &rx_status, sizeof(rx_status));
384 ieee80211_rx_irqsafe(dev, skb);
605bebe2
MW		 385
386 skb = dev_alloc_skb(RTL8187_MAX_RX);
387 if (unlikely(!skb)) {
605bebe2
MW		 388 /* TODO check rx queue length and refill *somewhere* */
389 return;
390 }
391
392 info = (struct rtl8187_rx_info *)skb->cb;
393 info->urb = urb;
394 info->dev = dev;
395 urb->transfer_buffer = skb_tail_pointer(skb);
396 urb->context = skb;
397 skb_queue_tail(&priv->rx_queue, skb);
398
c1db52b9
LF		 399 usb_anchor_urb(urb, &priv->anchored);
400 if (usb_submit_urb(urb, GFP_ATOMIC)) {
401 usb_unanchor_urb(urb);
402 skb_unlink(skb, &priv->rx_queue);
403 dev_kfree_skb_irq(skb);
404 }
605bebe2
MW		 405}
406
407static int rtl8187_init_urbs(struct ieee80211_hw *dev)
408{
409 struct rtl8187_priv *priv = dev->priv;
c1db52b9 410 struct urb *entry = NULL;
605bebe2
MW		 411 struct sk_buff *skb;
412 struct rtl8187_rx_info *info;
c1db52b9 413 int ret = 0;
605bebe2 414
2a57cf3e 415 while (skb_queue_len(&priv->rx_queue) < 16) {
605bebe2 416 skb = __dev_alloc_skb(RTL8187_MAX_RX, GFP_KERNEL);
c1db52b9
LF		 417 if (!skb) {
418 ret = -ENOMEM;
419 goto err;
420 }
605bebe2
MW		 421 entry = usb_alloc_urb(0, GFP_KERNEL);
422 if (!entry) {
c1db52b9
LF		 423 ret = -ENOMEM;
424 goto err;
605bebe2
MW		 425 }
426 usb_fill_bulk_urb(entry, priv->udev,
6f7853f3
HTL		 427 usb_rcvbulkpipe(priv->udev,
428 priv->is_rtl8187b ? 3 : 1),
605bebe2
MW		 429 skb_tail_pointer(skb),
430 RTL8187_MAX_RX, rtl8187_rx_cb, skb);
431 info = (struct rtl8187_rx_info *)skb->cb;
432 info->urb = entry;
433 info->dev = dev;
434 skb_queue_tail(&priv->rx_queue, skb);
c1db52b9
LF		 435 usb_anchor_urb(entry, &priv->anchored);
436 ret = usb_submit_urb(entry, GFP_KERNEL);
437 if (ret) {
438 skb_unlink(skb, &priv->rx_queue);
439 usb_unanchor_urb(entry);
440 goto err;
441 }
442 usb_free_urb(entry);
605bebe2 443 }
c1db52b9 444 return ret;
605bebe2 445
c1db52b9
LF		 446err:
447 usb_free_urb(entry);
448 kfree_skb(skb);
449 usb_kill_anchored_urbs(&priv->anchored);
450 return ret;
605bebe2
MW		 451}
452
3517afde
HRK		 453static void rtl8187b_status_cb(struct urb *urb)
454{
455 struct ieee80211_hw *hw = (struct ieee80211_hw *)urb->context;
456 struct rtl8187_priv *priv = hw->priv;
457 u64 val;
458 unsigned int cmd_type;
459
c1db52b9 460 if (unlikely(urb->status))
3517afde 461 return;
3517afde
HRK		 462
463 /*
464 * Read from status buffer:
465 *
466 * bits [30:31] = cmd type:
467 * - 0 indicates tx beacon interrupt
468 * - 1 indicates tx close descriptor
469 *
470 * In the case of tx beacon interrupt:
471 * [0:9] = Last Beacon CW
472 * [10:29] = reserved
473 * [30:31] = 00b
474 * [32:63] = Last Beacon TSF
475 *
476 * If it's tx close descriptor:
477 * [0:7] = Packet Retry Count
478 * [8:14] = RTS Retry Count
479 * [15] = TOK
480 * [16:27] = Sequence No
481 * [28] = LS
482 * [29] = FS
483 * [30:31] = 01b
484 * [32:47] = unused (reserved?)
485 * [48:63] = MAC Used Time
486 */
487 val = le64_to_cpu(priv->b_tx_status.buf);
488
489 cmd_type = (val >> 30) & 0x3;
490 if (cmd_type == 1) {
491 unsigned int pkt_rc, seq_no;
492 bool tok;
493 struct sk_buff *skb;
494 struct ieee80211_hdr *ieee80211hdr;
495 unsigned long flags;
496
497 pkt_rc = val & 0xFF;
498 tok = val & (1 << 15);
499 seq_no = (val >> 16) & 0xFFF;
500
501 spin_lock_irqsave(&priv->b_tx_status.queue.lock, flags);
502 skb_queue_reverse_walk(&priv->b_tx_status.queue, skb) {
503 ieee80211hdr = (struct ieee80211_hdr *)skb->data;
504
505 /*
506 * While testing, it was discovered that the seq_no
507 * doesn't actually contains the sequence number.
508 * Instead of returning just the 12 bits of sequence
509 * number, hardware is returning entire sequence control
510 * (fragment number plus sequence number) in a 12 bit
511 * only field overflowing after some time. As a
512 * workaround, just consider the lower bits, and expect
513 * it's unlikely we wrongly ack some sent data
514 */
515 if ((le16_to_cpu(ieee80211hdr->seq_ctrl)
516 & 0xFFF) == seq_no)
517 break;
518 }
519 if (skb != (struct sk_buff *) &priv->b_tx_status.queue) {
520 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
521
522 __skb_unlink(skb, &priv->b_tx_status.queue);
523 if (tok)
524 info->flags |= IEEE80211_TX_STAT_ACK;
1548c86a 525 info->status.rates[0].count = pkt_rc + 1;
3517afde
HRK		 526
527 ieee80211_tx_status_irqsafe(hw, skb);
528 }
529 spin_unlock_irqrestore(&priv->b_tx_status.queue.lock, flags);
530 }
531
c1db52b9
LF		 532 usb_anchor_urb(urb, &priv->anchored);
533 if (usb_submit_urb(urb, GFP_ATOMIC))
534 usb_unanchor_urb(urb);
3517afde
HRK		 535}
536
537static int rtl8187b_init_status_urb(struct ieee80211_hw *dev)
538{
539 struct rtl8187_priv *priv = dev->priv;
540 struct urb *entry;
c1db52b9 541 int ret = 0;
3517afde
HRK		 542
543 entry = usb_alloc_urb(0, GFP_KERNEL);
544 if (!entry)
545 return -ENOMEM;
3517afde
HRK		 546
547 usb_fill_bulk_urb(entry, priv->udev, usb_rcvbulkpipe(priv->udev, 9),
548 &priv->b_tx_status.buf, sizeof(priv->b_tx_status.buf),
549 rtl8187b_status_cb, dev);
550
c1db52b9
LF		 551 usb_anchor_urb(entry, &priv->anchored);
552 ret = usb_submit_urb(entry, GFP_KERNEL);
553 if (ret)
554 usb_unanchor_urb(entry);
555 usb_free_urb(entry);
3517afde 556
c1db52b9 557 return ret;
3517afde
HRK		 558}
559
f8a08c34 560static int rtl8187_cmd_reset(struct ieee80211_hw *dev)
605bebe2
MW		 561{
562 struct rtl8187_priv *priv = dev->priv;
563 u8 reg;
564 int i;
565
605bebe2
MW		 566 reg = rtl818x_ioread8(priv, &priv->map->CMD);
567 reg &= (1 << 1);
568 reg |= RTL818X_CMD_RESET;
569 rtl818x_iowrite8(priv, &priv->map->CMD, reg);
570
571 i = 10;
572 do {
573 msleep(2);
574 if (!(rtl818x_ioread8(priv, &priv->map->CMD) &
575 RTL818X_CMD_RESET))
576 break;
577 } while (--i);
578
579 if (!i) {
580 printk(KERN_ERR "%s: Reset timeout!\n", wiphy_name(dev->wiphy));
581 return -ETIMEDOUT;
582 }
583
584 /* reload registers from eeprom */
585 rtl818x_iowrite8(priv, &priv->map->EEPROM_CMD, RTL818X_EEPROM_CMD_LOAD);
586
587 i = 10;
588 do {
589 msleep(4);
590 if (!(rtl818x_ioread8(priv, &priv->map->EEPROM_CMD) &
591 RTL818X_EEPROM_CMD_CONFIG))
592 break;
593 } while (--i);
594
595 if (!i) {
596 printk(KERN_ERR "%s: eeprom reset timeout!\n",
597 wiphy_name(dev->wiphy));
598 return -ETIMEDOUT;
599 }
600
f8a08c34
HTL		 601 return 0;
602}
603
604static int rtl8187_init_hw(struct ieee80211_hw *dev)
605{
606 struct rtl8187_priv *priv = dev->priv;
607 u8 reg;
608 int res;
609
610 /* reset */
611 rtl818x_iowrite8(priv, &priv->map->EEPROM_CMD,
612 RTL818X_EEPROM_CMD_CONFIG);
613 reg = rtl818x_ioread8(priv, &priv->map->CONFIG3);
614 rtl818x_iowrite8(priv, &priv->map->CONFIG3, reg |
615 RTL818X_CONFIG3_ANAPARAM_WRITE);
4ece16a1
HRK		 616 rtl818x_iowrite32(priv, &priv->map->ANAPARAM,
617 RTL8187_RTL8225_ANAPARAM_ON);
618 rtl818x_iowrite32(priv, &priv->map->ANAPARAM2,
619 RTL8187_RTL8225_ANAPARAM2_ON);
f8a08c34
HTL		 620 rtl818x_iowrite8(priv, &priv->map->CONFIG3, reg &
621 ~RTL818X_CONFIG3_ANAPARAM_WRITE);
622 rtl818x_iowrite8(priv, &priv->map->EEPROM_CMD,
623 RTL818X_EEPROM_CMD_NORMAL);
624
625 rtl818x_iowrite16(priv, &priv->map->INT_MASK, 0);
626
627 msleep(200);
628 rtl818x_iowrite8(priv, (u8 *)0xFE18, 0x10);
629 rtl818x_iowrite8(priv, (u8 *)0xFE18, 0x11);
630 rtl818x_iowrite8(priv, (u8 *)0xFE18, 0x00);
631 msleep(200);
632
633 res = rtl8187_cmd_reset(dev);
634 if (res)
635 return res;
636
605bebe2
MW		 637 rtl818x_iowrite8(priv, &priv->map->EEPROM_CMD, RTL818X_EEPROM_CMD_CONFIG);
638 reg = rtl818x_ioread8(priv, &priv->map->CONFIG3);
f8a08c34
HTL		 639 rtl818x_iowrite8(priv, &priv->map->CONFIG3,
640 reg | RTL818X_CONFIG3_ANAPARAM_WRITE);
4ece16a1
HRK		 641 rtl818x_iowrite32(priv, &priv->map->ANAPARAM,
642 RTL8187_RTL8225_ANAPARAM_ON);
643 rtl818x_iowrite32(priv, &priv->map->ANAPARAM2,
644 RTL8187_RTL8225_ANAPARAM2_ON);
f8a08c34
HTL		 645 rtl818x_iowrite8(priv, &priv->map->CONFIG3,
646 reg & ~RTL818X_CONFIG3_ANAPARAM_WRITE);
605bebe2
MW		 647 rtl818x_iowrite8(priv, &priv->map->EEPROM_CMD, RTL818X_EEPROM_CMD_NORMAL);
648
649 /* setup card */
650 rtl818x_iowrite16(priv, &priv->map->RFPinsSelect, 0);
651 rtl818x_iowrite8(priv, &priv->map->GPIO, 0);
652
653 rtl818x_iowrite16(priv, &priv->map->RFPinsSelect, (4 << 8));
654 rtl818x_iowrite8(priv, &priv->map->GPIO, 1);
655 rtl818x_iowrite8(priv, &priv->map->GP_ENABLE, 0);
656
657 rtl818x_iowrite8(priv, &priv->map->EEPROM_CMD, RTL818X_EEPROM_CMD_CONFIG);
605bebe2
MW		 658
659 rtl818x_iowrite16(priv, (__le16 *)0xFFF4, 0xFFFF);
660 reg = rtl818x_ioread8(priv, &priv->map->CONFIG1);
661 reg &= 0x3F;
662 reg |= 0x80;
663 rtl818x_iowrite8(priv, &priv->map->CONFIG1, reg);
664
665 rtl818x_iowrite8(priv, &priv->map->EEPROM_CMD, RTL818X_EEPROM_CMD_NORMAL);
666
667 rtl818x_iowrite32(priv, &priv->map->INT_TIMEOUT, 0);
668 rtl818x_iowrite8(priv, &priv->map->WPA_CONF, 0);
2f47690e 669 rtl818x_iowrite8(priv, &priv->map->RATE_FALLBACK, 0);
605bebe2
MW		 670
671 // TODO: set RESP_RATE and BRSR properly
672 rtl818x_iowrite8(priv, &priv->map->RESP_RATE, (8 << 4) | 0);
673 rtl818x_iowrite16(priv, &priv->map->BRSR, 0x01F3);
674
675 /* host_usb_init */
676 rtl818x_iowrite16(priv, &priv->map->RFPinsSelect, 0);
677 rtl818x_iowrite8(priv, &priv->map->GPIO, 0);
678 reg = rtl818x_ioread8(priv, (u8 *)0xFE53);
679 rtl818x_iowrite8(priv, (u8 *)0xFE53, reg | (1 << 7));
680 rtl818x_iowrite16(priv, &priv->map->RFPinsSelect, (4 << 8));
681 rtl818x_iowrite8(priv, &priv->map->GPIO, 0x20);
682 rtl818x_iowrite8(priv, &priv->map->GP_ENABLE, 0);
683 rtl818x_iowrite16(priv, &priv->map->RFPinsOutput, 0x80);
684 rtl818x_iowrite16(priv, &priv->map->RFPinsSelect, 0x80);
685 rtl818x_iowrite16(priv, &priv->map->RFPinsEnable, 0x80);
686 msleep(100);
687
688 rtl818x_iowrite32(priv, &priv->map->RF_TIMING, 0x000a8008);
689 rtl818x_iowrite16(priv, &priv->map->BRSR, 0xFFFF);
690 rtl818x_iowrite32(priv, &priv->map->RF_PARA, 0x00100044);
f8a08c34
HTL		 691 rtl818x_iowrite8(priv, &priv->map->EEPROM_CMD,
692 RTL818X_EEPROM_CMD_CONFIG);
605bebe2 693 rtl818x_iowrite8(priv, &priv->map->CONFIG3, 0x44);
f8a08c34
HTL		 694 rtl818x_iowrite8(priv, &priv->map->EEPROM_CMD,
695 RTL818X_EEPROM_CMD_NORMAL);
605bebe2
MW		 696 rtl818x_iowrite16(priv, &priv->map->RFPinsEnable, 0x1FF7);
697 msleep(100);
698
f6532111 699 priv->rf->init(dev);
605bebe2
MW		 700
701 rtl818x_iowrite16(priv, &priv->map->BRSR, 0x01F3);
f6532111
MW		 702 reg = rtl818x_ioread8(priv, &priv->map->PGSELECT) & ~1;
703 rtl818x_iowrite8(priv, &priv->map->PGSELECT, reg | 1);
605bebe2
MW		 704 rtl818x_iowrite16(priv, (__le16 *)0xFFFE, 0x10);
705 rtl818x_iowrite8(priv, &priv->map->TALLY_SEL, 0x80);
706 rtl818x_iowrite8(priv, (u8 *)0xFFFF, 0x60);
f6532111 707 rtl818x_iowrite8(priv, &priv->map->PGSELECT, reg);
605bebe2
MW		 708
709 return 0;
710}
711
f8a08c34
HTL		 712static const u8 rtl8187b_reg_table[][3] = {
713 {0xF0, 0x32, 0}, {0xF1, 0x32, 0}, {0xF2, 0x00, 0}, {0xF3, 0x00, 0},
714 {0xF4, 0x32, 0}, {0xF5, 0x43, 0}, {0xF6, 0x00, 0}, {0xF7, 0x00, 0},
715 {0xF8, 0x46, 0}, {0xF9, 0xA4, 0}, {0xFA, 0x00, 0}, {0xFB, 0x00, 0},
716 {0xFC, 0x96, 0}, {0xFD, 0xA4, 0}, {0xFE, 0x00, 0}, {0xFF, 0x00, 0},
717
718 {0x58, 0x4B, 1}, {0x59, 0x00, 1}, {0x5A, 0x4B, 1}, {0x5B, 0x00, 1},
719 {0x60, 0x4B, 1}, {0x61, 0x09, 1}, {0x62, 0x4B, 1}, {0x63, 0x09, 1},
720 {0xCE, 0x0F, 1}, {0xCF, 0x00, 1}, {0xE0, 0xFF, 1}, {0xE1, 0x0F, 1},
721 {0xE2, 0x00, 1}, {0xF0, 0x4E, 1}, {0xF1, 0x01, 1}, {0xF2, 0x02, 1},
722 {0xF3, 0x03, 1}, {0xF4, 0x04, 1}, {0xF5, 0x05, 1}, {0xF6, 0x06, 1},
723 {0xF7, 0x07, 1}, {0xF8, 0x08, 1},
724
725 {0x4E, 0x00, 2}, {0x0C, 0x04, 2}, {0x21, 0x61, 2}, {0x22, 0x68, 2},
726 {0x23, 0x6F, 2}, {0x24, 0x76, 2}, {0x25, 0x7D, 2}, {0x26, 0x84, 2},
727 {0x27, 0x8D, 2}, {0x4D, 0x08, 2}, {0x50, 0x05, 2}, {0x51, 0xF5, 2},
728 {0x52, 0x04, 2}, {0x53, 0xA0, 2}, {0x54, 0x1F, 2}, {0x55, 0x23, 2},
729 {0x56, 0x45, 2}, {0x57, 0x67, 2}, {0x58, 0x08, 2}, {0x59, 0x08, 2},
730 {0x5A, 0x08, 2}, {0x5B, 0x08, 2}, {0x60, 0x08, 2}, {0x61, 0x08, 2},
731 {0x62, 0x08, 2}, {0x63, 0x08, 2}, {0x64, 0xCF, 2}, {0x72, 0x56, 2},
732 {0x73, 0x9A, 2},
733
734 {0x34, 0xF0, 0}, {0x35, 0x0F, 0}, {0x5B, 0x40, 0}, {0x84, 0x88, 0},
735 {0x85, 0x24, 0}, {0x88, 0x54, 0}, {0x8B, 0xB8, 0}, {0x8C, 0x07, 0},
736 {0x8D, 0x00, 0}, {0x94, 0x1B, 0}, {0x95, 0x12, 0}, {0x96, 0x00, 0},
737 {0x97, 0x06, 0}, {0x9D, 0x1A, 0}, {0x9F, 0x10, 0}, {0xB4, 0x22, 0},
a027087a 738 {0xBE, 0x80, 0}, {0xDB, 0x00, 0}, {0xEE, 0x00, 0}, {0x4C, 0x00, 2},
f8a08c34 739
a027087a
LF		 740 {0x9F, 0x00, 3}, {0x8C, 0x01, 0}, {0x8D, 0x10, 0}, {0x8E, 0x08, 0},
741 {0x8F, 0x00, 0}
f8a08c34
HTL		 742};
743
744static int rtl8187b_init_hw(struct ieee80211_hw *dev)
745{
746 struct rtl8187_priv *priv = dev->priv;
747 int res, i;
748 u8 reg;
749
750 rtl818x_iowrite8(priv, &priv->map->EEPROM_CMD,
751 RTL818X_EEPROM_CMD_CONFIG);
752
753 reg = rtl818x_ioread8(priv, &priv->map->CONFIG3);
754 reg |= RTL818X_CONFIG3_ANAPARAM_WRITE | RTL818X_CONFIG3_GNT_SELECT;
755 rtl818x_iowrite8(priv, &priv->map->CONFIG3, reg);
4ece16a1
HRK		 756 rtl818x_iowrite32(priv, &priv->map->ANAPARAM2,
757 RTL8187B_RTL8225_ANAPARAM2_ON);
758 rtl818x_iowrite32(priv, &priv->map->ANAPARAM,
759 RTL8187B_RTL8225_ANAPARAM_ON);
760 rtl818x_iowrite8(priv, &priv->map->ANAPARAM3,
761 RTL8187B_RTL8225_ANAPARAM3_ON);
f8a08c34
HTL		 762
763 rtl818x_iowrite8(priv, (u8 *)0xFF61, 0x10);
764 reg = rtl818x_ioread8(priv, (u8 *)0xFF62);
765 rtl818x_iowrite8(priv, (u8 *)0xFF62, reg & ~(1 << 5));
766 rtl818x_iowrite8(priv, (u8 *)0xFF62, reg | (1 << 5));
767
768 reg = rtl818x_ioread8(priv, &priv->map->CONFIG3);
769 reg &= ~RTL818X_CONFIG3_ANAPARAM_WRITE;
770 rtl818x_iowrite8(priv, &priv->map->CONFIG3, reg);
771
772 rtl818x_iowrite8(priv, &priv->map->EEPROM_CMD,
773 RTL818X_EEPROM_CMD_NORMAL);
774
775 res = rtl8187_cmd_reset(dev);
776 if (res)
777 return res;
778
779 rtl818x_iowrite16(priv, (__le16 *)0xFF2D, 0x0FFF);
780 reg = rtl818x_ioread8(priv, &priv->map->CW_CONF);
781 reg |= RTL818X_CW_CONF_PERPACKET_RETRY_SHIFT;
782 rtl818x_iowrite8(priv, &priv->map->CW_CONF, reg);
783 reg = rtl818x_ioread8(priv, &priv->map->TX_AGC_CTL);
784 reg |= RTL818X_TX_AGC_CTL_PERPACKET_GAIN_SHIFT |
785 RTL818X_TX_AGC_CTL_PERPACKET_ANTSEL_SHIFT;
786 rtl818x_iowrite8(priv, &priv->map->TX_AGC_CTL, reg);
787
788 rtl818x_iowrite16_idx(priv, (__le16 *)0xFFE0, 0x0FFF, 1);
f8a08c34
HTL		 789
790 rtl818x_iowrite16(priv, &priv->map->BEACON_INTERVAL, 100);
791 rtl818x_iowrite16(priv, &priv->map->ATIM_WND, 2);
792 rtl818x_iowrite16_idx(priv, (__le16 *)0xFFD4, 0xFFFF, 1);
793
794 rtl818x_iowrite8(priv, &priv->map->EEPROM_CMD,
795 RTL818X_EEPROM_CMD_CONFIG);
796 reg = rtl818x_ioread8(priv, &priv->map->CONFIG1);
797 rtl818x_iowrite8(priv, &priv->map->CONFIG1, (reg & 0x3F) | 0x80);
798 rtl818x_iowrite8(priv, &priv->map->EEPROM_CMD,
799 RTL818X_EEPROM_CMD_NORMAL);
800
801 rtl818x_iowrite8(priv, &priv->map->WPA_CONF, 0);
802 for (i = 0; i < ARRAY_SIZE(rtl8187b_reg_table); i++) {
803 rtl818x_iowrite8_idx(priv,
804 (u8 *)(uintptr_t)
805 (rtl8187b_reg_table[i][0] | 0xFF00),
806 rtl8187b_reg_table[i][1],
807 rtl8187b_reg_table[i][2]);
808 }
809
810 rtl818x_iowrite16(priv, &priv->map->TID_AC_MAP, 0xFA50);
811 rtl818x_iowrite16(priv, &priv->map->INT_MIG, 0);
812
813 rtl818x_iowrite32_idx(priv, (__le32 *)0xFFF0, 0, 1);
814 rtl818x_iowrite32_idx(priv, (__le32 *)0xFFF4, 0, 1);
815 rtl818x_iowrite8_idx(priv, (u8 *)0xFFF8, 0, 1);
816
817 rtl818x_iowrite32(priv, &priv->map->RF_TIMING, 0x00004001);
818
819 rtl818x_iowrite16_idx(priv, (__le16 *)0xFF72, 0x569A, 2);
820
821 rtl818x_iowrite8(priv, &priv->map->EEPROM_CMD,
822 RTL818X_EEPROM_CMD_CONFIG);
823 reg = rtl818x_ioread8(priv, &priv->map->CONFIG3);
824 reg |= RTL818X_CONFIG3_ANAPARAM_WRITE;
825 rtl818x_iowrite8(priv, &priv->map->CONFIG3, reg);
826 rtl818x_iowrite8(priv, &priv->map->EEPROM_CMD,
827 RTL818X_EEPROM_CMD_NORMAL);
828
829 rtl818x_iowrite16(priv, &priv->map->RFPinsOutput, 0x0480);
830 rtl818x_iowrite16(priv, &priv->map->RFPinsSelect, 0x2488);
831 rtl818x_iowrite16(priv, &priv->map->RFPinsEnable, 0x1FFF);
2f20596b 832 msleep(100);
f8a08c34
HTL		 833
834 priv->rf->init(dev);
835
836 reg = RTL818X_CMD_TX_ENABLE | RTL818X_CMD_RX_ENABLE;
837 rtl818x_iowrite8(priv, &priv->map->CMD, reg);
838 rtl818x_iowrite16(priv, &priv->map->INT_MASK, 0xFFFF);
839
840 rtl818x_iowrite8(priv, (u8 *)0xFE41, 0xF4);
841 rtl818x_iowrite8(priv, (u8 *)0xFE40, 0x00);
842 rtl818x_iowrite8(priv, (u8 *)0xFE42, 0x00);
843 rtl818x_iowrite8(priv, (u8 *)0xFE42, 0x01);
844 rtl818x_iowrite8(priv, (u8 *)0xFE40, 0x0F);
845 rtl818x_iowrite8(priv, (u8 *)0xFE42, 0x00);
846 rtl818x_iowrite8(priv, (u8 *)0xFE42, 0x01);
847
848 reg = rtl818x_ioread8(priv, (u8 *)0xFFDB);
849 rtl818x_iowrite8(priv, (u8 *)0xFFDB, reg | (1 << 2));
850 rtl818x_iowrite16_idx(priv, (__le16 *)0xFF72, 0x59FA, 3);
851 rtl818x_iowrite16_idx(priv, (__le16 *)0xFF74, 0x59D2, 3);
852 rtl818x_iowrite16_idx(priv, (__le16 *)0xFF76, 0x59D2, 3);
853 rtl818x_iowrite16_idx(priv, (__le16 *)0xFF78, 0x19FA, 3);
854 rtl818x_iowrite16_idx(priv, (__le16 *)0xFF7A, 0x19FA, 3);
855 rtl818x_iowrite16_idx(priv, (__le16 *)0xFF7C, 0x00D0, 3);
856 rtl818x_iowrite8(priv, (u8 *)0xFF61, 0);
857 rtl818x_iowrite8_idx(priv, (u8 *)0xFF80, 0x0F, 1);
858 rtl818x_iowrite8_idx(priv, (u8 *)0xFF83, 0x03, 1);
859 rtl818x_iowrite8(priv, (u8 *)0xFFDA, 0x10);
860 rtl818x_iowrite8_idx(priv, (u8 *)0xFF4D, 0x08, 2);
861
862 rtl818x_iowrite32(priv, &priv->map->HSSI_PARA, 0x0600321B);
863
864 rtl818x_iowrite16_idx(priv, (__le16 *)0xFFEC, 0x0800, 1);
865
b4572a92
HRK		 866 priv->slot_time = 0x9;
867 priv->aifsn[0] = 2; /* AIFSN[AC_VO] */
868 priv->aifsn[1] = 2; /* AIFSN[AC_VI] */
869 priv->aifsn[2] = 7; /* AIFSN[AC_BK] */
870 priv->aifsn[3] = 3; /* AIFSN[AC_BE] */
871 rtl818x_iowrite8(priv, &priv->map->ACM_CONTROL, 0);
872
f8a08c34
HTL		 873 return 0;
874}
875
2f47690e
LF		 876static void rtl8187_work(struct work_struct *work)
877{
878 /* The RTL8187 returns the retry count through register 0xFFFA. In
879 * addition, it appears to be a cumulative retry count, not the
880 * value for the current TX packet. When multiple TX entries are
881 * queued, the retry count will be valid for the last one in the queue.
882 * The "error" should not matter for purposes of rate setting. */
883 struct rtl8187_priv *priv = container_of(work, struct rtl8187_priv,
884 work.work);
885 struct ieee80211_tx_info *info;
886 struct ieee80211_hw *dev = priv->dev;
887 static u16 retry;
888 u16 tmp;
889
890 mutex_lock(&priv->conf_mutex);
891 tmp = rtl818x_ioread16(priv, (__le16 *)0xFFFA);
892 while (skb_queue_len(&priv->b_tx_status.queue) > 0) {
893 struct sk_buff *old_skb;
894
895 old_skb = skb_dequeue(&priv->b_tx_status.queue);
896 info = IEEE80211_SKB_CB(old_skb);
897 info->status.rates[0].count = tmp - retry + 1;
898 ieee80211_tx_status_irqsafe(dev, old_skb);
899 }
900 retry = tmp;
901 mutex_unlock(&priv->conf_mutex);
902}
903
4150c572 904static int rtl8187_start(struct ieee80211_hw *dev)
605bebe2
MW		 905{
906 struct rtl8187_priv *priv = dev->priv;
907 u32 reg;
908 int ret;
909
f8a08c34
HTL		 910 ret = (!priv->is_rtl8187b) ? rtl8187_init_hw(dev) :
911 rtl8187b_init_hw(dev);
605bebe2
MW		 912 if (ret)
913 return ret;
914
7dcdd073 915 mutex_lock(&priv->conf_mutex);
c1db52b9
LF		 916
917 init_usb_anchor(&priv->anchored);
2f47690e 918 priv->dev = dev;
c1db52b9 919
f8a08c34
HTL		 920 if (priv->is_rtl8187b) {
921 reg = RTL818X_RX_CONF_MGMT |
922 RTL818X_RX_CONF_DATA |
923 RTL818X_RX_CONF_BROADCAST |
924 RTL818X_RX_CONF_NICMAC |
925 RTL818X_RX_CONF_BSSID |
926 (7 << 13 /* RX FIFO threshold NONE */) |
927 (7 << 10 /* MAX RX DMA */) |
928 RTL818X_RX_CONF_RX_AUTORESETPHY |
929 RTL818X_RX_CONF_ONLYERLPKT |
930 RTL818X_RX_CONF_MULTICAST;
931 priv->rx_conf = reg;
932 rtl818x_iowrite32(priv, &priv->map->RX_CONF, reg);
933
934 rtl818x_iowrite32(priv, &priv->map->TX_CONF,
935 RTL818X_TX_CONF_HW_SEQNUM |
936 RTL818X_TX_CONF_DISREQQSIZE |
937 (7 << 8 /* short retry limit */) |
938 (7 << 0 /* long retry limit */) |
939 (7 << 21 /* MAX TX DMA */));
940 rtl8187_init_urbs(dev);
3517afde 941 rtl8187b_init_status_urb(dev);
7dcdd073 942 mutex_unlock(&priv->conf_mutex);
f8a08c34
HTL		 943 return 0;
944 }
945
605bebe2
MW		 946 rtl818x_iowrite16(priv, &priv->map->INT_MASK, 0xFFFF);
947
2fe14263
MW		 948 rtl818x_iowrite32(priv, &priv->map->MAR[0], ~0);
949 rtl818x_iowrite32(priv, &priv->map->MAR[1], ~0);
950
605bebe2
MW		 951 rtl8187_init_urbs(dev);
952
953 reg = RTL818X_RX_CONF_ONLYERLPKT |
954 RTL818X_RX_CONF_RX_AUTORESETPHY |
955 RTL818X_RX_CONF_BSSID |
956 RTL818X_RX_CONF_MGMT |
605bebe2
MW		 957 RTL818X_RX_CONF_DATA |
958 (7 << 13 /* RX FIFO threshold NONE */) |
959 (7 << 10 /* MAX RX DMA */) |
960 RTL818X_RX_CONF_BROADCAST |
605bebe2 961 RTL818X_RX_CONF_NICMAC;
605bebe2 962
4150c572 963 priv->rx_conf = reg;
605bebe2
MW		 964 rtl818x_iowrite32(priv, &priv->map->RX_CONF, reg);
965
966 reg = rtl818x_ioread8(priv, &priv->map->CW_CONF);
967 reg &= ~RTL818X_CW_CONF_PERPACKET_CW_SHIFT;
968 reg |= RTL818X_CW_CONF_PERPACKET_RETRY_SHIFT;
969 rtl818x_iowrite8(priv, &priv->map->CW_CONF, reg);
970
971 reg = rtl818x_ioread8(priv, &priv->map->TX_AGC_CTL);
972 reg &= ~RTL818X_TX_AGC_CTL_PERPACKET_GAIN_SHIFT;
973 reg &= ~RTL818X_TX_AGC_CTL_PERPACKET_ANTSEL_SHIFT;
974 reg &= ~RTL818X_TX_AGC_CTL_FEEDBACK_ANT;
975 rtl818x_iowrite8(priv, &priv->map->TX_AGC_CTL, reg);
976
977 reg = RTL818X_TX_CONF_CW_MIN |
978 (7 << 21 /* MAX TX DMA */) |
979 RTL818X_TX_CONF_NO_ICV;
980 rtl818x_iowrite32(priv, &priv->map->TX_CONF, reg);
981
982 reg = rtl818x_ioread8(priv, &priv->map->CMD);
983 reg |= RTL818X_CMD_TX_ENABLE;
984 reg |= RTL818X_CMD_RX_ENABLE;
985 rtl818x_iowrite8(priv, &priv->map->CMD, reg);
2f47690e 986 INIT_DELAYED_WORK(&priv->work, rtl8187_work);
7dcdd073 987 mutex_unlock(&priv->conf_mutex);
605bebe2
MW		 988
989 return 0;
990}
991
4150c572 992static void rtl8187_stop(struct ieee80211_hw *dev)
605bebe2
MW		 993{
994 struct rtl8187_priv *priv = dev->priv;
605bebe2
MW		 995 struct sk_buff *skb;
996 u32 reg;
997
7dcdd073 998 mutex_lock(&priv->conf_mutex);
605bebe2
MW		 999 rtl818x_iowrite16(priv, &priv->map->INT_MASK, 0);
1000
1001 reg = rtl818x_ioread8(priv, &priv->map->CMD);
1002 reg &= ~RTL818X_CMD_TX_ENABLE;
1003 reg &= ~RTL818X_CMD_RX_ENABLE;
1004 rtl818x_iowrite8(priv, &priv->map->CMD, reg);
1005
f6532111 1006 priv->rf->stop(dev);
605bebe2
MW		 1007
1008 rtl818x_iowrite8(priv, &priv->map->EEPROM_CMD, RTL818X_EEPROM_CMD_CONFIG);
1009 reg = rtl818x_ioread8(priv, &priv->map->CONFIG4);
1010 rtl818x_iowrite8(priv, &priv->map->CONFIG4, reg | RTL818X_CONFIG4_VCOOFF);
1011 rtl818x_iowrite8(priv, &priv->map->EEPROM_CMD, RTL818X_EEPROM_CMD_NORMAL);
1012
3517afde
HRK		 1013 while ((skb = skb_dequeue(&priv->b_tx_status.queue)))
1014 dev_kfree_skb_any(skb);
c1db52b9
LF		 1015
1016 usb_kill_anchored_urbs(&priv->anchored);
2f47690e
LF		 1017 if (!priv->is_rtl8187b)
1018 cancel_delayed_work_sync(&priv->work);
7dcdd073 1019 mutex_unlock(&priv->conf_mutex);
605bebe2
MW		 1020}
1021
1022static int rtl8187_add_interface(struct ieee80211_hw *dev,
1023 struct ieee80211_if_init_conf *conf)
1024{
1025 struct rtl8187_priv *priv = dev->priv;
4150c572 1026 int i;
66aafd9a 1027 int ret = -EOPNOTSUPP;
605bebe2 1028
66aafd9a 1029 mutex_lock(&priv->conf_mutex);
05c914fe 1030 if (priv->mode != NL80211_IFTYPE_MONITOR)
66aafd9a 1031 goto exit;
605bebe2
MW		 1032
1033 switch (conf->type) {
05c914fe 1034 case NL80211_IFTYPE_STATION:
605bebe2
MW		 1035 priv->mode = conf->type;
1036 break;
1037 default:
66aafd9a 1038 goto exit;
605bebe2
MW		 1039 }
1040
66aafd9a 1041 ret = 0;
aa979a6a
HRK		 1042 priv->vif = conf->vif;
1043
4150c572
JB		 1044 rtl818x_iowrite8(priv, &priv->map->EEPROM_CMD, RTL818X_EEPROM_CMD_CONFIG);
1045 for (i = 0; i < ETH_ALEN; i++)
1046 rtl818x_iowrite8(priv, &priv->map->MAC[i],
1047 ((u8 *)conf->mac_addr)[i]);
1048 rtl818x_iowrite8(priv, &priv->map->EEPROM_CMD, RTL818X_EEPROM_CMD_NORMAL);
605bebe2 1049
66aafd9a 1050exit:
7dcdd073 1051 mutex_unlock(&priv->conf_mutex);
66aafd9a 1052 return ret;
605bebe2
MW		 1053}
1054
1055static void rtl8187_remove_interface(struct ieee80211_hw *dev,
1056 struct ieee80211_if_init_conf *conf)
1057{
1058 struct rtl8187_priv *priv = dev->priv;
7dcdd073 1059 mutex_lock(&priv->conf_mutex);
05c914fe 1060 priv->mode = NL80211_IFTYPE_MONITOR;
aa979a6a 1061 priv->vif = NULL;
7dcdd073 1062 mutex_unlock(&priv->conf_mutex);
605bebe2
MW		 1063}
1064
e8975581 1065static int rtl8187_config(struct ieee80211_hw *dev, u32 changed)
605bebe2
MW		 1066{
1067 struct rtl8187_priv *priv = dev->priv;
e8975581 1068 struct ieee80211_conf *conf = &dev->conf;
f6532111
MW		 1069 u32 reg;
1070
7dcdd073 1071 mutex_lock(&priv->conf_mutex);
f6532111
MW		 1072 reg = rtl818x_ioread32(priv, &priv->map->TX_CONF);
1073 /* Enable TX loopback on MAC level to avoid TX during channel
1074 * changes, as this has be seen to causes problems and the
1075 * card will stop work until next reset
1076 */
1077 rtl818x_iowrite32(priv, &priv->map->TX_CONF,
1078 reg | RTL818X_TX_CONF_LOOPBACK_MAC);
f6532111
MW		 1079 priv->rf->set_chan(dev, conf);
1080 msleep(10);
1081 rtl818x_iowrite32(priv, &priv->map->TX_CONF, reg);
605bebe2 1082
605bebe2
MW		 1083 rtl818x_iowrite16(priv, &priv->map->ATIM_WND, 2);
1084 rtl818x_iowrite16(priv, &priv->map->ATIMTR_INTERVAL, 100);
1085 rtl818x_iowrite16(priv, &priv->map->BEACON_INTERVAL, 100);
1086 rtl818x_iowrite16(priv, &priv->map->BEACON_INTERVAL_TIME, 100);
7dcdd073 1087 mutex_unlock(&priv->conf_mutex);
605bebe2
MW		 1088 return 0;
1089}
1090
b4572a92
HRK		 1091/*
1092 * With 8187B, AC_*_PARAM clashes with FEMR definition in struct rtl818x_csr for
1093 * example. Thus we have to use raw values for AC_*_PARAM register addresses.
1094 */
1095static __le32 *rtl8187b_ac_addr[4] = {
1096 (__le32 *) 0xFFF0, /* AC_VO */
1097 (__le32 *) 0xFFF4, /* AC_VI */
1098 (__le32 *) 0xFFFC, /* AC_BK */
1099 (__le32 *) 0xFFF8, /* AC_BE */
1100};
1101
1102#define SIFS_TIME 0xa
1103
f8288317
HRK		 1104static void rtl8187_conf_erp(struct rtl8187_priv *priv, bool use_short_slot,
1105 bool use_short_preamble)
64761077 1106{
f8288317 1107 if (priv->is_rtl8187b) {
b4572a92 1108 u8 difs, eifs;
f8288317 1109 u16 ack_timeout;
b4572a92 1110 int queue;
f8288317
HRK		 1111
1112 if (use_short_slot) {
b4572a92 1113 priv->slot_time = 0x9;
f8288317
HRK		 1114 difs = 0x1c;
1115 eifs = 0x53;
1116 } else {
b4572a92 1117 priv->slot_time = 0x14;
f8288317
HRK		 1118 difs = 0x32;
1119 eifs = 0x5b;
1120 }
54ac218a 1121 rtl818x_iowrite8(priv, &priv->map->SIFS, 0x22);
b4572a92 1122 rtl818x_iowrite8(priv, &priv->map->SLOT, priv->slot_time);
f8288317
HRK		 1123 rtl818x_iowrite8(priv, &priv->map->DIFS, difs);
1124
1125 /*
1126 * BRSR+1 on 8187B is in fact EIFS register
1127 * Value in units of 4 us
1128 */
1129 rtl818x_iowrite8(priv, (u8 *)&priv->map->BRSR + 1, eifs);
1130
1131 /*
1132 * For 8187B, CARRIER_SENSE_COUNTER is in fact ack timeout
1133 * register. In units of 4 us like eifs register
1134 * ack_timeout = ack duration + plcp + difs + preamble
1135 */
1136 ack_timeout = 112 + 48 + difs;
1137 if (use_short_preamble)
1138 ack_timeout += 72;
1139 else
1140 ack_timeout += 144;
1141 rtl818x_iowrite8(priv, &priv->map->CARRIER_SENSE_COUNTER,
1142 DIV_ROUND_UP(ack_timeout, 4));
b4572a92
HRK		 1143
1144 for (queue = 0; queue < 4; queue++)
1145 rtl818x_iowrite8(priv, (u8 *) rtl8187b_ac_addr[queue],
1146 priv->aifsn[queue] * priv->slot_time +
1147 SIFS_TIME);
f8288317 1148 } else {
64761077
HRK		 1149 rtl818x_iowrite8(priv, &priv->map->SIFS, 0x22);
1150 if (use_short_slot) {
1151 rtl818x_iowrite8(priv, &priv->map->SLOT, 0x9);
1152 rtl818x_iowrite8(priv, &priv->map->DIFS, 0x14);
1153 rtl818x_iowrite8(priv, &priv->map->EIFS, 91 - 0x14);
64761077
HRK		 1154 } else {
1155 rtl818x_iowrite8(priv, &priv->map->SLOT, 0x14);
1156 rtl818x_iowrite8(priv, &priv->map->DIFS, 0x24);
1157 rtl818x_iowrite8(priv, &priv->map->EIFS, 91 - 0x24);
64761077
HRK		 1158 }
1159 }
1160}
1161
1162static void rtl8187_bss_info_changed(struct ieee80211_hw *dev,
1163 struct ieee80211_vif *vif,
1164 struct ieee80211_bss_conf *info,
1165 u32 changed)
1166{
1167 struct rtl8187_priv *priv = dev->priv;
2d0ddec5
JB		 1168 int i;
1169 u8 reg;
1170
1171 if (changed & BSS_CHANGED_BSSID) {
1172 mutex_lock(&priv->conf_mutex);
1173 for (i = 0; i < ETH_ALEN; i++)
1174 rtl818x_iowrite8(priv, &priv->map->BSSID[i],
1175 info->bssid[i]);
1176
1177 if (is_valid_ether_addr(info->bssid)) {
1178 reg = RTL818X_MSR_INFRA;
1179 if (priv->is_rtl8187b)
1180 reg |= RTL818X_MSR_ENEDCA;
1181 rtl818x_iowrite8(priv, &priv->map->MSR, reg);
1182 } else {
1183 reg = RTL818X_MSR_NO_LINK;
1184 rtl818x_iowrite8(priv, &priv->map->MSR, reg);
1185 }
1186
1187 mutex_unlock(&priv->conf_mutex);
1188 }
64761077 1189
f8288317
HRK		 1190 if (changed & (BSS_CHANGED_ERP_SLOT | BSS_CHANGED_ERP_PREAMBLE))
1191 rtl8187_conf_erp(priv, info->use_short_slot,
1192 info->use_short_preamble);
64761077
HRK		 1193}
1194
3ac64bee
JB		 1195static u64 rtl8187_prepare_multicast(struct ieee80211_hw *dev,
1196 int mc_count, struct dev_addr_list *mc_list)
1197{
1198 return mc_count;
1199}
1200
4150c572
JB		 1201static void rtl8187_configure_filter(struct ieee80211_hw *dev,
1202 unsigned int changed_flags,
1203 unsigned int *total_flags,
3ac64bee 1204 u64 multicast)
4150c572
JB		 1205{
1206 struct rtl8187_priv *priv = dev->priv;
1207
4150c572
JB		 1208 if (changed_flags & FIF_FCSFAIL)
1209 priv->rx_conf ^= RTL818X_RX_CONF_FCS;
1210 if (changed_flags & FIF_CONTROL)
1211 priv->rx_conf ^= RTL818X_RX_CONF_CTRL;
1212 if (changed_flags & FIF_OTHER_BSS)
1213 priv->rx_conf ^= RTL818X_RX_CONF_MONITOR;
3ac64bee 1214 if (*total_flags & FIF_ALLMULTI || multicast > 0)
4150c572 1215 priv->rx_conf |= RTL818X_RX_CONF_MULTICAST;
2fe14263
MW		 1216 else
1217 priv->rx_conf &= ~RTL818X_RX_CONF_MULTICAST;
1218
1219 *total_flags = 0;
4150c572 1220
4150c572
JB		 1221 if (priv->rx_conf & RTL818X_RX_CONF_FCS)
1222 *total_flags |= FIF_FCSFAIL;
1223 if (priv->rx_conf & RTL818X_RX_CONF_CTRL)
1224 *total_flags |= FIF_CONTROL;
1225 if (priv->rx_conf & RTL818X_RX_CONF_MONITOR)
1226 *total_flags |= FIF_OTHER_BSS;
2fe14263
MW		 1227 if (priv->rx_conf & RTL818X_RX_CONF_MULTICAST)
1228 *total_flags |= FIF_ALLMULTI;
4150c572
JB		 1229
1230 rtl818x_iowrite32_async(priv, &priv->map->RX_CONF, priv->rx_conf);
1231}
1232
b4572a92
HRK		 1233static int rtl8187_conf_tx(struct ieee80211_hw *dev, u16 queue,
1234 const struct ieee80211_tx_queue_params *params)
1235{
1236 struct rtl8187_priv *priv = dev->priv;
1237 u8 cw_min, cw_max;
1238
1239 if (queue > 3)
1240 return -EINVAL;
1241
1242 cw_min = fls(params->cw_min);
1243 cw_max = fls(params->cw_max);
1244
1245 if (priv->is_rtl8187b) {
1246 priv->aifsn[queue] = params->aifs;
1247
1248 /*
1249 * This is the structure of AC_*_PARAM registers in 8187B:
1250 * - TXOP limit field, bit offset = 16
1251 * - ECWmax, bit offset = 12
1252 * - ECWmin, bit offset = 8
1253 * - AIFS, bit offset = 0
1254 */
1255 rtl818x_iowrite32(priv, rtl8187b_ac_addr[queue],
1256 (params->txop << 16) | (cw_max << 12) |
1257 (cw_min << 8) | (params->aifs *
1258 priv->slot_time + SIFS_TIME));
1259 } else {
1260 if (queue != 0)
1261 return -EINVAL;
1262
1263 rtl818x_iowrite8(priv, &priv->map->CW_VAL,
1264 cw_min | (cw_max << 4));
1265 }
1266 return 0;
1267}
1268
605bebe2
MW		 1269static const struct ieee80211_ops rtl8187_ops = {
1270 .tx = rtl8187_tx,
4150c572 1271 .start = rtl8187_start,
605bebe2
MW		 1272 .stop = rtl8187_stop,
1273 .add_interface = rtl8187_add_interface,
1274 .remove_interface = rtl8187_remove_interface,
1275 .config = rtl8187_config,
64761077 1276 .bss_info_changed = rtl8187_bss_info_changed,
3ac64bee 1277 .prepare_multicast = rtl8187_prepare_multicast,
4150c572 1278 .configure_filter = rtl8187_configure_filter,
b4572a92 1279 .conf_tx = rtl8187_conf_tx
605bebe2
MW		 1280};
1281
1282static void rtl8187_eeprom_register_read(struct eeprom_93cx6 *eeprom)
1283{
1284 struct ieee80211_hw *dev = eeprom->data;
1285 struct rtl8187_priv *priv = dev->priv;
1286 u8 reg = rtl818x_ioread8(priv, &priv->map->EEPROM_CMD);
1287
1288 eeprom->reg_data_in = reg & RTL818X_EEPROM_CMD_WRITE;
1289 eeprom->reg_data_out = reg & RTL818X_EEPROM_CMD_READ;
1290 eeprom->reg_data_clock = reg & RTL818X_EEPROM_CMD_CK;
1291 eeprom->reg_chip_select = reg & RTL818X_EEPROM_CMD_CS;
1292}
1293
1294static void rtl8187_eeprom_register_write(struct eeprom_93cx6 *eeprom)
1295{
1296 struct ieee80211_hw *dev = eeprom->data;
1297 struct rtl8187_priv *priv = dev->priv;
1298 u8 reg = RTL818X_EEPROM_CMD_PROGRAM;
1299
1300 if (eeprom->reg_data_in)
1301 reg |= RTL818X_EEPROM_CMD_WRITE;
1302 if (eeprom->reg_data_out)
1303 reg |= RTL818X_EEPROM_CMD_READ;
1304 if (eeprom->reg_data_clock)
1305 reg |= RTL818X_EEPROM_CMD_CK;
1306 if (eeprom->reg_chip_select)
1307 reg |= RTL818X_EEPROM_CMD_CS;
1308
1309 rtl818x_iowrite8(priv, &priv->map->EEPROM_CMD, reg);
1310 udelay(10);
1311}
1312
1313static int __devinit rtl8187_probe(struct usb_interface *intf,
1314 const struct usb_device_id *id)
1315{
1316 struct usb_device *udev = interface_to_usbdev(intf);
1317 struct ieee80211_hw *dev;
1318 struct rtl8187_priv *priv;
1319 struct eeprom_93cx6 eeprom;
1320 struct ieee80211_channel *channel;
6f7853f3 1321 const char *chip_name;
605bebe2
MW		 1322 u16 txpwr, reg;
1323 int err, i;
1324
1325 dev = ieee80211_alloc_hw(sizeof(*priv), &rtl8187_ops);
1326 if (!dev) {
1327 printk(KERN_ERR "rtl8187: ieee80211 alloc failed\n");
1328 return -ENOMEM;
1329 }
1330
1331 priv = dev->priv;
0e25b4ef 1332 priv->is_rtl8187b = (id->driver_info == DEVICE_RTL8187B);
605bebe2 1333
9be6f0d4
JL		 1334 /* allocate "DMA aware" buffer for register accesses */
1335 priv->io_dmabuf = kmalloc(sizeof(*priv->io_dmabuf), GFP_KERNEL);
1336 if (!priv->io_dmabuf) {
1337 err = -ENOMEM;
1338 goto err_free_dev;
1339 }
1340 mutex_init(&priv->io_mutex);
1341
605bebe2
MW		 1342 SET_IEEE80211_DEV(dev, &intf->dev);
1343 usb_set_intfdata(intf, dev);
1344 priv->udev = udev;
1345
1346 usb_get_dev(udev);
1347
1348 skb_queue_head_init(&priv->rx_queue);
8318d78a
JB		 1349
1350 BUILD_BUG_ON(sizeof(priv->channels) != sizeof(rtl818x_channels));
1351 BUILD_BUG_ON(sizeof(priv->rates) != sizeof(rtl818x_rates));
1352
605bebe2
MW		 1353 memcpy(priv->channels, rtl818x_channels, sizeof(rtl818x_channels));
1354 memcpy(priv->rates, rtl818x_rates, sizeof(rtl818x_rates));
1355 priv->map = (struct rtl818x_csr *)0xFF00;
8318d78a
JB		 1356
1357 priv->band.band = IEEE80211_BAND_2GHZ;
1358 priv->band.channels = priv->channels;
1359 priv->band.n_channels = ARRAY_SIZE(rtl818x_channels);
1360 priv->band.bitrates = priv->rates;
1361 priv->band.n_bitrates = ARRAY_SIZE(rtl818x_rates);
1362 dev->wiphy->bands[IEEE80211_BAND_2GHZ] = &priv->band;
1363
1364
05c914fe 1365 priv->mode = NL80211_IFTYPE_MONITOR;
605bebe2 1366 dev->flags = IEEE80211_HW_HOST_BROADCAST_PS_BUFFERING |
a7db74f4 1367 IEEE80211_HW_SIGNAL_DBM |
0ccd58fc 1368 IEEE80211_HW_RX_INCLUDES_FCS;
605bebe2 1369
605bebe2
MW		 1370 eeprom.data = dev;
1371 eeprom.register_read = rtl8187_eeprom_register_read;
1372 eeprom.register_write = rtl8187_eeprom_register_write;
1373 if (rtl818x_ioread32(priv, &priv->map->RX_CONF) & (1 << 6))
1374 eeprom.width = PCI_EEPROM_WIDTH_93C66;
1375 else
1376 eeprom.width = PCI_EEPROM_WIDTH_93C46;
1377
1378 rtl818x_iowrite8(priv, &priv->map->EEPROM_CMD, RTL818X_EEPROM_CMD_CONFIG);
1379 udelay(10);
1380
1381 eeprom_93cx6_multiread(&eeprom, RTL8187_EEPROM_MAC_ADDR,
1382 (__le16 __force *)dev->wiphy->perm_addr, 3);
1383 if (!is_valid_ether_addr(dev->wiphy->perm_addr)) {
1384 printk(KERN_WARNING "rtl8187: Invalid hwaddr! Using randomly "
1385 "generated MAC address\n");
1386 random_ether_addr(dev->wiphy->perm_addr);
1387 }
1388
1389 channel = priv->channels;
1390 for (i = 0; i < 3; i++) {
1391 eeprom_93cx6_read(&eeprom, RTL8187_EEPROM_TXPWR_CHAN_1 + i,
1392 &txpwr);
8318d78a
JB		 1393 (*channel++).hw_value = txpwr & 0xFF;
1394 (*channel++).hw_value = txpwr >> 8;
605bebe2
MW		 1395 }
1396 for (i = 0; i < 2; i++) {
1397 eeprom_93cx6_read(&eeprom, RTL8187_EEPROM_TXPWR_CHAN_4 + i,
1398 &txpwr);
8318d78a
JB		 1399 (*channel++).hw_value = txpwr & 0xFF;
1400 (*channel++).hw_value = txpwr >> 8;
605bebe2 1401 }
605bebe2
MW		 1402
1403 eeprom_93cx6_read(&eeprom, RTL8187_EEPROM_TXPWR_BASE,
1404 &priv->txpwr_base);
1405
f6532111
MW		 1406 reg = rtl818x_ioread8(priv, &priv->map->PGSELECT) & ~1;
1407 rtl818x_iowrite8(priv, &priv->map->PGSELECT, reg | 1);
605bebe2
MW		 1408 /* 0 means asic B-cut, we should use SW 3 wire
1409 * bit-by-bit banging for radio. 1 means we can use
1410 * USB specific request to write radio registers */
1411 priv->asic_rev = rtl818x_ioread8(priv, (u8 *)0xFFFE) & 0x3;
f6532111 1412 rtl818x_iowrite8(priv, &priv->map->PGSELECT, reg);
605bebe2
MW		 1413 rtl818x_iowrite8(priv, &priv->map->EEPROM_CMD, RTL818X_EEPROM_CMD_NORMAL);
1414
6f7853f3
HTL		 1415 if (!priv->is_rtl8187b) {
1416 u32 reg32;
1417 reg32 = rtl818x_ioread32(priv, &priv->map->TX_CONF);
1418 reg32 &= RTL818X_TX_CONF_HWVER_MASK;
1419 switch (reg32) {
0e25b4ef
LF		 1420 case RTL818X_TX_CONF_R8187vD_B:
1421 /* Some RTL8187B devices have a USB ID of 0x8187
1422 * detect them here */
1423 chip_name = "RTL8187BvB(early)";
1424 priv->is_rtl8187b = 1;
1425 priv->hw_rev = RTL8187BvB;
1426 break;
1427 case RTL818X_TX_CONF_R8187vD:
6f7853f3
HTL		 1428 chip_name = "RTL8187vD";
1429 break;
1430 default:
1431 chip_name = "RTL8187vB (default)";
1432 }
1433 } else {
6f7853f3
HTL		 1434 /*
1435 * Force USB request to write radio registers for 8187B, Realtek
1436 * only uses it in their sources
1437 */
1438 /*if (priv->asic_rev == 0) {
1439 printk(KERN_WARNING "rtl8187: Forcing use of USB "
1440 "requests to write to radio registers\n");
1441 priv->asic_rev = 1;
1442 }*/
1443 switch (rtl818x_ioread8(priv, (u8 *)0xFFE1)) {
1444 case RTL818X_R8187B_B:
1445 chip_name = "RTL8187BvB";
1446 priv->hw_rev = RTL8187BvB;
1447 break;
1448 case RTL818X_R8187B_D:
1449 chip_name = "RTL8187BvD";
1450 priv->hw_rev = RTL8187BvD;
1451 break;
1452 case RTL818X_R8187B_E:
1453 chip_name = "RTL8187BvE";
1454 priv->hw_rev = RTL8187BvE;
1455 break;
1456 default:
1457 chip_name = "RTL8187BvB (default)";
1458 priv->hw_rev = RTL8187BvB;
1459 }
1460 }
1461
0e25b4ef
LF		 1462 if (!priv->is_rtl8187b) {
1463 for (i = 0; i < 2; i++) {
1464 eeprom_93cx6_read(&eeprom,
1465 RTL8187_EEPROM_TXPWR_CHAN_6 + i,
1466 &txpwr);
1467 (*channel++).hw_value = txpwr & 0xFF;
1468 (*channel++).hw_value = txpwr >> 8;
1469 }
1470 } else {
1471 eeprom_93cx6_read(&eeprom, RTL8187_EEPROM_TXPWR_CHAN_6,
1472 &txpwr);
1473 (*channel++).hw_value = txpwr & 0xFF;
1474
1475 eeprom_93cx6_read(&eeprom, 0x0A, &txpwr);
1476 (*channel++).hw_value = txpwr & 0xFF;
1477
1478 eeprom_93cx6_read(&eeprom, 0x1C, &txpwr);
1479 (*channel++).hw_value = txpwr & 0xFF;
1480 (*channel++).hw_value = txpwr >> 8;
1481 }
1482
94778280
JB		 1483 /*
1484 * XXX: Once this driver supports anything that requires
1485 * beacons it must implement IEEE80211_TX_CTL_ASSIGN_SEQ.
1486 */
f59ac048
LR		 1487 dev->wiphy->interface_modes = BIT(NL80211_IFTYPE_STATION);
1488
0e25b4ef
LF		 1489 if ((id->driver_info == DEVICE_RTL8187) && priv->is_rtl8187b)
1490 printk(KERN_INFO "rtl8187: inconsistency between id with OEM"
1491 " info!\n");
1492
f6532111 1493 priv->rf = rtl8187_detect_rf(dev);
0e25b4ef
LF		 1494 dev->extra_tx_headroom = (!priv->is_rtl8187b) ?
1495 sizeof(struct rtl8187_tx_hdr) :
1496 sizeof(struct rtl8187b_tx_hdr);
1497 if (!priv->is_rtl8187b)
1498 dev->queues = 1;
1499 else
1500 dev->queues = 4;
605bebe2
MW		 1501
1502 err = ieee80211_register_hw(dev);
1503 if (err) {
1504 printk(KERN_ERR "rtl8187: Cannot register device\n");
9be6f0d4 1505 goto err_free_dmabuf;
605bebe2 1506 }
7dcdd073 1507 mutex_init(&priv->conf_mutex);
3517afde 1508 skb_queue_head_init(&priv->b_tx_status.queue);
605bebe2 1509
e174961c
JB		 1510 printk(KERN_INFO "%s: hwaddr %pM, %s V%d + %s\n",
1511 wiphy_name(dev->wiphy), dev->wiphy->perm_addr,
6f7853f3 1512 chip_name, priv->asic_rev, priv->rf->name);
605bebe2 1513
a027087a
LF		 1514#ifdef CONFIG_RTL8187_LEDS
1515 eeprom_93cx6_read(&eeprom, 0x3F, &reg);
1516 reg &= 0xFF;
1517 rtl8187_leds_init(dev, reg);
1518#endif
1519
605bebe2
MW		 1520 return 0;
1521
9be6f0d4
JL		 1522 err_free_dmabuf:
1523 kfree(priv->io_dmabuf);
605bebe2
MW		 1524 err_free_dev:
1525 ieee80211_free_hw(dev);
1526 usb_set_intfdata(intf, NULL);
1527 usb_put_dev(udev);
1528 return err;
1529}
1530
1531static void __devexit rtl8187_disconnect(struct usb_interface *intf)
1532{
1533 struct ieee80211_hw *dev = usb_get_intfdata(intf);
1534 struct rtl8187_priv *priv;
1535
1536 if (!dev)
1537 return;
1538
a027087a
LF		 1539#ifdef CONFIG_RTL8187_LEDS
1540 rtl8187_leds_exit(dev);
1541#endif
605bebe2
MW		 1542 ieee80211_unregister_hw(dev);
1543
1544 priv = dev->priv;
d6e2be98 1545 usb_reset_device(priv->udev);
605bebe2 1546 usb_put_dev(interface_to_usbdev(intf));
9be6f0d4 1547 kfree(priv->io_dmabuf);
605bebe2
MW		 1548 ieee80211_free_hw(dev);
1549}
1550
1551static struct usb_driver rtl8187_driver = {
1552 .name = KBUILD_MODNAME,
1553 .id_table = rtl8187_table,
1554 .probe = rtl8187_probe,
500c1197 1555 .disconnect = __devexit_p(rtl8187_disconnect),
605bebe2
MW		 1556};
1557
1558static int __init rtl8187_init(void)
1559{
1560 return usb_register(&rtl8187_driver);
1561}
1562
1563static void __exit rtl8187_exit(void)
1564{
1565 usb_deregister(&rtl8187_driver);
1566}
1567
1568module_init(rtl8187_init);
1569module_exit(rtl8187_exit);
Linux kernel - Deliverables
This page took 0.513594 seconds and 5 git commands to generate.