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Update of MAINTAINERS for RTL8187
[deliverable/linux.git] / drivers / net / wireless / rtl818x / rtl8187_dev.c
CommitLineData
605bebe2
MW		 1/*
2 * Linux device driver for RTL8187
3 *
4 * Copyright 2007 Michael Wu <flamingice@sourmilk.net>
5 * Copyright 2007 Andrea Merello <andreamrl@tiscali.it>
6 *
7 * Based on the r8187 driver, which is:
8 * Copyright 2005 Andrea Merello <andreamrl@tiscali.it>, et al.
9 *
0aec00ae
JL		 10 * Magic delays and register offsets below are taken from the original
11 * r8187 driver sources. Thanks to Realtek for their support!
605bebe2
MW		 12 *
13 * This program is free software; you can redistribute it and/or modify
14 * it under the terms of the GNU General Public License version 2 as
15 * published by the Free Software Foundation.
16 */
17
18#include <linux/init.h>
19#include <linux/usb.h>
20#include <linux/delay.h>
21#include <linux/etherdevice.h>
22#include <linux/eeprom_93cx6.h>
23#include <net/mac80211.h>
24
25#include "rtl8187.h"
26#include "rtl8187_rtl8225.h"
27
28MODULE_AUTHOR("Michael Wu <flamingice@sourmilk.net>");
29MODULE_AUTHOR("Andrea Merello <andreamrl@tiscali.it>");
f8a08c34 30MODULE_DESCRIPTION("RTL8187/RTL8187B USB wireless driver");
605bebe2
MW		 31MODULE_LICENSE("GPL");
32
33static struct usb_device_id rtl8187_table[] __devinitdata = {
7c7e6af3
AM		 34 /* Asus */
35 {USB_DEVICE(0x0b05, 0x171d), .driver_info = DEVICE_RTL8187},
eaca90da
FF		 36 /* Belkin */
37 {USB_DEVICE(0x050d, 0x705e), .driver_info = DEVICE_RTL8187B},
605bebe2 38 /* Realtek */
f8a08c34
HTL		 39 {USB_DEVICE(0x0bda, 0x8187), .driver_info = DEVICE_RTL8187},
40 {USB_DEVICE(0x0bda, 0x8189), .driver_info = DEVICE_RTL8187B},
41 {USB_DEVICE(0x0bda, 0x8197), .driver_info = DEVICE_RTL8187B},
746db510 42 {USB_DEVICE(0x0bda, 0x8198), .driver_info = DEVICE_RTL8187B},
605bebe2 43 /* Netgear */
f8a08c34
HTL		 44 {USB_DEVICE(0x0846, 0x6100), .driver_info = DEVICE_RTL8187},
45 {USB_DEVICE(0x0846, 0x6a00), .driver_info = DEVICE_RTL8187},
fcd7cc14 46 {USB_DEVICE(0x0846, 0x4260), .driver_info = DEVICE_RTL8187B},
c3cf60a9 47 /* HP */
f8a08c34 48 {USB_DEVICE(0x03f0, 0xca02), .driver_info = DEVICE_RTL8187},
9934550d 49 /* Sitecom */
f8a08c34 50 {USB_DEVICE(0x0df6, 0x000d), .driver_info = DEVICE_RTL8187},
f3c76918 51 {USB_DEVICE(0x0df6, 0x0028), .driver_info = DEVICE_RTL8187B},
8f7c41d4
IK		 52 /* Abocom */
53 {USB_DEVICE(0x13d1, 0xabe6), .driver_info = DEVICE_RTL8187},
605bebe2
MW		 54 {}
55};
56
57MODULE_DEVICE_TABLE(usb, rtl8187_table);
58
8318d78a
JB		 59static const struct ieee80211_rate rtl818x_rates[] = {
60 { .bitrate = 10, .hw_value = 0, },
61 { .bitrate = 20, .hw_value = 1, },
62 { .bitrate = 55, .hw_value = 2, },
63 { .bitrate = 110, .hw_value = 3, },
64 { .bitrate = 60, .hw_value = 4, },
65 { .bitrate = 90, .hw_value = 5, },
66 { .bitrate = 120, .hw_value = 6, },
67 { .bitrate = 180, .hw_value = 7, },
68 { .bitrate = 240, .hw_value = 8, },
69 { .bitrate = 360, .hw_value = 9, },
70 { .bitrate = 480, .hw_value = 10, },
71 { .bitrate = 540, .hw_value = 11, },
72};
73
74static const struct ieee80211_channel rtl818x_channels[] = {
75 { .center_freq = 2412 },
76 { .center_freq = 2417 },
77 { .center_freq = 2422 },
78 { .center_freq = 2427 },
79 { .center_freq = 2432 },
80 { .center_freq = 2437 },
81 { .center_freq = 2442 },
82 { .center_freq = 2447 },
83 { .center_freq = 2452 },
84 { .center_freq = 2457 },
85 { .center_freq = 2462 },
86 { .center_freq = 2467 },
87 { .center_freq = 2472 },
88 { .center_freq = 2484 },
89};
90
4150c572
JB		 91static void rtl8187_iowrite_async_cb(struct urb *urb)
92{
93 kfree(urb->context);
94 usb_free_urb(urb);
95}
96
97static void rtl8187_iowrite_async(struct rtl8187_priv *priv, __le16 addr,
98 void *data, u16 len)
99{
100 struct usb_ctrlrequest *dr;
101 struct urb *urb;
102 struct rtl8187_async_write_data {
103 u8 data[4];
104 struct usb_ctrlrequest dr;
105 } *buf;
ea8ee240 106 int rc;
4150c572
JB		 107
108 buf = kmalloc(sizeof(*buf), GFP_ATOMIC);
109 if (!buf)
110 return;
111
112 urb = usb_alloc_urb(0, GFP_ATOMIC);
113 if (!urb) {
114 kfree(buf);
115 return;
116 }
117
118 dr = &buf->dr;
119
120 dr->bRequestType = RTL8187_REQT_WRITE;
121 dr->bRequest = RTL8187_REQ_SET_REG;
122 dr->wValue = addr;
123 dr->wIndex = 0;
124 dr->wLength = cpu_to_le16(len);
125
126 memcpy(buf, data, len);
127
128 usb_fill_control_urb(urb, priv->udev, usb_sndctrlpipe(priv->udev, 0),
129 (unsigned char *)dr, buf, len,
130 rtl8187_iowrite_async_cb, buf);
ea8ee240
ON		 131 rc = usb_submit_urb(urb, GFP_ATOMIC);
132 if (rc < 0) {
133 kfree(buf);
134 usb_free_urb(urb);
135 }
4150c572
JB		 136}
137
138static inline void rtl818x_iowrite32_async(struct rtl8187_priv *priv,
139 __le32 *addr, u32 val)
140{
141 __le32 buf = cpu_to_le32(val);
142
143 rtl8187_iowrite_async(priv, cpu_to_le16((unsigned long)addr),
144 &buf, sizeof(buf));
145}
146
605bebe2
MW		 147void rtl8187_write_phy(struct ieee80211_hw *dev, u8 addr, u32 data)
148{
149 struct rtl8187_priv *priv = dev->priv;
150
151 data <<= 8;
152 data |= addr | 0x80;
153
154 rtl818x_iowrite8(priv, &priv->map->PHY[3], (data >> 24) & 0xFF);
155 rtl818x_iowrite8(priv, &priv->map->PHY[2], (data >> 16) & 0xFF);
156 rtl818x_iowrite8(priv, &priv->map->PHY[1], (data >> 8) & 0xFF);
157 rtl818x_iowrite8(priv, &priv->map->PHY[0], data & 0xFF);
605bebe2
MW		 158}
159
160static void rtl8187_tx_cb(struct urb *urb)
161{
605bebe2 162 struct sk_buff *skb = (struct sk_buff *)urb->context;
e039fa4a 163 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
e6a9854b 164 struct ieee80211_hw *hw = info->rate_driver_data[0];
6f7853f3 165 struct rtl8187_priv *priv = hw->priv;
605bebe2 166
e6a9854b 167 usb_free_urb(info->rate_driver_data[1]);
6f7853f3
HTL		 168 skb_pull(skb, priv->is_rtl8187b ? sizeof(struct rtl8187b_tx_hdr) :
169 sizeof(struct rtl8187_tx_hdr));
e6a9854b 170 ieee80211_tx_info_clear_status(info);
e039fa4a
JB		 171 info->flags |= IEEE80211_TX_STAT_ACK;
172 ieee80211_tx_status_irqsafe(hw, skb);
605bebe2
MW		 173}
174
e039fa4a 175static int rtl8187_tx(struct ieee80211_hw *dev, struct sk_buff *skb)
605bebe2
MW		 176{
177 struct rtl8187_priv *priv = dev->priv;
e039fa4a 178 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
6f7853f3
HTL		 179 unsigned int ep;
180 void *buf;
605bebe2 181 struct urb *urb;
98798f48
MW		 182 __le16 rts_dur = 0;
183 u32 flags;
ea8ee240 184 int rc;
605bebe2
MW		 185
186 urb = usb_alloc_urb(0, GFP_ATOMIC);
187 if (!urb) {
188 kfree_skb(skb);
189 return 0;
190 }
191
98798f48 192 flags = skb->len;
38e3b0d8 193 flags |= RTL818X_TX_DESC_FLAG_NO_ENC;
aa68cbfb 194
e039fa4a 195 flags |= ieee80211_get_tx_rate(dev, info)->hw_value << 24;
8b7b1e05 196 if (ieee80211_has_morefrags(((struct ieee80211_hdr *)skb->data)->frame_control))
38e3b0d8 197 flags |= RTL818X_TX_DESC_FLAG_MOREFRAG;
e6a9854b 198 if (info->control.rates[0].flags & IEEE80211_TX_RC_USE_RTS_CTS) {
38e3b0d8 199 flags |= RTL818X_TX_DESC_FLAG_RTS;
e039fa4a 200 flags |= ieee80211_get_rts_cts_rate(dev, info)->hw_value << 19;
32bfd35d 201 rts_dur = ieee80211_rts_duration(dev, priv->vif,
e039fa4a 202 skb->len, info);
e6a9854b 203 } else if (info->control.rates[0].flags & IEEE80211_TX_RC_USE_CTS_PROTECT) {
38e3b0d8 204 flags |= RTL818X_TX_DESC_FLAG_CTS;
e039fa4a 205 flags |= ieee80211_get_rts_cts_rate(dev, info)->hw_value << 19;
aa68cbfb 206 }
98798f48 207
6f7853f3
HTL		 208 if (!priv->is_rtl8187b) {
209 struct rtl8187_tx_hdr *hdr =
210 (struct rtl8187_tx_hdr *)skb_push(skb, sizeof(*hdr));
211 hdr->flags = cpu_to_le32(flags);
212 hdr->len = 0;
213 hdr->rts_duration = rts_dur;
e6a9854b 214 hdr->retry = cpu_to_le32((info->control.rates[0].count - 1) << 8);
6f7853f3
HTL		 215 buf = hdr;
216
217 ep = 2;
218 } else {
219 /* fc needs to be calculated before skb_push() */
220 unsigned int epmap[4] = { 6, 7, 5, 4 };
221 struct ieee80211_hdr *tx_hdr =
222 (struct ieee80211_hdr *)(skb->data);
223 u16 fc = le16_to_cpu(tx_hdr->frame_control);
224
225 struct rtl8187b_tx_hdr *hdr =
226 (struct rtl8187b_tx_hdr *)skb_push(skb, sizeof(*hdr));
227 struct ieee80211_rate *txrate =
228 ieee80211_get_tx_rate(dev, info);
229 memset(hdr, 0, sizeof(*hdr));
230 hdr->flags = cpu_to_le32(flags);
231 hdr->rts_duration = rts_dur;
e6a9854b 232 hdr->retry = cpu_to_le32((info->control.rates[0].count - 1) << 8);
6f7853f3
HTL		 233 hdr->tx_duration =
234 ieee80211_generic_frame_duration(dev, priv->vif,
235 skb->len, txrate);
236 buf = hdr;
237
238 if ((fc & IEEE80211_FCTL_FTYPE) == IEEE80211_FTYPE_MGMT)
239 ep = 12;
240 else
241 ep = epmap[skb_get_queue_mapping(skb)];
242 }
605bebe2 243
e6a9854b
JB		 244 info->rate_driver_data[0] = dev;
245 info->rate_driver_data[1] = urb;
6f7853f3
HTL		 246
247 usb_fill_bulk_urb(urb, priv->udev, usb_sndbulkpipe(priv->udev, ep),
248 buf, skb->len, rtl8187_tx_cb, skb);
ea8ee240
ON		 249 rc = usb_submit_urb(urb, GFP_ATOMIC);
250 if (rc < 0) {
251 usb_free_urb(urb);
252 kfree_skb(skb);
253 }
605bebe2
MW		 254
255 return 0;
256}
257
258static void rtl8187_rx_cb(struct urb *urb)
259{
260 struct sk_buff *skb = (struct sk_buff *)urb->context;
261 struct rtl8187_rx_info *info = (struct rtl8187_rx_info *)skb->cb;
262 struct ieee80211_hw *dev = info->dev;
263 struct rtl8187_priv *priv = dev->priv;
605bebe2
MW		 264 struct ieee80211_rx_status rx_status = { 0 };
265 int rate, signal;
4150c572 266 u32 flags;
0ccd58fc 267 u32 quality;
605bebe2
MW		 268
269 spin_lock(&priv->rx_queue.lock);
270 if (skb->next)
271 __skb_unlink(skb, &priv->rx_queue);
272 else {
273 spin_unlock(&priv->rx_queue.lock);
274 return;
275 }
276 spin_unlock(&priv->rx_queue.lock);
277
278 if (unlikely(urb->status)) {
279 usb_free_urb(urb);
280 dev_kfree_skb_irq(skb);
281 return;
282 }
283
284 skb_put(skb, urb->actual_length);
6f7853f3
HTL		 285 if (!priv->is_rtl8187b) {
286 struct rtl8187_rx_hdr *hdr =
287 (typeof(hdr))(skb_tail_pointer(skb) - sizeof(*hdr));
288 flags = le32_to_cpu(hdr->flags);
289 signal = hdr->signal & 0x7f;
290 rx_status.antenna = (hdr->signal >> 7) & 1;
6f7853f3
HTL		 291 rx_status.noise = hdr->noise;
292 rx_status.mactime = le64_to_cpu(hdr->mac_time);
6f7853f3 293 priv->quality = signal;
0ccd58fc 294 rx_status.qual = priv->quality;
6f7853f3 295 priv->noise = hdr->noise;
0ccd58fc
LF		 296 rate = (flags >> 20) & 0xF;
297 if (rate > 3) { /* OFDM rate */
298 if (signal > 90)
299 signal = 90;
300 else if (signal < 25)
301 signal = 25;
302 signal = 90 - signal;
303 } else { /* CCK rate */
304 if (signal > 95)
305 signal = 95;
306 else if (signal < 30)
307 signal = 30;
308 signal = 95 - signal;
309 }
310 rx_status.signal = signal;
311 priv->signal = signal;
6f7853f3
HTL		 312 } else {
313 struct rtl8187b_rx_hdr *hdr =
314 (typeof(hdr))(skb_tail_pointer(skb) - sizeof(*hdr));
0ccd58fc
LF		 315 /* The Realtek datasheet for the RTL8187B shows that the RX
316 * header contains the following quantities: signal quality,
317 * RSSI, AGC, the received power in dB, and the measured SNR.
318 * In testing, none of these quantities show qualitative
319 * agreement with AP signal strength, except for the AGC,
320 * which is inversely proportional to the strength of the
321 * signal. In the following, the quality and signal strength
322 * are derived from the AGC. The arbitrary scaling constants
323 * are chosen to make the results close to the values obtained
324 * for a BCM4312 using b43 as the driver. The noise is ignored
325 * for now.
326 */
6f7853f3 327 flags = le32_to_cpu(hdr->flags);
0ccd58fc
LF		 328 quality = 170 - hdr->agc;
329 if (quality > 100)
330 quality = 100;
331 signal = 14 - hdr->agc / 2;
332 rx_status.qual = quality;
333 priv->quality = quality;
334 rx_status.signal = signal;
335 priv->signal = signal;
336 rx_status.antenna = (hdr->rssi >> 7) & 1;
6f7853f3 337 rx_status.mactime = le64_to_cpu(hdr->mac_time);
0ccd58fc 338 rate = (flags >> 20) & 0xF;
6f7853f3 339 }
605bebe2 340
6f7853f3 341 skb_trim(skb, flags & 0x0FFF);
8318d78a
JB		 342 rx_status.rate_idx = rate;
343 rx_status.freq = dev->conf.channel->center_freq;
344 rx_status.band = dev->conf.channel->band;
03bffc13 345 rx_status.flag |= RX_FLAG_TSFT;
38e3b0d8 346 if (flags & RTL818X_RX_DESC_FLAG_CRC32_ERR)
4150c572 347 rx_status.flag |= RX_FLAG_FAILED_FCS_CRC;
605bebe2
MW		 348 ieee80211_rx_irqsafe(dev, skb, &rx_status);
349
350 skb = dev_alloc_skb(RTL8187_MAX_RX);
351 if (unlikely(!skb)) {
352 usb_free_urb(urb);
353 /* TODO check rx queue length and refill *somewhere* */
354 return;
355 }
356
357 info = (struct rtl8187_rx_info *)skb->cb;
358 info->urb = urb;
359 info->dev = dev;
360 urb->transfer_buffer = skb_tail_pointer(skb);
361 urb->context = skb;
362 skb_queue_tail(&priv->rx_queue, skb);
363
364 usb_submit_urb(urb, GFP_ATOMIC);
365}
366
367static int rtl8187_init_urbs(struct ieee80211_hw *dev)
368{
369 struct rtl8187_priv *priv = dev->priv;
370 struct urb *entry;
371 struct sk_buff *skb;
372 struct rtl8187_rx_info *info;
373
374 while (skb_queue_len(&priv->rx_queue) < 8) {
375 skb = __dev_alloc_skb(RTL8187_MAX_RX, GFP_KERNEL);
376 if (!skb)
377 break;
378 entry = usb_alloc_urb(0, GFP_KERNEL);
379 if (!entry) {
380 kfree_skb(skb);
381 break;
382 }
383 usb_fill_bulk_urb(entry, priv->udev,
6f7853f3
HTL		 384 usb_rcvbulkpipe(priv->udev,
385 priv->is_rtl8187b ? 3 : 1),
605bebe2
MW		 386 skb_tail_pointer(skb),
387 RTL8187_MAX_RX, rtl8187_rx_cb, skb);
388 info = (struct rtl8187_rx_info *)skb->cb;
389 info->urb = entry;
390 info->dev = dev;
391 skb_queue_tail(&priv->rx_queue, skb);
392 usb_submit_urb(entry, GFP_KERNEL);
393 }
394
395 return 0;
396}
397
f8a08c34 398static int rtl8187_cmd_reset(struct ieee80211_hw *dev)
605bebe2
MW		 399{
400 struct rtl8187_priv *priv = dev->priv;
401 u8 reg;
402 int i;
403
605bebe2
MW		 404 reg = rtl818x_ioread8(priv, &priv->map->CMD);
405 reg &= (1 << 1);
406 reg |= RTL818X_CMD_RESET;
407 rtl818x_iowrite8(priv, &priv->map->CMD, reg);
408
409 i = 10;
410 do {
411 msleep(2);
412 if (!(rtl818x_ioread8(priv, &priv->map->CMD) &
413 RTL818X_CMD_RESET))
414 break;
415 } while (--i);
416
417 if (!i) {
418 printk(KERN_ERR "%s: Reset timeout!\n", wiphy_name(dev->wiphy));
419 return -ETIMEDOUT;
420 }
421
422 /* reload registers from eeprom */
423 rtl818x_iowrite8(priv, &priv->map->EEPROM_CMD, RTL818X_EEPROM_CMD_LOAD);
424
425 i = 10;
426 do {
427 msleep(4);
428 if (!(rtl818x_ioread8(priv, &priv->map->EEPROM_CMD) &
429 RTL818X_EEPROM_CMD_CONFIG))
430 break;
431 } while (--i);
432
433 if (!i) {
434 printk(KERN_ERR "%s: eeprom reset timeout!\n",
435 wiphy_name(dev->wiphy));
436 return -ETIMEDOUT;
437 }
438
f8a08c34
HTL		 439 return 0;
440}
441
442static int rtl8187_init_hw(struct ieee80211_hw *dev)
443{
444 struct rtl8187_priv *priv = dev->priv;
445 u8 reg;
446 int res;
447
448 /* reset */
449 rtl818x_iowrite8(priv, &priv->map->EEPROM_CMD,
450 RTL818X_EEPROM_CMD_CONFIG);
451 reg = rtl818x_ioread8(priv, &priv->map->CONFIG3);
452 rtl818x_iowrite8(priv, &priv->map->CONFIG3, reg |
453 RTL818X_CONFIG3_ANAPARAM_WRITE);
4ece16a1
HRK		 454 rtl818x_iowrite32(priv, &priv->map->ANAPARAM,
455 RTL8187_RTL8225_ANAPARAM_ON);
456 rtl818x_iowrite32(priv, &priv->map->ANAPARAM2,
457 RTL8187_RTL8225_ANAPARAM2_ON);
f8a08c34
HTL		 458 rtl818x_iowrite8(priv, &priv->map->CONFIG3, reg &
459 ~RTL818X_CONFIG3_ANAPARAM_WRITE);
460 rtl818x_iowrite8(priv, &priv->map->EEPROM_CMD,
461 RTL818X_EEPROM_CMD_NORMAL);
462
463 rtl818x_iowrite16(priv, &priv->map->INT_MASK, 0);
464
465 msleep(200);
466 rtl818x_iowrite8(priv, (u8 *)0xFE18, 0x10);
467 rtl818x_iowrite8(priv, (u8 *)0xFE18, 0x11);
468 rtl818x_iowrite8(priv, (u8 *)0xFE18, 0x00);
469 msleep(200);
470
471 res = rtl8187_cmd_reset(dev);
472 if (res)
473 return res;
474
605bebe2
MW		 475 rtl818x_iowrite8(priv, &priv->map->EEPROM_CMD, RTL818X_EEPROM_CMD_CONFIG);
476 reg = rtl818x_ioread8(priv, &priv->map->CONFIG3);
f8a08c34
HTL		 477 rtl818x_iowrite8(priv, &priv->map->CONFIG3,
478 reg | RTL818X_CONFIG3_ANAPARAM_WRITE);
4ece16a1
HRK		 479 rtl818x_iowrite32(priv, &priv->map->ANAPARAM,
480 RTL8187_RTL8225_ANAPARAM_ON);
481 rtl818x_iowrite32(priv, &priv->map->ANAPARAM2,
482 RTL8187_RTL8225_ANAPARAM2_ON);
f8a08c34
HTL		 483 rtl818x_iowrite8(priv, &priv->map->CONFIG3,
484 reg & ~RTL818X_CONFIG3_ANAPARAM_WRITE);
605bebe2
MW		 485 rtl818x_iowrite8(priv, &priv->map->EEPROM_CMD, RTL818X_EEPROM_CMD_NORMAL);
486
487 /* setup card */
488 rtl818x_iowrite16(priv, &priv->map->RFPinsSelect, 0);
489 rtl818x_iowrite8(priv, &priv->map->GPIO, 0);
490
491 rtl818x_iowrite16(priv, &priv->map->RFPinsSelect, (4 << 8));
492 rtl818x_iowrite8(priv, &priv->map->GPIO, 1);
493 rtl818x_iowrite8(priv, &priv->map->GP_ENABLE, 0);
494
495 rtl818x_iowrite8(priv, &priv->map->EEPROM_CMD, RTL818X_EEPROM_CMD_CONFIG);
605bebe2
MW		 496
497 rtl818x_iowrite16(priv, (__le16 *)0xFFF4, 0xFFFF);
498 reg = rtl818x_ioread8(priv, &priv->map->CONFIG1);
499 reg &= 0x3F;
500 reg |= 0x80;
501 rtl818x_iowrite8(priv, &priv->map->CONFIG1, reg);
502
503 rtl818x_iowrite8(priv, &priv->map->EEPROM_CMD, RTL818X_EEPROM_CMD_NORMAL);
504
505 rtl818x_iowrite32(priv, &priv->map->INT_TIMEOUT, 0);
506 rtl818x_iowrite8(priv, &priv->map->WPA_CONF, 0);
507 rtl818x_iowrite8(priv, &priv->map->RATE_FALLBACK, 0x81);
508
509 // TODO: set RESP_RATE and BRSR properly
510 rtl818x_iowrite8(priv, &priv->map->RESP_RATE, (8 << 4) | 0);
511 rtl818x_iowrite16(priv, &priv->map->BRSR, 0x01F3);
512
513 /* host_usb_init */
514 rtl818x_iowrite16(priv, &priv->map->RFPinsSelect, 0);
515 rtl818x_iowrite8(priv, &priv->map->GPIO, 0);
516 reg = rtl818x_ioread8(priv, (u8 *)0xFE53);
517 rtl818x_iowrite8(priv, (u8 *)0xFE53, reg | (1 << 7));
518 rtl818x_iowrite16(priv, &priv->map->RFPinsSelect, (4 << 8));
519 rtl818x_iowrite8(priv, &priv->map->GPIO, 0x20);
520 rtl818x_iowrite8(priv, &priv->map->GP_ENABLE, 0);
521 rtl818x_iowrite16(priv, &priv->map->RFPinsOutput, 0x80);
522 rtl818x_iowrite16(priv, &priv->map->RFPinsSelect, 0x80);
523 rtl818x_iowrite16(priv, &priv->map->RFPinsEnable, 0x80);
524 msleep(100);
525
526 rtl818x_iowrite32(priv, &priv->map->RF_TIMING, 0x000a8008);
527 rtl818x_iowrite16(priv, &priv->map->BRSR, 0xFFFF);
528 rtl818x_iowrite32(priv, &priv->map->RF_PARA, 0x00100044);
f8a08c34
HTL		 529 rtl818x_iowrite8(priv, &priv->map->EEPROM_CMD,
530 RTL818X_EEPROM_CMD_CONFIG);
605bebe2 531 rtl818x_iowrite8(priv, &priv->map->CONFIG3, 0x44);
f8a08c34
HTL		 532 rtl818x_iowrite8(priv, &priv->map->EEPROM_CMD,
533 RTL818X_EEPROM_CMD_NORMAL);
605bebe2
MW		 534 rtl818x_iowrite16(priv, &priv->map->RFPinsEnable, 0x1FF7);
535 msleep(100);
536
f6532111 537 priv->rf->init(dev);
605bebe2
MW		 538
539 rtl818x_iowrite16(priv, &priv->map->BRSR, 0x01F3);
f6532111
MW		 540 reg = rtl818x_ioread8(priv, &priv->map->PGSELECT) & ~1;
541 rtl818x_iowrite8(priv, &priv->map->PGSELECT, reg | 1);
605bebe2
MW		 542 rtl818x_iowrite16(priv, (__le16 *)0xFFFE, 0x10);
543 rtl818x_iowrite8(priv, &priv->map->TALLY_SEL, 0x80);
544 rtl818x_iowrite8(priv, (u8 *)0xFFFF, 0x60);
f6532111 545 rtl818x_iowrite8(priv, &priv->map->PGSELECT, reg);
605bebe2
MW		 546
547 return 0;
548}
549
f8a08c34
HTL		 550static const u8 rtl8187b_reg_table[][3] = {
551 {0xF0, 0x32, 0}, {0xF1, 0x32, 0}, {0xF2, 0x00, 0}, {0xF3, 0x00, 0},
552 {0xF4, 0x32, 0}, {0xF5, 0x43, 0}, {0xF6, 0x00, 0}, {0xF7, 0x00, 0},
553 {0xF8, 0x46, 0}, {0xF9, 0xA4, 0}, {0xFA, 0x00, 0}, {0xFB, 0x00, 0},
554 {0xFC, 0x96, 0}, {0xFD, 0xA4, 0}, {0xFE, 0x00, 0}, {0xFF, 0x00, 0},
555
556 {0x58, 0x4B, 1}, {0x59, 0x00, 1}, {0x5A, 0x4B, 1}, {0x5B, 0x00, 1},
557 {0x60, 0x4B, 1}, {0x61, 0x09, 1}, {0x62, 0x4B, 1}, {0x63, 0x09, 1},
558 {0xCE, 0x0F, 1}, {0xCF, 0x00, 1}, {0xE0, 0xFF, 1}, {0xE1, 0x0F, 1},
559 {0xE2, 0x00, 1}, {0xF0, 0x4E, 1}, {0xF1, 0x01, 1}, {0xF2, 0x02, 1},
560 {0xF3, 0x03, 1}, {0xF4, 0x04, 1}, {0xF5, 0x05, 1}, {0xF6, 0x06, 1},
561 {0xF7, 0x07, 1}, {0xF8, 0x08, 1},
562
563 {0x4E, 0x00, 2}, {0x0C, 0x04, 2}, {0x21, 0x61, 2}, {0x22, 0x68, 2},
564 {0x23, 0x6F, 2}, {0x24, 0x76, 2}, {0x25, 0x7D, 2}, {0x26, 0x84, 2},
565 {0x27, 0x8D, 2}, {0x4D, 0x08, 2}, {0x50, 0x05, 2}, {0x51, 0xF5, 2},
566 {0x52, 0x04, 2}, {0x53, 0xA0, 2}, {0x54, 0x1F, 2}, {0x55, 0x23, 2},
567 {0x56, 0x45, 2}, {0x57, 0x67, 2}, {0x58, 0x08, 2}, {0x59, 0x08, 2},
568 {0x5A, 0x08, 2}, {0x5B, 0x08, 2}, {0x60, 0x08, 2}, {0x61, 0x08, 2},
569 {0x62, 0x08, 2}, {0x63, 0x08, 2}, {0x64, 0xCF, 2}, {0x72, 0x56, 2},
570 {0x73, 0x9A, 2},
571
572 {0x34, 0xF0, 0}, {0x35, 0x0F, 0}, {0x5B, 0x40, 0}, {0x84, 0x88, 0},
573 {0x85, 0x24, 0}, {0x88, 0x54, 0}, {0x8B, 0xB8, 0}, {0x8C, 0x07, 0},
574 {0x8D, 0x00, 0}, {0x94, 0x1B, 0}, {0x95, 0x12, 0}, {0x96, 0x00, 0},
575 {0x97, 0x06, 0}, {0x9D, 0x1A, 0}, {0x9F, 0x10, 0}, {0xB4, 0x22, 0},
576 {0xBE, 0x80, 0}, {0xDB, 0x00, 0}, {0xEE, 0x00, 0}, {0x91, 0x03, 0},
577
578 {0x4C, 0x00, 2}, {0x9F, 0x00, 3}, {0x8C, 0x01, 0}, {0x8D, 0x10, 0},
579 {0x8E, 0x08, 0}, {0x8F, 0x00, 0}
580};
581
582static int rtl8187b_init_hw(struct ieee80211_hw *dev)
583{
584 struct rtl8187_priv *priv = dev->priv;
585 int res, i;
586 u8 reg;
587
588 rtl818x_iowrite8(priv, &priv->map->EEPROM_CMD,
589 RTL818X_EEPROM_CMD_CONFIG);
590
591 reg = rtl818x_ioread8(priv, &priv->map->CONFIG3);
592 reg |= RTL818X_CONFIG3_ANAPARAM_WRITE | RTL818X_CONFIG3_GNT_SELECT;
593 rtl818x_iowrite8(priv, &priv->map->CONFIG3, reg);
4ece16a1
HRK		 594 rtl818x_iowrite32(priv, &priv->map->ANAPARAM2,
595 RTL8187B_RTL8225_ANAPARAM2_ON);
596 rtl818x_iowrite32(priv, &priv->map->ANAPARAM,
597 RTL8187B_RTL8225_ANAPARAM_ON);
598 rtl818x_iowrite8(priv, &priv->map->ANAPARAM3,
599 RTL8187B_RTL8225_ANAPARAM3_ON);
f8a08c34
HTL		 600
601 rtl818x_iowrite8(priv, (u8 *)0xFF61, 0x10);
602 reg = rtl818x_ioread8(priv, (u8 *)0xFF62);
603 rtl818x_iowrite8(priv, (u8 *)0xFF62, reg & ~(1 << 5));
604 rtl818x_iowrite8(priv, (u8 *)0xFF62, reg | (1 << 5));
605
606 reg = rtl818x_ioread8(priv, &priv->map->CONFIG3);
607 reg &= ~RTL818X_CONFIG3_ANAPARAM_WRITE;
608 rtl818x_iowrite8(priv, &priv->map->CONFIG3, reg);
609
610 rtl818x_iowrite8(priv, &priv->map->EEPROM_CMD,
611 RTL818X_EEPROM_CMD_NORMAL);
612
613 res = rtl8187_cmd_reset(dev);
614 if (res)
615 return res;
616
617 rtl818x_iowrite16(priv, (__le16 *)0xFF2D, 0x0FFF);
618 reg = rtl818x_ioread8(priv, &priv->map->CW_CONF);
619 reg |= RTL818X_CW_CONF_PERPACKET_RETRY_SHIFT;
620 rtl818x_iowrite8(priv, &priv->map->CW_CONF, reg);
621 reg = rtl818x_ioread8(priv, &priv->map->TX_AGC_CTL);
622 reg |= RTL818X_TX_AGC_CTL_PERPACKET_GAIN_SHIFT |
623 RTL818X_TX_AGC_CTL_PERPACKET_ANTSEL_SHIFT;
624 rtl818x_iowrite8(priv, &priv->map->TX_AGC_CTL, reg);
625
626 rtl818x_iowrite16_idx(priv, (__le16 *)0xFFE0, 0x0FFF, 1);
627 reg = rtl818x_ioread8(priv, &priv->map->RATE_FALLBACK);
628 reg |= RTL818X_RATE_FALLBACK_ENABLE;
629 rtl818x_iowrite8(priv, &priv->map->RATE_FALLBACK, reg);
630
631 rtl818x_iowrite16(priv, &priv->map->BEACON_INTERVAL, 100);
632 rtl818x_iowrite16(priv, &priv->map->ATIM_WND, 2);
633 rtl818x_iowrite16_idx(priv, (__le16 *)0xFFD4, 0xFFFF, 1);
634
635 rtl818x_iowrite8(priv, &priv->map->EEPROM_CMD,
636 RTL818X_EEPROM_CMD_CONFIG);
637 reg = rtl818x_ioread8(priv, &priv->map->CONFIG1);
638 rtl818x_iowrite8(priv, &priv->map->CONFIG1, (reg & 0x3F) | 0x80);
639 rtl818x_iowrite8(priv, &priv->map->EEPROM_CMD,
640 RTL818X_EEPROM_CMD_NORMAL);
641
642 rtl818x_iowrite8(priv, &priv->map->WPA_CONF, 0);
643 for (i = 0; i < ARRAY_SIZE(rtl8187b_reg_table); i++) {
644 rtl818x_iowrite8_idx(priv,
645 (u8 *)(uintptr_t)
646 (rtl8187b_reg_table[i][0] | 0xFF00),
647 rtl8187b_reg_table[i][1],
648 rtl8187b_reg_table[i][2]);
649 }
650
651 rtl818x_iowrite16(priv, &priv->map->TID_AC_MAP, 0xFA50);
652 rtl818x_iowrite16(priv, &priv->map->INT_MIG, 0);
653
654 rtl818x_iowrite32_idx(priv, (__le32 *)0xFFF0, 0, 1);
655 rtl818x_iowrite32_idx(priv, (__le32 *)0xFFF4, 0, 1);
656 rtl818x_iowrite8_idx(priv, (u8 *)0xFFF8, 0, 1);
657
658 rtl818x_iowrite32(priv, &priv->map->RF_TIMING, 0x00004001);
659
660 rtl818x_iowrite16_idx(priv, (__le16 *)0xFF72, 0x569A, 2);
661
662 rtl818x_iowrite8(priv, &priv->map->EEPROM_CMD,
663 RTL818X_EEPROM_CMD_CONFIG);
664 reg = rtl818x_ioread8(priv, &priv->map->CONFIG3);
665 reg |= RTL818X_CONFIG3_ANAPARAM_WRITE;
666 rtl818x_iowrite8(priv, &priv->map->CONFIG3, reg);
667 rtl818x_iowrite8(priv, &priv->map->EEPROM_CMD,
668 RTL818X_EEPROM_CMD_NORMAL);
669
670 rtl818x_iowrite16(priv, &priv->map->RFPinsOutput, 0x0480);
671 rtl818x_iowrite16(priv, &priv->map->RFPinsSelect, 0x2488);
672 rtl818x_iowrite16(priv, &priv->map->RFPinsEnable, 0x1FFF);
2f20596b 673 msleep(100);
f8a08c34
HTL		 674
675 priv->rf->init(dev);
676
677 reg = RTL818X_CMD_TX_ENABLE | RTL818X_CMD_RX_ENABLE;
678 rtl818x_iowrite8(priv, &priv->map->CMD, reg);
679 rtl818x_iowrite16(priv, &priv->map->INT_MASK, 0xFFFF);
680
681 rtl818x_iowrite8(priv, (u8 *)0xFE41, 0xF4);
682 rtl818x_iowrite8(priv, (u8 *)0xFE40, 0x00);
683 rtl818x_iowrite8(priv, (u8 *)0xFE42, 0x00);
684 rtl818x_iowrite8(priv, (u8 *)0xFE42, 0x01);
685 rtl818x_iowrite8(priv, (u8 *)0xFE40, 0x0F);
686 rtl818x_iowrite8(priv, (u8 *)0xFE42, 0x00);
687 rtl818x_iowrite8(priv, (u8 *)0xFE42, 0x01);
688
689 reg = rtl818x_ioread8(priv, (u8 *)0xFFDB);
690 rtl818x_iowrite8(priv, (u8 *)0xFFDB, reg | (1 << 2));
691 rtl818x_iowrite16_idx(priv, (__le16 *)0xFF72, 0x59FA, 3);
692 rtl818x_iowrite16_idx(priv, (__le16 *)0xFF74, 0x59D2, 3);
693 rtl818x_iowrite16_idx(priv, (__le16 *)0xFF76, 0x59D2, 3);
694 rtl818x_iowrite16_idx(priv, (__le16 *)0xFF78, 0x19FA, 3);
695 rtl818x_iowrite16_idx(priv, (__le16 *)0xFF7A, 0x19FA, 3);
696 rtl818x_iowrite16_idx(priv, (__le16 *)0xFF7C, 0x00D0, 3);
697 rtl818x_iowrite8(priv, (u8 *)0xFF61, 0);
698 rtl818x_iowrite8_idx(priv, (u8 *)0xFF80, 0x0F, 1);
699 rtl818x_iowrite8_idx(priv, (u8 *)0xFF83, 0x03, 1);
700 rtl818x_iowrite8(priv, (u8 *)0xFFDA, 0x10);
701 rtl818x_iowrite8_idx(priv, (u8 *)0xFF4D, 0x08, 2);
702
703 rtl818x_iowrite32(priv, &priv->map->HSSI_PARA, 0x0600321B);
704
705 rtl818x_iowrite16_idx(priv, (__le16 *)0xFFEC, 0x0800, 1);
706
707 return 0;
708}
709
4150c572 710static int rtl8187_start(struct ieee80211_hw *dev)
605bebe2
MW		 711{
712 struct rtl8187_priv *priv = dev->priv;
713 u32 reg;
714 int ret;
715
f8a08c34
HTL		 716 ret = (!priv->is_rtl8187b) ? rtl8187_init_hw(dev) :
717 rtl8187b_init_hw(dev);
605bebe2
MW		 718 if (ret)
719 return ret;
720
7dcdd073 721 mutex_lock(&priv->conf_mutex);
f8a08c34
HTL		 722 if (priv->is_rtl8187b) {
723 reg = RTL818X_RX_CONF_MGMT |
724 RTL818X_RX_CONF_DATA |
725 RTL818X_RX_CONF_BROADCAST |
726 RTL818X_RX_CONF_NICMAC |
727 RTL818X_RX_CONF_BSSID |
728 (7 << 13 /* RX FIFO threshold NONE */) |
729 (7 << 10 /* MAX RX DMA */) |
730 RTL818X_RX_CONF_RX_AUTORESETPHY |
731 RTL818X_RX_CONF_ONLYERLPKT |
732 RTL818X_RX_CONF_MULTICAST;
733 priv->rx_conf = reg;
734 rtl818x_iowrite32(priv, &priv->map->RX_CONF, reg);
735
736 rtl818x_iowrite32(priv, &priv->map->TX_CONF,
737 RTL818X_TX_CONF_HW_SEQNUM |
738 RTL818X_TX_CONF_DISREQQSIZE |
739 (7 << 8 /* short retry limit */) |
740 (7 << 0 /* long retry limit */) |
741 (7 << 21 /* MAX TX DMA */));
742 rtl8187_init_urbs(dev);
7dcdd073 743 mutex_unlock(&priv->conf_mutex);
f8a08c34
HTL		 744 return 0;
745 }
746
605bebe2
MW		 747 rtl818x_iowrite16(priv, &priv->map->INT_MASK, 0xFFFF);
748
2fe14263
MW		 749 rtl818x_iowrite32(priv, &priv->map->MAR[0], ~0);
750 rtl818x_iowrite32(priv, &priv->map->MAR[1], ~0);
751
605bebe2
MW		 752 rtl8187_init_urbs(dev);
753
754 reg = RTL818X_RX_CONF_ONLYERLPKT |
755 RTL818X_RX_CONF_RX_AUTORESETPHY |
756 RTL818X_RX_CONF_BSSID |
757 RTL818X_RX_CONF_MGMT |
605bebe2
MW		 758 RTL818X_RX_CONF_DATA |
759 (7 << 13 /* RX FIFO threshold NONE */) |
760 (7 << 10 /* MAX RX DMA */) |
761 RTL818X_RX_CONF_BROADCAST |
605bebe2 762 RTL818X_RX_CONF_NICMAC;
605bebe2 763
4150c572 764 priv->rx_conf = reg;
605bebe2
MW		 765 rtl818x_iowrite32(priv, &priv->map->RX_CONF, reg);
766
767 reg = rtl818x_ioread8(priv, &priv->map->CW_CONF);
768 reg &= ~RTL818X_CW_CONF_PERPACKET_CW_SHIFT;
769 reg |= RTL818X_CW_CONF_PERPACKET_RETRY_SHIFT;
770 rtl818x_iowrite8(priv, &priv->map->CW_CONF, reg);
771
772 reg = rtl818x_ioread8(priv, &priv->map->TX_AGC_CTL);
773 reg &= ~RTL818X_TX_AGC_CTL_PERPACKET_GAIN_SHIFT;
774 reg &= ~RTL818X_TX_AGC_CTL_PERPACKET_ANTSEL_SHIFT;
775 reg &= ~RTL818X_TX_AGC_CTL_FEEDBACK_ANT;
776 rtl818x_iowrite8(priv, &priv->map->TX_AGC_CTL, reg);
777
778 reg = RTL818X_TX_CONF_CW_MIN |
779 (7 << 21 /* MAX TX DMA */) |
780 RTL818X_TX_CONF_NO_ICV;
781 rtl818x_iowrite32(priv, &priv->map->TX_CONF, reg);
782
783 reg = rtl818x_ioread8(priv, &priv->map->CMD);
784 reg |= RTL818X_CMD_TX_ENABLE;
785 reg |= RTL818X_CMD_RX_ENABLE;
786 rtl818x_iowrite8(priv, &priv->map->CMD, reg);
7dcdd073 787 mutex_unlock(&priv->conf_mutex);
605bebe2
MW		 788
789 return 0;
790}
791
4150c572 792static void rtl8187_stop(struct ieee80211_hw *dev)
605bebe2
MW		 793{
794 struct rtl8187_priv *priv = dev->priv;
795 struct rtl8187_rx_info *info;
796 struct sk_buff *skb;
797 u32 reg;
798
7dcdd073 799 mutex_lock(&priv->conf_mutex);
605bebe2
MW		 800 rtl818x_iowrite16(priv, &priv->map->INT_MASK, 0);
801
802 reg = rtl818x_ioread8(priv, &priv->map->CMD);
803 reg &= ~RTL818X_CMD_TX_ENABLE;
804 reg &= ~RTL818X_CMD_RX_ENABLE;
805 rtl818x_iowrite8(priv, &priv->map->CMD, reg);
806
f6532111 807 priv->rf->stop(dev);
605bebe2
MW		 808
809 rtl818x_iowrite8(priv, &priv->map->EEPROM_CMD, RTL818X_EEPROM_CMD_CONFIG);
810 reg = rtl818x_ioread8(priv, &priv->map->CONFIG4);
811 rtl818x_iowrite8(priv, &priv->map->CONFIG4, reg | RTL818X_CONFIG4_VCOOFF);
812 rtl818x_iowrite8(priv, &priv->map->EEPROM_CMD, RTL818X_EEPROM_CMD_NORMAL);
813
814 while ((skb = skb_dequeue(&priv->rx_queue))) {
815 info = (struct rtl8187_rx_info *)skb->cb;
816 usb_kill_urb(info->urb);
817 kfree_skb(skb);
818 }
7dcdd073 819 mutex_unlock(&priv->conf_mutex);
605bebe2
MW		 820}
821
822static int rtl8187_add_interface(struct ieee80211_hw *dev,
823 struct ieee80211_if_init_conf *conf)
824{
825 struct rtl8187_priv *priv = dev->priv;
4150c572 826 int i;
605bebe2 827
05c914fe 828 if (priv->mode != NL80211_IFTYPE_MONITOR)
4150c572 829 return -EOPNOTSUPP;
605bebe2
MW		 830
831 switch (conf->type) {
05c914fe 832 case NL80211_IFTYPE_STATION:
605bebe2
MW		 833 priv->mode = conf->type;
834 break;
835 default:
836 return -EOPNOTSUPP;
837 }
838
7dcdd073 839 mutex_lock(&priv->conf_mutex);
aa979a6a
HRK		 840 priv->vif = conf->vif;
841
4150c572
JB		 842 rtl818x_iowrite8(priv, &priv->map->EEPROM_CMD, RTL818X_EEPROM_CMD_CONFIG);
843 for (i = 0; i < ETH_ALEN; i++)
844 rtl818x_iowrite8(priv, &priv->map->MAC[i],
845 ((u8 *)conf->mac_addr)[i]);
846 rtl818x_iowrite8(priv, &priv->map->EEPROM_CMD, RTL818X_EEPROM_CMD_NORMAL);
605bebe2 847
7dcdd073 848 mutex_unlock(&priv->conf_mutex);
605bebe2
MW		 849 return 0;
850}
851
852static void rtl8187_remove_interface(struct ieee80211_hw *dev,
853 struct ieee80211_if_init_conf *conf)
854{
855 struct rtl8187_priv *priv = dev->priv;
7dcdd073 856 mutex_lock(&priv->conf_mutex);
05c914fe 857 priv->mode = NL80211_IFTYPE_MONITOR;
aa979a6a 858 priv->vif = NULL;
7dcdd073 859 mutex_unlock(&priv->conf_mutex);
605bebe2
MW		 860}
861
e8975581 862static int rtl8187_config(struct ieee80211_hw *dev, u32 changed)
605bebe2
MW		 863{
864 struct rtl8187_priv *priv = dev->priv;
e8975581 865 struct ieee80211_conf *conf = &dev->conf;
f6532111
MW		 866 u32 reg;
867
7dcdd073 868 mutex_lock(&priv->conf_mutex);
f6532111
MW		 869 reg = rtl818x_ioread32(priv, &priv->map->TX_CONF);
870 /* Enable TX loopback on MAC level to avoid TX during channel
871 * changes, as this has be seen to causes problems and the
872 * card will stop work until next reset
873 */
874 rtl818x_iowrite32(priv, &priv->map->TX_CONF,
875 reg | RTL818X_TX_CONF_LOOPBACK_MAC);
f6532111
MW		 876 priv->rf->set_chan(dev, conf);
877 msleep(10);
878 rtl818x_iowrite32(priv, &priv->map->TX_CONF, reg);
605bebe2 879
605bebe2
MW		 880 rtl818x_iowrite16(priv, &priv->map->ATIM_WND, 2);
881 rtl818x_iowrite16(priv, &priv->map->ATIMTR_INTERVAL, 100);
882 rtl818x_iowrite16(priv, &priv->map->BEACON_INTERVAL, 100);
883 rtl818x_iowrite16(priv, &priv->map->BEACON_INTERVAL_TIME, 100);
7dcdd073 884 mutex_unlock(&priv->conf_mutex);
605bebe2
MW		 885 return 0;
886}
887
32bfd35d
JB		 888static int rtl8187_config_interface(struct ieee80211_hw *dev,
889 struct ieee80211_vif *vif,
605bebe2
MW		 890 struct ieee80211_if_conf *conf)
891{
892 struct rtl8187_priv *priv = dev->priv;
893 int i;
6f7853f3 894 u8 reg;
605bebe2 895
7dcdd073 896 mutex_lock(&priv->conf_mutex);
605bebe2
MW		 897 for (i = 0; i < ETH_ALEN; i++)
898 rtl818x_iowrite8(priv, &priv->map->BSSID[i], conf->bssid[i]);
899
6f7853f3
HTL		 900 if (is_valid_ether_addr(conf->bssid)) {
901 reg = RTL818X_MSR_INFRA;
902 if (priv->is_rtl8187b)
903 reg |= RTL818X_MSR_ENEDCA;
904 rtl818x_iowrite8(priv, &priv->map->MSR, reg);
905 } else {
906 reg = RTL818X_MSR_NO_LINK;
907 rtl818x_iowrite8(priv, &priv->map->MSR, reg);
908 }
605bebe2 909
7dcdd073 910 mutex_unlock(&priv->conf_mutex);
605bebe2
MW		 911 return 0;
912}
913
f8288317
HRK		 914static void rtl8187_conf_erp(struct rtl8187_priv *priv, bool use_short_slot,
915 bool use_short_preamble)
64761077 916{
f8288317
HRK		 917 if (priv->is_rtl8187b) {
918 u8 difs, eifs, slot_time;
919 u16 ack_timeout;
920
921 if (use_short_slot) {
922 slot_time = 0x9;
923 difs = 0x1c;
924 eifs = 0x53;
925 } else {
926 slot_time = 0x14;
927 difs = 0x32;
928 eifs = 0x5b;
929 }
930 rtl818x_iowrite8(priv, &priv->map->SIFS, 0xa);
931 rtl818x_iowrite8(priv, &priv->map->SLOT, slot_time);
932 rtl818x_iowrite8(priv, &priv->map->DIFS, difs);
933
934 /*
935 * BRSR+1 on 8187B is in fact EIFS register
936 * Value in units of 4 us
937 */
938 rtl818x_iowrite8(priv, (u8 *)&priv->map->BRSR + 1, eifs);
939
940 /*
941 * For 8187B, CARRIER_SENSE_COUNTER is in fact ack timeout
942 * register. In units of 4 us like eifs register
943 * ack_timeout = ack duration + plcp + difs + preamble
944 */
945 ack_timeout = 112 + 48 + difs;
946 if (use_short_preamble)
947 ack_timeout += 72;
948 else
949 ack_timeout += 144;
950 rtl818x_iowrite8(priv, &priv->map->CARRIER_SENSE_COUNTER,
951 DIV_ROUND_UP(ack_timeout, 4));
952 } else {
64761077
HRK		 953 rtl818x_iowrite8(priv, &priv->map->SIFS, 0x22);
954 if (use_short_slot) {
955 rtl818x_iowrite8(priv, &priv->map->SLOT, 0x9);
956 rtl818x_iowrite8(priv, &priv->map->DIFS, 0x14);
957 rtl818x_iowrite8(priv, &priv->map->EIFS, 91 - 0x14);
958 rtl818x_iowrite8(priv, &priv->map->CW_VAL, 0x73);
959 } else {
960 rtl818x_iowrite8(priv, &priv->map->SLOT, 0x14);
961 rtl818x_iowrite8(priv, &priv->map->DIFS, 0x24);
962 rtl818x_iowrite8(priv, &priv->map->EIFS, 91 - 0x24);
963 rtl818x_iowrite8(priv, &priv->map->CW_VAL, 0xa5);
964 }
965 }
966}
967
968static void rtl8187_bss_info_changed(struct ieee80211_hw *dev,
969 struct ieee80211_vif *vif,
970 struct ieee80211_bss_conf *info,
971 u32 changed)
972{
973 struct rtl8187_priv *priv = dev->priv;
974
f8288317
HRK		 975 if (changed & (BSS_CHANGED_ERP_SLOT | BSS_CHANGED_ERP_PREAMBLE))
976 rtl8187_conf_erp(priv, info->use_short_slot,
977 info->use_short_preamble);
64761077
HRK		 978}
979
4150c572
JB		 980static void rtl8187_configure_filter(struct ieee80211_hw *dev,
981 unsigned int changed_flags,
982 unsigned int *total_flags,
2fe14263 983 int mc_count, struct dev_addr_list *mclist)
4150c572
JB		 984{
985 struct rtl8187_priv *priv = dev->priv;
986
4150c572
JB		 987 if (changed_flags & FIF_FCSFAIL)
988 priv->rx_conf ^= RTL818X_RX_CONF_FCS;
989 if (changed_flags & FIF_CONTROL)
990 priv->rx_conf ^= RTL818X_RX_CONF_CTRL;
991 if (changed_flags & FIF_OTHER_BSS)
992 priv->rx_conf ^= RTL818X_RX_CONF_MONITOR;
2fe14263 993 if (*total_flags & FIF_ALLMULTI || mc_count > 0)
4150c572 994 priv->rx_conf |= RTL818X_RX_CONF_MULTICAST;
2fe14263
MW		 995 else
996 priv->rx_conf &= ~RTL818X_RX_CONF_MULTICAST;
997
998 *total_flags = 0;
4150c572 999
4150c572
JB		 1000 if (priv->rx_conf & RTL818X_RX_CONF_FCS)
1001 *total_flags |= FIF_FCSFAIL;
1002 if (priv->rx_conf & RTL818X_RX_CONF_CTRL)
1003 *total_flags |= FIF_CONTROL;
1004 if (priv->rx_conf & RTL818X_RX_CONF_MONITOR)
1005 *total_flags |= FIF_OTHER_BSS;
2fe14263
MW		 1006 if (priv->rx_conf & RTL818X_RX_CONF_MULTICAST)
1007 *total_flags |= FIF_ALLMULTI;
4150c572
JB		 1008
1009 rtl818x_iowrite32_async(priv, &priv->map->RX_CONF, priv->rx_conf);
1010}
1011
605bebe2
MW		 1012static const struct ieee80211_ops rtl8187_ops = {
1013 .tx = rtl8187_tx,
4150c572 1014 .start = rtl8187_start,
605bebe2
MW		 1015 .stop = rtl8187_stop,
1016 .add_interface = rtl8187_add_interface,
1017 .remove_interface = rtl8187_remove_interface,
1018 .config = rtl8187_config,
1019 .config_interface = rtl8187_config_interface,
64761077 1020 .bss_info_changed = rtl8187_bss_info_changed,
4150c572 1021 .configure_filter = rtl8187_configure_filter,
605bebe2
MW		 1022};
1023
1024static void rtl8187_eeprom_register_read(struct eeprom_93cx6 *eeprom)
1025{
1026 struct ieee80211_hw *dev = eeprom->data;
1027 struct rtl8187_priv *priv = dev->priv;
1028 u8 reg = rtl818x_ioread8(priv, &priv->map->EEPROM_CMD);
1029
1030 eeprom->reg_data_in = reg & RTL818X_EEPROM_CMD_WRITE;
1031 eeprom->reg_data_out = reg & RTL818X_EEPROM_CMD_READ;
1032 eeprom->reg_data_clock = reg & RTL818X_EEPROM_CMD_CK;
1033 eeprom->reg_chip_select = reg & RTL818X_EEPROM_CMD_CS;
1034}
1035
1036static void rtl8187_eeprom_register_write(struct eeprom_93cx6 *eeprom)
1037{
1038 struct ieee80211_hw *dev = eeprom->data;
1039 struct rtl8187_priv *priv = dev->priv;
1040 u8 reg = RTL818X_EEPROM_CMD_PROGRAM;
1041
1042 if (eeprom->reg_data_in)
1043 reg |= RTL818X_EEPROM_CMD_WRITE;
1044 if (eeprom->reg_data_out)
1045 reg |= RTL818X_EEPROM_CMD_READ;
1046 if (eeprom->reg_data_clock)
1047 reg |= RTL818X_EEPROM_CMD_CK;
1048 if (eeprom->reg_chip_select)
1049 reg |= RTL818X_EEPROM_CMD_CS;
1050
1051 rtl818x_iowrite8(priv, &priv->map->EEPROM_CMD, reg);
1052 udelay(10);
1053}
1054
1055static int __devinit rtl8187_probe(struct usb_interface *intf,
1056 const struct usb_device_id *id)
1057{
1058 struct usb_device *udev = interface_to_usbdev(intf);
1059 struct ieee80211_hw *dev;
1060 struct rtl8187_priv *priv;
1061 struct eeprom_93cx6 eeprom;
1062 struct ieee80211_channel *channel;
6f7853f3 1063 const char *chip_name;
605bebe2
MW		 1064 u16 txpwr, reg;
1065 int err, i;
1066
1067 dev = ieee80211_alloc_hw(sizeof(*priv), &rtl8187_ops);
1068 if (!dev) {
1069 printk(KERN_ERR "rtl8187: ieee80211 alloc failed\n");
1070 return -ENOMEM;
1071 }
1072
1073 priv = dev->priv;
0e25b4ef 1074 priv->is_rtl8187b = (id->driver_info == DEVICE_RTL8187B);
605bebe2
MW		 1075
1076 SET_IEEE80211_DEV(dev, &intf->dev);
1077 usb_set_intfdata(intf, dev);
1078 priv->udev = udev;
1079
1080 usb_get_dev(udev);
1081
1082 skb_queue_head_init(&priv->rx_queue);
8318d78a
JB		 1083
1084 BUILD_BUG_ON(sizeof(priv->channels) != sizeof(rtl818x_channels));
1085 BUILD_BUG_ON(sizeof(priv->rates) != sizeof(rtl818x_rates));
1086
605bebe2
MW		 1087 memcpy(priv->channels, rtl818x_channels, sizeof(rtl818x_channels));
1088 memcpy(priv->rates, rtl818x_rates, sizeof(rtl818x_rates));
1089 priv->map = (struct rtl818x_csr *)0xFF00;
8318d78a
JB		 1090
1091 priv->band.band = IEEE80211_BAND_2GHZ;
1092 priv->band.channels = priv->channels;
1093 priv->band.n_channels = ARRAY_SIZE(rtl818x_channels);
1094 priv->band.bitrates = priv->rates;
1095 priv->band.n_bitrates = ARRAY_SIZE(rtl818x_rates);
1096 dev->wiphy->bands[IEEE80211_BAND_2GHZ] = &priv->band;
1097
1098
05c914fe 1099 priv->mode = NL80211_IFTYPE_MONITOR;
605bebe2 1100 dev->flags = IEEE80211_HW_HOST_BROADCAST_PS_BUFFERING |
0ccd58fc 1101 IEEE80211_HW_RX_INCLUDES_FCS;
605bebe2 1102
605bebe2
MW		 1103 eeprom.data = dev;
1104 eeprom.register_read = rtl8187_eeprom_register_read;
1105 eeprom.register_write = rtl8187_eeprom_register_write;
1106 if (rtl818x_ioread32(priv, &priv->map->RX_CONF) & (1 << 6))
1107 eeprom.width = PCI_EEPROM_WIDTH_93C66;
1108 else
1109 eeprom.width = PCI_EEPROM_WIDTH_93C46;
1110
1111 rtl818x_iowrite8(priv, &priv->map->EEPROM_CMD, RTL818X_EEPROM_CMD_CONFIG);
1112 udelay(10);
1113
1114 eeprom_93cx6_multiread(&eeprom, RTL8187_EEPROM_MAC_ADDR,
1115 (__le16 __force *)dev->wiphy->perm_addr, 3);
1116 if (!is_valid_ether_addr(dev->wiphy->perm_addr)) {
1117 printk(KERN_WARNING "rtl8187: Invalid hwaddr! Using randomly "
1118 "generated MAC address\n");
1119 random_ether_addr(dev->wiphy->perm_addr);
1120 }
1121
1122 channel = priv->channels;
1123 for (i = 0; i < 3; i++) {
1124 eeprom_93cx6_read(&eeprom, RTL8187_EEPROM_TXPWR_CHAN_1 + i,
1125 &txpwr);
8318d78a
JB		 1126 (*channel++).hw_value = txpwr & 0xFF;
1127 (*channel++).hw_value = txpwr >> 8;
605bebe2
MW		 1128 }
1129 for (i = 0; i < 2; i++) {
1130 eeprom_93cx6_read(&eeprom, RTL8187_EEPROM_TXPWR_CHAN_4 + i,
1131 &txpwr);
8318d78a
JB		 1132 (*channel++).hw_value = txpwr & 0xFF;
1133 (*channel++).hw_value = txpwr >> 8;
605bebe2 1134 }
605bebe2
MW		 1135
1136 eeprom_93cx6_read(&eeprom, RTL8187_EEPROM_TXPWR_BASE,
1137 &priv->txpwr_base);
1138
f6532111
MW		 1139 reg = rtl818x_ioread8(priv, &priv->map->PGSELECT) & ~1;
1140 rtl818x_iowrite8(priv, &priv->map->PGSELECT, reg | 1);
605bebe2
MW		 1141 /* 0 means asic B-cut, we should use SW 3 wire
1142 * bit-by-bit banging for radio. 1 means we can use
1143 * USB specific request to write radio registers */
1144 priv->asic_rev = rtl818x_ioread8(priv, (u8 *)0xFFFE) & 0x3;
f6532111 1145 rtl818x_iowrite8(priv, &priv->map->PGSELECT, reg);
605bebe2
MW		 1146 rtl818x_iowrite8(priv, &priv->map->EEPROM_CMD, RTL818X_EEPROM_CMD_NORMAL);
1147
6f7853f3
HTL		 1148 if (!priv->is_rtl8187b) {
1149 u32 reg32;
1150 reg32 = rtl818x_ioread32(priv, &priv->map->TX_CONF);
1151 reg32 &= RTL818X_TX_CONF_HWVER_MASK;
1152 switch (reg32) {
0e25b4ef
LF		 1153 case RTL818X_TX_CONF_R8187vD_B:
1154 /* Some RTL8187B devices have a USB ID of 0x8187
1155 * detect them here */
1156 chip_name = "RTL8187BvB(early)";
1157 priv->is_rtl8187b = 1;
1158 priv->hw_rev = RTL8187BvB;
1159 break;
1160 case RTL818X_TX_CONF_R8187vD:
6f7853f3
HTL		 1161 chip_name = "RTL8187vD";
1162 break;
1163 default:
1164 chip_name = "RTL8187vB (default)";
1165 }
1166 } else {
6f7853f3
HTL		 1167 /*
1168 * Force USB request to write radio registers for 8187B, Realtek
1169 * only uses it in their sources
1170 */
1171 /*if (priv->asic_rev == 0) {
1172 printk(KERN_WARNING "rtl8187: Forcing use of USB "
1173 "requests to write to radio registers\n");
1174 priv->asic_rev = 1;
1175 }*/
1176 switch (rtl818x_ioread8(priv, (u8 *)0xFFE1)) {
1177 case RTL818X_R8187B_B:
1178 chip_name = "RTL8187BvB";
1179 priv->hw_rev = RTL8187BvB;
1180 break;
1181 case RTL818X_R8187B_D:
1182 chip_name = "RTL8187BvD";
1183 priv->hw_rev = RTL8187BvD;
1184 break;
1185 case RTL818X_R8187B_E:
1186 chip_name = "RTL8187BvE";
1187 priv->hw_rev = RTL8187BvE;
1188 break;
1189 default:
1190 chip_name = "RTL8187BvB (default)";
1191 priv->hw_rev = RTL8187BvB;
1192 }
1193 }
1194
0e25b4ef
LF		 1195 if (!priv->is_rtl8187b) {
1196 for (i = 0; i < 2; i++) {
1197 eeprom_93cx6_read(&eeprom,
1198 RTL8187_EEPROM_TXPWR_CHAN_6 + i,
1199 &txpwr);
1200 (*channel++).hw_value = txpwr & 0xFF;
1201 (*channel++).hw_value = txpwr >> 8;
1202 }
1203 } else {
1204 eeprom_93cx6_read(&eeprom, RTL8187_EEPROM_TXPWR_CHAN_6,
1205 &txpwr);
1206 (*channel++).hw_value = txpwr & 0xFF;
1207
1208 eeprom_93cx6_read(&eeprom, 0x0A, &txpwr);
1209 (*channel++).hw_value = txpwr & 0xFF;
1210
1211 eeprom_93cx6_read(&eeprom, 0x1C, &txpwr);
1212 (*channel++).hw_value = txpwr & 0xFF;
1213 (*channel++).hw_value = txpwr >> 8;
1214 }
1215
0ccd58fc 1216 if (priv->is_rtl8187b) {
0e25b4ef
LF		 1217 printk(KERN_WARNING "rtl8187: 8187B chip detected. Support "
1218 "is EXPERIMENTAL, and could damage your\n"
1219 " hardware, use at your own risk\n");
0ccd58fc
LF		 1220 dev->flags |= IEEE80211_HW_SIGNAL_DBM;
1221 } else {
1222 dev->flags |= IEEE80211_HW_SIGNAL_UNSPEC;
1223 dev->max_signal = 65;
1224 }
1225
94778280
JB		 1226 /*
1227 * XXX: Once this driver supports anything that requires
1228 * beacons it must implement IEEE80211_TX_CTL_ASSIGN_SEQ.
1229 */
f59ac048
LR		 1230 dev->wiphy->interface_modes = BIT(NL80211_IFTYPE_STATION);
1231
0e25b4ef
LF		 1232 if ((id->driver_info == DEVICE_RTL8187) && priv->is_rtl8187b)
1233 printk(KERN_INFO "rtl8187: inconsistency between id with OEM"
1234 " info!\n");
1235
f6532111 1236 priv->rf = rtl8187_detect_rf(dev);
0e25b4ef
LF		 1237 dev->extra_tx_headroom = (!priv->is_rtl8187b) ?
1238 sizeof(struct rtl8187_tx_hdr) :
1239 sizeof(struct rtl8187b_tx_hdr);
1240 if (!priv->is_rtl8187b)
1241 dev->queues = 1;
1242 else
1243 dev->queues = 4;
605bebe2
MW		 1244
1245 err = ieee80211_register_hw(dev);
1246 if (err) {
1247 printk(KERN_ERR "rtl8187: Cannot register device\n");
1248 goto err_free_dev;
1249 }
7dcdd073 1250 mutex_init(&priv->conf_mutex);
605bebe2 1251
e174961c
JB		 1252 printk(KERN_INFO "%s: hwaddr %pM, %s V%d + %s\n",
1253 wiphy_name(dev->wiphy), dev->wiphy->perm_addr,
6f7853f3 1254 chip_name, priv->asic_rev, priv->rf->name);
605bebe2
MW		 1255
1256 return 0;
1257
1258 err_free_dev:
1259 ieee80211_free_hw(dev);
1260 usb_set_intfdata(intf, NULL);
1261 usb_put_dev(udev);
1262 return err;
1263}
1264
1265static void __devexit rtl8187_disconnect(struct usb_interface *intf)
1266{
1267 struct ieee80211_hw *dev = usb_get_intfdata(intf);
1268 struct rtl8187_priv *priv;
1269
1270 if (!dev)
1271 return;
1272
1273 ieee80211_unregister_hw(dev);
1274
1275 priv = dev->priv;
1276 usb_put_dev(interface_to_usbdev(intf));
1277 ieee80211_free_hw(dev);
1278}
1279
1280static struct usb_driver rtl8187_driver = {
1281 .name = KBUILD_MODNAME,
1282 .id_table = rtl8187_table,
1283 .probe = rtl8187_probe,
500c1197 1284 .disconnect = __devexit_p(rtl8187_disconnect),
605bebe2
MW		 1285};
1286
1287static int __init rtl8187_init(void)
1288{
1289 return usb_register(&rtl8187_driver);
1290}
1291
1292static void __exit rtl8187_exit(void)
1293{
1294 usb_deregister(&rtl8187_driver);
1295}
1296
1297module_init(rtl8187_init);
1298module_exit(rtl8187_exit);
Linux kernel - Deliverables
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