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rtlwifi: rtl8192ce: Change rtl8192ce routines phy and trx and modify rtl8192cu for...
[deliverable/linux.git] / drivers / net / wireless / rtlwifi / pci.c
CommitLineData
0c817338
LF		 1/******************************************************************************
2 *
3 * Copyright(c) 2009-2010 Realtek Corporation.
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of version 2 of the GNU General Public License as
7 * published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details.
13 *
14 * You should have received a copy of the GNU General Public License along with
15 * this program; if not, write to the Free Software Foundation, Inc.,
16 * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
17 *
18 * The full GNU General Public License is included in this distribution in the
19 * file called LICENSE.
20 *
21 * Contact Information:
22 * wlanfae <wlanfae@realtek.com>
23 * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
24 * Hsinchu 300, Taiwan.
25 *
26 * Larry Finger <Larry.Finger@lwfinger.net>
27 *
28 *****************************************************************************/
29
30#include "core.h"
31#include "wifi.h"
32#include "pci.h"
33#include "base.h"
34#include "ps.h"
c7cfe38e 35#include "efuse.h"
0c817338
LF		 36
37static const u16 pcibridge_vendors[PCI_BRIDGE_VENDOR_MAX] = {
38 INTEL_VENDOR_ID,
39 ATI_VENDOR_ID,
40 AMD_VENDOR_ID,
41 SIS_VENDOR_ID
42};
43
c7cfe38e
C		 44static const u8 ac_to_hwq[] = {
45 VO_QUEUE,
46 VI_QUEUE,
47 BE_QUEUE,
48 BK_QUEUE
49};
50
51u8 _rtl_mac_to_hwqueue(struct ieee80211_hw *hw,
52 struct sk_buff *skb)
53{
54 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
55 u16 fc = rtl_get_fc(skb);
56 u8 queue_index = skb_get_queue_mapping(skb);
57
58 if (unlikely(ieee80211_is_beacon(fc)))
59 return BEACON_QUEUE;
60 if (ieee80211_is_mgmt(fc))
61 return MGNT_QUEUE;
62 if (rtlhal->hw_type == HARDWARE_TYPE_RTL8192SE)
63 if (ieee80211_is_nullfunc(fc))
64 return HIGH_QUEUE;
65
66 return ac_to_hwq[queue_index];
67}
68
0c817338
LF		 69/* Update PCI dependent default settings*/
70static void _rtl_pci_update_default_setting(struct ieee80211_hw *hw)
71{
72 struct rtl_priv *rtlpriv = rtl_priv(hw);
73 struct rtl_pci_priv *pcipriv = rtl_pcipriv(hw);
74 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
75 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
76 u8 pcibridge_vendor = pcipriv->ndis_adapter.pcibridge_vendor;
c7cfe38e 77 u8 init_aspm;
0c817338
LF		 78
79 ppsc->reg_rfps_level = 0;
7ea47240 80 ppsc->support_aspm = 0;
0c817338
LF		 81
82 /*Update PCI ASPM setting */
83 ppsc->const_amdpci_aspm = rtlpci->const_amdpci_aspm;
84 switch (rtlpci->const_pci_aspm) {
85 case 0:
86 /*No ASPM */
87 break;
88
89 case 1:
90 /*ASPM dynamically enabled/disable. */
91 ppsc->reg_rfps_level |= RT_RF_LPS_LEVEL_ASPM;
92 break;
93
94 case 2:
95 /*ASPM with Clock Req dynamically enabled/disable. */
96 ppsc->reg_rfps_level |= (RT_RF_LPS_LEVEL_ASPM |
97 RT_RF_OFF_LEVL_CLK_REQ);
98 break;
99
100 case 3:
101 /*
102 * Always enable ASPM and Clock Req
103 * from initialization to halt.
104 * */
105 ppsc->reg_rfps_level &= ~(RT_RF_LPS_LEVEL_ASPM);
106 ppsc->reg_rfps_level |= (RT_RF_PS_LEVEL_ALWAYS_ASPM |
107 RT_RF_OFF_LEVL_CLK_REQ);
108 break;
109
110 case 4:
111 /*
112 * Always enable ASPM without Clock Req
113 * from initialization to halt.
114 * */
115 ppsc->reg_rfps_level &= ~(RT_RF_LPS_LEVEL_ASPM |
116 RT_RF_OFF_LEVL_CLK_REQ);
117 ppsc->reg_rfps_level |= RT_RF_PS_LEVEL_ALWAYS_ASPM;
118 break;
119 }
120
121 ppsc->reg_rfps_level |= RT_RF_OFF_LEVL_HALT_NIC;
122
123 /*Update Radio OFF setting */
124 switch (rtlpci->const_hwsw_rfoff_d3) {
125 case 1:
126 if (ppsc->reg_rfps_level & RT_RF_LPS_LEVEL_ASPM)
127 ppsc->reg_rfps_level |= RT_RF_OFF_LEVL_ASPM;
128 break;
129
130 case 2:
131 if (ppsc->reg_rfps_level & RT_RF_LPS_LEVEL_ASPM)
132 ppsc->reg_rfps_level |= RT_RF_OFF_LEVL_ASPM;
133 ppsc->reg_rfps_level |= RT_RF_OFF_LEVL_HALT_NIC;
134 break;
135
136 case 3:
137 ppsc->reg_rfps_level |= RT_RF_OFF_LEVL_PCI_D3;
138 break;
139 }
140
141 /*Set HW definition to determine if it supports ASPM. */
142 switch (rtlpci->const_support_pciaspm) {
c7cfe38e
C		 143 case 0:{
144 /*Not support ASPM. */
145 bool support_aspm = false;
146 ppsc->support_aspm = support_aspm;
147 break;
148 }
149 case 1:{
150 /*Support ASPM. */
151 bool support_aspm = true;
152 bool support_backdoor = true;
153 ppsc->support_aspm = support_aspm;
154
155 /*if (priv->oem_id == RT_CID_TOSHIBA &&
156 !priv->ndis_adapter.amd_l1_patch)
157 support_backdoor = false; */
158
159 ppsc->support_backdoor = support_backdoor;
160
161 break;
162 }
0c817338
LF		 163 case 2:
164 /*ASPM value set by chipset. */
c7cfe38e
C		 165 if (pcibridge_vendor == PCI_BRIDGE_VENDOR_INTEL) {
166 bool support_aspm = true;
167 ppsc->support_aspm = support_aspm;
168 }
0c817338
LF		 169 break;
170 default:
171 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
172 ("switch case not process\n"));
173 break;
174 }
c7cfe38e
C		 175
176 /* toshiba aspm issue, toshiba will set aspm selfly
177 * so we should not set aspm in driver */
178 pci_read_config_byte(rtlpci->pdev, 0x80, &init_aspm);
179 if (rtlpriv->rtlhal.hw_type == HARDWARE_TYPE_RTL8192SE &&
180 init_aspm == 0x43)
181 ppsc->support_aspm = false;
182}
183
184/*Disable L0s dirtectly. We will disable host L0s by default. */
185void rtl_pci_disable_host_l0s(struct ieee80211_hw *hw)
186{
187 struct rtl_priv *rtlpriv = rtl_priv(hw);
188 struct rtl_pci_priv *pcipriv = rtl_pcipriv(hw);
189 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
190 u8 pcibridge_busnum = pcipriv->ndis_adapter.pcibridge_busnum;
191 u8 pcibridge_devnum = pcipriv->ndis_adapter.pcibridge_devnum;
192 u8 pcibridge_funcnum = pcipriv->ndis_adapter.pcibridge_funcnum;
193 u32 pcicfg_addrport = pcipriv->ndis_adapter.pcicfg_addrport;
194 u8 num4bytes = pcipriv->ndis_adapter.num4bytes;
195 u8 u_pcibridge_aspmsetting = 0;
196
197 /*Read Link Control Register */
198 rtl_pci_raw_write_port_ulong(PCI_CONF_ADDRESS,
199 pcicfg_addrport + (num4bytes << 2));
200 rtl_pci_raw_read_port_uchar(PCI_CONF_DATA, &u_pcibridge_aspmsetting);
201
202 if (u_pcibridge_aspmsetting & BIT(0))
203 u_pcibridge_aspmsetting &= ~(BIT(0));
204
205 rtl_pci_raw_write_port_ulong(PCI_CONF_ADDRESS,
206 pcicfg_addrport + (num4bytes << 2));
207 rtl_pci_raw_write_port_uchar(PCI_CONF_DATA, u_pcibridge_aspmsetting);
208
209 udelay(50);
210
211 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
212 ("PciBridge busnumber[%x], DevNumbe[%x], "
213 "funcnumber[%x], Write reg[%x] = %lx\n",
214 pcibridge_busnum, pcibridge_devnum, pcibridge_funcnum,
215 (pcipriv->ndis_adapter.pcibridge_pciehdr_offset + 0x10),
216 (pcipriv->ndis_adapter.pcibridge_linkctrlreg |
217 (rtlpci->const_devicepci_aspm_setting & ~BIT(0)))));
218}
219
220/*Enable rtl8192ce backdoor to control ASPM and clock request.*/
221bool rtl_pci_enable_back_door(struct ieee80211_hw *hw)
222{
223 struct rtl_pci_priv *pcipriv = rtl_pcipriv(hw);
224 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
225 u8 pcibridge_vendor = pcipriv->ndis_adapter.pcibridge_vendor;
226 bool bresult = true;
227 u8 value;
228
229 pci_read_config_byte(rtlpci->pdev, 0x70f, &value);
230
231 /*0x70f BIT(7) is used to control L0S */
232 if (pcibridge_vendor == PCI_BRIDGE_VENDOR_INTEL) {
233 value |= BIT(7);
234 } else {
235 /*Set 0x70f to 0x23 when non-Intel platform. */
236 value = 0x23;
237 }
238
239 pci_write_config_byte(rtlpci->pdev, 0x70f, value);
240
241 pci_read_config_byte(rtlpci->pdev, 0x719, &value);
242 /*0x719 BIT(3) is for L1 BIT(4) is for clock request */
243 value |= (BIT(3) | BIT(4));
244 pci_write_config_byte(rtlpci->pdev, 0x719, value);
245
246 return bresult;
0c817338
LF		 247}
248
249static bool _rtl_pci_platform_switch_device_pci_aspm(
250 struct ieee80211_hw *hw,
251 u8 value)
252{
253 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
c7cfe38e
C		 254 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
255
256 if (rtlhal->hw_type != HARDWARE_TYPE_RTL8192SE)
257 value |= 0x40;
0c817338 258
0c817338
LF		 259 pci_write_config_byte(rtlpci->pdev, 0x80, value);
260
32473284 261 return false;
0c817338
LF		 262}
263
264/*When we set 0x01 to enable clk request. Set 0x0 to disable clk req.*/
265static bool _rtl_pci_switch_clk_req(struct ieee80211_hw *hw, u8 value)
266{
267 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
c7cfe38e 268 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
0c817338 269
0c817338 270 pci_write_config_byte(rtlpci->pdev, 0x81, value);
0c817338 271
c7cfe38e
C		 272 if (rtlhal->hw_type == HARDWARE_TYPE_RTL8192SE)
273 udelay(100);
274
32473284 275 return true;
0c817338
LF		 276}
277
278/*Disable RTL8192SE ASPM & Disable Pci Bridge ASPM*/
279static void rtl_pci_disable_aspm(struct ieee80211_hw *hw)
280{
281 struct rtl_priv *rtlpriv = rtl_priv(hw);
282 struct rtl_pci_priv *pcipriv = rtl_pcipriv(hw);
283 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
284 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
285 u8 pcibridge_vendor = pcipriv->ndis_adapter.pcibridge_vendor;
286 u32 pcicfg_addrport = pcipriv->ndis_adapter.pcicfg_addrport;
287 u8 num4bytes = pcipriv->ndis_adapter.num4bytes;
288 /*Retrieve original configuration settings. */
289 u8 linkctrl_reg = pcipriv->ndis_adapter.linkctrl_reg;
290 u16 pcibridge_linkctrlreg = pcipriv->ndis_adapter.
291 pcibridge_linkctrlreg;
292 u16 aspmlevel = 0;
32473284 293 u8 tmp_u1b = 0;
0c817338 294
c7cfe38e
C		 295 if (!ppsc->support_aspm)
296 return;
297
0c817338
LF		 298 if (pcibridge_vendor == PCI_BRIDGE_VENDOR_UNKNOWN) {
299 RT_TRACE(rtlpriv, COMP_POWER, DBG_TRACE,
300 ("PCI(Bridge) UNKNOWN.\n"));
301
302 return;
303 }
304
305 if (ppsc->reg_rfps_level & RT_RF_OFF_LEVL_CLK_REQ) {
306 RT_CLEAR_PS_LEVEL(ppsc, RT_RF_OFF_LEVL_CLK_REQ);
307 _rtl_pci_switch_clk_req(hw, 0x0);
308 }
309
32473284
LF		 310 /*for promising device will in L0 state after an I/O. */
311 pci_read_config_byte(rtlpci->pdev, 0x80, &tmp_u1b);
0c817338
LF		 312
313 /*Set corresponding value. */
314 aspmlevel |= BIT(0) | BIT(1);
315 linkctrl_reg &= ~aspmlevel;
316 pcibridge_linkctrlreg &= ~(BIT(0) | BIT(1));
317
318 _rtl_pci_platform_switch_device_pci_aspm(hw, linkctrl_reg);
319 udelay(50);
320
321 /*4 Disable Pci Bridge ASPM */
322 rtl_pci_raw_write_port_ulong(PCI_CONF_ADDRESS,
323 pcicfg_addrport + (num4bytes << 2));
324 rtl_pci_raw_write_port_uchar(PCI_CONF_DATA, pcibridge_linkctrlreg);
325
326 udelay(50);
0c817338
LF		 327}
328
329/*
330 *Enable RTL8192SE ASPM & Enable Pci Bridge ASPM for
331 *power saving We should follow the sequence to enable
332 *RTL8192SE first then enable Pci Bridge ASPM
333 *or the system will show bluescreen.
334 */
335static void rtl_pci_enable_aspm(struct ieee80211_hw *hw)
336{
337 struct rtl_priv *rtlpriv = rtl_priv(hw);
338 struct rtl_pci_priv *pcipriv = rtl_pcipriv(hw);
339 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
340 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
341 u8 pcibridge_busnum = pcipriv->ndis_adapter.pcibridge_busnum;
342 u8 pcibridge_devnum = pcipriv->ndis_adapter.pcibridge_devnum;
343 u8 pcibridge_funcnum = pcipriv->ndis_adapter.pcibridge_funcnum;
344 u8 pcibridge_vendor = pcipriv->ndis_adapter.pcibridge_vendor;
345 u32 pcicfg_addrport = pcipriv->ndis_adapter.pcicfg_addrport;
346 u8 num4bytes = pcipriv->ndis_adapter.num4bytes;
347 u16 aspmlevel;
348 u8 u_pcibridge_aspmsetting;
349 u8 u_device_aspmsetting;
350
c7cfe38e
C		 351 if (!ppsc->support_aspm)
352 return;
353
0c817338
LF		 354 if (pcibridge_vendor == PCI_BRIDGE_VENDOR_UNKNOWN) {
355 RT_TRACE(rtlpriv, COMP_POWER, DBG_TRACE,
356 ("PCI(Bridge) UNKNOWN.\n"));
357 return;
358 }
359
360 /*4 Enable Pci Bridge ASPM */
361 rtl_pci_raw_write_port_ulong(PCI_CONF_ADDRESS,
362 pcicfg_addrport + (num4bytes << 2));
363
364 u_pcibridge_aspmsetting =
365 pcipriv->ndis_adapter.pcibridge_linkctrlreg |
366 rtlpci->const_hostpci_aspm_setting;
367
368 if (pcibridge_vendor == PCI_BRIDGE_VENDOR_INTEL)
369 u_pcibridge_aspmsetting &= ~BIT(0);
370
371 rtl_pci_raw_write_port_uchar(PCI_CONF_DATA, u_pcibridge_aspmsetting);
372
373 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
374 ("PlatformEnableASPM():PciBridge busnumber[%x], "
375 "DevNumbe[%x], funcnumber[%x], Write reg[%x] = %x\n",
376 pcibridge_busnum, pcibridge_devnum, pcibridge_funcnum,
377 (pcipriv->ndis_adapter.pcibridge_pciehdr_offset + 0x10),
378 u_pcibridge_aspmsetting));
379
380 udelay(50);
381
382 /*Get ASPM level (with/without Clock Req) */
383 aspmlevel = rtlpci->const_devicepci_aspm_setting;
384 u_device_aspmsetting = pcipriv->ndis_adapter.linkctrl_reg;
385
386 /*_rtl_pci_platform_switch_device_pci_aspm(dev,*/
387 /*(priv->ndis_adapter.linkctrl_reg | ASPMLevel)); */
388
389 u_device_aspmsetting |= aspmlevel;
390
391 _rtl_pci_platform_switch_device_pci_aspm(hw, u_device_aspmsetting);
392
393 if (ppsc->reg_rfps_level & RT_RF_OFF_LEVL_CLK_REQ) {
394 _rtl_pci_switch_clk_req(hw, (ppsc->reg_rfps_level &
395 RT_RF_OFF_LEVL_CLK_REQ) ? 1 : 0);
396 RT_SET_PS_LEVEL(ppsc, RT_RF_OFF_LEVL_CLK_REQ);
397 }
c7cfe38e 398 udelay(100);
0c817338
LF		 399}
400
401static bool rtl_pci_get_amd_l1_patch(struct ieee80211_hw *hw)
402{
403 struct rtl_pci_priv *pcipriv = rtl_pcipriv(hw);
404 u32 pcicfg_addrport = pcipriv->ndis_adapter.pcicfg_addrport;
405
406 bool status = false;
407 u8 offset_e0;
408 unsigned offset_e4;
409
410 rtl_pci_raw_write_port_ulong(PCI_CONF_ADDRESS,
411 pcicfg_addrport + 0xE0);
412 rtl_pci_raw_write_port_uchar(PCI_CONF_DATA, 0xA0);
413
414 rtl_pci_raw_write_port_ulong(PCI_CONF_ADDRESS,
415 pcicfg_addrport + 0xE0);
416 rtl_pci_raw_read_port_uchar(PCI_CONF_DATA, &offset_e0);
417
418 if (offset_e0 == 0xA0) {
419 rtl_pci_raw_write_port_ulong(PCI_CONF_ADDRESS,
420 pcicfg_addrport + 0xE4);
421 rtl_pci_raw_read_port_ulong(PCI_CONF_DATA, &offset_e4);
422 if (offset_e4 & BIT(23))
423 status = true;
424 }
425
426 return status;
427}
428
c7cfe38e 429void rtl_pci_get_linkcontrol_field(struct ieee80211_hw *hw)
0c817338
LF		 430{
431 struct rtl_pci_priv *pcipriv = rtl_pcipriv(hw);
432 u8 capabilityoffset = pcipriv->ndis_adapter.pcibridge_pciehdr_offset;
433 u32 pcicfg_addrport = pcipriv->ndis_adapter.pcicfg_addrport;
434 u8 linkctrl_reg;
c7cfe38e 435 u8 num4bbytes;
0c817338 436
c7cfe38e 437 num4bbytes = (capabilityoffset + 0x10) / 4;
0c817338
LF		 438
439 /*Read Link Control Register */
440 rtl_pci_raw_write_port_ulong(PCI_CONF_ADDRESS,
c7cfe38e 441 pcicfg_addrport + (num4bbytes << 2));
0c817338
LF		 442 rtl_pci_raw_read_port_uchar(PCI_CONF_DATA, &linkctrl_reg);
443
444 pcipriv->ndis_adapter.pcibridge_linkctrlreg = linkctrl_reg;
445}
446
447static void rtl_pci_parse_configuration(struct pci_dev *pdev,
448 struct ieee80211_hw *hw)
449{
450 struct rtl_priv *rtlpriv = rtl_priv(hw);
451 struct rtl_pci_priv *pcipriv = rtl_pcipriv(hw);
452
453 u8 tmp;
454 int pos;
455 u8 linkctrl_reg;
456
457 /*Link Control Register */
458 pos = pci_find_capability(pdev, PCI_CAP_ID_EXP);
459 pci_read_config_byte(pdev, pos + PCI_EXP_LNKCTL, &linkctrl_reg);
460 pcipriv->ndis_adapter.linkctrl_reg = linkctrl_reg;
461
462 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
463 ("Link Control Register =%x\n",
464 pcipriv->ndis_adapter.linkctrl_reg));
465
466 pci_read_config_byte(pdev, 0x98, &tmp);
467 tmp |= BIT(4);
468 pci_write_config_byte(pdev, 0x98, tmp);
469
470 tmp = 0x17;
471 pci_write_config_byte(pdev, 0x70f, tmp);
472}
473
c7cfe38e 474static void rtl_pci_init_aspm(struct ieee80211_hw *hw)
0c817338
LF		 475{
476 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
477
478 _rtl_pci_update_default_setting(hw);
479
480 if (ppsc->reg_rfps_level & RT_RF_PS_LEVEL_ALWAYS_ASPM) {
481 /*Always enable ASPM & Clock Req. */
482 rtl_pci_enable_aspm(hw);
483 RT_SET_PS_LEVEL(ppsc, RT_RF_PS_LEVEL_ALWAYS_ASPM);
484 }
485
486}
487
0c817338
LF		 488static void _rtl_pci_io_handler_init(struct device *dev,
489 struct ieee80211_hw *hw)
490{
491 struct rtl_priv *rtlpriv = rtl_priv(hw);
492
493 rtlpriv->io.dev = dev;
494
495 rtlpriv->io.write8_async = pci_write8_async;
496 rtlpriv->io.write16_async = pci_write16_async;
497 rtlpriv->io.write32_async = pci_write32_async;
498
499 rtlpriv->io.read8_sync = pci_read8_sync;
500 rtlpriv->io.read16_sync = pci_read16_sync;
501 rtlpriv->io.read32_sync = pci_read32_sync;
502
503}
504
505static void _rtl_pci_io_handler_release(struct ieee80211_hw *hw)
506{
507}
508
c7cfe38e
C		 509static bool _rtl_update_earlymode_info(struct ieee80211_hw *hw,
510 struct sk_buff *skb, struct rtl_tcb_desc *tcb_desc, u8 tid)
511{
512 struct rtl_priv *rtlpriv = rtl_priv(hw);
513 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
514 u8 additionlen = FCS_LEN;
515 struct sk_buff *next_skb;
516
517 /* here open is 4, wep/tkip is 8, aes is 12*/
518 if (info->control.hw_key)
519 additionlen += info->control.hw_key->icv_len;
520
521 /* The most skb num is 6 */
522 tcb_desc->empkt_num = 0;
523 spin_lock_bh(&rtlpriv->locks.waitq_lock);
524 skb_queue_walk(&rtlpriv->mac80211.skb_waitq[tid], next_skb) {
525 struct ieee80211_tx_info *next_info;
526
527 next_info = IEEE80211_SKB_CB(next_skb);
528 if (next_info->flags & IEEE80211_TX_CTL_AMPDU) {
529 tcb_desc->empkt_len[tcb_desc->empkt_num] =
530 next_skb->len + additionlen;
531 tcb_desc->empkt_num++;
532 } else {
533 break;
534 }
535
536 if (skb_queue_is_last(&rtlpriv->mac80211.skb_waitq[tid],
537 next_skb))
538 break;
539
540 if (tcb_desc->empkt_num >= 5)
541 break;
542 }
543 spin_unlock_bh(&rtlpriv->locks.waitq_lock);
544
545 return true;
546}
547
548/* just for early mode now */
549static void _rtl_pci_tx_chk_waitq(struct ieee80211_hw *hw)
550{
551 struct rtl_priv *rtlpriv = rtl_priv(hw);
552 struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
553 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
554 struct sk_buff *skb = NULL;
555 struct ieee80211_tx_info *info = NULL;
556 int tid; /* should be int */
557
558 if (!rtlpriv->rtlhal.earlymode_enable)
559 return;
560
561 /* we juse use em for BE/BK/VI/VO */
562 for (tid = 7; tid >= 0; tid--) {
563 u8 hw_queue = ac_to_hwq[rtl_tid_to_ac(hw, tid)];
564 struct rtl8192_tx_ring *ring = &rtlpci->tx_ring[hw_queue];
565 while (!mac->act_scanning &&
566 rtlpriv->psc.rfpwr_state == ERFON) {
567 struct rtl_tcb_desc tcb_desc;
568 memset(&tcb_desc, 0, sizeof(struct rtl_tcb_desc));
569
570 spin_lock_bh(&rtlpriv->locks.waitq_lock);
571 if (!skb_queue_empty(&mac->skb_waitq[tid]) &&
572 (ring->entries - skb_queue_len(&ring->queue) > 5)) {
573 skb = skb_dequeue(&mac->skb_waitq[tid]);
574 } else {
575 spin_unlock_bh(&rtlpriv->locks.waitq_lock);
576 break;
577 }
578 spin_unlock_bh(&rtlpriv->locks.waitq_lock);
579
580 /* Some macaddr can't do early mode. like
581 * multicast/broadcast/no_qos data */
582 info = IEEE80211_SKB_CB(skb);
583 if (info->flags & IEEE80211_TX_CTL_AMPDU)
584 _rtl_update_earlymode_info(hw, skb,
585 &tcb_desc, tid);
586
c7cfe38e 587 rtlpriv->intf_ops->adapter_tx(hw, skb, &tcb_desc);
c7cfe38e
C		 588 }
589 }
590}
591
592
0c817338
LF		 593static void _rtl_pci_tx_isr(struct ieee80211_hw *hw, int prio)
594{
595 struct rtl_priv *rtlpriv = rtl_priv(hw);
596 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
597
598 struct rtl8192_tx_ring *ring = &rtlpci->tx_ring[prio];
599
600 while (skb_queue_len(&ring->queue)) {
601 struct rtl_tx_desc *entry = &ring->desc[ring->idx];
602 struct sk_buff *skb;
603 struct ieee80211_tx_info *info;
c7cfe38e
C		 604 __le16 fc;
605 u8 tid;
0c817338
LF		 606
607 u8 own = (u8) rtlpriv->cfg->ops->get_desc((u8 *) entry, true,
608 HW_DESC_OWN);
609
610 /*
611 *beacon packet will only use the first
612 *descriptor defautly,and the own may not
613 *be cleared by the hardware
614 */
615 if (own)
616 return;
617 ring->idx = (ring->idx + 1) % ring->entries;
618
619 skb = __skb_dequeue(&ring->queue);
620 pci_unmap_single(rtlpci->pdev,
c7cfe38e 621 le32_to_cpu(rtlpriv->cfg->ops->
0c817338 622 get_desc((u8 *) entry, true,
c7cfe38e 623 HW_DESC_TXBUFF_ADDR)),
0c817338
LF		 624 skb->len, PCI_DMA_TODEVICE);
625
c7cfe38e
C		 626 /* remove early mode header */
627 if (rtlpriv->rtlhal.earlymode_enable)
628 skb_pull(skb, EM_HDR_LEN);
629
0c817338
LF		 630 RT_TRACE(rtlpriv, (COMP_INTR | COMP_SEND), DBG_TRACE,
631 ("new ring->idx:%d, "
632 "free: skb_queue_len:%d, free: seq:%x\n",
633 ring->idx,
634 skb_queue_len(&ring->queue),
635 *(u16 *) (skb->data + 22)));
636
c7cfe38e
C		 637 if (prio == TXCMD_QUEUE) {
638 dev_kfree_skb(skb);
639 goto tx_status_ok;
640
641 }
642
643 /* for sw LPS, just after NULL skb send out, we can
644 * sure AP kown we are sleeped, our we should not let
645 * rf to sleep*/
646 fc = rtl_get_fc(skb);
647 if (ieee80211_is_nullfunc(fc)) {
648 if (ieee80211_has_pm(fc)) {
649 rtlpriv->mac80211.offchan_deley = true;
650 rtlpriv->psc.state_inap = 1;
651 } else {
652 rtlpriv->psc.state_inap = 0;
653 }
654 }
655
656 /* update tid tx pkt num */
657 tid = rtl_get_tid(skb);
658 if (tid <= 7)
659 rtlpriv->link_info.tidtx_inperiod[tid]++;
660
0c817338
LF		 661 info = IEEE80211_SKB_CB(skb);
662 ieee80211_tx_info_clear_status(info);
663
664 info->flags |= IEEE80211_TX_STAT_ACK;
665 /*info->status.rates[0].count = 1; */
666
667 ieee80211_tx_status_irqsafe(hw, skb);
668
669 if ((ring->entries - skb_queue_len(&ring->queue))
670 == 2) {
671
672 RT_TRACE(rtlpriv, COMP_ERR, DBG_LOUD,
673 ("more desc left, wake"
674 "skb_queue@%d,ring->idx = %d,"
675 "skb_queue_len = 0x%d\n",
676 prio, ring->idx,
677 skb_queue_len(&ring->queue)));
678
679 ieee80211_wake_queue(hw,
680 skb_get_queue_mapping
681 (skb));
682 }
c7cfe38e 683tx_status_ok:
0c817338
LF		 684 skb = NULL;
685 }
686
687 if (((rtlpriv->link_info.num_rx_inperiod +
688 rtlpriv->link_info.num_tx_inperiod) > 8) ||
689 (rtlpriv->link_info.num_rx_inperiod > 2)) {
690 rtl_lps_leave(hw);
691 }
692}
693
694static void _rtl_pci_rx_interrupt(struct ieee80211_hw *hw)
695{
696 struct rtl_priv *rtlpriv = rtl_priv(hw);
697 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
698 int rx_queue_idx = RTL_PCI_RX_MPDU_QUEUE;
699
700 struct ieee80211_rx_status rx_status = { 0 };
701 unsigned int count = rtlpci->rxringcount;
702 u8 own;
703 u8 tmp_one;
704 u32 bufferaddress;
705 bool unicast = false;
706
707 struct rtl_stats stats = {
708 .signal = 0,
709 .noise = -98,
710 .rate = 0,
711 };
712
713 /*RX NORMAL PKT */
714 while (count--) {
715 /*rx descriptor */
716 struct rtl_rx_desc *pdesc = &rtlpci->rx_ring[rx_queue_idx].desc[
717 rtlpci->rx_ring[rx_queue_idx].idx];
718 /*rx pkt */
719 struct sk_buff *skb = rtlpci->rx_ring[rx_queue_idx].rx_buf[
720 rtlpci->rx_ring[rx_queue_idx].idx];
721
722 own = (u8) rtlpriv->cfg->ops->get_desc((u8 *) pdesc,
723 false, HW_DESC_OWN);
724
725 if (own) {
726 /*wait data to be filled by hardware */
727 return;
728 } else {
729 struct ieee80211_hdr *hdr;
17c9ac62 730 __le16 fc;
0c817338
LF		 731 struct sk_buff *new_skb = NULL;
732
733 rtlpriv->cfg->ops->query_rx_desc(hw, &stats,
734 &rx_status,
735 (u8 *) pdesc, skb);
736
737 pci_unmap_single(rtlpci->pdev,
738 *((dma_addr_t *) skb->cb),
739 rtlpci->rxbuffersize,
740 PCI_DMA_FROMDEVICE);
741
742 skb_put(skb, rtlpriv->cfg->ops->get_desc((u8 *) pdesc,
743 false,
744 HW_DESC_RXPKT_LEN));
745 skb_reserve(skb,
746 stats.rx_drvinfo_size + stats.rx_bufshift);
747
748 /*
749 *NOTICE This can not be use for mac80211,
750 *this is done in mac80211 code,
751 *if you done here sec DHCP will fail
752 *skb_trim(skb, skb->len - 4);
753 */
754
c7cfe38e
C		 755 hdr = rtl_get_hdr(skb);
756 fc = rtl_get_fc(skb);
0c817338 757
c7cfe38e 758 if (!stats.crc || !stats.hwerror) {
0c817338
LF		 759 memcpy(IEEE80211_SKB_RXCB(skb), &rx_status,
760 sizeof(rx_status));
761
c7cfe38e 762 if (is_broadcast_ether_addr(hdr->addr1)) {
0c817338 763 ;/*TODO*/
c7cfe38e
C		 764 } else if (is_multicast_ether_addr(hdr->addr1)) {
765 ;/*TODO*/
766 } else {
767 unicast = true;
768 rtlpriv->stats.rxbytesunicast +=
769 skb->len;
0c817338
LF		 770 }
771
772 rtl_is_special_data(hw, skb, false);
773
774 if (ieee80211_is_data(fc)) {
775 rtlpriv->cfg->ops->led_control(hw,
776 LED_CTL_RX);
777
778 if (unicast)
779 rtlpriv->link_info.
780 num_rx_inperiod++;
781 }
782
c7cfe38e
C		 783 /* for sw lps */
784 rtl_swlps_beacon(hw, (void *)skb->data,
785 skb->len);
786 rtl_recognize_peer(hw, (void *)skb->data,
787 skb->len);
788 if ((rtlpriv->mac80211.opmode ==
789 NL80211_IFTYPE_AP) &&
790 (rtlpriv->rtlhal.current_bandtype ==
791 BAND_ON_2_4G) &&
792 (ieee80211_is_beacon(fc) ||
793 ieee80211_is_probe_resp(fc))) {
0c817338 794 dev_kfree_skb_any(skb);
5c4bc1ce 795 } else {
c7cfe38e
C		 796 if (unlikely(!rtl_action_proc(hw, skb,
797 false))) {
798 dev_kfree_skb_any(skb);
799 } else {
800 struct sk_buff *uskb = NULL;
801 u8 *pdata;
802 uskb = dev_alloc_skb(skb->len
803 + 128);
804 memcpy(IEEE80211_SKB_RXCB(uskb),
805 &rx_status,
806 sizeof(rx_status));
807 pdata = (u8 *)skb_put(uskb,
808 skb->len);
809 memcpy(pdata, skb->data,
810 skb->len);
811 dev_kfree_skb_any(skb);
812
813 ieee80211_rx_irqsafe(hw, uskb);
bdc4bf65 814 }
5c4bc1ce 815 }
0c817338
LF		 816 } else {
817 dev_kfree_skb_any(skb);
818 }
819
820 if (((rtlpriv->link_info.num_rx_inperiod +
821 rtlpriv->link_info.num_tx_inperiod) > 8) ||
822 (rtlpriv->link_info.num_rx_inperiod > 2)) {
823 rtl_lps_leave(hw);
824 }
825
826 new_skb = dev_alloc_skb(rtlpci->rxbuffersize);
827 if (unlikely(!new_skb)) {
828 RT_TRACE(rtlpriv, (COMP_INTR | COMP_RECV),
c7cfe38e 829 DBG_DMESG,
0c817338
LF		 830 ("can't alloc skb for rx\n"));
831 goto done;
832 }
833 skb = new_skb;
834 /*skb->dev = dev; */
835
836 rtlpci->rx_ring[rx_queue_idx].rx_buf[rtlpci->
837 rx_ring
838 [rx_queue_idx].
839 idx] = skb;
840 *((dma_addr_t *) skb->cb) =
841 pci_map_single(rtlpci->pdev, skb_tail_pointer(skb),
842 rtlpci->rxbuffersize,
843 PCI_DMA_FROMDEVICE);
844
845 }
846done:
c7cfe38e 847 bufferaddress = cpu_to_le32(*((dma_addr_t *)skb->cb));
0c817338
LF		 848 tmp_one = 1;
849 rtlpriv->cfg->ops->set_desc((u8 *) pdesc, false,
850 HW_DESC_RXBUFF_ADDR,
851 (u8 *)&bufferaddress);
852 rtlpriv->cfg->ops->set_desc((u8 *)pdesc, false, HW_DESC_RXOWN,
853 (u8 *)&tmp_one);
854 rtlpriv->cfg->ops->set_desc((u8 *)pdesc, false,
855 HW_DESC_RXPKT_LEN,
856 (u8 *)&rtlpci->rxbuffersize);
857
858 if (rtlpci->rx_ring[rx_queue_idx].idx ==
859 rtlpci->rxringcount - 1)
860 rtlpriv->cfg->ops->set_desc((u8 *)pdesc, false,
861 HW_DESC_RXERO,
862 (u8 *)&tmp_one);
863
864 rtlpci->rx_ring[rx_queue_idx].idx =
865 (rtlpci->rx_ring[rx_queue_idx].idx + 1) %
866 rtlpci->rxringcount;
867 }
868
869}
870
c7cfe38e
C		 871void _rtl_pci_tx_interrupt(struct ieee80211_hw *hw)
872{
873 struct rtl_priv *rtlpriv = rtl_priv(hw);
874 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
875 int prio;
876
877 for (prio = 0; prio < RTL_PCI_MAX_TX_QUEUE_COUNT; prio++) {
878 struct rtl8192_tx_ring *ring = &rtlpci->tx_ring[prio];
879
880 while (skb_queue_len(&ring->queue)) {
881 struct rtl_tx_desc *entry = &ring->desc[ring->idx];
882 struct sk_buff *skb;
883 struct ieee80211_tx_info *info;
884 u8 own;
885
886 /*
887 *beacon packet will only use the first
888 *descriptor defautly, and the own may not
889 *be cleared by the hardware, and
890 *beacon will free in prepare beacon
891 */
892 if (prio == BEACON_QUEUE || prio == TXCMD_QUEUE ||
893 prio == HCCA_QUEUE)
894 break;
895
896 own = (u8) rtlpriv->cfg->ops->get_desc((u8 *) entry,
897 true,
898 HW_DESC_OWN);
899
900 if (own)
901 break;
902
903 skb = __skb_dequeue(&ring->queue);
904 pci_unmap_single(rtlpci->pdev,
905 le32_to_cpu(rtlpriv->cfg->ops->
906 get_desc((u8 *) entry,
907 true,
908 HW_DESC_TXBUFF_ADDR)),
909 skb->len, PCI_DMA_TODEVICE);
910
911 ring->idx = (ring->idx + 1) % ring->entries;
912
913 info = IEEE80211_SKB_CB(skb);
914 ieee80211_tx_info_clear_status(info);
915
916 info->flags |= IEEE80211_TX_STAT_ACK;
917 /*info->status.rates[0].count = 1; */
918
919 ieee80211_tx_status_irqsafe(hw, skb);
920
921 if ((ring->entries - skb_queue_len(&ring->queue))
922 == 2 && prio != BEACON_QUEUE) {
923 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
924 ("more desc left, wake "
925 "skb_queue@%d,ring->idx = %d,"
926 "skb_queue_len = 0x%d\n",
927 prio, ring->idx,
928 skb_queue_len(&ring->queue)));
929
930 ieee80211_wake_queue(hw,
931 skb_get_queue_mapping
932 (skb));
933 }
934
935 skb = NULL;
936 }
937 }
938}
939
0c817338
LF		 940static irqreturn_t _rtl_pci_interrupt(int irq, void *dev_id)
941{
942 struct ieee80211_hw *hw = dev_id;
943 struct rtl_priv *rtlpriv = rtl_priv(hw);
944 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
c7cfe38e 945 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
0c817338
LF		 946 unsigned long flags;
947 u32 inta = 0;
948 u32 intb = 0;
949
950 if (rtlpci->irq_enabled == 0)
951 return IRQ_HANDLED;
952
953 spin_lock_irqsave(&rtlpriv->locks.irq_th_lock, flags);
954
955 /*read ISR: 4/8bytes */
956 rtlpriv->cfg->ops->interrupt_recognized(hw, &inta, &intb);
957
958 /*Shared IRQ or HW disappared */
959 if (!inta || inta == 0xffff)
960 goto done;
961
962 /*<1> beacon related */
963 if (inta & rtlpriv->cfg->maps[RTL_IMR_TBDOK]) {
964 RT_TRACE(rtlpriv, COMP_INTR, DBG_TRACE,
965 ("beacon ok interrupt!\n"));
966 }
967
968 if (unlikely(inta & rtlpriv->cfg->maps[RTL_IMR_TBDER])) {
969 RT_TRACE(rtlpriv, COMP_INTR, DBG_TRACE,
970 ("beacon err interrupt!\n"));
971 }
972
973 if (inta & rtlpriv->cfg->maps[RTL_IMR_BDOK]) {
974 RT_TRACE(rtlpriv, COMP_INTR, DBG_TRACE,
975 ("beacon interrupt!\n"));
976 }
977
978 if (inta & rtlpriv->cfg->maps[RTL_IMR_BcnInt]) {
979 RT_TRACE(rtlpriv, COMP_INTR, DBG_TRACE,
980 ("prepare beacon for interrupt!\n"));
981 tasklet_schedule(&rtlpriv->works.irq_prepare_bcn_tasklet);
982 }
983
984 /*<3> Tx related */
985 if (unlikely(inta & rtlpriv->cfg->maps[RTL_IMR_TXFOVW]))
986 RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING, ("IMR_TXFOVW!\n"));
987
988 if (inta & rtlpriv->cfg->maps[RTL_IMR_MGNTDOK]) {
989 RT_TRACE(rtlpriv, COMP_INTR, DBG_TRACE,
990 ("Manage ok interrupt!\n"));
991 _rtl_pci_tx_isr(hw, MGNT_QUEUE);
992 }
993
994 if (inta & rtlpriv->cfg->maps[RTL_IMR_HIGHDOK]) {
995 RT_TRACE(rtlpriv, COMP_INTR, DBG_TRACE,
996 ("HIGH_QUEUE ok interrupt!\n"));
997 _rtl_pci_tx_isr(hw, HIGH_QUEUE);
998 }
999
1000 if (inta & rtlpriv->cfg->maps[RTL_IMR_BKDOK]) {
1001 rtlpriv->link_info.num_tx_inperiod++;
1002
1003 RT_TRACE(rtlpriv, COMP_INTR, DBG_TRACE,
1004 ("BK Tx OK interrupt!\n"));
1005 _rtl_pci_tx_isr(hw, BK_QUEUE);
1006 }
1007
1008 if (inta & rtlpriv->cfg->maps[RTL_IMR_BEDOK]) {
1009 rtlpriv->link_info.num_tx_inperiod++;
1010
1011 RT_TRACE(rtlpriv, COMP_INTR, DBG_TRACE,
1012 ("BE TX OK interrupt!\n"));
1013 _rtl_pci_tx_isr(hw, BE_QUEUE);
1014 }
1015
1016 if (inta & rtlpriv->cfg->maps[RTL_IMR_VIDOK]) {
1017 rtlpriv->link_info.num_tx_inperiod++;
1018
1019 RT_TRACE(rtlpriv, COMP_INTR, DBG_TRACE,
1020 ("VI TX OK interrupt!\n"));
1021 _rtl_pci_tx_isr(hw, VI_QUEUE);
1022 }
1023
1024 if (inta & rtlpriv->cfg->maps[RTL_IMR_VODOK]) {
1025 rtlpriv->link_info.num_tx_inperiod++;
1026
1027 RT_TRACE(rtlpriv, COMP_INTR, DBG_TRACE,
1028 ("Vo TX OK interrupt!\n"));
1029 _rtl_pci_tx_isr(hw, VO_QUEUE);
1030 }
1031
c7cfe38e
C		 1032 if (rtlhal->hw_type == HARDWARE_TYPE_RTL8192SE) {
1033 if (inta & rtlpriv->cfg->maps[RTL_IMR_COMDOK]) {
1034 rtlpriv->link_info.num_tx_inperiod++;
1035
1036 RT_TRACE(rtlpriv, COMP_INTR, DBG_TRACE,
1037 ("CMD TX OK interrupt!\n"));
1038 _rtl_pci_tx_isr(hw, TXCMD_QUEUE);
1039 }
1040 }
1041
0c817338
LF		 1042 /*<2> Rx related */
1043 if (inta & rtlpriv->cfg->maps[RTL_IMR_ROK]) {
1044 RT_TRACE(rtlpriv, COMP_INTR, DBG_TRACE, ("Rx ok interrupt!\n"));
c7cfe38e 1045 _rtl_pci_rx_interrupt(hw);
0c817338
LF		 1046 }
1047
1048 if (unlikely(inta & rtlpriv->cfg->maps[RTL_IMR_RDU])) {
1049 RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING,
1050 ("rx descriptor unavailable!\n"));
c7cfe38e 1051 _rtl_pci_rx_interrupt(hw);
0c817338
LF		 1052 }
1053
1054 if (unlikely(inta & rtlpriv->cfg->maps[RTL_IMR_RXFOVW])) {
1055 RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING, ("rx overflow !\n"));
c7cfe38e 1056 _rtl_pci_rx_interrupt(hw);
0c817338
LF		 1057 }
1058
c7cfe38e
C		 1059 if (rtlpriv->rtlhal.earlymode_enable)
1060 tasklet_schedule(&rtlpriv->works.irq_tasklet);
1061
0c817338
LF		 1062 spin_unlock_irqrestore(&rtlpriv->locks.irq_th_lock, flags);
1063 return IRQ_HANDLED;
1064
1065done:
1066 spin_unlock_irqrestore(&rtlpriv->locks.irq_th_lock, flags);
1067 return IRQ_HANDLED;
1068}
1069
1070static void _rtl_pci_irq_tasklet(struct ieee80211_hw *hw)
1071{
c7cfe38e 1072 _rtl_pci_tx_chk_waitq(hw);
0c817338
LF		 1073}
1074
1075static void _rtl_pci_prepare_bcn_tasklet(struct ieee80211_hw *hw)
1076{
1077 struct rtl_priv *rtlpriv = rtl_priv(hw);
1078 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
1079 struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
c7cfe38e 1080 struct rtl8192_tx_ring *ring = NULL;
0c817338
LF		 1081 struct ieee80211_hdr *hdr = NULL;
1082 struct ieee80211_tx_info *info = NULL;
1083 struct sk_buff *pskb = NULL;
1084 struct rtl_tx_desc *pdesc = NULL;
c7cfe38e 1085 struct rtl_tcb_desc tcb_desc;
0c817338
LF		 1086 u8 temp_one = 1;
1087
c7cfe38e 1088 memset(&tcb_desc, 0, sizeof(struct rtl_tcb_desc));
0c817338
LF		 1089 ring = &rtlpci->tx_ring[BEACON_QUEUE];
1090 pskb = __skb_dequeue(&ring->queue);
1091 if (pskb)
1092 kfree_skb(pskb);
1093
1094 /*NB: the beacon data buffer must be 32-bit aligned. */
1095 pskb = ieee80211_beacon_get(hw, mac->vif);
1096 if (pskb == NULL)
1097 return;
c7cfe38e 1098 hdr = rtl_get_hdr(pskb);
0c817338 1099 info = IEEE80211_SKB_CB(pskb);
0c817338
LF		 1100 pdesc = &ring->desc[0];
1101 rtlpriv->cfg->ops->fill_tx_desc(hw, hdr, (u8 *) pdesc,
c7cfe38e 1102 info, pskb, BEACON_QUEUE, &tcb_desc);
0c817338
LF		 1103
1104 __skb_queue_tail(&ring->queue, pskb);
1105
1106 rtlpriv->cfg->ops->set_desc((u8 *) pdesc, true, HW_DESC_OWN,
1107 (u8 *)&temp_one);
1108
1109 return;
1110}
1111
1112static void _rtl_pci_init_trx_var(struct ieee80211_hw *hw)
1113{
1114 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
1115 u8 i;
1116
1117 for (i = 0; i < RTL_PCI_MAX_TX_QUEUE_COUNT; i++)
1118 rtlpci->txringcount[i] = RT_TXDESC_NUM;
1119
1120 /*
1121 *we just alloc 2 desc for beacon queue,
1122 *because we just need first desc in hw beacon.
1123 */
1124 rtlpci->txringcount[BEACON_QUEUE] = 2;
1125
1126 /*
1127 *BE queue need more descriptor for performance
1128 *consideration or, No more tx desc will happen,
1129 *and may cause mac80211 mem leakage.
1130 */
1131 rtlpci->txringcount[BE_QUEUE] = RT_TXDESC_NUM_BE_QUEUE;
1132
1133 rtlpci->rxbuffersize = 9100; /*2048/1024; */
1134 rtlpci->rxringcount = RTL_PCI_MAX_RX_COUNT; /*64; */
1135}
1136
1137static void _rtl_pci_init_struct(struct ieee80211_hw *hw,
1138 struct pci_dev *pdev)
1139{
1140 struct rtl_priv *rtlpriv = rtl_priv(hw);
1141 struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
1142 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
1143 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
0c817338
LF		 1144
1145 rtlpci->up_first_time = true;
1146 rtlpci->being_init_adapter = false;
1147
1148 rtlhal->hw = hw;
1149 rtlpci->pdev = pdev;
1150
0c817338
LF		 1151 /*Tx/Rx related var */
1152 _rtl_pci_init_trx_var(hw);
1153
c7cfe38e 1154 /*IBSS*/ mac->beacon_interval = 100;
0c817338 1155
c7cfe38e
C		 1156 /*AMPDU*/
1157 mac->min_space_cfg = 0;
0c817338
LF		 1158 mac->max_mss_density = 0;
1159 /*set sane AMPDU defaults */
1160 mac->current_ampdu_density = 7;
1161 mac->current_ampdu_factor = 3;
1162
c7cfe38e
C		 1163 /*QOS*/
1164 rtlpci->acm_method = eAcmWay2_SW;
0c817338
LF		 1165
1166 /*task */
1167 tasklet_init(&rtlpriv->works.irq_tasklet,
1168 (void (*)(unsigned long))_rtl_pci_irq_tasklet,
1169 (unsigned long)hw);
1170 tasklet_init(&rtlpriv->works.irq_prepare_bcn_tasklet,
1171 (void (*)(unsigned long))_rtl_pci_prepare_bcn_tasklet,
1172 (unsigned long)hw);
1173}
1174
1175static int _rtl_pci_init_tx_ring(struct ieee80211_hw *hw,
1176 unsigned int prio, unsigned int entries)
1177{
1178 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
1179 struct rtl_priv *rtlpriv = rtl_priv(hw);
1180 struct rtl_tx_desc *ring;
1181 dma_addr_t dma;
1182 u32 nextdescaddress;
1183 int i;
1184
1185 ring = pci_alloc_consistent(rtlpci->pdev,
1186 sizeof(*ring) * entries, &dma);
1187
1188 if (!ring || (unsigned long)ring & 0xFF) {
1189 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
1190 ("Cannot allocate TX ring (prio = %d)\n", prio));
1191 return -ENOMEM;
1192 }
1193
1194 memset(ring, 0, sizeof(*ring) * entries);
1195 rtlpci->tx_ring[prio].desc = ring;
1196 rtlpci->tx_ring[prio].dma = dma;
1197 rtlpci->tx_ring[prio].idx = 0;
1198 rtlpci->tx_ring[prio].entries = entries;
1199 skb_queue_head_init(&rtlpci->tx_ring[prio].queue);
1200
1201 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
1202 ("queue:%d, ring_addr:%p\n", prio, ring));
1203
1204 for (i = 0; i < entries; i++) {
c7cfe38e
C		 1205 nextdescaddress = cpu_to_le32((u32) dma +
1206 ((i + 11) % entries) *
1207 sizeof(*ring));
0c817338
LF		 1208
1209 rtlpriv->cfg->ops->set_desc((u8 *)&(ring[i]),
1210 true, HW_DESC_TX_NEXTDESC_ADDR,
1211 (u8 *)&nextdescaddress);
1212 }
1213
1214 return 0;
1215}
1216
1217static int _rtl_pci_init_rx_ring(struct ieee80211_hw *hw)
1218{
1219 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
1220 struct rtl_priv *rtlpriv = rtl_priv(hw);
1221 struct rtl_rx_desc *entry = NULL;
1222 int i, rx_queue_idx;
1223 u8 tmp_one = 1;
1224
1225 /*
1226 *rx_queue_idx 0:RX_MPDU_QUEUE
1227 *rx_queue_idx 1:RX_CMD_QUEUE
1228 */
1229 for (rx_queue_idx = 0; rx_queue_idx < RTL_PCI_MAX_RX_QUEUE;
1230 rx_queue_idx++) {
1231 rtlpci->rx_ring[rx_queue_idx].desc =
1232 pci_alloc_consistent(rtlpci->pdev,
1233 sizeof(*rtlpci->rx_ring[rx_queue_idx].
1234 desc) * rtlpci->rxringcount,
1235 &rtlpci->rx_ring[rx_queue_idx].dma);
1236
1237 if (!rtlpci->rx_ring[rx_queue_idx].desc ||
1238 (unsigned long)rtlpci->rx_ring[rx_queue_idx].desc & 0xFF) {
1239 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
1240 ("Cannot allocate RX ring\n"));
1241 return -ENOMEM;
1242 }
1243
1244 memset(rtlpci->rx_ring[rx_queue_idx].desc, 0,
1245 sizeof(*rtlpci->rx_ring[rx_queue_idx].desc) *
1246 rtlpci->rxringcount);
1247
1248 rtlpci->rx_ring[rx_queue_idx].idx = 0;
1249
1250 for (i = 0; i < rtlpci->rxringcount; i++) {
1251 struct sk_buff *skb =
1252 dev_alloc_skb(rtlpci->rxbuffersize);
1253 u32 bufferaddress;
0c817338
LF		 1254 if (!skb)
1255 return 0;
bdc4bf65 1256 entry = &rtlpci->rx_ring[rx_queue_idx].desc[i];
0c817338
LF		 1257
1258 /*skb->dev = dev; */
1259
1260 rtlpci->rx_ring[rx_queue_idx].rx_buf[i] = skb;
1261
1262 /*
1263 *just set skb->cb to mapping addr
1264 *for pci_unmap_single use
1265 */
1266 *((dma_addr_t *) skb->cb) =
1267 pci_map_single(rtlpci->pdev, skb_tail_pointer(skb),
1268 rtlpci->rxbuffersize,
1269 PCI_DMA_FROMDEVICE);
1270
c7cfe38e 1271 bufferaddress = cpu_to_le32(*((dma_addr_t *)skb->cb));
0c817338
LF		 1272 rtlpriv->cfg->ops->set_desc((u8 *)entry, false,
1273 HW_DESC_RXBUFF_ADDR,
1274 (u8 *)&bufferaddress);
1275 rtlpriv->cfg->ops->set_desc((u8 *)entry, false,
1276 HW_DESC_RXPKT_LEN,
1277 (u8 *)&rtlpci->
1278 rxbuffersize);
1279 rtlpriv->cfg->ops->set_desc((u8 *) entry, false,
1280 HW_DESC_RXOWN,
1281 (u8 *)&tmp_one);
1282 }
1283
1284 rtlpriv->cfg->ops->set_desc((u8 *) entry, false,
1285 HW_DESC_RXERO, (u8 *)&tmp_one);
1286 }
1287 return 0;
1288}
1289
1290static void _rtl_pci_free_tx_ring(struct ieee80211_hw *hw,
1291 unsigned int prio)
1292{
1293 struct rtl_priv *rtlpriv = rtl_priv(hw);
1294 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
1295 struct rtl8192_tx_ring *ring = &rtlpci->tx_ring[prio];
1296
1297 while (skb_queue_len(&ring->queue)) {
1298 struct rtl_tx_desc *entry = &ring->desc[ring->idx];
1299 struct sk_buff *skb = __skb_dequeue(&ring->queue);
1300
1301 pci_unmap_single(rtlpci->pdev,
c7cfe38e 1302 le32_to_cpu(rtlpriv->cfg->
0c817338 1303 ops->get_desc((u8 *) entry, true,
c7cfe38e 1304 HW_DESC_TXBUFF_ADDR)),
0c817338
LF		 1305 skb->len, PCI_DMA_TODEVICE);
1306 kfree_skb(skb);
1307 ring->idx = (ring->idx + 1) % ring->entries;
1308 }
1309
1310 pci_free_consistent(rtlpci->pdev,
1311 sizeof(*ring->desc) * ring->entries,
1312 ring->desc, ring->dma);
1313 ring->desc = NULL;
1314}
1315
1316static void _rtl_pci_free_rx_ring(struct rtl_pci *rtlpci)
1317{
1318 int i, rx_queue_idx;
1319
1320 /*rx_queue_idx 0:RX_MPDU_QUEUE */
1321 /*rx_queue_idx 1:RX_CMD_QUEUE */
1322 for (rx_queue_idx = 0; rx_queue_idx < RTL_PCI_MAX_RX_QUEUE;
1323 rx_queue_idx++) {
1324 for (i = 0; i < rtlpci->rxringcount; i++) {
1325 struct sk_buff *skb =
1326 rtlpci->rx_ring[rx_queue_idx].rx_buf[i];
1327 if (!skb)
1328 continue;
1329
1330 pci_unmap_single(rtlpci->pdev,
1331 *((dma_addr_t *) skb->cb),
1332 rtlpci->rxbuffersize,
1333 PCI_DMA_FROMDEVICE);
1334 kfree_skb(skb);
1335 }
1336
1337 pci_free_consistent(rtlpci->pdev,
1338 sizeof(*rtlpci->rx_ring[rx_queue_idx].
1339 desc) * rtlpci->rxringcount,
1340 rtlpci->rx_ring[rx_queue_idx].desc,
1341 rtlpci->rx_ring[rx_queue_idx].dma);
1342 rtlpci->rx_ring[rx_queue_idx].desc = NULL;
1343 }
1344}
1345
1346static int _rtl_pci_init_trx_ring(struct ieee80211_hw *hw)
1347{
1348 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
1349 int ret;
1350 int i;
1351
1352 ret = _rtl_pci_init_rx_ring(hw);
1353 if (ret)
1354 return ret;
1355
1356 for (i = 0; i < RTL_PCI_MAX_TX_QUEUE_COUNT; i++) {
1357 ret = _rtl_pci_init_tx_ring(hw, i,
1358 rtlpci->txringcount[i]);
1359 if (ret)
1360 goto err_free_rings;
1361 }
1362
1363 return 0;
1364
1365err_free_rings:
1366 _rtl_pci_free_rx_ring(rtlpci);
1367
1368 for (i = 0; i < RTL_PCI_MAX_TX_QUEUE_COUNT; i++)
1369 if (rtlpci->tx_ring[i].desc)
1370 _rtl_pci_free_tx_ring(hw, i);
1371
1372 return 1;
1373}
1374
1375static int _rtl_pci_deinit_trx_ring(struct ieee80211_hw *hw)
1376{
1377 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
1378 u32 i;
1379
1380 /*free rx rings */
1381 _rtl_pci_free_rx_ring(rtlpci);
1382
1383 /*free tx rings */
1384 for (i = 0; i < RTL_PCI_MAX_TX_QUEUE_COUNT; i++)
1385 _rtl_pci_free_tx_ring(hw, i);
1386
1387 return 0;
1388}
1389
1390int rtl_pci_reset_trx_ring(struct ieee80211_hw *hw)
1391{
1392 struct rtl_priv *rtlpriv = rtl_priv(hw);
1393 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
1394 int i, rx_queue_idx;
1395 unsigned long flags;
1396 u8 tmp_one = 1;
1397
1398 /*rx_queue_idx 0:RX_MPDU_QUEUE */
1399 /*rx_queue_idx 1:RX_CMD_QUEUE */
1400 for (rx_queue_idx = 0; rx_queue_idx < RTL_PCI_MAX_RX_QUEUE;
1401 rx_queue_idx++) {
1402 /*
1403 *force the rx_ring[RX_MPDU_QUEUE/
1404 *RX_CMD_QUEUE].idx to the first one
1405 */
1406 if (rtlpci->rx_ring[rx_queue_idx].desc) {
1407 struct rtl_rx_desc *entry = NULL;
1408
1409 for (i = 0; i < rtlpci->rxringcount; i++) {
1410 entry = &rtlpci->rx_ring[rx_queue_idx].desc[i];
1411 rtlpriv->cfg->ops->set_desc((u8 *) entry,
1412 false,
1413 HW_DESC_RXOWN,
1414 (u8 *)&tmp_one);
1415 }
1416 rtlpci->rx_ring[rx_queue_idx].idx = 0;
1417 }
1418 }
1419
1420 /*
1421 *after reset, release previous pending packet,
1422 *and force the tx idx to the first one
1423 */
1424 spin_lock_irqsave(&rtlpriv->locks.irq_th_lock, flags);
1425 for (i = 0; i < RTL_PCI_MAX_TX_QUEUE_COUNT; i++) {
1426 if (rtlpci->tx_ring[i].desc) {
1427 struct rtl8192_tx_ring *ring = &rtlpci->tx_ring[i];
1428
1429 while (skb_queue_len(&ring->queue)) {
1430 struct rtl_tx_desc *entry =
1431 &ring->desc[ring->idx];
1432 struct sk_buff *skb =
1433 __skb_dequeue(&ring->queue);
1434
1435 pci_unmap_single(rtlpci->pdev,
c7cfe38e 1436 le32_to_cpu(rtlpriv->cfg->ops->
0c817338
LF		 1437 get_desc((u8 *)
1438 entry,
1439 true,
c7cfe38e 1440 HW_DESC_TXBUFF_ADDR)),
0c817338
LF		 1441 skb->len, PCI_DMA_TODEVICE);
1442 kfree_skb(skb);
1443 ring->idx = (ring->idx + 1) % ring->entries;
1444 }
1445 ring->idx = 0;
1446 }
1447 }
1448
1449 spin_unlock_irqrestore(&rtlpriv->locks.irq_th_lock, flags);
1450
1451 return 0;
1452}
1453
c7cfe38e
C		 1454static bool rtl_pci_tx_chk_waitq_insert(struct ieee80211_hw *hw,
1455 struct sk_buff *skb)
0c817338 1456{
c7cfe38e
C		 1457 struct rtl_priv *rtlpriv = rtl_priv(hw);
1458 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
1459 struct ieee80211_sta *sta = info->control.sta;
1460 struct rtl_sta_info *sta_entry = NULL;
1461 u8 tid = rtl_get_tid(skb);
1462
1463 if (!sta)
1464 return false;
1465 sta_entry = (struct rtl_sta_info *)sta->drv_priv;
1466
1467 if (!rtlpriv->rtlhal.earlymode_enable)
1468 return false;
1469 if (sta_entry->tids[tid].agg.agg_state != RTL_AGG_OPERATIONAL)
1470 return false;
1471 if (_rtl_mac_to_hwqueue(hw, skb) > VO_QUEUE)
1472 return false;
1473 if (tid > 7)
1474 return false;
1475
1476 /* maybe every tid should be checked */
1477 if (!rtlpriv->link_info.higher_busytxtraffic[tid])
1478 return false;
1479
1480 spin_lock_bh(&rtlpriv->locks.waitq_lock);
1481 skb_queue_tail(&rtlpriv->mac80211.skb_waitq[tid], skb);
1482 spin_unlock_bh(&rtlpriv->locks.waitq_lock);
0c817338 1483
c7cfe38e 1484 return true;
0c817338
LF		 1485}
1486
c7cfe38e
C		 1487int rtl_pci_tx(struct ieee80211_hw *hw, struct sk_buff *skb,
1488 struct rtl_tcb_desc *ptcb_desc)
0c817338
LF		 1489{
1490 struct rtl_priv *rtlpriv = rtl_priv(hw);
c7cfe38e 1491 struct rtl_sta_info *sta_entry = NULL;
0c817338 1492 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
c7cfe38e 1493 struct ieee80211_sta *sta = info->control.sta;
0c817338
LF		 1494 struct rtl8192_tx_ring *ring;
1495 struct rtl_tx_desc *pdesc;
1496 u8 idx;
c7cfe38e 1497 u8 hw_queue = _rtl_mac_to_hwqueue(hw, skb);
0c817338 1498 unsigned long flags;
c7cfe38e
C		 1499 struct ieee80211_hdr *hdr = rtl_get_hdr(skb);
1500 __le16 fc = rtl_get_fc(skb);
0c817338
LF		 1501 u8 *pda_addr = hdr->addr1;
1502 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
1503 /*ssn */
0c817338
LF		 1504 u8 tid = 0;
1505 u16 seq_number = 0;
1506 u8 own;
1507 u8 temp_one = 1;
1508
c7cfe38e
C		 1509 if (ieee80211_is_auth(fc)) {
1510 RT_TRACE(rtlpriv, COMP_SEND, DBG_DMESG, ("MAC80211_LINKING\n"));
1511 rtl_ips_nic_on(hw);
1512 }
1513
1514 if (rtlpriv->psc.sw_ps_enabled) {
1515 if (ieee80211_is_data(fc) && !ieee80211_is_nullfunc(fc) &&
1516 !ieee80211_has_pm(fc))
1517 hdr->frame_control |= cpu_to_le16(IEEE80211_FCTL_PM);
1518 }
0c817338 1519
c7cfe38e 1520 rtl_action_proc(hw, skb, true);
0c817338
LF		 1521
1522 if (is_multicast_ether_addr(pda_addr))
1523 rtlpriv->stats.txbytesmulticast += skb->len;
1524 else if (is_broadcast_ether_addr(pda_addr))
1525 rtlpriv->stats.txbytesbroadcast += skb->len;
1526 else
1527 rtlpriv->stats.txbytesunicast += skb->len;
1528
1529 spin_lock_irqsave(&rtlpriv->locks.irq_th_lock, flags);
0c817338
LF		 1530 ring = &rtlpci->tx_ring[hw_queue];
1531 if (hw_queue != BEACON_QUEUE)
1532 idx = (ring->idx + skb_queue_len(&ring->queue)) %
1533 ring->entries;
1534 else
1535 idx = 0;
1536
1537 pdesc = &ring->desc[idx];
1538 own = (u8) rtlpriv->cfg->ops->get_desc((u8 *) pdesc,
1539 true, HW_DESC_OWN);
1540
1541 if ((own == 1) && (hw_queue != BEACON_QUEUE)) {
1542 RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING,
1543 ("No more TX desc@%d, ring->idx = %d,"
1544 "idx = %d, skb_queue_len = 0x%d\n",
1545 hw_queue, ring->idx, idx,
1546 skb_queue_len(&ring->queue)));
1547
1548 spin_unlock_irqrestore(&rtlpriv->locks.irq_th_lock, flags);
1549 return skb->len;
1550 }
1551
0c817338 1552 if (ieee80211_is_data_qos(fc)) {
c7cfe38e
C		 1553 tid = rtl_get_tid(skb);
1554 if (sta) {
1555 sta_entry = (struct rtl_sta_info *)sta->drv_priv;
1556 seq_number = (le16_to_cpu(hdr->seq_ctrl) &
1557 IEEE80211_SCTL_SEQ) >> 4;
1558 seq_number += 1;
1559
1560 if (!ieee80211_has_morefrags(hdr->frame_control))
1561 sta_entry->tids[tid].seq_number = seq_number;
1562 }
0c817338
LF		 1563 }
1564
1565 if (ieee80211_is_data(fc))
1566 rtlpriv->cfg->ops->led_control(hw, LED_CTL_TX);
1567
c7cfe38e
C		 1568 rtlpriv->cfg->ops->fill_tx_desc(hw, hdr, (u8 *)pdesc,
1569 info, skb, hw_queue, ptcb_desc);
0c817338
LF		 1570
1571 __skb_queue_tail(&ring->queue, skb);
1572
c7cfe38e 1573 rtlpriv->cfg->ops->set_desc((u8 *)pdesc, true,
0c817338
LF		 1574 HW_DESC_OWN, (u8 *)&temp_one);
1575
0c817338
LF		 1576
1577 if ((ring->entries - skb_queue_len(&ring->queue)) < 2 &&
1578 hw_queue != BEACON_QUEUE) {
1579
1580 RT_TRACE(rtlpriv, COMP_ERR, DBG_LOUD,
1581 ("less desc left, stop skb_queue@%d, "
1582 "ring->idx = %d,"
1583 "idx = %d, skb_queue_len = 0x%d\n",
1584 hw_queue, ring->idx, idx,
1585 skb_queue_len(&ring->queue)));
1586
1587 ieee80211_stop_queue(hw, skb_get_queue_mapping(skb));
1588 }
1589
1590 spin_unlock_irqrestore(&rtlpriv->locks.irq_th_lock, flags);
1591
1592 rtlpriv->cfg->ops->tx_polling(hw, hw_queue);
1593
1594 return 0;
1595}
1596
c7cfe38e
C		 1597static void rtl_pci_flush(struct ieee80211_hw *hw, bool drop)
1598{
1599 struct rtl_priv *rtlpriv = rtl_priv(hw);
1600 struct rtl_pci_priv *pcipriv = rtl_pcipriv(hw);
1601 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
1602 u16 i = 0;
1603 int queue_id;
1604 struct rtl8192_tx_ring *ring;
1605
1606 for (queue_id = RTL_PCI_MAX_TX_QUEUE_COUNT - 1; queue_id >= 0;) {
1607 u32 queue_len;
1608 ring = &pcipriv->dev.tx_ring[queue_id];
1609 queue_len = skb_queue_len(&ring->queue);
1610 if (queue_len == 0 || queue_id == BEACON_QUEUE ||
1611 queue_id == TXCMD_QUEUE) {
1612 queue_id--;
1613 continue;
1614 } else {
1615 msleep(20);
1616 i++;
1617 }
1618
1619 /* we just wait 1s for all queues */
1620 if (rtlpriv->psc.rfpwr_state == ERFOFF ||
1621 is_hal_stop(rtlhal) || i >= 200)
1622 return;
1623 }
1624}
1625
1626void rtl_pci_deinit(struct ieee80211_hw *hw)
0c817338
LF		 1627{
1628 struct rtl_priv *rtlpriv = rtl_priv(hw);
1629 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
1630
1631 _rtl_pci_deinit_trx_ring(hw);
1632
1633 synchronize_irq(rtlpci->pdev->irq);
1634 tasklet_kill(&rtlpriv->works.irq_tasklet);
1635
1636 flush_workqueue(rtlpriv->works.rtl_wq);
1637 destroy_workqueue(rtlpriv->works.rtl_wq);
1638
1639}
1640
c7cfe38e 1641int rtl_pci_init(struct ieee80211_hw *hw, struct pci_dev *pdev)
0c817338
LF		 1642{
1643 struct rtl_priv *rtlpriv = rtl_priv(hw);
1644 int err;
1645
1646 _rtl_pci_init_struct(hw, pdev);
1647
1648 err = _rtl_pci_init_trx_ring(hw);
1649 if (err) {
1650 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
1651 ("tx ring initialization failed"));
1652 return err;
1653 }
1654
1655 return 1;
1656}
1657
c7cfe38e 1658int rtl_pci_start(struct ieee80211_hw *hw)
0c817338
LF		 1659{
1660 struct rtl_priv *rtlpriv = rtl_priv(hw);
1661 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
1662 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
1663 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
1664
1665 int err;
1666
1667 rtl_pci_reset_trx_ring(hw);
1668
1669 rtlpci->driver_is_goingto_unload = false;
1670 err = rtlpriv->cfg->ops->hw_init(hw);
1671 if (err) {
1672 RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG,
1673 ("Failed to config hardware!\n"));
1674 return err;
1675 }
1676
1677 rtlpriv->cfg->ops->enable_interrupt(hw);
1678 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, ("enable_interrupt OK\n"));
1679
1680 rtl_init_rx_config(hw);
1681
1682 /*should after adapter start and interrupt enable. */
1683 set_hal_start(rtlhal);
1684
1685 RT_CLEAR_PS_LEVEL(ppsc, RT_RF_OFF_LEVL_HALT_NIC);
1686
1687 rtlpci->up_first_time = false;
1688
1689 RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG, ("OK\n"));
1690 return 0;
1691}
1692
c7cfe38e 1693void rtl_pci_stop(struct ieee80211_hw *hw)
0c817338
LF		 1694{
1695 struct rtl_priv *rtlpriv = rtl_priv(hw);
1696 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
1697 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
1698 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
1699 unsigned long flags;
1700 u8 RFInProgressTimeOut = 0;
1701
1702 /*
1703 *should before disable interrrupt&adapter
1704 *and will do it immediately.
1705 */
1706 set_hal_stop(rtlhal);
1707
1708 rtlpriv->cfg->ops->disable_interrupt(hw);
1709
1710 spin_lock_irqsave(&rtlpriv->locks.rf_ps_lock, flags);
1711 while (ppsc->rfchange_inprogress) {
1712 spin_unlock_irqrestore(&rtlpriv->locks.rf_ps_lock, flags);
1713 if (RFInProgressTimeOut > 100) {
1714 spin_lock_irqsave(&rtlpriv->locks.rf_ps_lock, flags);
1715 break;
1716 }
1717 mdelay(1);
1718 RFInProgressTimeOut++;
1719 spin_lock_irqsave(&rtlpriv->locks.rf_ps_lock, flags);
1720 }
1721 ppsc->rfchange_inprogress = true;
1722 spin_unlock_irqrestore(&rtlpriv->locks.rf_ps_lock, flags);
1723
1724 rtlpci->driver_is_goingto_unload = true;
1725 rtlpriv->cfg->ops->hw_disable(hw);
1726 rtlpriv->cfg->ops->led_control(hw, LED_CTL_POWER_OFF);
1727
1728 spin_lock_irqsave(&rtlpriv->locks.rf_ps_lock, flags);
1729 ppsc->rfchange_inprogress = false;
1730 spin_unlock_irqrestore(&rtlpriv->locks.rf_ps_lock, flags);
1731
1732 rtl_pci_enable_aspm(hw);
1733}
1734
1735static bool _rtl_pci_find_adapter(struct pci_dev *pdev,
1736 struct ieee80211_hw *hw)
1737{
1738 struct rtl_priv *rtlpriv = rtl_priv(hw);
1739 struct rtl_pci_priv *pcipriv = rtl_pcipriv(hw);
1740 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
1741 struct pci_dev *bridge_pdev = pdev->bus->self;
1742 u16 venderid;
1743 u16 deviceid;
c7cfe38e 1744 u8 revisionid;
0c817338
LF		 1745 u16 irqline;
1746 u8 tmp;
1747
1748 venderid = pdev->vendor;
1749 deviceid = pdev->device;
c7cfe38e 1750 pci_read_config_byte(pdev, 0x8, &revisionid);
0c817338
LF		 1751 pci_read_config_word(pdev, 0x3C, &irqline);
1752
1753 if (deviceid == RTL_PCI_8192_DID ||
1754 deviceid == RTL_PCI_0044_DID ||
1755 deviceid == RTL_PCI_0047_DID ||
1756 deviceid == RTL_PCI_8192SE_DID ||
1757 deviceid == RTL_PCI_8174_DID ||
1758 deviceid == RTL_PCI_8173_DID ||
1759 deviceid == RTL_PCI_8172_DID ||
1760 deviceid == RTL_PCI_8171_DID) {
c7cfe38e 1761 switch (revisionid) {
0c817338
LF		 1762 case RTL_PCI_REVISION_ID_8192PCIE:
1763 RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG,
1764 ("8192 PCI-E is found - "
1765 "vid/did=%x/%x\n", venderid, deviceid));
1766 rtlhal->hw_type = HARDWARE_TYPE_RTL8192E;
1767 break;
1768 case RTL_PCI_REVISION_ID_8192SE:
1769 RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG,
1770 ("8192SE is found - "
1771 "vid/did=%x/%x\n", venderid, deviceid));
1772 rtlhal->hw_type = HARDWARE_TYPE_RTL8192SE;
1773 break;
1774 default:
1775 RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING,
1776 ("Err: Unknown device - "
1777 "vid/did=%x/%x\n", venderid, deviceid));
1778 rtlhal->hw_type = HARDWARE_TYPE_RTL8192SE;
1779 break;
1780
1781 }
1782 } else if (deviceid == RTL_PCI_8192CET_DID ||
1783 deviceid == RTL_PCI_8192CE_DID ||
1784 deviceid == RTL_PCI_8191CE_DID ||
1785 deviceid == RTL_PCI_8188CE_DID) {
1786 rtlhal->hw_type = HARDWARE_TYPE_RTL8192CE;
1787 RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG,
1788 ("8192C PCI-E is found - "
1789 "vid/did=%x/%x\n", venderid, deviceid));
c7cfe38e
C		 1790 } else if (deviceid == RTL_PCI_8192DE_DID ||
1791 deviceid == RTL_PCI_8192DE_DID2) {
1792 rtlhal->hw_type = HARDWARE_TYPE_RTL8192DE;
1793 RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG,
1794 ("8192D PCI-E is found - "
1795 "vid/did=%x/%x\n", venderid, deviceid));
0c817338
LF		 1796 } else {
1797 RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING,
1798 ("Err: Unknown device -"
1799 " vid/did=%x/%x\n", venderid, deviceid));
1800
1801 rtlhal->hw_type = RTL_DEFAULT_HARDWARE_TYPE;
1802 }
1803
c7cfe38e
C		 1804 if (rtlhal->hw_type == HARDWARE_TYPE_RTL8192DE) {
1805 if (revisionid == 0 || revisionid == 1) {
1806 if (revisionid == 0) {
1807 RT_TRACE(rtlpriv, COMP_INIT,
1808 DBG_LOUD, ("Find 92DE MAC0.\n"));
1809 rtlhal->interfaceindex = 0;
1810 } else if (revisionid == 1) {
1811 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
1812 ("Find 92DE MAC1.\n"));
1813 rtlhal->interfaceindex = 1;
1814 }
1815 } else {
1816 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
1817 ("Unknown device - "
1818 "VendorID/DeviceID=%x/%x, Revision=%x\n",
1819 venderid, deviceid, revisionid));
1820 rtlhal->interfaceindex = 0;
1821 }
1822 }
0c817338
LF		 1823 /*find bus info */
1824 pcipriv->ndis_adapter.busnumber = pdev->bus->number;
1825 pcipriv->ndis_adapter.devnumber = PCI_SLOT(pdev->devfn);
1826 pcipriv->ndis_adapter.funcnumber = PCI_FUNC(pdev->devfn);
1827
1828 /*find bridge info */
1829 pcipriv->ndis_adapter.pcibridge_vendorid = bridge_pdev->vendor;
1830 for (tmp = 0; tmp < PCI_BRIDGE_VENDOR_MAX; tmp++) {
1831 if (bridge_pdev->vendor == pcibridge_vendors[tmp]) {
1832 pcipriv->ndis_adapter.pcibridge_vendor = tmp;
1833 RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG,
1834 ("Pci Bridge Vendor is found index: %d\n",
1835 tmp));
1836 break;
1837 }
1838 }
1839
1840 if (pcipriv->ndis_adapter.pcibridge_vendor !=
1841 PCI_BRIDGE_VENDOR_UNKNOWN) {
1842 pcipriv->ndis_adapter.pcibridge_busnum =
1843 bridge_pdev->bus->number;
1844 pcipriv->ndis_adapter.pcibridge_devnum =
1845 PCI_SLOT(bridge_pdev->devfn);
1846 pcipriv->ndis_adapter.pcibridge_funcnum =
1847 PCI_FUNC(bridge_pdev->devfn);
0c817338
LF		 1848 pcipriv->ndis_adapter.pcicfg_addrport =
1849 (pcipriv->ndis_adapter.pcibridge_busnum << 16) |
1850 (pcipriv->ndis_adapter.pcibridge_devnum << 11) |
1851 (pcipriv->ndis_adapter.pcibridge_funcnum << 8) | (1 << 31);
c7cfe38e
C		 1852 pcipriv->ndis_adapter.pcibridge_pciehdr_offset =
1853 pci_pcie_cap(bridge_pdev);
0c817338
LF		 1854 pcipriv->ndis_adapter.num4bytes =
1855 (pcipriv->ndis_adapter.pcibridge_pciehdr_offset + 0x10) / 4;
1856
1857 rtl_pci_get_linkcontrol_field(hw);
1858
1859 if (pcipriv->ndis_adapter.pcibridge_vendor ==
1860 PCI_BRIDGE_VENDOR_AMD) {
1861 pcipriv->ndis_adapter.amd_l1_patch =
1862 rtl_pci_get_amd_l1_patch(hw);
1863 }
1864 }
1865
1866 RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG,
1867 ("pcidev busnumber:devnumber:funcnumber:"
1868 "vendor:link_ctl %d:%d:%d:%x:%x\n",
1869 pcipriv->ndis_adapter.busnumber,
1870 pcipriv->ndis_adapter.devnumber,
1871 pcipriv->ndis_adapter.funcnumber,
1872 pdev->vendor, pcipriv->ndis_adapter.linkctrl_reg));
1873
1874 RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG,
1875 ("pci_bridge busnumber:devnumber:funcnumber:vendor:"
1876 "pcie_cap:link_ctl_reg:amd %d:%d:%d:%x:%x:%x:%x\n",
1877 pcipriv->ndis_adapter.pcibridge_busnum,
1878 pcipriv->ndis_adapter.pcibridge_devnum,
1879 pcipriv->ndis_adapter.pcibridge_funcnum,
1880 pcibridge_vendors[pcipriv->ndis_adapter.pcibridge_vendor],
1881 pcipriv->ndis_adapter.pcibridge_pciehdr_offset,
1882 pcipriv->ndis_adapter.pcibridge_linkctrlreg,
1883 pcipriv->ndis_adapter.amd_l1_patch));
1884
1885 rtl_pci_parse_configuration(pdev, hw);
1886
1887 return true;
1888}
1889
1890int __devinit rtl_pci_probe(struct pci_dev *pdev,
1891 const struct pci_device_id *id)
1892{
1893 struct ieee80211_hw *hw = NULL;
1894
1895 struct rtl_priv *rtlpriv = NULL;
1896 struct rtl_pci_priv *pcipriv = NULL;
1897 struct rtl_pci *rtlpci;
1898 unsigned long pmem_start, pmem_len, pmem_flags;
1899 int err;
1900
1901 err = pci_enable_device(pdev);
1902 if (err) {
1903 RT_ASSERT(false,
1904 ("%s : Cannot enable new PCI device\n",
1905 pci_name(pdev)));
1906 return err;
1907 }
1908
1909 if (!pci_set_dma_mask(pdev, DMA_BIT_MASK(32))) {
1910 if (pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32))) {
1911 RT_ASSERT(false, ("Unable to obtain 32bit DMA "
1912 "for consistent allocations\n"));
1913 pci_disable_device(pdev);
1914 return -ENOMEM;
1915 }
1916 }
1917
1918 pci_set_master(pdev);
1919
1920 hw = ieee80211_alloc_hw(sizeof(struct rtl_pci_priv) +
1921 sizeof(struct rtl_priv), &rtl_ops);
1922 if (!hw) {
1923 RT_ASSERT(false,
1924 ("%s : ieee80211 alloc failed\n", pci_name(pdev)));
1925 err = -ENOMEM;
1926 goto fail1;
1927 }
1928
1929 SET_IEEE80211_DEV(hw, &pdev->dev);
1930 pci_set_drvdata(pdev, hw);
1931
1932 rtlpriv = hw->priv;
1933 pcipriv = (void *)rtlpriv->priv;
1934 pcipriv->dev.pdev = pdev;
1935
c7cfe38e
C		 1936 /* init cfg & intf_ops */
1937 rtlpriv->rtlhal.interface = INTF_PCI;
1938 rtlpriv->cfg = (struct rtl_hal_cfg *)(id->driver_data);
1939 rtlpriv->intf_ops = &rtl_pci_ops;
1940
0c817338
LF		 1941 /*
1942 *init dbgp flags before all
1943 *other functions, because we will
1944 *use it in other funtions like
1945 *RT_TRACE/RT_PRINT/RTL_PRINT_DATA
1946 *you can not use these macro
1947 *before this
1948 */
1949 rtl_dbgp_flag_init(hw);
1950
1951 /* MEM map */
1952 err = pci_request_regions(pdev, KBUILD_MODNAME);
1953 if (err) {
1954 RT_ASSERT(false, ("Can't obtain PCI resources\n"));
1955 return err;
1956 }
1957
c7cfe38e
C		 1958 pmem_start = pci_resource_start(pdev, rtlpriv->cfg->bar_id);
1959 pmem_len = pci_resource_len(pdev, rtlpriv->cfg->bar_id);
1960 pmem_flags = pci_resource_flags(pdev, rtlpriv->cfg->bar_id);
0c817338
LF		 1961
1962 /*shared mem start */
1963 rtlpriv->io.pci_mem_start =
c7cfe38e
C		 1964 (unsigned long)pci_iomap(pdev,
1965 rtlpriv->cfg->bar_id, pmem_len);
0c817338
LF		 1966 if (rtlpriv->io.pci_mem_start == 0) {
1967 RT_ASSERT(false, ("Can't map PCI mem\n"));
1968 goto fail2;
1969 }
1970
1971 RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG,
1972 ("mem mapped space: start: 0x%08lx len:%08lx "
1973 "flags:%08lx, after map:0x%08lx\n",
1974 pmem_start, pmem_len, pmem_flags,
1975 rtlpriv->io.pci_mem_start));
1976
1977 /* Disable Clk Request */
1978 pci_write_config_byte(pdev, 0x81, 0);
1979 /* leave D3 mode */
1980 pci_write_config_byte(pdev, 0x44, 0);
1981 pci_write_config_byte(pdev, 0x04, 0x06);
1982 pci_write_config_byte(pdev, 0x04, 0x07);
1983
0c817338
LF		 1984 /* find adapter */
1985 _rtl_pci_find_adapter(pdev, hw);
1986
1987 /* Init IO handler */
1988 _rtl_pci_io_handler_init(&pdev->dev, hw);
1989
1990 /*like read eeprom and so on */
1991 rtlpriv->cfg->ops->read_eeprom_info(hw);
1992
1993 if (rtlpriv->cfg->ops->init_sw_vars(hw)) {
1994 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
1995 ("Can't init_sw_vars.\n"));
1996 goto fail3;
1997 }
1998
1999 rtlpriv->cfg->ops->init_sw_leds(hw);
2000
2001 /*aspm */
2002 rtl_pci_init_aspm(hw);
2003
2004 /* Init mac80211 sw */
2005 err = rtl_init_core(hw);
2006 if (err) {
2007 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
2008 ("Can't allocate sw for mac80211.\n"));
2009 goto fail3;
2010 }
2011
2012 /* Init PCI sw */
2013 err = !rtl_pci_init(hw, pdev);
2014 if (err) {
2015 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
2016 ("Failed to init PCI.\n"));
2017 goto fail3;
2018 }
2019
2020 err = ieee80211_register_hw(hw);
2021 if (err) {
2022 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
2023 ("Can't register mac80211 hw.\n"));
2024 goto fail3;
2025 } else {
2026 rtlpriv->mac80211.mac80211_registered = 1;
2027 }
2028
2029 err = sysfs_create_group(&pdev->dev.kobj, &rtl_attribute_group);
2030 if (err) {
2031 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
2032 ("failed to create sysfs device attributes\n"));
2033 goto fail3;
2034 }
2035
2036 /*init rfkill */
2037 rtl_init_rfkill(hw);
2038
2039 rtlpci = rtl_pcidev(pcipriv);
2040 err = request_irq(rtlpci->pdev->irq, &_rtl_pci_interrupt,
2041 IRQF_SHARED, KBUILD_MODNAME, hw);
2042 if (err) {
2043 RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG,
2044 ("%s: failed to register IRQ handler\n",
2045 wiphy_name(hw->wiphy)));
2046 goto fail3;
2047 } else {
2048 rtlpci->irq_alloc = 1;
2049 }
2050
2051 set_bit(RTL_STATUS_INTERFACE_START, &rtlpriv->status);
2052 return 0;
2053
2054fail3:
2055 pci_set_drvdata(pdev, NULL);
2056 rtl_deinit_core(hw);
2057 _rtl_pci_io_handler_release(hw);
2058 ieee80211_free_hw(hw);
2059
2060 if (rtlpriv->io.pci_mem_start != 0)
62e63975 2061 pci_iounmap(pdev, (void __iomem *)rtlpriv->io.pci_mem_start);
0c817338
LF		 2062
2063fail2:
2064 pci_release_regions(pdev);
2065
2066fail1:
2067
2068 pci_disable_device(pdev);
2069
2070 return -ENODEV;
2071
2072}
2073EXPORT_SYMBOL(rtl_pci_probe);
2074
2075void rtl_pci_disconnect(struct pci_dev *pdev)
2076{
2077 struct ieee80211_hw *hw = pci_get_drvdata(pdev);
2078 struct rtl_pci_priv *pcipriv = rtl_pcipriv(hw);
2079 struct rtl_priv *rtlpriv = rtl_priv(hw);
2080 struct rtl_pci *rtlpci = rtl_pcidev(pcipriv);
2081 struct rtl_mac *rtlmac = rtl_mac(rtlpriv);
2082
2083 clear_bit(RTL_STATUS_INTERFACE_START, &rtlpriv->status);
2084
2085 sysfs_remove_group(&pdev->dev.kobj, &rtl_attribute_group);
2086
2087 /*ieee80211_unregister_hw will call ops_stop */
2088 if (rtlmac->mac80211_registered == 1) {
2089 ieee80211_unregister_hw(hw);
2090 rtlmac->mac80211_registered = 0;
2091 } else {
2092 rtl_deinit_deferred_work(hw);
2093 rtlpriv->intf_ops->adapter_stop(hw);
2094 }
2095
2096 /*deinit rfkill */
2097 rtl_deinit_rfkill(hw);
2098
2099 rtl_pci_deinit(hw);
2100 rtl_deinit_core(hw);
0c817338
LF		 2101 _rtl_pci_io_handler_release(hw);
2102 rtlpriv->cfg->ops->deinit_sw_vars(hw);
2103
2104 if (rtlpci->irq_alloc) {
2105 free_irq(rtlpci->pdev->irq, hw);
2106 rtlpci->irq_alloc = 0;
2107 }
2108
2109 if (rtlpriv->io.pci_mem_start != 0) {
62e63975 2110 pci_iounmap(pdev, (void __iomem *)rtlpriv->io.pci_mem_start);
0c817338
LF		 2111 pci_release_regions(pdev);
2112 }
2113
2114 pci_disable_device(pdev);
c7cfe38e
C		 2115
2116 rtl_pci_disable_aspm(hw);
2117
0c817338
LF		 2118 pci_set_drvdata(pdev, NULL);
2119
2120 ieee80211_free_hw(hw);
2121}
2122EXPORT_SYMBOL(rtl_pci_disconnect);
2123
2124/***************************************
2125kernel pci power state define:
2126PCI_D0 ((pci_power_t __force) 0)
2127PCI_D1 ((pci_power_t __force) 1)
2128PCI_D2 ((pci_power_t __force) 2)
2129PCI_D3hot ((pci_power_t __force) 3)
2130PCI_D3cold ((pci_power_t __force) 4)
2131PCI_UNKNOWN ((pci_power_t __force) 5)
2132
2133This function is called when system
2134goes into suspend state mac80211 will
2135call rtl_mac_stop() from the mac80211
2136suspend function first, So there is
2137no need to call hw_disable here.
2138****************************************/
2139int rtl_pci_suspend(struct pci_dev *pdev, pm_message_t state)
2140{
c7cfe38e
C		 2141 struct ieee80211_hw *hw = pci_get_drvdata(pdev);
2142 struct rtl_priv *rtlpriv = rtl_priv(hw);
2143
2144 rtlpriv->cfg->ops->hw_suspend(hw);
2145 rtl_deinit_rfkill(hw);
2146
0c817338
LF		 2147 pci_save_state(pdev);
2148 pci_disable_device(pdev);
2149 pci_set_power_state(pdev, PCI_D3hot);
0c817338
LF		 2150 return 0;
2151}
2152EXPORT_SYMBOL(rtl_pci_suspend);
2153
2154int rtl_pci_resume(struct pci_dev *pdev)
2155{
2156 int ret;
c7cfe38e
C		 2157 struct ieee80211_hw *hw = pci_get_drvdata(pdev);
2158 struct rtl_priv *rtlpriv = rtl_priv(hw);
0c817338
LF		 2159
2160 pci_set_power_state(pdev, PCI_D0);
2161 ret = pci_enable_device(pdev);
2162 if (ret) {
2163 RT_ASSERT(false, ("ERR: <======\n"));
2164 return ret;
2165 }
2166
2167 pci_restore_state(pdev);
2168
c7cfe38e
C		 2169 rtlpriv->cfg->ops->hw_resume(hw);
2170 rtl_init_rfkill(hw);
0c817338
LF		 2171 return 0;
2172}
2173EXPORT_SYMBOL(rtl_pci_resume);
2174
2175struct rtl_intf_ops rtl_pci_ops = {
c7cfe38e 2176 .read_efuse_byte = read_efuse_byte,
0c817338
LF		 2177 .adapter_start = rtl_pci_start,
2178 .adapter_stop = rtl_pci_stop,
2179 .adapter_tx = rtl_pci_tx,
c7cfe38e 2180 .flush = rtl_pci_flush,
0c817338 2181 .reset_trx_ring = rtl_pci_reset_trx_ring,
c7cfe38e 2182 .waitq_insert = rtl_pci_tx_chk_waitq_insert,
0c817338
LF		 2183
2184 .disable_aspm = rtl_pci_disable_aspm,
2185 .enable_aspm = rtl_pci_enable_aspm,
2186};
Linux kernel - Deliverables
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