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rtlwifi: Fix kernel panic resulting from RX buffer allocation failure
[deliverable/linux.git] / drivers / net / wireless / rtlwifi / pci.c
CommitLineData
0c817338
LF		 1/******************************************************************************
2 *
3 * Copyright(c) 2009-2010 Realtek Corporation.
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of version 2 of the GNU General Public License as
7 * published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details.
13 *
14 * You should have received a copy of the GNU General Public License along with
15 * this program; if not, write to the Free Software Foundation, Inc.,
16 * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
17 *
18 * The full GNU General Public License is included in this distribution in the
19 * file called LICENSE.
20 *
21 * Contact Information:
22 * wlanfae <wlanfae@realtek.com>
23 * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
24 * Hsinchu 300, Taiwan.
25 *
26 * Larry Finger <Larry.Finger@lwfinger.net>
27 *
28 *****************************************************************************/
29
30#include "core.h"
31#include "wifi.h"
32#include "pci.h"
33#include "base.h"
34#include "ps.h"
c7cfe38e 35#include "efuse.h"
0c817338
LF		 36
37static const u16 pcibridge_vendors[PCI_BRIDGE_VENDOR_MAX] = {
38 INTEL_VENDOR_ID,
39 ATI_VENDOR_ID,
40 AMD_VENDOR_ID,
41 SIS_VENDOR_ID
42};
43
c7cfe38e
C		 44static const u8 ac_to_hwq[] = {
45 VO_QUEUE,
46 VI_QUEUE,
47 BE_QUEUE,
48 BK_QUEUE
49};
50
d3bb1429 51static u8 _rtl_mac_to_hwqueue(struct ieee80211_hw *hw,
c7cfe38e
C		 52 struct sk_buff *skb)
53{
54 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
d3bb1429 55 __le16 fc = rtl_get_fc(skb);
c7cfe38e
C		 56 u8 queue_index = skb_get_queue_mapping(skb);
57
58 if (unlikely(ieee80211_is_beacon(fc)))
59 return BEACON_QUEUE;
60 if (ieee80211_is_mgmt(fc))
61 return MGNT_QUEUE;
62 if (rtlhal->hw_type == HARDWARE_TYPE_RTL8192SE)
63 if (ieee80211_is_nullfunc(fc))
64 return HIGH_QUEUE;
65
66 return ac_to_hwq[queue_index];
67}
68
0c817338
LF		 69/* Update PCI dependent default settings*/
70static void _rtl_pci_update_default_setting(struct ieee80211_hw *hw)
71{
72 struct rtl_priv *rtlpriv = rtl_priv(hw);
73 struct rtl_pci_priv *pcipriv = rtl_pcipriv(hw);
74 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
75 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
76 u8 pcibridge_vendor = pcipriv->ndis_adapter.pcibridge_vendor;
c7cfe38e 77 u8 init_aspm;
0c817338
LF		 78
79 ppsc->reg_rfps_level = 0;
7ea47240 80 ppsc->support_aspm = 0;
0c817338
LF		 81
82 /*Update PCI ASPM setting */
83 ppsc->const_amdpci_aspm = rtlpci->const_amdpci_aspm;
84 switch (rtlpci->const_pci_aspm) {
85 case 0:
86 /*No ASPM */
87 break;
88
89 case 1:
90 /*ASPM dynamically enabled/disable. */
91 ppsc->reg_rfps_level |= RT_RF_LPS_LEVEL_ASPM;
92 break;
93
94 case 2:
95 /*ASPM with Clock Req dynamically enabled/disable. */
96 ppsc->reg_rfps_level |= (RT_RF_LPS_LEVEL_ASPM |
97 RT_RF_OFF_LEVL_CLK_REQ);
98 break;
99
100 case 3:
101 /*
102 * Always enable ASPM and Clock Req
103 * from initialization to halt.
104 * */
105 ppsc->reg_rfps_level &= ~(RT_RF_LPS_LEVEL_ASPM);
106 ppsc->reg_rfps_level |= (RT_RF_PS_LEVEL_ALWAYS_ASPM |
107 RT_RF_OFF_LEVL_CLK_REQ);
108 break;
109
110 case 4:
111 /*
112 * Always enable ASPM without Clock Req
113 * from initialization to halt.
114 * */
115 ppsc->reg_rfps_level &= ~(RT_RF_LPS_LEVEL_ASPM |
116 RT_RF_OFF_LEVL_CLK_REQ);
117 ppsc->reg_rfps_level |= RT_RF_PS_LEVEL_ALWAYS_ASPM;
118 break;
119 }
120
121 ppsc->reg_rfps_level |= RT_RF_OFF_LEVL_HALT_NIC;
122
123 /*Update Radio OFF setting */
124 switch (rtlpci->const_hwsw_rfoff_d3) {
125 case 1:
126 if (ppsc->reg_rfps_level & RT_RF_LPS_LEVEL_ASPM)
127 ppsc->reg_rfps_level |= RT_RF_OFF_LEVL_ASPM;
128 break;
129
130 case 2:
131 if (ppsc->reg_rfps_level & RT_RF_LPS_LEVEL_ASPM)
132 ppsc->reg_rfps_level |= RT_RF_OFF_LEVL_ASPM;
133 ppsc->reg_rfps_level |= RT_RF_OFF_LEVL_HALT_NIC;
134 break;
135
136 case 3:
137 ppsc->reg_rfps_level |= RT_RF_OFF_LEVL_PCI_D3;
138 break;
139 }
140
141 /*Set HW definition to determine if it supports ASPM. */
142 switch (rtlpci->const_support_pciaspm) {
c7cfe38e
C		 143 case 0:{
144 /*Not support ASPM. */
145 bool support_aspm = false;
146 ppsc->support_aspm = support_aspm;
147 break;
148 }
149 case 1:{
150 /*Support ASPM. */
151 bool support_aspm = true;
152 bool support_backdoor = true;
153 ppsc->support_aspm = support_aspm;
154
155 /*if (priv->oem_id == RT_CID_TOSHIBA &&
156 !priv->ndis_adapter.amd_l1_patch)
157 support_backdoor = false; */
158
159 ppsc->support_backdoor = support_backdoor;
160
161 break;
162 }
0c817338
LF		 163 case 2:
164 /*ASPM value set by chipset. */
c7cfe38e
C		 165 if (pcibridge_vendor == PCI_BRIDGE_VENDOR_INTEL) {
166 bool support_aspm = true;
167 ppsc->support_aspm = support_aspm;
168 }
0c817338
LF		 169 break;
170 default:
171 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
172 ("switch case not process\n"));
173 break;
174 }
c7cfe38e
C		 175
176 /* toshiba aspm issue, toshiba will set aspm selfly
177 * so we should not set aspm in driver */
178 pci_read_config_byte(rtlpci->pdev, 0x80, &init_aspm);
179 if (rtlpriv->rtlhal.hw_type == HARDWARE_TYPE_RTL8192SE &&
180 init_aspm == 0x43)
181 ppsc->support_aspm = false;
182}
183
0c817338
LF		 184static bool _rtl_pci_platform_switch_device_pci_aspm(
185 struct ieee80211_hw *hw,
186 u8 value)
187{
188 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
c7cfe38e
C		 189 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
190
191 if (rtlhal->hw_type != HARDWARE_TYPE_RTL8192SE)
192 value |= 0x40;
0c817338 193
0c817338
LF		 194 pci_write_config_byte(rtlpci->pdev, 0x80, value);
195
32473284 196 return false;
0c817338
LF		 197}
198
199/*When we set 0x01 to enable clk request. Set 0x0 to disable clk req.*/
200static bool _rtl_pci_switch_clk_req(struct ieee80211_hw *hw, u8 value)
201{
202 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
c7cfe38e 203 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
0c817338 204
0c817338 205 pci_write_config_byte(rtlpci->pdev, 0x81, value);
0c817338 206
c7cfe38e
C		 207 if (rtlhal->hw_type == HARDWARE_TYPE_RTL8192SE)
208 udelay(100);
209
32473284 210 return true;
0c817338
LF		 211}
212
213/*Disable RTL8192SE ASPM & Disable Pci Bridge ASPM*/
214static void rtl_pci_disable_aspm(struct ieee80211_hw *hw)
215{
216 struct rtl_priv *rtlpriv = rtl_priv(hw);
217 struct rtl_pci_priv *pcipriv = rtl_pcipriv(hw);
218 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
219 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
220 u8 pcibridge_vendor = pcipriv->ndis_adapter.pcibridge_vendor;
221 u32 pcicfg_addrport = pcipriv->ndis_adapter.pcicfg_addrport;
222 u8 num4bytes = pcipriv->ndis_adapter.num4bytes;
223 /*Retrieve original configuration settings. */
224 u8 linkctrl_reg = pcipriv->ndis_adapter.linkctrl_reg;
225 u16 pcibridge_linkctrlreg = pcipriv->ndis_adapter.
226 pcibridge_linkctrlreg;
227 u16 aspmlevel = 0;
32473284 228 u8 tmp_u1b = 0;
0c817338 229
c7cfe38e
C		 230 if (!ppsc->support_aspm)
231 return;
232
0c817338
LF		 233 if (pcibridge_vendor == PCI_BRIDGE_VENDOR_UNKNOWN) {
234 RT_TRACE(rtlpriv, COMP_POWER, DBG_TRACE,
235 ("PCI(Bridge) UNKNOWN.\n"));
236
237 return;
238 }
239
240 if (ppsc->reg_rfps_level & RT_RF_OFF_LEVL_CLK_REQ) {
241 RT_CLEAR_PS_LEVEL(ppsc, RT_RF_OFF_LEVL_CLK_REQ);
242 _rtl_pci_switch_clk_req(hw, 0x0);
243 }
244
32473284
LF		 245 /*for promising device will in L0 state after an I/O. */
246 pci_read_config_byte(rtlpci->pdev, 0x80, &tmp_u1b);
0c817338
LF		 247
248 /*Set corresponding value. */
249 aspmlevel |= BIT(0) | BIT(1);
250 linkctrl_reg &= ~aspmlevel;
251 pcibridge_linkctrlreg &= ~(BIT(0) | BIT(1));
252
253 _rtl_pci_platform_switch_device_pci_aspm(hw, linkctrl_reg);
254 udelay(50);
255
256 /*4 Disable Pci Bridge ASPM */
257 rtl_pci_raw_write_port_ulong(PCI_CONF_ADDRESS,
258 pcicfg_addrport + (num4bytes << 2));
259 rtl_pci_raw_write_port_uchar(PCI_CONF_DATA, pcibridge_linkctrlreg);
260
261 udelay(50);
0c817338
LF		 262}
263
264/*
265 *Enable RTL8192SE ASPM & Enable Pci Bridge ASPM for
266 *power saving We should follow the sequence to enable
267 *RTL8192SE first then enable Pci Bridge ASPM
268 *or the system will show bluescreen.
269 */
270static void rtl_pci_enable_aspm(struct ieee80211_hw *hw)
271{
272 struct rtl_priv *rtlpriv = rtl_priv(hw);
273 struct rtl_pci_priv *pcipriv = rtl_pcipriv(hw);
274 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
275 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
276 u8 pcibridge_busnum = pcipriv->ndis_adapter.pcibridge_busnum;
277 u8 pcibridge_devnum = pcipriv->ndis_adapter.pcibridge_devnum;
278 u8 pcibridge_funcnum = pcipriv->ndis_adapter.pcibridge_funcnum;
279 u8 pcibridge_vendor = pcipriv->ndis_adapter.pcibridge_vendor;
280 u32 pcicfg_addrport = pcipriv->ndis_adapter.pcicfg_addrport;
281 u8 num4bytes = pcipriv->ndis_adapter.num4bytes;
282 u16 aspmlevel;
283 u8 u_pcibridge_aspmsetting;
284 u8 u_device_aspmsetting;
285
c7cfe38e
C		 286 if (!ppsc->support_aspm)
287 return;
288
0c817338
LF		 289 if (pcibridge_vendor == PCI_BRIDGE_VENDOR_UNKNOWN) {
290 RT_TRACE(rtlpriv, COMP_POWER, DBG_TRACE,
291 ("PCI(Bridge) UNKNOWN.\n"));
292 return;
293 }
294
295 /*4 Enable Pci Bridge ASPM */
296 rtl_pci_raw_write_port_ulong(PCI_CONF_ADDRESS,
297 pcicfg_addrport + (num4bytes << 2));
298
299 u_pcibridge_aspmsetting =
300 pcipriv->ndis_adapter.pcibridge_linkctrlreg |
301 rtlpci->const_hostpci_aspm_setting;
302
303 if (pcibridge_vendor == PCI_BRIDGE_VENDOR_INTEL)
304 u_pcibridge_aspmsetting &= ~BIT(0);
305
306 rtl_pci_raw_write_port_uchar(PCI_CONF_DATA, u_pcibridge_aspmsetting);
307
308 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
309 ("PlatformEnableASPM():PciBridge busnumber[%x], "
310 "DevNumbe[%x], funcnumber[%x], Write reg[%x] = %x\n",
311 pcibridge_busnum, pcibridge_devnum, pcibridge_funcnum,
312 (pcipriv->ndis_adapter.pcibridge_pciehdr_offset + 0x10),
313 u_pcibridge_aspmsetting));
314
315 udelay(50);
316
317 /*Get ASPM level (with/without Clock Req) */
318 aspmlevel = rtlpci->const_devicepci_aspm_setting;
319 u_device_aspmsetting = pcipriv->ndis_adapter.linkctrl_reg;
320
321 /*_rtl_pci_platform_switch_device_pci_aspm(dev,*/
322 /*(priv->ndis_adapter.linkctrl_reg | ASPMLevel)); */
323
324 u_device_aspmsetting |= aspmlevel;
325
326 _rtl_pci_platform_switch_device_pci_aspm(hw, u_device_aspmsetting);
327
328 if (ppsc->reg_rfps_level & RT_RF_OFF_LEVL_CLK_REQ) {
329 _rtl_pci_switch_clk_req(hw, (ppsc->reg_rfps_level &
330 RT_RF_OFF_LEVL_CLK_REQ) ? 1 : 0);
331 RT_SET_PS_LEVEL(ppsc, RT_RF_OFF_LEVL_CLK_REQ);
332 }
c7cfe38e 333 udelay(100);
0c817338
LF		 334}
335
336static bool rtl_pci_get_amd_l1_patch(struct ieee80211_hw *hw)
337{
338 struct rtl_pci_priv *pcipriv = rtl_pcipriv(hw);
339 u32 pcicfg_addrport = pcipriv->ndis_adapter.pcicfg_addrport;
340
341 bool status = false;
342 u8 offset_e0;
343 unsigned offset_e4;
344
345 rtl_pci_raw_write_port_ulong(PCI_CONF_ADDRESS,
346 pcicfg_addrport + 0xE0);
347 rtl_pci_raw_write_port_uchar(PCI_CONF_DATA, 0xA0);
348
349 rtl_pci_raw_write_port_ulong(PCI_CONF_ADDRESS,
350 pcicfg_addrport + 0xE0);
351 rtl_pci_raw_read_port_uchar(PCI_CONF_DATA, &offset_e0);
352
353 if (offset_e0 == 0xA0) {
354 rtl_pci_raw_write_port_ulong(PCI_CONF_ADDRESS,
355 pcicfg_addrport + 0xE4);
356 rtl_pci_raw_read_port_ulong(PCI_CONF_DATA, &offset_e4);
357 if (offset_e4 & BIT(23))
358 status = true;
359 }
360
361 return status;
362}
363
d3bb1429 364static void rtl_pci_get_linkcontrol_field(struct ieee80211_hw *hw)
0c817338
LF		 365{
366 struct rtl_pci_priv *pcipriv = rtl_pcipriv(hw);
367 u8 capabilityoffset = pcipriv->ndis_adapter.pcibridge_pciehdr_offset;
368 u32 pcicfg_addrport = pcipriv->ndis_adapter.pcicfg_addrport;
369 u8 linkctrl_reg;
c7cfe38e 370 u8 num4bbytes;
0c817338 371
c7cfe38e 372 num4bbytes = (capabilityoffset + 0x10) / 4;
0c817338
LF		 373
374 /*Read Link Control Register */
375 rtl_pci_raw_write_port_ulong(PCI_CONF_ADDRESS,
c7cfe38e 376 pcicfg_addrport + (num4bbytes << 2));
0c817338
LF		 377 rtl_pci_raw_read_port_uchar(PCI_CONF_DATA, &linkctrl_reg);
378
379 pcipriv->ndis_adapter.pcibridge_linkctrlreg = linkctrl_reg;
380}
381
382static void rtl_pci_parse_configuration(struct pci_dev *pdev,
383 struct ieee80211_hw *hw)
384{
385 struct rtl_priv *rtlpriv = rtl_priv(hw);
386 struct rtl_pci_priv *pcipriv = rtl_pcipriv(hw);
387
388 u8 tmp;
389 int pos;
390 u8 linkctrl_reg;
391
392 /*Link Control Register */
393 pos = pci_find_capability(pdev, PCI_CAP_ID_EXP);
394 pci_read_config_byte(pdev, pos + PCI_EXP_LNKCTL, &linkctrl_reg);
395 pcipriv->ndis_adapter.linkctrl_reg = linkctrl_reg;
396
397 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
398 ("Link Control Register =%x\n",
399 pcipriv->ndis_adapter.linkctrl_reg));
400
401 pci_read_config_byte(pdev, 0x98, &tmp);
402 tmp |= BIT(4);
403 pci_write_config_byte(pdev, 0x98, tmp);
404
405 tmp = 0x17;
406 pci_write_config_byte(pdev, 0x70f, tmp);
407}
408
c7cfe38e 409static void rtl_pci_init_aspm(struct ieee80211_hw *hw)
0c817338
LF		 410{
411 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
412
413 _rtl_pci_update_default_setting(hw);
414
415 if (ppsc->reg_rfps_level & RT_RF_PS_LEVEL_ALWAYS_ASPM) {
416 /*Always enable ASPM & Clock Req. */
417 rtl_pci_enable_aspm(hw);
418 RT_SET_PS_LEVEL(ppsc, RT_RF_PS_LEVEL_ALWAYS_ASPM);
419 }
420
421}
422
0c817338
LF		 423static void _rtl_pci_io_handler_init(struct device *dev,
424 struct ieee80211_hw *hw)
425{
426 struct rtl_priv *rtlpriv = rtl_priv(hw);
427
428 rtlpriv->io.dev = dev;
429
430 rtlpriv->io.write8_async = pci_write8_async;
431 rtlpriv->io.write16_async = pci_write16_async;
432 rtlpriv->io.write32_async = pci_write32_async;
433
434 rtlpriv->io.read8_sync = pci_read8_sync;
435 rtlpriv->io.read16_sync = pci_read16_sync;
436 rtlpriv->io.read32_sync = pci_read32_sync;
437
438}
439
440static void _rtl_pci_io_handler_release(struct ieee80211_hw *hw)
441{
442}
443
c7cfe38e
C		 444static bool _rtl_update_earlymode_info(struct ieee80211_hw *hw,
445 struct sk_buff *skb, struct rtl_tcb_desc *tcb_desc, u8 tid)
446{
447 struct rtl_priv *rtlpriv = rtl_priv(hw);
448 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
449 u8 additionlen = FCS_LEN;
450 struct sk_buff *next_skb;
451
452 /* here open is 4, wep/tkip is 8, aes is 12*/
453 if (info->control.hw_key)
454 additionlen += info->control.hw_key->icv_len;
455
456 /* The most skb num is 6 */
457 tcb_desc->empkt_num = 0;
458 spin_lock_bh(&rtlpriv->locks.waitq_lock);
459 skb_queue_walk(&rtlpriv->mac80211.skb_waitq[tid], next_skb) {
460 struct ieee80211_tx_info *next_info;
461
462 next_info = IEEE80211_SKB_CB(next_skb);
463 if (next_info->flags & IEEE80211_TX_CTL_AMPDU) {
464 tcb_desc->empkt_len[tcb_desc->empkt_num] =
465 next_skb->len + additionlen;
466 tcb_desc->empkt_num++;
467 } else {
468 break;
469 }
470
471 if (skb_queue_is_last(&rtlpriv->mac80211.skb_waitq[tid],
472 next_skb))
473 break;
474
475 if (tcb_desc->empkt_num >= 5)
476 break;
477 }
478 spin_unlock_bh(&rtlpriv->locks.waitq_lock);
479
480 return true;
481}
482
483/* just for early mode now */
484static void _rtl_pci_tx_chk_waitq(struct ieee80211_hw *hw)
485{
486 struct rtl_priv *rtlpriv = rtl_priv(hw);
487 struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
488 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
489 struct sk_buff *skb = NULL;
490 struct ieee80211_tx_info *info = NULL;
491 int tid; /* should be int */
492
493 if (!rtlpriv->rtlhal.earlymode_enable)
494 return;
495
496 /* we juse use em for BE/BK/VI/VO */
497 for (tid = 7; tid >= 0; tid--) {
498 u8 hw_queue = ac_to_hwq[rtl_tid_to_ac(hw, tid)];
499 struct rtl8192_tx_ring *ring = &rtlpci->tx_ring[hw_queue];
500 while (!mac->act_scanning &&
501 rtlpriv->psc.rfpwr_state == ERFON) {
502 struct rtl_tcb_desc tcb_desc;
503 memset(&tcb_desc, 0, sizeof(struct rtl_tcb_desc));
504
505 spin_lock_bh(&rtlpriv->locks.waitq_lock);
506 if (!skb_queue_empty(&mac->skb_waitq[tid]) &&
507 (ring->entries - skb_queue_len(&ring->queue) > 5)) {
508 skb = skb_dequeue(&mac->skb_waitq[tid]);
509 } else {
510 spin_unlock_bh(&rtlpriv->locks.waitq_lock);
511 break;
512 }
513 spin_unlock_bh(&rtlpriv->locks.waitq_lock);
514
515 /* Some macaddr can't do early mode. like
516 * multicast/broadcast/no_qos data */
517 info = IEEE80211_SKB_CB(skb);
518 if (info->flags & IEEE80211_TX_CTL_AMPDU)
519 _rtl_update_earlymode_info(hw, skb,
520 &tcb_desc, tid);
521
c7cfe38e 522 rtlpriv->intf_ops->adapter_tx(hw, skb, &tcb_desc);
c7cfe38e
C		 523 }
524 }
525}
526
527
0c817338
LF		 528static void _rtl_pci_tx_isr(struct ieee80211_hw *hw, int prio)
529{
530 struct rtl_priv *rtlpriv = rtl_priv(hw);
531 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
532
533 struct rtl8192_tx_ring *ring = &rtlpci->tx_ring[prio];
534
535 while (skb_queue_len(&ring->queue)) {
536 struct rtl_tx_desc *entry = &ring->desc[ring->idx];
537 struct sk_buff *skb;
538 struct ieee80211_tx_info *info;
c7cfe38e
C		 539 __le16 fc;
540 u8 tid;
0c817338
LF		 541
542 u8 own = (u8) rtlpriv->cfg->ops->get_desc((u8 *) entry, true,
543 HW_DESC_OWN);
544
545 /*
546 *beacon packet will only use the first
547 *descriptor defautly,and the own may not
548 *be cleared by the hardware
549 */
550 if (own)
551 return;
552 ring->idx = (ring->idx + 1) % ring->entries;
553
554 skb = __skb_dequeue(&ring->queue);
555 pci_unmap_single(rtlpci->pdev,
d3bb1429 556 rtlpriv->cfg->ops->
0c817338 557 get_desc((u8 *) entry, true,
d3bb1429 558 HW_DESC_TXBUFF_ADDR),
0c817338
LF		 559 skb->len, PCI_DMA_TODEVICE);
560
c7cfe38e
C		 561 /* remove early mode header */
562 if (rtlpriv->rtlhal.earlymode_enable)
563 skb_pull(skb, EM_HDR_LEN);
564
0c817338
LF		 565 RT_TRACE(rtlpriv, (COMP_INTR | COMP_SEND), DBG_TRACE,
566 ("new ring->idx:%d, "
567 "free: skb_queue_len:%d, free: seq:%x\n",
568 ring->idx,
569 skb_queue_len(&ring->queue),
570 *(u16 *) (skb->data + 22)));
571
c7cfe38e
C		 572 if (prio == TXCMD_QUEUE) {
573 dev_kfree_skb(skb);
574 goto tx_status_ok;
575
576 }
577
578 /* for sw LPS, just after NULL skb send out, we can
579 * sure AP kown we are sleeped, our we should not let
580 * rf to sleep*/
581 fc = rtl_get_fc(skb);
582 if (ieee80211_is_nullfunc(fc)) {
583 if (ieee80211_has_pm(fc)) {
584 rtlpriv->mac80211.offchan_deley = true;
585 rtlpriv->psc.state_inap = 1;
586 } else {
587 rtlpriv->psc.state_inap = 0;
588 }
589 }
590
591 /* update tid tx pkt num */
592 tid = rtl_get_tid(skb);
593 if (tid <= 7)
594 rtlpriv->link_info.tidtx_inperiod[tid]++;
595
0c817338
LF		 596 info = IEEE80211_SKB_CB(skb);
597 ieee80211_tx_info_clear_status(info);
598
599 info->flags |= IEEE80211_TX_STAT_ACK;
600 /*info->status.rates[0].count = 1; */
601
602 ieee80211_tx_status_irqsafe(hw, skb);
603
604 if ((ring->entries - skb_queue_len(&ring->queue))
605 == 2) {
606
607 RT_TRACE(rtlpriv, COMP_ERR, DBG_LOUD,
608 ("more desc left, wake"
609 "skb_queue@%d,ring->idx = %d,"
610 "skb_queue_len = 0x%d\n",
611 prio, ring->idx,
612 skb_queue_len(&ring->queue)));
613
614 ieee80211_wake_queue(hw,
615 skb_get_queue_mapping
616 (skb));
617 }
c7cfe38e 618tx_status_ok:
0c817338
LF		 619 skb = NULL;
620 }
621
622 if (((rtlpriv->link_info.num_rx_inperiod +
623 rtlpriv->link_info.num_tx_inperiod) > 8) ||
624 (rtlpriv->link_info.num_rx_inperiod > 2)) {
625 rtl_lps_leave(hw);
626 }
627}
628
629static void _rtl_pci_rx_interrupt(struct ieee80211_hw *hw)
630{
631 struct rtl_priv *rtlpriv = rtl_priv(hw);
632 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
633 int rx_queue_idx = RTL_PCI_RX_MPDU_QUEUE;
634
635 struct ieee80211_rx_status rx_status = { 0 };
636 unsigned int count = rtlpci->rxringcount;
637 u8 own;
638 u8 tmp_one;
639 u32 bufferaddress;
640 bool unicast = false;
641
642 struct rtl_stats stats = {
643 .signal = 0,
644 .noise = -98,
645 .rate = 0,
646 };
647
648 /*RX NORMAL PKT */
649 while (count--) {
650 /*rx descriptor */
651 struct rtl_rx_desc *pdesc = &rtlpci->rx_ring[rx_queue_idx].desc[
652 rtlpci->rx_ring[rx_queue_idx].idx];
653 /*rx pkt */
654 struct sk_buff *skb = rtlpci->rx_ring[rx_queue_idx].rx_buf[
655 rtlpci->rx_ring[rx_queue_idx].idx];
656
657 own = (u8) rtlpriv->cfg->ops->get_desc((u8 *) pdesc,
658 false, HW_DESC_OWN);
659
660 if (own) {
661 /*wait data to be filled by hardware */
662 return;
663 } else {
664 struct ieee80211_hdr *hdr;
17c9ac62 665 __le16 fc;
0c817338
LF		 666 struct sk_buff *new_skb = NULL;
667
668 rtlpriv->cfg->ops->query_rx_desc(hw, &stats,
669 &rx_status,
670 (u8 *) pdesc, skb);
671
0c817338
LF		 672 skb_put(skb, rtlpriv->cfg->ops->get_desc((u8 *) pdesc,
673 false,
674 HW_DESC_RXPKT_LEN));
675 skb_reserve(skb,
676 stats.rx_drvinfo_size + stats.rx_bufshift);
677
678 /*
679 *NOTICE This can not be use for mac80211,
680 *this is done in mac80211 code,
681 *if you done here sec DHCP will fail
682 *skb_trim(skb, skb->len - 4);
683 */
684
c7cfe38e
C		 685 hdr = rtl_get_hdr(skb);
686 fc = rtl_get_fc(skb);
0c817338 687
a9e12869
LF		 688 /* try for new buffer - if allocation fails, drop
689 * frame and reuse old buffer
690 */
691 new_skb = dev_alloc_skb(rtlpci->rxbuffersize);
692 if (unlikely(!new_skb)) {
693 RT_TRACE(rtlpriv, (COMP_INTR | COMP_RECV),
694 DBG_DMESG,
695 ("can't alloc skb for rx\n"));
696 goto done;
697 }
698 pci_unmap_single(rtlpci->pdev,
699 *((dma_addr_t *) skb->cb),
700 rtlpci->rxbuffersize,
701 PCI_DMA_FROMDEVICE);
702
c7cfe38e 703 if (!stats.crc || !stats.hwerror) {
0c817338
LF		 704 memcpy(IEEE80211_SKB_RXCB(skb), &rx_status,
705 sizeof(rx_status));
706
c7cfe38e 707 if (is_broadcast_ether_addr(hdr->addr1)) {
0c817338 708 ;/*TODO*/
c7cfe38e
C		 709 } else if (is_multicast_ether_addr(hdr->addr1)) {
710 ;/*TODO*/
711 } else {
712 unicast = true;
713 rtlpriv->stats.rxbytesunicast +=
714 skb->len;
0c817338
LF		 715 }
716
717 rtl_is_special_data(hw, skb, false);
718
719 if (ieee80211_is_data(fc)) {
720 rtlpriv->cfg->ops->led_control(hw,
721 LED_CTL_RX);
722
723 if (unicast)
724 rtlpriv->link_info.
725 num_rx_inperiod++;
726 }
727
c7cfe38e
C		 728 /* for sw lps */
729 rtl_swlps_beacon(hw, (void *)skb->data,
730 skb->len);
731 rtl_recognize_peer(hw, (void *)skb->data,
732 skb->len);
733 if ((rtlpriv->mac80211.opmode ==
734 NL80211_IFTYPE_AP) &&
735 (rtlpriv->rtlhal.current_bandtype ==
736 BAND_ON_2_4G) &&
737 (ieee80211_is_beacon(fc) ||
738 ieee80211_is_probe_resp(fc))) {
0c817338 739 dev_kfree_skb_any(skb);
5c4bc1ce 740 } else {
c7cfe38e
C		 741 if (unlikely(!rtl_action_proc(hw, skb,
742 false))) {
743 dev_kfree_skb_any(skb);
744 } else {
745 struct sk_buff *uskb = NULL;
746 u8 *pdata;
747 uskb = dev_alloc_skb(skb->len
748 + 128);
749 memcpy(IEEE80211_SKB_RXCB(uskb),
750 &rx_status,
751 sizeof(rx_status));
752 pdata = (u8 *)skb_put(uskb,
753 skb->len);
754 memcpy(pdata, skb->data,
755 skb->len);
756 dev_kfree_skb_any(skb);
757
758 ieee80211_rx_irqsafe(hw, uskb);
bdc4bf65 759 }
5c4bc1ce 760 }
0c817338
LF		 761 } else {
762 dev_kfree_skb_any(skb);
763 }
764
765 if (((rtlpriv->link_info.num_rx_inperiod +
766 rtlpriv->link_info.num_tx_inperiod) > 8) ||
767 (rtlpriv->link_info.num_rx_inperiod > 2)) {
768 rtl_lps_leave(hw);
769 }
770
0c817338 771 skb = new_skb;
0c817338
LF		 772
773 rtlpci->rx_ring[rx_queue_idx].rx_buf[rtlpci->
774 rx_ring
775 [rx_queue_idx].
776 idx] = skb;
777 *((dma_addr_t *) skb->cb) =
778 pci_map_single(rtlpci->pdev, skb_tail_pointer(skb),
779 rtlpci->rxbuffersize,
780 PCI_DMA_FROMDEVICE);
781
782 }
783done:
d3bb1429 784 bufferaddress = (*((dma_addr_t *)skb->cb));
0c817338
LF		 785 tmp_one = 1;
786 rtlpriv->cfg->ops->set_desc((u8 *) pdesc, false,
787 HW_DESC_RXBUFF_ADDR,
788 (u8 *)&bufferaddress);
789 rtlpriv->cfg->ops->set_desc((u8 *)pdesc, false, HW_DESC_RXOWN,
790 (u8 *)&tmp_one);
791 rtlpriv->cfg->ops->set_desc((u8 *)pdesc, false,
792 HW_DESC_RXPKT_LEN,
793 (u8 *)&rtlpci->rxbuffersize);
794
795 if (rtlpci->rx_ring[rx_queue_idx].idx ==
796 rtlpci->rxringcount - 1)
797 rtlpriv->cfg->ops->set_desc((u8 *)pdesc, false,
798 HW_DESC_RXERO,
799 (u8 *)&tmp_one);
800
801 rtlpci->rx_ring[rx_queue_idx].idx =
802 (rtlpci->rx_ring[rx_queue_idx].idx + 1) %
803 rtlpci->rxringcount;
804 }
805
806}
807
0c817338
LF		 808static irqreturn_t _rtl_pci_interrupt(int irq, void *dev_id)
809{
810 struct ieee80211_hw *hw = dev_id;
811 struct rtl_priv *rtlpriv = rtl_priv(hw);
812 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
c7cfe38e 813 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
0c817338
LF		 814 unsigned long flags;
815 u32 inta = 0;
816 u32 intb = 0;
817
818 if (rtlpci->irq_enabled == 0)
819 return IRQ_HANDLED;
820
821 spin_lock_irqsave(&rtlpriv->locks.irq_th_lock, flags);
822
823 /*read ISR: 4/8bytes */
824 rtlpriv->cfg->ops->interrupt_recognized(hw, &inta, &intb);
825
826 /*Shared IRQ or HW disappared */
827 if (!inta || inta == 0xffff)
828 goto done;
829
830 /*<1> beacon related */
831 if (inta & rtlpriv->cfg->maps[RTL_IMR_TBDOK]) {
832 RT_TRACE(rtlpriv, COMP_INTR, DBG_TRACE,
833 ("beacon ok interrupt!\n"));
834 }
835
836 if (unlikely(inta & rtlpriv->cfg->maps[RTL_IMR_TBDER])) {
837 RT_TRACE(rtlpriv, COMP_INTR, DBG_TRACE,
838 ("beacon err interrupt!\n"));
839 }
840
841 if (inta & rtlpriv->cfg->maps[RTL_IMR_BDOK]) {
842 RT_TRACE(rtlpriv, COMP_INTR, DBG_TRACE,
843 ("beacon interrupt!\n"));
844 }
845
846 if (inta & rtlpriv->cfg->maps[RTL_IMR_BcnInt]) {
847 RT_TRACE(rtlpriv, COMP_INTR, DBG_TRACE,
848 ("prepare beacon for interrupt!\n"));
849 tasklet_schedule(&rtlpriv->works.irq_prepare_bcn_tasklet);
850 }
851
852 /*<3> Tx related */
853 if (unlikely(inta & rtlpriv->cfg->maps[RTL_IMR_TXFOVW]))
854 RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING, ("IMR_TXFOVW!\n"));
855
856 if (inta & rtlpriv->cfg->maps[RTL_IMR_MGNTDOK]) {
857 RT_TRACE(rtlpriv, COMP_INTR, DBG_TRACE,
858 ("Manage ok interrupt!\n"));
859 _rtl_pci_tx_isr(hw, MGNT_QUEUE);
860 }
861
862 if (inta & rtlpriv->cfg->maps[RTL_IMR_HIGHDOK]) {
863 RT_TRACE(rtlpriv, COMP_INTR, DBG_TRACE,
864 ("HIGH_QUEUE ok interrupt!\n"));
865 _rtl_pci_tx_isr(hw, HIGH_QUEUE);
866 }
867
868 if (inta & rtlpriv->cfg->maps[RTL_IMR_BKDOK]) {
869 rtlpriv->link_info.num_tx_inperiod++;
870
871 RT_TRACE(rtlpriv, COMP_INTR, DBG_TRACE,
872 ("BK Tx OK interrupt!\n"));
873 _rtl_pci_tx_isr(hw, BK_QUEUE);
874 }
875
876 if (inta & rtlpriv->cfg->maps[RTL_IMR_BEDOK]) {
877 rtlpriv->link_info.num_tx_inperiod++;
878
879 RT_TRACE(rtlpriv, COMP_INTR, DBG_TRACE,
880 ("BE TX OK interrupt!\n"));
881 _rtl_pci_tx_isr(hw, BE_QUEUE);
882 }
883
884 if (inta & rtlpriv->cfg->maps[RTL_IMR_VIDOK]) {
885 rtlpriv->link_info.num_tx_inperiod++;
886
887 RT_TRACE(rtlpriv, COMP_INTR, DBG_TRACE,
888 ("VI TX OK interrupt!\n"));
889 _rtl_pci_tx_isr(hw, VI_QUEUE);
890 }
891
892 if (inta & rtlpriv->cfg->maps[RTL_IMR_VODOK]) {
893 rtlpriv->link_info.num_tx_inperiod++;
894
895 RT_TRACE(rtlpriv, COMP_INTR, DBG_TRACE,
896 ("Vo TX OK interrupt!\n"));
897 _rtl_pci_tx_isr(hw, VO_QUEUE);
898 }
899
c7cfe38e
C		 900 if (rtlhal->hw_type == HARDWARE_TYPE_RTL8192SE) {
901 if (inta & rtlpriv->cfg->maps[RTL_IMR_COMDOK]) {
902 rtlpriv->link_info.num_tx_inperiod++;
903
904 RT_TRACE(rtlpriv, COMP_INTR, DBG_TRACE,
905 ("CMD TX OK interrupt!\n"));
906 _rtl_pci_tx_isr(hw, TXCMD_QUEUE);
907 }
908 }
909
0c817338
LF		 910 /*<2> Rx related */
911 if (inta & rtlpriv->cfg->maps[RTL_IMR_ROK]) {
912 RT_TRACE(rtlpriv, COMP_INTR, DBG_TRACE, ("Rx ok interrupt!\n"));
c7cfe38e 913 _rtl_pci_rx_interrupt(hw);
0c817338
LF		 914 }
915
916 if (unlikely(inta & rtlpriv->cfg->maps[RTL_IMR_RDU])) {
917 RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING,
918 ("rx descriptor unavailable!\n"));
c7cfe38e 919 _rtl_pci_rx_interrupt(hw);
0c817338
LF		 920 }
921
922 if (unlikely(inta & rtlpriv->cfg->maps[RTL_IMR_RXFOVW])) {
923 RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING, ("rx overflow !\n"));
c7cfe38e 924 _rtl_pci_rx_interrupt(hw);
0c817338
LF		 925 }
926
c7cfe38e
C		 927 if (rtlpriv->rtlhal.earlymode_enable)
928 tasklet_schedule(&rtlpriv->works.irq_tasklet);
929
0c817338
LF		 930 spin_unlock_irqrestore(&rtlpriv->locks.irq_th_lock, flags);
931 return IRQ_HANDLED;
932
933done:
934 spin_unlock_irqrestore(&rtlpriv->locks.irq_th_lock, flags);
935 return IRQ_HANDLED;
936}
937
938static void _rtl_pci_irq_tasklet(struct ieee80211_hw *hw)
939{
c7cfe38e 940 _rtl_pci_tx_chk_waitq(hw);
0c817338
LF		 941}
942
943static void _rtl_pci_prepare_bcn_tasklet(struct ieee80211_hw *hw)
944{
945 struct rtl_priv *rtlpriv = rtl_priv(hw);
946 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
947 struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
c7cfe38e 948 struct rtl8192_tx_ring *ring = NULL;
0c817338
LF		 949 struct ieee80211_hdr *hdr = NULL;
950 struct ieee80211_tx_info *info = NULL;
951 struct sk_buff *pskb = NULL;
952 struct rtl_tx_desc *pdesc = NULL;
c7cfe38e 953 struct rtl_tcb_desc tcb_desc;
0c817338
LF		 954 u8 temp_one = 1;
955
c7cfe38e 956 memset(&tcb_desc, 0, sizeof(struct rtl_tcb_desc));
0c817338
LF		 957 ring = &rtlpci->tx_ring[BEACON_QUEUE];
958 pskb = __skb_dequeue(&ring->queue);
959 if (pskb)
960 kfree_skb(pskb);
961
962 /*NB: the beacon data buffer must be 32-bit aligned. */
963 pskb = ieee80211_beacon_get(hw, mac->vif);
964 if (pskb == NULL)
965 return;
c7cfe38e 966 hdr = rtl_get_hdr(pskb);
0c817338 967 info = IEEE80211_SKB_CB(pskb);
0c817338
LF		 968 pdesc = &ring->desc[0];
969 rtlpriv->cfg->ops->fill_tx_desc(hw, hdr, (u8 *) pdesc,
c7cfe38e 970 info, pskb, BEACON_QUEUE, &tcb_desc);
0c817338
LF		 971
972 __skb_queue_tail(&ring->queue, pskb);
973
974 rtlpriv->cfg->ops->set_desc((u8 *) pdesc, true, HW_DESC_OWN,
975 (u8 *)&temp_one);
976
977 return;
978}
979
980static void _rtl_pci_init_trx_var(struct ieee80211_hw *hw)
981{
982 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
983 u8 i;
984
985 for (i = 0; i < RTL_PCI_MAX_TX_QUEUE_COUNT; i++)
986 rtlpci->txringcount[i] = RT_TXDESC_NUM;
987
988 /*
989 *we just alloc 2 desc for beacon queue,
990 *because we just need first desc in hw beacon.
991 */
992 rtlpci->txringcount[BEACON_QUEUE] = 2;
993
994 /*
995 *BE queue need more descriptor for performance
996 *consideration or, No more tx desc will happen,
997 *and may cause mac80211 mem leakage.
998 */
999 rtlpci->txringcount[BE_QUEUE] = RT_TXDESC_NUM_BE_QUEUE;
1000
1001 rtlpci->rxbuffersize = 9100; /*2048/1024; */
1002 rtlpci->rxringcount = RTL_PCI_MAX_RX_COUNT; /*64; */
1003}
1004
1005static void _rtl_pci_init_struct(struct ieee80211_hw *hw,
1006 struct pci_dev *pdev)
1007{
1008 struct rtl_priv *rtlpriv = rtl_priv(hw);
1009 struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
1010 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
1011 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
0c817338
LF		 1012
1013 rtlpci->up_first_time = true;
1014 rtlpci->being_init_adapter = false;
1015
1016 rtlhal->hw = hw;
1017 rtlpci->pdev = pdev;
1018
0c817338
LF		 1019 /*Tx/Rx related var */
1020 _rtl_pci_init_trx_var(hw);
1021
c7cfe38e 1022 /*IBSS*/ mac->beacon_interval = 100;
0c817338 1023
c7cfe38e
C		 1024 /*AMPDU*/
1025 mac->min_space_cfg = 0;
0c817338
LF		 1026 mac->max_mss_density = 0;
1027 /*set sane AMPDU defaults */
1028 mac->current_ampdu_density = 7;
1029 mac->current_ampdu_factor = 3;
1030
c7cfe38e
C		 1031 /*QOS*/
1032 rtlpci->acm_method = eAcmWay2_SW;
0c817338
LF		 1033
1034 /*task */
1035 tasklet_init(&rtlpriv->works.irq_tasklet,
1036 (void (*)(unsigned long))_rtl_pci_irq_tasklet,
1037 (unsigned long)hw);
1038 tasklet_init(&rtlpriv->works.irq_prepare_bcn_tasklet,
1039 (void (*)(unsigned long))_rtl_pci_prepare_bcn_tasklet,
1040 (unsigned long)hw);
1041}
1042
1043static int _rtl_pci_init_tx_ring(struct ieee80211_hw *hw,
1044 unsigned int prio, unsigned int entries)
1045{
1046 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
1047 struct rtl_priv *rtlpriv = rtl_priv(hw);
1048 struct rtl_tx_desc *ring;
1049 dma_addr_t dma;
1050 u32 nextdescaddress;
1051 int i;
1052
1053 ring = pci_alloc_consistent(rtlpci->pdev,
1054 sizeof(*ring) * entries, &dma);
1055
1056 if (!ring || (unsigned long)ring & 0xFF) {
1057 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
1058 ("Cannot allocate TX ring (prio = %d)\n", prio));
1059 return -ENOMEM;
1060 }
1061
1062 memset(ring, 0, sizeof(*ring) * entries);
1063 rtlpci->tx_ring[prio].desc = ring;
1064 rtlpci->tx_ring[prio].dma = dma;
1065 rtlpci->tx_ring[prio].idx = 0;
1066 rtlpci->tx_ring[prio].entries = entries;
1067 skb_queue_head_init(&rtlpci->tx_ring[prio].queue);
1068
1069 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
1070 ("queue:%d, ring_addr:%p\n", prio, ring));
1071
1072 for (i = 0; i < entries; i++) {
d3bb1429 1073 nextdescaddress = (u32) dma +
982d96bb 1074 ((i + 1) % entries) *
d3bb1429 1075 sizeof(*ring);
0c817338
LF		 1076
1077 rtlpriv->cfg->ops->set_desc((u8 *)&(ring[i]),
1078 true, HW_DESC_TX_NEXTDESC_ADDR,
1079 (u8 *)&nextdescaddress);
1080 }
1081
1082 return 0;
1083}
1084
1085static int _rtl_pci_init_rx_ring(struct ieee80211_hw *hw)
1086{
1087 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
1088 struct rtl_priv *rtlpriv = rtl_priv(hw);
1089 struct rtl_rx_desc *entry = NULL;
1090 int i, rx_queue_idx;
1091 u8 tmp_one = 1;
1092
1093 /*
1094 *rx_queue_idx 0:RX_MPDU_QUEUE
1095 *rx_queue_idx 1:RX_CMD_QUEUE
1096 */
1097 for (rx_queue_idx = 0; rx_queue_idx < RTL_PCI_MAX_RX_QUEUE;
1098 rx_queue_idx++) {
1099 rtlpci->rx_ring[rx_queue_idx].desc =
1100 pci_alloc_consistent(rtlpci->pdev,
1101 sizeof(*rtlpci->rx_ring[rx_queue_idx].
1102 desc) * rtlpci->rxringcount,
1103 &rtlpci->rx_ring[rx_queue_idx].dma);
1104
1105 if (!rtlpci->rx_ring[rx_queue_idx].desc ||
1106 (unsigned long)rtlpci->rx_ring[rx_queue_idx].desc & 0xFF) {
1107 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
1108 ("Cannot allocate RX ring\n"));
1109 return -ENOMEM;
1110 }
1111
1112 memset(rtlpci->rx_ring[rx_queue_idx].desc, 0,
1113 sizeof(*rtlpci->rx_ring[rx_queue_idx].desc) *
1114 rtlpci->rxringcount);
1115
1116 rtlpci->rx_ring[rx_queue_idx].idx = 0;
1117
1118 for (i = 0; i < rtlpci->rxringcount; i++) {
1119 struct sk_buff *skb =
1120 dev_alloc_skb(rtlpci->rxbuffersize);
1121 u32 bufferaddress;
0c817338
LF		 1122 if (!skb)
1123 return 0;
bdc4bf65 1124 entry = &rtlpci->rx_ring[rx_queue_idx].desc[i];
0c817338
LF		 1125
1126 /*skb->dev = dev; */
1127
1128 rtlpci->rx_ring[rx_queue_idx].rx_buf[i] = skb;
1129
1130 /*
1131 *just set skb->cb to mapping addr
1132 *for pci_unmap_single use
1133 */
1134 *((dma_addr_t *) skb->cb) =
1135 pci_map_single(rtlpci->pdev, skb_tail_pointer(skb),
1136 rtlpci->rxbuffersize,
1137 PCI_DMA_FROMDEVICE);
1138
d3bb1429 1139 bufferaddress = (*((dma_addr_t *)skb->cb));
0c817338
LF		 1140 rtlpriv->cfg->ops->set_desc((u8 *)entry, false,
1141 HW_DESC_RXBUFF_ADDR,
1142 (u8 *)&bufferaddress);
1143 rtlpriv->cfg->ops->set_desc((u8 *)entry, false,
1144 HW_DESC_RXPKT_LEN,
1145 (u8 *)&rtlpci->
1146 rxbuffersize);
1147 rtlpriv->cfg->ops->set_desc((u8 *) entry, false,
1148 HW_DESC_RXOWN,
1149 (u8 *)&tmp_one);
1150 }
1151
1152 rtlpriv->cfg->ops->set_desc((u8 *) entry, false,
1153 HW_DESC_RXERO, (u8 *)&tmp_one);
1154 }
1155 return 0;
1156}
1157
1158static void _rtl_pci_free_tx_ring(struct ieee80211_hw *hw,
1159 unsigned int prio)
1160{
1161 struct rtl_priv *rtlpriv = rtl_priv(hw);
1162 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
1163 struct rtl8192_tx_ring *ring = &rtlpci->tx_ring[prio];
1164
1165 while (skb_queue_len(&ring->queue)) {
1166 struct rtl_tx_desc *entry = &ring->desc[ring->idx];
1167 struct sk_buff *skb = __skb_dequeue(&ring->queue);
1168
1169 pci_unmap_single(rtlpci->pdev,
d3bb1429 1170 rtlpriv->cfg->
0c817338 1171 ops->get_desc((u8 *) entry, true,
d3bb1429 1172 HW_DESC_TXBUFF_ADDR),
0c817338
LF		 1173 skb->len, PCI_DMA_TODEVICE);
1174 kfree_skb(skb);
1175 ring->idx = (ring->idx + 1) % ring->entries;
1176 }
1177
1178 pci_free_consistent(rtlpci->pdev,
1179 sizeof(*ring->desc) * ring->entries,
1180 ring->desc, ring->dma);
1181 ring->desc = NULL;
1182}
1183
1184static void _rtl_pci_free_rx_ring(struct rtl_pci *rtlpci)
1185{
1186 int i, rx_queue_idx;
1187
1188 /*rx_queue_idx 0:RX_MPDU_QUEUE */
1189 /*rx_queue_idx 1:RX_CMD_QUEUE */
1190 for (rx_queue_idx = 0; rx_queue_idx < RTL_PCI_MAX_RX_QUEUE;
1191 rx_queue_idx++) {
1192 for (i = 0; i < rtlpci->rxringcount; i++) {
1193 struct sk_buff *skb =
1194 rtlpci->rx_ring[rx_queue_idx].rx_buf[i];
1195 if (!skb)
1196 continue;
1197
1198 pci_unmap_single(rtlpci->pdev,
1199 *((dma_addr_t *) skb->cb),
1200 rtlpci->rxbuffersize,
1201 PCI_DMA_FROMDEVICE);
1202 kfree_skb(skb);
1203 }
1204
1205 pci_free_consistent(rtlpci->pdev,
1206 sizeof(*rtlpci->rx_ring[rx_queue_idx].
1207 desc) * rtlpci->rxringcount,
1208 rtlpci->rx_ring[rx_queue_idx].desc,
1209 rtlpci->rx_ring[rx_queue_idx].dma);
1210 rtlpci->rx_ring[rx_queue_idx].desc = NULL;
1211 }
1212}
1213
1214static int _rtl_pci_init_trx_ring(struct ieee80211_hw *hw)
1215{
1216 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
1217 int ret;
1218 int i;
1219
1220 ret = _rtl_pci_init_rx_ring(hw);
1221 if (ret)
1222 return ret;
1223
1224 for (i = 0; i < RTL_PCI_MAX_TX_QUEUE_COUNT; i++) {
1225 ret = _rtl_pci_init_tx_ring(hw, i,
1226 rtlpci->txringcount[i]);
1227 if (ret)
1228 goto err_free_rings;
1229 }
1230
1231 return 0;
1232
1233err_free_rings:
1234 _rtl_pci_free_rx_ring(rtlpci);
1235
1236 for (i = 0; i < RTL_PCI_MAX_TX_QUEUE_COUNT; i++)
1237 if (rtlpci->tx_ring[i].desc)
1238 _rtl_pci_free_tx_ring(hw, i);
1239
1240 return 1;
1241}
1242
1243static int _rtl_pci_deinit_trx_ring(struct ieee80211_hw *hw)
1244{
1245 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
1246 u32 i;
1247
1248 /*free rx rings */
1249 _rtl_pci_free_rx_ring(rtlpci);
1250
1251 /*free tx rings */
1252 for (i = 0; i < RTL_PCI_MAX_TX_QUEUE_COUNT; i++)
1253 _rtl_pci_free_tx_ring(hw, i);
1254
1255 return 0;
1256}
1257
1258int rtl_pci_reset_trx_ring(struct ieee80211_hw *hw)
1259{
1260 struct rtl_priv *rtlpriv = rtl_priv(hw);
1261 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
1262 int i, rx_queue_idx;
1263 unsigned long flags;
1264 u8 tmp_one = 1;
1265
1266 /*rx_queue_idx 0:RX_MPDU_QUEUE */
1267 /*rx_queue_idx 1:RX_CMD_QUEUE */
1268 for (rx_queue_idx = 0; rx_queue_idx < RTL_PCI_MAX_RX_QUEUE;
1269 rx_queue_idx++) {
1270 /*
1271 *force the rx_ring[RX_MPDU_QUEUE/
1272 *RX_CMD_QUEUE].idx to the first one
1273 */
1274 if (rtlpci->rx_ring[rx_queue_idx].desc) {
1275 struct rtl_rx_desc *entry = NULL;
1276
1277 for (i = 0; i < rtlpci->rxringcount; i++) {
1278 entry = &rtlpci->rx_ring[rx_queue_idx].desc[i];
1279 rtlpriv->cfg->ops->set_desc((u8 *) entry,
1280 false,
1281 HW_DESC_RXOWN,
1282 (u8 *)&tmp_one);
1283 }
1284 rtlpci->rx_ring[rx_queue_idx].idx = 0;
1285 }
1286 }
1287
1288 /*
1289 *after reset, release previous pending packet,
1290 *and force the tx idx to the first one
1291 */
1292 spin_lock_irqsave(&rtlpriv->locks.irq_th_lock, flags);
1293 for (i = 0; i < RTL_PCI_MAX_TX_QUEUE_COUNT; i++) {
1294 if (rtlpci->tx_ring[i].desc) {
1295 struct rtl8192_tx_ring *ring = &rtlpci->tx_ring[i];
1296
1297 while (skb_queue_len(&ring->queue)) {
1298 struct rtl_tx_desc *entry =
1299 &ring->desc[ring->idx];
1300 struct sk_buff *skb =
1301 __skb_dequeue(&ring->queue);
1302
1303 pci_unmap_single(rtlpci->pdev,
d3bb1429 1304 rtlpriv->cfg->ops->
0c817338
LF		 1305 get_desc((u8 *)
1306 entry,
1307 true,
d3bb1429 1308 HW_DESC_TXBUFF_ADDR),
0c817338
LF		 1309 skb->len, PCI_DMA_TODEVICE);
1310 kfree_skb(skb);
1311 ring->idx = (ring->idx + 1) % ring->entries;
1312 }
1313 ring->idx = 0;
1314 }
1315 }
1316
1317 spin_unlock_irqrestore(&rtlpriv->locks.irq_th_lock, flags);
1318
1319 return 0;
1320}
1321
c7cfe38e
C		 1322static bool rtl_pci_tx_chk_waitq_insert(struct ieee80211_hw *hw,
1323 struct sk_buff *skb)
0c817338 1324{
c7cfe38e
C		 1325 struct rtl_priv *rtlpriv = rtl_priv(hw);
1326 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
1327 struct ieee80211_sta *sta = info->control.sta;
1328 struct rtl_sta_info *sta_entry = NULL;
1329 u8 tid = rtl_get_tid(skb);
1330
1331 if (!sta)
1332 return false;
1333 sta_entry = (struct rtl_sta_info *)sta->drv_priv;
1334
1335 if (!rtlpriv->rtlhal.earlymode_enable)
1336 return false;
1337 if (sta_entry->tids[tid].agg.agg_state != RTL_AGG_OPERATIONAL)
1338 return false;
1339 if (_rtl_mac_to_hwqueue(hw, skb) > VO_QUEUE)
1340 return false;
1341 if (tid > 7)
1342 return false;
1343
1344 /* maybe every tid should be checked */
1345 if (!rtlpriv->link_info.higher_busytxtraffic[tid])
1346 return false;
1347
1348 spin_lock_bh(&rtlpriv->locks.waitq_lock);
1349 skb_queue_tail(&rtlpriv->mac80211.skb_waitq[tid], skb);
1350 spin_unlock_bh(&rtlpriv->locks.waitq_lock);
0c817338 1351
c7cfe38e 1352 return true;
0c817338
LF		 1353}
1354
d3bb1429 1355static int rtl_pci_tx(struct ieee80211_hw *hw, struct sk_buff *skb,
c7cfe38e 1356 struct rtl_tcb_desc *ptcb_desc)
0c817338
LF		 1357{
1358 struct rtl_priv *rtlpriv = rtl_priv(hw);
c7cfe38e 1359 struct rtl_sta_info *sta_entry = NULL;
0c817338 1360 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
c7cfe38e 1361 struct ieee80211_sta *sta = info->control.sta;
0c817338
LF		 1362 struct rtl8192_tx_ring *ring;
1363 struct rtl_tx_desc *pdesc;
1364 u8 idx;
c7cfe38e 1365 u8 hw_queue = _rtl_mac_to_hwqueue(hw, skb);
0c817338 1366 unsigned long flags;
c7cfe38e
C		 1367 struct ieee80211_hdr *hdr = rtl_get_hdr(skb);
1368 __le16 fc = rtl_get_fc(skb);
0c817338
LF		 1369 u8 *pda_addr = hdr->addr1;
1370 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
1371 /*ssn */
0c817338
LF		 1372 u8 tid = 0;
1373 u16 seq_number = 0;
1374 u8 own;
1375 u8 temp_one = 1;
1376
c7cfe38e
C		 1377 if (ieee80211_is_auth(fc)) {
1378 RT_TRACE(rtlpriv, COMP_SEND, DBG_DMESG, ("MAC80211_LINKING\n"));
1379 rtl_ips_nic_on(hw);
1380 }
1381
1382 if (rtlpriv->psc.sw_ps_enabled) {
1383 if (ieee80211_is_data(fc) && !ieee80211_is_nullfunc(fc) &&
1384 !ieee80211_has_pm(fc))
1385 hdr->frame_control |= cpu_to_le16(IEEE80211_FCTL_PM);
1386 }
0c817338 1387
c7cfe38e 1388 rtl_action_proc(hw, skb, true);
0c817338
LF		 1389
1390 if (is_multicast_ether_addr(pda_addr))
1391 rtlpriv->stats.txbytesmulticast += skb->len;
1392 else if (is_broadcast_ether_addr(pda_addr))
1393 rtlpriv->stats.txbytesbroadcast += skb->len;
1394 else
1395 rtlpriv->stats.txbytesunicast += skb->len;
1396
1397 spin_lock_irqsave(&rtlpriv->locks.irq_th_lock, flags);
0c817338
LF		 1398 ring = &rtlpci->tx_ring[hw_queue];
1399 if (hw_queue != BEACON_QUEUE)
1400 idx = (ring->idx + skb_queue_len(&ring->queue)) %
1401 ring->entries;
1402 else
1403 idx = 0;
1404
1405 pdesc = &ring->desc[idx];
1406 own = (u8) rtlpriv->cfg->ops->get_desc((u8 *) pdesc,
1407 true, HW_DESC_OWN);
1408
1409 if ((own == 1) && (hw_queue != BEACON_QUEUE)) {
1410 RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING,
1411 ("No more TX desc@%d, ring->idx = %d,"
1412 "idx = %d, skb_queue_len = 0x%d\n",
1413 hw_queue, ring->idx, idx,
1414 skb_queue_len(&ring->queue)));
1415
1416 spin_unlock_irqrestore(&rtlpriv->locks.irq_th_lock, flags);
1417 return skb->len;
1418 }
1419
0c817338 1420 if (ieee80211_is_data_qos(fc)) {
c7cfe38e
C		 1421 tid = rtl_get_tid(skb);
1422 if (sta) {
1423 sta_entry = (struct rtl_sta_info *)sta->drv_priv;
1424 seq_number = (le16_to_cpu(hdr->seq_ctrl) &
1425 IEEE80211_SCTL_SEQ) >> 4;
1426 seq_number += 1;
1427
1428 if (!ieee80211_has_morefrags(hdr->frame_control))
1429 sta_entry->tids[tid].seq_number = seq_number;
1430 }
0c817338
LF		 1431 }
1432
1433 if (ieee80211_is_data(fc))
1434 rtlpriv->cfg->ops->led_control(hw, LED_CTL_TX);
1435
c7cfe38e
C		 1436 rtlpriv->cfg->ops->fill_tx_desc(hw, hdr, (u8 *)pdesc,
1437 info, skb, hw_queue, ptcb_desc);
0c817338
LF		 1438
1439 __skb_queue_tail(&ring->queue, skb);
1440
c7cfe38e 1441 rtlpriv->cfg->ops->set_desc((u8 *)pdesc, true,
0c817338
LF		 1442 HW_DESC_OWN, (u8 *)&temp_one);
1443
0c817338
LF		 1444
1445 if ((ring->entries - skb_queue_len(&ring->queue)) < 2 &&
1446 hw_queue != BEACON_QUEUE) {
1447
1448 RT_TRACE(rtlpriv, COMP_ERR, DBG_LOUD,
1449 ("less desc left, stop skb_queue@%d, "
1450 "ring->idx = %d,"
1451 "idx = %d, skb_queue_len = 0x%d\n",
1452 hw_queue, ring->idx, idx,
1453 skb_queue_len(&ring->queue)));
1454
1455 ieee80211_stop_queue(hw, skb_get_queue_mapping(skb));
1456 }
1457
1458 spin_unlock_irqrestore(&rtlpriv->locks.irq_th_lock, flags);
1459
1460 rtlpriv->cfg->ops->tx_polling(hw, hw_queue);
1461
1462 return 0;
1463}
1464
c7cfe38e
C		 1465static void rtl_pci_flush(struct ieee80211_hw *hw, bool drop)
1466{
1467 struct rtl_priv *rtlpriv = rtl_priv(hw);
1468 struct rtl_pci_priv *pcipriv = rtl_pcipriv(hw);
1469 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
1470 u16 i = 0;
1471 int queue_id;
1472 struct rtl8192_tx_ring *ring;
1473
1474 for (queue_id = RTL_PCI_MAX_TX_QUEUE_COUNT - 1; queue_id >= 0;) {
1475 u32 queue_len;
1476 ring = &pcipriv->dev.tx_ring[queue_id];
1477 queue_len = skb_queue_len(&ring->queue);
1478 if (queue_len == 0 || queue_id == BEACON_QUEUE ||
1479 queue_id == TXCMD_QUEUE) {
1480 queue_id--;
1481 continue;
1482 } else {
1483 msleep(20);
1484 i++;
1485 }
1486
1487 /* we just wait 1s for all queues */
1488 if (rtlpriv->psc.rfpwr_state == ERFOFF ||
1489 is_hal_stop(rtlhal) || i >= 200)
1490 return;
1491 }
1492}
1493
d3bb1429 1494static void rtl_pci_deinit(struct ieee80211_hw *hw)
0c817338
LF		 1495{
1496 struct rtl_priv *rtlpriv = rtl_priv(hw);
1497 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
1498
1499 _rtl_pci_deinit_trx_ring(hw);
1500
1501 synchronize_irq(rtlpci->pdev->irq);
1502 tasklet_kill(&rtlpriv->works.irq_tasklet);
1503
1504 flush_workqueue(rtlpriv->works.rtl_wq);
1505 destroy_workqueue(rtlpriv->works.rtl_wq);
1506
1507}
1508
d3bb1429 1509static int rtl_pci_init(struct ieee80211_hw *hw, struct pci_dev *pdev)
0c817338
LF		 1510{
1511 struct rtl_priv *rtlpriv = rtl_priv(hw);
1512 int err;
1513
1514 _rtl_pci_init_struct(hw, pdev);
1515
1516 err = _rtl_pci_init_trx_ring(hw);
1517 if (err) {
1518 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
1519 ("tx ring initialization failed"));
1520 return err;
1521 }
1522
1523 return 1;
1524}
1525
d3bb1429 1526static int rtl_pci_start(struct ieee80211_hw *hw)
0c817338
LF		 1527{
1528 struct rtl_priv *rtlpriv = rtl_priv(hw);
1529 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
1530 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
1531 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
1532
1533 int err;
1534
1535 rtl_pci_reset_trx_ring(hw);
1536
1537 rtlpci->driver_is_goingto_unload = false;
1538 err = rtlpriv->cfg->ops->hw_init(hw);
1539 if (err) {
1540 RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG,
1541 ("Failed to config hardware!\n"));
1542 return err;
1543 }
1544
1545 rtlpriv->cfg->ops->enable_interrupt(hw);
1546 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, ("enable_interrupt OK\n"));
1547
1548 rtl_init_rx_config(hw);
1549
1550 /*should after adapter start and interrupt enable. */
1551 set_hal_start(rtlhal);
1552
1553 RT_CLEAR_PS_LEVEL(ppsc, RT_RF_OFF_LEVL_HALT_NIC);
1554
1555 rtlpci->up_first_time = false;
1556
1557 RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG, ("OK\n"));
1558 return 0;
1559}
1560
d3bb1429 1561static void rtl_pci_stop(struct ieee80211_hw *hw)
0c817338
LF		 1562{
1563 struct rtl_priv *rtlpriv = rtl_priv(hw);
1564 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
1565 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
1566 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
1567 unsigned long flags;
1568 u8 RFInProgressTimeOut = 0;
1569
1570 /*
1571 *should before disable interrrupt&adapter
1572 *and will do it immediately.
1573 */
1574 set_hal_stop(rtlhal);
1575
1576 rtlpriv->cfg->ops->disable_interrupt(hw);
1577
1578 spin_lock_irqsave(&rtlpriv->locks.rf_ps_lock, flags);
1579 while (ppsc->rfchange_inprogress) {
1580 spin_unlock_irqrestore(&rtlpriv->locks.rf_ps_lock, flags);
1581 if (RFInProgressTimeOut > 100) {
1582 spin_lock_irqsave(&rtlpriv->locks.rf_ps_lock, flags);
1583 break;
1584 }
1585 mdelay(1);
1586 RFInProgressTimeOut++;
1587 spin_lock_irqsave(&rtlpriv->locks.rf_ps_lock, flags);
1588 }
1589 ppsc->rfchange_inprogress = true;
1590 spin_unlock_irqrestore(&rtlpriv->locks.rf_ps_lock, flags);
1591
1592 rtlpci->driver_is_goingto_unload = true;
1593 rtlpriv->cfg->ops->hw_disable(hw);
1594 rtlpriv->cfg->ops->led_control(hw, LED_CTL_POWER_OFF);
1595
1596 spin_lock_irqsave(&rtlpriv->locks.rf_ps_lock, flags);
1597 ppsc->rfchange_inprogress = false;
1598 spin_unlock_irqrestore(&rtlpriv->locks.rf_ps_lock, flags);
1599
1600 rtl_pci_enable_aspm(hw);
1601}
1602
1603static bool _rtl_pci_find_adapter(struct pci_dev *pdev,
1604 struct ieee80211_hw *hw)
1605{
1606 struct rtl_priv *rtlpriv = rtl_priv(hw);
1607 struct rtl_pci_priv *pcipriv = rtl_pcipriv(hw);
1608 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
1609 struct pci_dev *bridge_pdev = pdev->bus->self;
1610 u16 venderid;
1611 u16 deviceid;
c7cfe38e 1612 u8 revisionid;
0c817338
LF		 1613 u16 irqline;
1614 u8 tmp;
1615
fc7707a4 1616 pcipriv->ndis_adapter.pcibridge_vendor = PCI_BRIDGE_VENDOR_UNKNOWN;
0c817338
LF		 1617 venderid = pdev->vendor;
1618 deviceid = pdev->device;
c7cfe38e 1619 pci_read_config_byte(pdev, 0x8, &revisionid);
0c817338
LF		 1620 pci_read_config_word(pdev, 0x3C, &irqline);
1621
1622 if (deviceid == RTL_PCI_8192_DID ||
1623 deviceid == RTL_PCI_0044_DID ||
1624 deviceid == RTL_PCI_0047_DID ||
1625 deviceid == RTL_PCI_8192SE_DID ||
1626 deviceid == RTL_PCI_8174_DID ||
1627 deviceid == RTL_PCI_8173_DID ||
1628 deviceid == RTL_PCI_8172_DID ||
1629 deviceid == RTL_PCI_8171_DID) {
c7cfe38e 1630 switch (revisionid) {
0c817338
LF		 1631 case RTL_PCI_REVISION_ID_8192PCIE:
1632 RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG,
1633 ("8192 PCI-E is found - "
1634 "vid/did=%x/%x\n", venderid, deviceid));
1635 rtlhal->hw_type = HARDWARE_TYPE_RTL8192E;
1636 break;
1637 case RTL_PCI_REVISION_ID_8192SE:
1638 RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG,
1639 ("8192SE is found - "
1640 "vid/did=%x/%x\n", venderid, deviceid));
1641 rtlhal->hw_type = HARDWARE_TYPE_RTL8192SE;
1642 break;
1643 default:
1644 RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING,
1645 ("Err: Unknown device - "
1646 "vid/did=%x/%x\n", venderid, deviceid));
1647 rtlhal->hw_type = HARDWARE_TYPE_RTL8192SE;
1648 break;
1649
1650 }
1651 } else if (deviceid == RTL_PCI_8192CET_DID ||
1652 deviceid == RTL_PCI_8192CE_DID ||
1653 deviceid == RTL_PCI_8191CE_DID ||
1654 deviceid == RTL_PCI_8188CE_DID) {
1655 rtlhal->hw_type = HARDWARE_TYPE_RTL8192CE;
1656 RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG,
1657 ("8192C PCI-E is found - "
1658 "vid/did=%x/%x\n", venderid, deviceid));
c7cfe38e
C		 1659 } else if (deviceid == RTL_PCI_8192DE_DID ||
1660 deviceid == RTL_PCI_8192DE_DID2) {
1661 rtlhal->hw_type = HARDWARE_TYPE_RTL8192DE;
1662 RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG,
1663 ("8192D PCI-E is found - "
1664 "vid/did=%x/%x\n", venderid, deviceid));
0c817338
LF		 1665 } else {
1666 RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING,
1667 ("Err: Unknown device -"
1668 " vid/did=%x/%x\n", venderid, deviceid));
1669
1670 rtlhal->hw_type = RTL_DEFAULT_HARDWARE_TYPE;
1671 }
1672
c7cfe38e
C		 1673 if (rtlhal->hw_type == HARDWARE_TYPE_RTL8192DE) {
1674 if (revisionid == 0 || revisionid == 1) {
1675 if (revisionid == 0) {
1676 RT_TRACE(rtlpriv, COMP_INIT,
1677 DBG_LOUD, ("Find 92DE MAC0.\n"));
1678 rtlhal->interfaceindex = 0;
1679 } else if (revisionid == 1) {
1680 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
1681 ("Find 92DE MAC1.\n"));
1682 rtlhal->interfaceindex = 1;
1683 }
1684 } else {
1685 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
1686 ("Unknown device - "
1687 "VendorID/DeviceID=%x/%x, Revision=%x\n",
1688 venderid, deviceid, revisionid));
1689 rtlhal->interfaceindex = 0;
1690 }
1691 }
0c817338
LF		 1692 /*find bus info */
1693 pcipriv->ndis_adapter.busnumber = pdev->bus->number;
1694 pcipriv->ndis_adapter.devnumber = PCI_SLOT(pdev->devfn);
1695 pcipriv->ndis_adapter.funcnumber = PCI_FUNC(pdev->devfn);
1696
1697 /*find bridge info */
1698 pcipriv->ndis_adapter.pcibridge_vendorid = bridge_pdev->vendor;
1699 for (tmp = 0; tmp < PCI_BRIDGE_VENDOR_MAX; tmp++) {
1700 if (bridge_pdev->vendor == pcibridge_vendors[tmp]) {
1701 pcipriv->ndis_adapter.pcibridge_vendor = tmp;
1702 RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG,
1703 ("Pci Bridge Vendor is found index: %d\n",
1704 tmp));
1705 break;
1706 }
1707 }
1708
1709 if (pcipriv->ndis_adapter.pcibridge_vendor !=
1710 PCI_BRIDGE_VENDOR_UNKNOWN) {
1711 pcipriv->ndis_adapter.pcibridge_busnum =
1712 bridge_pdev->bus->number;
1713 pcipriv->ndis_adapter.pcibridge_devnum =
1714 PCI_SLOT(bridge_pdev->devfn);
1715 pcipriv->ndis_adapter.pcibridge_funcnum =
1716 PCI_FUNC(bridge_pdev->devfn);
0c817338
LF		 1717 pcipriv->ndis_adapter.pcicfg_addrport =
1718 (pcipriv->ndis_adapter.pcibridge_busnum << 16) |
1719 (pcipriv->ndis_adapter.pcibridge_devnum << 11) |
1720 (pcipriv->ndis_adapter.pcibridge_funcnum << 8) | (1 << 31);
c7cfe38e
C		 1721 pcipriv->ndis_adapter.pcibridge_pciehdr_offset =
1722 pci_pcie_cap(bridge_pdev);
0c817338
LF		 1723 pcipriv->ndis_adapter.num4bytes =
1724 (pcipriv->ndis_adapter.pcibridge_pciehdr_offset + 0x10) / 4;
1725
1726 rtl_pci_get_linkcontrol_field(hw);
1727
1728 if (pcipriv->ndis_adapter.pcibridge_vendor ==
1729 PCI_BRIDGE_VENDOR_AMD) {
1730 pcipriv->ndis_adapter.amd_l1_patch =
1731 rtl_pci_get_amd_l1_patch(hw);
1732 }
1733 }
1734
1735 RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG,
1736 ("pcidev busnumber:devnumber:funcnumber:"
1737 "vendor:link_ctl %d:%d:%d:%x:%x\n",
1738 pcipriv->ndis_adapter.busnumber,
1739 pcipriv->ndis_adapter.devnumber,
1740 pcipriv->ndis_adapter.funcnumber,
1741 pdev->vendor, pcipriv->ndis_adapter.linkctrl_reg));
1742
1743 RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG,
1744 ("pci_bridge busnumber:devnumber:funcnumber:vendor:"
1745 "pcie_cap:link_ctl_reg:amd %d:%d:%d:%x:%x:%x:%x\n",
1746 pcipriv->ndis_adapter.pcibridge_busnum,
1747 pcipriv->ndis_adapter.pcibridge_devnum,
1748 pcipriv->ndis_adapter.pcibridge_funcnum,
1749 pcibridge_vendors[pcipriv->ndis_adapter.pcibridge_vendor],
1750 pcipriv->ndis_adapter.pcibridge_pciehdr_offset,
1751 pcipriv->ndis_adapter.pcibridge_linkctrlreg,
1752 pcipriv->ndis_adapter.amd_l1_patch));
1753
1754 rtl_pci_parse_configuration(pdev, hw);
1755
1756 return true;
1757}
1758
1759int __devinit rtl_pci_probe(struct pci_dev *pdev,
1760 const struct pci_device_id *id)
1761{
1762 struct ieee80211_hw *hw = NULL;
1763
1764 struct rtl_priv *rtlpriv = NULL;
1765 struct rtl_pci_priv *pcipriv = NULL;
1766 struct rtl_pci *rtlpci;
1767 unsigned long pmem_start, pmem_len, pmem_flags;
1768 int err;
1769
1770 err = pci_enable_device(pdev);
1771 if (err) {
1772 RT_ASSERT(false,
1773 ("%s : Cannot enable new PCI device\n",
1774 pci_name(pdev)));
1775 return err;
1776 }
1777
1778 if (!pci_set_dma_mask(pdev, DMA_BIT_MASK(32))) {
1779 if (pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32))) {
1780 RT_ASSERT(false, ("Unable to obtain 32bit DMA "
1781 "for consistent allocations\n"));
1782 pci_disable_device(pdev);
1783 return -ENOMEM;
1784 }
1785 }
1786
1787 pci_set_master(pdev);
1788
1789 hw = ieee80211_alloc_hw(sizeof(struct rtl_pci_priv) +
1790 sizeof(struct rtl_priv), &rtl_ops);
1791 if (!hw) {
1792 RT_ASSERT(false,
1793 ("%s : ieee80211 alloc failed\n", pci_name(pdev)));
1794 err = -ENOMEM;
1795 goto fail1;
1796 }
1797
1798 SET_IEEE80211_DEV(hw, &pdev->dev);
1799 pci_set_drvdata(pdev, hw);
1800
1801 rtlpriv = hw->priv;
1802 pcipriv = (void *)rtlpriv->priv;
1803 pcipriv->dev.pdev = pdev;
1804
c7cfe38e
C		 1805 /* init cfg & intf_ops */
1806 rtlpriv->rtlhal.interface = INTF_PCI;
1807 rtlpriv->cfg = (struct rtl_hal_cfg *)(id->driver_data);
1808 rtlpriv->intf_ops = &rtl_pci_ops;
1809
0c817338
LF		 1810 /*
1811 *init dbgp flags before all
1812 *other functions, because we will
1813 *use it in other funtions like
1814 *RT_TRACE/RT_PRINT/RTL_PRINT_DATA
1815 *you can not use these macro
1816 *before this
1817 */
1818 rtl_dbgp_flag_init(hw);
1819
1820 /* MEM map */
1821 err = pci_request_regions(pdev, KBUILD_MODNAME);
1822 if (err) {
1823 RT_ASSERT(false, ("Can't obtain PCI resources\n"));
1824 return err;
1825 }
1826
c7cfe38e
C		 1827 pmem_start = pci_resource_start(pdev, rtlpriv->cfg->bar_id);
1828 pmem_len = pci_resource_len(pdev, rtlpriv->cfg->bar_id);
1829 pmem_flags = pci_resource_flags(pdev, rtlpriv->cfg->bar_id);
0c817338
LF		 1830
1831 /*shared mem start */
1832 rtlpriv->io.pci_mem_start =
c7cfe38e
C		 1833 (unsigned long)pci_iomap(pdev,
1834 rtlpriv->cfg->bar_id, pmem_len);
0c817338
LF		 1835 if (rtlpriv->io.pci_mem_start == 0) {
1836 RT_ASSERT(false, ("Can't map PCI mem\n"));
1837 goto fail2;
1838 }
1839
1840 RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG,
1841 ("mem mapped space: start: 0x%08lx len:%08lx "
1842 "flags:%08lx, after map:0x%08lx\n",
1843 pmem_start, pmem_len, pmem_flags,
1844 rtlpriv->io.pci_mem_start));
1845
1846 /* Disable Clk Request */
1847 pci_write_config_byte(pdev, 0x81, 0);
1848 /* leave D3 mode */
1849 pci_write_config_byte(pdev, 0x44, 0);
1850 pci_write_config_byte(pdev, 0x04, 0x06);
1851 pci_write_config_byte(pdev, 0x04, 0x07);
1852
0c817338
LF		 1853 /* find adapter */
1854 _rtl_pci_find_adapter(pdev, hw);
1855
1856 /* Init IO handler */
1857 _rtl_pci_io_handler_init(&pdev->dev, hw);
1858
1859 /*like read eeprom and so on */
1860 rtlpriv->cfg->ops->read_eeprom_info(hw);
1861
1862 if (rtlpriv->cfg->ops->init_sw_vars(hw)) {
1863 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
1864 ("Can't init_sw_vars.\n"));
1865 goto fail3;
1866 }
1867
1868 rtlpriv->cfg->ops->init_sw_leds(hw);
1869
1870 /*aspm */
1871 rtl_pci_init_aspm(hw);
1872
1873 /* Init mac80211 sw */
1874 err = rtl_init_core(hw);
1875 if (err) {
1876 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
1877 ("Can't allocate sw for mac80211.\n"));
1878 goto fail3;
1879 }
1880
1881 /* Init PCI sw */
1882 err = !rtl_pci_init(hw, pdev);
1883 if (err) {
1884 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
1885 ("Failed to init PCI.\n"));
1886 goto fail3;
1887 }
1888
1889 err = ieee80211_register_hw(hw);
1890 if (err) {
1891 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
1892 ("Can't register mac80211 hw.\n"));
1893 goto fail3;
1894 } else {
1895 rtlpriv->mac80211.mac80211_registered = 1;
1896 }
1897
1898 err = sysfs_create_group(&pdev->dev.kobj, &rtl_attribute_group);
1899 if (err) {
1900 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
1901 ("failed to create sysfs device attributes\n"));
1902 goto fail3;
1903 }
1904
1905 /*init rfkill */
1906 rtl_init_rfkill(hw);
1907
1908 rtlpci = rtl_pcidev(pcipriv);
1909 err = request_irq(rtlpci->pdev->irq, &_rtl_pci_interrupt,
1910 IRQF_SHARED, KBUILD_MODNAME, hw);
1911 if (err) {
1912 RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG,
1913 ("%s: failed to register IRQ handler\n",
1914 wiphy_name(hw->wiphy)));
1915 goto fail3;
1916 } else {
1917 rtlpci->irq_alloc = 1;
1918 }
1919
1920 set_bit(RTL_STATUS_INTERFACE_START, &rtlpriv->status);
1921 return 0;
1922
1923fail3:
1924 pci_set_drvdata(pdev, NULL);
1925 rtl_deinit_core(hw);
1926 _rtl_pci_io_handler_release(hw);
1927 ieee80211_free_hw(hw);
1928
1929 if (rtlpriv->io.pci_mem_start != 0)
62e63975 1930 pci_iounmap(pdev, (void __iomem *)rtlpriv->io.pci_mem_start);
0c817338
LF		 1931
1932fail2:
1933 pci_release_regions(pdev);
1934
1935fail1:
1936
1937 pci_disable_device(pdev);
1938
1939 return -ENODEV;
1940
1941}
1942EXPORT_SYMBOL(rtl_pci_probe);
1943
1944void rtl_pci_disconnect(struct pci_dev *pdev)
1945{
1946 struct ieee80211_hw *hw = pci_get_drvdata(pdev);
1947 struct rtl_pci_priv *pcipriv = rtl_pcipriv(hw);
1948 struct rtl_priv *rtlpriv = rtl_priv(hw);
1949 struct rtl_pci *rtlpci = rtl_pcidev(pcipriv);
1950 struct rtl_mac *rtlmac = rtl_mac(rtlpriv);
1951
1952 clear_bit(RTL_STATUS_INTERFACE_START, &rtlpriv->status);
1953
1954 sysfs_remove_group(&pdev->dev.kobj, &rtl_attribute_group);
1955
1956 /*ieee80211_unregister_hw will call ops_stop */
1957 if (rtlmac->mac80211_registered == 1) {
1958 ieee80211_unregister_hw(hw);
1959 rtlmac->mac80211_registered = 0;
1960 } else {
1961 rtl_deinit_deferred_work(hw);
1962 rtlpriv->intf_ops->adapter_stop(hw);
1963 }
1964
1965 /*deinit rfkill */
1966 rtl_deinit_rfkill(hw);
1967
1968 rtl_pci_deinit(hw);
1969 rtl_deinit_core(hw);
0c817338
LF		 1970 _rtl_pci_io_handler_release(hw);
1971 rtlpriv->cfg->ops->deinit_sw_vars(hw);
1972
1973 if (rtlpci->irq_alloc) {
1974 free_irq(rtlpci->pdev->irq, hw);
1975 rtlpci->irq_alloc = 0;
1976 }
1977
1978 if (rtlpriv->io.pci_mem_start != 0) {
62e63975 1979 pci_iounmap(pdev, (void __iomem *)rtlpriv->io.pci_mem_start);
0c817338
LF		 1980 pci_release_regions(pdev);
1981 }
1982
1983 pci_disable_device(pdev);
c7cfe38e
C		 1984
1985 rtl_pci_disable_aspm(hw);
1986
0c817338
LF		 1987 pci_set_drvdata(pdev, NULL);
1988
1989 ieee80211_free_hw(hw);
1990}
1991EXPORT_SYMBOL(rtl_pci_disconnect);
1992
1993/***************************************
1994kernel pci power state define:
1995PCI_D0 ((pci_power_t __force) 0)
1996PCI_D1 ((pci_power_t __force) 1)
1997PCI_D2 ((pci_power_t __force) 2)
1998PCI_D3hot ((pci_power_t __force) 3)
1999PCI_D3cold ((pci_power_t __force) 4)
2000PCI_UNKNOWN ((pci_power_t __force) 5)
2001
2002This function is called when system
2003goes into suspend state mac80211 will
2004call rtl_mac_stop() from the mac80211
2005suspend function first, So there is
2006no need to call hw_disable here.
2007****************************************/
2008int rtl_pci_suspend(struct pci_dev *pdev, pm_message_t state)
2009{
c7cfe38e
C		 2010 struct ieee80211_hw *hw = pci_get_drvdata(pdev);
2011 struct rtl_priv *rtlpriv = rtl_priv(hw);
2012
2013 rtlpriv->cfg->ops->hw_suspend(hw);
2014 rtl_deinit_rfkill(hw);
2015
0c817338
LF		 2016 pci_save_state(pdev);
2017 pci_disable_device(pdev);
2018 pci_set_power_state(pdev, PCI_D3hot);
0c817338
LF		 2019 return 0;
2020}
2021EXPORT_SYMBOL(rtl_pci_suspend);
2022
2023int rtl_pci_resume(struct pci_dev *pdev)
2024{
2025 int ret;
c7cfe38e
C		 2026 struct ieee80211_hw *hw = pci_get_drvdata(pdev);
2027 struct rtl_priv *rtlpriv = rtl_priv(hw);
0c817338
LF		 2028
2029 pci_set_power_state(pdev, PCI_D0);
2030 ret = pci_enable_device(pdev);
2031 if (ret) {
2032 RT_ASSERT(false, ("ERR: <======\n"));
2033 return ret;
2034 }
2035
2036 pci_restore_state(pdev);
2037
c7cfe38e
C		 2038 rtlpriv->cfg->ops->hw_resume(hw);
2039 rtl_init_rfkill(hw);
0c817338
LF		 2040 return 0;
2041}
2042EXPORT_SYMBOL(rtl_pci_resume);
2043
2044struct rtl_intf_ops rtl_pci_ops = {
c7cfe38e 2045 .read_efuse_byte = read_efuse_byte,
0c817338
LF		 2046 .adapter_start = rtl_pci_start,
2047 .adapter_stop = rtl_pci_stop,
2048 .adapter_tx = rtl_pci_tx,
c7cfe38e 2049 .flush = rtl_pci_flush,
0c817338 2050 .reset_trx_ring = rtl_pci_reset_trx_ring,
c7cfe38e 2051 .waitq_insert = rtl_pci_tx_chk_waitq_insert,
0c817338
LF		 2052
2053 .disable_aspm = rtl_pci_disable_aspm,
2054 .enable_aspm = rtl_pci_enable_aspm,
2055};
Linux kernel - Deliverables
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