Commit | Line | Data |
---|---|---|
0c817338 LF |
1 | /****************************************************************************** |
2 | * | |
a8d76066 | 3 | * Copyright(c) 2009-2012 Realtek Corporation. |
0c817338 LF |
4 | * |
5 | * This program is free software; you can redistribute it and/or modify it | |
6 | * under the terms of version 2 of the GNU General Public License as | |
7 | * published by the Free Software Foundation. | |
8 | * | |
9 | * This program is distributed in the hope that it will be useful, but WITHOUT | |
10 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
11 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | |
12 | * more details. | |
13 | * | |
14 | * You should have received a copy of the GNU General Public License along with | |
15 | * this program; if not, write to the Free Software Foundation, Inc., | |
16 | * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA | |
17 | * | |
18 | * The full GNU General Public License is included in this distribution in the | |
19 | * file called LICENSE. | |
20 | * | |
21 | * Contact Information: | |
22 | * wlanfae <wlanfae@realtek.com> | |
23 | * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park, | |
24 | * Hsinchu 300, Taiwan. | |
25 | * | |
26 | * Larry Finger <Larry.Finger@lwfinger.net> | |
27 | * | |
28 | *****************************************************************************/ | |
29 | ||
0c817338 | 30 | #include "wifi.h" |
d273bb20 | 31 | #include "core.h" |
0c817338 LF |
32 | #include "pci.h" |
33 | #include "base.h" | |
34 | #include "ps.h" | |
c7cfe38e | 35 | #include "efuse.h" |
d273bb20 | 36 | #include <linux/export.h> |
f11bbfd8 | 37 | #include <linux/kmemleak.h> |
0c817338 LF |
38 | |
39 | static const u16 pcibridge_vendors[PCI_BRIDGE_VENDOR_MAX] = { | |
f01dce94 JM |
40 | PCI_VENDOR_ID_INTEL, |
41 | PCI_VENDOR_ID_ATI, | |
42 | PCI_VENDOR_ID_AMD, | |
43 | PCI_VENDOR_ID_SI | |
0c817338 LF |
44 | }; |
45 | ||
c7cfe38e C |
46 | static const u8 ac_to_hwq[] = { |
47 | VO_QUEUE, | |
48 | VI_QUEUE, | |
49 | BE_QUEUE, | |
50 | BK_QUEUE | |
51 | }; | |
52 | ||
d3bb1429 | 53 | static u8 _rtl_mac_to_hwqueue(struct ieee80211_hw *hw, |
c7cfe38e C |
54 | struct sk_buff *skb) |
55 | { | |
56 | struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw)); | |
d3bb1429 | 57 | __le16 fc = rtl_get_fc(skb); |
c7cfe38e C |
58 | u8 queue_index = skb_get_queue_mapping(skb); |
59 | ||
60 | if (unlikely(ieee80211_is_beacon(fc))) | |
61 | return BEACON_QUEUE; | |
62 | if (ieee80211_is_mgmt(fc)) | |
63 | return MGNT_QUEUE; | |
64 | if (rtlhal->hw_type == HARDWARE_TYPE_RTL8192SE) | |
65 | if (ieee80211_is_nullfunc(fc)) | |
66 | return HIGH_QUEUE; | |
67 | ||
68 | return ac_to_hwq[queue_index]; | |
69 | } | |
70 | ||
0c817338 LF |
71 | /* Update PCI dependent default settings*/ |
72 | static void _rtl_pci_update_default_setting(struct ieee80211_hw *hw) | |
73 | { | |
74 | struct rtl_priv *rtlpriv = rtl_priv(hw); | |
75 | struct rtl_pci_priv *pcipriv = rtl_pcipriv(hw); | |
76 | struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw)); | |
77 | struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw)); | |
78 | u8 pcibridge_vendor = pcipriv->ndis_adapter.pcibridge_vendor; | |
c7cfe38e | 79 | u8 init_aspm; |
0c817338 LF |
80 | |
81 | ppsc->reg_rfps_level = 0; | |
3db1cd5c | 82 | ppsc->support_aspm = false; |
0c817338 LF |
83 | |
84 | /*Update PCI ASPM setting */ | |
85 | ppsc->const_amdpci_aspm = rtlpci->const_amdpci_aspm; | |
86 | switch (rtlpci->const_pci_aspm) { | |
87 | case 0: | |
88 | /*No ASPM */ | |
89 | break; | |
90 | ||
91 | case 1: | |
92 | /*ASPM dynamically enabled/disable. */ | |
93 | ppsc->reg_rfps_level |= RT_RF_LPS_LEVEL_ASPM; | |
94 | break; | |
95 | ||
96 | case 2: | |
97 | /*ASPM with Clock Req dynamically enabled/disable. */ | |
98 | ppsc->reg_rfps_level |= (RT_RF_LPS_LEVEL_ASPM | | |
99 | RT_RF_OFF_LEVL_CLK_REQ); | |
100 | break; | |
101 | ||
102 | case 3: | |
103 | /* | |
104 | * Always enable ASPM and Clock Req | |
105 | * from initialization to halt. | |
106 | * */ | |
107 | ppsc->reg_rfps_level &= ~(RT_RF_LPS_LEVEL_ASPM); | |
108 | ppsc->reg_rfps_level |= (RT_RF_PS_LEVEL_ALWAYS_ASPM | | |
109 | RT_RF_OFF_LEVL_CLK_REQ); | |
110 | break; | |
111 | ||
112 | case 4: | |
113 | /* | |
114 | * Always enable ASPM without Clock Req | |
115 | * from initialization to halt. | |
116 | * */ | |
117 | ppsc->reg_rfps_level &= ~(RT_RF_LPS_LEVEL_ASPM | | |
118 | RT_RF_OFF_LEVL_CLK_REQ); | |
119 | ppsc->reg_rfps_level |= RT_RF_PS_LEVEL_ALWAYS_ASPM; | |
120 | break; | |
121 | } | |
122 | ||
123 | ppsc->reg_rfps_level |= RT_RF_OFF_LEVL_HALT_NIC; | |
124 | ||
125 | /*Update Radio OFF setting */ | |
126 | switch (rtlpci->const_hwsw_rfoff_d3) { | |
127 | case 1: | |
128 | if (ppsc->reg_rfps_level & RT_RF_LPS_LEVEL_ASPM) | |
129 | ppsc->reg_rfps_level |= RT_RF_OFF_LEVL_ASPM; | |
130 | break; | |
131 | ||
132 | case 2: | |
133 | if (ppsc->reg_rfps_level & RT_RF_LPS_LEVEL_ASPM) | |
134 | ppsc->reg_rfps_level |= RT_RF_OFF_LEVL_ASPM; | |
135 | ppsc->reg_rfps_level |= RT_RF_OFF_LEVL_HALT_NIC; | |
136 | break; | |
137 | ||
138 | case 3: | |
139 | ppsc->reg_rfps_level |= RT_RF_OFF_LEVL_PCI_D3; | |
140 | break; | |
141 | } | |
142 | ||
143 | /*Set HW definition to determine if it supports ASPM. */ | |
144 | switch (rtlpci->const_support_pciaspm) { | |
c7cfe38e C |
145 | case 0:{ |
146 | /*Not support ASPM. */ | |
147 | bool support_aspm = false; | |
148 | ppsc->support_aspm = support_aspm; | |
149 | break; | |
150 | } | |
151 | case 1:{ | |
152 | /*Support ASPM. */ | |
153 | bool support_aspm = true; | |
154 | bool support_backdoor = true; | |
155 | ppsc->support_aspm = support_aspm; | |
156 | ||
157 | /*if (priv->oem_id == RT_CID_TOSHIBA && | |
158 | !priv->ndis_adapter.amd_l1_patch) | |
159 | support_backdoor = false; */ | |
160 | ||
161 | ppsc->support_backdoor = support_backdoor; | |
162 | ||
163 | break; | |
164 | } | |
0c817338 LF |
165 | case 2: |
166 | /*ASPM value set by chipset. */ | |
c7cfe38e C |
167 | if (pcibridge_vendor == PCI_BRIDGE_VENDOR_INTEL) { |
168 | bool support_aspm = true; | |
169 | ppsc->support_aspm = support_aspm; | |
170 | } | |
0c817338 LF |
171 | break; |
172 | default: | |
173 | RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG, | |
f30d7507 | 174 | "switch case not processed\n"); |
0c817338 LF |
175 | break; |
176 | } | |
c7cfe38e C |
177 | |
178 | /* toshiba aspm issue, toshiba will set aspm selfly | |
179 | * so we should not set aspm in driver */ | |
180 | pci_read_config_byte(rtlpci->pdev, 0x80, &init_aspm); | |
181 | if (rtlpriv->rtlhal.hw_type == HARDWARE_TYPE_RTL8192SE && | |
182 | init_aspm == 0x43) | |
183 | ppsc->support_aspm = false; | |
184 | } | |
185 | ||
0c817338 LF |
186 | static bool _rtl_pci_platform_switch_device_pci_aspm( |
187 | struct ieee80211_hw *hw, | |
188 | u8 value) | |
189 | { | |
190 | struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw)); | |
c7cfe38e C |
191 | struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw)); |
192 | ||
193 | if (rtlhal->hw_type != HARDWARE_TYPE_RTL8192SE) | |
194 | value |= 0x40; | |
0c817338 | 195 | |
0c817338 LF |
196 | pci_write_config_byte(rtlpci->pdev, 0x80, value); |
197 | ||
32473284 | 198 | return false; |
0c817338 LF |
199 | } |
200 | ||
201 | /*When we set 0x01 to enable clk request. Set 0x0 to disable clk req.*/ | |
1d73c51a | 202 | static void _rtl_pci_switch_clk_req(struct ieee80211_hw *hw, u8 value) |
0c817338 LF |
203 | { |
204 | struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw)); | |
c7cfe38e | 205 | struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw)); |
0c817338 | 206 | |
0c817338 | 207 | pci_write_config_byte(rtlpci->pdev, 0x81, value); |
0c817338 | 208 | |
c7cfe38e C |
209 | if (rtlhal->hw_type == HARDWARE_TYPE_RTL8192SE) |
210 | udelay(100); | |
0c817338 LF |
211 | } |
212 | ||
213 | /*Disable RTL8192SE ASPM & Disable Pci Bridge ASPM*/ | |
214 | static void rtl_pci_disable_aspm(struct ieee80211_hw *hw) | |
215 | { | |
216 | struct rtl_priv *rtlpriv = rtl_priv(hw); | |
217 | struct rtl_pci_priv *pcipriv = rtl_pcipriv(hw); | |
218 | struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw)); | |
219 | struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw)); | |
220 | u8 pcibridge_vendor = pcipriv->ndis_adapter.pcibridge_vendor; | |
0c817338 LF |
221 | u8 num4bytes = pcipriv->ndis_adapter.num4bytes; |
222 | /*Retrieve original configuration settings. */ | |
223 | u8 linkctrl_reg = pcipriv->ndis_adapter.linkctrl_reg; | |
224 | u16 pcibridge_linkctrlreg = pcipriv->ndis_adapter. | |
225 | pcibridge_linkctrlreg; | |
226 | u16 aspmlevel = 0; | |
32473284 | 227 | u8 tmp_u1b = 0; |
0c817338 | 228 | |
c7cfe38e C |
229 | if (!ppsc->support_aspm) |
230 | return; | |
231 | ||
0c817338 LF |
232 | if (pcibridge_vendor == PCI_BRIDGE_VENDOR_UNKNOWN) { |
233 | RT_TRACE(rtlpriv, COMP_POWER, DBG_TRACE, | |
f30d7507 | 234 | "PCI(Bridge) UNKNOWN\n"); |
0c817338 LF |
235 | |
236 | return; | |
237 | } | |
238 | ||
239 | if (ppsc->reg_rfps_level & RT_RF_OFF_LEVL_CLK_REQ) { | |
240 | RT_CLEAR_PS_LEVEL(ppsc, RT_RF_OFF_LEVL_CLK_REQ); | |
241 | _rtl_pci_switch_clk_req(hw, 0x0); | |
242 | } | |
243 | ||
32473284 LF |
244 | /*for promising device will in L0 state after an I/O. */ |
245 | pci_read_config_byte(rtlpci->pdev, 0x80, &tmp_u1b); | |
0c817338 LF |
246 | |
247 | /*Set corresponding value. */ | |
248 | aspmlevel |= BIT(0) | BIT(1); | |
249 | linkctrl_reg &= ~aspmlevel; | |
250 | pcibridge_linkctrlreg &= ~(BIT(0) | BIT(1)); | |
251 | ||
252 | _rtl_pci_platform_switch_device_pci_aspm(hw, linkctrl_reg); | |
253 | udelay(50); | |
254 | ||
255 | /*4 Disable Pci Bridge ASPM */ | |
886e14b6 LF |
256 | pci_write_config_byte(rtlpci->pdev, (num4bytes << 2), |
257 | pcibridge_linkctrlreg); | |
0c817338 LF |
258 | |
259 | udelay(50); | |
0c817338 LF |
260 | } |
261 | ||
262 | /* | |
263 | *Enable RTL8192SE ASPM & Enable Pci Bridge ASPM for | |
264 | *power saving We should follow the sequence to enable | |
265 | *RTL8192SE first then enable Pci Bridge ASPM | |
266 | *or the system will show bluescreen. | |
267 | */ | |
268 | static void rtl_pci_enable_aspm(struct ieee80211_hw *hw) | |
269 | { | |
270 | struct rtl_priv *rtlpriv = rtl_priv(hw); | |
271 | struct rtl_pci_priv *pcipriv = rtl_pcipriv(hw); | |
272 | struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw)); | |
273 | struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw)); | |
274 | u8 pcibridge_busnum = pcipriv->ndis_adapter.pcibridge_busnum; | |
275 | u8 pcibridge_devnum = pcipriv->ndis_adapter.pcibridge_devnum; | |
276 | u8 pcibridge_funcnum = pcipriv->ndis_adapter.pcibridge_funcnum; | |
277 | u8 pcibridge_vendor = pcipriv->ndis_adapter.pcibridge_vendor; | |
0c817338 LF |
278 | u8 num4bytes = pcipriv->ndis_adapter.num4bytes; |
279 | u16 aspmlevel; | |
280 | u8 u_pcibridge_aspmsetting; | |
281 | u8 u_device_aspmsetting; | |
282 | ||
c7cfe38e C |
283 | if (!ppsc->support_aspm) |
284 | return; | |
285 | ||
0c817338 LF |
286 | if (pcibridge_vendor == PCI_BRIDGE_VENDOR_UNKNOWN) { |
287 | RT_TRACE(rtlpriv, COMP_POWER, DBG_TRACE, | |
f30d7507 | 288 | "PCI(Bridge) UNKNOWN\n"); |
0c817338 LF |
289 | return; |
290 | } | |
291 | ||
292 | /*4 Enable Pci Bridge ASPM */ | |
0c817338 LF |
293 | |
294 | u_pcibridge_aspmsetting = | |
295 | pcipriv->ndis_adapter.pcibridge_linkctrlreg | | |
296 | rtlpci->const_hostpci_aspm_setting; | |
297 | ||
298 | if (pcibridge_vendor == PCI_BRIDGE_VENDOR_INTEL) | |
299 | u_pcibridge_aspmsetting &= ~BIT(0); | |
300 | ||
886e14b6 LF |
301 | pci_write_config_byte(rtlpci->pdev, (num4bytes << 2), |
302 | u_pcibridge_aspmsetting); | |
0c817338 LF |
303 | |
304 | RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, | |
f30d7507 JP |
305 | "PlatformEnableASPM():PciBridge busnumber[%x], DevNumbe[%x], funcnumber[%x], Write reg[%x] = %x\n", |
306 | pcibridge_busnum, pcibridge_devnum, pcibridge_funcnum, | |
307 | (pcipriv->ndis_adapter.pcibridge_pciehdr_offset + 0x10), | |
308 | u_pcibridge_aspmsetting); | |
0c817338 LF |
309 | |
310 | udelay(50); | |
311 | ||
312 | /*Get ASPM level (with/without Clock Req) */ | |
313 | aspmlevel = rtlpci->const_devicepci_aspm_setting; | |
314 | u_device_aspmsetting = pcipriv->ndis_adapter.linkctrl_reg; | |
315 | ||
316 | /*_rtl_pci_platform_switch_device_pci_aspm(dev,*/ | |
317 | /*(priv->ndis_adapter.linkctrl_reg | ASPMLevel)); */ | |
318 | ||
319 | u_device_aspmsetting |= aspmlevel; | |
320 | ||
321 | _rtl_pci_platform_switch_device_pci_aspm(hw, u_device_aspmsetting); | |
322 | ||
323 | if (ppsc->reg_rfps_level & RT_RF_OFF_LEVL_CLK_REQ) { | |
324 | _rtl_pci_switch_clk_req(hw, (ppsc->reg_rfps_level & | |
325 | RT_RF_OFF_LEVL_CLK_REQ) ? 1 : 0); | |
326 | RT_SET_PS_LEVEL(ppsc, RT_RF_OFF_LEVL_CLK_REQ); | |
327 | } | |
c7cfe38e | 328 | udelay(100); |
0c817338 LF |
329 | } |
330 | ||
331 | static bool rtl_pci_get_amd_l1_patch(struct ieee80211_hw *hw) | |
332 | { | |
886e14b6 | 333 | struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw)); |
0c817338 LF |
334 | |
335 | bool status = false; | |
336 | u8 offset_e0; | |
337 | unsigned offset_e4; | |
338 | ||
886e14b6 | 339 | pci_write_config_byte(rtlpci->pdev, 0xe0, 0xa0); |
0c817338 | 340 | |
886e14b6 | 341 | pci_read_config_byte(rtlpci->pdev, 0xe0, &offset_e0); |
0c817338 LF |
342 | |
343 | if (offset_e0 == 0xA0) { | |
886e14b6 | 344 | pci_read_config_dword(rtlpci->pdev, 0xe4, &offset_e4); |
0c817338 LF |
345 | if (offset_e4 & BIT(23)) |
346 | status = true; | |
347 | } | |
348 | ||
349 | return status; | |
350 | } | |
351 | ||
d3bb1429 | 352 | static void rtl_pci_get_linkcontrol_field(struct ieee80211_hw *hw) |
0c817338 LF |
353 | { |
354 | struct rtl_pci_priv *pcipriv = rtl_pcipriv(hw); | |
886e14b6 | 355 | struct rtl_pci *rtlpci = rtl_pcidev(pcipriv); |
0c817338 | 356 | u8 capabilityoffset = pcipriv->ndis_adapter.pcibridge_pciehdr_offset; |
0c817338 | 357 | u8 linkctrl_reg; |
c7cfe38e | 358 | u8 num4bbytes; |
0c817338 | 359 | |
c7cfe38e | 360 | num4bbytes = (capabilityoffset + 0x10) / 4; |
0c817338 LF |
361 | |
362 | /*Read Link Control Register */ | |
886e14b6 | 363 | pci_read_config_byte(rtlpci->pdev, (num4bbytes << 2), &linkctrl_reg); |
0c817338 LF |
364 | |
365 | pcipriv->ndis_adapter.pcibridge_linkctrlreg = linkctrl_reg; | |
366 | } | |
367 | ||
368 | static void rtl_pci_parse_configuration(struct pci_dev *pdev, | |
369 | struct ieee80211_hw *hw) | |
370 | { | |
371 | struct rtl_priv *rtlpriv = rtl_priv(hw); | |
372 | struct rtl_pci_priv *pcipriv = rtl_pcipriv(hw); | |
373 | ||
374 | u8 tmp; | |
375 | int pos; | |
376 | u8 linkctrl_reg; | |
377 | ||
378 | /*Link Control Register */ | |
6a4ecc29 | 379 | pos = pci_pcie_cap(pdev); |
0c817338 LF |
380 | pci_read_config_byte(pdev, pos + PCI_EXP_LNKCTL, &linkctrl_reg); |
381 | pcipriv->ndis_adapter.linkctrl_reg = linkctrl_reg; | |
382 | ||
f30d7507 JP |
383 | RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE, "Link Control Register =%x\n", |
384 | pcipriv->ndis_adapter.linkctrl_reg); | |
0c817338 LF |
385 | |
386 | pci_read_config_byte(pdev, 0x98, &tmp); | |
387 | tmp |= BIT(4); | |
388 | pci_write_config_byte(pdev, 0x98, tmp); | |
389 | ||
390 | tmp = 0x17; | |
391 | pci_write_config_byte(pdev, 0x70f, tmp); | |
392 | } | |
393 | ||
c7cfe38e | 394 | static void rtl_pci_init_aspm(struct ieee80211_hw *hw) |
0c817338 LF |
395 | { |
396 | struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw)); | |
397 | ||
398 | _rtl_pci_update_default_setting(hw); | |
399 | ||
400 | if (ppsc->reg_rfps_level & RT_RF_PS_LEVEL_ALWAYS_ASPM) { | |
401 | /*Always enable ASPM & Clock Req. */ | |
402 | rtl_pci_enable_aspm(hw); | |
403 | RT_SET_PS_LEVEL(ppsc, RT_RF_PS_LEVEL_ALWAYS_ASPM); | |
404 | } | |
405 | ||
406 | } | |
407 | ||
0c817338 LF |
408 | static void _rtl_pci_io_handler_init(struct device *dev, |
409 | struct ieee80211_hw *hw) | |
410 | { | |
411 | struct rtl_priv *rtlpriv = rtl_priv(hw); | |
412 | ||
413 | rtlpriv->io.dev = dev; | |
414 | ||
415 | rtlpriv->io.write8_async = pci_write8_async; | |
416 | rtlpriv->io.write16_async = pci_write16_async; | |
417 | rtlpriv->io.write32_async = pci_write32_async; | |
418 | ||
419 | rtlpriv->io.read8_sync = pci_read8_sync; | |
420 | rtlpriv->io.read16_sync = pci_read16_sync; | |
421 | rtlpriv->io.read32_sync = pci_read32_sync; | |
422 | ||
423 | } | |
424 | ||
425 | static void _rtl_pci_io_handler_release(struct ieee80211_hw *hw) | |
426 | { | |
427 | } | |
428 | ||
c7cfe38e C |
429 | static bool _rtl_update_earlymode_info(struct ieee80211_hw *hw, |
430 | struct sk_buff *skb, struct rtl_tcb_desc *tcb_desc, u8 tid) | |
431 | { | |
432 | struct rtl_priv *rtlpriv = rtl_priv(hw); | |
433 | struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb); | |
434 | u8 additionlen = FCS_LEN; | |
435 | struct sk_buff *next_skb; | |
436 | ||
437 | /* here open is 4, wep/tkip is 8, aes is 12*/ | |
438 | if (info->control.hw_key) | |
439 | additionlen += info->control.hw_key->icv_len; | |
440 | ||
441 | /* The most skb num is 6 */ | |
442 | tcb_desc->empkt_num = 0; | |
443 | spin_lock_bh(&rtlpriv->locks.waitq_lock); | |
444 | skb_queue_walk(&rtlpriv->mac80211.skb_waitq[tid], next_skb) { | |
445 | struct ieee80211_tx_info *next_info; | |
446 | ||
447 | next_info = IEEE80211_SKB_CB(next_skb); | |
448 | if (next_info->flags & IEEE80211_TX_CTL_AMPDU) { | |
449 | tcb_desc->empkt_len[tcb_desc->empkt_num] = | |
450 | next_skb->len + additionlen; | |
451 | tcb_desc->empkt_num++; | |
452 | } else { | |
453 | break; | |
454 | } | |
455 | ||
456 | if (skb_queue_is_last(&rtlpriv->mac80211.skb_waitq[tid], | |
457 | next_skb)) | |
458 | break; | |
459 | ||
460 | if (tcb_desc->empkt_num >= 5) | |
461 | break; | |
462 | } | |
463 | spin_unlock_bh(&rtlpriv->locks.waitq_lock); | |
464 | ||
465 | return true; | |
466 | } | |
467 | ||
468 | /* just for early mode now */ | |
469 | static void _rtl_pci_tx_chk_waitq(struct ieee80211_hw *hw) | |
470 | { | |
471 | struct rtl_priv *rtlpriv = rtl_priv(hw); | |
472 | struct rtl_mac *mac = rtl_mac(rtl_priv(hw)); | |
473 | struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw)); | |
474 | struct sk_buff *skb = NULL; | |
475 | struct ieee80211_tx_info *info = NULL; | |
fb914ebf | 476 | int tid; |
c7cfe38e C |
477 | |
478 | if (!rtlpriv->rtlhal.earlymode_enable) | |
479 | return; | |
480 | ||
481 | /* we juse use em for BE/BK/VI/VO */ | |
482 | for (tid = 7; tid >= 0; tid--) { | |
483 | u8 hw_queue = ac_to_hwq[rtl_tid_to_ac(hw, tid)]; | |
484 | struct rtl8192_tx_ring *ring = &rtlpci->tx_ring[hw_queue]; | |
485 | while (!mac->act_scanning && | |
486 | rtlpriv->psc.rfpwr_state == ERFON) { | |
487 | struct rtl_tcb_desc tcb_desc; | |
488 | memset(&tcb_desc, 0, sizeof(struct rtl_tcb_desc)); | |
489 | ||
490 | spin_lock_bh(&rtlpriv->locks.waitq_lock); | |
491 | if (!skb_queue_empty(&mac->skb_waitq[tid]) && | |
492 | (ring->entries - skb_queue_len(&ring->queue) > 5)) { | |
493 | skb = skb_dequeue(&mac->skb_waitq[tid]); | |
494 | } else { | |
495 | spin_unlock_bh(&rtlpriv->locks.waitq_lock); | |
496 | break; | |
497 | } | |
498 | spin_unlock_bh(&rtlpriv->locks.waitq_lock); | |
499 | ||
500 | /* Some macaddr can't do early mode. like | |
501 | * multicast/broadcast/no_qos data */ | |
502 | info = IEEE80211_SKB_CB(skb); | |
503 | if (info->flags & IEEE80211_TX_CTL_AMPDU) | |
504 | _rtl_update_earlymode_info(hw, skb, | |
505 | &tcb_desc, tid); | |
506 | ||
c7cfe38e | 507 | rtlpriv->intf_ops->adapter_tx(hw, skb, &tcb_desc); |
c7cfe38e C |
508 | } |
509 | } | |
510 | } | |
511 | ||
512 | ||
0c817338 LF |
513 | static void _rtl_pci_tx_isr(struct ieee80211_hw *hw, int prio) |
514 | { | |
515 | struct rtl_priv *rtlpriv = rtl_priv(hw); | |
516 | struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw)); | |
517 | ||
518 | struct rtl8192_tx_ring *ring = &rtlpci->tx_ring[prio]; | |
519 | ||
520 | while (skb_queue_len(&ring->queue)) { | |
521 | struct rtl_tx_desc *entry = &ring->desc[ring->idx]; | |
522 | struct sk_buff *skb; | |
523 | struct ieee80211_tx_info *info; | |
c7cfe38e C |
524 | __le16 fc; |
525 | u8 tid; | |
0c817338 LF |
526 | |
527 | u8 own = (u8) rtlpriv->cfg->ops->get_desc((u8 *) entry, true, | |
528 | HW_DESC_OWN); | |
529 | ||
530 | /* | |
531 | *beacon packet will only use the first | |
532 | *descriptor defautly,and the own may not | |
533 | *be cleared by the hardware | |
534 | */ | |
535 | if (own) | |
536 | return; | |
537 | ring->idx = (ring->idx + 1) % ring->entries; | |
538 | ||
539 | skb = __skb_dequeue(&ring->queue); | |
540 | pci_unmap_single(rtlpci->pdev, | |
d3bb1429 | 541 | rtlpriv->cfg->ops-> |
0c817338 | 542 | get_desc((u8 *) entry, true, |
d3bb1429 | 543 | HW_DESC_TXBUFF_ADDR), |
0c817338 LF |
544 | skb->len, PCI_DMA_TODEVICE); |
545 | ||
c7cfe38e C |
546 | /* remove early mode header */ |
547 | if (rtlpriv->rtlhal.earlymode_enable) | |
548 | skb_pull(skb, EM_HDR_LEN); | |
549 | ||
0c817338 | 550 | RT_TRACE(rtlpriv, (COMP_INTR | COMP_SEND), DBG_TRACE, |
f30d7507 JP |
551 | "new ring->idx:%d, free: skb_queue_len:%d, free: seq:%x\n", |
552 | ring->idx, | |
553 | skb_queue_len(&ring->queue), | |
554 | *(u16 *) (skb->data + 22)); | |
0c817338 | 555 | |
c7cfe38e C |
556 | if (prio == TXCMD_QUEUE) { |
557 | dev_kfree_skb(skb); | |
558 | goto tx_status_ok; | |
559 | ||
560 | } | |
561 | ||
562 | /* for sw LPS, just after NULL skb send out, we can | |
563 | * sure AP kown we are sleeped, our we should not let | |
564 | * rf to sleep*/ | |
565 | fc = rtl_get_fc(skb); | |
566 | if (ieee80211_is_nullfunc(fc)) { | |
567 | if (ieee80211_has_pm(fc)) { | |
9c050440 | 568 | rtlpriv->mac80211.offchan_delay = true; |
3db1cd5c | 569 | rtlpriv->psc.state_inap = true; |
c7cfe38e | 570 | } else { |
3db1cd5c | 571 | rtlpriv->psc.state_inap = false; |
c7cfe38e C |
572 | } |
573 | } | |
574 | ||
575 | /* update tid tx pkt num */ | |
576 | tid = rtl_get_tid(skb); | |
577 | if (tid <= 7) | |
578 | rtlpriv->link_info.tidtx_inperiod[tid]++; | |
579 | ||
0c817338 LF |
580 | info = IEEE80211_SKB_CB(skb); |
581 | ieee80211_tx_info_clear_status(info); | |
582 | ||
583 | info->flags |= IEEE80211_TX_STAT_ACK; | |
584 | /*info->status.rates[0].count = 1; */ | |
585 | ||
586 | ieee80211_tx_status_irqsafe(hw, skb); | |
587 | ||
588 | if ((ring->entries - skb_queue_len(&ring->queue)) | |
589 | == 2) { | |
590 | ||
591 | RT_TRACE(rtlpriv, COMP_ERR, DBG_LOUD, | |
f30d7507 JP |
592 | "more desc left, wake skb_queue@%d, ring->idx = %d, skb_queue_len = 0x%d\n", |
593 | prio, ring->idx, | |
594 | skb_queue_len(&ring->queue)); | |
0c817338 LF |
595 | |
596 | ieee80211_wake_queue(hw, | |
597 | skb_get_queue_mapping | |
598 | (skb)); | |
599 | } | |
c7cfe38e | 600 | tx_status_ok: |
0c817338 LF |
601 | skb = NULL; |
602 | } | |
603 | ||
604 | if (((rtlpriv->link_info.num_rx_inperiod + | |
605 | rtlpriv->link_info.num_tx_inperiod) > 8) || | |
606 | (rtlpriv->link_info.num_rx_inperiod > 2)) { | |
41affd52 | 607 | schedule_work(&rtlpriv->works.lps_leave_work); |
0c817338 LF |
608 | } |
609 | } | |
610 | ||
fd854772 MM |
611 | static void _rtl_receive_one(struct ieee80211_hw *hw, struct sk_buff *skb, |
612 | struct ieee80211_rx_status rx_status) | |
613 | { | |
614 | struct rtl_priv *rtlpriv = rtl_priv(hw); | |
615 | struct ieee80211_hdr *hdr = rtl_get_hdr(skb); | |
616 | __le16 fc = rtl_get_fc(skb); | |
617 | bool unicast = false; | |
618 | struct sk_buff *uskb = NULL; | |
619 | u8 *pdata; | |
620 | ||
621 | ||
622 | memcpy(IEEE80211_SKB_RXCB(skb), &rx_status, sizeof(rx_status)); | |
623 | ||
624 | if (is_broadcast_ether_addr(hdr->addr1)) { | |
625 | ;/*TODO*/ | |
626 | } else if (is_multicast_ether_addr(hdr->addr1)) { | |
627 | ;/*TODO*/ | |
628 | } else { | |
629 | unicast = true; | |
630 | rtlpriv->stats.rxbytesunicast += skb->len; | |
631 | } | |
632 | ||
633 | rtl_is_special_data(hw, skb, false); | |
634 | ||
635 | if (ieee80211_is_data(fc)) { | |
636 | rtlpriv->cfg->ops->led_control(hw, LED_CTL_RX); | |
637 | ||
638 | if (unicast) | |
639 | rtlpriv->link_info.num_rx_inperiod++; | |
640 | } | |
641 | ||
642 | /* for sw lps */ | |
643 | rtl_swlps_beacon(hw, (void *)skb->data, skb->len); | |
644 | rtl_recognize_peer(hw, (void *)skb->data, skb->len); | |
645 | if ((rtlpriv->mac80211.opmode == NL80211_IFTYPE_AP) && | |
646 | (rtlpriv->rtlhal.current_bandtype == BAND_ON_2_4G) && | |
647 | (ieee80211_is_beacon(fc) || ieee80211_is_probe_resp(fc))) | |
648 | return; | |
649 | ||
650 | if (unlikely(!rtl_action_proc(hw, skb, false))) | |
651 | return; | |
652 | ||
653 | uskb = dev_alloc_skb(skb->len + 128); | |
76a92be5 LF |
654 | if (!uskb) |
655 | return; /* exit if allocation failed */ | |
fd854772 MM |
656 | memcpy(IEEE80211_SKB_RXCB(uskb), &rx_status, sizeof(rx_status)); |
657 | pdata = (u8 *)skb_put(uskb, skb->len); | |
658 | memcpy(pdata, skb->data, skb->len); | |
659 | ||
660 | ieee80211_rx_irqsafe(hw, uskb); | |
661 | } | |
662 | ||
0c817338 LF |
663 | static void _rtl_pci_rx_interrupt(struct ieee80211_hw *hw) |
664 | { | |
665 | struct rtl_priv *rtlpriv = rtl_priv(hw); | |
666 | struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw)); | |
667 | int rx_queue_idx = RTL_PCI_RX_MPDU_QUEUE; | |
668 | ||
669 | struct ieee80211_rx_status rx_status = { 0 }; | |
670 | unsigned int count = rtlpci->rxringcount; | |
671 | u8 own; | |
672 | u8 tmp_one; | |
673 | u32 bufferaddress; | |
0c817338 LF |
674 | |
675 | struct rtl_stats stats = { | |
676 | .signal = 0, | |
677 | .noise = -98, | |
678 | .rate = 0, | |
679 | }; | |
34ddb207 | 680 | int index = rtlpci->rx_ring[rx_queue_idx].idx; |
0c817338 LF |
681 | |
682 | /*RX NORMAL PKT */ | |
683 | while (count--) { | |
684 | /*rx descriptor */ | |
685 | struct rtl_rx_desc *pdesc = &rtlpci->rx_ring[rx_queue_idx].desc[ | |
34ddb207 | 686 | index]; |
0c817338 LF |
687 | /*rx pkt */ |
688 | struct sk_buff *skb = rtlpci->rx_ring[rx_queue_idx].rx_buf[ | |
34ddb207 | 689 | index]; |
2c333366 | 690 | struct sk_buff *new_skb = NULL; |
0c817338 LF |
691 | |
692 | own = (u8) rtlpriv->cfg->ops->get_desc((u8 *) pdesc, | |
693 | false, HW_DESC_OWN); | |
694 | ||
2c333366 MM |
695 | /*wait data to be filled by hardware */ |
696 | if (own) | |
34ddb207 | 697 | break; |
6633d649 | 698 | |
2c333366 MM |
699 | rtlpriv->cfg->ops->query_rx_desc(hw, &stats, |
700 | &rx_status, | |
701 | (u8 *) pdesc, skb); | |
702 | ||
8db8ddf1 MM |
703 | if (stats.crc || stats.hwerror) |
704 | goto done; | |
705 | ||
2c333366 MM |
706 | new_skb = dev_alloc_skb(rtlpci->rxbuffersize); |
707 | if (unlikely(!new_skb)) { | |
f30d7507 JP |
708 | RT_TRACE(rtlpriv, (COMP_INTR | COMP_RECV), DBG_DMESG, |
709 | "can't alloc skb for rx\n"); | |
2c333366 MM |
710 | goto done; |
711 | } | |
712 | ||
713 | pci_unmap_single(rtlpci->pdev, | |
714 | *((dma_addr_t *) skb->cb), | |
715 | rtlpci->rxbuffersize, | |
716 | PCI_DMA_FROMDEVICE); | |
717 | ||
718 | skb_put(skb, rtlpriv->cfg->ops->get_desc((u8 *) pdesc, false, | |
719 | HW_DESC_RXPKT_LEN)); | |
720 | skb_reserve(skb, stats.rx_drvinfo_size + stats.rx_bufshift); | |
721 | ||
722 | /* | |
723 | * NOTICE This can not be use for mac80211, | |
724 | * this is done in mac80211 code, | |
725 | * if you done here sec DHCP will fail | |
726 | * skb_trim(skb, skb->len - 4); | |
727 | */ | |
728 | ||
fd854772 | 729 | _rtl_receive_one(hw, skb, rx_status); |
0c817338 | 730 | |
2c333366 MM |
731 | if (((rtlpriv->link_info.num_rx_inperiod + |
732 | rtlpriv->link_info.num_tx_inperiod) > 8) || | |
733 | (rtlpriv->link_info.num_rx_inperiod > 2)) { | |
41affd52 | 734 | schedule_work(&rtlpriv->works.lps_leave_work); |
2c333366 | 735 | } |
0c817338 | 736 | |
14058add | 737 | dev_kfree_skb_any(skb); |
2c333366 | 738 | skb = new_skb; |
0c817338 | 739 | |
2c333366 MM |
740 | rtlpci->rx_ring[rx_queue_idx].rx_buf[index] = skb; |
741 | *((dma_addr_t *) skb->cb) = | |
0c817338 LF |
742 | pci_map_single(rtlpci->pdev, skb_tail_pointer(skb), |
743 | rtlpci->rxbuffersize, | |
744 | PCI_DMA_FROMDEVICE); | |
745 | ||
0c817338 | 746 | done: |
d3bb1429 | 747 | bufferaddress = (*((dma_addr_t *)skb->cb)); |
0c817338 LF |
748 | tmp_one = 1; |
749 | rtlpriv->cfg->ops->set_desc((u8 *) pdesc, false, | |
750 | HW_DESC_RXBUFF_ADDR, | |
751 | (u8 *)&bufferaddress); | |
0c817338 LF |
752 | rtlpriv->cfg->ops->set_desc((u8 *)pdesc, false, |
753 | HW_DESC_RXPKT_LEN, | |
754 | (u8 *)&rtlpci->rxbuffersize); | |
755 | ||
34ddb207 | 756 | if (index == rtlpci->rxringcount - 1) |
0c817338 LF |
757 | rtlpriv->cfg->ops->set_desc((u8 *)pdesc, false, |
758 | HW_DESC_RXERO, | |
759 | (u8 *)&tmp_one); | |
760 | ||
febc9fe5 MM |
761 | rtlpriv->cfg->ops->set_desc((u8 *)pdesc, false, HW_DESC_RXOWN, |
762 | (u8 *)&tmp_one); | |
763 | ||
34ddb207 | 764 | index = (index + 1) % rtlpci->rxringcount; |
0c817338 LF |
765 | } |
766 | ||
34ddb207 | 767 | rtlpci->rx_ring[rx_queue_idx].idx = index; |
0c817338 LF |
768 | } |
769 | ||
0c817338 LF |
770 | static irqreturn_t _rtl_pci_interrupt(int irq, void *dev_id) |
771 | { | |
772 | struct ieee80211_hw *hw = dev_id; | |
773 | struct rtl_priv *rtlpriv = rtl_priv(hw); | |
c7cfe38e | 774 | struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw)); |
0c817338 LF |
775 | unsigned long flags; |
776 | u32 inta = 0; | |
777 | u32 intb = 0; | |
de2e56ce | 778 | irqreturn_t ret = IRQ_HANDLED; |
0c817338 | 779 | |
0c817338 LF |
780 | spin_lock_irqsave(&rtlpriv->locks.irq_th_lock, flags); |
781 | ||
782 | /*read ISR: 4/8bytes */ | |
783 | rtlpriv->cfg->ops->interrupt_recognized(hw, &inta, &intb); | |
784 | ||
785 | /*Shared IRQ or HW disappared */ | |
de2e56ce LF |
786 | if (!inta || inta == 0xffff) { |
787 | ret = IRQ_NONE; | |
0c817338 | 788 | goto done; |
de2e56ce | 789 | } |
0c817338 LF |
790 | |
791 | /*<1> beacon related */ | |
792 | if (inta & rtlpriv->cfg->maps[RTL_IMR_TBDOK]) { | |
793 | RT_TRACE(rtlpriv, COMP_INTR, DBG_TRACE, | |
f30d7507 | 794 | "beacon ok interrupt!\n"); |
0c817338 LF |
795 | } |
796 | ||
797 | if (unlikely(inta & rtlpriv->cfg->maps[RTL_IMR_TBDER])) { | |
798 | RT_TRACE(rtlpriv, COMP_INTR, DBG_TRACE, | |
f30d7507 | 799 | "beacon err interrupt!\n"); |
0c817338 LF |
800 | } |
801 | ||
802 | if (inta & rtlpriv->cfg->maps[RTL_IMR_BDOK]) { | |
f30d7507 | 803 | RT_TRACE(rtlpriv, COMP_INTR, DBG_TRACE, "beacon interrupt!\n"); |
0c817338 LF |
804 | } |
805 | ||
806 | if (inta & rtlpriv->cfg->maps[RTL_IMR_BcnInt]) { | |
807 | RT_TRACE(rtlpriv, COMP_INTR, DBG_TRACE, | |
f30d7507 | 808 | "prepare beacon for interrupt!\n"); |
0c817338 LF |
809 | tasklet_schedule(&rtlpriv->works.irq_prepare_bcn_tasklet); |
810 | } | |
811 | ||
812 | /*<3> Tx related */ | |
813 | if (unlikely(inta & rtlpriv->cfg->maps[RTL_IMR_TXFOVW])) | |
f30d7507 | 814 | RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING, "IMR_TXFOVW!\n"); |
0c817338 LF |
815 | |
816 | if (inta & rtlpriv->cfg->maps[RTL_IMR_MGNTDOK]) { | |
817 | RT_TRACE(rtlpriv, COMP_INTR, DBG_TRACE, | |
f30d7507 | 818 | "Manage ok interrupt!\n"); |
0c817338 LF |
819 | _rtl_pci_tx_isr(hw, MGNT_QUEUE); |
820 | } | |
821 | ||
822 | if (inta & rtlpriv->cfg->maps[RTL_IMR_HIGHDOK]) { | |
823 | RT_TRACE(rtlpriv, COMP_INTR, DBG_TRACE, | |
f30d7507 | 824 | "HIGH_QUEUE ok interrupt!\n"); |
0c817338 LF |
825 | _rtl_pci_tx_isr(hw, HIGH_QUEUE); |
826 | } | |
827 | ||
828 | if (inta & rtlpriv->cfg->maps[RTL_IMR_BKDOK]) { | |
829 | rtlpriv->link_info.num_tx_inperiod++; | |
830 | ||
831 | RT_TRACE(rtlpriv, COMP_INTR, DBG_TRACE, | |
f30d7507 | 832 | "BK Tx OK interrupt!\n"); |
0c817338 LF |
833 | _rtl_pci_tx_isr(hw, BK_QUEUE); |
834 | } | |
835 | ||
836 | if (inta & rtlpriv->cfg->maps[RTL_IMR_BEDOK]) { | |
837 | rtlpriv->link_info.num_tx_inperiod++; | |
838 | ||
839 | RT_TRACE(rtlpriv, COMP_INTR, DBG_TRACE, | |
f30d7507 | 840 | "BE TX OK interrupt!\n"); |
0c817338 LF |
841 | _rtl_pci_tx_isr(hw, BE_QUEUE); |
842 | } | |
843 | ||
844 | if (inta & rtlpriv->cfg->maps[RTL_IMR_VIDOK]) { | |
845 | rtlpriv->link_info.num_tx_inperiod++; | |
846 | ||
847 | RT_TRACE(rtlpriv, COMP_INTR, DBG_TRACE, | |
f30d7507 | 848 | "VI TX OK interrupt!\n"); |
0c817338 LF |
849 | _rtl_pci_tx_isr(hw, VI_QUEUE); |
850 | } | |
851 | ||
852 | if (inta & rtlpriv->cfg->maps[RTL_IMR_VODOK]) { | |
853 | rtlpriv->link_info.num_tx_inperiod++; | |
854 | ||
855 | RT_TRACE(rtlpriv, COMP_INTR, DBG_TRACE, | |
f30d7507 | 856 | "Vo TX OK interrupt!\n"); |
0c817338 LF |
857 | _rtl_pci_tx_isr(hw, VO_QUEUE); |
858 | } | |
859 | ||
c7cfe38e C |
860 | if (rtlhal->hw_type == HARDWARE_TYPE_RTL8192SE) { |
861 | if (inta & rtlpriv->cfg->maps[RTL_IMR_COMDOK]) { | |
862 | rtlpriv->link_info.num_tx_inperiod++; | |
863 | ||
864 | RT_TRACE(rtlpriv, COMP_INTR, DBG_TRACE, | |
f30d7507 | 865 | "CMD TX OK interrupt!\n"); |
c7cfe38e C |
866 | _rtl_pci_tx_isr(hw, TXCMD_QUEUE); |
867 | } | |
868 | } | |
869 | ||
0c817338 LF |
870 | /*<2> Rx related */ |
871 | if (inta & rtlpriv->cfg->maps[RTL_IMR_ROK]) { | |
f30d7507 | 872 | RT_TRACE(rtlpriv, COMP_INTR, DBG_TRACE, "Rx ok interrupt!\n"); |
c7cfe38e | 873 | _rtl_pci_rx_interrupt(hw); |
0c817338 LF |
874 | } |
875 | ||
876 | if (unlikely(inta & rtlpriv->cfg->maps[RTL_IMR_RDU])) { | |
877 | RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING, | |
f30d7507 | 878 | "rx descriptor unavailable!\n"); |
c7cfe38e | 879 | _rtl_pci_rx_interrupt(hw); |
0c817338 LF |
880 | } |
881 | ||
882 | if (unlikely(inta & rtlpriv->cfg->maps[RTL_IMR_RXFOVW])) { | |
f30d7507 | 883 | RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING, "rx overflow !\n"); |
c7cfe38e | 884 | _rtl_pci_rx_interrupt(hw); |
0c817338 LF |
885 | } |
886 | ||
c7cfe38e C |
887 | if (rtlpriv->rtlhal.earlymode_enable) |
888 | tasklet_schedule(&rtlpriv->works.irq_tasklet); | |
889 | ||
0c817338 LF |
890 | done: |
891 | spin_unlock_irqrestore(&rtlpriv->locks.irq_th_lock, flags); | |
de2e56ce | 892 | return ret; |
0c817338 LF |
893 | } |
894 | ||
895 | static void _rtl_pci_irq_tasklet(struct ieee80211_hw *hw) | |
896 | { | |
c7cfe38e | 897 | _rtl_pci_tx_chk_waitq(hw); |
0c817338 LF |
898 | } |
899 | ||
900 | static void _rtl_pci_prepare_bcn_tasklet(struct ieee80211_hw *hw) | |
901 | { | |
902 | struct rtl_priv *rtlpriv = rtl_priv(hw); | |
903 | struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw)); | |
904 | struct rtl_mac *mac = rtl_mac(rtl_priv(hw)); | |
c7cfe38e | 905 | struct rtl8192_tx_ring *ring = NULL; |
0c817338 LF |
906 | struct ieee80211_hdr *hdr = NULL; |
907 | struct ieee80211_tx_info *info = NULL; | |
908 | struct sk_buff *pskb = NULL; | |
909 | struct rtl_tx_desc *pdesc = NULL; | |
c7cfe38e | 910 | struct rtl_tcb_desc tcb_desc; |
0c817338 LF |
911 | u8 temp_one = 1; |
912 | ||
c7cfe38e | 913 | memset(&tcb_desc, 0, sizeof(struct rtl_tcb_desc)); |
0c817338 LF |
914 | ring = &rtlpci->tx_ring[BEACON_QUEUE]; |
915 | pskb = __skb_dequeue(&ring->queue); | |
a75e2ad7 LF |
916 | if (pskb) { |
917 | struct rtl_tx_desc *entry = &ring->desc[ring->idx]; | |
918 | pci_unmap_single(rtlpci->pdev, rtlpriv->cfg->ops->get_desc( | |
919 | (u8 *) entry, true, HW_DESC_TXBUFF_ADDR), | |
920 | pskb->len, PCI_DMA_TODEVICE); | |
0c817338 | 921 | kfree_skb(pskb); |
a75e2ad7 | 922 | } |
0c817338 LF |
923 | |
924 | /*NB: the beacon data buffer must be 32-bit aligned. */ | |
925 | pskb = ieee80211_beacon_get(hw, mac->vif); | |
926 | if (pskb == NULL) | |
927 | return; | |
c7cfe38e | 928 | hdr = rtl_get_hdr(pskb); |
0c817338 | 929 | info = IEEE80211_SKB_CB(pskb); |
0c817338 LF |
930 | pdesc = &ring->desc[0]; |
931 | rtlpriv->cfg->ops->fill_tx_desc(hw, hdr, (u8 *) pdesc, | |
c7cfe38e | 932 | info, pskb, BEACON_QUEUE, &tcb_desc); |
0c817338 LF |
933 | |
934 | __skb_queue_tail(&ring->queue, pskb); | |
935 | ||
936 | rtlpriv->cfg->ops->set_desc((u8 *) pdesc, true, HW_DESC_OWN, | |
937 | (u8 *)&temp_one); | |
938 | ||
939 | return; | |
940 | } | |
941 | ||
41affd52 SG |
942 | static void rtl_lps_leave_work_callback(struct work_struct *work) |
943 | { | |
944 | struct rtl_works *rtlworks = | |
945 | container_of(work, struct rtl_works, lps_leave_work); | |
946 | struct ieee80211_hw *hw = rtlworks->hw; | |
947 | ||
948 | rtl_lps_leave(hw); | |
949 | } | |
950 | ||
0c817338 LF |
951 | static void _rtl_pci_init_trx_var(struct ieee80211_hw *hw) |
952 | { | |
953 | struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw)); | |
954 | u8 i; | |
955 | ||
956 | for (i = 0; i < RTL_PCI_MAX_TX_QUEUE_COUNT; i++) | |
957 | rtlpci->txringcount[i] = RT_TXDESC_NUM; | |
958 | ||
959 | /* | |
960 | *we just alloc 2 desc for beacon queue, | |
961 | *because we just need first desc in hw beacon. | |
962 | */ | |
963 | rtlpci->txringcount[BEACON_QUEUE] = 2; | |
964 | ||
965 | /* | |
966 | *BE queue need more descriptor for performance | |
967 | *consideration or, No more tx desc will happen, | |
968 | *and may cause mac80211 mem leakage. | |
969 | */ | |
970 | rtlpci->txringcount[BE_QUEUE] = RT_TXDESC_NUM_BE_QUEUE; | |
971 | ||
972 | rtlpci->rxbuffersize = 9100; /*2048/1024; */ | |
973 | rtlpci->rxringcount = RTL_PCI_MAX_RX_COUNT; /*64; */ | |
974 | } | |
975 | ||
976 | static void _rtl_pci_init_struct(struct ieee80211_hw *hw, | |
977 | struct pci_dev *pdev) | |
978 | { | |
979 | struct rtl_priv *rtlpriv = rtl_priv(hw); | |
980 | struct rtl_mac *mac = rtl_mac(rtl_priv(hw)); | |
981 | struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw)); | |
982 | struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw)); | |
0c817338 LF |
983 | |
984 | rtlpci->up_first_time = true; | |
985 | rtlpci->being_init_adapter = false; | |
986 | ||
987 | rtlhal->hw = hw; | |
988 | rtlpci->pdev = pdev; | |
989 | ||
0c817338 LF |
990 | /*Tx/Rx related var */ |
991 | _rtl_pci_init_trx_var(hw); | |
992 | ||
c7cfe38e | 993 | /*IBSS*/ mac->beacon_interval = 100; |
0c817338 | 994 | |
c7cfe38e C |
995 | /*AMPDU*/ |
996 | mac->min_space_cfg = 0; | |
0c817338 LF |
997 | mac->max_mss_density = 0; |
998 | /*set sane AMPDU defaults */ | |
999 | mac->current_ampdu_density = 7; | |
1000 | mac->current_ampdu_factor = 3; | |
1001 | ||
c7cfe38e C |
1002 | /*QOS*/ |
1003 | rtlpci->acm_method = eAcmWay2_SW; | |
0c817338 LF |
1004 | |
1005 | /*task */ | |
1006 | tasklet_init(&rtlpriv->works.irq_tasklet, | |
1007 | (void (*)(unsigned long))_rtl_pci_irq_tasklet, | |
1008 | (unsigned long)hw); | |
1009 | tasklet_init(&rtlpriv->works.irq_prepare_bcn_tasklet, | |
1010 | (void (*)(unsigned long))_rtl_pci_prepare_bcn_tasklet, | |
1011 | (unsigned long)hw); | |
41affd52 | 1012 | INIT_WORK(&rtlpriv->works.lps_leave_work, rtl_lps_leave_work_callback); |
0c817338 LF |
1013 | } |
1014 | ||
1015 | static int _rtl_pci_init_tx_ring(struct ieee80211_hw *hw, | |
1016 | unsigned int prio, unsigned int entries) | |
1017 | { | |
1018 | struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw)); | |
1019 | struct rtl_priv *rtlpriv = rtl_priv(hw); | |
1020 | struct rtl_tx_desc *ring; | |
1021 | dma_addr_t dma; | |
1022 | u32 nextdescaddress; | |
1023 | int i; | |
1024 | ||
1025 | ring = pci_alloc_consistent(rtlpci->pdev, | |
1026 | sizeof(*ring) * entries, &dma); | |
1027 | ||
1028 | if (!ring || (unsigned long)ring & 0xFF) { | |
1029 | RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG, | |
f30d7507 | 1030 | "Cannot allocate TX ring (prio = %d)\n", prio); |
0c817338 LF |
1031 | return -ENOMEM; |
1032 | } | |
1033 | ||
1034 | memset(ring, 0, sizeof(*ring) * entries); | |
1035 | rtlpci->tx_ring[prio].desc = ring; | |
1036 | rtlpci->tx_ring[prio].dma = dma; | |
1037 | rtlpci->tx_ring[prio].idx = 0; | |
1038 | rtlpci->tx_ring[prio].entries = entries; | |
1039 | skb_queue_head_init(&rtlpci->tx_ring[prio].queue); | |
1040 | ||
f30d7507 JP |
1041 | RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, "queue:%d, ring_addr:%p\n", |
1042 | prio, ring); | |
0c817338 LF |
1043 | |
1044 | for (i = 0; i < entries; i++) { | |
d3bb1429 | 1045 | nextdescaddress = (u32) dma + |
982d96bb | 1046 | ((i + 1) % entries) * |
d3bb1429 | 1047 | sizeof(*ring); |
0c817338 LF |
1048 | |
1049 | rtlpriv->cfg->ops->set_desc((u8 *)&(ring[i]), | |
1050 | true, HW_DESC_TX_NEXTDESC_ADDR, | |
1051 | (u8 *)&nextdescaddress); | |
1052 | } | |
1053 | ||
1054 | return 0; | |
1055 | } | |
1056 | ||
1057 | static int _rtl_pci_init_rx_ring(struct ieee80211_hw *hw) | |
1058 | { | |
1059 | struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw)); | |
1060 | struct rtl_priv *rtlpriv = rtl_priv(hw); | |
1061 | struct rtl_rx_desc *entry = NULL; | |
1062 | int i, rx_queue_idx; | |
1063 | u8 tmp_one = 1; | |
1064 | ||
1065 | /* | |
1066 | *rx_queue_idx 0:RX_MPDU_QUEUE | |
1067 | *rx_queue_idx 1:RX_CMD_QUEUE | |
1068 | */ | |
1069 | for (rx_queue_idx = 0; rx_queue_idx < RTL_PCI_MAX_RX_QUEUE; | |
1070 | rx_queue_idx++) { | |
1071 | rtlpci->rx_ring[rx_queue_idx].desc = | |
1072 | pci_alloc_consistent(rtlpci->pdev, | |
1073 | sizeof(*rtlpci->rx_ring[rx_queue_idx]. | |
1074 | desc) * rtlpci->rxringcount, | |
1075 | &rtlpci->rx_ring[rx_queue_idx].dma); | |
1076 | ||
1077 | if (!rtlpci->rx_ring[rx_queue_idx].desc || | |
1078 | (unsigned long)rtlpci->rx_ring[rx_queue_idx].desc & 0xFF) { | |
1079 | RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG, | |
f30d7507 | 1080 | "Cannot allocate RX ring\n"); |
0c817338 LF |
1081 | return -ENOMEM; |
1082 | } | |
1083 | ||
1084 | memset(rtlpci->rx_ring[rx_queue_idx].desc, 0, | |
1085 | sizeof(*rtlpci->rx_ring[rx_queue_idx].desc) * | |
1086 | rtlpci->rxringcount); | |
1087 | ||
1088 | rtlpci->rx_ring[rx_queue_idx].idx = 0; | |
1089 | ||
0019a2c9 LF |
1090 | /* If amsdu_8k is disabled, set buffersize to 4096. This |
1091 | * change will reduce memory fragmentation. | |
1092 | */ | |
1093 | if (rtlpci->rxbuffersize > 4096 && | |
1094 | rtlpriv->rtlhal.disable_amsdu_8k) | |
1095 | rtlpci->rxbuffersize = 4096; | |
1096 | ||
0c817338 LF |
1097 | for (i = 0; i < rtlpci->rxringcount; i++) { |
1098 | struct sk_buff *skb = | |
1099 | dev_alloc_skb(rtlpci->rxbuffersize); | |
1100 | u32 bufferaddress; | |
0c817338 LF |
1101 | if (!skb) |
1102 | return 0; | |
f11bbfd8 | 1103 | kmemleak_not_leak(skb); |
bdc4bf65 | 1104 | entry = &rtlpci->rx_ring[rx_queue_idx].desc[i]; |
0c817338 LF |
1105 | |
1106 | /*skb->dev = dev; */ | |
1107 | ||
1108 | rtlpci->rx_ring[rx_queue_idx].rx_buf[i] = skb; | |
1109 | ||
1110 | /* | |
1111 | *just set skb->cb to mapping addr | |
1112 | *for pci_unmap_single use | |
1113 | */ | |
1114 | *((dma_addr_t *) skb->cb) = | |
1115 | pci_map_single(rtlpci->pdev, skb_tail_pointer(skb), | |
1116 | rtlpci->rxbuffersize, | |
1117 | PCI_DMA_FROMDEVICE); | |
1118 | ||
d3bb1429 | 1119 | bufferaddress = (*((dma_addr_t *)skb->cb)); |
0c817338 LF |
1120 | rtlpriv->cfg->ops->set_desc((u8 *)entry, false, |
1121 | HW_DESC_RXBUFF_ADDR, | |
1122 | (u8 *)&bufferaddress); | |
1123 | rtlpriv->cfg->ops->set_desc((u8 *)entry, false, | |
1124 | HW_DESC_RXPKT_LEN, | |
1125 | (u8 *)&rtlpci-> | |
1126 | rxbuffersize); | |
1127 | rtlpriv->cfg->ops->set_desc((u8 *) entry, false, | |
1128 | HW_DESC_RXOWN, | |
1129 | (u8 *)&tmp_one); | |
1130 | } | |
1131 | ||
1132 | rtlpriv->cfg->ops->set_desc((u8 *) entry, false, | |
1133 | HW_DESC_RXERO, (u8 *)&tmp_one); | |
1134 | } | |
1135 | return 0; | |
1136 | } | |
1137 | ||
1138 | static void _rtl_pci_free_tx_ring(struct ieee80211_hw *hw, | |
1139 | unsigned int prio) | |
1140 | { | |
1141 | struct rtl_priv *rtlpriv = rtl_priv(hw); | |
1142 | struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw)); | |
1143 | struct rtl8192_tx_ring *ring = &rtlpci->tx_ring[prio]; | |
1144 | ||
1145 | while (skb_queue_len(&ring->queue)) { | |
1146 | struct rtl_tx_desc *entry = &ring->desc[ring->idx]; | |
1147 | struct sk_buff *skb = __skb_dequeue(&ring->queue); | |
1148 | ||
1149 | pci_unmap_single(rtlpci->pdev, | |
d3bb1429 | 1150 | rtlpriv->cfg-> |
0c817338 | 1151 | ops->get_desc((u8 *) entry, true, |
d3bb1429 | 1152 | HW_DESC_TXBUFF_ADDR), |
0c817338 LF |
1153 | skb->len, PCI_DMA_TODEVICE); |
1154 | kfree_skb(skb); | |
1155 | ring->idx = (ring->idx + 1) % ring->entries; | |
1156 | } | |
1157 | ||
7f66c2f9 SG |
1158 | if (ring->desc) { |
1159 | pci_free_consistent(rtlpci->pdev, | |
1160 | sizeof(*ring->desc) * ring->entries, | |
1161 | ring->desc, ring->dma); | |
1162 | ring->desc = NULL; | |
1163 | } | |
0c817338 LF |
1164 | } |
1165 | ||
1166 | static void _rtl_pci_free_rx_ring(struct rtl_pci *rtlpci) | |
1167 | { | |
1168 | int i, rx_queue_idx; | |
1169 | ||
1170 | /*rx_queue_idx 0:RX_MPDU_QUEUE */ | |
1171 | /*rx_queue_idx 1:RX_CMD_QUEUE */ | |
1172 | for (rx_queue_idx = 0; rx_queue_idx < RTL_PCI_MAX_RX_QUEUE; | |
1173 | rx_queue_idx++) { | |
1174 | for (i = 0; i < rtlpci->rxringcount; i++) { | |
1175 | struct sk_buff *skb = | |
1176 | rtlpci->rx_ring[rx_queue_idx].rx_buf[i]; | |
1177 | if (!skb) | |
1178 | continue; | |
1179 | ||
1180 | pci_unmap_single(rtlpci->pdev, | |
1181 | *((dma_addr_t *) skb->cb), | |
1182 | rtlpci->rxbuffersize, | |
1183 | PCI_DMA_FROMDEVICE); | |
1184 | kfree_skb(skb); | |
1185 | } | |
1186 | ||
7f66c2f9 SG |
1187 | if (rtlpci->rx_ring[rx_queue_idx].desc) { |
1188 | pci_free_consistent(rtlpci->pdev, | |
0c817338 LF |
1189 | sizeof(*rtlpci->rx_ring[rx_queue_idx]. |
1190 | desc) * rtlpci->rxringcount, | |
1191 | rtlpci->rx_ring[rx_queue_idx].desc, | |
1192 | rtlpci->rx_ring[rx_queue_idx].dma); | |
7f66c2f9 SG |
1193 | rtlpci->rx_ring[rx_queue_idx].desc = NULL; |
1194 | } | |
0c817338 LF |
1195 | } |
1196 | } | |
1197 | ||
1198 | static int _rtl_pci_init_trx_ring(struct ieee80211_hw *hw) | |
1199 | { | |
1200 | struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw)); | |
1201 | int ret; | |
1202 | int i; | |
1203 | ||
1204 | ret = _rtl_pci_init_rx_ring(hw); | |
1205 | if (ret) | |
1206 | return ret; | |
1207 | ||
1208 | for (i = 0; i < RTL_PCI_MAX_TX_QUEUE_COUNT; i++) { | |
1209 | ret = _rtl_pci_init_tx_ring(hw, i, | |
1210 | rtlpci->txringcount[i]); | |
1211 | if (ret) | |
1212 | goto err_free_rings; | |
1213 | } | |
1214 | ||
1215 | return 0; | |
1216 | ||
1217 | err_free_rings: | |
1218 | _rtl_pci_free_rx_ring(rtlpci); | |
1219 | ||
1220 | for (i = 0; i < RTL_PCI_MAX_TX_QUEUE_COUNT; i++) | |
1221 | if (rtlpci->tx_ring[i].desc) | |
1222 | _rtl_pci_free_tx_ring(hw, i); | |
1223 | ||
1224 | return 1; | |
1225 | } | |
1226 | ||
1227 | static int _rtl_pci_deinit_trx_ring(struct ieee80211_hw *hw) | |
1228 | { | |
1229 | struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw)); | |
1230 | u32 i; | |
1231 | ||
1232 | /*free rx rings */ | |
1233 | _rtl_pci_free_rx_ring(rtlpci); | |
1234 | ||
1235 | /*free tx rings */ | |
1236 | for (i = 0; i < RTL_PCI_MAX_TX_QUEUE_COUNT; i++) | |
1237 | _rtl_pci_free_tx_ring(hw, i); | |
1238 | ||
1239 | return 0; | |
1240 | } | |
1241 | ||
1242 | int rtl_pci_reset_trx_ring(struct ieee80211_hw *hw) | |
1243 | { | |
1244 | struct rtl_priv *rtlpriv = rtl_priv(hw); | |
1245 | struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw)); | |
1246 | int i, rx_queue_idx; | |
1247 | unsigned long flags; | |
1248 | u8 tmp_one = 1; | |
1249 | ||
1250 | /*rx_queue_idx 0:RX_MPDU_QUEUE */ | |
1251 | /*rx_queue_idx 1:RX_CMD_QUEUE */ | |
1252 | for (rx_queue_idx = 0; rx_queue_idx < RTL_PCI_MAX_RX_QUEUE; | |
1253 | rx_queue_idx++) { | |
1254 | /* | |
1255 | *force the rx_ring[RX_MPDU_QUEUE/ | |
1256 | *RX_CMD_QUEUE].idx to the first one | |
1257 | */ | |
1258 | if (rtlpci->rx_ring[rx_queue_idx].desc) { | |
1259 | struct rtl_rx_desc *entry = NULL; | |
1260 | ||
1261 | for (i = 0; i < rtlpci->rxringcount; i++) { | |
1262 | entry = &rtlpci->rx_ring[rx_queue_idx].desc[i]; | |
1263 | rtlpriv->cfg->ops->set_desc((u8 *) entry, | |
1264 | false, | |
1265 | HW_DESC_RXOWN, | |
1266 | (u8 *)&tmp_one); | |
1267 | } | |
1268 | rtlpci->rx_ring[rx_queue_idx].idx = 0; | |
1269 | } | |
1270 | } | |
1271 | ||
1272 | /* | |
1273 | *after reset, release previous pending packet, | |
1274 | *and force the tx idx to the first one | |
1275 | */ | |
0c817338 LF |
1276 | for (i = 0; i < RTL_PCI_MAX_TX_QUEUE_COUNT; i++) { |
1277 | if (rtlpci->tx_ring[i].desc) { | |
1278 | struct rtl8192_tx_ring *ring = &rtlpci->tx_ring[i]; | |
1279 | ||
1280 | while (skb_queue_len(&ring->queue)) { | |
5a2766ab LF |
1281 | struct rtl_tx_desc *entry; |
1282 | struct sk_buff *skb; | |
0c817338 | 1283 | |
5a2766ab LF |
1284 | spin_lock_irqsave(&rtlpriv->locks.irq_th_lock, |
1285 | flags); | |
1286 | entry = &ring->desc[ring->idx]; | |
1287 | skb = __skb_dequeue(&ring->queue); | |
0c817338 | 1288 | pci_unmap_single(rtlpci->pdev, |
d3bb1429 | 1289 | rtlpriv->cfg->ops-> |
0c817338 LF |
1290 | get_desc((u8 *) |
1291 | entry, | |
1292 | true, | |
d3bb1429 | 1293 | HW_DESC_TXBUFF_ADDR), |
0c817338 | 1294 | skb->len, PCI_DMA_TODEVICE); |
0c817338 | 1295 | ring->idx = (ring->idx + 1) % ring->entries; |
5a2766ab LF |
1296 | spin_unlock_irqrestore(&rtlpriv->locks.irq_th_lock, |
1297 | flags); | |
1298 | kfree_skb(skb); | |
0c817338 LF |
1299 | } |
1300 | ring->idx = 0; | |
1301 | } | |
1302 | } | |
1303 | ||
0c817338 LF |
1304 | return 0; |
1305 | } | |
1306 | ||
c7cfe38e C |
1307 | static bool rtl_pci_tx_chk_waitq_insert(struct ieee80211_hw *hw, |
1308 | struct sk_buff *skb) | |
0c817338 | 1309 | { |
c7cfe38e C |
1310 | struct rtl_priv *rtlpriv = rtl_priv(hw); |
1311 | struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb); | |
1312 | struct ieee80211_sta *sta = info->control.sta; | |
1313 | struct rtl_sta_info *sta_entry = NULL; | |
1314 | u8 tid = rtl_get_tid(skb); | |
1315 | ||
1316 | if (!sta) | |
1317 | return false; | |
1318 | sta_entry = (struct rtl_sta_info *)sta->drv_priv; | |
1319 | ||
1320 | if (!rtlpriv->rtlhal.earlymode_enable) | |
1321 | return false; | |
1322 | if (sta_entry->tids[tid].agg.agg_state != RTL_AGG_OPERATIONAL) | |
1323 | return false; | |
1324 | if (_rtl_mac_to_hwqueue(hw, skb) > VO_QUEUE) | |
1325 | return false; | |
1326 | if (tid > 7) | |
1327 | return false; | |
1328 | ||
1329 | /* maybe every tid should be checked */ | |
1330 | if (!rtlpriv->link_info.higher_busytxtraffic[tid]) | |
1331 | return false; | |
1332 | ||
1333 | spin_lock_bh(&rtlpriv->locks.waitq_lock); | |
1334 | skb_queue_tail(&rtlpriv->mac80211.skb_waitq[tid], skb); | |
1335 | spin_unlock_bh(&rtlpriv->locks.waitq_lock); | |
0c817338 | 1336 | |
c7cfe38e | 1337 | return true; |
0c817338 LF |
1338 | } |
1339 | ||
d3bb1429 | 1340 | static int rtl_pci_tx(struct ieee80211_hw *hw, struct sk_buff *skb, |
c7cfe38e | 1341 | struct rtl_tcb_desc *ptcb_desc) |
0c817338 LF |
1342 | { |
1343 | struct rtl_priv *rtlpriv = rtl_priv(hw); | |
c7cfe38e | 1344 | struct rtl_sta_info *sta_entry = NULL; |
0c817338 | 1345 | struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb); |
c7cfe38e | 1346 | struct ieee80211_sta *sta = info->control.sta; |
0c817338 LF |
1347 | struct rtl8192_tx_ring *ring; |
1348 | struct rtl_tx_desc *pdesc; | |
1349 | u8 idx; | |
c7cfe38e | 1350 | u8 hw_queue = _rtl_mac_to_hwqueue(hw, skb); |
0c817338 | 1351 | unsigned long flags; |
c7cfe38e C |
1352 | struct ieee80211_hdr *hdr = rtl_get_hdr(skb); |
1353 | __le16 fc = rtl_get_fc(skb); | |
0c817338 LF |
1354 | u8 *pda_addr = hdr->addr1; |
1355 | struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw)); | |
1356 | /*ssn */ | |
0c817338 LF |
1357 | u8 tid = 0; |
1358 | u16 seq_number = 0; | |
1359 | u8 own; | |
1360 | u8 temp_one = 1; | |
1361 | ||
c7cfe38e | 1362 | if (ieee80211_is_auth(fc)) { |
f30d7507 | 1363 | RT_TRACE(rtlpriv, COMP_SEND, DBG_DMESG, "MAC80211_LINKING\n"); |
c7cfe38e C |
1364 | rtl_ips_nic_on(hw); |
1365 | } | |
1366 | ||
1367 | if (rtlpriv->psc.sw_ps_enabled) { | |
1368 | if (ieee80211_is_data(fc) && !ieee80211_is_nullfunc(fc) && | |
1369 | !ieee80211_has_pm(fc)) | |
1370 | hdr->frame_control |= cpu_to_le16(IEEE80211_FCTL_PM); | |
1371 | } | |
0c817338 | 1372 | |
c7cfe38e | 1373 | rtl_action_proc(hw, skb, true); |
0c817338 LF |
1374 | |
1375 | if (is_multicast_ether_addr(pda_addr)) | |
1376 | rtlpriv->stats.txbytesmulticast += skb->len; | |
1377 | else if (is_broadcast_ether_addr(pda_addr)) | |
1378 | rtlpriv->stats.txbytesbroadcast += skb->len; | |
1379 | else | |
1380 | rtlpriv->stats.txbytesunicast += skb->len; | |
1381 | ||
1382 | spin_lock_irqsave(&rtlpriv->locks.irq_th_lock, flags); | |
0c817338 LF |
1383 | ring = &rtlpci->tx_ring[hw_queue]; |
1384 | if (hw_queue != BEACON_QUEUE) | |
1385 | idx = (ring->idx + skb_queue_len(&ring->queue)) % | |
1386 | ring->entries; | |
1387 | else | |
1388 | idx = 0; | |
1389 | ||
1390 | pdesc = &ring->desc[idx]; | |
1391 | own = (u8) rtlpriv->cfg->ops->get_desc((u8 *) pdesc, | |
1392 | true, HW_DESC_OWN); | |
1393 | ||
1394 | if ((own == 1) && (hw_queue != BEACON_QUEUE)) { | |
1395 | RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING, | |
f30d7507 JP |
1396 | "No more TX desc@%d, ring->idx = %d, idx = %d, skb_queue_len = 0x%d\n", |
1397 | hw_queue, ring->idx, idx, | |
1398 | skb_queue_len(&ring->queue)); | |
0c817338 LF |
1399 | |
1400 | spin_unlock_irqrestore(&rtlpriv->locks.irq_th_lock, flags); | |
1401 | return skb->len; | |
1402 | } | |
1403 | ||
0c817338 | 1404 | if (ieee80211_is_data_qos(fc)) { |
c7cfe38e C |
1405 | tid = rtl_get_tid(skb); |
1406 | if (sta) { | |
1407 | sta_entry = (struct rtl_sta_info *)sta->drv_priv; | |
1408 | seq_number = (le16_to_cpu(hdr->seq_ctrl) & | |
1409 | IEEE80211_SCTL_SEQ) >> 4; | |
1410 | seq_number += 1; | |
1411 | ||
1412 | if (!ieee80211_has_morefrags(hdr->frame_control)) | |
1413 | sta_entry->tids[tid].seq_number = seq_number; | |
1414 | } | |
0c817338 LF |
1415 | } |
1416 | ||
1417 | if (ieee80211_is_data(fc)) | |
1418 | rtlpriv->cfg->ops->led_control(hw, LED_CTL_TX); | |
1419 | ||
c7cfe38e C |
1420 | rtlpriv->cfg->ops->fill_tx_desc(hw, hdr, (u8 *)pdesc, |
1421 | info, skb, hw_queue, ptcb_desc); | |
0c817338 LF |
1422 | |
1423 | __skb_queue_tail(&ring->queue, skb); | |
1424 | ||
c7cfe38e | 1425 | rtlpriv->cfg->ops->set_desc((u8 *)pdesc, true, |
0c817338 LF |
1426 | HW_DESC_OWN, (u8 *)&temp_one); |
1427 | ||
0c817338 LF |
1428 | |
1429 | if ((ring->entries - skb_queue_len(&ring->queue)) < 2 && | |
1430 | hw_queue != BEACON_QUEUE) { | |
1431 | ||
1432 | RT_TRACE(rtlpriv, COMP_ERR, DBG_LOUD, | |
f30d7507 JP |
1433 | "less desc left, stop skb_queue@%d, ring->idx = %d, idx = %d, skb_queue_len = 0x%d\n", |
1434 | hw_queue, ring->idx, idx, | |
1435 | skb_queue_len(&ring->queue)); | |
0c817338 LF |
1436 | |
1437 | ieee80211_stop_queue(hw, skb_get_queue_mapping(skb)); | |
1438 | } | |
1439 | ||
1440 | spin_unlock_irqrestore(&rtlpriv->locks.irq_th_lock, flags); | |
1441 | ||
1442 | rtlpriv->cfg->ops->tx_polling(hw, hw_queue); | |
1443 | ||
1444 | return 0; | |
1445 | } | |
1446 | ||
c7cfe38e C |
1447 | static void rtl_pci_flush(struct ieee80211_hw *hw, bool drop) |
1448 | { | |
1449 | struct rtl_priv *rtlpriv = rtl_priv(hw); | |
1450 | struct rtl_pci_priv *pcipriv = rtl_pcipriv(hw); | |
1451 | struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw)); | |
1452 | u16 i = 0; | |
1453 | int queue_id; | |
1454 | struct rtl8192_tx_ring *ring; | |
1455 | ||
1456 | for (queue_id = RTL_PCI_MAX_TX_QUEUE_COUNT - 1; queue_id >= 0;) { | |
1457 | u32 queue_len; | |
1458 | ring = &pcipriv->dev.tx_ring[queue_id]; | |
1459 | queue_len = skb_queue_len(&ring->queue); | |
1460 | if (queue_len == 0 || queue_id == BEACON_QUEUE || | |
1461 | queue_id == TXCMD_QUEUE) { | |
1462 | queue_id--; | |
1463 | continue; | |
1464 | } else { | |
1465 | msleep(20); | |
1466 | i++; | |
1467 | } | |
1468 | ||
1469 | /* we just wait 1s for all queues */ | |
1470 | if (rtlpriv->psc.rfpwr_state == ERFOFF || | |
1471 | is_hal_stop(rtlhal) || i >= 200) | |
1472 | return; | |
1473 | } | |
1474 | } | |
1475 | ||
d3bb1429 | 1476 | static void rtl_pci_deinit(struct ieee80211_hw *hw) |
0c817338 LF |
1477 | { |
1478 | struct rtl_priv *rtlpriv = rtl_priv(hw); | |
1479 | struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw)); | |
1480 | ||
1481 | _rtl_pci_deinit_trx_ring(hw); | |
1482 | ||
1483 | synchronize_irq(rtlpci->pdev->irq); | |
1484 | tasklet_kill(&rtlpriv->works.irq_tasklet); | |
41affd52 | 1485 | cancel_work_sync(&rtlpriv->works.lps_leave_work); |
0c817338 LF |
1486 | |
1487 | flush_workqueue(rtlpriv->works.rtl_wq); | |
1488 | destroy_workqueue(rtlpriv->works.rtl_wq); | |
1489 | ||
1490 | } | |
1491 | ||
d3bb1429 | 1492 | static int rtl_pci_init(struct ieee80211_hw *hw, struct pci_dev *pdev) |
0c817338 LF |
1493 | { |
1494 | struct rtl_priv *rtlpriv = rtl_priv(hw); | |
1495 | int err; | |
1496 | ||
1497 | _rtl_pci_init_struct(hw, pdev); | |
1498 | ||
1499 | err = _rtl_pci_init_trx_ring(hw); | |
1500 | if (err) { | |
1501 | RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG, | |
f30d7507 | 1502 | "tx ring initialization failed\n"); |
12325280 | 1503 | return err; |
0c817338 LF |
1504 | } |
1505 | ||
12325280 | 1506 | return 0; |
0c817338 LF |
1507 | } |
1508 | ||
d3bb1429 | 1509 | static int rtl_pci_start(struct ieee80211_hw *hw) |
0c817338 LF |
1510 | { |
1511 | struct rtl_priv *rtlpriv = rtl_priv(hw); | |
1512 | struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw)); | |
1513 | struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw)); | |
1514 | struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw)); | |
1515 | ||
1516 | int err; | |
1517 | ||
1518 | rtl_pci_reset_trx_ring(hw); | |
1519 | ||
1520 | rtlpci->driver_is_goingto_unload = false; | |
1521 | err = rtlpriv->cfg->ops->hw_init(hw); | |
1522 | if (err) { | |
1523 | RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG, | |
f30d7507 | 1524 | "Failed to config hardware!\n"); |
0c817338 LF |
1525 | return err; |
1526 | } | |
1527 | ||
1528 | rtlpriv->cfg->ops->enable_interrupt(hw); | |
f30d7507 | 1529 | RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, "enable_interrupt OK\n"); |
0c817338 LF |
1530 | |
1531 | rtl_init_rx_config(hw); | |
1532 | ||
fb914ebf | 1533 | /*should be after adapter start and interrupt enable. */ |
0c817338 LF |
1534 | set_hal_start(rtlhal); |
1535 | ||
1536 | RT_CLEAR_PS_LEVEL(ppsc, RT_RF_OFF_LEVL_HALT_NIC); | |
1537 | ||
1538 | rtlpci->up_first_time = false; | |
1539 | ||
f30d7507 | 1540 | RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG, "OK\n"); |
0c817338 LF |
1541 | return 0; |
1542 | } | |
1543 | ||
d3bb1429 | 1544 | static void rtl_pci_stop(struct ieee80211_hw *hw) |
0c817338 LF |
1545 | { |
1546 | struct rtl_priv *rtlpriv = rtl_priv(hw); | |
1547 | struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw)); | |
1548 | struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw)); | |
1549 | struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw)); | |
1550 | unsigned long flags; | |
1551 | u8 RFInProgressTimeOut = 0; | |
1552 | ||
1553 | /* | |
fb914ebf | 1554 | *should be before disable interrupt&adapter |
0c817338 LF |
1555 | *and will do it immediately. |
1556 | */ | |
1557 | set_hal_stop(rtlhal); | |
1558 | ||
1559 | rtlpriv->cfg->ops->disable_interrupt(hw); | |
41affd52 | 1560 | cancel_work_sync(&rtlpriv->works.lps_leave_work); |
0c817338 LF |
1561 | |
1562 | spin_lock_irqsave(&rtlpriv->locks.rf_ps_lock, flags); | |
1563 | while (ppsc->rfchange_inprogress) { | |
1564 | spin_unlock_irqrestore(&rtlpriv->locks.rf_ps_lock, flags); | |
1565 | if (RFInProgressTimeOut > 100) { | |
1566 | spin_lock_irqsave(&rtlpriv->locks.rf_ps_lock, flags); | |
1567 | break; | |
1568 | } | |
1569 | mdelay(1); | |
1570 | RFInProgressTimeOut++; | |
1571 | spin_lock_irqsave(&rtlpriv->locks.rf_ps_lock, flags); | |
1572 | } | |
1573 | ppsc->rfchange_inprogress = true; | |
1574 | spin_unlock_irqrestore(&rtlpriv->locks.rf_ps_lock, flags); | |
1575 | ||
1576 | rtlpci->driver_is_goingto_unload = true; | |
1577 | rtlpriv->cfg->ops->hw_disable(hw); | |
b0302aba LF |
1578 | /* some things are not needed if firmware not available */ |
1579 | if (!rtlpriv->max_fw_size) | |
1580 | return; | |
0c817338 LF |
1581 | rtlpriv->cfg->ops->led_control(hw, LED_CTL_POWER_OFF); |
1582 | ||
1583 | spin_lock_irqsave(&rtlpriv->locks.rf_ps_lock, flags); | |
1584 | ppsc->rfchange_inprogress = false; | |
1585 | spin_unlock_irqrestore(&rtlpriv->locks.rf_ps_lock, flags); | |
1586 | ||
1587 | rtl_pci_enable_aspm(hw); | |
1588 | } | |
1589 | ||
1590 | static bool _rtl_pci_find_adapter(struct pci_dev *pdev, | |
1591 | struct ieee80211_hw *hw) | |
1592 | { | |
1593 | struct rtl_priv *rtlpriv = rtl_priv(hw); | |
1594 | struct rtl_pci_priv *pcipriv = rtl_pcipriv(hw); | |
1595 | struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw)); | |
1596 | struct pci_dev *bridge_pdev = pdev->bus->self; | |
1597 | u16 venderid; | |
1598 | u16 deviceid; | |
c7cfe38e | 1599 | u8 revisionid; |
0c817338 LF |
1600 | u16 irqline; |
1601 | u8 tmp; | |
1602 | ||
fc7707a4 | 1603 | pcipriv->ndis_adapter.pcibridge_vendor = PCI_BRIDGE_VENDOR_UNKNOWN; |
0c817338 LF |
1604 | venderid = pdev->vendor; |
1605 | deviceid = pdev->device; | |
c7cfe38e | 1606 | pci_read_config_byte(pdev, 0x8, &revisionid); |
0c817338 LF |
1607 | pci_read_config_word(pdev, 0x3C, &irqline); |
1608 | ||
fa7ccfb1 LF |
1609 | /* PCI ID 0x10ec:0x8192 occurs for both RTL8192E, which uses |
1610 | * r8192e_pci, and RTL8192SE, which uses this driver. If the | |
1611 | * revision ID is RTL_PCI_REVISION_ID_8192PCIE (0x01), then | |
1612 | * the correct driver is r8192e_pci, thus this routine should | |
1613 | * return false. | |
1614 | */ | |
1615 | if (deviceid == RTL_PCI_8192SE_DID && | |
1616 | revisionid == RTL_PCI_REVISION_ID_8192PCIE) | |
1617 | return false; | |
1618 | ||
0c817338 LF |
1619 | if (deviceid == RTL_PCI_8192_DID || |
1620 | deviceid == RTL_PCI_0044_DID || | |
1621 | deviceid == RTL_PCI_0047_DID || | |
1622 | deviceid == RTL_PCI_8192SE_DID || | |
1623 | deviceid == RTL_PCI_8174_DID || | |
1624 | deviceid == RTL_PCI_8173_DID || | |
1625 | deviceid == RTL_PCI_8172_DID || | |
1626 | deviceid == RTL_PCI_8171_DID) { | |
c7cfe38e | 1627 | switch (revisionid) { |
0c817338 LF |
1628 | case RTL_PCI_REVISION_ID_8192PCIE: |
1629 | RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG, | |
f30d7507 JP |
1630 | "8192 PCI-E is found - vid/did=%x/%x\n", |
1631 | venderid, deviceid); | |
0c817338 LF |
1632 | rtlhal->hw_type = HARDWARE_TYPE_RTL8192E; |
1633 | break; | |
1634 | case RTL_PCI_REVISION_ID_8192SE: | |
1635 | RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG, | |
f30d7507 JP |
1636 | "8192SE is found - vid/did=%x/%x\n", |
1637 | venderid, deviceid); | |
0c817338 LF |
1638 | rtlhal->hw_type = HARDWARE_TYPE_RTL8192SE; |
1639 | break; | |
1640 | default: | |
1641 | RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING, | |
f30d7507 JP |
1642 | "Err: Unknown device - vid/did=%x/%x\n", |
1643 | venderid, deviceid); | |
0c817338 LF |
1644 | rtlhal->hw_type = HARDWARE_TYPE_RTL8192SE; |
1645 | break; | |
1646 | ||
1647 | } | |
1648 | } else if (deviceid == RTL_PCI_8192CET_DID || | |
1649 | deviceid == RTL_PCI_8192CE_DID || | |
1650 | deviceid == RTL_PCI_8191CE_DID || | |
1651 | deviceid == RTL_PCI_8188CE_DID) { | |
1652 | rtlhal->hw_type = HARDWARE_TYPE_RTL8192CE; | |
1653 | RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG, | |
f30d7507 JP |
1654 | "8192C PCI-E is found - vid/did=%x/%x\n", |
1655 | venderid, deviceid); | |
c7cfe38e C |
1656 | } else if (deviceid == RTL_PCI_8192DE_DID || |
1657 | deviceid == RTL_PCI_8192DE_DID2) { | |
1658 | rtlhal->hw_type = HARDWARE_TYPE_RTL8192DE; | |
1659 | RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG, | |
f30d7507 JP |
1660 | "8192D PCI-E is found - vid/did=%x/%x\n", |
1661 | venderid, deviceid); | |
0c817338 LF |
1662 | } else { |
1663 | RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING, | |
f30d7507 JP |
1664 | "Err: Unknown device - vid/did=%x/%x\n", |
1665 | venderid, deviceid); | |
0c817338 LF |
1666 | |
1667 | rtlhal->hw_type = RTL_DEFAULT_HARDWARE_TYPE; | |
1668 | } | |
1669 | ||
c7cfe38e C |
1670 | if (rtlhal->hw_type == HARDWARE_TYPE_RTL8192DE) { |
1671 | if (revisionid == 0 || revisionid == 1) { | |
1672 | if (revisionid == 0) { | |
f30d7507 JP |
1673 | RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, |
1674 | "Find 92DE MAC0\n"); | |
c7cfe38e C |
1675 | rtlhal->interfaceindex = 0; |
1676 | } else if (revisionid == 1) { | |
1677 | RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, | |
f30d7507 | 1678 | "Find 92DE MAC1\n"); |
c7cfe38e C |
1679 | rtlhal->interfaceindex = 1; |
1680 | } | |
1681 | } else { | |
1682 | RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, | |
f30d7507 JP |
1683 | "Unknown device - VendorID/DeviceID=%x/%x, Revision=%x\n", |
1684 | venderid, deviceid, revisionid); | |
c7cfe38e C |
1685 | rtlhal->interfaceindex = 0; |
1686 | } | |
1687 | } | |
0c817338 LF |
1688 | /*find bus info */ |
1689 | pcipriv->ndis_adapter.busnumber = pdev->bus->number; | |
1690 | pcipriv->ndis_adapter.devnumber = PCI_SLOT(pdev->devfn); | |
1691 | pcipriv->ndis_adapter.funcnumber = PCI_FUNC(pdev->devfn); | |
1692 | ||
b6b67df3 LF |
1693 | if (bridge_pdev) { |
1694 | /*find bridge info if available */ | |
1695 | pcipriv->ndis_adapter.pcibridge_vendorid = bridge_pdev->vendor; | |
1696 | for (tmp = 0; tmp < PCI_BRIDGE_VENDOR_MAX; tmp++) { | |
1697 | if (bridge_pdev->vendor == pcibridge_vendors[tmp]) { | |
1698 | pcipriv->ndis_adapter.pcibridge_vendor = tmp; | |
1699 | RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG, | |
f30d7507 JP |
1700 | "Pci Bridge Vendor is found index: %d\n", |
1701 | tmp); | |
b6b67df3 LF |
1702 | break; |
1703 | } | |
0c817338 LF |
1704 | } |
1705 | } | |
1706 | ||
1707 | if (pcipriv->ndis_adapter.pcibridge_vendor != | |
1708 | PCI_BRIDGE_VENDOR_UNKNOWN) { | |
1709 | pcipriv->ndis_adapter.pcibridge_busnum = | |
1710 | bridge_pdev->bus->number; | |
1711 | pcipriv->ndis_adapter.pcibridge_devnum = | |
1712 | PCI_SLOT(bridge_pdev->devfn); | |
1713 | pcipriv->ndis_adapter.pcibridge_funcnum = | |
1714 | PCI_FUNC(bridge_pdev->devfn); | |
c7cfe38e C |
1715 | pcipriv->ndis_adapter.pcibridge_pciehdr_offset = |
1716 | pci_pcie_cap(bridge_pdev); | |
0c817338 LF |
1717 | pcipriv->ndis_adapter.num4bytes = |
1718 | (pcipriv->ndis_adapter.pcibridge_pciehdr_offset + 0x10) / 4; | |
1719 | ||
1720 | rtl_pci_get_linkcontrol_field(hw); | |
1721 | ||
1722 | if (pcipriv->ndis_adapter.pcibridge_vendor == | |
1723 | PCI_BRIDGE_VENDOR_AMD) { | |
1724 | pcipriv->ndis_adapter.amd_l1_patch = | |
1725 | rtl_pci_get_amd_l1_patch(hw); | |
1726 | } | |
1727 | } | |
1728 | ||
1729 | RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG, | |
f30d7507 JP |
1730 | "pcidev busnumber:devnumber:funcnumber:vendor:link_ctl %d:%d:%d:%x:%x\n", |
1731 | pcipriv->ndis_adapter.busnumber, | |
1732 | pcipriv->ndis_adapter.devnumber, | |
1733 | pcipriv->ndis_adapter.funcnumber, | |
1734 | pdev->vendor, pcipriv->ndis_adapter.linkctrl_reg); | |
0c817338 LF |
1735 | |
1736 | RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG, | |
f30d7507 JP |
1737 | "pci_bridge busnumber:devnumber:funcnumber:vendor:pcie_cap:link_ctl_reg:amd %d:%d:%d:%x:%x:%x:%x\n", |
1738 | pcipriv->ndis_adapter.pcibridge_busnum, | |
1739 | pcipriv->ndis_adapter.pcibridge_devnum, | |
1740 | pcipriv->ndis_adapter.pcibridge_funcnum, | |
1741 | pcibridge_vendors[pcipriv->ndis_adapter.pcibridge_vendor], | |
1742 | pcipriv->ndis_adapter.pcibridge_pciehdr_offset, | |
1743 | pcipriv->ndis_adapter.pcibridge_linkctrlreg, | |
1744 | pcipriv->ndis_adapter.amd_l1_patch); | |
0c817338 LF |
1745 | |
1746 | rtl_pci_parse_configuration(pdev, hw); | |
1747 | ||
1748 | return true; | |
1749 | } | |
1750 | ||
1751 | int __devinit rtl_pci_probe(struct pci_dev *pdev, | |
1752 | const struct pci_device_id *id) | |
1753 | { | |
1754 | struct ieee80211_hw *hw = NULL; | |
1755 | ||
1756 | struct rtl_priv *rtlpriv = NULL; | |
1757 | struct rtl_pci_priv *pcipriv = NULL; | |
1758 | struct rtl_pci *rtlpci; | |
1759 | unsigned long pmem_start, pmem_len, pmem_flags; | |
1760 | int err; | |
1761 | ||
1762 | err = pci_enable_device(pdev); | |
1763 | if (err) { | |
9d833ed7 JP |
1764 | RT_ASSERT(false, "%s : Cannot enable new PCI device\n", |
1765 | pci_name(pdev)); | |
0c817338 LF |
1766 | return err; |
1767 | } | |
1768 | ||
1769 | if (!pci_set_dma_mask(pdev, DMA_BIT_MASK(32))) { | |
1770 | if (pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32))) { | |
9d833ed7 JP |
1771 | RT_ASSERT(false, |
1772 | "Unable to obtain 32bit DMA for consistent allocations\n"); | |
3d86b930 TG |
1773 | err = -ENOMEM; |
1774 | goto fail1; | |
0c817338 LF |
1775 | } |
1776 | } | |
1777 | ||
1778 | pci_set_master(pdev); | |
1779 | ||
1780 | hw = ieee80211_alloc_hw(sizeof(struct rtl_pci_priv) + | |
1781 | sizeof(struct rtl_priv), &rtl_ops); | |
1782 | if (!hw) { | |
1783 | RT_ASSERT(false, | |
9d833ed7 | 1784 | "%s : ieee80211 alloc failed\n", pci_name(pdev)); |
0c817338 LF |
1785 | err = -ENOMEM; |
1786 | goto fail1; | |
1787 | } | |
1788 | ||
1789 | SET_IEEE80211_DEV(hw, &pdev->dev); | |
1790 | pci_set_drvdata(pdev, hw); | |
1791 | ||
1792 | rtlpriv = hw->priv; | |
1793 | pcipriv = (void *)rtlpriv->priv; | |
1794 | pcipriv->dev.pdev = pdev; | |
b0302aba | 1795 | init_completion(&rtlpriv->firmware_loading_complete); |
0c817338 | 1796 | |
c7cfe38e C |
1797 | /* init cfg & intf_ops */ |
1798 | rtlpriv->rtlhal.interface = INTF_PCI; | |
1799 | rtlpriv->cfg = (struct rtl_hal_cfg *)(id->driver_data); | |
1800 | rtlpriv->intf_ops = &rtl_pci_ops; | |
1801 | ||
0c817338 LF |
1802 | /* |
1803 | *init dbgp flags before all | |
1804 | *other functions, because we will | |
1805 | *use it in other funtions like | |
1806 | *RT_TRACE/RT_PRINT/RTL_PRINT_DATA | |
1807 | *you can not use these macro | |
1808 | *before this | |
1809 | */ | |
1810 | rtl_dbgp_flag_init(hw); | |
1811 | ||
1812 | /* MEM map */ | |
1813 | err = pci_request_regions(pdev, KBUILD_MODNAME); | |
1814 | if (err) { | |
9d833ed7 | 1815 | RT_ASSERT(false, "Can't obtain PCI resources\n"); |
3d86b930 | 1816 | goto fail1; |
0c817338 LF |
1817 | } |
1818 | ||
c7cfe38e C |
1819 | pmem_start = pci_resource_start(pdev, rtlpriv->cfg->bar_id); |
1820 | pmem_len = pci_resource_len(pdev, rtlpriv->cfg->bar_id); | |
1821 | pmem_flags = pci_resource_flags(pdev, rtlpriv->cfg->bar_id); | |
0c817338 LF |
1822 | |
1823 | /*shared mem start */ | |
1824 | rtlpriv->io.pci_mem_start = | |
c7cfe38e C |
1825 | (unsigned long)pci_iomap(pdev, |
1826 | rtlpriv->cfg->bar_id, pmem_len); | |
0c817338 | 1827 | if (rtlpriv->io.pci_mem_start == 0) { |
9d833ed7 | 1828 | RT_ASSERT(false, "Can't map PCI mem\n"); |
3d86b930 | 1829 | err = -ENOMEM; |
0c817338 LF |
1830 | goto fail2; |
1831 | } | |
1832 | ||
1833 | RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG, | |
f30d7507 JP |
1834 | "mem mapped space: start: 0x%08lx len:%08lx flags:%08lx, after map:0x%08lx\n", |
1835 | pmem_start, pmem_len, pmem_flags, | |
1836 | rtlpriv->io.pci_mem_start); | |
0c817338 LF |
1837 | |
1838 | /* Disable Clk Request */ | |
1839 | pci_write_config_byte(pdev, 0x81, 0); | |
1840 | /* leave D3 mode */ | |
1841 | pci_write_config_byte(pdev, 0x44, 0); | |
1842 | pci_write_config_byte(pdev, 0x04, 0x06); | |
1843 | pci_write_config_byte(pdev, 0x04, 0x07); | |
1844 | ||
0c817338 | 1845 | /* find adapter */ |
3d86b930 TG |
1846 | if (!_rtl_pci_find_adapter(pdev, hw)) { |
1847 | err = -ENODEV; | |
fa7ccfb1 | 1848 | goto fail3; |
3d86b930 | 1849 | } |
0c817338 LF |
1850 | |
1851 | /* Init IO handler */ | |
1852 | _rtl_pci_io_handler_init(&pdev->dev, hw); | |
1853 | ||
1854 | /*like read eeprom and so on */ | |
1855 | rtlpriv->cfg->ops->read_eeprom_info(hw); | |
1856 | ||
0c817338 LF |
1857 | /*aspm */ |
1858 | rtl_pci_init_aspm(hw); | |
1859 | ||
1860 | /* Init mac80211 sw */ | |
1861 | err = rtl_init_core(hw); | |
1862 | if (err) { | |
1863 | RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG, | |
f30d7507 | 1864 | "Can't allocate sw for mac80211\n"); |
0c817338 LF |
1865 | goto fail3; |
1866 | } | |
1867 | ||
1868 | /* Init PCI sw */ | |
12325280 | 1869 | err = rtl_pci_init(hw, pdev); |
0c817338 | 1870 | if (err) { |
f30d7507 | 1871 | RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG, "Failed to init PCI\n"); |
0c817338 LF |
1872 | goto fail3; |
1873 | } | |
1874 | ||
574e02ab LF |
1875 | if (rtlpriv->cfg->ops->init_sw_vars(hw)) { |
1876 | RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG, "Can't init_sw_vars\n"); | |
1877 | err = -ENODEV; | |
1878 | goto fail3; | |
1879 | } | |
1880 | ||
1881 | rtlpriv->cfg->ops->init_sw_leds(hw); | |
1882 | ||
0c817338 LF |
1883 | err = sysfs_create_group(&pdev->dev.kobj, &rtl_attribute_group); |
1884 | if (err) { | |
1885 | RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG, | |
f30d7507 | 1886 | "failed to create sysfs device attributes\n"); |
0c817338 LF |
1887 | goto fail3; |
1888 | } | |
1889 | ||
0c817338 LF |
1890 | rtlpci = rtl_pcidev(pcipriv); |
1891 | err = request_irq(rtlpci->pdev->irq, &_rtl_pci_interrupt, | |
1892 | IRQF_SHARED, KBUILD_MODNAME, hw); | |
1893 | if (err) { | |
1894 | RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG, | |
f30d7507 JP |
1895 | "%s: failed to register IRQ handler\n", |
1896 | wiphy_name(hw->wiphy)); | |
0c817338 | 1897 | goto fail3; |
0c817338 | 1898 | } |
b0302aba | 1899 | rtlpci->irq_alloc = 1; |
0c817338 | 1900 | |
0c817338 LF |
1901 | return 0; |
1902 | ||
1903 | fail3: | |
0c817338 LF |
1904 | rtl_deinit_core(hw); |
1905 | _rtl_pci_io_handler_release(hw); | |
0c817338 LF |
1906 | |
1907 | if (rtlpriv->io.pci_mem_start != 0) | |
62e63975 | 1908 | pci_iounmap(pdev, (void __iomem *)rtlpriv->io.pci_mem_start); |
0c817338 LF |
1909 | |
1910 | fail2: | |
1911 | pci_release_regions(pdev); | |
b0302aba | 1912 | complete(&rtlpriv->firmware_loading_complete); |
0c817338 LF |
1913 | |
1914 | fail1: | |
3d86b930 TG |
1915 | if (hw) |
1916 | ieee80211_free_hw(hw); | |
1917 | pci_set_drvdata(pdev, NULL); | |
0c817338 LF |
1918 | pci_disable_device(pdev); |
1919 | ||
3d86b930 | 1920 | return err; |
0c817338 LF |
1921 | |
1922 | } | |
1923 | EXPORT_SYMBOL(rtl_pci_probe); | |
1924 | ||
1925 | void rtl_pci_disconnect(struct pci_dev *pdev) | |
1926 | { | |
1927 | struct ieee80211_hw *hw = pci_get_drvdata(pdev); | |
1928 | struct rtl_pci_priv *pcipriv = rtl_pcipriv(hw); | |
1929 | struct rtl_priv *rtlpriv = rtl_priv(hw); | |
1930 | struct rtl_pci *rtlpci = rtl_pcidev(pcipriv); | |
1931 | struct rtl_mac *rtlmac = rtl_mac(rtlpriv); | |
1932 | ||
b0302aba LF |
1933 | /* just in case driver is removed before firmware callback */ |
1934 | wait_for_completion(&rtlpriv->firmware_loading_complete); | |
0c817338 LF |
1935 | clear_bit(RTL_STATUS_INTERFACE_START, &rtlpriv->status); |
1936 | ||
1937 | sysfs_remove_group(&pdev->dev.kobj, &rtl_attribute_group); | |
1938 | ||
1939 | /*ieee80211_unregister_hw will call ops_stop */ | |
1940 | if (rtlmac->mac80211_registered == 1) { | |
1941 | ieee80211_unregister_hw(hw); | |
1942 | rtlmac->mac80211_registered = 0; | |
1943 | } else { | |
1944 | rtl_deinit_deferred_work(hw); | |
1945 | rtlpriv->intf_ops->adapter_stop(hw); | |
1946 | } | |
44eb65cf | 1947 | rtlpriv->cfg->ops->disable_interrupt(hw); |
0c817338 LF |
1948 | |
1949 | /*deinit rfkill */ | |
1950 | rtl_deinit_rfkill(hw); | |
1951 | ||
1952 | rtl_pci_deinit(hw); | |
1953 | rtl_deinit_core(hw); | |
0c817338 LF |
1954 | _rtl_pci_io_handler_release(hw); |
1955 | rtlpriv->cfg->ops->deinit_sw_vars(hw); | |
1956 | ||
1957 | if (rtlpci->irq_alloc) { | |
1958 | free_irq(rtlpci->pdev->irq, hw); | |
1959 | rtlpci->irq_alloc = 0; | |
1960 | } | |
1961 | ||
1962 | if (rtlpriv->io.pci_mem_start != 0) { | |
62e63975 | 1963 | pci_iounmap(pdev, (void __iomem *)rtlpriv->io.pci_mem_start); |
0c817338 LF |
1964 | pci_release_regions(pdev); |
1965 | } | |
1966 | ||
1967 | pci_disable_device(pdev); | |
c7cfe38e C |
1968 | |
1969 | rtl_pci_disable_aspm(hw); | |
1970 | ||
0c817338 LF |
1971 | pci_set_drvdata(pdev, NULL); |
1972 | ||
1973 | ieee80211_free_hw(hw); | |
1974 | } | |
1975 | EXPORT_SYMBOL(rtl_pci_disconnect); | |
1976 | ||
1977 | /*************************************** | |
1978 | kernel pci power state define: | |
1979 | PCI_D0 ((pci_power_t __force) 0) | |
1980 | PCI_D1 ((pci_power_t __force) 1) | |
1981 | PCI_D2 ((pci_power_t __force) 2) | |
1982 | PCI_D3hot ((pci_power_t __force) 3) | |
1983 | PCI_D3cold ((pci_power_t __force) 4) | |
1984 | PCI_UNKNOWN ((pci_power_t __force) 5) | |
1985 | ||
1986 | This function is called when system | |
1987 | goes into suspend state mac80211 will | |
1988 | call rtl_mac_stop() from the mac80211 | |
1989 | suspend function first, So there is | |
1990 | no need to call hw_disable here. | |
1991 | ****************************************/ | |
603be388 | 1992 | int rtl_pci_suspend(struct device *dev) |
0c817338 | 1993 | { |
603be388 | 1994 | struct pci_dev *pdev = to_pci_dev(dev); |
c7cfe38e C |
1995 | struct ieee80211_hw *hw = pci_get_drvdata(pdev); |
1996 | struct rtl_priv *rtlpriv = rtl_priv(hw); | |
1997 | ||
1998 | rtlpriv->cfg->ops->hw_suspend(hw); | |
1999 | rtl_deinit_rfkill(hw); | |
2000 | ||
0c817338 LF |
2001 | return 0; |
2002 | } | |
2003 | EXPORT_SYMBOL(rtl_pci_suspend); | |
2004 | ||
603be388 | 2005 | int rtl_pci_resume(struct device *dev) |
0c817338 | 2006 | { |
603be388 | 2007 | struct pci_dev *pdev = to_pci_dev(dev); |
c7cfe38e C |
2008 | struct ieee80211_hw *hw = pci_get_drvdata(pdev); |
2009 | struct rtl_priv *rtlpriv = rtl_priv(hw); | |
0c817338 | 2010 | |
c7cfe38e C |
2011 | rtlpriv->cfg->ops->hw_resume(hw); |
2012 | rtl_init_rfkill(hw); | |
0c817338 LF |
2013 | return 0; |
2014 | } | |
2015 | EXPORT_SYMBOL(rtl_pci_resume); | |
2016 | ||
2017 | struct rtl_intf_ops rtl_pci_ops = { | |
c7cfe38e | 2018 | .read_efuse_byte = read_efuse_byte, |
0c817338 LF |
2019 | .adapter_start = rtl_pci_start, |
2020 | .adapter_stop = rtl_pci_stop, | |
2021 | .adapter_tx = rtl_pci_tx, | |
c7cfe38e | 2022 | .flush = rtl_pci_flush, |
0c817338 | 2023 | .reset_trx_ring = rtl_pci_reset_trx_ring, |
c7cfe38e | 2024 | .waitq_insert = rtl_pci_tx_chk_waitq_insert, |
0c817338 LF |
2025 | |
2026 | .disable_aspm = rtl_pci_disable_aspm, | |
2027 | .enable_aspm = rtl_pci_enable_aspm, | |
2028 | }; |