[deliverable/linux.git] / drivers / net / wireless / rtlwifi / pci.h

/******************************************************************************
 *
 * Copyright(c) 2009-2012  Realtek Corporation.
 *
 * This program is free software; you can redistribute it and/or modify it
 * under the terms of version 2 of the GNU General Public License as
 * published by the Free Software Foundation.
 *
 * This program is distributed in the hope that it will be useful, but WITHOUT
 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
 * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
 * more details.
 *
 * You should have received a copy of the GNU General Public License along with
 * this program; if not, write to the Free Software Foundation, Inc.,
 * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
 *
 * The full GNU General Public License is included in this distribution in the
 * file called LICENSE.
 *
 * Contact Information:
 * wlanfae <wlanfae@realtek.com>
 * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
 * Hsinchu 300, Taiwan.
 *
 * Larry Finger <Larry.Finger@lwfinger.net>
 *
 *****************************************************************************/

#ifndef __RTL_PCI_H__
#define __RTL_PCI_H__

#include <linux/pci.h>
/*
1: MSDU packet queue,
2: Rx Command Queue
*/
#define RTL_PCI_RX_MPDU_QUEUE			0
#define RTL_PCI_RX_CMD_QUEUE			1
#define RTL_PCI_MAX_RX_QUEUE			2

#define RTL_PCI_MAX_RX_COUNT			64
#define RTL_PCI_MAX_TX_QUEUE_COUNT		9

#define RT_TXDESC_NUM				128
#define RT_TXDESC_NUM_BE_QUEUE			256

#define BK_QUEUE				0
#define BE_QUEUE				1
#define VI_QUEUE				2
#define VO_QUEUE				3
#define BEACON_QUEUE				4
#define TXCMD_QUEUE				5
#define MGNT_QUEUE				6
#define HIGH_QUEUE				7
#define HCCA_QUEUE				8

#define RTL_PCI_DEVICE(vend, dev, cfg)  \
	.vendor = (vend), \
	.device = (dev), \
	.subvendor = PCI_ANY_ID, \
	.subdevice = PCI_ANY_ID,\
	.driver_data = (kernel_ulong_t)&(cfg)

#define PCI_MAX_BRIDGE_NUMBER			255
#define PCI_MAX_DEVICES				32
#define PCI_MAX_FUNCTION			8

#define PCI_CONF_ADDRESS	0x0CF8	/*PCI Configuration Space Address */
#define PCI_CONF_DATA		0x0CFC	/*PCI Configuration Space Data */

#define U1DONTCARE			0xFF
#define U2DONTCARE			0xFFFF
#define U4DONTCARE			0xFFFFFFFF

#define RTL_PCI_8192_DID	0x8192	/*8192 PCI-E */
#define RTL_PCI_8192SE_DID	0x8192	/*8192 SE */
#define RTL_PCI_8174_DID	0x8174	/*8192 SE */
#define RTL_PCI_8173_DID	0x8173	/*8191 SE Crab */
#define RTL_PCI_8172_DID	0x8172	/*8191 SE RE */
#define RTL_PCI_8171_DID	0x8171	/*8191 SE Unicron */
#define RTL_PCI_8723AE_DID	0x8723	/*8723AE */
#define RTL_PCI_0045_DID	0x0045	/*8190 PCI for Ceraga */
#define RTL_PCI_0046_DID	0x0046	/*8190 Cardbus for Ceraga */
#define RTL_PCI_0044_DID	0x0044	/*8192e PCIE for Ceraga */
#define RTL_PCI_0047_DID	0x0047	/*8192e Express Card for Ceraga */
#define RTL_PCI_700F_DID	0x700F
#define RTL_PCI_701F_DID	0x701F
#define RTL_PCI_DLINK_DID	0x3304
#define RTL_PCI_8192CET_DID	0x8191	/*8192ce */
#define RTL_PCI_8192CE_DID	0x8178	/*8192ce */
#define RTL_PCI_8191CE_DID	0x8177	/*8192ce */
#define RTL_PCI_8188CE_DID	0x8176	/*8192ce */
#define RTL_PCI_8192CU_DID	0x8191	/*8192ce */
#define RTL_PCI_8192DE_DID	0x8193	/*8192de */
#define RTL_PCI_8192DE_DID2	0x002B	/*92DE*/

/*8192 support 16 pages of IO registers*/
#define RTL_MEM_MAPPED_IO_RANGE_8190PCI		0x1000
#define RTL_MEM_MAPPED_IO_RANGE_8192PCIE	0x4000
#define RTL_MEM_MAPPED_IO_RANGE_8192SE		0x4000
#define RTL_MEM_MAPPED_IO_RANGE_8192CE		0x4000
#define RTL_MEM_MAPPED_IO_RANGE_8192DE		0x4000

#define RTL_PCI_REVISION_ID_8190PCI		0x00
#define RTL_PCI_REVISION_ID_8192PCIE		0x01
#define RTL_PCI_REVISION_ID_8192SE		0x10
#define RTL_PCI_REVISION_ID_8192CE		0x1
#define RTL_PCI_REVISION_ID_8192DE		0x0

#define RTL_DEFAULT_HARDWARE_TYPE	HARDWARE_TYPE_RTL8192CE

enum pci_bridge_vendor {
	PCI_BRIDGE_VENDOR_INTEL = 0x0,	/*0b'0000,0001 */
	PCI_BRIDGE_VENDOR_ATI,		/*0b'0000,0010*/
	PCI_BRIDGE_VENDOR_AMD,		/*0b'0000,0100*/
	PCI_BRIDGE_VENDOR_SIS,		/*0b'0000,1000*/
	PCI_BRIDGE_VENDOR_UNKNOWN,	/*0b'0100,0000*/
	PCI_BRIDGE_VENDOR_MAX,
};

struct rtl_pci_capabilities_header {
	u8 capability_id;
	u8 next;
};

struct rtl_rx_desc {
	u32 dword[8];
} __packed;

struct rtl_tx_desc {
	u32 dword[16];
} __packed;

struct rtl_tx_cmd_desc {
	u32 dword[16];
} __packed;

struct rtl8192_tx_ring {
	struct rtl_tx_desc *desc;
	dma_addr_t dma;
	unsigned int idx;
	unsigned int entries;
	struct sk_buff_head queue;
};

struct rtl8192_rx_ring {
	struct rtl_rx_desc *desc;
	dma_addr_t dma;
	unsigned int idx;
	struct sk_buff *rx_buf[RTL_PCI_MAX_RX_COUNT];
};

struct rtl_pci {
	struct pci_dev *pdev;
	bool irq_enabled;

	bool driver_is_goingto_unload;
	bool up_first_time;
	bool first_init;
	bool being_init_adapter;
	bool init_ready;

	/*Tx */
	struct rtl8192_tx_ring tx_ring[RTL_PCI_MAX_TX_QUEUE_COUNT];
	int txringcount[RTL_PCI_MAX_TX_QUEUE_COUNT];
	u32 transmit_config;

	/*Rx */
	struct rtl8192_rx_ring rx_ring[RTL_PCI_MAX_RX_QUEUE];
	int rxringcount;
	u16 rxbuffersize;
	u32 receive_config;

	/*irq */
	u8 irq_alloc;
	u32 irq_mask[2];

	/*Bcn control register setting */
	u32 reg_bcn_ctrl_val;

	 /*ASPM*/ u8 const_pci_aspm;
	u8 const_amdpci_aspm;
	u8 const_hwsw_rfoff_d3;
	u8 const_support_pciaspm;
	/*pci-e bridge */
	u8 const_hostpci_aspm_setting;
	/*pci-e device */
	u8 const_devicepci_aspm_setting;
	/*If it supports ASPM, Offset[560h] = 0x40,
	   otherwise Offset[560h] = 0x00. */
	bool support_aspm;
	bool support_backdoor;

	/*QOS & EDCA */
	enum acm_method acm_method;

	u16 shortretry_limit;
	u16 longretry_limit;
};

struct mp_adapter {
	u8 linkctrl_reg;

	u8 busnumber;
	u8 devnumber;
	u8 funcnumber;

	u8 pcibridge_busnum;
	u8 pcibridge_devnum;
	u8 pcibridge_funcnum;

	u8 pcibridge_vendor;
	u16 pcibridge_vendorid;
	u16 pcibridge_deviceid;

	u8 num4bytes;

	u8 pcibridge_pciehdr_offset;
	u8 pcibridge_linkctrlreg;

	bool amd_l1_patch;
};

struct rtl_pci_priv {
	struct rtl_pci dev;
	struct mp_adapter ndis_adapter;
	struct rtl_led_ctl ledctl;
	struct bt_coexist_info bt_coexist;
};

#define rtl_pcipriv(hw)		(((struct rtl_pci_priv *)(rtl_priv(hw))->priv))
#define rtl_pcidev(pcipriv)	(&((pcipriv)->dev))

int rtl_pci_reset_trx_ring(struct ieee80211_hw *hw);

extern struct rtl_intf_ops rtl_pci_ops;

int __devinit rtl_pci_probe(struct pci_dev *pdev,
			    const struct pci_device_id *id);
void rtl_pci_disconnect(struct pci_dev *pdev);
int rtl_pci_suspend(struct device *dev);
int rtl_pci_resume(struct device *dev);
static inline u8 pci_read8_sync(struct rtl_priv *rtlpriv, u32 addr)
{
	return readb((u8 __iomem *) rtlpriv->io.pci_mem_start + addr);
}

static inline u16 pci_read16_sync(struct rtl_priv *rtlpriv, u32 addr)
{
	return readw((u8 __iomem *) rtlpriv->io.pci_mem_start + addr);
}

static inline u32 pci_read32_sync(struct rtl_priv *rtlpriv, u32 addr)
{
	return readl((u8 __iomem *) rtlpriv->io.pci_mem_start + addr);
}

static inline void pci_write8_async(struct rtl_priv *rtlpriv, u32 addr, u8 val)
{
	writeb(val, (u8 __iomem *) rtlpriv->io.pci_mem_start + addr);
}

static inline void pci_write16_async(struct rtl_priv *rtlpriv,
				     u32 addr, u16 val)
{
	writew(val, (u8 __iomem *) rtlpriv->io.pci_mem_start + addr);
}

static inline void pci_write32_async(struct rtl_priv *rtlpriv,
				     u32 addr, u32 val)
{
	writel(val, (u8 __iomem *) rtlpriv->io.pci_mem_start + addr);
}

#endif
Commit	Line	Data
0c817338 LF	1	/******************************************************************************
0c817338 LF	2	*
a8d76066	3	* Copyright(c) 2009-2012 Realtek Corporation.
0c817338 LF	4	*
	5	* This program is free software; you can redistribute it and/or modify it
	6	* under the terms of version 2 of the GNU General Public License as
	7	* published by the Free Software Foundation.
	8	*
	9	* This program is distributed in the hope that it will be useful, but WITHOUT
	10	* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
	11	* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
	12	* more details.
	13	*
	14	* You should have received a copy of the GNU General Public License along with
	15	* this program; if not, write to the Free Software Foundation, Inc.,
	16	* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
	17	*
	18	* The full GNU General Public License is included in this distribution in the
	19	* file called LICENSE.
	20	*
	21	* Contact Information:
	22	* wlanfae <wlanfae@realtek.com>
	23	* Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
	24	* Hsinchu 300, Taiwan.
	25	*
	26	* Larry Finger <Larry.Finger@lwfinger.net>
	27	*
	28	*****************************************************************************/
	29
	30	#ifndef __RTL_PCI_H__
	31	#define __RTL_PCI_H__
	32
	33	#include <linux/pci.h>
	34	/*
	35	1: MSDU packet queue,
	36	2: Rx Command Queue
	37	*/
	38	#define RTL_PCI_RX_MPDU_QUEUE 0
	39	#define RTL_PCI_RX_CMD_QUEUE 1
	40	#define RTL_PCI_MAX_RX_QUEUE 2
	41
	42	#define RTL_PCI_MAX_RX_COUNT 64
	43	#define RTL_PCI_MAX_TX_QUEUE_COUNT 9
	44
	45	#define RT_TXDESC_NUM 128
	46	#define RT_TXDESC_NUM_BE_QUEUE 256
	47
	48	#define BK_QUEUE 0
	49	#define BE_QUEUE 1
	50	#define VI_QUEUE 2
	51	#define VO_QUEUE 3
	52	#define BEACON_QUEUE 4
	53	#define TXCMD_QUEUE 5
	54	#define MGNT_QUEUE 6
	55	#define HIGH_QUEUE 7
	56	#define HCCA_QUEUE 8
	57
	58	#define RTL_PCI_DEVICE(vend, dev, cfg) \
	59	.vendor = (vend), \
	60	.device = (dev), \
	61	.subvendor = PCI_ANY_ID, \
	62	.subdevice = PCI_ANY_ID,\
	63	.driver_data = (kernel_ulong_t)&(cfg)
	64
0c817338 LF	65	#define PCI_MAX_BRIDGE_NUMBER 255
	66	#define PCI_MAX_DEVICES 32
	67	#define PCI_MAX_FUNCTION 8
	68
	69	#define PCI_CONF_ADDRESS 0x0CF8 /PCI Configuration Space Address /
	70	#define PCI_CONF_DATA 0x0CFC /PCI Configuration Space Data /
	71
0c817338 LF	72	#define U1DONTCARE 0xFF
	73	#define U2DONTCARE 0xFFFF
	74	#define U4DONTCARE 0xFFFFFFFF
	75
	76	#define RTL_PCI_8192_DID 0x8192 /8192 PCI-E /
	77	#define RTL_PCI_8192SE_DID 0x8192 /8192 SE /
	78	#define RTL_PCI_8174_DID 0x8174 /8192 SE /
	79	#define RTL_PCI_8173_DID 0x8173 /8191 SE Crab /
	80	#define RTL_PCI_8172_DID 0x8172 /8191 SE RE /
	81	#define RTL_PCI_8171_DID 0x8171 /8191 SE Unicron /
0f015453	82	#define RTL_PCI_8723AE_DID 0x8723 /8723AE /
0c817338 LF	83	#define RTL_PCI_0045_DID 0x0045 /8190 PCI for Ceraga /
	84	#define RTL_PCI_0046_DID 0x0046 /8190 Cardbus for Ceraga /
	85	#define RTL_PCI_0044_DID 0x0044 /8192e PCIE for Ceraga /
	86	#define RTL_PCI_0047_DID 0x0047 /8192e Express Card for Ceraga /
	87	#define RTL_PCI_700F_DID 0x700F
	88	#define RTL_PCI_701F_DID 0x701F
	89	#define RTL_PCI_DLINK_DID 0x3304
	90	#define RTL_PCI_8192CET_DID 0x8191 /8192ce /
	91	#define RTL_PCI_8192CE_DID 0x8178 /8192ce /
	92	#define RTL_PCI_8191CE_DID 0x8177 /8192ce /
	93	#define RTL_PCI_8188CE_DID 0x8176 /8192ce /
	94	#define RTL_PCI_8192CU_DID 0x8191 /8192ce /
c7cfe38e C	95	#define RTL_PCI_8192DE_DID 0x8193 /8192de /
c7cfe38e C	96	#define RTL_PCI_8192DE_DID2 0x002B /92DE/
0c817338 LF	97
	98	/8192 support 16 pages of IO registers/
	99	#define RTL_MEM_MAPPED_IO_RANGE_8190PCI 0x1000
	100	#define RTL_MEM_MAPPED_IO_RANGE_8192PCIE 0x4000
	101	#define RTL_MEM_MAPPED_IO_RANGE_8192SE 0x4000
	102	#define RTL_MEM_MAPPED_IO_RANGE_8192CE 0x4000
	103	#define RTL_MEM_MAPPED_IO_RANGE_8192DE 0x4000
	104
	105	#define RTL_PCI_REVISION_ID_8190PCI 0x00
	106	#define RTL_PCI_REVISION_ID_8192PCIE 0x01
	107	#define RTL_PCI_REVISION_ID_8192SE 0x10
	108	#define RTL_PCI_REVISION_ID_8192CE 0x1
	109	#define RTL_PCI_REVISION_ID_8192DE 0x0
	110
	111	#define RTL_DEFAULT_HARDWARE_TYPE HARDWARE_TYPE_RTL8192CE
	112
	113	enum pci_bridge_vendor {
	114	PCI_BRIDGE_VENDOR_INTEL = 0x0, /0b'0000,0001 /
	115	PCI_BRIDGE_VENDOR_ATI, /0b'0000,0010/
	116	PCI_BRIDGE_VENDOR_AMD, /0b'0000,0100/
	117	PCI_BRIDGE_VENDOR_SIS, /0b'0000,1000/
	118	PCI_BRIDGE_VENDOR_UNKNOWN, /0b'0100,0000/
	119	PCI_BRIDGE_VENDOR_MAX,
	120	};
	121
c7cfe38e C	122	struct rtl_pci_capabilities_header {
	123	u8 capability_id;
	124	u8 next;
	125	};
	126
0c817338 LF	127	struct rtl_rx_desc {
0c817338 LF	128	u32 dword[8];
e137478b	129	} __packed;
0c817338 LF	130
	131	struct rtl_tx_desc {
	132	u32 dword[16];
e137478b	133	} __packed;
0c817338 LF	134
	135	struct rtl_tx_cmd_desc {
	136	u32 dword[16];
e137478b	137	} __packed;
0c817338 LF	138
	139	struct rtl8192_tx_ring {
	140	struct rtl_tx_desc *desc;
	141	dma_addr_t dma;
	142	unsigned int idx;
	143	unsigned int entries;
	144	struct sk_buff_head queue;
	145	};
	146
	147	struct rtl8192_rx_ring {
	148	struct rtl_rx_desc *desc;
	149	dma_addr_t dma;
	150	unsigned int idx;
	151	struct sk_buff *rx_buf[RTL_PCI_MAX_RX_COUNT];
	152	};
	153
	154	struct rtl_pci {
	155	struct pci_dev *pdev;
a2905935	156	bool irq_enabled;
0c817338 LF	157
	158	bool driver_is_goingto_unload;
	159	bool up_first_time;
c7cfe38e	160	bool first_init;
0c817338	161	bool being_init_adapter;
c7cfe38e	162	bool init_ready;
0c817338 LF	163
	164	/Tx /
	165	struct rtl8192_tx_ring tx_ring[RTL_PCI_MAX_TX_QUEUE_COUNT];
	166	int txringcount[RTL_PCI_MAX_TX_QUEUE_COUNT];
	167	u32 transmit_config;
	168
	169	/Rx /
	170	struct rtl8192_rx_ring rx_ring[RTL_PCI_MAX_RX_QUEUE];
	171	int rxringcount;
	172	u16 rxbuffersize;
	173	u32 receive_config;
	174
	175	/irq /
	176	u8 irq_alloc;
	177	u32 irq_mask[2];
	178
	179	/Bcn control register setting /
	180	u32 reg_bcn_ctrl_val;
	181
	182	/ASPM/ u8 const_pci_aspm;
	183	u8 const_amdpci_aspm;
	184	u8 const_hwsw_rfoff_d3;
	185	u8 const_support_pciaspm;
	186	/pci-e bridge /
	187	u8 const_hostpci_aspm_setting;
	188	/pci-e device /
	189	u8 const_devicepci_aspm_setting;
	190	/*If it supports ASPM, Offset[560h] = 0x40,
	191	otherwise Offset[560h] = 0x00. */
32473284 LF	192	bool support_aspm;
32473284 LF	193	bool support_backdoor;
0c817338 LF	194
	195	/QOS & EDCA /
	196	enum acm_method acm_method;
c7cfe38e C	197
	198	u16 shortretry_limit;
	199	u16 longretry_limit;
0c817338 LF	200	};
	201
	202	struct mp_adapter {
	203	u8 linkctrl_reg;
	204
	205	u8 busnumber;
	206	u8 devnumber;
	207	u8 funcnumber;
	208
	209	u8 pcibridge_busnum;
	210	u8 pcibridge_devnum;
	211	u8 pcibridge_funcnum;
	212
	213	u8 pcibridge_vendor;
	214	u16 pcibridge_vendorid;
	215	u16 pcibridge_deviceid;
	216
0c817338 LF	217	u8 num4bytes;
	218
	219	u8 pcibridge_pciehdr_offset;
	220	u8 pcibridge_linkctrlreg;
	221
	222	bool amd_l1_patch;
	223	};
	224
	225	struct rtl_pci_priv {
	226	struct rtl_pci dev;
	227	struct mp_adapter ndis_adapter;
	228	struct rtl_led_ctl ledctl;
c7cfe38e	229	struct bt_coexist_info bt_coexist;
0c817338 LF	230	};
	231
	232	#define rtl_pcipriv(hw) (((struct rtl_pci_priv *)(rtl_priv(hw))->priv))
	233	#define rtl_pcidev(pcipriv) (&((pcipriv)->dev))
	234
	235	int rtl_pci_reset_trx_ring(struct ieee80211_hw *hw);
	236
	237	extern struct rtl_intf_ops rtl_pci_ops;
	238
	239	int __devinit rtl_pci_probe(struct pci_dev *pdev,
	240	const struct pci_device_id *id);
	241	void rtl_pci_disconnect(struct pci_dev *pdev);
603be388 LF	242	int rtl_pci_suspend(struct device *dev);
603be388 LF	243	int rtl_pci_resume(struct device *dev);
0c817338 LF	244	static inline u8 pci_read8_sync(struct rtl_priv *rtlpriv, u32 addr)
0c817338 LF	245	{
62e63975	246	return readb((u8 __iomem *) rtlpriv->io.pci_mem_start + addr);
0c817338 LF	247	}
	248
	249	static inline u16 pci_read16_sync(struct rtl_priv *rtlpriv, u32 addr)
	250	{
62e63975	251	return readw((u8 __iomem *) rtlpriv->io.pci_mem_start + addr);
0c817338 LF	252	}
	253
	254	static inline u32 pci_read32_sync(struct rtl_priv *rtlpriv, u32 addr)
	255	{
62e63975	256	return readl((u8 __iomem *) rtlpriv->io.pci_mem_start + addr);
0c817338 LF	257	}
	258
	259	static inline void pci_write8_async(struct rtl_priv *rtlpriv, u32 addr, u8 val)
	260	{
62e63975	261	writeb(val, (u8 __iomem *) rtlpriv->io.pci_mem_start + addr);
0c817338 LF	262	}
	263
	264	static inline void pci_write16_async(struct rtl_priv *rtlpriv,
	265	u32 addr, u16 val)
	266	{
62e63975	267	writew(val, (u8 __iomem *) rtlpriv->io.pci_mem_start + addr);
0c817338 LF	268	}
	269
	270	static inline void pci_write32_async(struct rtl_priv *rtlpriv,
	271	u32 addr, u32 val)
	272	{
62e63975	273	writel(val, (u8 __iomem *) rtlpriv->io.pci_mem_start + addr);
0c817338 LF	274	}
0c817338 LF	275
0c817338	276	#endif