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rename dev_hw_addr_random and remove redundant second
[deliverable/linux.git] / drivers / net / wireless / rtlwifi / rtl8192c / dm_common.c
CommitLineData
8c96fcf7
LF		 1/******************************************************************************
2 *
fc616856 3 * Copyright(c) 2009-2012 Realtek Corporation.
8c96fcf7
LF		 4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of version 2 of the GNU General Public License as
7 * published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details.
13 *
14 * You should have received a copy of the GNU General Public License along with
15 * this program; if not, write to the Free Software Foundation, Inc.,
16 * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
17 *
18 * The full GNU General Public License is included in this distribution in the
19 * file called LICENSE.
20 *
21 * Contact Information:
22 * wlanfae <wlanfae@realtek.com>
23 * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
24 * Hsinchu 300, Taiwan.
25 *
26 * Larry Finger <Larry.Finger@lwfinger.net>
27 *
28 *****************************************************************************/
29
ee40fa06 30#include <linux/export.h>
1472d3a8 31#include "dm_common.h"
beb5bc40
C		 32#include "phy_common.h"
33#include "../pci.h"
34#include "../base.h"
1472d3a8 35
8c96fcf7
LF		 36struct dig_t dm_digtable;
37static struct ps_t dm_pstable;
38
beb5bc40
C		 39#define BT_RSSI_STATE_NORMAL_POWER BIT_OFFSET_LEN_MASK_32(0, 1)
40#define BT_RSSI_STATE_AMDPU_OFF BIT_OFFSET_LEN_MASK_32(1, 1)
41#define BT_RSSI_STATE_SPECIAL_LOW BIT_OFFSET_LEN_MASK_32(2, 1)
42#define BT_RSSI_STATE_BG_EDCA_LOW BIT_OFFSET_LEN_MASK_32(3, 1)
43#define BT_RSSI_STATE_TXPOWER_LOW BIT_OFFSET_LEN_MASK_32(4, 1)
44
45#define RTLPRIV (struct rtl_priv *)
46#define GET_UNDECORATED_AVERAGE_RSSI(_priv) \
47 ((RTLPRIV(_priv))->mac80211.opmode == \
48 NL80211_IFTYPE_ADHOC) ? \
49 ((RTLPRIV(_priv))->dm.entry_min_undecoratedsmoothed_pwdb) : \
50 ((RTLPRIV(_priv))->dm.undecorated_smoothed_pwdb)
51
8c96fcf7
LF		 52static const u32 ofdmswing_table[OFDM_TABLE_SIZE] = {
53 0x7f8001fe,
54 0x788001e2,
55 0x71c001c7,
56 0x6b8001ae,
57 0x65400195,
58 0x5fc0017f,
59 0x5a400169,
60 0x55400155,
61 0x50800142,
62 0x4c000130,
63 0x47c0011f,
64 0x43c0010f,
65 0x40000100,
66 0x3c8000f2,
67 0x390000e4,
68 0x35c000d7,
69 0x32c000cb,
70 0x300000c0,
71 0x2d4000b5,
72 0x2ac000ab,
73 0x288000a2,
74 0x26000098,
75 0x24000090,
76 0x22000088,
77 0x20000080,
78 0x1e400079,
79 0x1c800072,
80 0x1b00006c,
81 0x19800066,
82 0x18000060,
83 0x16c0005b,
84 0x15800056,
85 0x14400051,
86 0x1300004c,
87 0x12000048,
88 0x11000044,
89 0x10000040,
90};
91
92static const u8 cckswing_table_ch1ch13[CCK_TABLE_SIZE][8] = {
93 {0x36, 0x35, 0x2e, 0x25, 0x1c, 0x12, 0x09, 0x04},
94 {0x33, 0x32, 0x2b, 0x23, 0x1a, 0x11, 0x08, 0x04},
95 {0x30, 0x2f, 0x29, 0x21, 0x19, 0x10, 0x08, 0x03},
96 {0x2d, 0x2d, 0x27, 0x1f, 0x18, 0x0f, 0x08, 0x03},
97 {0x2b, 0x2a, 0x25, 0x1e, 0x16, 0x0e, 0x07, 0x03},
98 {0x28, 0x28, 0x22, 0x1c, 0x15, 0x0d, 0x07, 0x03},
99 {0x26, 0x25, 0x21, 0x1b, 0x14, 0x0d, 0x06, 0x03},
100 {0x24, 0x23, 0x1f, 0x19, 0x13, 0x0c, 0x06, 0x03},
101 {0x22, 0x21, 0x1d, 0x18, 0x11, 0x0b, 0x06, 0x02},
102 {0x20, 0x20, 0x1b, 0x16, 0x11, 0x08, 0x05, 0x02},
103 {0x1f, 0x1e, 0x1a, 0x15, 0x10, 0x0a, 0x05, 0x02},
104 {0x1d, 0x1c, 0x18, 0x14, 0x0f, 0x0a, 0x05, 0x02},
105 {0x1b, 0x1a, 0x17, 0x13, 0x0e, 0x09, 0x04, 0x02},
106 {0x1a, 0x19, 0x16, 0x12, 0x0d, 0x09, 0x04, 0x02},
107 {0x18, 0x17, 0x15, 0x11, 0x0c, 0x08, 0x04, 0x02},
108 {0x17, 0x16, 0x13, 0x10, 0x0c, 0x08, 0x04, 0x02},
109 {0x16, 0x15, 0x12, 0x0f, 0x0b, 0x07, 0x04, 0x01},
110 {0x14, 0x14, 0x11, 0x0e, 0x0b, 0x07, 0x03, 0x02},
111 {0x13, 0x13, 0x10, 0x0d, 0x0a, 0x06, 0x03, 0x01},
112 {0x12, 0x12, 0x0f, 0x0c, 0x09, 0x06, 0x03, 0x01},
113 {0x11, 0x11, 0x0f, 0x0c, 0x09, 0x06, 0x03, 0x01},
114 {0x10, 0x10, 0x0e, 0x0b, 0x08, 0x05, 0x03, 0x01},
115 {0x0f, 0x0f, 0x0d, 0x0b, 0x08, 0x05, 0x03, 0x01},
116 {0x0e, 0x0e, 0x0c, 0x0a, 0x08, 0x05, 0x02, 0x01},
117 {0x0d, 0x0d, 0x0c, 0x0a, 0x07, 0x05, 0x02, 0x01},
118 {0x0d, 0x0c, 0x0b, 0x09, 0x07, 0x04, 0x02, 0x01},
119 {0x0c, 0x0c, 0x0a, 0x09, 0x06, 0x04, 0x02, 0x01},
120 {0x0b, 0x0b, 0x0a, 0x08, 0x06, 0x04, 0x02, 0x01},
121 {0x0b, 0x0a, 0x09, 0x08, 0x06, 0x04, 0x02, 0x01},
122 {0x0a, 0x0a, 0x09, 0x07, 0x05, 0x03, 0x02, 0x01},
123 {0x0a, 0x09, 0x08, 0x07, 0x05, 0x03, 0x02, 0x01},
124 {0x09, 0x09, 0x08, 0x06, 0x05, 0x03, 0x01, 0x01},
125 {0x09, 0x08, 0x07, 0x06, 0x04, 0x03, 0x01, 0x01}
126};
127
128static const u8 cckswing_table_ch14[CCK_TABLE_SIZE][8] = {
129 {0x36, 0x35, 0x2e, 0x1b, 0x00, 0x00, 0x00, 0x00},
130 {0x33, 0x32, 0x2b, 0x19, 0x00, 0x00, 0x00, 0x00},
131 {0x30, 0x2f, 0x29, 0x18, 0x00, 0x00, 0x00, 0x00},
132 {0x2d, 0x2d, 0x17, 0x17, 0x00, 0x00, 0x00, 0x00},
133 {0x2b, 0x2a, 0x25, 0x15, 0x00, 0x00, 0x00, 0x00},
134 {0x28, 0x28, 0x24, 0x14, 0x00, 0x00, 0x00, 0x00},
135 {0x26, 0x25, 0x21, 0x13, 0x00, 0x00, 0x00, 0x00},
136 {0x24, 0x23, 0x1f, 0x12, 0x00, 0x00, 0x00, 0x00},
137 {0x22, 0x21, 0x1d, 0x11, 0x00, 0x00, 0x00, 0x00},
138 {0x20, 0x20, 0x1b, 0x10, 0x00, 0x00, 0x00, 0x00},
139 {0x1f, 0x1e, 0x1a, 0x0f, 0x00, 0x00, 0x00, 0x00},
140 {0x1d, 0x1c, 0x18, 0x0e, 0x00, 0x00, 0x00, 0x00},
141 {0x1b, 0x1a, 0x17, 0x0e, 0x00, 0x00, 0x00, 0x00},
142 {0x1a, 0x19, 0x16, 0x0d, 0x00, 0x00, 0x00, 0x00},
143 {0x18, 0x17, 0x15, 0x0c, 0x00, 0x00, 0x00, 0x00},
144 {0x17, 0x16, 0x13, 0x0b, 0x00, 0x00, 0x00, 0x00},
145 {0x16, 0x15, 0x12, 0x0b, 0x00, 0x00, 0x00, 0x00},
146 {0x14, 0x14, 0x11, 0x0a, 0x00, 0x00, 0x00, 0x00},
147 {0x13, 0x13, 0x10, 0x0a, 0x00, 0x00, 0x00, 0x00},
148 {0x12, 0x12, 0x0f, 0x09, 0x00, 0x00, 0x00, 0x00},
149 {0x11, 0x11, 0x0f, 0x09, 0x00, 0x00, 0x00, 0x00},
150 {0x10, 0x10, 0x0e, 0x08, 0x00, 0x00, 0x00, 0x00},
151 {0x0f, 0x0f, 0x0d, 0x08, 0x00, 0x00, 0x00, 0x00},
152 {0x0e, 0x0e, 0x0c, 0x07, 0x00, 0x00, 0x00, 0x00},
153 {0x0d, 0x0d, 0x0c, 0x07, 0x00, 0x00, 0x00, 0x00},
154 {0x0d, 0x0c, 0x0b, 0x06, 0x00, 0x00, 0x00, 0x00},
155 {0x0c, 0x0c, 0x0a, 0x06, 0x00, 0x00, 0x00, 0x00},
156 {0x0b, 0x0b, 0x0a, 0x06, 0x00, 0x00, 0x00, 0x00},
157 {0x0b, 0x0a, 0x09, 0x05, 0x00, 0x00, 0x00, 0x00},
158 {0x0a, 0x0a, 0x09, 0x05, 0x00, 0x00, 0x00, 0x00},
159 {0x0a, 0x09, 0x08, 0x05, 0x00, 0x00, 0x00, 0x00},
160 {0x09, 0x09, 0x08, 0x05, 0x00, 0x00, 0x00, 0x00},
161 {0x09, 0x08, 0x07, 0x04, 0x00, 0x00, 0x00, 0x00}
162};
163
164static void rtl92c_dm_diginit(struct ieee80211_hw *hw)
165{
166 dm_digtable.dig_enable_flag = true;
167 dm_digtable.dig_ext_port_stage = DIG_EXT_PORT_STAGE_MAX;
168 dm_digtable.cur_igvalue = 0x20;
169 dm_digtable.pre_igvalue = 0x0;
170 dm_digtable.cursta_connectctate = DIG_STA_DISCONNECT;
171 dm_digtable.presta_connectstate = DIG_STA_DISCONNECT;
172 dm_digtable.curmultista_connectstate = DIG_MULTISTA_DISCONNECT;
173 dm_digtable.rssi_lowthresh = DM_DIG_THRESH_LOW;
174 dm_digtable.rssi_highthresh = DM_DIG_THRESH_HIGH;
175 dm_digtable.fa_lowthresh = DM_FALSEALARM_THRESH_LOW;
176 dm_digtable.fa_highthresh = DM_FALSEALARM_THRESH_HIGH;
177 dm_digtable.rx_gain_range_max = DM_DIG_MAX;
178 dm_digtable.rx_gain_range_min = DM_DIG_MIN;
179 dm_digtable.backoff_val = DM_DIG_BACKOFF_DEFAULT;
180 dm_digtable.backoff_val_range_max = DM_DIG_BACKOFF_MAX;
181 dm_digtable.backoff_val_range_min = DM_DIG_BACKOFF_MIN;
182 dm_digtable.pre_cck_pd_state = CCK_PD_STAGE_MAX;
183 dm_digtable.cur_cck_pd_state = CCK_PD_STAGE_MAX;
184}
185
186static u8 rtl92c_dm_initial_gain_min_pwdb(struct ieee80211_hw *hw)
187{
188 struct rtl_priv *rtlpriv = rtl_priv(hw);
189 long rssi_val_min = 0;
190
191 if ((dm_digtable.curmultista_connectstate == DIG_MULTISTA_CONNECT) &&
192 (dm_digtable.cursta_connectctate == DIG_STA_CONNECT)) {
193 if (rtlpriv->dm.entry_min_undecoratedsmoothed_pwdb != 0)
194 rssi_val_min =
195 (rtlpriv->dm.entry_min_undecoratedsmoothed_pwdb >
196 rtlpriv->dm.undecorated_smoothed_pwdb) ?
197 rtlpriv->dm.undecorated_smoothed_pwdb :
198 rtlpriv->dm.entry_min_undecoratedsmoothed_pwdb;
199 else
200 rssi_val_min = rtlpriv->dm.undecorated_smoothed_pwdb;
201 } else if (dm_digtable.cursta_connectctate == DIG_STA_CONNECT ||
202 dm_digtable.cursta_connectctate == DIG_STA_BEFORE_CONNECT) {
203 rssi_val_min = rtlpriv->dm.undecorated_smoothed_pwdb;
204 } else if (dm_digtable.curmultista_connectstate ==
205 DIG_MULTISTA_CONNECT) {
206 rssi_val_min = rtlpriv->dm.entry_min_undecoratedsmoothed_pwdb;
207 }
208
209 return (u8) rssi_val_min;
210}
211
212static void rtl92c_dm_false_alarm_counter_statistics(struct ieee80211_hw *hw)
213{
214 u32 ret_value;
215 struct rtl_priv *rtlpriv = rtl_priv(hw);
216 struct false_alarm_statistics *falsealm_cnt = &(rtlpriv->falsealm_cnt);
217
218 ret_value = rtl_get_bbreg(hw, ROFDM_PHYCOUNTER1, MASKDWORD);
219 falsealm_cnt->cnt_parity_fail = ((ret_value & 0xffff0000) >> 16);
220
221 ret_value = rtl_get_bbreg(hw, ROFDM_PHYCOUNTER2, MASKDWORD);
222 falsealm_cnt->cnt_rate_illegal = (ret_value & 0xffff);
223 falsealm_cnt->cnt_crc8_fail = ((ret_value & 0xffff0000) >> 16);
224
225 ret_value = rtl_get_bbreg(hw, ROFDM_PHYCOUNTER3, MASKDWORD);
226 falsealm_cnt->cnt_mcs_fail = (ret_value & 0xffff);
227 falsealm_cnt->cnt_ofdm_fail = falsealm_cnt->cnt_parity_fail +
228 falsealm_cnt->cnt_rate_illegal +
229 falsealm_cnt->cnt_crc8_fail + falsealm_cnt->cnt_mcs_fail;
230
231 rtl_set_bbreg(hw, RCCK0_FALSEALARMREPORT, BIT(14), 1);
232 ret_value = rtl_get_bbreg(hw, RCCK0_FACOUNTERLOWER, MASKBYTE0);
233 falsealm_cnt->cnt_cck_fail = ret_value;
234
235 ret_value = rtl_get_bbreg(hw, RCCK0_FACOUNTERUPPER, MASKBYTE3);
236 falsealm_cnt->cnt_cck_fail += (ret_value & 0xff) << 8;
237 falsealm_cnt->cnt_all = (falsealm_cnt->cnt_parity_fail +
238 falsealm_cnt->cnt_rate_illegal +
239 falsealm_cnt->cnt_crc8_fail +
240 falsealm_cnt->cnt_mcs_fail +
241 falsealm_cnt->cnt_cck_fail);
242
243 rtl_set_bbreg(hw, ROFDM1_LSTF, 0x08000000, 1);
244 rtl_set_bbreg(hw, ROFDM1_LSTF, 0x08000000, 0);
245 rtl_set_bbreg(hw, RCCK0_FALSEALARMREPORT, 0x0000c000, 0);
246 rtl_set_bbreg(hw, RCCK0_FALSEALARMREPORT, 0x0000c000, 2);
247
248 RT_TRACE(rtlpriv, COMP_DIG, DBG_TRACE,
f30d7507
JP		 249 "cnt_parity_fail = %d, cnt_rate_illegal = %d, cnt_crc8_fail = %d, cnt_mcs_fail = %d\n",
250 falsealm_cnt->cnt_parity_fail,
251 falsealm_cnt->cnt_rate_illegal,
252 falsealm_cnt->cnt_crc8_fail, falsealm_cnt->cnt_mcs_fail);
8c96fcf7
LF		 253
254 RT_TRACE(rtlpriv, COMP_DIG, DBG_TRACE,
f30d7507
JP		 255 "cnt_ofdm_fail = %x, cnt_cck_fail = %x, cnt_all = %x\n",
256 falsealm_cnt->cnt_ofdm_fail,
257 falsealm_cnt->cnt_cck_fail, falsealm_cnt->cnt_all);
8c96fcf7
LF		 258}
259
260static void rtl92c_dm_ctrl_initgain_by_fa(struct ieee80211_hw *hw)
261{
262 struct rtl_priv *rtlpriv = rtl_priv(hw);
263 u8 value_igi = dm_digtable.cur_igvalue;
264
265 if (rtlpriv->falsealm_cnt.cnt_all < DM_DIG_FA_TH0)
266 value_igi--;
267 else if (rtlpriv->falsealm_cnt.cnt_all < DM_DIG_FA_TH1)
268 value_igi += 0;
269 else if (rtlpriv->falsealm_cnt.cnt_all < DM_DIG_FA_TH2)
270 value_igi++;
271 else if (rtlpriv->falsealm_cnt.cnt_all >= DM_DIG_FA_TH2)
272 value_igi += 2;
273 if (value_igi > DM_DIG_FA_UPPER)
274 value_igi = DM_DIG_FA_UPPER;
275 else if (value_igi < DM_DIG_FA_LOWER)
276 value_igi = DM_DIG_FA_LOWER;
277 if (rtlpriv->falsealm_cnt.cnt_all > 10000)
278 value_igi = 0x32;
279
280 dm_digtable.cur_igvalue = value_igi;
281 rtl92c_dm_write_dig(hw);
282}
283
284static void rtl92c_dm_ctrl_initgain_by_rssi(struct ieee80211_hw *hw)
285{
286 struct rtl_priv *rtlpriv = rtl_priv(hw);
287
288 if (rtlpriv->falsealm_cnt.cnt_all > dm_digtable.fa_highthresh) {
289 if ((dm_digtable.backoff_val - 2) <
290 dm_digtable.backoff_val_range_min)
291 dm_digtable.backoff_val =
292 dm_digtable.backoff_val_range_min;
293 else
294 dm_digtable.backoff_val -= 2;
295 } else if (rtlpriv->falsealm_cnt.cnt_all < dm_digtable.fa_lowthresh) {
296 if ((dm_digtable.backoff_val + 2) >
297 dm_digtable.backoff_val_range_max)
298 dm_digtable.backoff_val =
299 dm_digtable.backoff_val_range_max;
300 else
301 dm_digtable.backoff_val += 2;
302 }
303
304 if ((dm_digtable.rssi_val_min + 10 - dm_digtable.backoff_val) >
305 dm_digtable.rx_gain_range_max)
306 dm_digtable.cur_igvalue = dm_digtable.rx_gain_range_max;
307 else if ((dm_digtable.rssi_val_min + 10 -
308 dm_digtable.backoff_val) < dm_digtable.rx_gain_range_min)
309 dm_digtable.cur_igvalue = dm_digtable.rx_gain_range_min;
310 else
311 dm_digtable.cur_igvalue = dm_digtable.rssi_val_min + 10 -
312 dm_digtable.backoff_val;
313
314 RT_TRACE(rtlpriv, COMP_DIG, DBG_TRACE,
f30d7507
JP		 315 "rssi_val_min = %x backoff_val %x\n",
316 dm_digtable.rssi_val_min, dm_digtable.backoff_val);
8c96fcf7
LF		 317
318 rtl92c_dm_write_dig(hw);
319}
320
321static void rtl92c_dm_initial_gain_multi_sta(struct ieee80211_hw *hw)
322{
2b8359f8 323 static u8 initialized; /* initialized to false */
8c96fcf7
LF		 324 struct rtl_priv *rtlpriv = rtl_priv(hw);
325 struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
326 long rssi_strength = rtlpriv->dm.entry_min_undecoratedsmoothed_pwdb;
7ea47240 327 bool multi_sta = false;
8c96fcf7
LF		 328
329 if (mac->opmode == NL80211_IFTYPE_ADHOC)
7ea47240 330 multi_sta = true;
8c96fcf7 331
7ea47240
LF		 332 if ((multi_sta == false) || (dm_digtable.cursta_connectctate !=
333 DIG_STA_DISCONNECT)) {
2b8359f8 334 initialized = false;
8c96fcf7
LF		 335 dm_digtable.dig_ext_port_stage = DIG_EXT_PORT_STAGE_MAX;
336 return;
2b8359f8
C		 337 } else if (initialized == false) {
338 initialized = true;
8c96fcf7
LF		 339 dm_digtable.dig_ext_port_stage = DIG_EXT_PORT_STAGE_0;
340 dm_digtable.cur_igvalue = 0x20;
341 rtl92c_dm_write_dig(hw);
342 }
343
344 if (dm_digtable.curmultista_connectstate == DIG_MULTISTA_CONNECT) {
345 if ((rssi_strength < dm_digtable.rssi_lowthresh) &&
346 (dm_digtable.dig_ext_port_stage != DIG_EXT_PORT_STAGE_1)) {
347
348 if (dm_digtable.dig_ext_port_stage ==
349 DIG_EXT_PORT_STAGE_2) {
350 dm_digtable.cur_igvalue = 0x20;
351 rtl92c_dm_write_dig(hw);
352 }
353
354 dm_digtable.dig_ext_port_stage = DIG_EXT_PORT_STAGE_1;
355 } else if (rssi_strength > dm_digtable.rssi_highthresh) {
356 dm_digtable.dig_ext_port_stage = DIG_EXT_PORT_STAGE_2;
357 rtl92c_dm_ctrl_initgain_by_fa(hw);
358 }
359 } else if (dm_digtable.dig_ext_port_stage != DIG_EXT_PORT_STAGE_0) {
360 dm_digtable.dig_ext_port_stage = DIG_EXT_PORT_STAGE_0;
361 dm_digtable.cur_igvalue = 0x20;
362 rtl92c_dm_write_dig(hw);
363 }
364
365 RT_TRACE(rtlpriv, COMP_DIG, DBG_TRACE,
f30d7507
JP		 366 "curmultista_connectstate = %x dig_ext_port_stage %x\n",
367 dm_digtable.curmultista_connectstate,
368 dm_digtable.dig_ext_port_stage);
8c96fcf7
LF		 369}
370
371static void rtl92c_dm_initial_gain_sta(struct ieee80211_hw *hw)
372{
373 struct rtl_priv *rtlpriv = rtl_priv(hw);
374
375 RT_TRACE(rtlpriv, COMP_DIG, DBG_TRACE,
f30d7507
JP		 376 "presta_connectstate = %x, cursta_connectctate = %x\n",
377 dm_digtable.presta_connectstate,
378 dm_digtable.cursta_connectctate);
8c96fcf7
LF		 379
380 if (dm_digtable.presta_connectstate == dm_digtable.cursta_connectctate
381 || dm_digtable.cursta_connectctate == DIG_STA_BEFORE_CONNECT
382 || dm_digtable.cursta_connectctate == DIG_STA_CONNECT) {
383
384 if (dm_digtable.cursta_connectctate != DIG_STA_DISCONNECT) {
385 dm_digtable.rssi_val_min =
386 rtl92c_dm_initial_gain_min_pwdb(hw);
387 rtl92c_dm_ctrl_initgain_by_rssi(hw);
388 }
389 } else {
390 dm_digtable.rssi_val_min = 0;
391 dm_digtable.dig_ext_port_stage = DIG_EXT_PORT_STAGE_MAX;
392 dm_digtable.backoff_val = DM_DIG_BACKOFF_DEFAULT;
393 dm_digtable.cur_igvalue = 0x20;
394 dm_digtable.pre_igvalue = 0;
395 rtl92c_dm_write_dig(hw);
396 }
397}
398
399static void rtl92c_dm_cck_packet_detection_thresh(struct ieee80211_hw *hw)
400{
401 struct rtl_priv *rtlpriv = rtl_priv(hw);
402 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
403
404 if (dm_digtable.cursta_connectctate == DIG_STA_CONNECT) {
405 dm_digtable.rssi_val_min = rtl92c_dm_initial_gain_min_pwdb(hw);
406
407 if (dm_digtable.pre_cck_pd_state == CCK_PD_STAGE_LowRssi) {
408 if (dm_digtable.rssi_val_min <= 25)
409 dm_digtable.cur_cck_pd_state =
410 CCK_PD_STAGE_LowRssi;
411 else
412 dm_digtable.cur_cck_pd_state =
413 CCK_PD_STAGE_HighRssi;
414 } else {
415 if (dm_digtable.rssi_val_min <= 20)
416 dm_digtable.cur_cck_pd_state =
417 CCK_PD_STAGE_LowRssi;
418 else
419 dm_digtable.cur_cck_pd_state =
420 CCK_PD_STAGE_HighRssi;
421 }
422 } else {
423 dm_digtable.cur_cck_pd_state = CCK_PD_STAGE_MAX;
424 }
425
426 if (dm_digtable.pre_cck_pd_state != dm_digtable.cur_cck_pd_state) {
427 if (dm_digtable.cur_cck_pd_state == CCK_PD_STAGE_LowRssi) {
428 if (rtlpriv->falsealm_cnt.cnt_cck_fail > 800)
429 dm_digtable.cur_cck_fa_state =
430 CCK_FA_STAGE_High;
431 else
432 dm_digtable.cur_cck_fa_state = CCK_FA_STAGE_Low;
433
434 if (dm_digtable.pre_cck_fa_state !=
435 dm_digtable.cur_cck_fa_state) {
436 if (dm_digtable.cur_cck_fa_state ==
437 CCK_FA_STAGE_Low)
438 rtl_set_bbreg(hw, RCCK0_CCA, MASKBYTE2,
439 0x83);
440 else
441 rtl_set_bbreg(hw, RCCK0_CCA, MASKBYTE2,
442 0xcd);
443
444 dm_digtable.pre_cck_fa_state =
445 dm_digtable.cur_cck_fa_state;
446 }
447
448 rtl_set_bbreg(hw, RCCK0_SYSTEM, MASKBYTE1, 0x40);
449
450 if (IS_92C_SERIAL(rtlhal->version))
451 rtl_set_bbreg(hw, RCCK0_FALSEALARMREPORT,
452 MASKBYTE2, 0xd7);
453 } else {
454 rtl_set_bbreg(hw, RCCK0_CCA, MASKBYTE2, 0xcd);
455 rtl_set_bbreg(hw, RCCK0_SYSTEM, MASKBYTE1, 0x47);
456
457 if (IS_92C_SERIAL(rtlhal->version))
458 rtl_set_bbreg(hw, RCCK0_FALSEALARMREPORT,
459 MASKBYTE2, 0xd3);
460 }
461 dm_digtable.pre_cck_pd_state = dm_digtable.cur_cck_pd_state;
462 }
463
f30d7507
JP		 464 RT_TRACE(rtlpriv, COMP_DIG, DBG_TRACE, "CCKPDStage=%x\n",
465 dm_digtable.cur_cck_pd_state);
8c96fcf7 466
f30d7507
JP		 467 RT_TRACE(rtlpriv, COMP_DIG, DBG_TRACE, "is92C=%x\n",
468 IS_92C_SERIAL(rtlhal->version));
8c96fcf7
LF		 469}
470
471static void rtl92c_dm_ctrl_initgain_by_twoport(struct ieee80211_hw *hw)
472{
473 struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
474
e10542c4 475 if (mac->act_scanning)
8c96fcf7
LF		 476 return;
477
beb5bc40 478 if (mac->link_state >= MAC80211_LINKED)
8c96fcf7
LF		 479 dm_digtable.cursta_connectctate = DIG_STA_CONNECT;
480 else
481 dm_digtable.cursta_connectctate = DIG_STA_DISCONNECT;
482
483 rtl92c_dm_initial_gain_sta(hw);
484 rtl92c_dm_initial_gain_multi_sta(hw);
485 rtl92c_dm_cck_packet_detection_thresh(hw);
486
487 dm_digtable.presta_connectstate = dm_digtable.cursta_connectctate;
488
489}
490
491static void rtl92c_dm_dig(struct ieee80211_hw *hw)
492{
493 struct rtl_priv *rtlpriv = rtl_priv(hw);
494
7ea47240 495 if (rtlpriv->dm.dm_initialgain_enable == false)
8c96fcf7
LF		 496 return;
497 if (dm_digtable.dig_enable_flag == false)
498 return;
499
500 rtl92c_dm_ctrl_initgain_by_twoport(hw);
501
502}
503
504static void rtl92c_dm_init_dynamic_txpower(struct ieee80211_hw *hw)
505{
506 struct rtl_priv *rtlpriv = rtl_priv(hw);
507
7ea47240 508 rtlpriv->dm.dynamic_txpower_enable = false;
8c96fcf7
LF		 509
510 rtlpriv->dm.last_dtp_lvl = TXHIGHPWRLEVEL_NORMAL;
511 rtlpriv->dm.dynamic_txhighpower_lvl = TXHIGHPWRLEVEL_NORMAL;
512}
513
514void rtl92c_dm_write_dig(struct ieee80211_hw *hw)
515{
516 struct rtl_priv *rtlpriv = rtl_priv(hw);
517
518 RT_TRACE(rtlpriv, COMP_DIG, DBG_LOUD,
f30d7507
JP		 519 "cur_igvalue = 0x%x, pre_igvalue = 0x%x, backoff_val = %d\n",
520 dm_digtable.cur_igvalue, dm_digtable.pre_igvalue,
521 dm_digtable.backoff_val);
8c96fcf7
LF		 522
523 if (dm_digtable.pre_igvalue != dm_digtable.cur_igvalue) {
524 rtl_set_bbreg(hw, ROFDM0_XAAGCCORE1, 0x7f,
525 dm_digtable.cur_igvalue);
526 rtl_set_bbreg(hw, ROFDM0_XBAGCCORE1, 0x7f,
527 dm_digtable.cur_igvalue);
528
529 dm_digtable.pre_igvalue = dm_digtable.cur_igvalue;
530 }
531}
1472d3a8 532EXPORT_SYMBOL(rtl92c_dm_write_dig);
8c96fcf7
LF		 533
534static void rtl92c_dm_pwdb_monitor(struct ieee80211_hw *hw)
535{
536 struct rtl_priv *rtlpriv = rtl_priv(hw);
537 long tmpentry_max_pwdb = 0, tmpentry_min_pwdb = 0xff;
538
539 u8 h2c_parameter[3] = { 0 };
540
541 return;
542
543 if (tmpentry_max_pwdb != 0) {
544 rtlpriv->dm.entry_max_undecoratedsmoothed_pwdb =
545 tmpentry_max_pwdb;
546 } else {
547 rtlpriv->dm.entry_max_undecoratedsmoothed_pwdb = 0;
548 }
549
550 if (tmpentry_min_pwdb != 0xff) {
551 rtlpriv->dm.entry_min_undecoratedsmoothed_pwdb =
552 tmpentry_min_pwdb;
553 } else {
554 rtlpriv->dm.entry_min_undecoratedsmoothed_pwdb = 0;
555 }
556
557 h2c_parameter[2] = (u8) (rtlpriv->dm.undecorated_smoothed_pwdb & 0xFF);
558 h2c_parameter[0] = 0;
559
560 rtl92c_fill_h2c_cmd(hw, H2C_RSSI_REPORT, 3, h2c_parameter);
561}
562
563void rtl92c_dm_init_edca_turbo(struct ieee80211_hw *hw)
564{
565 struct rtl_priv *rtlpriv = rtl_priv(hw);
7ea47240
LF		 566 rtlpriv->dm.current_turbo_edca = false;
567 rtlpriv->dm.is_any_nonbepkts = false;
568 rtlpriv->dm.is_cur_rdlstate = false;
8c96fcf7 569}
1472d3a8 570EXPORT_SYMBOL(rtl92c_dm_init_edca_turbo);
8c96fcf7
LF		 571
572static void rtl92c_dm_check_edca_turbo(struct ieee80211_hw *hw)
573{
574 struct rtl_priv *rtlpriv = rtl_priv(hw);
beb5bc40 575 struct rtl_pci_priv *rtlpcipriv = rtl_pcipriv(hw);
8c96fcf7 576 struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
beb5bc40 577
8c96fcf7
LF		 578 static u64 last_txok_cnt;
579 static u64 last_rxok_cnt;
beb5bc40
C		 580 static u32 last_bt_edca_ul;
581 static u32 last_bt_edca_dl;
582 u64 cur_txok_cnt = 0;
583 u64 cur_rxok_cnt = 0;
8c96fcf7
LF		 584 u32 edca_be_ul = 0x5ea42b;
585 u32 edca_be_dl = 0x5ea42b;
beb5bc40 586 bool bt_change_edca = false;
8c96fcf7 587
beb5bc40
C		 588 if ((last_bt_edca_ul != rtlpcipriv->bt_coexist.bt_edca_ul) ||
589 (last_bt_edca_dl != rtlpcipriv->bt_coexist.bt_edca_dl)) {
590 rtlpriv->dm.current_turbo_edca = false;
591 last_bt_edca_ul = rtlpcipriv->bt_coexist.bt_edca_ul;
592 last_bt_edca_dl = rtlpcipriv->bt_coexist.bt_edca_dl;
593 }
594
595 if (rtlpcipriv->bt_coexist.bt_edca_ul != 0) {
596 edca_be_ul = rtlpcipriv->bt_coexist.bt_edca_ul;
597 bt_change_edca = true;
598 }
599
600 if (rtlpcipriv->bt_coexist.bt_edca_dl != 0) {
601 edca_be_ul = rtlpcipriv->bt_coexist.bt_edca_dl;
602 bt_change_edca = true;
603 }
8c96fcf7
LF		 604
605 if (mac->link_state != MAC80211_LINKED) {
7ea47240 606 rtlpriv->dm.current_turbo_edca = false;
8c96fcf7
LF		 607 return;
608 }
609
beb5bc40 610 if ((!mac->ht_enable) && (!rtlpcipriv->bt_coexist.bt_coexistence)) {
8c96fcf7
LF		 611 if (!(edca_be_ul & 0xffff0000))
612 edca_be_ul |= 0x005e0000;
613
614 if (!(edca_be_dl & 0xffff0000))
615 edca_be_dl |= 0x005e0000;
616 }
617
beb5bc40
C		 618 if ((bt_change_edca) || ((!rtlpriv->dm.is_any_nonbepkts) &&
619 (!rtlpriv->dm.disable_framebursting))) {
620
8c96fcf7
LF		 621 cur_txok_cnt = rtlpriv->stats.txbytesunicast - last_txok_cnt;
622 cur_rxok_cnt = rtlpriv->stats.rxbytesunicast - last_rxok_cnt;
beb5bc40 623
8c96fcf7 624 if (cur_rxok_cnt > 4 * cur_txok_cnt) {
7ea47240
LF		 625 if (!rtlpriv->dm.is_cur_rdlstate ||
626 !rtlpriv->dm.current_turbo_edca) {
8c96fcf7
LF		 627 rtl_write_dword(rtlpriv,
628 REG_EDCA_BE_PARAM,
629 edca_be_dl);
7ea47240 630 rtlpriv->dm.is_cur_rdlstate = true;
8c96fcf7
LF		 631 }
632 } else {
7ea47240
LF		 633 if (rtlpriv->dm.is_cur_rdlstate ||
634 !rtlpriv->dm.current_turbo_edca) {
8c96fcf7
LF		 635 rtl_write_dword(rtlpriv,
636 REG_EDCA_BE_PARAM,
637 edca_be_ul);
7ea47240 638 rtlpriv->dm.is_cur_rdlstate = false;
8c96fcf7
LF		 639 }
640 }
7ea47240 641 rtlpriv->dm.current_turbo_edca = true;
8c96fcf7 642 } else {
7ea47240 643 if (rtlpriv->dm.current_turbo_edca) {
8c96fcf7
LF		 644 u8 tmp = AC0_BE;
645 rtlpriv->cfg->ops->set_hw_reg(hw,
646 HW_VAR_AC_PARAM,
647 (u8 *) (&tmp));
7ea47240 648 rtlpriv->dm.current_turbo_edca = false;
8c96fcf7
LF		 649 }
650 }
651
7ea47240 652 rtlpriv->dm.is_any_nonbepkts = false;
8c96fcf7
LF		 653 last_txok_cnt = rtlpriv->stats.txbytesunicast;
654 last_rxok_cnt = rtlpriv->stats.rxbytesunicast;
655}
656
657static void rtl92c_dm_txpower_tracking_callback_thermalmeter(struct ieee80211_hw
658 *hw)
659{
660 struct rtl_priv *rtlpriv = rtl_priv(hw);
661 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
662 struct rtl_phy *rtlphy = &(rtlpriv->phy);
663 struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
664 u8 thermalvalue, delta, delta_lck, delta_iqk;
665 long ele_a, ele_d, temp_cck, val_x, value32;
beb5bc40 666 long val_y, ele_c = 0;
9f219bd2 667 u8 ofdm_index[2], cck_index = 0, ofdm_index_old[2], cck_index_old = 0;
8c96fcf7
LF		 668 int i;
669 bool is2t = IS_92C_SERIAL(rtlhal->version);
7101f404 670 s8 txpwr_level[2] = {0, 0};
8c96fcf7
LF		 671 u8 ofdm_min_index = 6, rf;
672
3dad618b 673 rtlpriv->dm.txpower_trackinginit = true;
8c96fcf7 674 RT_TRACE(rtlpriv, COMP_POWER_TRACKING, DBG_LOUD,
f30d7507 675 "rtl92c_dm_txpower_tracking_callback_thermalmeter\n");
8c96fcf7
LF		 676
677 thermalvalue = (u8) rtl_get_rfreg(hw, RF90_PATH_A, RF_T_METER, 0x1f);
678
679 RT_TRACE(rtlpriv, COMP_POWER_TRACKING, DBG_LOUD,
f30d7507
JP		 680 "Readback Thermal Meter = 0x%x pre thermal meter 0x%x eeprom_thermalmeter 0x%x\n",
681 thermalvalue, rtlpriv->dm.thermalvalue,
682 rtlefuse->eeprom_thermalmeter);
8c96fcf7
LF		 683
684 rtl92c_phy_ap_calibrate(hw, (thermalvalue -
685 rtlefuse->eeprom_thermalmeter));
686 if (is2t)
687 rf = 2;
688 else
689 rf = 1;
690
691 if (thermalvalue) {
692 ele_d = rtl_get_bbreg(hw, ROFDM0_XATXIQIMBALANCE,
693 MASKDWORD) & MASKOFDM_D;
694
695 for (i = 0; i < OFDM_TABLE_LENGTH; i++) {
696 if (ele_d == (ofdmswing_table[i] & MASKOFDM_D)) {
697 ofdm_index_old[0] = (u8) i;
698
699 RT_TRACE(rtlpriv, COMP_POWER_TRACKING, DBG_LOUD,
f30d7507 700 "Initial pathA ele_d reg0x%x = 0x%lx, ofdm_index=0x%x\n",
8c96fcf7 701 ROFDM0_XATXIQIMBALANCE,
f30d7507 702 ele_d, ofdm_index_old[0]);
8c96fcf7
LF		 703 break;
704 }
705 }
706
707 if (is2t) {
708 ele_d = rtl_get_bbreg(hw, ROFDM0_XBTXIQIMBALANCE,
709 MASKDWORD) & MASKOFDM_D;
710
711 for (i = 0; i < OFDM_TABLE_LENGTH; i++) {
712 if (ele_d == (ofdmswing_table[i] &
713 MASKOFDM_D)) {
8c96fcf7
LF		 714
715 RT_TRACE(rtlpriv, COMP_POWER_TRACKING,
f30d7507
JP		 716 DBG_LOUD,
717 "Initial pathB ele_d reg0x%x = 0x%lx, ofdm_index=0x%x\n",
718 ROFDM0_XBTXIQIMBALANCE, ele_d,
719 ofdm_index_old[1]);
8c96fcf7
LF		 720 break;
721 }
722 }
723 }
724
725 temp_cck =
726 rtl_get_bbreg(hw, RCCK0_TXFILTER2, MASKDWORD) & MASKCCK;
727
728 for (i = 0; i < CCK_TABLE_LENGTH; i++) {
7ea47240 729 if (rtlpriv->dm.cck_inch14) {
8c96fcf7
LF		 730 if (memcmp((void *)&temp_cck,
731 (void *)&cckswing_table_ch14[i][2],
732 4) == 0) {
733 cck_index_old = (u8) i;
734
735 RT_TRACE(rtlpriv, COMP_POWER_TRACKING,
736 DBG_LOUD,
f30d7507
JP		 737 "Initial reg0x%x = 0x%lx, cck_index=0x%x, ch 14 %d\n",
738 RCCK0_TXFILTER2, temp_cck,
739 cck_index_old,
740 rtlpriv->dm.cck_inch14);
8c96fcf7
LF		 741 break;
742 }
743 } else {
744 if (memcmp((void *)&temp_cck,
745 (void *)
746 &cckswing_table_ch1ch13[i][2],
747 4) == 0) {
748 cck_index_old = (u8) i;
749
750 RT_TRACE(rtlpriv, COMP_POWER_TRACKING,
751 DBG_LOUD,
f30d7507
JP		 752 "Initial reg0x%x = 0x%lx, cck_index=0x%x, ch14 %d\n",
753 RCCK0_TXFILTER2, temp_cck,
754 cck_index_old,
755 rtlpriv->dm.cck_inch14);
8c96fcf7
LF		 756 break;
757 }
758 }
759 }
760
761 if (!rtlpriv->dm.thermalvalue) {
762 rtlpriv->dm.thermalvalue =
763 rtlefuse->eeprom_thermalmeter;
764 rtlpriv->dm.thermalvalue_lck = thermalvalue;
765 rtlpriv->dm.thermalvalue_iqk = thermalvalue;
766 for (i = 0; i < rf; i++)
767 rtlpriv->dm.ofdm_index[i] = ofdm_index_old[i];
768 rtlpriv->dm.cck_index = cck_index_old;
769 }
770
771 delta = (thermalvalue > rtlpriv->dm.thermalvalue) ?
772 (thermalvalue - rtlpriv->dm.thermalvalue) :
773 (rtlpriv->dm.thermalvalue - thermalvalue);
774
775 delta_lck = (thermalvalue > rtlpriv->dm.thermalvalue_lck) ?
776 (thermalvalue - rtlpriv->dm.thermalvalue_lck) :
777 (rtlpriv->dm.thermalvalue_lck - thermalvalue);
778
779 delta_iqk = (thermalvalue > rtlpriv->dm.thermalvalue_iqk) ?
780 (thermalvalue - rtlpriv->dm.thermalvalue_iqk) :
781 (rtlpriv->dm.thermalvalue_iqk - thermalvalue);
782
783 RT_TRACE(rtlpriv, COMP_POWER_TRACKING, DBG_LOUD,
f30d7507 784 "Readback Thermal Meter = 0x%x pre thermal meter 0x%x eeprom_thermalmeter 0x%x delta 0x%x delta_lck 0x%x delta_iqk 0x%x\n",
8c96fcf7
LF		 785 thermalvalue, rtlpriv->dm.thermalvalue,
786 rtlefuse->eeprom_thermalmeter, delta, delta_lck,
f30d7507 787 delta_iqk);
8c96fcf7
LF		 788
789 if (delta_lck > 1) {
790 rtlpriv->dm.thermalvalue_lck = thermalvalue;
791 rtl92c_phy_lc_calibrate(hw);
792 }
793
794 if (delta > 0 && rtlpriv->dm.txpower_track_control) {
795 if (thermalvalue > rtlpriv->dm.thermalvalue) {
796 for (i = 0; i < rf; i++)
797 rtlpriv->dm.ofdm_index[i] -= delta;
798 rtlpriv->dm.cck_index -= delta;
799 } else {
800 for (i = 0; i < rf; i++)
801 rtlpriv->dm.ofdm_index[i] += delta;
802 rtlpriv->dm.cck_index += delta;
803 }
804
805 if (is2t) {
806 RT_TRACE(rtlpriv, COMP_POWER_TRACKING, DBG_LOUD,
f30d7507
JP		 807 "temp OFDM_A_index=0x%x, OFDM_B_index=0x%x, cck_index=0x%x\n",
808 rtlpriv->dm.ofdm_index[0],
809 rtlpriv->dm.ofdm_index[1],
810 rtlpriv->dm.cck_index);
8c96fcf7
LF		 811 } else {
812 RT_TRACE(rtlpriv, COMP_POWER_TRACKING, DBG_LOUD,
f30d7507
JP		 813 "temp OFDM_A_index=0x%x, cck_index=0x%x\n",
814 rtlpriv->dm.ofdm_index[0],
815 rtlpriv->dm.cck_index);
8c96fcf7
LF		 816 }
817
818 if (thermalvalue > rtlefuse->eeprom_thermalmeter) {
819 for (i = 0; i < rf; i++)
820 ofdm_index[i] =
821 rtlpriv->dm.ofdm_index[i]
822 + 1;
823 cck_index = rtlpriv->dm.cck_index + 1;
824 } else {
825 for (i = 0; i < rf; i++)
826 ofdm_index[i] =
827 rtlpriv->dm.ofdm_index[i];
828 cck_index = rtlpriv->dm.cck_index;
829 }
830
831 for (i = 0; i < rf; i++) {
832 if (txpwr_level[i] >= 0 &&
833 txpwr_level[i] <= 26) {
834 if (thermalvalue >
835 rtlefuse->eeprom_thermalmeter) {
836 if (delta < 5)
837 ofdm_index[i] -= 1;
838
839 else
840 ofdm_index[i] -= 2;
841 } else if (delta > 5 && thermalvalue <
842 rtlefuse->
843 eeprom_thermalmeter) {
844 ofdm_index[i] += 1;
845 }
846 } else if (txpwr_level[i] >= 27 &&
847 txpwr_level[i] <= 32
848 && thermalvalue >
849 rtlefuse->eeprom_thermalmeter) {
850 if (delta < 5)
851 ofdm_index[i] -= 1;
852
853 else
854 ofdm_index[i] -= 2;
855 } else if (txpwr_level[i] >= 32 &&
856 txpwr_level[i] <= 38 &&
857 thermalvalue >
858 rtlefuse->eeprom_thermalmeter
859 && delta > 5) {
860 ofdm_index[i] -= 1;
861 }
862 }
863
864 if (txpwr_level[i] >= 0 && txpwr_level[i] <= 26) {
865 if (thermalvalue >
866 rtlefuse->eeprom_thermalmeter) {
867 if (delta < 5)
868 cck_index -= 1;
869
870 else
871 cck_index -= 2;
872 } else if (delta > 5 && thermalvalue <
873 rtlefuse->eeprom_thermalmeter) {
874 cck_index += 1;
875 }
876 } else if (txpwr_level[i] >= 27 &&
877 txpwr_level[i] <= 32 &&
878 thermalvalue >
879 rtlefuse->eeprom_thermalmeter) {
880 if (delta < 5)
881 cck_index -= 1;
882
883 else
884 cck_index -= 2;
885 } else if (txpwr_level[i] >= 32 &&
886 txpwr_level[i] <= 38 &&
887 thermalvalue > rtlefuse->eeprom_thermalmeter
888 && delta > 5) {
889 cck_index -= 1;
890 }
891
892 for (i = 0; i < rf; i++) {
893 if (ofdm_index[i] > OFDM_TABLE_SIZE - 1)
894 ofdm_index[i] = OFDM_TABLE_SIZE - 1;
895
896 else if (ofdm_index[i] < ofdm_min_index)
897 ofdm_index[i] = ofdm_min_index;
898 }
899
900 if (cck_index > CCK_TABLE_SIZE - 1)
901 cck_index = CCK_TABLE_SIZE - 1;
902 else if (cck_index < 0)
903 cck_index = 0;
904
905 if (is2t) {
906 RT_TRACE(rtlpriv, COMP_POWER_TRACKING, DBG_LOUD,
f30d7507
JP		 907 "new OFDM_A_index=0x%x, OFDM_B_index=0x%x, cck_index=0x%x\n",
908 ofdm_index[0], ofdm_index[1],
909 cck_index);
8c96fcf7
LF		 910 } else {
911 RT_TRACE(rtlpriv, COMP_POWER_TRACKING, DBG_LOUD,
f30d7507
JP		 912 "new OFDM_A_index=0x%x, cck_index=0x%x\n",
913 ofdm_index[0], cck_index);
8c96fcf7
LF		 914 }
915 }
916
917 if (rtlpriv->dm.txpower_track_control && delta != 0) {
918 ele_d =
919 (ofdmswing_table[ofdm_index[0]] & 0xFFC00000) >> 22;
920 val_x = rtlphy->reg_e94;
921 val_y = rtlphy->reg_e9c;
922
923 if (val_x != 0) {
924 if ((val_x & 0x00000200) != 0)
925 val_x = val_x | 0xFFFFFC00;
926 ele_a = ((val_x * ele_d) >> 8) & 0x000003FF;
927
928 if ((val_y & 0x00000200) != 0)
929 val_y = val_y | 0xFFFFFC00;
930 ele_c = ((val_y * ele_d) >> 8) & 0x000003FF;
931
932 value32 = (ele_d << 22) |
933 ((ele_c & 0x3F) << 16) | ele_a;
934
935 rtl_set_bbreg(hw, ROFDM0_XATXIQIMBALANCE,
936 MASKDWORD, value32);
937
938 value32 = (ele_c & 0x000003C0) >> 6;
939 rtl_set_bbreg(hw, ROFDM0_XCTXAFE, MASKH4BITS,
940 value32);
941
942 value32 = ((val_x * ele_d) >> 7) & 0x01;
943 rtl_set_bbreg(hw, ROFDM0_ECCATHRESHOLD,
944 BIT(31), value32);
945
946 value32 = ((val_y * ele_d) >> 7) & 0x01;
947 rtl_set_bbreg(hw, ROFDM0_ECCATHRESHOLD,
948 BIT(29), value32);
949 } else {
950 rtl_set_bbreg(hw, ROFDM0_XATXIQIMBALANCE,
951 MASKDWORD,
952 ofdmswing_table[ofdm_index[0]]);
953
954 rtl_set_bbreg(hw, ROFDM0_XCTXAFE, MASKH4BITS,
955 0x00);
956 rtl_set_bbreg(hw, ROFDM0_ECCATHRESHOLD,
957 BIT(31) | BIT(29), 0x00);
958 }
959
7ea47240 960 if (!rtlpriv->dm.cck_inch14) {
8c96fcf7
LF		 961 rtl_write_byte(rtlpriv, 0xa22,
962 cckswing_table_ch1ch13[cck_index]
963 [0]);
964 rtl_write_byte(rtlpriv, 0xa23,
965 cckswing_table_ch1ch13[cck_index]
966 [1]);
967 rtl_write_byte(rtlpriv, 0xa24,
968 cckswing_table_ch1ch13[cck_index]
969 [2]);
970 rtl_write_byte(rtlpriv, 0xa25,
971 cckswing_table_ch1ch13[cck_index]
972 [3]);
973 rtl_write_byte(rtlpriv, 0xa26,
974 cckswing_table_ch1ch13[cck_index]
975 [4]);
976 rtl_write_byte(rtlpriv, 0xa27,
977 cckswing_table_ch1ch13[cck_index]
978 [5]);
979 rtl_write_byte(rtlpriv, 0xa28,
980 cckswing_table_ch1ch13[cck_index]
981 [6]);
982 rtl_write_byte(rtlpriv, 0xa29,
983 cckswing_table_ch1ch13[cck_index]
984 [7]);
985 } else {
986 rtl_write_byte(rtlpriv, 0xa22,
987 cckswing_table_ch14[cck_index]
988 [0]);
989 rtl_write_byte(rtlpriv, 0xa23,
990 cckswing_table_ch14[cck_index]
991 [1]);
992 rtl_write_byte(rtlpriv, 0xa24,
993 cckswing_table_ch14[cck_index]
994 [2]);
995 rtl_write_byte(rtlpriv, 0xa25,
996 cckswing_table_ch14[cck_index]
997 [3]);
998 rtl_write_byte(rtlpriv, 0xa26,
999 cckswing_table_ch14[cck_index]
1000 [4]);
1001 rtl_write_byte(rtlpriv, 0xa27,
1002 cckswing_table_ch14[cck_index]
1003 [5]);
1004 rtl_write_byte(rtlpriv, 0xa28,
1005 cckswing_table_ch14[cck_index]
1006 [6]);
1007 rtl_write_byte(rtlpriv, 0xa29,
1008 cckswing_table_ch14[cck_index]
1009 [7]);
1010 }
1011
1012 if (is2t) {
1013 ele_d = (ofdmswing_table[ofdm_index[1]] &
1014 0xFFC00000) >> 22;
1015
1016 val_x = rtlphy->reg_eb4;
1017 val_y = rtlphy->reg_ebc;
1018
1019 if (val_x != 0) {
1020 if ((val_x & 0x00000200) != 0)
1021 val_x = val_x | 0xFFFFFC00;
1022 ele_a = ((val_x * ele_d) >> 8) &
1023 0x000003FF;
1024
1025 if ((val_y & 0x00000200) != 0)
1026 val_y = val_y | 0xFFFFFC00;
1027 ele_c = ((val_y * ele_d) >> 8) &
1028 0x00003FF;
1029
1030 value32 = (ele_d << 22) |
1031 ((ele_c & 0x3F) << 16) | ele_a;
1032 rtl_set_bbreg(hw,
1033 ROFDM0_XBTXIQIMBALANCE,
1034 MASKDWORD, value32);
1035
1036 value32 = (ele_c & 0x000003C0) >> 6;
1037 rtl_set_bbreg(hw, ROFDM0_XDTXAFE,
1038 MASKH4BITS, value32);
1039
1040 value32 = ((val_x * ele_d) >> 7) & 0x01;
1041 rtl_set_bbreg(hw, ROFDM0_ECCATHRESHOLD,
1042 BIT(27), value32);
1043
1044 value32 = ((val_y * ele_d) >> 7) & 0x01;
1045 rtl_set_bbreg(hw, ROFDM0_ECCATHRESHOLD,
1046 BIT(25), value32);
1047 } else {
1048 rtl_set_bbreg(hw,
1049 ROFDM0_XBTXIQIMBALANCE,
1050 MASKDWORD,
1051 ofdmswing_table[ofdm_index
1052 [1]]);
1053 rtl_set_bbreg(hw, ROFDM0_XDTXAFE,
1054 MASKH4BITS, 0x00);
1055 rtl_set_bbreg(hw, ROFDM0_ECCATHRESHOLD,
1056 BIT(27) | BIT(25), 0x00);
1057 }
1058
1059 }
1060 }
1061
1062 if (delta_iqk > 3) {
1063 rtlpriv->dm.thermalvalue_iqk = thermalvalue;
1064 rtl92c_phy_iq_calibrate(hw, false);
1065 }
1066
1067 if (rtlpriv->dm.txpower_track_control)
1068 rtlpriv->dm.thermalvalue = thermalvalue;
1069 }
1070
f30d7507 1071 RT_TRACE(rtlpriv, COMP_POWER_TRACKING, DBG_LOUD, "<===\n");
8c96fcf7
LF		 1072
1073}
1074
1075static void rtl92c_dm_initialize_txpower_tracking_thermalmeter(
1076 struct ieee80211_hw *hw)
1077{
1078 struct rtl_priv *rtlpriv = rtl_priv(hw);
1079
7ea47240 1080 rtlpriv->dm.txpower_tracking = true;
3dad618b 1081 rtlpriv->dm.txpower_trackinginit = false;
8c96fcf7
LF		 1082
1083 RT_TRACE(rtlpriv, COMP_POWER_TRACKING, DBG_LOUD,
f30d7507
JP		 1084 "pMgntInfo->txpower_tracking = %d\n",
1085 rtlpriv->dm.txpower_tracking);
8c96fcf7
LF		 1086}
1087
1088static void rtl92c_dm_initialize_txpower_tracking(struct ieee80211_hw *hw)
1089{
1090 rtl92c_dm_initialize_txpower_tracking_thermalmeter(hw);
1091}
1092
1093static void rtl92c_dm_txpower_tracking_directcall(struct ieee80211_hw *hw)
1094{
1095 rtl92c_dm_txpower_tracking_callback_thermalmeter(hw);
1096}
1097
1098static void rtl92c_dm_check_txpower_tracking_thermal_meter(
1099 struct ieee80211_hw *hw)
1100{
1101 struct rtl_priv *rtlpriv = rtl_priv(hw);
1102 static u8 tm_trigger;
1103
7ea47240 1104 if (!rtlpriv->dm.txpower_tracking)
8c96fcf7
LF		 1105 return;
1106
1107 if (!tm_trigger) {
1108 rtl_set_rfreg(hw, RF90_PATH_A, RF_T_METER, RFREG_OFFSET_MASK,
1109 0x60);
1110 RT_TRACE(rtlpriv, COMP_POWER_TRACKING, DBG_LOUD,
f30d7507 1111 "Trigger 92S Thermal Meter!!\n");
8c96fcf7
LF		 1112 tm_trigger = 1;
1113 return;
1114 } else {
1115 RT_TRACE(rtlpriv, COMP_POWER_TRACKING, DBG_LOUD,
f30d7507 1116 "Schedule TxPowerTracking direct call!!\n");
8c96fcf7
LF		 1117 rtl92c_dm_txpower_tracking_directcall(hw);
1118 tm_trigger = 0;
1119 }
1120}
1121
1122void rtl92c_dm_check_txpower_tracking(struct ieee80211_hw *hw)
1123{
1124 rtl92c_dm_check_txpower_tracking_thermal_meter(hw);
1125}
1472d3a8 1126EXPORT_SYMBOL(rtl92c_dm_check_txpower_tracking);
8c96fcf7
LF		 1127
1128void rtl92c_dm_init_rate_adaptive_mask(struct ieee80211_hw *hw)
1129{
1130 struct rtl_priv *rtlpriv = rtl_priv(hw);
1131 struct rate_adaptive *p_ra = &(rtlpriv->ra);
1132
1133 p_ra->ratr_state = DM_RATR_STA_INIT;
1134 p_ra->pre_ratr_state = DM_RATR_STA_INIT;
1135
1136 if (rtlpriv->dm.dm_type == DM_TYPE_BYDRIVER)
7ea47240 1137 rtlpriv->dm.useramask = true;
8c96fcf7 1138 else
7ea47240 1139 rtlpriv->dm.useramask = false;
8c96fcf7
LF		 1140
1141}
1472d3a8 1142EXPORT_SYMBOL(rtl92c_dm_init_rate_adaptive_mask);
8c96fcf7
LF		 1143
1144static void rtl92c_dm_refresh_rate_adaptive_mask(struct ieee80211_hw *hw)
1145{
1146 struct rtl_priv *rtlpriv = rtl_priv(hw);
1147 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
1148 struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
1149 struct rate_adaptive *p_ra = &(rtlpriv->ra);
1150 u32 low_rssithresh_for_ra, high_rssithresh_for_ra;
beb5bc40 1151 struct ieee80211_sta *sta = NULL;
8c96fcf7
LF		 1152
1153 if (is_hal_stop(rtlhal)) {
1154 RT_TRACE(rtlpriv, COMP_RATE, DBG_LOUD,
f30d7507 1155 "<---- driver is going to unload\n");
8c96fcf7
LF		 1156 return;
1157 }
1158
7ea47240 1159 if (!rtlpriv->dm.useramask) {
8c96fcf7 1160 RT_TRACE(rtlpriv, COMP_RATE, DBG_LOUD,
f30d7507 1161 "<---- driver does not control rate adaptive mask\n");
8c96fcf7
LF		 1162 return;
1163 }
1164
beb5bc40
C		 1165 if (mac->link_state == MAC80211_LINKED &&
1166 mac->opmode == NL80211_IFTYPE_STATION) {
8c96fcf7
LF		 1167 switch (p_ra->pre_ratr_state) {
1168 case DM_RATR_STA_HIGH:
1169 high_rssithresh_for_ra = 50;
1170 low_rssithresh_for_ra = 20;
1171 break;
1172 case DM_RATR_STA_MIDDLE:
1173 high_rssithresh_for_ra = 55;
1174 low_rssithresh_for_ra = 20;
1175 break;
1176 case DM_RATR_STA_LOW:
1177 high_rssithresh_for_ra = 50;
1178 low_rssithresh_for_ra = 25;
1179 break;
1180 default:
1181 high_rssithresh_for_ra = 50;
1182 low_rssithresh_for_ra = 20;
1183 break;
1184 }
1185
1186 if (rtlpriv->dm.undecorated_smoothed_pwdb >
1187 (long)high_rssithresh_for_ra)
1188 p_ra->ratr_state = DM_RATR_STA_HIGH;
1189 else if (rtlpriv->dm.undecorated_smoothed_pwdb >
1190 (long)low_rssithresh_for_ra)
1191 p_ra->ratr_state = DM_RATR_STA_MIDDLE;
1192 else
1193 p_ra->ratr_state = DM_RATR_STA_LOW;
1194
1195 if (p_ra->pre_ratr_state != p_ra->ratr_state) {
f30d7507
JP		 1196 RT_TRACE(rtlpriv, COMP_RATE, DBG_LOUD, "RSSI = %ld\n",
1197 rtlpriv->dm.undecorated_smoothed_pwdb);
8c96fcf7 1198 RT_TRACE(rtlpriv, COMP_RATE, DBG_LOUD,
f30d7507 1199 "RSSI_LEVEL = %d\n", p_ra->ratr_state);
8c96fcf7 1200 RT_TRACE(rtlpriv, COMP_RATE, DBG_LOUD,
f30d7507
JP		 1201 "PreState = %d, CurState = %d\n",
1202 p_ra->pre_ratr_state, p_ra->ratr_state);
8c96fcf7 1203
beb5bc40
C		 1204 rcu_read_lock();
1205 sta = ieee80211_find_sta(mac->vif, mac->bssid);
1206 rtlpriv->cfg->ops->update_rate_tbl(hw, sta,
8c96fcf7
LF		 1207 p_ra->ratr_state);
1208
1209 p_ra->pre_ratr_state = p_ra->ratr_state;
beb5bc40 1210 rcu_read_unlock();
8c96fcf7
LF		 1211 }
1212 }
1213}
1214
1215static void rtl92c_dm_init_dynamic_bb_powersaving(struct ieee80211_hw *hw)
1216{
1217 dm_pstable.pre_ccastate = CCA_MAX;
1218 dm_pstable.cur_ccasate = CCA_MAX;
1219 dm_pstable.pre_rfstate = RF_MAX;
1220 dm_pstable.cur_rfstate = RF_MAX;
1221 dm_pstable.rssi_val_min = 0;
1222}
1223
8c96fcf7
LF		 1224void rtl92c_dm_rf_saving(struct ieee80211_hw *hw, u8 bforce_in_normal)
1225{
1226 static u8 initialize;
1227 static u32 reg_874, reg_c70, reg_85c, reg_a74;
1228
1229 if (initialize == 0) {
1230 reg_874 = (rtl_get_bbreg(hw, RFPGA0_XCD_RFINTERFACESW,
1231 MASKDWORD) & 0x1CC000) >> 14;
1232
1233 reg_c70 = (rtl_get_bbreg(hw, ROFDM0_AGCPARAMETER1,
1234 MASKDWORD) & BIT(3)) >> 3;
1235
1236 reg_85c = (rtl_get_bbreg(hw, RFPGA0_XCD_SWITCHCONTROL,
1237 MASKDWORD) & 0xFF000000) >> 24;
1238
1239 reg_a74 = (rtl_get_bbreg(hw, 0xa74, MASKDWORD) & 0xF000) >> 12;
1240
1241 initialize = 1;
1242 }
1243
1244 if (!bforce_in_normal) {
1245 if (dm_pstable.rssi_val_min != 0) {
1246 if (dm_pstable.pre_rfstate == RF_NORMAL) {
1247 if (dm_pstable.rssi_val_min >= 30)
1248 dm_pstable.cur_rfstate = RF_SAVE;
1249 else
1250 dm_pstable.cur_rfstate = RF_NORMAL;
1251 } else {
1252 if (dm_pstable.rssi_val_min <= 25)
1253 dm_pstable.cur_rfstate = RF_NORMAL;
1254 else
1255 dm_pstable.cur_rfstate = RF_SAVE;
1256 }
1257 } else {
1258 dm_pstable.cur_rfstate = RF_MAX;
1259 }
1260 } else {
1261 dm_pstable.cur_rfstate = RF_NORMAL;
1262 }
1263
1264 if (dm_pstable.pre_rfstate != dm_pstable.cur_rfstate) {
1265 if (dm_pstable.cur_rfstate == RF_SAVE) {
1266 rtl_set_bbreg(hw, RFPGA0_XCD_RFINTERFACESW,
1267 0x1C0000, 0x2);
1268 rtl_set_bbreg(hw, ROFDM0_AGCPARAMETER1, BIT(3), 0);
1269 rtl_set_bbreg(hw, RFPGA0_XCD_SWITCHCONTROL,
1270 0xFF000000, 0x63);
1271 rtl_set_bbreg(hw, RFPGA0_XCD_RFINTERFACESW,
1272 0xC000, 0x2);
1273 rtl_set_bbreg(hw, 0xa74, 0xF000, 0x3);
1274 rtl_set_bbreg(hw, 0x818, BIT(28), 0x0);
1275 rtl_set_bbreg(hw, 0x818, BIT(28), 0x1);
1276 } else {
1277 rtl_set_bbreg(hw, RFPGA0_XCD_RFINTERFACESW,
1278 0x1CC000, reg_874);
1279 rtl_set_bbreg(hw, ROFDM0_AGCPARAMETER1, BIT(3),
1280 reg_c70);
1281 rtl_set_bbreg(hw, RFPGA0_XCD_SWITCHCONTROL, 0xFF000000,
1282 reg_85c);
1283 rtl_set_bbreg(hw, 0xa74, 0xF000, reg_a74);
1284 rtl_set_bbreg(hw, 0x818, BIT(28), 0x0);
1285 }
1286
1287 dm_pstable.pre_rfstate = dm_pstable.cur_rfstate;
1288 }
1289}
1472d3a8 1290EXPORT_SYMBOL(rtl92c_dm_rf_saving);
8c96fcf7
LF		 1291
1292static void rtl92c_dm_dynamic_bb_powersaving(struct ieee80211_hw *hw)
1293{
1294 struct rtl_priv *rtlpriv = rtl_priv(hw);
1295 struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
1296 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
1297
1298 if (((mac->link_state == MAC80211_NOLINK)) &&
1299 (rtlpriv->dm.entry_min_undecoratedsmoothed_pwdb == 0)) {
1300 dm_pstable.rssi_val_min = 0;
f30d7507 1301 RT_TRACE(rtlpriv, DBG_LOUD, DBG_LOUD, "Not connected to any\n");
8c96fcf7
LF		 1302 }
1303
1304 if (mac->link_state == MAC80211_LINKED) {
1305 if (mac->opmode == NL80211_IFTYPE_ADHOC) {
1306 dm_pstable.rssi_val_min =
1307 rtlpriv->dm.entry_min_undecoratedsmoothed_pwdb;
1308 RT_TRACE(rtlpriv, DBG_LOUD, DBG_LOUD,
f30d7507
JP		 1309 "AP Client PWDB = 0x%lx\n",
1310 dm_pstable.rssi_val_min);
8c96fcf7
LF		 1311 } else {
1312 dm_pstable.rssi_val_min =
1313 rtlpriv->dm.undecorated_smoothed_pwdb;
1314 RT_TRACE(rtlpriv, DBG_LOUD, DBG_LOUD,
f30d7507
JP		 1315 "STA Default Port PWDB = 0x%lx\n",
1316 dm_pstable.rssi_val_min);
8c96fcf7
LF		 1317 }
1318 } else {
1319 dm_pstable.rssi_val_min =
1320 rtlpriv->dm.entry_min_undecoratedsmoothed_pwdb;
1321
1322 RT_TRACE(rtlpriv, DBG_LOUD, DBG_LOUD,
f30d7507
JP		 1323 "AP Ext Port PWDB = 0x%lx\n",
1324 dm_pstable.rssi_val_min);
8c96fcf7
LF		 1325 }
1326
1327 if (IS_92C_SERIAL(rtlhal->version))
beb5bc40
C		 1328 ;/* rtl92c_dm_1r_cca(hw); */
1329 else
1330 rtl92c_dm_rf_saving(hw, false);
8c96fcf7
LF		 1331}
1332
1333void rtl92c_dm_init(struct ieee80211_hw *hw)
1334{
1335 struct rtl_priv *rtlpriv = rtl_priv(hw);
1336
1337 rtlpriv->dm.dm_type = DM_TYPE_BYDRIVER;
1338 rtl92c_dm_diginit(hw);
1339 rtl92c_dm_init_dynamic_txpower(hw);
1340 rtl92c_dm_init_edca_turbo(hw);
1341 rtl92c_dm_init_rate_adaptive_mask(hw);
1342 rtl92c_dm_initialize_txpower_tracking(hw);
1343 rtl92c_dm_init_dynamic_bb_powersaving(hw);
1344}
1472d3a8 1345EXPORT_SYMBOL(rtl92c_dm_init);
8c96fcf7 1346
beb5bc40
C		 1347void rtl92c_dm_dynamic_txpower(struct ieee80211_hw *hw)
1348{
1349 struct rtl_priv *rtlpriv = rtl_priv(hw);
1350 struct rtl_phy *rtlphy = &(rtlpriv->phy);
1351 struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
1352 long undecorated_smoothed_pwdb;
1353
1354 if (!rtlpriv->dm.dynamic_txpower_enable)
1355 return;
1356
1357 if (rtlpriv->dm.dm_flag & HAL_DM_HIPWR_DISABLE) {
1358 rtlpriv->dm.dynamic_txhighpower_lvl = TXHIGHPWRLEVEL_NORMAL;
1359 return;
1360 }
1361
1362 if ((mac->link_state < MAC80211_LINKED) &&
1363 (rtlpriv->dm.entry_min_undecoratedsmoothed_pwdb == 0)) {
1364 RT_TRACE(rtlpriv, COMP_POWER, DBG_TRACE,
f30d7507 1365 "Not connected to any\n");
beb5bc40
C		 1366
1367 rtlpriv->dm.dynamic_txhighpower_lvl = TXHIGHPWRLEVEL_NORMAL;
1368
1369 rtlpriv->dm.last_dtp_lvl = TXHIGHPWRLEVEL_NORMAL;
1370 return;
1371 }
1372
1373 if (mac->link_state >= MAC80211_LINKED) {
1374 if (mac->opmode == NL80211_IFTYPE_ADHOC) {
1375 undecorated_smoothed_pwdb =
1376 rtlpriv->dm.entry_min_undecoratedsmoothed_pwdb;
1377 RT_TRACE(rtlpriv, COMP_POWER, DBG_LOUD,
f30d7507
JP		 1378 "AP Client PWDB = 0x%lx\n",
1379 undecorated_smoothed_pwdb);
beb5bc40
C		 1380 } else {
1381 undecorated_smoothed_pwdb =
1382 rtlpriv->dm.undecorated_smoothed_pwdb;
1383 RT_TRACE(rtlpriv, COMP_POWER, DBG_LOUD,
f30d7507
JP		 1384 "STA Default Port PWDB = 0x%lx\n",
1385 undecorated_smoothed_pwdb);
beb5bc40
C		 1386 }
1387 } else {
1388 undecorated_smoothed_pwdb =
1389 rtlpriv->dm.entry_min_undecoratedsmoothed_pwdb;
1390
1391 RT_TRACE(rtlpriv, COMP_POWER, DBG_LOUD,
f30d7507
JP		 1392 "AP Ext Port PWDB = 0x%lx\n",
1393 undecorated_smoothed_pwdb);
beb5bc40
C		 1394 }
1395
1396 if (undecorated_smoothed_pwdb >= TX_POWER_NEAR_FIELD_THRESH_LVL2) {
1397 rtlpriv->dm.dynamic_txhighpower_lvl = TXHIGHPWRLEVEL_LEVEL1;
1398 RT_TRACE(rtlpriv, COMP_POWER, DBG_LOUD,
f30d7507 1399 "TXHIGHPWRLEVEL_LEVEL1 (TxPwr=0x0)\n");
beb5bc40
C		 1400 } else if ((undecorated_smoothed_pwdb <
1401 (TX_POWER_NEAR_FIELD_THRESH_LVL2 - 3)) &&
1402 (undecorated_smoothed_pwdb >=
1403 TX_POWER_NEAR_FIELD_THRESH_LVL1)) {
1404
1405 rtlpriv->dm.dynamic_txhighpower_lvl = TXHIGHPWRLEVEL_LEVEL1;
1406 RT_TRACE(rtlpriv, COMP_POWER, DBG_LOUD,
f30d7507 1407 "TXHIGHPWRLEVEL_LEVEL1 (TxPwr=0x10)\n");
beb5bc40
C		 1408 } else if (undecorated_smoothed_pwdb <
1409 (TX_POWER_NEAR_FIELD_THRESH_LVL1 - 5)) {
1410 rtlpriv->dm.dynamic_txhighpower_lvl = TXHIGHPWRLEVEL_NORMAL;
1411 RT_TRACE(rtlpriv, COMP_POWER, DBG_LOUD,
f30d7507 1412 "TXHIGHPWRLEVEL_NORMAL\n");
beb5bc40
C		 1413 }
1414
1415 if ((rtlpriv->dm.dynamic_txhighpower_lvl != rtlpriv->dm.last_dtp_lvl)) {
1416 RT_TRACE(rtlpriv, COMP_POWER, DBG_LOUD,
f30d7507
JP		 1417 "PHY_SetTxPowerLevel8192S() Channel = %d\n",
1418 rtlphy->current_channel);
beb5bc40
C		 1419 rtl92c_phy_set_txpower_level(hw, rtlphy->current_channel);
1420 }
1421
1422 rtlpriv->dm.last_dtp_lvl = rtlpriv->dm.dynamic_txhighpower_lvl;
1423}
1424
8c96fcf7
LF		 1425void rtl92c_dm_watchdog(struct ieee80211_hw *hw)
1426{
1427 struct rtl_priv *rtlpriv = rtl_priv(hw);
1428 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
7ea47240
LF		 1429 bool fw_current_inpsmode = false;
1430 bool fw_ps_awake = true;
8c96fcf7
LF		 1431
1432 rtlpriv->cfg->ops->get_hw_reg(hw, HW_VAR_FW_PSMODE_STATUS,
7ea47240 1433 (u8 *) (&fw_current_inpsmode));
8c96fcf7 1434 rtlpriv->cfg->ops->get_hw_reg(hw, HW_VAR_FWLPS_RF_ON,
7ea47240 1435 (u8 *) (&fw_ps_awake));
8c96fcf7 1436
7ea47240
LF		 1437 if ((ppsc->rfpwr_state == ERFON) && ((!fw_current_inpsmode) &&
1438 fw_ps_awake)
8c96fcf7
LF		 1439 && (!ppsc->rfchange_inprogress)) {
1440 rtl92c_dm_pwdb_monitor(hw);
1441 rtl92c_dm_dig(hw);
1442 rtl92c_dm_false_alarm_counter_statistics(hw);
1443 rtl92c_dm_dynamic_bb_powersaving(hw);
beb5bc40 1444 rtl92c_dm_dynamic_txpower(hw);
8c96fcf7
LF		 1445 rtl92c_dm_check_txpower_tracking(hw);
1446 rtl92c_dm_refresh_rate_adaptive_mask(hw);
beb5bc40 1447 rtl92c_dm_bt_coexist(hw);
8c96fcf7
LF		 1448 rtl92c_dm_check_edca_turbo(hw);
1449 }
1450}
1472d3a8 1451EXPORT_SYMBOL(rtl92c_dm_watchdog);
beb5bc40 1452
2b8359f8 1453u8 rtl92c_bt_rssi_state_change(struct ieee80211_hw *hw)
beb5bc40
C		 1454{
1455 struct rtl_priv *rtlpriv = rtl_priv(hw);
1456 struct rtl_pci_priv *rtlpcipriv = rtl_pcipriv(hw);
1457 long undecorated_smoothed_pwdb;
1458 u8 curr_bt_rssi_state = 0x00;
1459
1460 if (rtlpriv->mac80211.link_state == MAC80211_LINKED) {
1461 undecorated_smoothed_pwdb =
1462 GET_UNDECORATED_AVERAGE_RSSI(rtlpriv);
1463 } else {
1464 if (rtlpriv->dm.entry_min_undecoratedsmoothed_pwdb == 0)
1465 undecorated_smoothed_pwdb = 100;
1466 else
1467 undecorated_smoothed_pwdb =
1468 rtlpriv->dm.entry_min_undecoratedsmoothed_pwdb;
1469 }
1470
1471 /* Check RSSI to determine HighPower/NormalPower state for
1472 * BT coexistence. */
1473 if (undecorated_smoothed_pwdb >= 67)
1474 curr_bt_rssi_state &= (~BT_RSSI_STATE_NORMAL_POWER);
1475 else if (undecorated_smoothed_pwdb < 62)
1476 curr_bt_rssi_state |= BT_RSSI_STATE_NORMAL_POWER;
1477
1478 /* Check RSSI to determine AMPDU setting for BT coexistence. */
1479 if (undecorated_smoothed_pwdb >= 40)
1480 curr_bt_rssi_state &= (~BT_RSSI_STATE_AMDPU_OFF);
1481 else if (undecorated_smoothed_pwdb <= 32)
1482 curr_bt_rssi_state |= BT_RSSI_STATE_AMDPU_OFF;
1483
1484 /* Marked RSSI state. It will be used to determine BT coexistence
1485 * setting later. */
1486 if (undecorated_smoothed_pwdb < 35)
1487 curr_bt_rssi_state |= BT_RSSI_STATE_SPECIAL_LOW;
1488 else
1489 curr_bt_rssi_state &= (~BT_RSSI_STATE_SPECIAL_LOW);
1490
1491 /* Set Tx Power according to BT status. */
1492 if (undecorated_smoothed_pwdb >= 30)
1493 curr_bt_rssi_state |= BT_RSSI_STATE_TXPOWER_LOW;
1494 else if (undecorated_smoothed_pwdb < 25)
1495 curr_bt_rssi_state &= (~BT_RSSI_STATE_TXPOWER_LOW);
1496
1497 /* Check BT state related to BT_Idle in B/G mode. */
1498 if (undecorated_smoothed_pwdb < 15)
1499 curr_bt_rssi_state |= BT_RSSI_STATE_BG_EDCA_LOW;
1500 else
1501 curr_bt_rssi_state &= (~BT_RSSI_STATE_BG_EDCA_LOW);
1502
1503 if (curr_bt_rssi_state != rtlpcipriv->bt_coexist.bt_rssi_state) {
1504 rtlpcipriv->bt_coexist.bt_rssi_state = curr_bt_rssi_state;
1505 return true;
1506 } else {
1507 return false;
1508 }
1509}
2b8359f8 1510EXPORT_SYMBOL(rtl92c_bt_rssi_state_change);
beb5bc40
C		 1511
1512static bool rtl92c_bt_state_change(struct ieee80211_hw *hw)
1513{
1514 struct rtl_priv *rtlpriv = rtl_priv(hw);
1515 struct rtl_pci_priv *rtlpcipriv = rtl_pcipriv(hw);
1516
1517 u32 polling, ratio_tx, ratio_pri;
1518 u32 bt_tx, bt_pri;
1519 u8 bt_state;
1520 u8 cur_service_type;
1521
1522 if (rtlpriv->mac80211.link_state < MAC80211_LINKED)
1523 return false;
1524
1525 bt_state = rtl_read_byte(rtlpriv, 0x4fd);
1526 bt_tx = rtl_read_dword(rtlpriv, 0x488);
1527 bt_tx = bt_tx & 0x00ffffff;
1528 bt_pri = rtl_read_dword(rtlpriv, 0x48c);
1529 bt_pri = bt_pri & 0x00ffffff;
1530 polling = rtl_read_dword(rtlpriv, 0x490);
1531
1532 if (bt_tx == 0xffffffff && bt_pri == 0xffffffff &&
1533 polling == 0xffffffff && bt_state == 0xff)
1534 return false;
1535
1536 bt_state &= BIT_OFFSET_LEN_MASK_32(0, 1);
1537 if (bt_state != rtlpcipriv->bt_coexist.bt_cur_state) {
1538 rtlpcipriv->bt_coexist.bt_cur_state = bt_state;
1539
1540 if (rtlpcipriv->bt_coexist.reg_bt_sco == 3) {
1541 rtlpcipriv->bt_coexist.bt_service = BT_IDLE;
1542
1543 bt_state = bt_state |
1544 ((rtlpcipriv->bt_coexist.bt_ant_isolation == 1) ?
1545 0 : BIT_OFFSET_LEN_MASK_32(1, 1)) |
1546 BIT_OFFSET_LEN_MASK_32(2, 1);
1547 rtl_write_byte(rtlpriv, 0x4fd, bt_state);
1548 }
1549 return true;
1550 }
1551
1552 ratio_tx = bt_tx * 1000 / polling;
1553 ratio_pri = bt_pri * 1000 / polling;
1554 rtlpcipriv->bt_coexist.ratio_tx = ratio_tx;
1555 rtlpcipriv->bt_coexist.ratio_pri = ratio_pri;
1556
1557 if (bt_state && rtlpcipriv->bt_coexist.reg_bt_sco == 3) {
1558
1559 if ((ratio_tx < 30) && (ratio_pri < 30))
1560 cur_service_type = BT_IDLE;
1561 else if ((ratio_pri > 110) && (ratio_pri < 250))
1562 cur_service_type = BT_SCO;
1563 else if ((ratio_tx >= 200) && (ratio_pri >= 200))
1564 cur_service_type = BT_BUSY;
1565 else if ((ratio_tx >= 350) && (ratio_tx < 500))
1566 cur_service_type = BT_OTHERBUSY;
1567 else if (ratio_tx >= 500)
1568 cur_service_type = BT_PAN;
1569 else
1570 cur_service_type = BT_OTHER_ACTION;
1571
1572 if (cur_service_type != rtlpcipriv->bt_coexist.bt_service) {
1573 rtlpcipriv->bt_coexist.bt_service = cur_service_type;
1574 bt_state = bt_state |
1575 ((rtlpcipriv->bt_coexist.bt_ant_isolation == 1) ?
1576 0 : BIT_OFFSET_LEN_MASK_32(1, 1)) |
1577 ((rtlpcipriv->bt_coexist.bt_service != BT_IDLE) ?
1578 0 : BIT_OFFSET_LEN_MASK_32(2, 1));
1579
1580 /* Add interrupt migration when bt is not ini
1581 * idle state (no traffic). */
1582 if (rtlpcipriv->bt_coexist.bt_service != BT_IDLE) {
1583 rtl_write_word(rtlpriv, 0x504, 0x0ccc);
1584 rtl_write_byte(rtlpriv, 0x506, 0x54);
1585 rtl_write_byte(rtlpriv, 0x507, 0x54);
1586 } else {
1587 rtl_write_byte(rtlpriv, 0x506, 0x00);
1588 rtl_write_byte(rtlpriv, 0x507, 0x00);
1589 }
1590
1591 rtl_write_byte(rtlpriv, 0x4fd, bt_state);
1592 return true;
1593 }
1594 }
1595
1596 return false;
1597
1598}
1599
1600static bool rtl92c_bt_wifi_connect_change(struct ieee80211_hw *hw)
1601{
1602 struct rtl_priv *rtlpriv = rtl_priv(hw);
1603 static bool media_connect;
1604
1605 if (rtlpriv->mac80211.link_state < MAC80211_LINKED) {
1606 media_connect = false;
1607 } else {
1608 if (!media_connect) {
1609 media_connect = true;
1610 return true;
1611 }
1612 media_connect = true;
1613 }
1614
1615 return false;
1616}
1617
1618static void rtl92c_bt_set_normal(struct ieee80211_hw *hw)
1619{
1620 struct rtl_priv *rtlpriv = rtl_priv(hw);
1621 struct rtl_pci_priv *rtlpcipriv = rtl_pcipriv(hw);
1622
1623
1624 if (rtlpcipriv->bt_coexist.bt_service == BT_OTHERBUSY) {
1625 rtlpcipriv->bt_coexist.bt_edca_ul = 0x5ea72b;
1626 rtlpcipriv->bt_coexist.bt_edca_dl = 0x5ea72b;
1627 } else if (rtlpcipriv->bt_coexist.bt_service == BT_BUSY) {
1628 rtlpcipriv->bt_coexist.bt_edca_ul = 0x5eb82f;
1629 rtlpcipriv->bt_coexist.bt_edca_dl = 0x5eb82f;
1630 } else if (rtlpcipriv->bt_coexist.bt_service == BT_SCO) {
1631 if (rtlpcipriv->bt_coexist.ratio_tx > 160) {
1632 rtlpcipriv->bt_coexist.bt_edca_ul = 0x5ea72f;
1633 rtlpcipriv->bt_coexist.bt_edca_dl = 0x5ea72f;
1634 } else {
1635 rtlpcipriv->bt_coexist.bt_edca_ul = 0x5ea32b;
1636 rtlpcipriv->bt_coexist.bt_edca_dl = 0x5ea42b;
1637 }
1638 } else {
1639 rtlpcipriv->bt_coexist.bt_edca_ul = 0;
1640 rtlpcipriv->bt_coexist.bt_edca_dl = 0;
1641 }
1642
1643 if ((rtlpcipriv->bt_coexist.bt_service != BT_IDLE) &&
1644 (rtlpriv->mac80211.mode == WIRELESS_MODE_G ||
1645 (rtlpriv->mac80211.mode == (WIRELESS_MODE_G | WIRELESS_MODE_B))) &&
1646 (rtlpcipriv->bt_coexist.bt_rssi_state &
1647 BT_RSSI_STATE_BG_EDCA_LOW)) {
1648 rtlpcipriv->bt_coexist.bt_edca_ul = 0x5eb82b;
1649 rtlpcipriv->bt_coexist.bt_edca_dl = 0x5eb82b;
1650 }
1651}
1652
1653static void rtl92c_bt_ant_isolation(struct ieee80211_hw *hw)
1654{
1655 struct rtl_priv *rtlpriv = rtl_priv(hw);
1656 struct rtl_pci_priv *rtlpcipriv = rtl_pcipriv(hw);
1657
1658
1659 /* Only enable HW BT coexist when BT in "Busy" state. */
1660 if (rtlpriv->mac80211.vendor == PEER_CISCO &&
1661 rtlpcipriv->bt_coexist.bt_service == BT_OTHER_ACTION) {
1662 rtl_write_byte(rtlpriv, REG_GPIO_MUXCFG, 0xa0);
1663 } else {
1664 if ((rtlpcipriv->bt_coexist.bt_service == BT_BUSY) &&
1665 (rtlpcipriv->bt_coexist.bt_rssi_state &
1666 BT_RSSI_STATE_NORMAL_POWER)) {
1667 rtl_write_byte(rtlpriv, REG_GPIO_MUXCFG, 0xa0);
1668 } else if ((rtlpcipriv->bt_coexist.bt_service ==
1669 BT_OTHER_ACTION) && (rtlpriv->mac80211.mode <
1670 WIRELESS_MODE_N_24G) &&
1671 (rtlpcipriv->bt_coexist.bt_rssi_state &
1672 BT_RSSI_STATE_SPECIAL_LOW)) {
1673 rtl_write_byte(rtlpriv, REG_GPIO_MUXCFG, 0xa0);
1674 } else if (rtlpcipriv->bt_coexist.bt_service == BT_PAN) {
1675 rtl_write_byte(rtlpriv, REG_GPIO_MUXCFG, 0x00);
1676 } else {
1677 rtl_write_byte(rtlpriv, REG_GPIO_MUXCFG, 0x00);
1678 }
1679 }
1680
1681 if (rtlpcipriv->bt_coexist.bt_service == BT_PAN)
1682 rtl_write_dword(rtlpriv, REG_GPIO_PIN_CTRL, 0x10100);
1683 else
1684 rtl_write_dword(rtlpriv, REG_GPIO_PIN_CTRL, 0x0);
1685
1686 if (rtlpcipriv->bt_coexist.bt_rssi_state &
1687 BT_RSSI_STATE_NORMAL_POWER) {
1688 rtl92c_bt_set_normal(hw);
1689 } else {
1690 rtlpcipriv->bt_coexist.bt_edca_ul = 0;
1691 rtlpcipriv->bt_coexist.bt_edca_dl = 0;
1692 }
1693
1694 if (rtlpcipriv->bt_coexist.bt_service != BT_IDLE) {
1695 rtlpriv->cfg->ops->set_rfreg(hw,
1696 RF90_PATH_A,
1697 0x1e,
1698 0xf0, 0xf);
1699 } else {
1700 rtlpriv->cfg->ops->set_rfreg(hw,
1701 RF90_PATH_A, 0x1e, 0xf0,
1702 rtlpcipriv->bt_coexist.bt_rfreg_origin_1e);
1703 }
1704
1705 if (!rtlpriv->dm.dynamic_txpower_enable) {
1706 if (rtlpcipriv->bt_coexist.bt_service != BT_IDLE) {
1707 if (rtlpcipriv->bt_coexist.bt_rssi_state &
1708 BT_RSSI_STATE_TXPOWER_LOW) {
1709 rtlpriv->dm.dynamic_txhighpower_lvl =
1710 TXHIGHPWRLEVEL_BT2;
1711 } else {
1712 rtlpriv->dm.dynamic_txhighpower_lvl =
1713 TXHIGHPWRLEVEL_BT1;
1714 }
1715 } else {
1716 rtlpriv->dm.dynamic_txhighpower_lvl =
1717 TXHIGHPWRLEVEL_NORMAL;
1718 }
1719 rtl92c_phy_set_txpower_level(hw,
1720 rtlpriv->phy.current_channel);
1721 }
1722}
1723
1724static void rtl92c_check_bt_change(struct ieee80211_hw *hw)
1725{
1726 struct rtl_priv *rtlpriv = rtl_priv(hw);
1727 struct rtl_pci_priv *rtlpcipriv = rtl_pcipriv(hw);
1728
1729 if (rtlpcipriv->bt_coexist.bt_cur_state) {
1730 if (rtlpcipriv->bt_coexist.bt_ant_isolation)
1731 rtl92c_bt_ant_isolation(hw);
1732 } else {
1733 rtl_write_byte(rtlpriv, REG_GPIO_MUXCFG, 0x00);
1734 rtlpriv->cfg->ops->set_rfreg(hw, RF90_PATH_A, 0x1e, 0xf0,
1735 rtlpcipriv->bt_coexist.bt_rfreg_origin_1e);
1736
1737 rtlpcipriv->bt_coexist.bt_edca_ul = 0;
1738 rtlpcipriv->bt_coexist.bt_edca_dl = 0;
1739 }
1740}
1741
1742void rtl92c_dm_bt_coexist(struct ieee80211_hw *hw)
1743{
1744 struct rtl_pci_priv *rtlpcipriv = rtl_pcipriv(hw);
1745
1746 bool wifi_connect_change;
1747 bool bt_state_change;
1748 bool rssi_state_change;
1749
1750 if ((rtlpcipriv->bt_coexist.bt_coexistence) &&
1751 (rtlpcipriv->bt_coexist.bt_coexist_type == BT_CSR_BC4)) {
1752
1753 wifi_connect_change = rtl92c_bt_wifi_connect_change(hw);
1754 bt_state_change = rtl92c_bt_state_change(hw);
1755 rssi_state_change = rtl92c_bt_rssi_state_change(hw);
1756
1757 if (wifi_connect_change || bt_state_change || rssi_state_change)
1758 rtl92c_check_bt_change(hw);
1759 }
1760}
2b8359f8 1761EXPORT_SYMBOL(rtl92c_dm_bt_coexist);
Linux kernel - Deliverables
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