[deliverable/linux.git] / drivers / net / wireless / rtlwifi / rtl8192ce / def.h

/******************************************************************************
 *
 * Copyright(c) 2009-2012  Realtek Corporation.
 *
 * This program is free software; you can redistribute it and/or modify it
 * under the terms of version 2 of the GNU General Public License as
 * published by the Free Software Foundation.
 *
 * This program is distributed in the hope that it will be useful, but WITHOUT
 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
 * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
 * more details.
 *
 * You should have received a copy of the GNU General Public License along with
 * this program; if not, write to the Free Software Foundation, Inc.,
 * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
 *
 * The full GNU General Public License is included in this distribution in the
 * file called LICENSE.
 *
 * Contact Information:
 * wlanfae <wlanfae@realtek.com>
 * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
 * Hsinchu 300, Taiwan.
 *
 * Larry Finger <Larry.Finger@lwfinger.net>
 *
 *****************************************************************************/

#ifndef __RTL92C_DEF_H__
#define __RTL92C_DEF_H__

#define HAL_RETRY_LIMIT_INFRA				48
#define HAL_RETRY_LIMIT_AP_ADHOC			7

#define	PHY_RSSI_SLID_WIN_MAX				100
#define	PHY_LINKQUALITY_SLID_WIN_MAX			20
#define	PHY_BEACON_RSSI_SLID_WIN_MAX			10

#define RESET_DELAY_8185				20

#define RT_IBSS_INT_MASKS	(IMR_BCNINT | IMR_TBDOK | IMR_TBDER)
#define RT_AC_INT_MASKS		(IMR_VIDOK | IMR_VODOK | IMR_BEDOK|IMR_BKDOK)

#define NUM_OF_FIRMWARE_QUEUE				10
#define NUM_OF_PAGES_IN_FW				0x100
#define NUM_OF_PAGE_IN_FW_QUEUE_BK			0x07
#define NUM_OF_PAGE_IN_FW_QUEUE_BE			0x07
#define NUM_OF_PAGE_IN_FW_QUEUE_VI			0x07
#define NUM_OF_PAGE_IN_FW_QUEUE_VO			0x07
#define NUM_OF_PAGE_IN_FW_QUEUE_HCCA			0x0
#define NUM_OF_PAGE_IN_FW_QUEUE_CMD			0x0
#define NUM_OF_PAGE_IN_FW_QUEUE_MGNT			0x02
#define NUM_OF_PAGE_IN_FW_QUEUE_HIGH			0x02
#define NUM_OF_PAGE_IN_FW_QUEUE_BCN			0x2
#define NUM_OF_PAGE_IN_FW_QUEUE_PUB			0xA1

#define NUM_OF_PAGE_IN_FW_QUEUE_BK_DTM			0x026
#define NUM_OF_PAGE_IN_FW_QUEUE_BE_DTM			0x048
#define NUM_OF_PAGE_IN_FW_QUEUE_VI_DTM			0x048
#define NUM_OF_PAGE_IN_FW_QUEUE_VO_DTM			0x026
#define NUM_OF_PAGE_IN_FW_QUEUE_PUB_DTM			0x00

#define MAX_LINES_HWCONFIG_TXT				1000
#define MAX_BYTES_LINE_HWCONFIG_TXT			256

#define SW_THREE_WIRE					0
#define HW_THREE_WIRE					2

#define BT_DEMO_BOARD					0
#define BT_QA_BOARD					1
#define BT_FPGA						2

#define RX_SMOOTH_FACTOR				20

#define HAL_PRIME_CHNL_OFFSET_DONT_CARE			0
#define HAL_PRIME_CHNL_OFFSET_LOWER			1
#define HAL_PRIME_CHNL_OFFSET_UPPER			2

#define MAX_H2C_QUEUE_NUM				10

#define RX_MPDU_QUEUE					0
#define RX_CMD_QUEUE					1
#define RX_MAX_QUEUE					2
#define AC2QUEUEID(_AC)					(_AC)

#define	C2H_RX_CMD_HDR_LEN				8
#define	GET_C2H_CMD_CMD_LEN(__prxhdr)		\
	LE_BITS_TO_4BYTE((__prxhdr), 0, 16)
#define	GET_C2H_CMD_ELEMENT_ID(__prxhdr)	\
	LE_BITS_TO_4BYTE((__prxhdr), 16, 8)
#define	GET_C2H_CMD_CMD_SEQ(__prxhdr)		\
	LE_BITS_TO_4BYTE((__prxhdr), 24, 7)
#define	GET_C2H_CMD_CONTINUE(__prxhdr)		\
	LE_BITS_TO_4BYTE((__prxhdr), 31, 1)
#define	GET_C2H_CMD_CONTENT(__prxhdr)		\
	((u8 *)(__prxhdr) + C2H_RX_CMD_HDR_LEN)

#define	GET_C2H_CMD_FEEDBACK_ELEMENT_ID(__pcmdfbhdr)	\
	LE_BITS_TO_4BYTE((__pcmdfbhdr), 0, 8)
#define	GET_C2H_CMD_FEEDBACK_CCX_LEN(__pcmdfbhdr)	\
	LE_BITS_TO_4BYTE((__pcmdfbhdr), 8, 8)
#define	GET_C2H_CMD_FEEDBACK_CCX_CMD_CNT(__pcmdfbhdr)	\
	LE_BITS_TO_4BYTE((__pcmdfbhdr), 16, 16)
#define	GET_C2H_CMD_FEEDBACK_CCX_MAC_ID(__pcmdfbhdr)	\
	LE_BITS_TO_4BYTE(((__pcmdfbhdr) + 4), 0, 5)
#define	GET_C2H_CMD_FEEDBACK_CCX_VALID(__pcmdfbhdr)	\
	LE_BITS_TO_4BYTE(((__pcmdfbhdr) + 4), 7, 1)
#define	GET_C2H_CMD_FEEDBACK_CCX_RETRY_CNT(__pcmdfbhdr)	\
	LE_BITS_TO_4BYTE(((__pcmdfbhdr) + 4), 8, 5)
#define	GET_C2H_CMD_FEEDBACK_CCX_TOK(__pcmdfbhdr)	\
	LE_BITS_TO_4BYTE(((__pcmdfbhdr) + 4), 15, 1)
#define	GET_C2H_CMD_FEEDBACK_CCX_QSEL(__pcmdfbhdr)	\
	LE_BITS_TO_4BYTE(((__pcmdfbhdr) + 4), 16, 4)
#define	GET_C2H_CMD_FEEDBACK_CCX_SEQ(__pcmdfbhdr)	\
	LE_BITS_TO_4BYTE(((__pcmdfbhdr) + 4), 20, 12)

#define CHIP_VER_B			BIT(4)
#define CHIP_BONDING_IDENTIFIER(_value) (((_value) >> 22) & 0x3)
#define CHIP_BONDING_92C_1T2R		0x1
#define RF_TYPE_1T2R			BIT(1)
#define CHIP_92C_BITMASK		BIT(0)
#define CHIP_UNKNOWN			BIT(7)
#define CHIP_92C_1T2R			0x03
#define CHIP_92C			0x01
#define CHIP_88C			0x00

enum version_8192c {
	VERSION_A_CHIP_92C = 0x01,
	VERSION_A_CHIP_88C = 0x00,
	VERSION_B_CHIP_92C = 0x11,
	VERSION_B_CHIP_88C = 0x10,
	VERSION_TEST_CHIP_88C = 0x00,
	VERSION_TEST_CHIP_92C = 0x01,
	VERSION_NORMAL_TSMC_CHIP_88C = 0x10,
	VERSION_NORMAL_TSMC_CHIP_92C = 0x11,
	VERSION_NORMAL_TSMC_CHIP_92C_1T2R = 0x13,
	VERSION_NORMAL_UMC_CHIP_88C_A_CUT = 0x30,
	VERSION_NORMAL_UMC_CHIP_92C_A_CUT = 0x31,
	VERSION_NORMAL_UMC_CHIP_92C_1T2R_A_CUT = 0x33,
	VERSION_NORMA_UMC_CHIP_8723_1T1R_A_CUT = 0x34,
	VERSION_NORMA_UMC_CHIP_8723_1T1R_B_CUT = 0x3c,
	VERSION_NORMAL_UMC_CHIP_88C_B_CUT = 0x70,
	VERSION_NORMAL_UMC_CHIP_92C_B_CUT = 0x71,
	VERSION_NORMAL_UMC_CHIP_92C_1T2R_B_CUT = 0x73,
	VERSION_UNKNOWN = 0x88,
};

#define CUT_VERSION_MASK		(BIT(6)|BIT(7))
#define CHIP_VENDOR_UMC			BIT(5)
#define CHIP_VENDOR_UMC_B_CUT		BIT(6) /* Chip version for ECO */
#define IS_VENDOR_UMC_A_CUT(version)	((IS_CHIP_VENDOR_UMC(version)) ? \
	((GET_CVID_CUT_VERSION(version)) ? false : true) : false)
#define IS_CHIP_VER_B(version)  ((version & CHIP_VER_B) ? true : false)
#define IS_VENDOR_UMC_A_CUT(version)	((IS_CHIP_VENDOR_UMC(version)) ? \
	((GET_CVID_CUT_VERSION(version)) ? false : true) : false)
#define IS_92C_SERIAL(version)  ((version & CHIP_92C_BITMASK) ? true : false)
#define IS_CHIP_VENDOR_UMC(version)		\
	((version & CHIP_VENDOR_UMC) ? true : false)
#define GET_CVID_CUT_VERSION(version)	((version) & CUT_VERSION_MASK)
#define IS_81xxC_VENDOR_UMC_B_CUT(version)		\
	((IS_CHIP_VENDOR_UMC(version)) ? \
	((GET_CVID_CUT_VERSION(version) == CHIP_VENDOR_UMC_B_CUT) ?	\
	true : false) : false)

enum rtl819x_loopback_e {
	RTL819X_NO_LOOPBACK = 0,
	RTL819X_MAC_LOOPBACK = 1,
	RTL819X_DMA_LOOPBACK = 2,
	RTL819X_CCK_LOOPBACK = 3,
};

enum rf_optype {
	RF_OP_BY_SW_3WIRE = 0,
	RF_OP_BY_FW,
	RF_OP_MAX
};

enum rf_power_state {
	RF_ON,
	RF_OFF,
	RF_SLEEP,
	RF_SHUT_DOWN,
};

enum power_save_mode {
	POWER_SAVE_MODE_ACTIVE,
	POWER_SAVE_MODE_SAVE,
};

enum power_polocy_config {
	POWERCFG_MAX_POWER_SAVINGS,
	POWERCFG_GLOBAL_POWER_SAVINGS,
	POWERCFG_LOCAL_POWER_SAVINGS,
	POWERCFG_LENOVO,
};

enum interface_select_pci {
	INTF_SEL1_MINICARD = 0,
	INTF_SEL0_PCIE = 1,
	INTF_SEL2_RSV = 2,
	INTF_SEL3_RSV = 3,
};

enum hal_fw_c2h_cmd_id {
	HAL_FW_C2H_CMD_Read_MACREG = 0,
	HAL_FW_C2H_CMD_Read_BBREG = 1,
	HAL_FW_C2H_CMD_Read_RFREG = 2,
	HAL_FW_C2H_CMD_Read_EEPROM = 3,
	HAL_FW_C2H_CMD_Read_EFUSE = 4,
	HAL_FW_C2H_CMD_Read_CAM = 5,
	HAL_FW_C2H_CMD_Get_BasicRate = 6,
	HAL_FW_C2H_CMD_Get_DataRate = 7,
	HAL_FW_C2H_CMD_Survey = 8,
	HAL_FW_C2H_CMD_SurveyDone = 9,
	HAL_FW_C2H_CMD_JoinBss = 10,
	HAL_FW_C2H_CMD_AddSTA = 11,
	HAL_FW_C2H_CMD_DelSTA = 12,
	HAL_FW_C2H_CMD_AtimDone = 13,
	HAL_FW_C2H_CMD_TX_Report = 14,
	HAL_FW_C2H_CMD_CCX_Report = 15,
	HAL_FW_C2H_CMD_DTM_Report = 16,
	HAL_FW_C2H_CMD_TX_Rate_Statistics = 17,
	HAL_FW_C2H_CMD_C2HLBK = 18,
	HAL_FW_C2H_CMD_C2HDBG = 19,
	HAL_FW_C2H_CMD_C2HFEEDBACK = 20,
	HAL_FW_C2H_CMD_MAX
};

enum rtl_desc_qsel {
	QSLT_BK = 0x2,
	QSLT_BE = 0x0,
	QSLT_VI = 0x5,
	QSLT_VO = 0x7,
	QSLT_BEACON = 0x10,
	QSLT_HIGH = 0x11,
	QSLT_MGNT = 0x12,
	QSLT_CMD = 0x13,
};

struct phy_sts_cck_8192s_t {
	u8 adc_pwdb_X[4];
	u8 sq_rpt;
	u8 cck_agc_rpt;
};

struct h2c_cmd_8192c {
	u8 element_id;
	u32 cmd_len;
	u8 *p_cmdbuffer;
};

#endif
Commit	Line	Data
0c817338 LF	1	/******************************************************************************
0c817338 LF	2	*
9003a4ab	3	* Copyright(c) 2009-2012 Realtek Corporation.
0c817338 LF	4	*
	5	* This program is free software; you can redistribute it and/or modify it
	6	* under the terms of version 2 of the GNU General Public License as
	7	* published by the Free Software Foundation.
	8	*
	9	* This program is distributed in the hope that it will be useful, but WITHOUT
	10	* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
	11	* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
	12	* more details.
	13	*
	14	* You should have received a copy of the GNU General Public License along with
	15	* this program; if not, write to the Free Software Foundation, Inc.,
	16	* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
	17	*
	18	* The full GNU General Public License is included in this distribution in the
	19	* file called LICENSE.
	20	*
	21	* Contact Information:
	22	* wlanfae <wlanfae@realtek.com>
	23	* Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
	24	* Hsinchu 300, Taiwan.
	25	*
	26	* Larry Finger <Larry.Finger@lwfinger.net>
	27	*
	28	*****************************************************************************/
	29
	30	#ifndef __RTL92C_DEF_H__
	31	#define __RTL92C_DEF_H__
	32
	33	#define HAL_RETRY_LIMIT_INFRA 48
	34	#define HAL_RETRY_LIMIT_AP_ADHOC 7
	35
	36	#define PHY_RSSI_SLID_WIN_MAX 100
	37	#define PHY_LINKQUALITY_SLID_WIN_MAX 20
	38	#define PHY_BEACON_RSSI_SLID_WIN_MAX 10
	39
	40	#define RESET_DELAY_8185 20
	41
	42	#define RT_IBSS_INT_MASKS (IMR_BCNINT \| IMR_TBDOK \| IMR_TBDER)
	43	#define RT_AC_INT_MASKS (IMR_VIDOK \| IMR_VODOK \| IMR_BEDOK\|IMR_BKDOK)
	44
	45	#define NUM_OF_FIRMWARE_QUEUE 10
	46	#define NUM_OF_PAGES_IN_FW 0x100
	47	#define NUM_OF_PAGE_IN_FW_QUEUE_BK 0x07
	48	#define NUM_OF_PAGE_IN_FW_QUEUE_BE 0x07
	49	#define NUM_OF_PAGE_IN_FW_QUEUE_VI 0x07
	50	#define NUM_OF_PAGE_IN_FW_QUEUE_VO 0x07
	51	#define NUM_OF_PAGE_IN_FW_QUEUE_HCCA 0x0
	52	#define NUM_OF_PAGE_IN_FW_QUEUE_CMD 0x0
	53	#define NUM_OF_PAGE_IN_FW_QUEUE_MGNT 0x02
	54	#define NUM_OF_PAGE_IN_FW_QUEUE_HIGH 0x02
	55	#define NUM_OF_PAGE_IN_FW_QUEUE_BCN 0x2
	56	#define NUM_OF_PAGE_IN_FW_QUEUE_PUB 0xA1
	57
	58	#define NUM_OF_PAGE_IN_FW_QUEUE_BK_DTM 0x026
	59	#define NUM_OF_PAGE_IN_FW_QUEUE_BE_DTM 0x048
	60	#define NUM_OF_PAGE_IN_FW_QUEUE_VI_DTM 0x048
	61	#define NUM_OF_PAGE_IN_FW_QUEUE_VO_DTM 0x026
	62	#define NUM_OF_PAGE_IN_FW_QUEUE_PUB_DTM 0x00
	63
	64	#define MAX_LINES_HWCONFIG_TXT 1000
	65	#define MAX_BYTES_LINE_HWCONFIG_TXT 256
	66
	67	#define SW_THREE_WIRE 0
68	#define HW_THREE_WIRE 2
69
70	#define BT_DEMO_BOARD 0
71	#define BT_QA_BOARD 1
72	#define BT_FPGA 2
73
74	#define RX_SMOOTH_FACTOR 20
75
76	#define HAL_PRIME_CHNL_OFFSET_DONT_CARE 0
77	#define HAL_PRIME_CHNL_OFFSET_LOWER 1
78	#define HAL_PRIME_CHNL_OFFSET_UPPER 2
79
80	#define MAX_H2C_QUEUE_NUM 10
81
82	#define RX_MPDU_QUEUE 0
83	#define RX_CMD_QUEUE 1
84	#define RX_MAX_QUEUE 2
85	#define AC2QUEUEID(_AC) (_AC)
86
87	#define C2H_RX_CMD_HDR_LEN 8
88	#define GET_C2H_CMD_CMD_LEN(__prxhdr) \
89	LE_BITS_TO_4BYTE((__prxhdr), 0, 16)
90	#define GET_C2H_CMD_ELEMENT_ID(__prxhdr) \
91	LE_BITS_TO_4BYTE((__prxhdr), 16, 8)
92	#define GET_C2H_CMD_CMD_SEQ(__prxhdr) \
93	LE_BITS_TO_4BYTE((__prxhdr), 24, 7)
94	#define GET_C2H_CMD_CONTINUE(__prxhdr) \
95	LE_BITS_TO_4BYTE((__prxhdr), 31, 1)
96	#define GET_C2H_CMD_CONTENT(__prxhdr) \
97	((u8 *)(__prxhdr) + C2H_RX_CMD_HDR_LEN)
98
99	#define GET_C2H_CMD_FEEDBACK_ELEMENT_ID(__pcmdfbhdr) \
100	LE_BITS_TO_4BYTE((__pcmdfbhdr), 0, 8)
101	#define GET_C2H_CMD_FEEDBACK_CCX_LEN(__pcmdfbhdr) \
102	LE_BITS_TO_4BYTE((__pcmdfbhdr), 8, 8)
103	#define GET_C2H_CMD_FEEDBACK_CCX_CMD_CNT(__pcmdfbhdr) \
104	LE_BITS_TO_4BYTE((__pcmdfbhdr), 16, 16)
105	#define GET_C2H_CMD_FEEDBACK_CCX_MAC_ID(__pcmdfbhdr) \
106	LE_BITS_TO_4BYTE(((__pcmdfbhdr) + 4), 0, 5)
107	#define GET_C2H_CMD_FEEDBACK_CCX_VALID(__pcmdfbhdr) \
108	LE_BITS_TO_4BYTE(((__pcmdfbhdr) + 4), 7, 1)
109	#define GET_C2H_CMD_FEEDBACK_CCX_RETRY_CNT(__pcmdfbhdr) \
110	LE_BITS_TO_4BYTE(((__pcmdfbhdr) + 4), 8, 5)
111	#define GET_C2H_CMD_FEEDBACK_CCX_TOK(__pcmdfbhdr) \
112	LE_BITS_TO_4BYTE(((__pcmdfbhdr) + 4), 15, 1)
113	#define GET_C2H_CMD_FEEDBACK_CCX_QSEL(__pcmdfbhdr) \
114	LE_BITS_TO_4BYTE(((__pcmdfbhdr) + 4), 16, 4)
115	#define GET_C2H_CMD_FEEDBACK_CCX_SEQ(__pcmdfbhdr) \
116	LE_BITS_TO_4BYTE(((__pcmdfbhdr) + 4), 20, 12)
117
118	#define CHIP_VER_B BIT(4)
0bd899e7 LF	119	#define CHIP_BONDING_IDENTIFIER(_value) (((_value) >> 22) & 0x3)
	120	#define CHIP_BONDING_92C_1T2R 0x1
	121	#define RF_TYPE_1T2R BIT(1)
0c817338	122	#define CHIP_92C_BITMASK BIT(0)
022e1d06	123	#define CHIP_UNKNOWN BIT(7)
0c817338 LF	124	#define CHIP_92C_1T2R 0x03
	125	#define CHIP_92C 0x01
	126	#define CHIP_88C 0x00
	127
	128	enum version_8192c {
	129	VERSION_A_CHIP_92C = 0x01,
	130	VERSION_A_CHIP_88C = 0x00,
	131	VERSION_B_CHIP_92C = 0x11,
	132	VERSION_B_CHIP_88C = 0x10,
0e80b9d1 LF	133	VERSION_TEST_CHIP_88C = 0x00,
	134	VERSION_TEST_CHIP_92C = 0x01,
	135	VERSION_NORMAL_TSMC_CHIP_88C = 0x10,
	136	VERSION_NORMAL_TSMC_CHIP_92C = 0x11,
	137	VERSION_NORMAL_TSMC_CHIP_92C_1T2R = 0x13,
	138	VERSION_NORMAL_UMC_CHIP_88C_A_CUT = 0x30,
	139	VERSION_NORMAL_UMC_CHIP_92C_A_CUT = 0x31,
	140	VERSION_NORMAL_UMC_CHIP_92C_1T2R_A_CUT = 0x33,
	141	VERSION_NORMA_UMC_CHIP_8723_1T1R_A_CUT = 0x34,
	142	VERSION_NORMA_UMC_CHIP_8723_1T1R_B_CUT = 0x3c,
	143	VERSION_NORMAL_UMC_CHIP_88C_B_CUT = 0x70,
	144	VERSION_NORMAL_UMC_CHIP_92C_B_CUT = 0x71,
	145	VERSION_NORMAL_UMC_CHIP_92C_1T2R_B_CUT = 0x73,
0c817338 LF	146	VERSION_UNKNOWN = 0x88,
	147	};
	148
db759939 CL	149	#define CUT_VERSION_MASK (BIT(6)\|BIT(7))
	150	#define CHIP_VENDOR_UMC BIT(5)
	151	#define CHIP_VENDOR_UMC_B_CUT BIT(6) /* Chip version for ECO */
	152	#define IS_VENDOR_UMC_A_CUT(version) ((IS_CHIP_VENDOR_UMC(version)) ? \
	153	((GET_CVID_CUT_VERSION(version)) ? false : true) : false)
0c817338	154	#define IS_CHIP_VER_B(version) ((version & CHIP_VER_B) ? true : false)
db759939 CL	155	#define IS_VENDOR_UMC_A_CUT(version) ((IS_CHIP_VENDOR_UMC(version)) ? \
db759939 CL	156	((GET_CVID_CUT_VERSION(version)) ? false : true) : false)
0c817338	157	#define IS_92C_SERIAL(version) ((version & CHIP_92C_BITMASK) ? true : false)
db759939 CL	158	#define IS_CHIP_VENDOR_UMC(version) \
	159	((version & CHIP_VENDOR_UMC) ? true : false)
	160	#define GET_CVID_CUT_VERSION(version) ((version) & CUT_VERSION_MASK)
	161	#define IS_81xxC_VENDOR_UMC_B_CUT(version) \
	162	((IS_CHIP_VENDOR_UMC(version)) ? \
	163	((GET_CVID_CUT_VERSION(version) == CHIP_VENDOR_UMC_B_CUT) ? \
	164	true : false) : false)
0c817338 LF	165
	166	enum rtl819x_loopback_e {
	167	RTL819X_NO_LOOPBACK = 0,
	168	RTL819X_MAC_LOOPBACK = 1,
	169	RTL819X_DMA_LOOPBACK = 2,
	170	RTL819X_CCK_LOOPBACK = 3,
	171	};
	172
	173	enum rf_optype {
	174	RF_OP_BY_SW_3WIRE = 0,
	175	RF_OP_BY_FW,
	176	RF_OP_MAX
	177	};
	178
	179	enum rf_power_state {
	180	RF_ON,
	181	RF_OFF,
	182	RF_SLEEP,
	183	RF_SHUT_DOWN,
	184	};
	185
	186	enum power_save_mode {
	187	POWER_SAVE_MODE_ACTIVE,
	188	POWER_SAVE_MODE_SAVE,
	189	};
	190
	191	enum power_polocy_config {
	192	POWERCFG_MAX_POWER_SAVINGS,
	193	POWERCFG_GLOBAL_POWER_SAVINGS,
	194	POWERCFG_LOCAL_POWER_SAVINGS,
	195	POWERCFG_LENOVO,
	196	};
	197
	198	enum interface_select_pci {
	199	INTF_SEL1_MINICARD = 0,
	200	INTF_SEL0_PCIE = 1,
	201	INTF_SEL2_RSV = 2,
	202	INTF_SEL3_RSV = 3,
	203	};
	204
	205	enum hal_fw_c2h_cmd_id {
	206	HAL_FW_C2H_CMD_Read_MACREG = 0,
	207	HAL_FW_C2H_CMD_Read_BBREG = 1,
	208	HAL_FW_C2H_CMD_Read_RFREG = 2,
	209	HAL_FW_C2H_CMD_Read_EEPROM = 3,
	210	HAL_FW_C2H_CMD_Read_EFUSE = 4,
	211	HAL_FW_C2H_CMD_Read_CAM = 5,
	212	HAL_FW_C2H_CMD_Get_BasicRate = 6,
	213	HAL_FW_C2H_CMD_Get_DataRate = 7,
	214	HAL_FW_C2H_CMD_Survey = 8,
	215	HAL_FW_C2H_CMD_SurveyDone = 9,
	216	HAL_FW_C2H_CMD_JoinBss = 10,
	217	HAL_FW_C2H_CMD_AddSTA = 11,
	218	HAL_FW_C2H_CMD_DelSTA = 12,
	219	HAL_FW_C2H_CMD_AtimDone = 13,
	220	HAL_FW_C2H_CMD_TX_Report = 14,
	221	HAL_FW_C2H_CMD_CCX_Report = 15,
	222	HAL_FW_C2H_CMD_DTM_Report = 16,
	223	HAL_FW_C2H_CMD_TX_Rate_Statistics = 17,
	224	HAL_FW_C2H_CMD_C2HLBK = 18,
	225	HAL_FW_C2H_CMD_C2HDBG = 19,
	226	HAL_FW_C2H_CMD_C2HFEEDBACK = 20,
	227	HAL_FW_C2H_CMD_MAX
	228	};
229
230	enum rtl_desc_qsel {
231	QSLT_BK = 0x2,
232	QSLT_BE = 0x0,
233	QSLT_VI = 0x5,
234	QSLT_VO = 0x7,
235	QSLT_BEACON = 0x10,
236	QSLT_HIGH = 0x11,
237	QSLT_MGNT = 0x12,
238	QSLT_CMD = 0x13,
239	};
240
0c817338 LF	241	struct phy_sts_cck_8192s_t {
	242	u8 adc_pwdb_X[4];
	243	u8 sq_rpt;
	244	u8 cck_agc_rpt;
	245	};
	246
	247	struct h2c_cmd_8192c {
	248	u8 element_id;
	249	u32 cmd_len;
	250	u8 *p_cmdbuffer;
	251	};
	252
	253	#endif