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0c817338 LF |
1 | /****************************************************************************** |
2 | * | |
9003a4ab | 3 | * Copyright(c) 2009-2012 Realtek Corporation. |
0c817338 LF |
4 | * |
5 | * This program is free software; you can redistribute it and/or modify it | |
6 | * under the terms of version 2 of the GNU General Public License as | |
7 | * published by the Free Software Foundation. | |
8 | * | |
9 | * This program is distributed in the hope that it will be useful, but WITHOUT | |
10 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
11 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | |
12 | * more details. | |
13 | * | |
14 | * You should have received a copy of the GNU General Public License along with | |
15 | * this program; if not, write to the Free Software Foundation, Inc., | |
16 | * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA | |
17 | * | |
18 | * The full GNU General Public License is included in this distribution in the | |
19 | * file called LICENSE. | |
20 | * | |
21 | * Contact Information: | |
22 | * wlanfae <wlanfae@realtek.com> | |
23 | * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park, | |
24 | * Hsinchu 300, Taiwan. | |
25 | * | |
26 | * Larry Finger <Larry.Finger@lwfinger.net> | |
27 | * | |
28 | *****************************************************************************/ | |
29 | ||
30 | #include "../wifi.h" | |
31 | #include "../efuse.h" | |
32 | #include "../base.h" | |
f73b279c | 33 | #include "../regd.h" |
0c817338 LF |
34 | #include "../cam.h" |
35 | #include "../ps.h" | |
36 | #include "../pci.h" | |
5c405b5c JL |
37 | #include "reg.h" |
38 | #include "def.h" | |
39 | #include "phy.h" | |
f73b279c | 40 | #include "../rtl8192c/fw_common.h" |
5c405b5c | 41 | #include "dm.h" |
5c405b5c JL |
42 | #include "led.h" |
43 | #include "hw.h" | |
0c817338 LF |
44 | |
45 | #define LLT_CONFIG 5 | |
46 | ||
47 | static void _rtl92ce_set_bcn_ctrl_reg(struct ieee80211_hw *hw, | |
48 | u8 set_bits, u8 clear_bits) | |
49 | { | |
50 | struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw)); | |
51 | struct rtl_priv *rtlpriv = rtl_priv(hw); | |
52 | ||
53 | rtlpci->reg_bcn_ctrl_val |= set_bits; | |
54 | rtlpci->reg_bcn_ctrl_val &= ~clear_bits; | |
55 | ||
56 | rtl_write_byte(rtlpriv, REG_BCN_CTRL, (u8) rtlpci->reg_bcn_ctrl_val); | |
57 | } | |
58 | ||
59 | static void _rtl92ce_stop_tx_beacon(struct ieee80211_hw *hw) | |
60 | { | |
61 | struct rtl_priv *rtlpriv = rtl_priv(hw); | |
62 | u8 tmp1byte; | |
63 | ||
64 | tmp1byte = rtl_read_byte(rtlpriv, REG_FWHW_TXQ_CTRL + 2); | |
65 | rtl_write_byte(rtlpriv, REG_FWHW_TXQ_CTRL + 2, tmp1byte & (~BIT(6))); | |
66 | rtl_write_byte(rtlpriv, REG_TBTT_PROHIBIT + 1, 0x64); | |
67 | tmp1byte = rtl_read_byte(rtlpriv, REG_TBTT_PROHIBIT + 2); | |
68 | tmp1byte &= ~(BIT(0)); | |
69 | rtl_write_byte(rtlpriv, REG_TBTT_PROHIBIT + 2, tmp1byte); | |
70 | } | |
71 | ||
72 | static void _rtl92ce_resume_tx_beacon(struct ieee80211_hw *hw) | |
73 | { | |
74 | struct rtl_priv *rtlpriv = rtl_priv(hw); | |
75 | u8 tmp1byte; | |
76 | ||
77 | tmp1byte = rtl_read_byte(rtlpriv, REG_FWHW_TXQ_CTRL + 2); | |
78 | rtl_write_byte(rtlpriv, REG_FWHW_TXQ_CTRL + 2, tmp1byte | BIT(6)); | |
79 | rtl_write_byte(rtlpriv, REG_TBTT_PROHIBIT + 1, 0xff); | |
80 | tmp1byte = rtl_read_byte(rtlpriv, REG_TBTT_PROHIBIT + 2); | |
81 | tmp1byte |= BIT(0); | |
82 | rtl_write_byte(rtlpriv, REG_TBTT_PROHIBIT + 2, tmp1byte); | |
83 | } | |
84 | ||
85 | static void _rtl92ce_enable_bcn_sub_func(struct ieee80211_hw *hw) | |
86 | { | |
87 | _rtl92ce_set_bcn_ctrl_reg(hw, 0, BIT(1)); | |
88 | } | |
89 | ||
90 | static void _rtl92ce_disable_bcn_sub_func(struct ieee80211_hw *hw) | |
91 | { | |
92 | _rtl92ce_set_bcn_ctrl_reg(hw, BIT(1), 0); | |
93 | } | |
94 | ||
95 | void rtl92ce_get_hw_reg(struct ieee80211_hw *hw, u8 variable, u8 *val) | |
96 | { | |
97 | struct rtl_priv *rtlpriv = rtl_priv(hw); | |
98 | struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw)); | |
99 | struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw)); | |
100 | ||
101 | switch (variable) { | |
102 | case HW_VAR_RCR: | |
103 | *((u32 *) (val)) = rtlpci->receive_config; | |
104 | break; | |
105 | case HW_VAR_RF_STATE: | |
106 | *((enum rf_pwrstate *)(val)) = ppsc->rfpwr_state; | |
107 | break; | |
108 | case HW_VAR_FWLPS_RF_ON:{ | |
109 | enum rf_pwrstate rfState; | |
110 | u32 val_rcr; | |
111 | ||
112 | rtlpriv->cfg->ops->get_hw_reg(hw, | |
113 | HW_VAR_RF_STATE, | |
114 | (u8 *) (&rfState)); | |
115 | if (rfState == ERFOFF) { | |
116 | *((bool *) (val)) = true; | |
117 | } else { | |
118 | val_rcr = rtl_read_dword(rtlpriv, REG_RCR); | |
119 | val_rcr &= 0x00070000; | |
120 | if (val_rcr) | |
121 | *((bool *) (val)) = false; | |
122 | else | |
123 | *((bool *) (val)) = true; | |
124 | } | |
125 | break; | |
126 | } | |
127 | case HW_VAR_FW_PSMODE_STATUS: | |
7ea47240 | 128 | *((bool *) (val)) = ppsc->fw_current_inpsmode; |
0c817338 LF |
129 | break; |
130 | case HW_VAR_CORRECT_TSF:{ | |
131 | u64 tsf; | |
132 | u32 *ptsf_low = (u32 *)&tsf; | |
133 | u32 *ptsf_high = ((u32 *)&tsf) + 1; | |
134 | ||
135 | *ptsf_high = rtl_read_dword(rtlpriv, (REG_TSFTR + 4)); | |
136 | *ptsf_low = rtl_read_dword(rtlpriv, REG_TSFTR); | |
137 | ||
138 | *((u64 *) (val)) = tsf; | |
139 | ||
140 | break; | |
141 | } | |
0c817338 LF |
142 | default: |
143 | RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG, | |
f30d7507 | 144 | "switch case not processed\n"); |
0c817338 LF |
145 | break; |
146 | } | |
147 | } | |
148 | ||
149 | void rtl92ce_set_hw_reg(struct ieee80211_hw *hw, u8 variable, u8 *val) | |
150 | { | |
151 | struct rtl_priv *rtlpriv = rtl_priv(hw); | |
f73b279c | 152 | struct rtl_pci_priv *rtlpcipriv = rtl_pcipriv(hw); |
0c817338 LF |
153 | struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw)); |
154 | struct rtl_mac *mac = rtl_mac(rtl_priv(hw)); | |
155 | struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw)); | |
156 | struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw)); | |
157 | struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw)); | |
158 | u8 idx; | |
159 | ||
160 | switch (variable) { | |
161 | case HW_VAR_ETHER_ADDR:{ | |
162 | for (idx = 0; idx < ETH_ALEN; idx++) { | |
163 | rtl_write_byte(rtlpriv, (REG_MACID + idx), | |
164 | val[idx]); | |
165 | } | |
166 | break; | |
167 | } | |
168 | case HW_VAR_BASIC_RATE:{ | |
7ea47240 | 169 | u16 rate_cfg = ((u16 *) val)[0]; |
0c817338 | 170 | u8 rate_index = 0; |
7ea47240 LF |
171 | rate_cfg &= 0x15f; |
172 | rate_cfg |= 0x01; | |
173 | rtl_write_byte(rtlpriv, REG_RRSR, rate_cfg & 0xff); | |
0c817338 | 174 | rtl_write_byte(rtlpriv, REG_RRSR + 1, |
f73b279c | 175 | (rate_cfg >> 8) & 0xff); |
7ea47240 LF |
176 | while (rate_cfg > 0x1) { |
177 | rate_cfg = (rate_cfg >> 1); | |
0c817338 LF |
178 | rate_index++; |
179 | } | |
180 | rtl_write_byte(rtlpriv, REG_INIRTS_RATE_SEL, | |
181 | rate_index); | |
182 | break; | |
183 | } | |
184 | case HW_VAR_BSSID:{ | |
185 | for (idx = 0; idx < ETH_ALEN; idx++) { | |
186 | rtl_write_byte(rtlpriv, (REG_BSSID + idx), | |
187 | val[idx]); | |
188 | } | |
189 | break; | |
190 | } | |
191 | case HW_VAR_SIFS:{ | |
192 | rtl_write_byte(rtlpriv, REG_SIFS_CTX + 1, val[0]); | |
193 | rtl_write_byte(rtlpriv, REG_SIFS_TRX + 1, val[1]); | |
194 | ||
195 | rtl_write_byte(rtlpriv, REG_SPEC_SIFS + 1, val[0]); | |
196 | rtl_write_byte(rtlpriv, REG_MAC_SPEC_SIFS + 1, val[0]); | |
197 | ||
198 | if (!mac->ht_enable) | |
199 | rtl_write_word(rtlpriv, REG_RESP_SIFS_OFDM, | |
200 | 0x0e0e); | |
201 | else | |
202 | rtl_write_word(rtlpriv, REG_RESP_SIFS_OFDM, | |
203 | *((u16 *) val)); | |
204 | break; | |
205 | } | |
206 | case HW_VAR_SLOT_TIME:{ | |
207 | u8 e_aci; | |
208 | ||
209 | RT_TRACE(rtlpriv, COMP_MLME, DBG_LOUD, | |
f30d7507 | 210 | "HW_VAR_SLOT_TIME %x\n", val[0]); |
0c817338 LF |
211 | |
212 | rtl_write_byte(rtlpriv, REG_SLOT, val[0]); | |
213 | ||
214 | for (e_aci = 0; e_aci < AC_MAX; e_aci++) { | |
215 | rtlpriv->cfg->ops->set_hw_reg(hw, | |
216 | HW_VAR_AC_PARAM, | |
2c208890 | 217 | &e_aci); |
0c817338 LF |
218 | } |
219 | break; | |
220 | } | |
221 | case HW_VAR_ACK_PREAMBLE:{ | |
222 | u8 reg_tmp; | |
2c208890 | 223 | u8 short_preamble = (bool)*val; |
0c817338 LF |
224 | reg_tmp = (mac->cur_40_prime_sc) << 5; |
225 | if (short_preamble) | |
226 | reg_tmp |= 0x80; | |
227 | ||
228 | rtl_write_byte(rtlpriv, REG_RRSR + 2, reg_tmp); | |
229 | break; | |
230 | } | |
231 | case HW_VAR_AMPDU_MIN_SPACE:{ | |
232 | u8 min_spacing_to_set; | |
233 | u8 sec_min_space; | |
234 | ||
2c208890 | 235 | min_spacing_to_set = *val; |
0c817338 LF |
236 | if (min_spacing_to_set <= 7) { |
237 | sec_min_space = 0; | |
238 | ||
239 | if (min_spacing_to_set < sec_min_space) | |
240 | min_spacing_to_set = sec_min_space; | |
241 | ||
242 | mac->min_space_cfg = ((mac->min_space_cfg & | |
243 | 0xf8) | | |
244 | min_spacing_to_set); | |
245 | ||
246 | *val = min_spacing_to_set; | |
247 | ||
248 | RT_TRACE(rtlpriv, COMP_MLME, DBG_LOUD, | |
f30d7507 JP |
249 | "Set HW_VAR_AMPDU_MIN_SPACE: %#x\n", |
250 | mac->min_space_cfg); | |
0c817338 LF |
251 | |
252 | rtl_write_byte(rtlpriv, REG_AMPDU_MIN_SPACE, | |
253 | mac->min_space_cfg); | |
254 | } | |
255 | break; | |
256 | } | |
257 | case HW_VAR_SHORTGI_DENSITY:{ | |
258 | u8 density_to_set; | |
259 | ||
2c208890 | 260 | density_to_set = *val; |
0c817338 LF |
261 | mac->min_space_cfg |= (density_to_set << 3); |
262 | ||
263 | RT_TRACE(rtlpriv, COMP_MLME, DBG_LOUD, | |
f30d7507 JP |
264 | "Set HW_VAR_SHORTGI_DENSITY: %#x\n", |
265 | mac->min_space_cfg); | |
0c817338 LF |
266 | |
267 | rtl_write_byte(rtlpriv, REG_AMPDU_MIN_SPACE, | |
268 | mac->min_space_cfg); | |
269 | ||
270 | break; | |
271 | } | |
272 | case HW_VAR_AMPDU_FACTOR:{ | |
f73b279c C |
273 | u8 regtoset_normal[4] = {0x41, 0xa8, 0x72, 0xb9}; |
274 | u8 regtoset_bt[4] = {0x31, 0x74, 0x42, 0x97}; | |
0c817338 LF |
275 | |
276 | u8 factor_toset; | |
277 | u8 *p_regtoset = NULL; | |
278 | u8 index = 0; | |
279 | ||
f73b279c C |
280 | if ((rtlpcipriv->bt_coexist.bt_coexistence) && |
281 | (rtlpcipriv->bt_coexist.bt_coexist_type == | |
282 | BT_CSR_BC4)) | |
283 | p_regtoset = regtoset_bt; | |
284 | else | |
285 | p_regtoset = regtoset_normal; | |
0c817338 | 286 | |
2c208890 | 287 | factor_toset = *(val); |
0c817338 LF |
288 | if (factor_toset <= 3) { |
289 | factor_toset = (1 << (factor_toset + 2)); | |
290 | if (factor_toset > 0xf) | |
291 | factor_toset = 0xf; | |
292 | ||
293 | for (index = 0; index < 4; index++) { | |
294 | if ((p_regtoset[index] & 0xf0) > | |
295 | (factor_toset << 4)) | |
296 | p_regtoset[index] = | |
297 | (p_regtoset[index] & 0x0f) | | |
298 | (factor_toset << 4); | |
299 | ||
300 | if ((p_regtoset[index] & 0x0f) > | |
301 | factor_toset) | |
302 | p_regtoset[index] = | |
303 | (p_regtoset[index] & 0xf0) | | |
304 | (factor_toset); | |
305 | ||
306 | rtl_write_byte(rtlpriv, | |
307 | (REG_AGGLEN_LMT + index), | |
308 | p_regtoset[index]); | |
309 | ||
310 | } | |
311 | ||
312 | RT_TRACE(rtlpriv, COMP_MLME, DBG_LOUD, | |
f30d7507 JP |
313 | "Set HW_VAR_AMPDU_FACTOR: %#x\n", |
314 | factor_toset); | |
0c817338 LF |
315 | } |
316 | break; | |
317 | } | |
318 | case HW_VAR_AC_PARAM:{ | |
2c208890 | 319 | u8 e_aci = *(val); |
f73b279c | 320 | rtl92c_dm_init_edca_turbo(hw); |
0c817338 LF |
321 | |
322 | if (rtlpci->acm_method != eAcmWay2_SW) | |
323 | rtlpriv->cfg->ops->set_hw_reg(hw, | |
324 | HW_VAR_ACM_CTRL, | |
2c208890 | 325 | (&e_aci)); |
0c817338 LF |
326 | break; |
327 | } | |
328 | case HW_VAR_ACM_CTRL:{ | |
2c208890 | 329 | u8 e_aci = *(val); |
0c817338 LF |
330 | union aci_aifsn *p_aci_aifsn = |
331 | (union aci_aifsn *)(&(mac->ac[0].aifs)); | |
332 | u8 acm = p_aci_aifsn->f.acm; | |
333 | u8 acm_ctrl = rtl_read_byte(rtlpriv, REG_ACMHWCTRL); | |
334 | ||
335 | acm_ctrl = | |
336 | acm_ctrl | ((rtlpci->acm_method == 2) ? 0x0 : 0x1); | |
337 | ||
338 | if (acm) { | |
339 | switch (e_aci) { | |
340 | case AC0_BE: | |
341 | acm_ctrl |= AcmHw_BeqEn; | |
342 | break; | |
343 | case AC2_VI: | |
344 | acm_ctrl |= AcmHw_ViqEn; | |
345 | break; | |
346 | case AC3_VO: | |
347 | acm_ctrl |= AcmHw_VoqEn; | |
348 | break; | |
349 | default: | |
350 | RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING, | |
f30d7507 JP |
351 | "HW_VAR_ACM_CTRL acm set failed: eACI is %d\n", |
352 | acm); | |
0c817338 LF |
353 | break; |
354 | } | |
355 | } else { | |
356 | switch (e_aci) { | |
357 | case AC0_BE: | |
358 | acm_ctrl &= (~AcmHw_BeqEn); | |
359 | break; | |
360 | case AC2_VI: | |
361 | acm_ctrl &= (~AcmHw_ViqEn); | |
362 | break; | |
363 | case AC3_VO: | |
364 | acm_ctrl &= (~AcmHw_BeqEn); | |
365 | break; | |
366 | default: | |
367 | RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG, | |
f30d7507 | 368 | "switch case not processed\n"); |
0c817338 LF |
369 | break; |
370 | } | |
371 | } | |
372 | ||
373 | RT_TRACE(rtlpriv, COMP_QOS, DBG_TRACE, | |
f30d7507 JP |
374 | "SetHwReg8190pci(): [HW_VAR_ACM_CTRL] Write 0x%X\n", |
375 | acm_ctrl); | |
0c817338 LF |
376 | rtl_write_byte(rtlpriv, REG_ACMHWCTRL, acm_ctrl); |
377 | break; | |
378 | } | |
379 | case HW_VAR_RCR:{ | |
380 | rtl_write_dword(rtlpriv, REG_RCR, ((u32 *) (val))[0]); | |
381 | rtlpci->receive_config = ((u32 *) (val))[0]; | |
382 | break; | |
383 | } | |
384 | case HW_VAR_RETRY_LIMIT:{ | |
2c208890 | 385 | u8 retry_limit = val[0]; |
0c817338 LF |
386 | |
387 | rtl_write_word(rtlpriv, REG_RL, | |
388 | retry_limit << RETRY_LIMIT_SHORT_SHIFT | | |
389 | retry_limit << RETRY_LIMIT_LONG_SHIFT); | |
390 | break; | |
391 | } | |
392 | case HW_VAR_DUAL_TSF_RST: | |
393 | rtl_write_byte(rtlpriv, REG_DUAL_TSF_RST, (BIT(0) | BIT(1))); | |
394 | break; | |
395 | case HW_VAR_EFUSE_BYTES: | |
396 | rtlefuse->efuse_usedbytes = *((u16 *) val); | |
397 | break; | |
398 | case HW_VAR_EFUSE_USAGE: | |
2c208890 | 399 | rtlefuse->efuse_usedpercentage = *val; |
0c817338 LF |
400 | break; |
401 | case HW_VAR_IO_CMD: | |
402 | rtl92c_phy_set_io_cmd(hw, (*(enum io_type *)val)); | |
403 | break; | |
404 | case HW_VAR_WPA_CONFIG: | |
2c208890 | 405 | rtl_write_byte(rtlpriv, REG_SECCFG, *val); |
0c817338 LF |
406 | break; |
407 | case HW_VAR_SET_RPWM:{ | |
408 | u8 rpwm_val; | |
409 | ||
410 | rpwm_val = rtl_read_byte(rtlpriv, REG_PCIE_HRPWM); | |
411 | udelay(1); | |
412 | ||
413 | if (rpwm_val & BIT(7)) { | |
2c208890 | 414 | rtl_write_byte(rtlpriv, REG_PCIE_HRPWM, *val); |
0c817338 LF |
415 | } else { |
416 | rtl_write_byte(rtlpriv, REG_PCIE_HRPWM, | |
2c208890 | 417 | *val | BIT(7)); |
0c817338 LF |
418 | } |
419 | ||
420 | break; | |
421 | } | |
422 | case HW_VAR_H2C_FW_PWRMODE:{ | |
2c208890 | 423 | u8 psmode = *val; |
0c817338 LF |
424 | |
425 | if ((psmode != FW_PS_ACTIVE_MODE) && | |
426 | (!IS_92C_SERIAL(rtlhal->version))) { | |
427 | rtl92c_dm_rf_saving(hw, true); | |
428 | } | |
429 | ||
2c208890 | 430 | rtl92c_set_fw_pwrmode_cmd(hw, *val); |
0c817338 LF |
431 | break; |
432 | } | |
433 | case HW_VAR_FW_PSMODE_STATUS: | |
7ea47240 | 434 | ppsc->fw_current_inpsmode = *((bool *) val); |
0c817338 LF |
435 | break; |
436 | case HW_VAR_H2C_FW_JOINBSSRPT:{ | |
2c208890 | 437 | u8 mstatus = *val; |
0c817338 | 438 | u8 tmp_regcr, tmp_reg422; |
7ea47240 | 439 | bool recover = false; |
0c817338 LF |
440 | |
441 | if (mstatus == RT_MEDIA_CONNECT) { | |
442 | rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_AID, | |
443 | NULL); | |
444 | ||
445 | tmp_regcr = rtl_read_byte(rtlpriv, REG_CR + 1); | |
446 | rtl_write_byte(rtlpriv, REG_CR + 1, | |
447 | (tmp_regcr | BIT(0))); | |
448 | ||
449 | _rtl92ce_set_bcn_ctrl_reg(hw, 0, BIT(3)); | |
450 | _rtl92ce_set_bcn_ctrl_reg(hw, BIT(4), 0); | |
451 | ||
452 | tmp_reg422 = | |
453 | rtl_read_byte(rtlpriv, | |
454 | REG_FWHW_TXQ_CTRL + 2); | |
455 | if (tmp_reg422 & BIT(6)) | |
7ea47240 | 456 | recover = true; |
0c817338 LF |
457 | rtl_write_byte(rtlpriv, REG_FWHW_TXQ_CTRL + 2, |
458 | tmp_reg422 & (~BIT(6))); | |
459 | ||
460 | rtl92c_set_fw_rsvdpagepkt(hw, 0); | |
461 | ||
462 | _rtl92ce_set_bcn_ctrl_reg(hw, BIT(3), 0); | |
463 | _rtl92ce_set_bcn_ctrl_reg(hw, 0, BIT(4)); | |
464 | ||
7ea47240 | 465 | if (recover) { |
0c817338 LF |
466 | rtl_write_byte(rtlpriv, |
467 | REG_FWHW_TXQ_CTRL + 2, | |
468 | tmp_reg422); | |
469 | } | |
470 | ||
471 | rtl_write_byte(rtlpriv, REG_CR + 1, | |
472 | (tmp_regcr & ~(BIT(0)))); | |
473 | } | |
2c208890 | 474 | rtl92c_set_fw_joinbss_report_cmd(hw, *val); |
0c817338 LF |
475 | |
476 | break; | |
477 | } | |
3a16b412 LF |
478 | case HW_VAR_H2C_FW_P2P_PS_OFFLOAD: |
479 | rtl92c_set_p2p_ps_offload_cmd(hw, (*(u8 *)val)); | |
480 | break; | |
0c817338 LF |
481 | case HW_VAR_AID:{ |
482 | u16 u2btmp; | |
483 | u2btmp = rtl_read_word(rtlpriv, REG_BCN_PSR_RPT); | |
484 | u2btmp &= 0xC000; | |
485 | rtl_write_word(rtlpriv, REG_BCN_PSR_RPT, (u2btmp | | |
486 | mac->assoc_id)); | |
487 | ||
488 | break; | |
489 | } | |
490 | case HW_VAR_CORRECT_TSF:{ | |
2c208890 | 491 | u8 btype_ibss = val[0]; |
0c817338 | 492 | |
e10542c4 | 493 | if (btype_ibss) |
0c817338 LF |
494 | _rtl92ce_stop_tx_beacon(hw); |
495 | ||
496 | _rtl92ce_set_bcn_ctrl_reg(hw, 0, BIT(3)); | |
497 | ||
498 | rtl_write_dword(rtlpriv, REG_TSFTR, | |
499 | (u32) (mac->tsf & 0xffffffff)); | |
500 | rtl_write_dword(rtlpriv, REG_TSFTR + 4, | |
f73b279c | 501 | (u32) ((mac->tsf >> 32) & 0xffffffff)); |
0c817338 LF |
502 | |
503 | _rtl92ce_set_bcn_ctrl_reg(hw, BIT(3), 0); | |
504 | ||
e10542c4 | 505 | if (btype_ibss) |
0c817338 LF |
506 | _rtl92ce_resume_tx_beacon(hw); |
507 | ||
508 | break; | |
509 | ||
510 | } | |
3a16b412 LF |
511 | case HW_VAR_FW_LPS_ACTION: { |
512 | bool enter_fwlps = *((bool *)val); | |
513 | u8 rpwm_val, fw_pwrmode; | |
514 | bool fw_current_inps; | |
515 | ||
516 | if (enter_fwlps) { | |
517 | rpwm_val = 0x02; /* RF off */ | |
518 | fw_current_inps = true; | |
519 | rtlpriv->cfg->ops->set_hw_reg(hw, | |
520 | HW_VAR_FW_PSMODE_STATUS, | |
521 | (u8 *)(&fw_current_inps)); | |
522 | rtlpriv->cfg->ops->set_hw_reg(hw, | |
523 | HW_VAR_H2C_FW_PWRMODE, | |
524 | (u8 *)(&ppsc->fwctrl_psmode)); | |
525 | ||
526 | rtlpriv->cfg->ops->set_hw_reg(hw, | |
527 | HW_VAR_SET_RPWM, | |
528 | (u8 *)(&rpwm_val)); | |
529 | } else { | |
530 | rpwm_val = 0x0C; /* RF on */ | |
531 | fw_pwrmode = FW_PS_ACTIVE_MODE; | |
532 | fw_current_inps = false; | |
533 | rtlpriv->cfg->ops->set_hw_reg(hw, | |
534 | HW_VAR_SET_RPWM, | |
535 | (u8 *)(&rpwm_val)); | |
536 | rtlpriv->cfg->ops->set_hw_reg(hw, | |
537 | HW_VAR_H2C_FW_PWRMODE, | |
538 | (u8 *)(&fw_pwrmode)); | |
539 | ||
540 | rtlpriv->cfg->ops->set_hw_reg(hw, | |
541 | HW_VAR_FW_PSMODE_STATUS, | |
542 | (u8 *)(&fw_current_inps)); | |
543 | } | |
544 | break; } | |
0c817338 | 545 | default: |
f30d7507 JP |
546 | RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG, |
547 | "switch case not processed\n"); | |
0c817338 LF |
548 | break; |
549 | } | |
550 | } | |
551 | ||
552 | static bool _rtl92ce_llt_write(struct ieee80211_hw *hw, u32 address, u32 data) | |
553 | { | |
554 | struct rtl_priv *rtlpriv = rtl_priv(hw); | |
555 | bool status = true; | |
556 | long count = 0; | |
557 | u32 value = _LLT_INIT_ADDR(address) | | |
558 | _LLT_INIT_DATA(data) | _LLT_OP(_LLT_WRITE_ACCESS); | |
559 | ||
560 | rtl_write_dword(rtlpriv, REG_LLT_INIT, value); | |
561 | ||
562 | do { | |
563 | value = rtl_read_dword(rtlpriv, REG_LLT_INIT); | |
564 | if (_LLT_NO_ACTIVE == _LLT_OP_VALUE(value)) | |
565 | break; | |
566 | ||
567 | if (count > POLLING_LLT_THRESHOLD) { | |
568 | RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG, | |
f30d7507 JP |
569 | "Failed to polling write LLT done at address %d!\n", |
570 | address); | |
0c817338 LF |
571 | status = false; |
572 | break; | |
573 | } | |
574 | } while (++count); | |
575 | ||
576 | return status; | |
577 | } | |
578 | ||
579 | static bool _rtl92ce_llt_table_init(struct ieee80211_hw *hw) | |
580 | { | |
581 | struct rtl_priv *rtlpriv = rtl_priv(hw); | |
582 | unsigned short i; | |
583 | u8 txpktbuf_bndy; | |
584 | u8 maxPage; | |
585 | bool status; | |
586 | ||
587 | #if LLT_CONFIG == 1 | |
588 | maxPage = 255; | |
589 | txpktbuf_bndy = 252; | |
590 | #elif LLT_CONFIG == 2 | |
591 | maxPage = 127; | |
592 | txpktbuf_bndy = 124; | |
593 | #elif LLT_CONFIG == 3 | |
594 | maxPage = 255; | |
595 | txpktbuf_bndy = 174; | |
596 | #elif LLT_CONFIG == 4 | |
597 | maxPage = 255; | |
598 | txpktbuf_bndy = 246; | |
599 | #elif LLT_CONFIG == 5 | |
600 | maxPage = 255; | |
601 | txpktbuf_bndy = 246; | |
602 | #endif | |
603 | ||
604 | #if LLT_CONFIG == 1 | |
605 | rtl_write_byte(rtlpriv, REG_RQPN_NPQ, 0x1c); | |
606 | rtl_write_dword(rtlpriv, REG_RQPN, 0x80a71c1c); | |
607 | #elif LLT_CONFIG == 2 | |
608 | rtl_write_dword(rtlpriv, REG_RQPN, 0x845B1010); | |
609 | #elif LLT_CONFIG == 3 | |
610 | rtl_write_dword(rtlpriv, REG_RQPN, 0x84838484); | |
611 | #elif LLT_CONFIG == 4 | |
612 | rtl_write_dword(rtlpriv, REG_RQPN, 0x80bd1c1c); | |
613 | #elif LLT_CONFIG == 5 | |
614 | rtl_write_word(rtlpriv, REG_RQPN_NPQ, 0x0000); | |
615 | ||
616 | rtl_write_dword(rtlpriv, REG_RQPN, 0x80b01c29); | |
617 | #endif | |
618 | ||
619 | rtl_write_dword(rtlpriv, REG_TRXFF_BNDY, (0x27FF0000 | txpktbuf_bndy)); | |
620 | rtl_write_byte(rtlpriv, REG_TDECTRL + 1, txpktbuf_bndy); | |
621 | ||
622 | rtl_write_byte(rtlpriv, REG_TXPKTBUF_BCNQ_BDNY, txpktbuf_bndy); | |
623 | rtl_write_byte(rtlpriv, REG_TXPKTBUF_MGQ_BDNY, txpktbuf_bndy); | |
624 | ||
625 | rtl_write_byte(rtlpriv, 0x45D, txpktbuf_bndy); | |
626 | rtl_write_byte(rtlpriv, REG_PBP, 0x11); | |
627 | rtl_write_byte(rtlpriv, REG_RX_DRVINFO_SZ, 0x4); | |
628 | ||
629 | for (i = 0; i < (txpktbuf_bndy - 1); i++) { | |
630 | status = _rtl92ce_llt_write(hw, i, i + 1); | |
631 | if (true != status) | |
632 | return status; | |
633 | } | |
634 | ||
635 | status = _rtl92ce_llt_write(hw, (txpktbuf_bndy - 1), 0xFF); | |
636 | if (true != status) | |
637 | return status; | |
638 | ||
639 | for (i = txpktbuf_bndy; i < maxPage; i++) { | |
640 | status = _rtl92ce_llt_write(hw, i, (i + 1)); | |
641 | if (true != status) | |
642 | return status; | |
643 | } | |
644 | ||
645 | status = _rtl92ce_llt_write(hw, maxPage, txpktbuf_bndy); | |
646 | if (true != status) | |
647 | return status; | |
648 | ||
649 | return true; | |
650 | } | |
651 | ||
652 | static void _rtl92ce_gen_refresh_led_state(struct ieee80211_hw *hw) | |
653 | { | |
654 | struct rtl_pci_priv *pcipriv = rtl_pcipriv(hw); | |
655 | struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw)); | |
656 | struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw)); | |
657 | struct rtl_led *pLed0 = &(pcipriv->ledctl.sw_led0); | |
658 | ||
659 | if (rtlpci->up_first_time) | |
660 | return; | |
661 | ||
662 | if (ppsc->rfoff_reason == RF_CHANGE_BY_IPS) | |
663 | rtl92ce_sw_led_on(hw, pLed0); | |
664 | else if (ppsc->rfoff_reason == RF_CHANGE_BY_INIT) | |
665 | rtl92ce_sw_led_on(hw, pLed0); | |
666 | else | |
667 | rtl92ce_sw_led_off(hw, pLed0); | |
0c817338 LF |
668 | } |
669 | ||
670 | static bool _rtl92ce_init_mac(struct ieee80211_hw *hw) | |
671 | { | |
672 | struct rtl_priv *rtlpriv = rtl_priv(hw); | |
f73b279c | 673 | struct rtl_pci_priv *rtlpcipriv = rtl_pcipriv(hw); |
0c817338 LF |
674 | struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw)); |
675 | struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw)); | |
676 | ||
677 | unsigned char bytetmp; | |
678 | unsigned short wordtmp; | |
679 | u16 retry; | |
680 | ||
681 | rtl_write_byte(rtlpriv, REG_RSV_CTRL, 0x00); | |
f73b279c C |
682 | if (rtlpcipriv->bt_coexist.bt_coexistence) { |
683 | u32 value32; | |
684 | value32 = rtl_read_dword(rtlpriv, REG_APS_FSMCO); | |
685 | value32 |= (SOP_ABG | SOP_AMB | XOP_BTCK); | |
686 | rtl_write_dword(rtlpriv, REG_APS_FSMCO, value32); | |
687 | } | |
0c817338 LF |
688 | rtl_write_byte(rtlpriv, REG_SPS0_CTRL, 0x2b); |
689 | rtl_write_byte(rtlpriv, REG_AFE_XTAL_CTRL, 0x0F); | |
690 | ||
f73b279c C |
691 | if (rtlpcipriv->bt_coexist.bt_coexistence) { |
692 | u32 u4b_tmp = rtl_read_dword(rtlpriv, REG_AFE_XTAL_CTRL); | |
693 | ||
694 | u4b_tmp &= (~0x00024800); | |
695 | rtl_write_dword(rtlpriv, REG_AFE_XTAL_CTRL, u4b_tmp); | |
696 | } | |
697 | ||
0c817338 LF |
698 | bytetmp = rtl_read_byte(rtlpriv, REG_APS_FSMCO + 1) | BIT(0); |
699 | udelay(2); | |
700 | ||
701 | rtl_write_byte(rtlpriv, REG_APS_FSMCO + 1, bytetmp); | |
702 | udelay(2); | |
703 | ||
704 | bytetmp = rtl_read_byte(rtlpriv, REG_APS_FSMCO + 1); | |
705 | udelay(2); | |
706 | ||
707 | retry = 0; | |
f30d7507 JP |
708 | RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, "reg0xec:%x:%x\n", |
709 | rtl_read_dword(rtlpriv, 0xEC), bytetmp); | |
0c817338 LF |
710 | |
711 | while ((bytetmp & BIT(0)) && retry < 1000) { | |
712 | retry++; | |
713 | udelay(50); | |
714 | bytetmp = rtl_read_byte(rtlpriv, REG_APS_FSMCO + 1); | |
f30d7507 JP |
715 | RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, "reg0xec:%x:%x\n", |
716 | rtl_read_dword(rtlpriv, 0xEC), bytetmp); | |
0c817338 LF |
717 | udelay(50); |
718 | } | |
719 | ||
720 | rtl_write_word(rtlpriv, REG_APS_FSMCO, 0x1012); | |
721 | ||
722 | rtl_write_byte(rtlpriv, REG_SYS_ISO_CTRL + 1, 0x82); | |
723 | udelay(2); | |
724 | ||
f73b279c C |
725 | if (rtlpcipriv->bt_coexist.bt_coexistence) { |
726 | bytetmp = rtl_read_byte(rtlpriv, REG_AFE_XTAL_CTRL+2) & 0xfd; | |
727 | rtl_write_byte(rtlpriv, REG_AFE_XTAL_CTRL+2, bytetmp); | |
728 | } | |
729 | ||
0c817338 LF |
730 | rtl_write_word(rtlpriv, REG_CR, 0x2ff); |
731 | ||
23677ce3 | 732 | if (!_rtl92ce_llt_table_init(hw)) |
6eab04a8 | 733 | return false; |
0c817338 LF |
734 | |
735 | rtl_write_dword(rtlpriv, REG_HISR, 0xffffffff); | |
736 | rtl_write_byte(rtlpriv, REG_HISRE, 0xff); | |
737 | ||
738 | rtl_write_word(rtlpriv, REG_TRXFF_BNDY + 2, 0x27ff); | |
739 | ||
740 | wordtmp = rtl_read_word(rtlpriv, REG_TRXDMA_CTRL); | |
741 | wordtmp &= 0xf; | |
742 | wordtmp |= 0xF771; | |
743 | rtl_write_word(rtlpriv, REG_TRXDMA_CTRL, wordtmp); | |
744 | ||
745 | rtl_write_byte(rtlpriv, REG_FWHW_TXQ_CTRL + 1, 0x1F); | |
746 | rtl_write_dword(rtlpriv, REG_RCR, rtlpci->receive_config); | |
747 | rtl_write_dword(rtlpriv, REG_TCR, rtlpci->transmit_config); | |
748 | ||
749 | rtl_write_byte(rtlpriv, 0x4d0, 0x0); | |
750 | ||
751 | rtl_write_dword(rtlpriv, REG_BCNQ_DESA, | |
752 | ((u64) rtlpci->tx_ring[BEACON_QUEUE].dma) & | |
753 | DMA_BIT_MASK(32)); | |
754 | rtl_write_dword(rtlpriv, REG_MGQ_DESA, | |
755 | (u64) rtlpci->tx_ring[MGNT_QUEUE].dma & | |
756 | DMA_BIT_MASK(32)); | |
757 | rtl_write_dword(rtlpriv, REG_VOQ_DESA, | |
758 | (u64) rtlpci->tx_ring[VO_QUEUE].dma & DMA_BIT_MASK(32)); | |
759 | rtl_write_dword(rtlpriv, REG_VIQ_DESA, | |
760 | (u64) rtlpci->tx_ring[VI_QUEUE].dma & DMA_BIT_MASK(32)); | |
761 | rtl_write_dword(rtlpriv, REG_BEQ_DESA, | |
762 | (u64) rtlpci->tx_ring[BE_QUEUE].dma & DMA_BIT_MASK(32)); | |
763 | rtl_write_dword(rtlpriv, REG_BKQ_DESA, | |
764 | (u64) rtlpci->tx_ring[BK_QUEUE].dma & DMA_BIT_MASK(32)); | |
765 | rtl_write_dword(rtlpriv, REG_HQ_DESA, | |
766 | (u64) rtlpci->tx_ring[HIGH_QUEUE].dma & | |
767 | DMA_BIT_MASK(32)); | |
768 | rtl_write_dword(rtlpriv, REG_RX_DESA, | |
769 | (u64) rtlpci->rx_ring[RX_MPDU_QUEUE].dma & | |
770 | DMA_BIT_MASK(32)); | |
771 | ||
772 | if (IS_92C_SERIAL(rtlhal->version)) | |
773 | rtl_write_byte(rtlpriv, REG_PCIE_CTRL_REG + 3, 0x77); | |
774 | else | |
775 | rtl_write_byte(rtlpriv, REG_PCIE_CTRL_REG + 3, 0x22); | |
776 | ||
777 | rtl_write_dword(rtlpriv, REG_INT_MIG, 0); | |
778 | ||
779 | bytetmp = rtl_read_byte(rtlpriv, REG_APSD_CTRL); | |
780 | rtl_write_byte(rtlpriv, REG_APSD_CTRL, bytetmp & ~BIT(6)); | |
781 | do { | |
782 | retry++; | |
783 | bytetmp = rtl_read_byte(rtlpriv, REG_APSD_CTRL); | |
784 | } while ((retry < 200) && (bytetmp & BIT(7))); | |
785 | ||
786 | _rtl92ce_gen_refresh_led_state(hw); | |
787 | ||
788 | rtl_write_dword(rtlpriv, REG_MCUTST_1, 0x0); | |
789 | ||
6eab04a8 | 790 | return true; |
0c817338 LF |
791 | } |
792 | ||
793 | static void _rtl92ce_hw_configure(struct ieee80211_hw *hw) | |
794 | { | |
795 | struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw)); | |
796 | struct rtl_priv *rtlpriv = rtl_priv(hw); | |
f73b279c | 797 | struct rtl_pci_priv *rtlpcipriv = rtl_pcipriv(hw); |
0c817338 | 798 | u8 reg_bw_opmode; |
6c0d4988 | 799 | u32 reg_prsr; |
0c817338 LF |
800 | |
801 | reg_bw_opmode = BW_OPMODE_20MHZ; | |
0c817338 LF |
802 | reg_prsr = RATE_ALL_CCK | RATE_ALL_OFDM_AG; |
803 | ||
804 | rtl_write_byte(rtlpriv, REG_INIRTS_RATE_SEL, 0x8); | |
805 | ||
806 | rtl_write_byte(rtlpriv, REG_BWOPMODE, reg_bw_opmode); | |
807 | ||
808 | rtl_write_dword(rtlpriv, REG_RRSR, reg_prsr); | |
809 | ||
810 | rtl_write_byte(rtlpriv, REG_SLOT, 0x09); | |
811 | ||
812 | rtl_write_byte(rtlpriv, REG_AMPDU_MIN_SPACE, 0x0); | |
813 | ||
814 | rtl_write_word(rtlpriv, REG_FWHW_TXQ_CTRL, 0x1F80); | |
815 | ||
816 | rtl_write_word(rtlpriv, REG_RL, 0x0707); | |
817 | ||
818 | rtl_write_dword(rtlpriv, REG_BAR_MODE_CTRL, 0x02012802); | |
819 | ||
820 | rtl_write_byte(rtlpriv, REG_HWSEQ_CTRL, 0xFF); | |
821 | ||
822 | rtl_write_dword(rtlpriv, REG_DARFRC, 0x01000000); | |
823 | rtl_write_dword(rtlpriv, REG_DARFRC + 4, 0x07060504); | |
824 | rtl_write_dword(rtlpriv, REG_RARFRC, 0x01000000); | |
825 | rtl_write_dword(rtlpriv, REG_RARFRC + 4, 0x07060504); | |
826 | ||
f73b279c C |
827 | if ((rtlpcipriv->bt_coexist.bt_coexistence) && |
828 | (rtlpcipriv->bt_coexist.bt_coexist_type == BT_CSR_BC4)) | |
829 | rtl_write_dword(rtlpriv, REG_AGGLEN_LMT, 0x97427431); | |
830 | else | |
831 | rtl_write_dword(rtlpriv, REG_AGGLEN_LMT, 0xb972a841); | |
0c817338 LF |
832 | |
833 | rtl_write_byte(rtlpriv, REG_ATIMWND, 0x2); | |
834 | ||
835 | rtl_write_byte(rtlpriv, REG_BCN_MAX_ERR, 0xff); | |
836 | ||
837 | rtlpci->reg_bcn_ctrl_val = 0x1f; | |
838 | rtl_write_byte(rtlpriv, REG_BCN_CTRL, rtlpci->reg_bcn_ctrl_val); | |
839 | ||
840 | rtl_write_byte(rtlpriv, REG_TBTT_PROHIBIT + 1, 0xff); | |
841 | ||
842 | rtl_write_byte(rtlpriv, REG_TBTT_PROHIBIT + 1, 0xff); | |
843 | ||
844 | rtl_write_byte(rtlpriv, REG_PIFS, 0x1C); | |
845 | rtl_write_byte(rtlpriv, REG_AGGR_BREAK_TIME, 0x16); | |
846 | ||
f73b279c C |
847 | if ((rtlpcipriv->bt_coexist.bt_coexistence) && |
848 | (rtlpcipriv->bt_coexist.bt_coexist_type == BT_CSR_BC4)) { | |
849 | rtl_write_word(rtlpriv, REG_NAV_PROT_LEN, 0x0020); | |
850 | rtl_write_word(rtlpriv, REG_PROT_MODE_CTRL, 0x0402); | |
851 | } else { | |
852 | rtl_write_word(rtlpriv, REG_NAV_PROT_LEN, 0x0020); | |
853 | rtl_write_word(rtlpriv, REG_NAV_PROT_LEN, 0x0020); | |
854 | } | |
0c817338 | 855 | |
f73b279c C |
856 | if ((rtlpcipriv->bt_coexist.bt_coexistence) && |
857 | (rtlpcipriv->bt_coexist.bt_coexist_type == BT_CSR_BC4)) | |
858 | rtl_write_dword(rtlpriv, REG_FAST_EDCA_CTRL, 0x03086666); | |
859 | else | |
860 | rtl_write_dword(rtlpriv, REG_FAST_EDCA_CTRL, 0x086666); | |
0c817338 LF |
861 | |
862 | rtl_write_byte(rtlpriv, REG_ACKTO, 0x40); | |
863 | ||
864 | rtl_write_word(rtlpriv, REG_SPEC_SIFS, 0x1010); | |
865 | rtl_write_word(rtlpriv, REG_MAC_SPEC_SIFS, 0x1010); | |
866 | ||
867 | rtl_write_word(rtlpriv, REG_SIFS_CTX, 0x1010); | |
868 | ||
869 | rtl_write_word(rtlpriv, REG_SIFS_TRX, 0x1010); | |
870 | ||
871 | rtl_write_dword(rtlpriv, REG_MAR, 0xffffffff); | |
872 | rtl_write_dword(rtlpriv, REG_MAR + 4, 0xffffffff); | |
873 | ||
874 | } | |
875 | ||
876 | static void _rtl92ce_enable_aspm_back_door(struct ieee80211_hw *hw) | |
877 | { | |
878 | struct rtl_priv *rtlpriv = rtl_priv(hw); | |
879 | struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw)); | |
880 | ||
881 | rtl_write_byte(rtlpriv, 0x34b, 0x93); | |
882 | rtl_write_word(rtlpriv, 0x350, 0x870c); | |
883 | rtl_write_byte(rtlpriv, 0x352, 0x1); | |
884 | ||
7ea47240 | 885 | if (ppsc->support_backdoor) |
0c817338 LF |
886 | rtl_write_byte(rtlpriv, 0x349, 0x1b); |
887 | else | |
888 | rtl_write_byte(rtlpriv, 0x349, 0x03); | |
889 | ||
890 | rtl_write_word(rtlpriv, 0x350, 0x2718); | |
891 | rtl_write_byte(rtlpriv, 0x352, 0x1); | |
892 | } | |
893 | ||
894 | void rtl92ce_enable_hw_security_config(struct ieee80211_hw *hw) | |
895 | { | |
896 | struct rtl_priv *rtlpriv = rtl_priv(hw); | |
897 | u8 sec_reg_value; | |
898 | ||
899 | RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, | |
f30d7507 JP |
900 | "PairwiseEncAlgorithm = %d GroupEncAlgorithm = %d\n", |
901 | rtlpriv->sec.pairwise_enc_algorithm, | |
902 | rtlpriv->sec.group_enc_algorithm); | |
0c817338 LF |
903 | |
904 | if (rtlpriv->cfg->mod_params->sw_crypto || rtlpriv->sec.use_sw_sec) { | |
f30d7507 JP |
905 | RT_TRACE(rtlpriv, COMP_SEC, DBG_DMESG, |
906 | "not open hw encryption\n"); | |
0c817338 LF |
907 | return; |
908 | } | |
909 | ||
910 | sec_reg_value = SCR_TxEncEnable | SCR_RxDecEnable; | |
911 | ||
912 | if (rtlpriv->sec.use_defaultkey) { | |
913 | sec_reg_value |= SCR_TxUseDK; | |
914 | sec_reg_value |= SCR_RxUseDK; | |
915 | } | |
916 | ||
917 | sec_reg_value |= (SCR_RXBCUSEDK | SCR_TXBCUSEDK); | |
918 | ||
919 | rtl_write_byte(rtlpriv, REG_CR + 1, 0x02); | |
920 | ||
921 | RT_TRACE(rtlpriv, COMP_SEC, DBG_LOUD, | |
f30d7507 | 922 | "The SECR-value %x\n", sec_reg_value); |
0c817338 LF |
923 | |
924 | rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_WPA_CONFIG, &sec_reg_value); | |
925 | ||
926 | } | |
927 | ||
928 | int rtl92ce_hw_init(struct ieee80211_hw *hw) | |
929 | { | |
930 | struct rtl_priv *rtlpriv = rtl_priv(hw); | |
931 | struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw)); | |
932 | struct rtl_mac *mac = rtl_mac(rtl_priv(hw)); | |
933 | struct rtl_phy *rtlphy = &(rtlpriv->phy); | |
934 | struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw)); | |
935 | struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw)); | |
0c817338 LF |
936 | bool rtstatus = true; |
937 | bool is92c; | |
938 | int err; | |
939 | u8 tmp_u1b; | |
f78bccd7 | 940 | unsigned long flags; |
0c817338 LF |
941 | |
942 | rtlpci->being_init_adapter = true; | |
f78bccd7 OL |
943 | |
944 | /* Since this function can take a very long time (up to 350 ms) | |
945 | * and can be called with irqs disabled, reenable the irqs | |
946 | * to let the other devices continue being serviced. | |
947 | * | |
948 | * It is safe doing so since our own interrupts will only be enabled | |
949 | * in a subsequent step. | |
950 | */ | |
951 | local_save_flags(flags); | |
952 | local_irq_enable(); | |
953 | ||
0c817338 LF |
954 | rtlpriv->intf_ops->disable_aspm(hw); |
955 | rtstatus = _rtl92ce_init_mac(hw); | |
23677ce3 | 956 | if (!rtstatus) { |
f30d7507 | 957 | RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG, "Init MAC failed\n"); |
0c817338 | 958 | err = 1; |
f78bccd7 | 959 | goto exit; |
0c817338 LF |
960 | } |
961 | ||
962 | err = rtl92c_download_fw(hw); | |
963 | if (err) { | |
964 | RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING, | |
f30d7507 | 965 | "Failed to download FW. Init HW without FW now..\n"); |
0c817338 | 966 | err = 1; |
f78bccd7 | 967 | goto exit; |
0c817338 LF |
968 | } |
969 | ||
970 | rtlhal->last_hmeboxnum = 0; | |
f73b279c | 971 | rtl92c_phy_mac_config(hw); |
0bd899e7 LF |
972 | /* because last function modify RCR, so we update |
973 | * rcr var here, or TP will unstable for receive_config | |
974 | * is wrong, RX RCR_ACRC32 will cause TP unstabel & Rx | |
975 | * RCR_APP_ICV will cause mac80211 unassoc for cisco 1252*/ | |
976 | rtlpci->receive_config = rtl_read_dword(rtlpriv, REG_RCR); | |
977 | rtlpci->receive_config &= ~(RCR_ACRC32 | RCR_AICV); | |
978 | rtl_write_dword(rtlpriv, REG_RCR, rtlpci->receive_config); | |
f73b279c | 979 | rtl92c_phy_bb_config(hw); |
0c817338 LF |
980 | rtlphy->rf_mode = RF_OP_BY_SW_3WIRE; |
981 | rtl92c_phy_rf_config(hw); | |
0bd899e7 LF |
982 | if (IS_VENDOR_UMC_A_CUT(rtlhal->version) && |
983 | !IS_92C_SERIAL(rtlhal->version)) { | |
984 | rtl_set_rfreg(hw, RF90_PATH_A, RF_RX_G1, MASKDWORD, 0x30255); | |
985 | rtl_set_rfreg(hw, RF90_PATH_A, RF_RX_G2, MASKDWORD, 0x50a00); | |
986 | } else if (IS_81xxC_VENDOR_UMC_B_CUT(rtlhal->version)) { | |
987 | rtl_set_rfreg(hw, RF90_PATH_A, 0x0C, MASKDWORD, 0x894AE); | |
988 | rtl_set_rfreg(hw, RF90_PATH_A, 0x0A, MASKDWORD, 0x1AF31); | |
989 | rtl_set_rfreg(hw, RF90_PATH_A, RF_IPA, MASKDWORD, 0x8F425); | |
990 | rtl_set_rfreg(hw, RF90_PATH_A, RF_SYN_G2, MASKDWORD, 0x4F200); | |
991 | rtl_set_rfreg(hw, RF90_PATH_A, RF_RCK1, MASKDWORD, 0x44053); | |
992 | rtl_set_rfreg(hw, RF90_PATH_A, RF_RCK2, MASKDWORD, 0x80201); | |
993 | } | |
0c817338 LF |
994 | rtlphy->rfreg_chnlval[0] = rtl_get_rfreg(hw, (enum radio_path)0, |
995 | RF_CHNLBW, RFREG_OFFSET_MASK); | |
996 | rtlphy->rfreg_chnlval[1] = rtl_get_rfreg(hw, (enum radio_path)1, | |
997 | RF_CHNLBW, RFREG_OFFSET_MASK); | |
998 | rtl_set_bbreg(hw, RFPGA0_RFMOD, BCCKEN, 0x1); | |
999 | rtl_set_bbreg(hw, RFPGA0_RFMOD, BOFDMEN, 0x1); | |
1000 | rtl_set_bbreg(hw, RFPGA0_ANALOGPARAMETER2, BIT(10), 1); | |
1001 | _rtl92ce_hw_configure(hw); | |
1002 | rtl_cam_reset_all_entry(hw); | |
1003 | rtl92ce_enable_hw_security_config(hw); | |
f73b279c | 1004 | |
0c817338 | 1005 | ppsc->rfpwr_state = ERFON; |
f73b279c | 1006 | |
0c817338 LF |
1007 | rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_ETHER_ADDR, mac->mac_addr); |
1008 | _rtl92ce_enable_aspm_back_door(hw); | |
1009 | rtlpriv->intf_ops->enable_aspm(hw); | |
f73b279c C |
1010 | |
1011 | rtl8192ce_bt_hw_init(hw); | |
1012 | ||
0c817338 LF |
1013 | if (ppsc->rfpwr_state == ERFON) { |
1014 | rtl92c_phy_set_rfpath_switch(hw, 1); | |
0bd899e7 | 1015 | if (rtlphy->iqk_initialized) { |
0c817338 | 1016 | rtl92c_phy_iq_calibrate(hw, true); |
f73b279c | 1017 | } else { |
0c817338 | 1018 | rtl92c_phy_iq_calibrate(hw, false); |
0bd899e7 | 1019 | rtlphy->iqk_initialized = true; |
0c817338 LF |
1020 | } |
1021 | ||
1022 | rtl92c_dm_check_txpower_tracking(hw); | |
1023 | rtl92c_phy_lc_calibrate(hw); | |
1024 | } | |
1025 | ||
1026 | is92c = IS_92C_SERIAL(rtlhal->version); | |
1027 | tmp_u1b = efuse_read_1byte(hw, 0x1FA); | |
1028 | if (!(tmp_u1b & BIT(0))) { | |
1029 | rtl_set_rfreg(hw, RF90_PATH_A, 0x15, 0x0F, 0x05); | |
f30d7507 | 1030 | RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE, "PA BIAS path A\n"); |
0c817338 LF |
1031 | } |
1032 | ||
1033 | if (!(tmp_u1b & BIT(1)) && is92c) { | |
1034 | rtl_set_rfreg(hw, RF90_PATH_B, 0x15, 0x0F, 0x05); | |
f30d7507 | 1035 | RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE, "PA BIAS path B\n"); |
0c817338 LF |
1036 | } |
1037 | ||
1038 | if (!(tmp_u1b & BIT(4))) { | |
1039 | tmp_u1b = rtl_read_byte(rtlpriv, 0x16); | |
1040 | tmp_u1b &= 0x0F; | |
1041 | rtl_write_byte(rtlpriv, 0x16, tmp_u1b | 0x80); | |
1042 | udelay(10); | |
1043 | rtl_write_byte(rtlpriv, 0x16, tmp_u1b | 0x90); | |
f30d7507 | 1044 | RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE, "under 1.5V\n"); |
0c817338 LF |
1045 | } |
1046 | rtl92c_dm_init(hw); | |
f78bccd7 OL |
1047 | exit: |
1048 | local_irq_restore(flags); | |
0c817338 LF |
1049 | rtlpci->being_init_adapter = false; |
1050 | return err; | |
1051 | } | |
1052 | ||
1053 | static enum version_8192c _rtl92ce_read_chip_version(struct ieee80211_hw *hw) | |
1054 | { | |
1055 | struct rtl_priv *rtlpriv = rtl_priv(hw); | |
1056 | struct rtl_phy *rtlphy = &(rtlpriv->phy); | |
1057 | enum version_8192c version = VERSION_UNKNOWN; | |
1058 | u32 value32; | |
07839b14 | 1059 | const char *versionid; |
0c817338 LF |
1060 | |
1061 | value32 = rtl_read_dword(rtlpriv, REG_SYS_CFG); | |
1062 | if (value32 & TRP_VAUX_EN) { | |
1063 | version = (value32 & TYPE_ID) ? VERSION_A_CHIP_92C : | |
1064 | VERSION_A_CHIP_88C; | |
1065 | } else { | |
022e1d06 LF |
1066 | version = (enum version_8192c) (CHIP_VER_B | |
1067 | ((value32 & TYPE_ID) ? CHIP_92C_BITMASK : 0) | | |
1068 | ((value32 & VENDOR_ID) ? CHIP_VENDOR_UMC : 0)); | |
1069 | if ((!IS_CHIP_VENDOR_UMC(version)) && (value32 & | |
1070 | CHIP_VER_RTL_MASK)) { | |
1071 | version = (enum version_8192c)(version | | |
1072 | ((((value32 & CHIP_VER_RTL_MASK) == BIT(12)) | |
1073 | ? CHIP_VENDOR_UMC_B_CUT : CHIP_UNKNOWN) | | |
1074 | CHIP_VENDOR_UMC)); | |
1075 | } | |
0bd899e7 LF |
1076 | if (IS_92C_SERIAL(version)) { |
1077 | value32 = rtl_read_dword(rtlpriv, REG_HPON_FSM); | |
1078 | version = (enum version_8192c)(version | | |
1079 | ((CHIP_BONDING_IDENTIFIER(value32) | |
1080 | == CHIP_BONDING_92C_1T2R) ? | |
1081 | RF_TYPE_1T2R : 0)); | |
1082 | } | |
0c817338 LF |
1083 | } |
1084 | ||
1085 | switch (version) { | |
1086 | case VERSION_B_CHIP_92C: | |
07839b14 | 1087 | versionid = "B_CHIP_92C"; |
0c817338 LF |
1088 | break; |
1089 | case VERSION_B_CHIP_88C: | |
07839b14 | 1090 | versionid = "B_CHIP_88C"; |
0c817338 LF |
1091 | break; |
1092 | case VERSION_A_CHIP_92C: | |
07839b14 | 1093 | versionid = "A_CHIP_92C"; |
0c817338 LF |
1094 | break; |
1095 | case VERSION_A_CHIP_88C: | |
07839b14 | 1096 | versionid = "A_CHIP_88C"; |
0c817338 | 1097 | break; |
0bd899e7 LF |
1098 | case VERSION_NORMAL_UMC_CHIP_92C_1T2R_A_CUT: |
1099 | versionid = "A_CUT_92C_1T2R"; | |
1100 | break; | |
1101 | case VERSION_NORMAL_UMC_CHIP_92C_A_CUT: | |
1102 | versionid = "A_CUT_92C"; | |
1103 | break; | |
1104 | case VERSION_NORMAL_UMC_CHIP_88C_A_CUT: | |
1105 | versionid = "A_CUT_88C"; | |
1106 | break; | |
1107 | case VERSION_NORMAL_UMC_CHIP_92C_1T2R_B_CUT: | |
1108 | versionid = "B_CUT_92C_1T2R"; | |
1109 | break; | |
1110 | case VERSION_NORMAL_UMC_CHIP_92C_B_CUT: | |
1111 | versionid = "B_CUT_92C"; | |
1112 | break; | |
1113 | case VERSION_NORMAL_UMC_CHIP_88C_B_CUT: | |
1114 | versionid = "B_CUT_88C"; | |
1115 | break; | |
0c817338 | 1116 | default: |
07839b14 | 1117 | versionid = "Unknown. Bug?"; |
0c817338 LF |
1118 | break; |
1119 | } | |
1120 | ||
0bd899e7 | 1121 | RT_TRACE(rtlpriv, COMP_INIT, DBG_EMERG, |
07839b14 JP |
1122 | "Chip Version ID: %s\n", versionid); |
1123 | ||
0c817338 LF |
1124 | switch (version & 0x3) { |
1125 | case CHIP_88C: | |
1126 | rtlphy->rf_type = RF_1T1R; | |
1127 | break; | |
1128 | case CHIP_92C: | |
1129 | rtlphy->rf_type = RF_2T2R; | |
1130 | break; | |
1131 | case CHIP_92C_1T2R: | |
1132 | rtlphy->rf_type = RF_1T2R; | |
1133 | break; | |
1134 | default: | |
1135 | rtlphy->rf_type = RF_1T1R; | |
1136 | RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG, | |
f30d7507 | 1137 | "ERROR RF_Type is set!!\n"); |
0c817338 LF |
1138 | break; |
1139 | } | |
1140 | ||
f30d7507 JP |
1141 | RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, "Chip RF Type: %s\n", |
1142 | rtlphy->rf_type == RF_2T2R ? "RF_2T2R" : "RF_1T1R"); | |
0c817338 LF |
1143 | |
1144 | return version; | |
1145 | } | |
1146 | ||
1147 | static int _rtl92ce_set_media_status(struct ieee80211_hw *hw, | |
1148 | enum nl80211_iftype type) | |
1149 | { | |
1150 | struct rtl_priv *rtlpriv = rtl_priv(hw); | |
1151 | u8 bt_msr = rtl_read_byte(rtlpriv, MSR); | |
1152 | enum led_ctl_mode ledaction = LED_CTL_NO_LINK; | |
1153 | bt_msr &= 0xfc; | |
1154 | ||
1155 | if (type == NL80211_IFTYPE_UNSPECIFIED || | |
1156 | type == NL80211_IFTYPE_STATION) { | |
1157 | _rtl92ce_stop_tx_beacon(hw); | |
1158 | _rtl92ce_enable_bcn_sub_func(hw); | |
3a16b412 LF |
1159 | } else if (type == NL80211_IFTYPE_ADHOC || type == NL80211_IFTYPE_AP || |
1160 | type == NL80211_IFTYPE_MESH_POINT) { | |
0c817338 LF |
1161 | _rtl92ce_resume_tx_beacon(hw); |
1162 | _rtl92ce_disable_bcn_sub_func(hw); | |
1163 | } else { | |
1164 | RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING, | |
f30d7507 JP |
1165 | "Set HW_VAR_MEDIA_STATUS: No such media status(%x)\n", |
1166 | type); | |
0c817338 LF |
1167 | } |
1168 | ||
1169 | switch (type) { | |
1170 | case NL80211_IFTYPE_UNSPECIFIED: | |
1171 | bt_msr |= MSR_NOLINK; | |
1172 | ledaction = LED_CTL_LINK; | |
1173 | RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE, | |
f30d7507 | 1174 | "Set Network type to NO LINK!\n"); |
0c817338 LF |
1175 | break; |
1176 | case NL80211_IFTYPE_ADHOC: | |
1177 | bt_msr |= MSR_ADHOC; | |
1178 | RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE, | |
f30d7507 | 1179 | "Set Network type to Ad Hoc!\n"); |
0c817338 LF |
1180 | break; |
1181 | case NL80211_IFTYPE_STATION: | |
1182 | bt_msr |= MSR_INFRA; | |
1183 | ledaction = LED_CTL_LINK; | |
1184 | RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE, | |
f30d7507 | 1185 | "Set Network type to STA!\n"); |
0c817338 LF |
1186 | break; |
1187 | case NL80211_IFTYPE_AP: | |
1188 | bt_msr |= MSR_AP; | |
1189 | RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE, | |
f30d7507 | 1190 | "Set Network type to AP!\n"); |
0c817338 | 1191 | break; |
3a16b412 LF |
1192 | case NL80211_IFTYPE_MESH_POINT: |
1193 | bt_msr |= MSR_ADHOC; | |
1194 | RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE, | |
1195 | "Set Network type to Mesh Point!\n"); | |
1196 | break; | |
0c817338 LF |
1197 | default: |
1198 | RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG, | |
f30d7507 | 1199 | "Network type %d not supported!\n", type); |
0c817338 LF |
1200 | return 1; |
1201 | break; | |
1202 | ||
1203 | } | |
1204 | ||
1205 | rtl_write_byte(rtlpriv, (MSR), bt_msr); | |
1206 | rtlpriv->cfg->ops->led_control(hw, ledaction); | |
1207 | if ((bt_msr & 0xfc) == MSR_AP) | |
1208 | rtl_write_byte(rtlpriv, REG_BCNTCFG + 1, 0x00); | |
1209 | else | |
1210 | rtl_write_byte(rtlpriv, REG_BCNTCFG + 1, 0x66); | |
1211 | return 0; | |
1212 | } | |
1213 | ||
f73b279c | 1214 | void rtl92ce_set_check_bssid(struct ieee80211_hw *hw, bool check_bssid) |
0c817338 LF |
1215 | { |
1216 | struct rtl_priv *rtlpriv = rtl_priv(hw); | |
1217 | u32 reg_rcr = rtl_read_dword(rtlpriv, REG_RCR); | |
0c817338 | 1218 | |
f73b279c C |
1219 | if (rtlpriv->psc.rfpwr_state != ERFON) |
1220 | return; | |
0c817338 | 1221 | |
e10542c4 | 1222 | if (check_bssid) { |
0c817338 LF |
1223 | reg_rcr |= (RCR_CBSSID_DATA | RCR_CBSSID_BCN); |
1224 | rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_RCR, | |
1225 | (u8 *) (®_rcr)); | |
1226 | _rtl92ce_set_bcn_ctrl_reg(hw, 0, BIT(4)); | |
23677ce3 | 1227 | } else if (!check_bssid) { |
0c817338 LF |
1228 | reg_rcr &= (~(RCR_CBSSID_DATA | RCR_CBSSID_BCN)); |
1229 | _rtl92ce_set_bcn_ctrl_reg(hw, BIT(4), 0); | |
1230 | rtlpriv->cfg->ops->set_hw_reg(hw, | |
1231 | HW_VAR_RCR, (u8 *) (®_rcr)); | |
1232 | } | |
f73b279c | 1233 | |
0c817338 LF |
1234 | } |
1235 | ||
1236 | int rtl92ce_set_network_type(struct ieee80211_hw *hw, enum nl80211_iftype type) | |
1237 | { | |
f73b279c C |
1238 | struct rtl_priv *rtlpriv = rtl_priv(hw); |
1239 | ||
0c817338 LF |
1240 | if (_rtl92ce_set_media_status(hw, type)) |
1241 | return -EOPNOTSUPP; | |
f73b279c C |
1242 | |
1243 | if (rtlpriv->mac80211.link_state == MAC80211_LINKED) { | |
3a16b412 LF |
1244 | if (type != NL80211_IFTYPE_AP && |
1245 | type != NL80211_IFTYPE_MESH_POINT) | |
f73b279c C |
1246 | rtl92ce_set_check_bssid(hw, true); |
1247 | } else { | |
1248 | rtl92ce_set_check_bssid(hw, false); | |
1249 | } | |
1250 | ||
0c817338 LF |
1251 | return 0; |
1252 | } | |
1253 | ||
f73b279c | 1254 | /* don't set REG_EDCA_BE_PARAM here because mac80211 will send pkt when scan */ |
0c817338 LF |
1255 | void rtl92ce_set_qos(struct ieee80211_hw *hw, int aci) |
1256 | { | |
1257 | struct rtl_priv *rtlpriv = rtl_priv(hw); | |
0c817338 | 1258 | rtl92c_dm_init_edca_turbo(hw); |
0c817338 LF |
1259 | switch (aci) { |
1260 | case AC1_BK: | |
f73b279c | 1261 | rtl_write_dword(rtlpriv, REG_EDCA_BK_PARAM, 0xa44f); |
0c817338 LF |
1262 | break; |
1263 | case AC0_BE: | |
f73b279c | 1264 | /* rtl_write_dword(rtlpriv, REG_EDCA_BE_PARAM, u4b_ac_param); */ |
0c817338 LF |
1265 | break; |
1266 | case AC2_VI: | |
f73b279c | 1267 | rtl_write_dword(rtlpriv, REG_EDCA_VI_PARAM, 0x5e4322); |
0c817338 LF |
1268 | break; |
1269 | case AC3_VO: | |
f73b279c | 1270 | rtl_write_dword(rtlpriv, REG_EDCA_VO_PARAM, 0x2f3222); |
0c817338 LF |
1271 | break; |
1272 | default: | |
9d833ed7 | 1273 | RT_ASSERT(false, "invalid aci: %d !\n", aci); |
0c817338 LF |
1274 | break; |
1275 | } | |
1276 | } | |
1277 | ||
1278 | void rtl92ce_enable_interrupt(struct ieee80211_hw *hw) | |
1279 | { | |
1280 | struct rtl_priv *rtlpriv = rtl_priv(hw); | |
1281 | struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw)); | |
1282 | ||
1283 | rtl_write_dword(rtlpriv, REG_HIMR, rtlpci->irq_mask[0] & 0xFFFFFFFF); | |
1284 | rtl_write_dword(rtlpriv, REG_HIMRE, rtlpci->irq_mask[1] & 0xFFFFFFFF); | |
0c817338 LF |
1285 | } |
1286 | ||
1287 | void rtl92ce_disable_interrupt(struct ieee80211_hw *hw) | |
1288 | { | |
1289 | struct rtl_priv *rtlpriv = rtl_priv(hw); | |
1290 | struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw)); | |
1291 | ||
1292 | rtl_write_dword(rtlpriv, REG_HIMR, IMR8190_DISABLED); | |
1293 | rtl_write_dword(rtlpriv, REG_HIMRE, IMR8190_DISABLED); | |
2e69167c | 1294 | synchronize_irq(rtlpci->pdev->irq); |
0c817338 LF |
1295 | } |
1296 | ||
1297 | static void _rtl92ce_poweroff_adapter(struct ieee80211_hw *hw) | |
1298 | { | |
1299 | struct rtl_priv *rtlpriv = rtl_priv(hw); | |
f73b279c | 1300 | struct rtl_pci_priv *rtlpcipriv = rtl_pcipriv(hw); |
0bd899e7 | 1301 | struct rtl_hal *rtlhal = rtl_hal(rtlpriv); |
0c817338 | 1302 | u8 u1b_tmp; |
f73b279c | 1303 | u32 u4b_tmp; |
0c817338 LF |
1304 | |
1305 | rtlpriv->intf_ops->enable_aspm(hw); | |
1306 | rtl_write_byte(rtlpriv, REG_TXPAUSE, 0xFF); | |
1307 | rtl_set_rfreg(hw, RF90_PATH_A, 0x00, RFREG_OFFSET_MASK, 0x00); | |
1308 | rtl_write_byte(rtlpriv, REG_RF_CTRL, 0x00); | |
1309 | rtl_write_byte(rtlpriv, REG_APSD_CTRL, 0x40); | |
1310 | rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN, 0xE2); | |
1311 | rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN, 0xE0); | |
b0302aba | 1312 | if (rtl_read_byte(rtlpriv, REG_MCUFWDL) & BIT(7)) |
0c817338 LF |
1313 | rtl92c_firmware_selfreset(hw); |
1314 | rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN + 1, 0x51); | |
1315 | rtl_write_byte(rtlpriv, REG_MCUFWDL, 0x00); | |
1316 | rtl_write_dword(rtlpriv, REG_GPIO_PIN_CTRL, 0x00000000); | |
1317 | u1b_tmp = rtl_read_byte(rtlpriv, REG_GPIO_PIN_CTRL); | |
f73b279c C |
1318 | if ((rtlpcipriv->bt_coexist.bt_coexistence) && |
1319 | ((rtlpcipriv->bt_coexist.bt_coexist_type == BT_CSR_BC4) || | |
1320 | (rtlpcipriv->bt_coexist.bt_coexist_type == BT_CSR_BC8))) { | |
1321 | rtl_write_dword(rtlpriv, REG_GPIO_PIN_CTRL, 0x00F30000 | | |
1322 | (u1b_tmp << 8)); | |
1323 | } else { | |
1324 | rtl_write_dword(rtlpriv, REG_GPIO_PIN_CTRL, 0x00FF0000 | | |
1325 | (u1b_tmp << 8)); | |
1326 | } | |
0c817338 LF |
1327 | rtl_write_word(rtlpriv, REG_GPIO_IO_SEL, 0x0790); |
1328 | rtl_write_word(rtlpriv, REG_LEDCFG0, 0x8080); | |
1329 | rtl_write_byte(rtlpriv, REG_AFE_PLL_CTRL, 0x80); | |
0bd899e7 LF |
1330 | if (!IS_81xxC_VENDOR_UMC_B_CUT(rtlhal->version)) |
1331 | rtl_write_byte(rtlpriv, REG_SPS0_CTRL, 0x23); | |
f73b279c C |
1332 | if (rtlpcipriv->bt_coexist.bt_coexistence) { |
1333 | u4b_tmp = rtl_read_dword(rtlpriv, REG_AFE_XTAL_CTRL); | |
1334 | u4b_tmp |= 0x03824800; | |
1335 | rtl_write_dword(rtlpriv, REG_AFE_XTAL_CTRL, u4b_tmp); | |
1336 | } else { | |
1337 | rtl_write_dword(rtlpriv, REG_AFE_XTAL_CTRL, 0x0e); | |
1338 | } | |
1339 | ||
0c817338 LF |
1340 | rtl_write_byte(rtlpriv, REG_RSV_CTRL, 0x0e); |
1341 | rtl_write_byte(rtlpriv, REG_APS_FSMCO + 1, 0x10); | |
1342 | } | |
1343 | ||
1344 | void rtl92ce_card_disable(struct ieee80211_hw *hw) | |
1345 | { | |
1346 | struct rtl_priv *rtlpriv = rtl_priv(hw); | |
1347 | struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw)); | |
1348 | struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw)); | |
1349 | struct rtl_mac *mac = rtl_mac(rtl_priv(hw)); | |
1350 | enum nl80211_iftype opmode; | |
1351 | ||
1352 | mac->link_state = MAC80211_NOLINK; | |
1353 | opmode = NL80211_IFTYPE_UNSPECIFIED; | |
1354 | _rtl92ce_set_media_status(hw, opmode); | |
1355 | if (rtlpci->driver_is_goingto_unload || | |
1356 | ppsc->rfoff_reason > RF_CHANGE_BY_PS) | |
1357 | rtlpriv->cfg->ops->led_control(hw, LED_CTL_POWER_OFF); | |
1358 | RT_SET_PS_LEVEL(ppsc, RT_RF_OFF_LEVL_HALT_NIC); | |
1359 | _rtl92ce_poweroff_adapter(hw); | |
0bd899e7 LF |
1360 | |
1361 | /* after power off we should do iqk again */ | |
1362 | rtlpriv->phy.iqk_initialized = false; | |
0c817338 LF |
1363 | } |
1364 | ||
1365 | void rtl92ce_interrupt_recognized(struct ieee80211_hw *hw, | |
1366 | u32 *p_inta, u32 *p_intb) | |
1367 | { | |
1368 | struct rtl_priv *rtlpriv = rtl_priv(hw); | |
1369 | struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw)); | |
1370 | ||
1371 | *p_inta = rtl_read_dword(rtlpriv, ISR) & rtlpci->irq_mask[0]; | |
1372 | rtl_write_dword(rtlpriv, ISR, *p_inta); | |
1373 | ||
1374 | /* | |
1375 | * *p_intb = rtl_read_dword(rtlpriv, REG_HISRE) & rtlpci->irq_mask[1]; | |
1376 | * rtl_write_dword(rtlpriv, ISR + 4, *p_intb); | |
1377 | */ | |
1378 | } | |
1379 | ||
1380 | void rtl92ce_set_beacon_related_registers(struct ieee80211_hw *hw) | |
1381 | { | |
1382 | ||
1383 | struct rtl_priv *rtlpriv = rtl_priv(hw); | |
1384 | struct rtl_mac *mac = rtl_mac(rtl_priv(hw)); | |
1385 | u16 bcn_interval, atim_window; | |
1386 | ||
1387 | bcn_interval = mac->beacon_interval; | |
1388 | atim_window = 2; /*FIX MERGE */ | |
1389 | rtl92ce_disable_interrupt(hw); | |
1390 | rtl_write_word(rtlpriv, REG_ATIMWND, atim_window); | |
1391 | rtl_write_word(rtlpriv, REG_BCN_INTERVAL, bcn_interval); | |
1392 | rtl_write_word(rtlpriv, REG_BCNTCFG, 0x660f); | |
1393 | rtl_write_byte(rtlpriv, REG_RXTSF_OFFSET_CCK, 0x18); | |
1394 | rtl_write_byte(rtlpriv, REG_RXTSF_OFFSET_OFDM, 0x18); | |
1395 | rtl_write_byte(rtlpriv, 0x606, 0x30); | |
1396 | rtl92ce_enable_interrupt(hw); | |
1397 | } | |
1398 | ||
1399 | void rtl92ce_set_beacon_interval(struct ieee80211_hw *hw) | |
1400 | { | |
1401 | struct rtl_priv *rtlpriv = rtl_priv(hw); | |
1402 | struct rtl_mac *mac = rtl_mac(rtl_priv(hw)); | |
1403 | u16 bcn_interval = mac->beacon_interval; | |
1404 | ||
1405 | RT_TRACE(rtlpriv, COMP_BEACON, DBG_DMESG, | |
f30d7507 | 1406 | "beacon_interval:%d\n", bcn_interval); |
0c817338 LF |
1407 | rtl92ce_disable_interrupt(hw); |
1408 | rtl_write_word(rtlpriv, REG_BCN_INTERVAL, bcn_interval); | |
1409 | rtl92ce_enable_interrupt(hw); | |
1410 | } | |
1411 | ||
1412 | void rtl92ce_update_interrupt_mask(struct ieee80211_hw *hw, | |
1413 | u32 add_msr, u32 rm_msr) | |
1414 | { | |
1415 | struct rtl_priv *rtlpriv = rtl_priv(hw); | |
1416 | struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw)); | |
1417 | ||
f30d7507 JP |
1418 | RT_TRACE(rtlpriv, COMP_INTR, DBG_LOUD, "add_msr:%x, rm_msr:%x\n", |
1419 | add_msr, rm_msr); | |
f73b279c | 1420 | |
0c817338 LF |
1421 | if (add_msr) |
1422 | rtlpci->irq_mask[0] |= add_msr; | |
1423 | if (rm_msr) | |
1424 | rtlpci->irq_mask[0] &= (~rm_msr); | |
1425 | rtl92ce_disable_interrupt(hw); | |
1426 | rtl92ce_enable_interrupt(hw); | |
1427 | } | |
1428 | ||
0c817338 LF |
1429 | static void _rtl92ce_read_txpower_info_from_hwpg(struct ieee80211_hw *hw, |
1430 | bool autoload_fail, | |
1431 | u8 *hwinfo) | |
1432 | { | |
1433 | struct rtl_priv *rtlpriv = rtl_priv(hw); | |
1434 | struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw)); | |
1435 | u8 rf_path, index, tempval; | |
1436 | u16 i; | |
1437 | ||
1438 | for (rf_path = 0; rf_path < 2; rf_path++) { | |
1439 | for (i = 0; i < 3; i++) { | |
1440 | if (!autoload_fail) { | |
1441 | rtlefuse-> | |
1442 | eeprom_chnlarea_txpwr_cck[rf_path][i] = | |
1443 | hwinfo[EEPROM_TXPOWERCCK + rf_path * 3 + i]; | |
1444 | rtlefuse-> | |
1445 | eeprom_chnlarea_txpwr_ht40_1s[rf_path][i] = | |
1446 | hwinfo[EEPROM_TXPOWERHT40_1S + rf_path * 3 + | |
1447 | i]; | |
1448 | } else { | |
1449 | rtlefuse-> | |
1450 | eeprom_chnlarea_txpwr_cck[rf_path][i] = | |
1451 | EEPROM_DEFAULT_TXPOWERLEVEL; | |
1452 | rtlefuse-> | |
1453 | eeprom_chnlarea_txpwr_ht40_1s[rf_path][i] = | |
1454 | EEPROM_DEFAULT_TXPOWERLEVEL; | |
1455 | } | |
1456 | } | |
1457 | } | |
1458 | ||
1459 | for (i = 0; i < 3; i++) { | |
1460 | if (!autoload_fail) | |
1461 | tempval = hwinfo[EEPROM_TXPOWERHT40_2SDIFF + i]; | |
1462 | else | |
1463 | tempval = EEPROM_DEFAULT_HT40_2SDIFF; | |
da17fcff | 1464 | rtlefuse->eprom_chnl_txpwr_ht40_2sdf[RF90_PATH_A][i] = |
0c817338 | 1465 | (tempval & 0xf); |
da17fcff | 1466 | rtlefuse->eprom_chnl_txpwr_ht40_2sdf[RF90_PATH_B][i] = |
0c817338 LF |
1467 | ((tempval & 0xf0) >> 4); |
1468 | } | |
1469 | ||
1470 | for (rf_path = 0; rf_path < 2; rf_path++) | |
1471 | for (i = 0; i < 3; i++) | |
1472 | RTPRINT(rtlpriv, FINIT, INIT_EEPROM, | |
4c48869f JP |
1473 | "RF(%d) EEPROM CCK Area(%d) = 0x%x\n", |
1474 | rf_path, i, | |
1475 | rtlefuse-> | |
1476 | eeprom_chnlarea_txpwr_cck[rf_path][i]); | |
0c817338 LF |
1477 | for (rf_path = 0; rf_path < 2; rf_path++) |
1478 | for (i = 0; i < 3; i++) | |
1479 | RTPRINT(rtlpriv, FINIT, INIT_EEPROM, | |
4c48869f JP |
1480 | "RF(%d) EEPROM HT40 1S Area(%d) = 0x%x\n", |
1481 | rf_path, i, | |
1482 | rtlefuse-> | |
1483 | eeprom_chnlarea_txpwr_ht40_1s[rf_path][i]); | |
0c817338 LF |
1484 | for (rf_path = 0; rf_path < 2; rf_path++) |
1485 | for (i = 0; i < 3; i++) | |
1486 | RTPRINT(rtlpriv, FINIT, INIT_EEPROM, | |
4c48869f JP |
1487 | "RF(%d) EEPROM HT40 2S Diff Area(%d) = 0x%x\n", |
1488 | rf_path, i, | |
1489 | rtlefuse-> | |
da17fcff | 1490 | eprom_chnl_txpwr_ht40_2sdf[rf_path][i]); |
0c817338 LF |
1491 | |
1492 | for (rf_path = 0; rf_path < 2; rf_path++) { | |
1493 | for (i = 0; i < 14; i++) { | |
1494 | index = _rtl92c_get_chnl_group((u8) i); | |
1495 | ||
1496 | rtlefuse->txpwrlevel_cck[rf_path][i] = | |
1497 | rtlefuse->eeprom_chnlarea_txpwr_cck[rf_path][index]; | |
1498 | rtlefuse->txpwrlevel_ht40_1s[rf_path][i] = | |
1499 | rtlefuse-> | |
1500 | eeprom_chnlarea_txpwr_ht40_1s[rf_path][index]; | |
1501 | ||
1502 | if ((rtlefuse-> | |
1503 | eeprom_chnlarea_txpwr_ht40_1s[rf_path][index] - | |
1504 | rtlefuse-> | |
da17fcff | 1505 | eprom_chnl_txpwr_ht40_2sdf[rf_path][index]) |
0c817338 LF |
1506 | > 0) { |
1507 | rtlefuse->txpwrlevel_ht40_2s[rf_path][i] = | |
1508 | rtlefuse-> | |
1509 | eeprom_chnlarea_txpwr_ht40_1s[rf_path] | |
1510 | [index] - | |
1511 | rtlefuse-> | |
da17fcff | 1512 | eprom_chnl_txpwr_ht40_2sdf[rf_path] |
0c817338 LF |
1513 | [index]; |
1514 | } else { | |
1515 | rtlefuse->txpwrlevel_ht40_2s[rf_path][i] = 0; | |
1516 | } | |
1517 | } | |
1518 | ||
1519 | for (i = 0; i < 14; i++) { | |
e6deaf81 | 1520 | RTPRINT(rtlpriv, FINIT, INIT_TXPOWER, |
4c48869f JP |
1521 | "RF(%d)-Ch(%d) [CCK / HT40_1S / HT40_2S] = [0x%x / 0x%x / 0x%x]\n", |
1522 | rf_path, i, | |
1523 | rtlefuse->txpwrlevel_cck[rf_path][i], | |
1524 | rtlefuse->txpwrlevel_ht40_1s[rf_path][i], | |
1525 | rtlefuse->txpwrlevel_ht40_2s[rf_path][i]); | |
0c817338 LF |
1526 | } |
1527 | } | |
1528 | ||
1529 | for (i = 0; i < 3; i++) { | |
1530 | if (!autoload_fail) { | |
1531 | rtlefuse->eeprom_pwrlimit_ht40[i] = | |
1532 | hwinfo[EEPROM_TXPWR_GROUP + i]; | |
1533 | rtlefuse->eeprom_pwrlimit_ht20[i] = | |
1534 | hwinfo[EEPROM_TXPWR_GROUP + 3 + i]; | |
1535 | } else { | |
1536 | rtlefuse->eeprom_pwrlimit_ht40[i] = 0; | |
1537 | rtlefuse->eeprom_pwrlimit_ht20[i] = 0; | |
1538 | } | |
1539 | } | |
1540 | ||
1541 | for (rf_path = 0; rf_path < 2; rf_path++) { | |
1542 | for (i = 0; i < 14; i++) { | |
1543 | index = _rtl92c_get_chnl_group((u8) i); | |
1544 | ||
1545 | if (rf_path == RF90_PATH_A) { | |
1546 | rtlefuse->pwrgroup_ht20[rf_path][i] = | |
1547 | (rtlefuse->eeprom_pwrlimit_ht20[index] | |
1548 | & 0xf); | |
1549 | rtlefuse->pwrgroup_ht40[rf_path][i] = | |
1550 | (rtlefuse->eeprom_pwrlimit_ht40[index] | |
1551 | & 0xf); | |
1552 | } else if (rf_path == RF90_PATH_B) { | |
1553 | rtlefuse->pwrgroup_ht20[rf_path][i] = | |
1554 | ((rtlefuse->eeprom_pwrlimit_ht20[index] | |
1555 | & 0xf0) >> 4); | |
1556 | rtlefuse->pwrgroup_ht40[rf_path][i] = | |
1557 | ((rtlefuse->eeprom_pwrlimit_ht40[index] | |
1558 | & 0xf0) >> 4); | |
1559 | } | |
1560 | ||
e6deaf81 | 1561 | RTPRINT(rtlpriv, FINIT, INIT_TXPOWER, |
4c48869f JP |
1562 | "RF-%d pwrgroup_ht20[%d] = 0x%x\n", |
1563 | rf_path, i, | |
1564 | rtlefuse->pwrgroup_ht20[rf_path][i]); | |
e6deaf81 | 1565 | RTPRINT(rtlpriv, FINIT, INIT_TXPOWER, |
4c48869f JP |
1566 | "RF-%d pwrgroup_ht40[%d] = 0x%x\n", |
1567 | rf_path, i, | |
1568 | rtlefuse->pwrgroup_ht40[rf_path][i]); | |
0c817338 LF |
1569 | } |
1570 | } | |
1571 | ||
1572 | for (i = 0; i < 14; i++) { | |
1573 | index = _rtl92c_get_chnl_group((u8) i); | |
1574 | ||
1575 | if (!autoload_fail) | |
1576 | tempval = hwinfo[EEPROM_TXPOWERHT20DIFF + index]; | |
1577 | else | |
1578 | tempval = EEPROM_DEFAULT_HT20_DIFF; | |
1579 | ||
1580 | rtlefuse->txpwr_ht20diff[RF90_PATH_A][i] = (tempval & 0xF); | |
1581 | rtlefuse->txpwr_ht20diff[RF90_PATH_B][i] = | |
1582 | ((tempval >> 4) & 0xF); | |
1583 | ||
1584 | if (rtlefuse->txpwr_ht20diff[RF90_PATH_A][i] & BIT(3)) | |
1585 | rtlefuse->txpwr_ht20diff[RF90_PATH_A][i] |= 0xF0; | |
1586 | ||
1587 | if (rtlefuse->txpwr_ht20diff[RF90_PATH_B][i] & BIT(3)) | |
1588 | rtlefuse->txpwr_ht20diff[RF90_PATH_B][i] |= 0xF0; | |
1589 | ||
1590 | index = _rtl92c_get_chnl_group((u8) i); | |
1591 | ||
1592 | if (!autoload_fail) | |
1593 | tempval = hwinfo[EEPROM_TXPOWER_OFDMDIFF + index]; | |
1594 | else | |
1595 | tempval = EEPROM_DEFAULT_LEGACYHTTXPOWERDIFF; | |
1596 | ||
1597 | rtlefuse->txpwr_legacyhtdiff[RF90_PATH_A][i] = (tempval & 0xF); | |
1598 | rtlefuse->txpwr_legacyhtdiff[RF90_PATH_B][i] = | |
1599 | ((tempval >> 4) & 0xF); | |
1600 | } | |
1601 | ||
1602 | rtlefuse->legacy_ht_txpowerdiff = | |
1603 | rtlefuse->txpwr_legacyhtdiff[RF90_PATH_A][7]; | |
1604 | ||
1605 | for (i = 0; i < 14; i++) | |
e6deaf81 | 1606 | RTPRINT(rtlpriv, FINIT, INIT_TXPOWER, |
4c48869f JP |
1607 | "RF-A Ht20 to HT40 Diff[%d] = 0x%x\n", |
1608 | i, rtlefuse->txpwr_ht20diff[RF90_PATH_A][i]); | |
0c817338 | 1609 | for (i = 0; i < 14; i++) |
e6deaf81 | 1610 | RTPRINT(rtlpriv, FINIT, INIT_TXPOWER, |
4c48869f JP |
1611 | "RF-A Legacy to Ht40 Diff[%d] = 0x%x\n", |
1612 | i, rtlefuse->txpwr_legacyhtdiff[RF90_PATH_A][i]); | |
0c817338 | 1613 | for (i = 0; i < 14; i++) |
e6deaf81 | 1614 | RTPRINT(rtlpriv, FINIT, INIT_TXPOWER, |
4c48869f JP |
1615 | "RF-B Ht20 to HT40 Diff[%d] = 0x%x\n", |
1616 | i, rtlefuse->txpwr_ht20diff[RF90_PATH_B][i]); | |
0c817338 | 1617 | for (i = 0; i < 14; i++) |
e6deaf81 | 1618 | RTPRINT(rtlpriv, FINIT, INIT_TXPOWER, |
4c48869f JP |
1619 | "RF-B Legacy to HT40 Diff[%d] = 0x%x\n", |
1620 | i, rtlefuse->txpwr_legacyhtdiff[RF90_PATH_B][i]); | |
0c817338 LF |
1621 | |
1622 | if (!autoload_fail) | |
1623 | rtlefuse->eeprom_regulatory = (hwinfo[RF_OPTION1] & 0x7); | |
1624 | else | |
1625 | rtlefuse->eeprom_regulatory = 0; | |
e6deaf81 | 1626 | RTPRINT(rtlpriv, FINIT, INIT_TXPOWER, |
4c48869f | 1627 | "eeprom_regulatory = 0x%x\n", rtlefuse->eeprom_regulatory); |
0c817338 LF |
1628 | |
1629 | if (!autoload_fail) { | |
1630 | rtlefuse->eeprom_tssi[RF90_PATH_A] = hwinfo[EEPROM_TSSI_A]; | |
1631 | rtlefuse->eeprom_tssi[RF90_PATH_B] = hwinfo[EEPROM_TSSI_B]; | |
1632 | } else { | |
1633 | rtlefuse->eeprom_tssi[RF90_PATH_A] = EEPROM_DEFAULT_TSSI; | |
1634 | rtlefuse->eeprom_tssi[RF90_PATH_B] = EEPROM_DEFAULT_TSSI; | |
1635 | } | |
e6deaf81 | 1636 | RTPRINT(rtlpriv, FINIT, INIT_TXPOWER, "TSSI_A = 0x%x, TSSI_B = 0x%x\n", |
4c48869f JP |
1637 | rtlefuse->eeprom_tssi[RF90_PATH_A], |
1638 | rtlefuse->eeprom_tssi[RF90_PATH_B]); | |
0c817338 LF |
1639 | |
1640 | if (!autoload_fail) | |
1641 | tempval = hwinfo[EEPROM_THERMAL_METER]; | |
1642 | else | |
1643 | tempval = EEPROM_DEFAULT_THERMALMETER; | |
1644 | rtlefuse->eeprom_thermalmeter = (tempval & 0x1f); | |
1645 | ||
1646 | if (rtlefuse->eeprom_thermalmeter == 0x1f || autoload_fail) | |
7ea47240 | 1647 | rtlefuse->apk_thermalmeterignore = true; |
0c817338 LF |
1648 | |
1649 | rtlefuse->thermalmeter[0] = rtlefuse->eeprom_thermalmeter; | |
e6deaf81 | 1650 | RTPRINT(rtlpriv, FINIT, INIT_TXPOWER, |
4c48869f | 1651 | "thermalmeter = 0x%x\n", rtlefuse->eeprom_thermalmeter); |
0c817338 LF |
1652 | } |
1653 | ||
1654 | static void _rtl92ce_read_adapter_info(struct ieee80211_hw *hw) | |
1655 | { | |
1656 | struct rtl_priv *rtlpriv = rtl_priv(hw); | |
1657 | struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw)); | |
1658 | struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw)); | |
1659 | u16 i, usvalue; | |
1660 | u8 hwinfo[HWSET_MAX_SIZE]; | |
1661 | u16 eeprom_id; | |
1662 | ||
1663 | if (rtlefuse->epromtype == EEPROM_BOOT_EFUSE) { | |
1664 | rtl_efuse_shadow_map_update(hw); | |
1665 | ||
1666 | memcpy((void *)hwinfo, | |
1667 | (void *)&rtlefuse->efuse_map[EFUSE_INIT_MAP][0], | |
1668 | HWSET_MAX_SIZE); | |
1669 | } else if (rtlefuse->epromtype == EEPROM_93C46) { | |
1670 | RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG, | |
f30d7507 | 1671 | "RTL819X Not boot from eeprom, check it !!"); |
0c817338 LF |
1672 | } |
1673 | ||
af08687b | 1674 | RT_PRINT_DATA(rtlpriv, COMP_INIT, DBG_DMESG, "MAP", |
0c817338 LF |
1675 | hwinfo, HWSET_MAX_SIZE); |
1676 | ||
1677 | eeprom_id = *((u16 *)&hwinfo[0]); | |
1678 | if (eeprom_id != RTL8190_EEPROM_ID) { | |
1679 | RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING, | |
f30d7507 | 1680 | "EEPROM ID(%#x) is invalid!!\n", eeprom_id); |
0c817338 LF |
1681 | rtlefuse->autoload_failflag = true; |
1682 | } else { | |
f30d7507 | 1683 | RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, "Autoload OK\n"); |
0c817338 LF |
1684 | rtlefuse->autoload_failflag = false; |
1685 | } | |
1686 | ||
e10542c4 | 1687 | if (rtlefuse->autoload_failflag) |
0c817338 LF |
1688 | return; |
1689 | ||
3a16b412 LF |
1690 | rtlefuse->eeprom_vid = *(u16 *)&hwinfo[EEPROM_VID]; |
1691 | rtlefuse->eeprom_did = *(u16 *)&hwinfo[EEPROM_DID]; | |
1692 | rtlefuse->eeprom_svid = *(u16 *)&hwinfo[EEPROM_SVID]; | |
1693 | rtlefuse->eeprom_smid = *(u16 *)&hwinfo[EEPROM_SMID]; | |
1694 | RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, | |
1695 | "EEPROMId = 0x%4x\n", eeprom_id); | |
1696 | RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, | |
1697 | "EEPROM VID = 0x%4x\n", rtlefuse->eeprom_vid); | |
1698 | RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, | |
1699 | "EEPROM DID = 0x%4x\n", rtlefuse->eeprom_did); | |
1700 | RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, | |
1701 | "EEPROM SVID = 0x%4x\n", rtlefuse->eeprom_svid); | |
1702 | RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, | |
1703 | "EEPROM SMID = 0x%4x\n", rtlefuse->eeprom_smid); | |
1704 | ||
0c817338 LF |
1705 | for (i = 0; i < 6; i += 2) { |
1706 | usvalue = *(u16 *)&hwinfo[EEPROM_MAC_ADDR + i]; | |
1707 | *((u16 *) (&rtlefuse->dev_addr[i])) = usvalue; | |
1708 | } | |
1709 | ||
f30d7507 | 1710 | RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG, "%pM\n", rtlefuse->dev_addr); |
0c817338 LF |
1711 | |
1712 | _rtl92ce_read_txpower_info_from_hwpg(hw, | |
1713 | rtlefuse->autoload_failflag, | |
1714 | hwinfo); | |
1715 | ||
f73b279c C |
1716 | rtl8192ce_read_bt_coexist_info_from_hwpg(hw, |
1717 | rtlefuse->autoload_failflag, | |
1718 | hwinfo); | |
1719 | ||
2c208890 | 1720 | rtlefuse->eeprom_channelplan = *&hwinfo[EEPROM_CHANNELPLAN]; |
0c817338 | 1721 | rtlefuse->eeprom_version = *(u16 *)&hwinfo[EEPROM_VERSION]; |
7ea47240 | 1722 | rtlefuse->txpwr_fromeprom = true; |
2c208890 | 1723 | rtlefuse->eeprom_oemid = *&hwinfo[EEPROM_CUSTOMER_ID]; |
0c817338 LF |
1724 | |
1725 | RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, | |
f30d7507 | 1726 | "EEPROM Customer ID: 0x%2x\n", rtlefuse->eeprom_oemid); |
0c817338 | 1727 | |
f73b279c C |
1728 | /* set channel paln to world wide 13 */ |
1729 | rtlefuse->channel_plan = COUNTRY_CODE_WORLD_WIDE_13; | |
1730 | ||
0c817338 LF |
1731 | if (rtlhal->oem_id == RT_CID_DEFAULT) { |
1732 | switch (rtlefuse->eeprom_oemid) { | |
1733 | case EEPROM_CID_DEFAULT: | |
1734 | if (rtlefuse->eeprom_did == 0x8176) { | |
1735 | if ((rtlefuse->eeprom_svid == 0x103C && | |
1736 | rtlefuse->eeprom_smid == 0x1629)) | |
1737 | rtlhal->oem_id = RT_CID_819x_HP; | |
1738 | else | |
1739 | rtlhal->oem_id = RT_CID_DEFAULT; | |
1740 | } else { | |
1741 | rtlhal->oem_id = RT_CID_DEFAULT; | |
1742 | } | |
1743 | break; | |
1744 | case EEPROM_CID_TOSHIBA: | |
1745 | rtlhal->oem_id = RT_CID_TOSHIBA; | |
1746 | break; | |
1747 | case EEPROM_CID_QMI: | |
1748 | rtlhal->oem_id = RT_CID_819x_QMI; | |
1749 | break; | |
1750 | case EEPROM_CID_WHQL: | |
1751 | default: | |
1752 | rtlhal->oem_id = RT_CID_DEFAULT; | |
1753 | break; | |
1754 | ||
1755 | } | |
1756 | } | |
1757 | ||
1758 | } | |
1759 | ||
1760 | static void _rtl92ce_hal_customized_behavior(struct ieee80211_hw *hw) | |
1761 | { | |
1762 | struct rtl_priv *rtlpriv = rtl_priv(hw); | |
1763 | struct rtl_pci_priv *pcipriv = rtl_pcipriv(hw); | |
1764 | struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw)); | |
1765 | ||
1766 | switch (rtlhal->oem_id) { | |
1767 | case RT_CID_819x_HP: | |
7ea47240 | 1768 | pcipriv->ledctl.led_opendrain = true; |
0c817338 LF |
1769 | break; |
1770 | case RT_CID_819x_Lenovo: | |
1771 | case RT_CID_DEFAULT: | |
1772 | case RT_CID_TOSHIBA: | |
1773 | case RT_CID_CCX: | |
1774 | case RT_CID_819x_Acer: | |
1775 | case RT_CID_WHQL: | |
1776 | default: | |
1777 | break; | |
1778 | } | |
1779 | RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG, | |
f30d7507 | 1780 | "RT Customized ID: 0x%02X\n", rtlhal->oem_id); |
0c817338 LF |
1781 | } |
1782 | ||
1783 | void rtl92ce_read_eeprom_info(struct ieee80211_hw *hw) | |
1784 | { | |
1785 | struct rtl_priv *rtlpriv = rtl_priv(hw); | |
1786 | struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw)); | |
1787 | struct rtl_phy *rtlphy = &(rtlpriv->phy); | |
1788 | struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw)); | |
1789 | u8 tmp_u1b; | |
1790 | ||
1791 | rtlhal->version = _rtl92ce_read_chip_version(hw); | |
1792 | if (get_rf_type(rtlphy) == RF_1T1R) | |
7ea47240 | 1793 | rtlpriv->dm.rfpath_rxenable[0] = true; |
0c817338 | 1794 | else |
7ea47240 LF |
1795 | rtlpriv->dm.rfpath_rxenable[0] = |
1796 | rtlpriv->dm.rfpath_rxenable[1] = true; | |
f30d7507 JP |
1797 | RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, "VersionID = 0x%4x\n", |
1798 | rtlhal->version); | |
0c817338 LF |
1799 | tmp_u1b = rtl_read_byte(rtlpriv, REG_9346CR); |
1800 | if (tmp_u1b & BIT(4)) { | |
f30d7507 | 1801 | RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG, "Boot from EEPROM\n"); |
0c817338 LF |
1802 | rtlefuse->epromtype = EEPROM_93C46; |
1803 | } else { | |
f30d7507 | 1804 | RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG, "Boot from EFUSE\n"); |
0c817338 LF |
1805 | rtlefuse->epromtype = EEPROM_BOOT_EFUSE; |
1806 | } | |
1807 | if (tmp_u1b & BIT(5)) { | |
f30d7507 | 1808 | RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, "Autoload OK\n"); |
0c817338 LF |
1809 | rtlefuse->autoload_failflag = false; |
1810 | _rtl92ce_read_adapter_info(hw); | |
1811 | } else { | |
f30d7507 | 1812 | RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG, "Autoload ERR!!\n"); |
0c817338 | 1813 | } |
0c817338 LF |
1814 | _rtl92ce_hal_customized_behavior(hw); |
1815 | } | |
1816 | ||
f73b279c C |
1817 | static void rtl92ce_update_hal_rate_table(struct ieee80211_hw *hw, |
1818 | struct ieee80211_sta *sta) | |
0c817338 LF |
1819 | { |
1820 | struct rtl_priv *rtlpriv = rtl_priv(hw); | |
f73b279c | 1821 | struct rtl_pci_priv *rtlpcipriv = rtl_pcipriv(hw); |
0c817338 LF |
1822 | struct rtl_phy *rtlphy = &(rtlpriv->phy); |
1823 | struct rtl_mac *mac = rtl_mac(rtl_priv(hw)); | |
f73b279c C |
1824 | struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw)); |
1825 | u32 ratr_value; | |
0c817338 | 1826 | u8 ratr_index = 0; |
7ea47240 | 1827 | u8 nmode = mac->ht_enable; |
f73b279c | 1828 | u8 mimo_ps = IEEE80211_SMPS_OFF; |
0c817338 LF |
1829 | u16 shortgi_rate; |
1830 | u32 tmp_ratr_value; | |
7ea47240 | 1831 | u8 curtxbw_40mhz = mac->bw_40; |
f73b279c C |
1832 | u8 curshortgi_40mhz = (sta->ht_cap.cap & IEEE80211_HT_CAP_SGI_40) ? |
1833 | 1 : 0; | |
1834 | u8 curshortgi_20mhz = (sta->ht_cap.cap & IEEE80211_HT_CAP_SGI_20) ? | |
1835 | 1 : 0; | |
0c817338 LF |
1836 | enum wireless_mode wirelessmode = mac->mode; |
1837 | ||
f73b279c C |
1838 | if (rtlhal->current_bandtype == BAND_ON_5G) |
1839 | ratr_value = sta->supp_rates[1] << 4; | |
1840 | else | |
1841 | ratr_value = sta->supp_rates[0]; | |
3a16b412 LF |
1842 | if (mac->opmode == NL80211_IFTYPE_ADHOC) |
1843 | ratr_value = 0xfff; | |
1844 | ||
f73b279c C |
1845 | ratr_value |= (sta->ht_cap.mcs.rx_mask[1] << 20 | |
1846 | sta->ht_cap.mcs.rx_mask[0] << 12); | |
0c817338 LF |
1847 | switch (wirelessmode) { |
1848 | case WIRELESS_MODE_B: | |
1849 | if (ratr_value & 0x0000000c) | |
1850 | ratr_value &= 0x0000000d; | |
1851 | else | |
1852 | ratr_value &= 0x0000000f; | |
1853 | break; | |
1854 | case WIRELESS_MODE_G: | |
1855 | ratr_value &= 0x00000FF5; | |
1856 | break; | |
1857 | case WIRELESS_MODE_N_24G: | |
1858 | case WIRELESS_MODE_N_5G: | |
7ea47240 | 1859 | nmode = 1; |
f73b279c | 1860 | if (mimo_ps == IEEE80211_SMPS_STATIC) { |
0c817338 LF |
1861 | ratr_value &= 0x0007F005; |
1862 | } else { | |
1863 | u32 ratr_mask; | |
1864 | ||
1865 | if (get_rf_type(rtlphy) == RF_1T2R || | |
1866 | get_rf_type(rtlphy) == RF_1T1R) | |
1867 | ratr_mask = 0x000ff005; | |
1868 | else | |
1869 | ratr_mask = 0x0f0ff005; | |
1870 | ||
1871 | ratr_value &= ratr_mask; | |
1872 | } | |
1873 | break; | |
1874 | default: | |
1875 | if (rtlphy->rf_type == RF_1T2R) | |
1876 | ratr_value &= 0x000ff0ff; | |
1877 | else | |
1878 | ratr_value &= 0x0f0ff0ff; | |
1879 | ||
1880 | break; | |
1881 | } | |
1882 | ||
f73b279c C |
1883 | if ((rtlpcipriv->bt_coexist.bt_coexistence) && |
1884 | (rtlpcipriv->bt_coexist.bt_coexist_type == BT_CSR_BC4) && | |
1885 | (rtlpcipriv->bt_coexist.bt_cur_state) && | |
1886 | (rtlpcipriv->bt_coexist.bt_ant_isolation) && | |
1887 | ((rtlpcipriv->bt_coexist.bt_service == BT_SCO) || | |
1888 | (rtlpcipriv->bt_coexist.bt_service == BT_BUSY))) | |
1889 | ratr_value &= 0x0fffcfc0; | |
1890 | else | |
1891 | ratr_value &= 0x0FFFFFFF; | |
0c817338 | 1892 | |
f73b279c C |
1893 | if (nmode && ((curtxbw_40mhz && |
1894 | curshortgi_40mhz) || (!curtxbw_40mhz && | |
1895 | curshortgi_20mhz))) { | |
0c817338 LF |
1896 | |
1897 | ratr_value |= 0x10000000; | |
1898 | tmp_ratr_value = (ratr_value >> 12); | |
1899 | ||
1900 | for (shortgi_rate = 15; shortgi_rate > 0; shortgi_rate--) { | |
1901 | if ((1 << shortgi_rate) & tmp_ratr_value) | |
1902 | break; | |
1903 | } | |
1904 | ||
1905 | shortgi_rate = (shortgi_rate << 12) | (shortgi_rate << 8) | | |
1906 | (shortgi_rate << 4) | (shortgi_rate); | |
1907 | } | |
1908 | ||
1909 | rtl_write_dword(rtlpriv, REG_ARFR0 + ratr_index * 4, ratr_value); | |
1910 | ||
f30d7507 JP |
1911 | RT_TRACE(rtlpriv, COMP_RATR, DBG_DMESG, "%x\n", |
1912 | rtl_read_dword(rtlpriv, REG_ARFR0)); | |
0c817338 LF |
1913 | } |
1914 | ||
f73b279c C |
1915 | static void rtl92ce_update_hal_rate_mask(struct ieee80211_hw *hw, |
1916 | struct ieee80211_sta *sta, u8 rssi_level) | |
0c817338 LF |
1917 | { |
1918 | struct rtl_priv *rtlpriv = rtl_priv(hw); | |
1919 | struct rtl_phy *rtlphy = &(rtlpriv->phy); | |
1920 | struct rtl_mac *mac = rtl_mac(rtl_priv(hw)); | |
f73b279c C |
1921 | struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw)); |
1922 | struct rtl_sta_info *sta_entry = NULL; | |
1923 | u32 ratr_bitmap; | |
0c817338 | 1924 | u8 ratr_index; |
e1a0c6b3 JB |
1925 | u8 curtxbw_40mhz = (sta->bandwidth >= IEEE80211_STA_RX_BW_40) ? 1 : 0; |
1926 | u8 curshortgi_40mhz = curtxbw_40mhz && | |
1927 | (sta->ht_cap.cap & IEEE80211_HT_CAP_SGI_40) ? | |
f73b279c C |
1928 | 1 : 0; |
1929 | u8 curshortgi_20mhz = (sta->ht_cap.cap & IEEE80211_HT_CAP_SGI_20) ? | |
1930 | 1 : 0; | |
1931 | enum wireless_mode wirelessmode = 0; | |
7ea47240 | 1932 | bool shortgi = false; |
0c817338 LF |
1933 | u8 rate_mask[5]; |
1934 | u8 macid = 0; | |
f73b279c C |
1935 | u8 mimo_ps = IEEE80211_SMPS_OFF; |
1936 | ||
1937 | sta_entry = (struct rtl_sta_info *) sta->drv_priv; | |
1938 | wirelessmode = sta_entry->wireless_mode; | |
3a16b412 LF |
1939 | if (mac->opmode == NL80211_IFTYPE_STATION || |
1940 | mac->opmode == NL80211_IFTYPE_MESH_POINT) | |
f73b279c C |
1941 | curtxbw_40mhz = mac->bw_40; |
1942 | else if (mac->opmode == NL80211_IFTYPE_AP || | |
1943 | mac->opmode == NL80211_IFTYPE_ADHOC) | |
1944 | macid = sta->aid + 1; | |
1945 | ||
1946 | if (rtlhal->current_bandtype == BAND_ON_5G) | |
1947 | ratr_bitmap = sta->supp_rates[1] << 4; | |
1948 | else | |
1949 | ratr_bitmap = sta->supp_rates[0]; | |
3a16b412 LF |
1950 | if (mac->opmode == NL80211_IFTYPE_ADHOC) |
1951 | ratr_bitmap = 0xfff; | |
f73b279c C |
1952 | ratr_bitmap |= (sta->ht_cap.mcs.rx_mask[1] << 20 | |
1953 | sta->ht_cap.mcs.rx_mask[0] << 12); | |
0c817338 LF |
1954 | switch (wirelessmode) { |
1955 | case WIRELESS_MODE_B: | |
1956 | ratr_index = RATR_INX_WIRELESS_B; | |
1957 | if (ratr_bitmap & 0x0000000c) | |
1958 | ratr_bitmap &= 0x0000000d; | |
1959 | else | |
1960 | ratr_bitmap &= 0x0000000f; | |
1961 | break; | |
1962 | case WIRELESS_MODE_G: | |
1963 | ratr_index = RATR_INX_WIRELESS_GB; | |
1964 | ||
1965 | if (rssi_level == 1) | |
1966 | ratr_bitmap &= 0x00000f00; | |
1967 | else if (rssi_level == 2) | |
1968 | ratr_bitmap &= 0x00000ff0; | |
1969 | else | |
1970 | ratr_bitmap &= 0x00000ff5; | |
1971 | break; | |
1972 | case WIRELESS_MODE_A: | |
1973 | ratr_index = RATR_INX_WIRELESS_A; | |
1974 | ratr_bitmap &= 0x00000ff0; | |
1975 | break; | |
1976 | case WIRELESS_MODE_N_24G: | |
1977 | case WIRELESS_MODE_N_5G: | |
1978 | ratr_index = RATR_INX_WIRELESS_NGB; | |
1979 | ||
f73b279c | 1980 | if (mimo_ps == IEEE80211_SMPS_STATIC) { |
0c817338 LF |
1981 | if (rssi_level == 1) |
1982 | ratr_bitmap &= 0x00070000; | |
1983 | else if (rssi_level == 2) | |
1984 | ratr_bitmap &= 0x0007f000; | |
1985 | else | |
1986 | ratr_bitmap &= 0x0007f005; | |
1987 | } else { | |
1988 | if (rtlphy->rf_type == RF_1T2R || | |
1989 | rtlphy->rf_type == RF_1T1R) { | |
7ea47240 | 1990 | if (curtxbw_40mhz) { |
0c817338 LF |
1991 | if (rssi_level == 1) |
1992 | ratr_bitmap &= 0x000f0000; | |
1993 | else if (rssi_level == 2) | |
1994 | ratr_bitmap &= 0x000ff000; | |
1995 | else | |
1996 | ratr_bitmap &= 0x000ff015; | |
1997 | } else { | |
1998 | if (rssi_level == 1) | |
1999 | ratr_bitmap &= 0x000f0000; | |
2000 | else if (rssi_level == 2) | |
2001 | ratr_bitmap &= 0x000ff000; | |
2002 | else | |
2003 | ratr_bitmap &= 0x000ff005; | |
2004 | } | |
2005 | } else { | |
7ea47240 | 2006 | if (curtxbw_40mhz) { |
0c817338 LF |
2007 | if (rssi_level == 1) |
2008 | ratr_bitmap &= 0x0f0f0000; | |
2009 | else if (rssi_level == 2) | |
2010 | ratr_bitmap &= 0x0f0ff000; | |
2011 | else | |
2012 | ratr_bitmap &= 0x0f0ff015; | |
2013 | } else { | |
2014 | if (rssi_level == 1) | |
2015 | ratr_bitmap &= 0x0f0f0000; | |
2016 | else if (rssi_level == 2) | |
2017 | ratr_bitmap &= 0x0f0ff000; | |
2018 | else | |
2019 | ratr_bitmap &= 0x0f0ff005; | |
2020 | } | |
2021 | } | |
2022 | } | |
2023 | ||
7ea47240 LF |
2024 | if ((curtxbw_40mhz && curshortgi_40mhz) || |
2025 | (!curtxbw_40mhz && curshortgi_20mhz)) { | |
0c817338 LF |
2026 | |
2027 | if (macid == 0) | |
7ea47240 | 2028 | shortgi = true; |
0c817338 | 2029 | else if (macid == 1) |
7ea47240 | 2030 | shortgi = false; |
0c817338 LF |
2031 | } |
2032 | break; | |
2033 | default: | |
2034 | ratr_index = RATR_INX_WIRELESS_NGB; | |
2035 | ||
2036 | if (rtlphy->rf_type == RF_1T2R) | |
2037 | ratr_bitmap &= 0x000ff0ff; | |
2038 | else | |
2039 | ratr_bitmap &= 0x0f0ff0ff; | |
2040 | break; | |
2041 | } | |
0bd899e7 LF |
2042 | sta_entry->ratr_index = ratr_index; |
2043 | ||
0c817338 | 2044 | RT_TRACE(rtlpriv, COMP_RATR, DBG_DMESG, |
f30d7507 | 2045 | "ratr_bitmap :%x\n", ratr_bitmap); |
8e2c406a LF |
2046 | *(u32 *)&rate_mask = (ratr_bitmap & 0x0fffffff) | |
2047 | (ratr_index << 28); | |
7ea47240 | 2048 | rate_mask[4] = macid | (shortgi ? 0x20 : 0x00) | 0x80; |
f30d7507 | 2049 | RT_TRACE(rtlpriv, COMP_RATR, DBG_DMESG, |
ed9f0ed3 AS |
2050 | "Rate_index:%x, ratr_val:%x, %5phC\n", |
2051 | ratr_index, ratr_bitmap, rate_mask); | |
0c817338 | 2052 | rtl92c_fill_h2c_cmd(hw, H2C_RA_MASK, 5, rate_mask); |
f73b279c C |
2053 | |
2054 | if (macid != 0) | |
2055 | sta_entry->ratr_index = ratr_index; | |
2056 | } | |
2057 | ||
2058 | void rtl92ce_update_hal_rate_tbl(struct ieee80211_hw *hw, | |
2059 | struct ieee80211_sta *sta, u8 rssi_level) | |
2060 | { | |
2061 | struct rtl_priv *rtlpriv = rtl_priv(hw); | |
2062 | ||
2063 | if (rtlpriv->dm.useramask) | |
2064 | rtl92ce_update_hal_rate_mask(hw, sta, rssi_level); | |
2065 | else | |
2066 | rtl92ce_update_hal_rate_table(hw, sta); | |
0c817338 LF |
2067 | } |
2068 | ||
2069 | void rtl92ce_update_channel_access_setting(struct ieee80211_hw *hw) | |
2070 | { | |
2071 | struct rtl_priv *rtlpriv = rtl_priv(hw); | |
2072 | struct rtl_mac *mac = rtl_mac(rtl_priv(hw)); | |
2073 | u16 sifs_timer; | |
2074 | ||
2075 | rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_SLOT_TIME, | |
2c208890 | 2076 | &mac->slot_time); |
0c817338 LF |
2077 | if (!mac->ht_enable) |
2078 | sifs_timer = 0x0a0a; | |
2079 | else | |
2080 | sifs_timer = 0x1010; | |
2081 | rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_SIFS, (u8 *)&sifs_timer); | |
2082 | } | |
2083 | ||
f73b279c | 2084 | bool rtl92ce_gpio_radio_on_off_checking(struct ieee80211_hw *hw, u8 *valid) |
0c817338 LF |
2085 | { |
2086 | struct rtl_priv *rtlpriv = rtl_priv(hw); | |
2087 | struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw)); | |
2088 | struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw)); | |
6c0d4988 | 2089 | enum rf_pwrstate e_rfpowerstate_toset; |
0c817338 | 2090 | u8 u1tmp; |
7ea47240 | 2091 | bool actuallyset = false; |
0c817338 LF |
2092 | unsigned long flag; |
2093 | ||
f73b279c | 2094 | if (rtlpci->being_init_adapter) |
0c817338 LF |
2095 | return false; |
2096 | ||
7ea47240 | 2097 | if (ppsc->swrf_processing) |
0c817338 LF |
2098 | return false; |
2099 | ||
2100 | spin_lock_irqsave(&rtlpriv->locks.rf_ps_lock, flag); | |
2101 | if (ppsc->rfchange_inprogress) { | |
2102 | spin_unlock_irqrestore(&rtlpriv->locks.rf_ps_lock, flag); | |
2103 | return false; | |
2104 | } else { | |
2105 | ppsc->rfchange_inprogress = true; | |
2106 | spin_unlock_irqrestore(&rtlpriv->locks.rf_ps_lock, flag); | |
2107 | } | |
2108 | ||
0c817338 LF |
2109 | rtl_write_byte(rtlpriv, REG_MAC_PINMUX_CFG, rtl_read_byte(rtlpriv, |
2110 | REG_MAC_PINMUX_CFG)&~(BIT(3))); | |
2111 | ||
2112 | u1tmp = rtl_read_byte(rtlpriv, REG_GPIO_IO_SEL); | |
2113 | e_rfpowerstate_toset = (u1tmp & BIT(3)) ? ERFON : ERFOFF; | |
2114 | ||
e10542c4 | 2115 | if ((ppsc->hwradiooff) && (e_rfpowerstate_toset == ERFON)) { |
0c817338 | 2116 | RT_TRACE(rtlpriv, COMP_RF, DBG_DMESG, |
f30d7507 | 2117 | "GPIOChangeRF - HW Radio ON, RF ON\n"); |
0c817338 LF |
2118 | |
2119 | e_rfpowerstate_toset = ERFON; | |
7ea47240 LF |
2120 | ppsc->hwradiooff = false; |
2121 | actuallyset = true; | |
23677ce3 | 2122 | } else if (!ppsc->hwradiooff && (e_rfpowerstate_toset == ERFOFF)) { |
0c817338 | 2123 | RT_TRACE(rtlpriv, COMP_RF, DBG_DMESG, |
f30d7507 | 2124 | "GPIOChangeRF - HW Radio OFF, RF OFF\n"); |
0c817338 LF |
2125 | |
2126 | e_rfpowerstate_toset = ERFOFF; | |
7ea47240 LF |
2127 | ppsc->hwradiooff = true; |
2128 | actuallyset = true; | |
0c817338 LF |
2129 | } |
2130 | ||
7ea47240 | 2131 | if (actuallyset) { |
0c817338 LF |
2132 | spin_lock_irqsave(&rtlpriv->locks.rf_ps_lock, flag); |
2133 | ppsc->rfchange_inprogress = false; | |
2134 | spin_unlock_irqrestore(&rtlpriv->locks.rf_ps_lock, flag); | |
f73b279c | 2135 | } else { |
0c817338 LF |
2136 | if (ppsc->reg_rfps_level & RT_RF_OFF_LEVL_HALT_NIC) |
2137 | RT_SET_PS_LEVEL(ppsc, RT_RF_OFF_LEVL_HALT_NIC); | |
2138 | ||
0c817338 LF |
2139 | spin_lock_irqsave(&rtlpriv->locks.rf_ps_lock, flag); |
2140 | ppsc->rfchange_inprogress = false; | |
2141 | spin_unlock_irqrestore(&rtlpriv->locks.rf_ps_lock, flag); | |
2142 | } | |
2143 | ||
2144 | *valid = 1; | |
7ea47240 | 2145 | return !ppsc->hwradiooff; |
0c817338 LF |
2146 | |
2147 | } | |
2148 | ||
2149 | void rtl92ce_set_key(struct ieee80211_hw *hw, u32 key_index, | |
2150 | u8 *p_macaddr, bool is_group, u8 enc_algo, | |
2151 | bool is_wepkey, bool clear_all) | |
2152 | { | |
2153 | struct rtl_priv *rtlpriv = rtl_priv(hw); | |
2154 | struct rtl_mac *mac = rtl_mac(rtl_priv(hw)); | |
2155 | struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw)); | |
2156 | u8 *macaddr = p_macaddr; | |
2157 | u32 entry_id = 0; | |
2158 | bool is_pairwise = false; | |
2159 | ||
2160 | static u8 cam_const_addr[4][6] = { | |
2161 | {0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, | |
2162 | {0x00, 0x00, 0x00, 0x00, 0x00, 0x01}, | |
2163 | {0x00, 0x00, 0x00, 0x00, 0x00, 0x02}, | |
2164 | {0x00, 0x00, 0x00, 0x00, 0x00, 0x03} | |
2165 | }; | |
2166 | static u8 cam_const_broad[] = { | |
2167 | 0xff, 0xff, 0xff, 0xff, 0xff, 0xff | |
2168 | }; | |
2169 | ||
2170 | if (clear_all) { | |
2171 | u8 idx = 0; | |
2172 | u8 cam_offset = 0; | |
2173 | u8 clear_number = 5; | |
2174 | ||
f30d7507 | 2175 | RT_TRACE(rtlpriv, COMP_SEC, DBG_DMESG, "clear_all\n"); |
0c817338 LF |
2176 | |
2177 | for (idx = 0; idx < clear_number; idx++) { | |
2178 | rtl_cam_mark_invalid(hw, cam_offset + idx); | |
2179 | rtl_cam_empty_entry(hw, cam_offset + idx); | |
2180 | ||
2181 | if (idx < 5) { | |
2182 | memset(rtlpriv->sec.key_buf[idx], 0, | |
2183 | MAX_KEY_LEN); | |
2184 | rtlpriv->sec.key_len[idx] = 0; | |
2185 | } | |
2186 | } | |
2187 | ||
2188 | } else { | |
2189 | switch (enc_algo) { | |
2190 | case WEP40_ENCRYPTION: | |
2191 | enc_algo = CAM_WEP40; | |
2192 | break; | |
2193 | case WEP104_ENCRYPTION: | |
2194 | enc_algo = CAM_WEP104; | |
2195 | break; | |
2196 | case TKIP_ENCRYPTION: | |
2197 | enc_algo = CAM_TKIP; | |
2198 | break; | |
2199 | case AESCCMP_ENCRYPTION: | |
2200 | enc_algo = CAM_AES; | |
2201 | break; | |
2202 | default: | |
f30d7507 JP |
2203 | RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG, |
2204 | "switch case not processed\n"); | |
0c817338 LF |
2205 | enc_algo = CAM_TKIP; |
2206 | break; | |
2207 | } | |
2208 | ||
2209 | if (is_wepkey || rtlpriv->sec.use_defaultkey) { | |
2210 | macaddr = cam_const_addr[key_index]; | |
2211 | entry_id = key_index; | |
2212 | } else { | |
2213 | if (is_group) { | |
2214 | macaddr = cam_const_broad; | |
2215 | entry_id = key_index; | |
2216 | } else { | |
3a16b412 LF |
2217 | if (mac->opmode == NL80211_IFTYPE_AP || |
2218 | mac->opmode == NL80211_IFTYPE_MESH_POINT) { | |
f73b279c C |
2219 | entry_id = rtl_cam_get_free_entry(hw, |
2220 | p_macaddr); | |
2221 | if (entry_id >= TOTAL_CAM_ENTRY) { | |
2222 | RT_TRACE(rtlpriv, COMP_SEC, | |
f30d7507 JP |
2223 | DBG_EMERG, |
2224 | "Can not find free hw security cam entry\n"); | |
f73b279c C |
2225 | return; |
2226 | } | |
2227 | } else { | |
2228 | entry_id = CAM_PAIRWISE_KEY_POSITION; | |
2229 | } | |
2230 | ||
0c817338 | 2231 | key_index = PAIRWISE_KEYIDX; |
0c817338 LF |
2232 | is_pairwise = true; |
2233 | } | |
2234 | } | |
2235 | ||
2236 | if (rtlpriv->sec.key_len[key_index] == 0) { | |
2237 | RT_TRACE(rtlpriv, COMP_SEC, DBG_DMESG, | |
f30d7507 JP |
2238 | "delete one entry, entry_id is %d\n", |
2239 | entry_id); | |
3a16b412 LF |
2240 | if (mac->opmode == NL80211_IFTYPE_AP || |
2241 | mac->opmode == NL80211_IFTYPE_MESH_POINT) | |
f73b279c | 2242 | rtl_cam_del_entry(hw, p_macaddr); |
0c817338 LF |
2243 | rtl_cam_delete_one_entry(hw, p_macaddr, entry_id); |
2244 | } else { | |
2245 | RT_TRACE(rtlpriv, COMP_SEC, DBG_LOUD, | |
f30d7507 JP |
2246 | "The insert KEY length is %d\n", |
2247 | rtlpriv->sec.key_len[PAIRWISE_KEYIDX]); | |
0c817338 | 2248 | RT_TRACE(rtlpriv, COMP_SEC, DBG_LOUD, |
f30d7507 JP |
2249 | "The insert KEY is %x %x\n", |
2250 | rtlpriv->sec.key_buf[0][0], | |
2251 | rtlpriv->sec.key_buf[0][1]); | |
0c817338 LF |
2252 | |
2253 | RT_TRACE(rtlpriv, COMP_SEC, DBG_DMESG, | |
f30d7507 | 2254 | "add one entry\n"); |
0c817338 LF |
2255 | if (is_pairwise) { |
2256 | RT_PRINT_DATA(rtlpriv, COMP_SEC, DBG_LOUD, | |
af08687b | 2257 | "Pairwise Key content", |
0c817338 LF |
2258 | rtlpriv->sec.pairwise_key, |
2259 | rtlpriv->sec. | |
2260 | key_len[PAIRWISE_KEYIDX]); | |
2261 | ||
2262 | RT_TRACE(rtlpriv, COMP_SEC, DBG_DMESG, | |
f30d7507 | 2263 | "set Pairwise key\n"); |
0c817338 LF |
2264 | |
2265 | rtl_cam_add_one_entry(hw, macaddr, key_index, | |
2266 | entry_id, enc_algo, | |
2267 | CAM_CONFIG_NO_USEDK, | |
2268 | rtlpriv->sec. | |
2269 | key_buf[key_index]); | |
2270 | } else { | |
2271 | RT_TRACE(rtlpriv, COMP_SEC, DBG_DMESG, | |
f30d7507 | 2272 | "set group key\n"); |
0c817338 LF |
2273 | |
2274 | if (mac->opmode == NL80211_IFTYPE_ADHOC) { | |
2275 | rtl_cam_add_one_entry(hw, | |
2276 | rtlefuse->dev_addr, | |
2277 | PAIRWISE_KEYIDX, | |
2278 | CAM_PAIRWISE_KEY_POSITION, | |
2279 | enc_algo, | |
2280 | CAM_CONFIG_NO_USEDK, | |
2281 | rtlpriv->sec.key_buf | |
2282 | [entry_id]); | |
2283 | } | |
2284 | ||
2285 | rtl_cam_add_one_entry(hw, macaddr, key_index, | |
2286 | entry_id, enc_algo, | |
2287 | CAM_CONFIG_NO_USEDK, | |
2288 | rtlpriv->sec.key_buf[entry_id]); | |
2289 | } | |
2290 | ||
2291 | } | |
2292 | } | |
2293 | } | |
f73b279c | 2294 | |
d3bb1429 | 2295 | static void rtl8192ce_bt_var_init(struct ieee80211_hw *hw) |
f73b279c C |
2296 | { |
2297 | struct rtl_pci_priv *rtlpcipriv = rtl_pcipriv(hw); | |
2298 | ||
2299 | rtlpcipriv->bt_coexist.bt_coexistence = | |
2300 | rtlpcipriv->bt_coexist.eeprom_bt_coexist; | |
2301 | rtlpcipriv->bt_coexist.bt_ant_num = | |
2302 | rtlpcipriv->bt_coexist.eeprom_bt_ant_num; | |
2303 | rtlpcipriv->bt_coexist.bt_coexist_type = | |
2304 | rtlpcipriv->bt_coexist.eeprom_bt_type; | |
2305 | ||
2306 | if (rtlpcipriv->bt_coexist.reg_bt_iso == 2) | |
2307 | rtlpcipriv->bt_coexist.bt_ant_isolation = | |
da17fcff | 2308 | rtlpcipriv->bt_coexist.eeprom_bt_ant_isol; |
f73b279c C |
2309 | else |
2310 | rtlpcipriv->bt_coexist.bt_ant_isolation = | |
2311 | rtlpcipriv->bt_coexist.reg_bt_iso; | |
2312 | ||
2313 | rtlpcipriv->bt_coexist.bt_radio_shared_type = | |
2314 | rtlpcipriv->bt_coexist.eeprom_bt_radio_shared; | |
2315 | ||
2316 | if (rtlpcipriv->bt_coexist.bt_coexistence) { | |
2317 | ||
2318 | if (rtlpcipriv->bt_coexist.reg_bt_sco == 1) | |
2319 | rtlpcipriv->bt_coexist.bt_service = BT_OTHER_ACTION; | |
2320 | else if (rtlpcipriv->bt_coexist.reg_bt_sco == 2) | |
2321 | rtlpcipriv->bt_coexist.bt_service = BT_SCO; | |
2322 | else if (rtlpcipriv->bt_coexist.reg_bt_sco == 4) | |
2323 | rtlpcipriv->bt_coexist.bt_service = BT_BUSY; | |
2324 | else if (rtlpcipriv->bt_coexist.reg_bt_sco == 5) | |
2325 | rtlpcipriv->bt_coexist.bt_service = BT_OTHERBUSY; | |
2326 | else | |
2327 | rtlpcipriv->bt_coexist.bt_service = BT_IDLE; | |
2328 | ||
2329 | rtlpcipriv->bt_coexist.bt_edca_ul = 0; | |
2330 | rtlpcipriv->bt_coexist.bt_edca_dl = 0; | |
2331 | rtlpcipriv->bt_coexist.bt_rssi_state = 0xff; | |
2332 | } | |
2333 | } | |
2334 | ||
2335 | void rtl8192ce_read_bt_coexist_info_from_hwpg(struct ieee80211_hw *hw, | |
2336 | bool auto_load_fail, u8 *hwinfo) | |
2337 | { | |
2338 | struct rtl_pci_priv *rtlpcipriv = rtl_pcipriv(hw); | |
da17fcff | 2339 | u8 val; |
f73b279c C |
2340 | |
2341 | if (!auto_load_fail) { | |
2342 | rtlpcipriv->bt_coexist.eeprom_bt_coexist = | |
2343 | ((hwinfo[RF_OPTION1] & 0xe0) >> 5); | |
da17fcff LF |
2344 | val = hwinfo[RF_OPTION4]; |
2345 | rtlpcipriv->bt_coexist.eeprom_bt_type = ((val & 0xe) >> 1); | |
2346 | rtlpcipriv->bt_coexist.eeprom_bt_ant_num = (val & 0x1); | |
2347 | rtlpcipriv->bt_coexist.eeprom_bt_ant_isol = ((val & 0x10) >> 4); | |
f73b279c | 2348 | rtlpcipriv->bt_coexist.eeprom_bt_radio_shared = |
da17fcff | 2349 | ((val & 0x20) >> 5); |
f73b279c C |
2350 | } else { |
2351 | rtlpcipriv->bt_coexist.eeprom_bt_coexist = 0; | |
2352 | rtlpcipriv->bt_coexist.eeprom_bt_type = BT_2WIRE; | |
2353 | rtlpcipriv->bt_coexist.eeprom_bt_ant_num = ANT_X2; | |
da17fcff | 2354 | rtlpcipriv->bt_coexist.eeprom_bt_ant_isol = 0; |
f73b279c C |
2355 | rtlpcipriv->bt_coexist.eeprom_bt_radio_shared = BT_RADIO_SHARED; |
2356 | } | |
2357 | ||
2358 | rtl8192ce_bt_var_init(hw); | |
2359 | } | |
2360 | ||
2361 | void rtl8192ce_bt_reg_init(struct ieee80211_hw *hw) | |
2362 | { | |
2363 | struct rtl_pci_priv *rtlpcipriv = rtl_pcipriv(hw); | |
2364 | ||
2365 | /* 0:Low, 1:High, 2:From Efuse. */ | |
2366 | rtlpcipriv->bt_coexist.reg_bt_iso = 2; | |
2367 | /* 0:Idle, 1:None-SCO, 2:SCO, 3:From Counter. */ | |
2368 | rtlpcipriv->bt_coexist.reg_bt_sco = 3; | |
2369 | /* 0:Disable BT control A-MPDU, 1:Enable BT control A-MPDU. */ | |
2370 | rtlpcipriv->bt_coexist.reg_bt_sco = 0; | |
2371 | } | |
2372 | ||
2373 | ||
2374 | void rtl8192ce_bt_hw_init(struct ieee80211_hw *hw) | |
2375 | { | |
2376 | struct rtl_priv *rtlpriv = rtl_priv(hw); | |
2377 | struct rtl_phy *rtlphy = &(rtlpriv->phy); | |
2378 | struct rtl_pci_priv *rtlpcipriv = rtl_pcipriv(hw); | |
2379 | ||
2380 | u8 u1_tmp; | |
2381 | ||
2382 | if (rtlpcipriv->bt_coexist.bt_coexistence && | |
2383 | ((rtlpcipriv->bt_coexist.bt_coexist_type == BT_CSR_BC4) || | |
2384 | rtlpcipriv->bt_coexist.bt_coexist_type == BT_CSR_BC8)) { | |
2385 | ||
2386 | if (rtlpcipriv->bt_coexist.bt_ant_isolation) | |
2387 | rtl_write_byte(rtlpriv, REG_GPIO_MUXCFG, 0xa0); | |
2388 | ||
2389 | u1_tmp = rtl_read_byte(rtlpriv, 0x4fd) & | |
2390 | BIT_OFFSET_LEN_MASK_32(0, 1); | |
2391 | u1_tmp = u1_tmp | | |
2392 | ((rtlpcipriv->bt_coexist.bt_ant_isolation == 1) ? | |
2393 | 0 : BIT_OFFSET_LEN_MASK_32(1, 1)) | | |
2394 | ((rtlpcipriv->bt_coexist.bt_service == BT_SCO) ? | |
2395 | 0 : BIT_OFFSET_LEN_MASK_32(2, 1)); | |
2396 | rtl_write_byte(rtlpriv, 0x4fd, u1_tmp); | |
2397 | ||
2398 | rtl_write_dword(rtlpriv, REG_BT_COEX_TABLE+4, 0xaaaa9aaa); | |
2399 | rtl_write_dword(rtlpriv, REG_BT_COEX_TABLE+8, 0xffbd0040); | |
2400 | rtl_write_dword(rtlpriv, REG_BT_COEX_TABLE+0xc, 0x40000010); | |
2401 | ||
2402 | /* Config to 1T1R. */ | |
2403 | if (rtlphy->rf_type == RF_1T1R) { | |
2404 | u1_tmp = rtl_read_byte(rtlpriv, ROFDM0_TRXPATHENABLE); | |
2405 | u1_tmp &= ~(BIT_OFFSET_LEN_MASK_32(1, 1)); | |
2406 | rtl_write_byte(rtlpriv, ROFDM0_TRXPATHENABLE, u1_tmp); | |
2407 | ||
2408 | u1_tmp = rtl_read_byte(rtlpriv, ROFDM1_TRXPATHENABLE); | |
2409 | u1_tmp &= ~(BIT_OFFSET_LEN_MASK_32(1, 1)); | |
2410 | rtl_write_byte(rtlpriv, ROFDM1_TRXPATHENABLE, u1_tmp); | |
2411 | } | |
2412 | } | |
2413 | } | |
2414 | ||
2415 | void rtl92ce_suspend(struct ieee80211_hw *hw) | |
2416 | { | |
2417 | } | |
2418 | ||
2419 | void rtl92ce_resume(struct ieee80211_hw *hw) | |
2420 | { | |
2421 | } | |
3a16b412 LF |
2422 | |
2423 | /* Turn on AAP (RCR:bit 0) for promicuous mode. */ | |
2424 | void rtl92ce_allow_all_destaddr(struct ieee80211_hw *hw, | |
2425 | bool allow_all_da, bool write_into_reg) | |
2426 | { | |
2427 | struct rtl_priv *rtlpriv = rtl_priv(hw); | |
2428 | struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw)); | |
2429 | ||
2430 | if (allow_all_da) {/* Set BIT0 */ | |
2431 | rtlpci->receive_config |= RCR_AAP; | |
2432 | } else {/* Clear BIT0 */ | |
2433 | rtlpci->receive_config &= ~RCR_AAP; | |
2434 | } | |
2435 | ||
2436 | if (write_into_reg) | |
2437 | rtl_write_dword(rtlpriv, REG_RCR, rtlpci->receive_config); | |
2438 | ||
2439 | RT_TRACE(rtlpriv, COMP_TURBO | COMP_INIT, DBG_LOUD, | |
2440 | "receive_config=0x%08X, write_into_reg=%d\n", | |
2441 | rtlpci->receive_config, write_into_reg); | |
2442 | } |