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0c817338 LF |
1 | /****************************************************************************** |
2 | * | |
3 | * Copyright(c) 2009-2010 Realtek Corporation. | |
4 | * | |
5 | * This program is free software; you can redistribute it and/or modify it | |
6 | * under the terms of version 2 of the GNU General Public License as | |
7 | * published by the Free Software Foundation. | |
8 | * | |
9 | * This program is distributed in the hope that it will be useful, but WITHOUT | |
10 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
11 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | |
12 | * more details. | |
13 | * | |
14 | * You should have received a copy of the GNU General Public License along with | |
15 | * this program; if not, write to the Free Software Foundation, Inc., | |
16 | * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA | |
17 | * | |
18 | * The full GNU General Public License is included in this distribution in the | |
19 | * file called LICENSE. | |
20 | * | |
21 | * Contact Information: | |
22 | * wlanfae <wlanfae@realtek.com> | |
23 | * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park, | |
24 | * Hsinchu 300, Taiwan. | |
25 | * | |
26 | * Larry Finger <Larry.Finger@lwfinger.net> | |
27 | * | |
28 | *****************************************************************************/ | |
29 | ||
4aea248d | 30 | #include <linux/vmalloc.h> |
9d9779e7 | 31 | #include <linux/module.h> |
4aea248d | 32 | |
0c817338 LF |
33 | #include "../wifi.h" |
34 | #include "../core.h" | |
35 | #include "../pci.h" | |
5c405b5c JL |
36 | #include "reg.h" |
37 | #include "def.h" | |
38 | #include "phy.h" | |
39 | #include "dm.h" | |
40 | #include "hw.h" | |
1472d3a8 | 41 | #include "rf.h" |
5c405b5c JL |
42 | #include "sw.h" |
43 | #include "trx.h" | |
44 | #include "led.h" | |
0c817338 | 45 | |
d3bb1429 | 46 | static void rtl92c_init_aspm_vars(struct ieee80211_hw *hw) |
2b8359f8 C |
47 | { |
48 | struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw)); | |
49 | ||
50 | /*close ASPM for AMD defaultly */ | |
51 | rtlpci->const_amdpci_aspm = 0; | |
52 | ||
53 | /* | |
54 | * ASPM PS mode. | |
55 | * 0 - Disable ASPM, | |
56 | * 1 - Enable ASPM without Clock Req, | |
57 | * 2 - Enable ASPM with Clock Req, | |
58 | * 3 - Alwyas Enable ASPM with Clock Req, | |
59 | * 4 - Always Enable ASPM without Clock Req. | |
60 | * set defult to RTL8192CE:3 RTL8192E:2 | |
61 | * */ | |
62 | rtlpci->const_pci_aspm = 3; | |
63 | ||
64 | /*Setting for PCI-E device */ | |
65 | rtlpci->const_devicepci_aspm_setting = 0x03; | |
66 | ||
67 | /*Setting for PCI-E bridge */ | |
68 | rtlpci->const_hostpci_aspm_setting = 0x02; | |
69 | ||
70 | /* | |
71 | * In Hw/Sw Radio Off situation. | |
72 | * 0 - Default, | |
73 | * 1 - From ASPM setting without low Mac Pwr, | |
74 | * 2 - From ASPM setting with low Mac Pwr, | |
75 | * 3 - Bus D3 | |
76 | * set default to RTL8192CE:0 RTL8192SE:2 | |
77 | */ | |
78 | rtlpci->const_hwsw_rfoff_d3 = 0; | |
79 | ||
80 | /* | |
81 | * This setting works for those device with | |
82 | * backdoor ASPM setting such as EPHY setting. | |
83 | * 0 - Not support ASPM, | |
84 | * 1 - Support ASPM, | |
85 | * 2 - According to chipset. | |
86 | */ | |
87 | rtlpci->const_support_pciaspm = 1; | |
88 | } | |
89 | ||
0c817338 LF |
90 | int rtl92c_init_sw_vars(struct ieee80211_hw *hw) |
91 | { | |
2b8359f8 | 92 | int err; |
0c817338 LF |
93 | struct rtl_priv *rtlpriv = rtl_priv(hw); |
94 | struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw)); | |
2b8359f8 | 95 | const struct firmware *firmware; |
db759939 CL |
96 | struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw)); |
97 | char *fw_name = NULL; | |
2b8359f8 C |
98 | |
99 | rtl8192ce_bt_reg_init(hw); | |
0c817338 | 100 | |
7ea47240 | 101 | rtlpriv->dm.dm_initialgain_enable = 1; |
0c817338 | 102 | rtlpriv->dm.dm_flag = 0; |
7ea47240 | 103 | rtlpriv->dm.disable_framebursting = 0; |
0c817338 LF |
104 | rtlpriv->dm.thermalvalue = 0; |
105 | rtlpci->transmit_config = CFENDFORM | BIT(12) | BIT(13); | |
106 | ||
2b8359f8 C |
107 | /* compatible 5G band 88ce just 2.4G band & smsp */ |
108 | rtlpriv->rtlhal.current_bandtype = BAND_ON_2_4G; | |
109 | rtlpriv->rtlhal.bandset = BAND_ON_2_4G; | |
110 | rtlpriv->rtlhal.macphymode = SINGLEMAC_SINGLEPHY; | |
111 | ||
112 | rtlpci->receive_config = (RCR_APPFCS | | |
0c817338 LF |
113 | RCR_AMF | |
114 | RCR_ADF | | |
115 | RCR_APP_MIC | | |
116 | RCR_APP_ICV | | |
117 | RCR_AICV | | |
118 | RCR_ACRC32 | | |
119 | RCR_AB | | |
120 | RCR_AM | | |
121 | RCR_APM | | |
122 | RCR_APP_PHYST_RXFF | RCR_HTC_LOC_CTRL | 0); | |
123 | ||
124 | rtlpci->irq_mask[0] = | |
125 | (u32) (IMR_ROK | | |
126 | IMR_VODOK | | |
127 | IMR_VIDOK | | |
128 | IMR_BEDOK | | |
129 | IMR_BKDOK | | |
130 | IMR_MGNTDOK | | |
131 | IMR_HIGHDOK | IMR_BDOK | IMR_RDU | IMR_RXFOVW | 0); | |
132 | ||
133 | rtlpci->irq_mask[1] = (u32) (IMR_CPWM | IMR_C2HCMD | 0); | |
134 | ||
73a253ca LF |
135 | /* for debug level */ |
136 | rtlpriv->dbg.global_debuglevel = rtlpriv->cfg->mod_params->debug; | |
2b8359f8 C |
137 | /* for LPS & IPS */ |
138 | rtlpriv->psc.inactiveps = rtlpriv->cfg->mod_params->inactiveps; | |
139 | rtlpriv->psc.swctrl_lps = rtlpriv->cfg->mod_params->swctrl_lps; | |
140 | rtlpriv->psc.fwctrl_lps = rtlpriv->cfg->mod_params->fwctrl_lps; | |
eed72316 LF |
141 | if (!rtlpriv->psc.inactiveps) |
142 | pr_info("rtl8192ce: Power Save off (module option)\n"); | |
143 | if (!rtlpriv->psc.fwctrl_lps) | |
144 | pr_info("rtl8192ce: FW Power Save off (module option)\n"); | |
2b8359f8 C |
145 | rtlpriv->psc.reg_fwctrl_lps = 3; |
146 | rtlpriv->psc.reg_max_lps_awakeintvl = 5; | |
147 | /* for ASPM, you can close aspm through | |
148 | * set const_support_pciaspm = 0 */ | |
149 | rtl92c_init_aspm_vars(hw); | |
150 | ||
151 | if (rtlpriv->psc.reg_fwctrl_lps == 1) | |
152 | rtlpriv->psc.fwctrl_psmode = FW_PS_MIN_MODE; | |
153 | else if (rtlpriv->psc.reg_fwctrl_lps == 2) | |
154 | rtlpriv->psc.fwctrl_psmode = FW_PS_MAX_MODE; | |
155 | else if (rtlpriv->psc.reg_fwctrl_lps == 3) | |
156 | rtlpriv->psc.fwctrl_psmode = FW_PS_DTIM_MODE; | |
157 | ||
158 | /* for firmware buf */ | |
159 | rtlpriv->rtlhal.pfirmware = vzalloc(0x4000); | |
0c817338 LF |
160 | if (!rtlpriv->rtlhal.pfirmware) { |
161 | RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG, | |
162 | ("Can't alloc buffer for fw.\n")); | |
163 | return 1; | |
164 | } | |
165 | ||
2b8359f8 | 166 | /* request fw */ |
db759939 CL |
167 | if (IS_VENDOR_UMC_A_CUT(rtlhal->version) && |
168 | !IS_92C_SERIAL(rtlhal->version)) | |
169 | fw_name = "rtlwifi/rtl8192cfwU.bin"; | |
170 | else if (IS_81xxC_VENDOR_UMC_B_CUT(rtlhal->version)) | |
171 | fw_name = "rtlwifi/rtl8192cfwU_B.bin"; | |
172 | else | |
173 | fw_name = rtlpriv->cfg->fw_name; | |
174 | err = request_firmware(&firmware, fw_name, rtlpriv->io.dev); | |
2b8359f8 C |
175 | if (err) { |
176 | RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG, | |
177 | ("Failed to request firmware!\n")); | |
178 | return 1; | |
179 | } | |
180 | if (firmware->size > 0x4000) { | |
181 | RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG, | |
182 | ("Firmware is too big!\n")); | |
183 | release_firmware(firmware); | |
184 | return 1; | |
185 | } | |
186 | memcpy(rtlpriv->rtlhal.pfirmware, firmware->data, firmware->size); | |
187 | rtlpriv->rtlhal.fwsize = firmware->size; | |
188 | release_firmware(firmware); | |
189 | ||
0c817338 LF |
190 | return 0; |
191 | } | |
192 | ||
193 | void rtl92c_deinit_sw_vars(struct ieee80211_hw *hw) | |
194 | { | |
195 | struct rtl_priv *rtlpriv = rtl_priv(hw); | |
196 | ||
197 | if (rtlpriv->rtlhal.pfirmware) { | |
198 | vfree(rtlpriv->rtlhal.pfirmware); | |
199 | rtlpriv->rtlhal.pfirmware = NULL; | |
200 | } | |
201 | } | |
202 | ||
d3bb1429 | 203 | static struct rtl_hal_ops rtl8192ce_hal_ops = { |
0c817338 LF |
204 | .init_sw_vars = rtl92c_init_sw_vars, |
205 | .deinit_sw_vars = rtl92c_deinit_sw_vars, | |
206 | .read_eeprom_info = rtl92ce_read_eeprom_info, | |
207 | .interrupt_recognized = rtl92ce_interrupt_recognized, | |
208 | .hw_init = rtl92ce_hw_init, | |
209 | .hw_disable = rtl92ce_card_disable, | |
2b8359f8 C |
210 | .hw_suspend = rtl92ce_suspend, |
211 | .hw_resume = rtl92ce_resume, | |
0c817338 LF |
212 | .enable_interrupt = rtl92ce_enable_interrupt, |
213 | .disable_interrupt = rtl92ce_disable_interrupt, | |
214 | .set_network_type = rtl92ce_set_network_type, | |
2b8359f8 | 215 | .set_chk_bssid = rtl92ce_set_check_bssid, |
0c817338 LF |
216 | .set_qos = rtl92ce_set_qos, |
217 | .set_bcn_reg = rtl92ce_set_beacon_related_registers, | |
218 | .set_bcn_intv = rtl92ce_set_beacon_interval, | |
219 | .update_interrupt_mask = rtl92ce_update_interrupt_mask, | |
220 | .get_hw_reg = rtl92ce_get_hw_reg, | |
221 | .set_hw_reg = rtl92ce_set_hw_reg, | |
2b8359f8 | 222 | .update_rate_tbl = rtl92ce_update_hal_rate_tbl, |
0c817338 LF |
223 | .fill_tx_desc = rtl92ce_tx_fill_desc, |
224 | .fill_tx_cmddesc = rtl92ce_tx_fill_cmddesc, | |
225 | .query_rx_desc = rtl92ce_rx_query_desc, | |
226 | .set_channel_access = rtl92ce_update_channel_access_setting, | |
227 | .radio_onoff_checking = rtl92ce_gpio_radio_on_off_checking, | |
228 | .set_bw_mode = rtl92c_phy_set_bw_mode, | |
229 | .switch_channel = rtl92c_phy_sw_chnl, | |
230 | .dm_watchdog = rtl92c_dm_watchdog, | |
231 | .scan_operation_backup = rtl92c_phy_scan_operation_backup, | |
2b8359f8 | 232 | .set_rf_power_state = rtl92c_phy_set_rf_power_state, |
0c817338 LF |
233 | .led_control = rtl92ce_led_control, |
234 | .set_desc = rtl92ce_set_desc, | |
235 | .get_desc = rtl92ce_get_desc, | |
236 | .tx_polling = rtl92ce_tx_polling, | |
237 | .enable_hw_sec = rtl92ce_enable_hw_security_config, | |
238 | .set_key = rtl92ce_set_key, | |
239 | .init_sw_leds = rtl92ce_init_sw_leds, | |
0c817338 LF |
240 | .get_bbreg = rtl92c_phy_query_bb_reg, |
241 | .set_bbreg = rtl92c_phy_set_bb_reg, | |
1472d3a8 | 242 | .set_rfreg = rtl92ce_phy_set_rf_reg, |
2b8359f8 | 243 | .get_rfreg = rtl92c_phy_query_rf_reg, |
1472d3a8 LF |
244 | .phy_rf6052_config = rtl92ce_phy_rf6052_config, |
245 | .phy_rf6052_set_cck_txpower = rtl92ce_phy_rf6052_set_cck_txpower, | |
246 | .phy_rf6052_set_ofdm_txpower = rtl92ce_phy_rf6052_set_ofdm_txpower, | |
247 | .config_bb_with_headerfile = _rtl92ce_phy_config_bb_with_headerfile, | |
248 | .config_bb_with_pgheaderfile = _rtl92ce_phy_config_bb_with_pgheaderfile, | |
249 | .phy_lc_calibrate = _rtl92ce_phy_lc_calibrate, | |
099fb8ab | 250 | .phy_set_bw_mode_callback = rtl92ce_phy_set_bw_mode_callback, |
1472d3a8 | 251 | .dm_dynamic_txpower = rtl92ce_dm_dynamic_txpower, |
0c817338 LF |
252 | }; |
253 | ||
d3bb1429 | 254 | static struct rtl_mod_params rtl92ce_mod_params = { |
2b8359f8 C |
255 | .sw_crypto = false, |
256 | .inactiveps = true, | |
257 | .swctrl_lps = false, | |
258 | .fwctrl_lps = true, | |
73a253ca | 259 | .debug = DBG_EMERG, |
0c817338 LF |
260 | }; |
261 | ||
d3bb1429 | 262 | static struct rtl_hal_cfg rtl92ce_hal_cfg = { |
2b8359f8 C |
263 | .bar_id = 2, |
264 | .write_readback = true, | |
0c817338 LF |
265 | .name = "rtl92c_pci", |
266 | .fw_name = "rtlwifi/rtl8192cfw.bin", | |
267 | .ops = &rtl8192ce_hal_ops, | |
268 | .mod_params = &rtl92ce_mod_params, | |
269 | ||
270 | .maps[SYS_ISO_CTRL] = REG_SYS_ISO_CTRL, | |
271 | .maps[SYS_FUNC_EN] = REG_SYS_FUNC_EN, | |
272 | .maps[SYS_CLK] = REG_SYS_CLKR, | |
273 | .maps[MAC_RCR_AM] = AM, | |
274 | .maps[MAC_RCR_AB] = AB, | |
275 | .maps[MAC_RCR_ACRC32] = ACRC32, | |
276 | .maps[MAC_RCR_ACF] = ACF, | |
277 | .maps[MAC_RCR_AAP] = AAP, | |
278 | ||
279 | .maps[EFUSE_TEST] = REG_EFUSE_TEST, | |
280 | .maps[EFUSE_CTRL] = REG_EFUSE_CTRL, | |
281 | .maps[EFUSE_CLK] = 0, | |
282 | .maps[EFUSE_CLK_CTRL] = REG_EFUSE_CTRL, | |
283 | .maps[EFUSE_PWC_EV12V] = PWC_EV12V, | |
284 | .maps[EFUSE_FEN_ELDR] = FEN_ELDR, | |
285 | .maps[EFUSE_LOADER_CLK_EN] = LOADER_CLK_EN, | |
286 | .maps[EFUSE_ANA8M] = EFUSE_ANA8M, | |
287 | .maps[EFUSE_HWSET_MAX_SIZE] = HWSET_MAX_SIZE, | |
2b8359f8 C |
288 | .maps[EFUSE_MAX_SECTION_MAP] = EFUSE_MAX_SECTION, |
289 | .maps[EFUSE_REAL_CONTENT_SIZE] = EFUSE_REAL_CONTENT_LEN, | |
0c817338 LF |
290 | |
291 | .maps[RWCAM] = REG_CAMCMD, | |
292 | .maps[WCAMI] = REG_CAMWRITE, | |
293 | .maps[RCAMO] = REG_CAMREAD, | |
294 | .maps[CAMDBG] = REG_CAMDBG, | |
295 | .maps[SECR] = REG_SECCFG, | |
296 | .maps[SEC_CAM_NONE] = CAM_NONE, | |
297 | .maps[SEC_CAM_WEP40] = CAM_WEP40, | |
298 | .maps[SEC_CAM_TKIP] = CAM_TKIP, | |
299 | .maps[SEC_CAM_AES] = CAM_AES, | |
300 | .maps[SEC_CAM_WEP104] = CAM_WEP104, | |
301 | ||
302 | .maps[RTL_IMR_BCNDMAINT6] = IMR_BCNDMAINT6, | |
303 | .maps[RTL_IMR_BCNDMAINT5] = IMR_BCNDMAINT5, | |
304 | .maps[RTL_IMR_BCNDMAINT4] = IMR_BCNDMAINT4, | |
305 | .maps[RTL_IMR_BCNDMAINT3] = IMR_BCNDMAINT3, | |
306 | .maps[RTL_IMR_BCNDMAINT2] = IMR_BCNDMAINT2, | |
307 | .maps[RTL_IMR_BCNDMAINT1] = IMR_BCNDMAINT1, | |
308 | .maps[RTL_IMR_BCNDOK8] = IMR_BCNDOK8, | |
309 | .maps[RTL_IMR_BCNDOK7] = IMR_BCNDOK7, | |
310 | .maps[RTL_IMR_BCNDOK6] = IMR_BCNDOK6, | |
311 | .maps[RTL_IMR_BCNDOK5] = IMR_BCNDOK5, | |
312 | .maps[RTL_IMR_BCNDOK4] = IMR_BCNDOK4, | |
313 | .maps[RTL_IMR_BCNDOK3] = IMR_BCNDOK3, | |
314 | .maps[RTL_IMR_BCNDOK2] = IMR_BCNDOK2, | |
315 | .maps[RTL_IMR_BCNDOK1] = IMR_BCNDOK1, | |
316 | .maps[RTL_IMR_TIMEOUT2] = IMR_TIMEOUT2, | |
317 | .maps[RTL_IMR_TIMEOUT1] = IMR_TIMEOUT1, | |
318 | ||
319 | .maps[RTL_IMR_TXFOVW] = IMR_TXFOVW, | |
320 | .maps[RTL_IMR_PSTIMEOUT] = IMR_PSTIMEOUT, | |
321 | .maps[RTL_IMR_BcnInt] = IMR_BCNINT, | |
322 | .maps[RTL_IMR_RXFOVW] = IMR_RXFOVW, | |
323 | .maps[RTL_IMR_RDU] = IMR_RDU, | |
324 | .maps[RTL_IMR_ATIMEND] = IMR_ATIMEND, | |
325 | .maps[RTL_IMR_BDOK] = IMR_BDOK, | |
326 | .maps[RTL_IMR_MGNTDOK] = IMR_MGNTDOK, | |
327 | .maps[RTL_IMR_TBDER] = IMR_TBDER, | |
328 | .maps[RTL_IMR_HIGHDOK] = IMR_HIGHDOK, | |
329 | .maps[RTL_IMR_TBDOK] = IMR_TBDOK, | |
330 | .maps[RTL_IMR_BKDOK] = IMR_BKDOK, | |
331 | .maps[RTL_IMR_BEDOK] = IMR_BEDOK, | |
332 | .maps[RTL_IMR_VIDOK] = IMR_VIDOK, | |
333 | .maps[RTL_IMR_VODOK] = IMR_VODOK, | |
334 | .maps[RTL_IMR_ROK] = IMR_ROK, | |
335 | .maps[RTL_IBSS_INT_MASKS] = (IMR_BCNINT | IMR_TBDOK | IMR_TBDER), | |
336 | ||
78851b66 LF |
337 | .maps[RTL_RC_CCK_RATE1M] = DESC92_RATE1M, |
338 | .maps[RTL_RC_CCK_RATE2M] = DESC92_RATE2M, | |
339 | .maps[RTL_RC_CCK_RATE5_5M] = DESC92_RATE5_5M, | |
340 | .maps[RTL_RC_CCK_RATE11M] = DESC92_RATE11M, | |
341 | .maps[RTL_RC_OFDM_RATE6M] = DESC92_RATE6M, | |
342 | .maps[RTL_RC_OFDM_RATE9M] = DESC92_RATE9M, | |
343 | .maps[RTL_RC_OFDM_RATE12M] = DESC92_RATE12M, | |
344 | .maps[RTL_RC_OFDM_RATE18M] = DESC92_RATE18M, | |
345 | .maps[RTL_RC_OFDM_RATE24M] = DESC92_RATE24M, | |
346 | .maps[RTL_RC_OFDM_RATE36M] = DESC92_RATE36M, | |
347 | .maps[RTL_RC_OFDM_RATE48M] = DESC92_RATE48M, | |
348 | .maps[RTL_RC_OFDM_RATE54M] = DESC92_RATE54M, | |
349 | ||
350 | .maps[RTL_RC_HT_RATEMCS7] = DESC92_RATEMCS7, | |
351 | .maps[RTL_RC_HT_RATEMCS15] = DESC92_RATEMCS15, | |
0c817338 LF |
352 | }; |
353 | ||
2b8359f8 | 354 | DEFINE_PCI_DEVICE_TABLE(rtl92ce_pci_ids) = { |
0c817338 LF |
355 | {RTL_PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8191, rtl92ce_hal_cfg)}, |
356 | {RTL_PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8178, rtl92ce_hal_cfg)}, | |
357 | {RTL_PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8177, rtl92ce_hal_cfg)}, | |
358 | {RTL_PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8176, rtl92ce_hal_cfg)}, | |
359 | {}, | |
360 | }; | |
361 | ||
362 | MODULE_DEVICE_TABLE(pci, rtl92ce_pci_ids); | |
363 | ||
364 | MODULE_AUTHOR("lizhaoming <chaoming_li@realsil.com.cn>"); | |
365 | MODULE_AUTHOR("Realtek WlanFAE <wlanfae@realtek.com>"); | |
366 | MODULE_AUTHOR("Larry Finger <Larry.Finger@lwfinger.net>"); | |
367 | MODULE_LICENSE("GPL"); | |
368 | MODULE_DESCRIPTION("Realtek 8192C/8188C 802.11n PCI wireless"); | |
369 | MODULE_FIRMWARE("rtlwifi/rtl8192cfw.bin"); | |
db759939 CL |
370 | MODULE_FIRMWARE("rtlwifi/rtl8192cfwU.bin"); |
371 | MODULE_FIRMWARE("rtlwifi/rtl8192cfwU_B.bin"); | |
0c817338 LF |
372 | |
373 | module_param_named(swenc, rtl92ce_mod_params.sw_crypto, bool, 0444); | |
73a253ca | 374 | module_param_named(debug, rtl92ce_mod_params.debug, int, 0444); |
2b8359f8 C |
375 | module_param_named(ips, rtl92ce_mod_params.inactiveps, bool, 0444); |
376 | module_param_named(swlps, rtl92ce_mod_params.swctrl_lps, bool, 0444); | |
377 | module_param_named(fwlps, rtl92ce_mod_params.fwctrl_lps, bool, 0444); | |
eed72316 LF |
378 | MODULE_PARM_DESC(swenc, "Set to 1 for software crypto (default 0)\n"); |
379 | MODULE_PARM_DESC(ips, "Set to 0 to not use link power save (default 1)\n"); | |
380 | MODULE_PARM_DESC(swlps, "Set to 1 to use SW control power save (default 0)\n"); | |
381 | MODULE_PARM_DESC(fwlps, "Set to 1 to use FW control power save (default 1)\n"); | |
73a253ca | 382 | MODULE_PARM_DESC(debug, "Set debug level (0-5) (default 0)"); |
0c817338 | 383 | |
603be388 LF |
384 | static const struct dev_pm_ops rtlwifi_pm_ops = { |
385 | .suspend = rtl_pci_suspend, | |
386 | .resume = rtl_pci_resume, | |
387 | .freeze = rtl_pci_suspend, | |
388 | .thaw = rtl_pci_resume, | |
389 | .poweroff = rtl_pci_suspend, | |
390 | .restore = rtl_pci_resume, | |
391 | }; | |
392 | ||
0c817338 LF |
393 | static struct pci_driver rtl92ce_driver = { |
394 | .name = KBUILD_MODNAME, | |
395 | .id_table = rtl92ce_pci_ids, | |
396 | .probe = rtl_pci_probe, | |
397 | .remove = rtl_pci_disconnect, | |
603be388 | 398 | .driver.pm = &rtlwifi_pm_ops, |
0c817338 LF |
399 | }; |
400 | ||
401 | static int __init rtl92ce_module_init(void) | |
402 | { | |
403 | int ret; | |
404 | ||
405 | ret = pci_register_driver(&rtl92ce_driver); | |
406 | if (ret) | |
407 | RT_ASSERT(false, (": No device found\n")); | |
408 | ||
409 | return ret; | |
410 | } | |
411 | ||
412 | static void __exit rtl92ce_module_exit(void) | |
413 | { | |
414 | pci_unregister_driver(&rtl92ce_driver); | |
415 | } | |
416 | ||
417 | module_init(rtl92ce_module_init); | |
418 | module_exit(rtl92ce_module_exit); |