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ath9k: Advertise support for AP mode channel width changes
[deliverable/linux.git] / drivers / net / wireless / rtlwifi / rtl8192cu / hw.c
CommitLineData
dc0313f4
G		 1/******************************************************************************
2 *
c1d6604d 3 * Copyright(c) 2009-2012 Realtek Corporation. All rights reserved.
dc0313f4
G		 4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of version 2 of the GNU General Public License as
7 * published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details.
13 *
14 * You should have received a copy of the GNU General Public License along with
15 * this program; if not, write to the Free Software Foundation, Inc.,
16 * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
17 *
18 * The full GNU General Public License is included in this distribution in the
19 * file called LICENSE.
20 *
21 * Contact Information:
22 * wlanfae <wlanfae@realtek.com>
23 * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
24 * Hsinchu 300, Taiwan.
25 *
26 * Larry Finger <Larry.Finger@lwfinger.net>
27 *
28 *****************************************************************************/
29
30#include "../wifi.h"
31#include "../efuse.h"
32#include "../base.h"
33#include "../cam.h"
34#include "../ps.h"
35#include "../usb.h"
36#include "reg.h"
37#include "def.h"
38#include "phy.h"
39#include "mac.h"
40#include "dm.h"
dc0313f4 41#include "hw.h"
76c34f91 42#include "../rtl8192ce/hw.h"
dc0313f4
G		 43#include "trx.h"
44#include "led.h"
45#include "table.h"
46
47static void _rtl92cu_phy_param_tab_init(struct ieee80211_hw *hw)
48{
49 struct rtl_priv *rtlpriv = rtl_priv(hw);
50 struct rtl_phy *rtlphy = &(rtlpriv->phy);
51 struct rtl_efuse *rtlefuse = rtl_efuse(rtlpriv);
52
53 rtlphy->hwparam_tables[MAC_REG].length = RTL8192CUMAC_2T_ARRAYLENGTH;
54 rtlphy->hwparam_tables[MAC_REG].pdata = RTL8192CUMAC_2T_ARRAY;
55 if (IS_HIGHT_PA(rtlefuse->board_type)) {
56 rtlphy->hwparam_tables[PHY_REG_PG].length =
57 RTL8192CUPHY_REG_Array_PG_HPLength;
58 rtlphy->hwparam_tables[PHY_REG_PG].pdata =
59 RTL8192CUPHY_REG_Array_PG_HP;
60 } else {
61 rtlphy->hwparam_tables[PHY_REG_PG].length =
62 RTL8192CUPHY_REG_ARRAY_PGLENGTH;
63 rtlphy->hwparam_tables[PHY_REG_PG].pdata =
64 RTL8192CUPHY_REG_ARRAY_PG;
65 }
66 /* 2T */
67 rtlphy->hwparam_tables[PHY_REG_2T].length =
68 RTL8192CUPHY_REG_2TARRAY_LENGTH;
69 rtlphy->hwparam_tables[PHY_REG_2T].pdata =
70 RTL8192CUPHY_REG_2TARRAY;
71 rtlphy->hwparam_tables[RADIOA_2T].length =
72 RTL8192CURADIOA_2TARRAYLENGTH;
73 rtlphy->hwparam_tables[RADIOA_2T].pdata =
74 RTL8192CURADIOA_2TARRAY;
75 rtlphy->hwparam_tables[RADIOB_2T].length =
76 RTL8192CURADIOB_2TARRAYLENGTH;
77 rtlphy->hwparam_tables[RADIOB_2T].pdata =
78 RTL8192CU_RADIOB_2TARRAY;
79 rtlphy->hwparam_tables[AGCTAB_2T].length =
80 RTL8192CUAGCTAB_2TARRAYLENGTH;
81 rtlphy->hwparam_tables[AGCTAB_2T].pdata =
82 RTL8192CUAGCTAB_2TARRAY;
83 /* 1T */
84 if (IS_HIGHT_PA(rtlefuse->board_type)) {
85 rtlphy->hwparam_tables[PHY_REG_1T].length =
86 RTL8192CUPHY_REG_1T_HPArrayLength;
87 rtlphy->hwparam_tables[PHY_REG_1T].pdata =
88 RTL8192CUPHY_REG_1T_HPArray;
89 rtlphy->hwparam_tables[RADIOA_1T].length =
90 RTL8192CURadioA_1T_HPArrayLength;
91 rtlphy->hwparam_tables[RADIOA_1T].pdata =
92 RTL8192CURadioA_1T_HPArray;
93 rtlphy->hwparam_tables[RADIOB_1T].length =
94 RTL8192CURADIOB_1TARRAYLENGTH;
95 rtlphy->hwparam_tables[RADIOB_1T].pdata =
96 RTL8192CU_RADIOB_1TARRAY;
97 rtlphy->hwparam_tables[AGCTAB_1T].length =
98 RTL8192CUAGCTAB_1T_HPArrayLength;
99 rtlphy->hwparam_tables[AGCTAB_1T].pdata =
100 Rtl8192CUAGCTAB_1T_HPArray;
101 } else {
102 rtlphy->hwparam_tables[PHY_REG_1T].length =
103 RTL8192CUPHY_REG_1TARRAY_LENGTH;
104 rtlphy->hwparam_tables[PHY_REG_1T].pdata =
105 RTL8192CUPHY_REG_1TARRAY;
106 rtlphy->hwparam_tables[RADIOA_1T].length =
107 RTL8192CURADIOA_1TARRAYLENGTH;
108 rtlphy->hwparam_tables[RADIOA_1T].pdata =
109 RTL8192CU_RADIOA_1TARRAY;
110 rtlphy->hwparam_tables[RADIOB_1T].length =
111 RTL8192CURADIOB_1TARRAYLENGTH;
112 rtlphy->hwparam_tables[RADIOB_1T].pdata =
113 RTL8192CU_RADIOB_1TARRAY;
114 rtlphy->hwparam_tables[AGCTAB_1T].length =
115 RTL8192CUAGCTAB_1TARRAYLENGTH;
116 rtlphy->hwparam_tables[AGCTAB_1T].pdata =
117 RTL8192CUAGCTAB_1TARRAY;
118 }
119}
120
121static void _rtl92cu_read_txpower_info_from_hwpg(struct ieee80211_hw *hw,
122 bool autoload_fail,
123 u8 *hwinfo)
124{
125 struct rtl_priv *rtlpriv = rtl_priv(hw);
126 struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
127 u8 rf_path, index, tempval;
128 u16 i;
129
130 for (rf_path = 0; rf_path < 2; rf_path++) {
131 for (i = 0; i < 3; i++) {
132 if (!autoload_fail) {
133 rtlefuse->
134 eeprom_chnlarea_txpwr_cck[rf_path][i] =
135 hwinfo[EEPROM_TXPOWERCCK + rf_path * 3 + i];
136 rtlefuse->
137 eeprom_chnlarea_txpwr_ht40_1s[rf_path][i] =
138 hwinfo[EEPROM_TXPOWERHT40_1S + rf_path * 3 +
139 i];
140 } else {
141 rtlefuse->
142 eeprom_chnlarea_txpwr_cck[rf_path][i] =
143 EEPROM_DEFAULT_TXPOWERLEVEL;
144 rtlefuse->
145 eeprom_chnlarea_txpwr_ht40_1s[rf_path][i] =
146 EEPROM_DEFAULT_TXPOWERLEVEL;
147 }
148 }
149 }
150 for (i = 0; i < 3; i++) {
151 if (!autoload_fail)
152 tempval = hwinfo[EEPROM_TXPOWERHT40_2SDIFF + i];
153 else
154 tempval = EEPROM_DEFAULT_HT40_2SDIFF;
da17fcff 155 rtlefuse->eprom_chnl_txpwr_ht40_2sdf[RF90_PATH_A][i] =
dc0313f4 156 (tempval & 0xf);
da17fcff 157 rtlefuse->eprom_chnl_txpwr_ht40_2sdf[RF90_PATH_B][i] =
dc0313f4
G		 158 ((tempval & 0xf0) >> 4);
159 }
160 for (rf_path = 0; rf_path < 2; rf_path++)
161 for (i = 0; i < 3; i++)
162 RTPRINT(rtlpriv, FINIT, INIT_EEPROM,
4c48869f
JP		 163 "RF(%d) EEPROM CCK Area(%d) = 0x%x\n",
164 rf_path, i,
165 rtlefuse->
166 eeprom_chnlarea_txpwr_cck[rf_path][i]);
dc0313f4
G		 167 for (rf_path = 0; rf_path < 2; rf_path++)
168 for (i = 0; i < 3; i++)
169 RTPRINT(rtlpriv, FINIT, INIT_EEPROM,
4c48869f
JP		 170 "RF(%d) EEPROM HT40 1S Area(%d) = 0x%x\n",
171 rf_path, i,
172 rtlefuse->
173 eeprom_chnlarea_txpwr_ht40_1s[rf_path][i]);
dc0313f4
G		 174 for (rf_path = 0; rf_path < 2; rf_path++)
175 for (i = 0; i < 3; i++)
176 RTPRINT(rtlpriv, FINIT, INIT_EEPROM,
4c48869f
JP		 177 "RF(%d) EEPROM HT40 2S Diff Area(%d) = 0x%x\n",
178 rf_path, i,
179 rtlefuse->
da17fcff 180 eprom_chnl_txpwr_ht40_2sdf[rf_path][i]);
dc0313f4
G		 181 for (rf_path = 0; rf_path < 2; rf_path++) {
182 for (i = 0; i < 14; i++) {
183 index = _rtl92c_get_chnl_group((u8) i);
184 rtlefuse->txpwrlevel_cck[rf_path][i] =
185 rtlefuse->eeprom_chnlarea_txpwr_cck[rf_path][index];
186 rtlefuse->txpwrlevel_ht40_1s[rf_path][i] =
187 rtlefuse->
188 eeprom_chnlarea_txpwr_ht40_1s[rf_path][index];
189 if ((rtlefuse->
190 eeprom_chnlarea_txpwr_ht40_1s[rf_path][index] -
191 rtlefuse->
da17fcff 192 eprom_chnl_txpwr_ht40_2sdf[rf_path][index])
dc0313f4
G		 193 > 0) {
194 rtlefuse->txpwrlevel_ht40_2s[rf_path][i] =
195 rtlefuse->
196 eeprom_chnlarea_txpwr_ht40_1s[rf_path]
197 [index] - rtlefuse->
da17fcff 198 eprom_chnl_txpwr_ht40_2sdf[rf_path]
dc0313f4
G		 199 [index];
200 } else {
201 rtlefuse->txpwrlevel_ht40_2s[rf_path][i] = 0;
202 }
203 }
204 for (i = 0; i < 14; i++) {
e6deaf81 205 RTPRINT(rtlpriv, FINIT, INIT_TXPOWER,
4c48869f
JP		 206 "RF(%d)-Ch(%d) [CCK / HT40_1S / HT40_2S] = [0x%x / 0x%x / 0x%x]\n", rf_path, i,
207 rtlefuse->txpwrlevel_cck[rf_path][i],
208 rtlefuse->txpwrlevel_ht40_1s[rf_path][i],
209 rtlefuse->txpwrlevel_ht40_2s[rf_path][i]);
dc0313f4
G		 210 }
211 }
212 for (i = 0; i < 3; i++) {
213 if (!autoload_fail) {
214 rtlefuse->eeprom_pwrlimit_ht40[i] =
215 hwinfo[EEPROM_TXPWR_GROUP + i];
216 rtlefuse->eeprom_pwrlimit_ht20[i] =
217 hwinfo[EEPROM_TXPWR_GROUP + 3 + i];
218 } else {
219 rtlefuse->eeprom_pwrlimit_ht40[i] = 0;
220 rtlefuse->eeprom_pwrlimit_ht20[i] = 0;
221 }
222 }
223 for (rf_path = 0; rf_path < 2; rf_path++) {
224 for (i = 0; i < 14; i++) {
225 index = _rtl92c_get_chnl_group((u8) i);
226 if (rf_path == RF90_PATH_A) {
227 rtlefuse->pwrgroup_ht20[rf_path][i] =
228 (rtlefuse->eeprom_pwrlimit_ht20[index]
229 & 0xf);
230 rtlefuse->pwrgroup_ht40[rf_path][i] =
231 (rtlefuse->eeprom_pwrlimit_ht40[index]
232 & 0xf);
233 } else if (rf_path == RF90_PATH_B) {
234 rtlefuse->pwrgroup_ht20[rf_path][i] =
235 ((rtlefuse->eeprom_pwrlimit_ht20[index]
236 & 0xf0) >> 4);
237 rtlefuse->pwrgroup_ht40[rf_path][i] =
238 ((rtlefuse->eeprom_pwrlimit_ht40[index]
239 & 0xf0) >> 4);
240 }
e6deaf81 241 RTPRINT(rtlpriv, FINIT, INIT_TXPOWER,
4c48869f
JP		 242 "RF-%d pwrgroup_ht20[%d] = 0x%x\n",
243 rf_path, i,
244 rtlefuse->pwrgroup_ht20[rf_path][i]);
e6deaf81 245 RTPRINT(rtlpriv, FINIT, INIT_TXPOWER,
4c48869f
JP		 246 "RF-%d pwrgroup_ht40[%d] = 0x%x\n",
247 rf_path, i,
248 rtlefuse->pwrgroup_ht40[rf_path][i]);
dc0313f4
G		 249 }
250 }
251 for (i = 0; i < 14; i++) {
252 index = _rtl92c_get_chnl_group((u8) i);
253 if (!autoload_fail)
254 tempval = hwinfo[EEPROM_TXPOWERHT20DIFF + index];
255 else
256 tempval = EEPROM_DEFAULT_HT20_DIFF;
257 rtlefuse->txpwr_ht20diff[RF90_PATH_A][i] = (tempval & 0xF);
258 rtlefuse->txpwr_ht20diff[RF90_PATH_B][i] =
259 ((tempval >> 4) & 0xF);
260 if (rtlefuse->txpwr_ht20diff[RF90_PATH_A][i] & BIT(3))
261 rtlefuse->txpwr_ht20diff[RF90_PATH_A][i] |= 0xF0;
262 if (rtlefuse->txpwr_ht20diff[RF90_PATH_B][i] & BIT(3))
263 rtlefuse->txpwr_ht20diff[RF90_PATH_B][i] |= 0xF0;
264 index = _rtl92c_get_chnl_group((u8) i);
265 if (!autoload_fail)
266 tempval = hwinfo[EEPROM_TXPOWER_OFDMDIFF + index];
267 else
268 tempval = EEPROM_DEFAULT_LEGACYHTTXPOWERDIFF;
269 rtlefuse->txpwr_legacyhtdiff[RF90_PATH_A][i] = (tempval & 0xF);
270 rtlefuse->txpwr_legacyhtdiff[RF90_PATH_B][i] =
271 ((tempval >> 4) & 0xF);
272 }
273 rtlefuse->legacy_ht_txpowerdiff =
274 rtlefuse->txpwr_legacyhtdiff[RF90_PATH_A][7];
275 for (i = 0; i < 14; i++)
e6deaf81 276 RTPRINT(rtlpriv, FINIT, INIT_TXPOWER,
4c48869f
JP		 277 "RF-A Ht20 to HT40 Diff[%d] = 0x%x\n",
278 i, rtlefuse->txpwr_ht20diff[RF90_PATH_A][i]);
dc0313f4 279 for (i = 0; i < 14; i++)
e6deaf81 280 RTPRINT(rtlpriv, FINIT, INIT_TXPOWER,
4c48869f
JP		 281 "RF-A Legacy to Ht40 Diff[%d] = 0x%x\n",
282 i, rtlefuse->txpwr_legacyhtdiff[RF90_PATH_A][i]);
dc0313f4 283 for (i = 0; i < 14; i++)
e6deaf81 284 RTPRINT(rtlpriv, FINIT, INIT_TXPOWER,
4c48869f
JP		 285 "RF-B Ht20 to HT40 Diff[%d] = 0x%x\n",
286 i, rtlefuse->txpwr_ht20diff[RF90_PATH_B][i]);
dc0313f4 287 for (i = 0; i < 14; i++)
e6deaf81 288 RTPRINT(rtlpriv, FINIT, INIT_TXPOWER,
4c48869f
JP		 289 "RF-B Legacy to HT40 Diff[%d] = 0x%x\n",
290 i, rtlefuse->txpwr_legacyhtdiff[RF90_PATH_B][i]);
dc0313f4
G		 291 if (!autoload_fail)
292 rtlefuse->eeprom_regulatory = (hwinfo[RF_OPTION1] & 0x7);
293 else
294 rtlefuse->eeprom_regulatory = 0;
e6deaf81 295 RTPRINT(rtlpriv, FINIT, INIT_TXPOWER,
4c48869f 296 "eeprom_regulatory = 0x%x\n", rtlefuse->eeprom_regulatory);
dc0313f4
G		 297 if (!autoload_fail) {
298 rtlefuse->eeprom_tssi[RF90_PATH_A] = hwinfo[EEPROM_TSSI_A];
299 rtlefuse->eeprom_tssi[RF90_PATH_B] = hwinfo[EEPROM_TSSI_B];
300 } else {
301 rtlefuse->eeprom_tssi[RF90_PATH_A] = EEPROM_DEFAULT_TSSI;
302 rtlefuse->eeprom_tssi[RF90_PATH_B] = EEPROM_DEFAULT_TSSI;
303 }
e6deaf81 304 RTPRINT(rtlpriv, FINIT, INIT_TXPOWER,
4c48869f
JP		 305 "TSSI_A = 0x%x, TSSI_B = 0x%x\n",
306 rtlefuse->eeprom_tssi[RF90_PATH_A],
307 rtlefuse->eeprom_tssi[RF90_PATH_B]);
dc0313f4
G		 308 if (!autoload_fail)
309 tempval = hwinfo[EEPROM_THERMAL_METER];
310 else
311 tempval = EEPROM_DEFAULT_THERMALMETER;
312 rtlefuse->eeprom_thermalmeter = (tempval & 0x1f);
313 if (rtlefuse->eeprom_thermalmeter < 0x06 ||
314 rtlefuse->eeprom_thermalmeter > 0x1c)
315 rtlefuse->eeprom_thermalmeter = 0x12;
316 if (rtlefuse->eeprom_thermalmeter == 0x1f || autoload_fail)
317 rtlefuse->apk_thermalmeterignore = true;
318 rtlefuse->thermalmeter[0] = rtlefuse->eeprom_thermalmeter;
e6deaf81 319 RTPRINT(rtlpriv, FINIT, INIT_TXPOWER,
4c48869f 320 "thermalmeter = 0x%x\n", rtlefuse->eeprom_thermalmeter);
dc0313f4
G		 321}
322
323static void _rtl92cu_read_board_type(struct ieee80211_hw *hw, u8 *contents)
324{
325 struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
326 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
327 u8 boardType;
328
329 if (IS_NORMAL_CHIP(rtlhal->version)) {
330 boardType = ((contents[EEPROM_RF_OPT1]) &
331 BOARD_TYPE_NORMAL_MASK) >> 5; /*bit[7:5]*/
332 } else {
333 boardType = contents[EEPROM_RF_OPT4];
334 boardType &= BOARD_TYPE_TEST_MASK;
335 }
336 rtlefuse->board_type = boardType;
337 if (IS_HIGHT_PA(rtlefuse->board_type))
338 rtlefuse->external_pa = 1;
292b1192 339 pr_info("Board Type %x\n", rtlefuse->board_type);
dc0313f4
G		 340}
341
dc0313f4
G		 342static void _rtl92cu_read_adapter_info(struct ieee80211_hw *hw)
343{
344 struct rtl_priv *rtlpriv = rtl_priv(hw);
345 struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
346 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
347 u16 i, usvalue;
348 u8 hwinfo[HWSET_MAX_SIZE] = {0};
349 u16 eeprom_id;
350
351 if (rtlefuse->epromtype == EEPROM_BOOT_EFUSE) {
352 rtl_efuse_shadow_map_update(hw);
353 memcpy((void *)hwinfo,
354 (void *)&rtlefuse->efuse_map[EFUSE_INIT_MAP][0],
355 HWSET_MAX_SIZE);
356 } else if (rtlefuse->epromtype == EEPROM_93C46) {
357 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
f30d7507 358 "RTL819X Not boot from eeprom, check it !!\n");
dc0313f4 359 }
af08687b 360 RT_PRINT_DATA(rtlpriv, COMP_INIT, DBG_LOUD, "MAP",
dc0313f4 361 hwinfo, HWSET_MAX_SIZE);
abfabc9b 362 eeprom_id = le16_to_cpu(*((__le16 *)&hwinfo[0]));
dc0313f4
G		 363 if (eeprom_id != RTL8190_EEPROM_ID) {
364 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
f30d7507 365 "EEPROM ID(%#x) is invalid!!\n", eeprom_id);
dc0313f4
G		 366 rtlefuse->autoload_failflag = true;
367 } else {
f30d7507 368 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, "Autoload OK\n");
dc0313f4
G		 369 rtlefuse->autoload_failflag = false;
370 }
e10542c4 371 if (rtlefuse->autoload_failflag)
dc0313f4
G		 372 return;
373 for (i = 0; i < 6; i += 2) {
374 usvalue = *(u16 *)&hwinfo[EEPROM_MAC_ADDR + i];
375 *((u16 *) (&rtlefuse->dev_addr[i])) = usvalue;
376 }
292b1192 377 pr_info("MAC address: %pM\n", rtlefuse->dev_addr);
dc0313f4
G		 378 _rtl92cu_read_txpower_info_from_hwpg(hw,
379 rtlefuse->autoload_failflag, hwinfo);
abfabc9b
LF		 380 rtlefuse->eeprom_vid = le16_to_cpu(*(__le16 *)&hwinfo[EEPROM_VID]);
381 rtlefuse->eeprom_did = le16_to_cpu(*(__le16 *)&hwinfo[EEPROM_DID]);
f30d7507
JP		 382 RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG, " VID = 0x%02x PID = 0x%02x\n",
383 rtlefuse->eeprom_vid, rtlefuse->eeprom_did);
2c208890 384 rtlefuse->eeprom_channelplan = hwinfo[EEPROM_CHANNELPLAN];
abfabc9b
LF		 385 rtlefuse->eeprom_version =
386 le16_to_cpu(*(__le16 *)&hwinfo[EEPROM_VERSION]);
dc0313f4 387 rtlefuse->txpwr_fromeprom = true;
2c208890 388 rtlefuse->eeprom_oemid = hwinfo[EEPROM_CUSTOMER_ID];
f30d7507
JP		 389 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, "EEPROM Customer ID: 0x%2x\n",
390 rtlefuse->eeprom_oemid);
dc0313f4
G		 391 if (rtlhal->oem_id == RT_CID_DEFAULT) {
392 switch (rtlefuse->eeprom_oemid) {
393 case EEPROM_CID_DEFAULT:
394 if (rtlefuse->eeprom_did == 0x8176) {
395 if ((rtlefuse->eeprom_svid == 0x103C &&
396 rtlefuse->eeprom_smid == 0x1629))
2cddad3c 397 rtlhal->oem_id = RT_CID_819X_HP;
dc0313f4
G		 398 else
399 rtlhal->oem_id = RT_CID_DEFAULT;
400 } else {
401 rtlhal->oem_id = RT_CID_DEFAULT;
402 }
403 break;
404 case EEPROM_CID_TOSHIBA:
405 rtlhal->oem_id = RT_CID_TOSHIBA;
406 break;
407 case EEPROM_CID_QMI:
2cddad3c 408 rtlhal->oem_id = RT_CID_819X_QMI;
dc0313f4
G		 409 break;
410 case EEPROM_CID_WHQL:
411 default:
412 rtlhal->oem_id = RT_CID_DEFAULT;
413 break;
414 }
415 }
416 _rtl92cu_read_board_type(hw, hwinfo);
dc0313f4
G		 417}
418
419static void _rtl92cu_hal_customized_behavior(struct ieee80211_hw *hw)
420{
421 struct rtl_priv *rtlpriv = rtl_priv(hw);
422 struct rtl_usb_priv *usb_priv = rtl_usbpriv(hw);
423 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
424
425 switch (rtlhal->oem_id) {
2cddad3c 426 case RT_CID_819X_HP:
dc0313f4
G		 427 usb_priv->ledctl.led_opendrain = true;
428 break;
2cddad3c 429 case RT_CID_819X_LENOVO:
dc0313f4
G		 430 case RT_CID_DEFAULT:
431 case RT_CID_TOSHIBA:
432 case RT_CID_CCX:
2cddad3c 433 case RT_CID_819X_ACER:
dc0313f4
G		 434 case RT_CID_WHQL:
435 default:
436 break;
437 }
f30d7507
JP		 438 RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG, "RT Customized ID: 0x%02X\n",
439 rtlhal->oem_id);
dc0313f4
G		 440}
441
442void rtl92cu_read_eeprom_info(struct ieee80211_hw *hw)
443{
444
445 struct rtl_priv *rtlpriv = rtl_priv(hw);
446 struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
447 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
448 u8 tmp_u1b;
449
450 if (!IS_NORMAL_CHIP(rtlhal->version))
451 return;
452 tmp_u1b = rtl_read_byte(rtlpriv, REG_9346CR);
76c34f91 453 rtlefuse->epromtype = (tmp_u1b & BOOT_FROM_EEPROM) ?
dc0313f4 454 EEPROM_93C46 : EEPROM_BOOT_EFUSE;
f30d7507
JP		 455 RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG, "Boot from %s\n",
456 tmp_u1b & BOOT_FROM_EEPROM ? "EERROM" : "EFUSE");
dc0313f4 457 rtlefuse->autoload_failflag = (tmp_u1b & EEPROM_EN) ? false : true;
f30d7507
JP		 458 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, "Autoload %s\n",
459 tmp_u1b & EEPROM_EN ? "OK!!" : "ERR!!");
dc0313f4
G		 460 _rtl92cu_read_adapter_info(hw);
461 _rtl92cu_hal_customized_behavior(hw);
462 return;
463}
464
465static int _rtl92cu_init_power_on(struct ieee80211_hw *hw)
466{
467 struct rtl_priv *rtlpriv = rtl_priv(hw);
468 int status = 0;
469 u16 value16;
470 u8 value8;
471 /* polling autoload done. */
472 u32 pollingCount = 0;
473
474 do {
475 if (rtl_read_byte(rtlpriv, REG_APS_FSMCO) & PFM_ALDN) {
476 RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG,
f30d7507 477 "Autoload Done!\n");
dc0313f4
G		 478 break;
479 }
480 if (pollingCount++ > 100) {
481 RT_TRACE(rtlpriv, COMP_INIT, DBG_EMERG,
f30d7507 482 "Failed to polling REG_APS_FSMCO[PFM_ALDN] done!\n");
dc0313f4
G		 483 return -ENODEV;
484 }
485 } while (true);
486 /* 0. RSV_CTRL 0x1C[7:0] = 0 unlock ISO/CLK/Power control register */
487 rtl_write_byte(rtlpriv, REG_RSV_CTRL, 0x0);
488 /* Power on when re-enter from IPS/Radio off/card disable */
489 /* enable SPS into PWM mode */
490 rtl_write_byte(rtlpriv, REG_SPS0_CTRL, 0x2b);
491 udelay(100);
492 value8 = rtl_read_byte(rtlpriv, REG_LDOV12D_CTRL);
493 if (0 == (value8 & LDV12_EN)) {
494 value8 |= LDV12_EN;
495 rtl_write_byte(rtlpriv, REG_LDOV12D_CTRL, value8);
496 RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG,
f30d7507
JP		 497 " power-on :REG_LDOV12D_CTRL Reg0x21:0x%02x\n",
498 value8);
dc0313f4
G		 499 udelay(100);
500 value8 = rtl_read_byte(rtlpriv, REG_SYS_ISO_CTRL);
501 value8 &= ~ISO_MD2PP;
502 rtl_write_byte(rtlpriv, REG_SYS_ISO_CTRL, value8);
503 }
504 /* auto enable WLAN */
505 pollingCount = 0;
506 value16 = rtl_read_word(rtlpriv, REG_APS_FSMCO);
507 value16 |= APFM_ONMAC;
508 rtl_write_word(rtlpriv, REG_APS_FSMCO, value16);
509 do {
510 if (!(rtl_read_word(rtlpriv, REG_APS_FSMCO) & APFM_ONMAC)) {
292b1192 511 pr_info("MAC auto ON okay!\n");
dc0313f4
G		 512 break;
513 }
514 if (pollingCount++ > 100) {
515 RT_TRACE(rtlpriv, COMP_INIT, DBG_EMERG,
f30d7507 516 "Failed to polling REG_APS_FSMCO[APFM_ONMAC] done!\n");
dc0313f4
G		 517 return -ENODEV;
518 }
519 } while (true);
520 /* Enable Radio ,GPIO ,and LED function */
521 rtl_write_word(rtlpriv, REG_APS_FSMCO, 0x0812);
522 /* release RF digital isolation */
523 value16 = rtl_read_word(rtlpriv, REG_SYS_ISO_CTRL);
524 value16 &= ~ISO_DIOR;
525 rtl_write_word(rtlpriv, REG_SYS_ISO_CTRL, value16);
526 /* Reconsider when to do this operation after asking HWSD. */
527 pollingCount = 0;
528 rtl_write_byte(rtlpriv, REG_APSD_CTRL, (rtl_read_byte(rtlpriv,
529 REG_APSD_CTRL) & ~BIT(6)));
530 do {
531 pollingCount++;
532 } while ((pollingCount < 200) &&
533 (rtl_read_byte(rtlpriv, REG_APSD_CTRL) & BIT(7)));
534 /* Enable MAC DMA/WMAC/SCHEDULE/SEC block */
535 value16 = rtl_read_word(rtlpriv, REG_CR);
536 value16 |= (HCI_TXDMA_EN | HCI_RXDMA_EN | TXDMA_EN | RXDMA_EN |
537 PROTOCOL_EN | SCHEDULE_EN | MACTXEN | MACRXEN | ENSEC);
538 rtl_write_word(rtlpriv, REG_CR, value16);
539 return status;
540}
541
542static void _rtl92cu_init_queue_reserved_page(struct ieee80211_hw *hw,
543 bool wmm_enable,
544 u8 out_ep_num,
545 u8 queue_sel)
546{
547 struct rtl_priv *rtlpriv = rtl_priv(hw);
548 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
549 bool isChipN = IS_NORMAL_CHIP(rtlhal->version);
550 u32 outEPNum = (u32)out_ep_num;
551 u32 numHQ = 0;
552 u32 numLQ = 0;
553 u32 numNQ = 0;
554 u32 numPubQ;
555 u32 value32;
556 u8 value8;
557 u32 txQPageNum, txQPageUnit, txQRemainPage;
558
559 if (!wmm_enable) {
560 numPubQ = (isChipN) ? CHIP_B_PAGE_NUM_PUBQ :
561 CHIP_A_PAGE_NUM_PUBQ;
562 txQPageNum = TX_TOTAL_PAGE_NUMBER - numPubQ;
563
564 txQPageUnit = txQPageNum/outEPNum;
565 txQRemainPage = txQPageNum % outEPNum;
566 if (queue_sel & TX_SELE_HQ)
567 numHQ = txQPageUnit;
568 if (queue_sel & TX_SELE_LQ)
569 numLQ = txQPageUnit;
570 /* HIGH priority queue always present in the configuration of
571 * 2 out-ep. Remainder pages have assigned to High queue */
572 if ((outEPNum > 1) && (txQRemainPage))
573 numHQ += txQRemainPage;
574 /* NOTE: This step done before writting REG_RQPN. */
575 if (isChipN) {
576 if (queue_sel & TX_SELE_NQ)
577 numNQ = txQPageUnit;
578 value8 = (u8)_NPQ(numNQ);
579 rtl_write_byte(rtlpriv, REG_RQPN_NPQ, value8);
580 }
581 } else {
582 /* for WMM ,number of out-ep must more than or equal to 2! */
583 numPubQ = isChipN ? WMM_CHIP_B_PAGE_NUM_PUBQ :
584 WMM_CHIP_A_PAGE_NUM_PUBQ;
585 if (queue_sel & TX_SELE_HQ) {
586 numHQ = isChipN ? WMM_CHIP_B_PAGE_NUM_HPQ :
587 WMM_CHIP_A_PAGE_NUM_HPQ;
588 }
589 if (queue_sel & TX_SELE_LQ) {
590 numLQ = isChipN ? WMM_CHIP_B_PAGE_NUM_LPQ :
591 WMM_CHIP_A_PAGE_NUM_LPQ;
592 }
593 /* NOTE: This step done before writting REG_RQPN. */
594 if (isChipN) {
595 if (queue_sel & TX_SELE_NQ)
596 numNQ = WMM_CHIP_B_PAGE_NUM_NPQ;
597 value8 = (u8)_NPQ(numNQ);
598 rtl_write_byte(rtlpriv, REG_RQPN_NPQ, value8);
599 }
600 }
601 /* TX DMA */
602 value32 = _HPQ(numHQ) | _LPQ(numLQ) | _PUBQ(numPubQ) | LD_RQPN;
603 rtl_write_dword(rtlpriv, REG_RQPN, value32);
604}
605
606static void _rtl92c_init_trx_buffer(struct ieee80211_hw *hw, bool wmm_enable)
607{
608 struct rtl_priv *rtlpriv = rtl_priv(hw);
609 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
610 u8 txpktbuf_bndy;
611 u8 value8;
612
613 if (!wmm_enable)
614 txpktbuf_bndy = TX_PAGE_BOUNDARY;
615 else /* for WMM */
616 txpktbuf_bndy = (IS_NORMAL_CHIP(rtlhal->version))
617 ? WMM_CHIP_B_TX_PAGE_BOUNDARY
618 : WMM_CHIP_A_TX_PAGE_BOUNDARY;
619 rtl_write_byte(rtlpriv, REG_TXPKTBUF_BCNQ_BDNY, txpktbuf_bndy);
620 rtl_write_byte(rtlpriv, REG_TXPKTBUF_MGQ_BDNY, txpktbuf_bndy);
621 rtl_write_byte(rtlpriv, REG_TXPKTBUF_WMAC_LBK_BF_HD, txpktbuf_bndy);
622 rtl_write_byte(rtlpriv, REG_TRXFF_BNDY, txpktbuf_bndy);
623 rtl_write_byte(rtlpriv, REG_TDECTRL+1, txpktbuf_bndy);
624 rtl_write_word(rtlpriv, (REG_TRXFF_BNDY + 2), 0x27FF);
625 value8 = _PSRX(RX_PAGE_SIZE_REG_VALUE) | _PSTX(PBP_128);
626 rtl_write_byte(rtlpriv, REG_PBP, value8);
627}
628
629static void _rtl92c_init_chipN_reg_priority(struct ieee80211_hw *hw, u16 beQ,
630 u16 bkQ, u16 viQ, u16 voQ,
631 u16 mgtQ, u16 hiQ)
632{
633 struct rtl_priv *rtlpriv = rtl_priv(hw);
634 u16 value16 = (rtl_read_word(rtlpriv, REG_TRXDMA_CTRL) & 0x7);
635
636 value16 |= _TXDMA_BEQ_MAP(beQ) | _TXDMA_BKQ_MAP(bkQ) |
637 _TXDMA_VIQ_MAP(viQ) | _TXDMA_VOQ_MAP(voQ) |
638 _TXDMA_MGQ_MAP(mgtQ) | _TXDMA_HIQ_MAP(hiQ);
639 rtl_write_word(rtlpriv, REG_TRXDMA_CTRL, value16);
640}
641
642static void _rtl92cu_init_chipN_one_out_ep_priority(struct ieee80211_hw *hw,
643 bool wmm_enable,
644 u8 queue_sel)
645{
646 u16 uninitialized_var(value);
647
648 switch (queue_sel) {
649 case TX_SELE_HQ:
650 value = QUEUE_HIGH;
651 break;
652 case TX_SELE_LQ:
653 value = QUEUE_LOW;
654 break;
655 case TX_SELE_NQ:
656 value = QUEUE_NORMAL;
657 break;
658 default:
659 WARN_ON(1); /* Shall not reach here! */
660 break;
661 }
662 _rtl92c_init_chipN_reg_priority(hw, value, value, value, value,
663 value, value);
292b1192 664 pr_info("Tx queue select: 0x%02x\n", queue_sel);
dc0313f4
G		 665}
666
667static void _rtl92cu_init_chipN_two_out_ep_priority(struct ieee80211_hw *hw,
668 bool wmm_enable,
669 u8 queue_sel)
670{
671 u16 beQ, bkQ, viQ, voQ, mgtQ, hiQ;
672 u16 uninitialized_var(valueHi);
673 u16 uninitialized_var(valueLow);
674
675 switch (queue_sel) {
676 case (TX_SELE_HQ | TX_SELE_LQ):
677 valueHi = QUEUE_HIGH;
678 valueLow = QUEUE_LOW;
679 break;
680 case (TX_SELE_NQ | TX_SELE_LQ):
681 valueHi = QUEUE_NORMAL;
682 valueLow = QUEUE_LOW;
683 break;
684 case (TX_SELE_HQ | TX_SELE_NQ):
685 valueHi = QUEUE_HIGH;
686 valueLow = QUEUE_NORMAL;
687 break;
688 default:
689 WARN_ON(1);
690 break;
691 }
692 if (!wmm_enable) {
693 beQ = valueLow;
694 bkQ = valueLow;
695 viQ = valueHi;
696 voQ = valueHi;
697 mgtQ = valueHi;
698 hiQ = valueHi;
699 } else {/* for WMM ,CONFIG_OUT_EP_WIFI_MODE */
700 beQ = valueHi;
701 bkQ = valueLow;
702 viQ = valueLow;
703 voQ = valueHi;
704 mgtQ = valueHi;
705 hiQ = valueHi;
706 }
707 _rtl92c_init_chipN_reg_priority(hw, beQ, bkQ, viQ, voQ, mgtQ, hiQ);
292b1192 708 pr_info("Tx queue select: 0x%02x\n", queue_sel);
dc0313f4
G		 709}
710
711static void _rtl92cu_init_chipN_three_out_ep_priority(struct ieee80211_hw *hw,
712 bool wmm_enable,
713 u8 queue_sel)
714{
715 u16 beQ, bkQ, viQ, voQ, mgtQ, hiQ;
716 struct rtl_priv *rtlpriv = rtl_priv(hw);
717
718 if (!wmm_enable) { /* typical setting */
719 beQ = QUEUE_LOW;
720 bkQ = QUEUE_LOW;
721 viQ = QUEUE_NORMAL;
722 voQ = QUEUE_HIGH;
723 mgtQ = QUEUE_HIGH;
724 hiQ = QUEUE_HIGH;
725 } else { /* for WMM */
726 beQ = QUEUE_LOW;
727 bkQ = QUEUE_NORMAL;
728 viQ = QUEUE_NORMAL;
729 voQ = QUEUE_HIGH;
730 mgtQ = QUEUE_HIGH;
731 hiQ = QUEUE_HIGH;
732 }
733 _rtl92c_init_chipN_reg_priority(hw, beQ, bkQ, viQ, voQ, mgtQ, hiQ);
f30d7507
JP		 734 RT_TRACE(rtlpriv, COMP_INIT, DBG_EMERG, "Tx queue select :0x%02x..\n",
735 queue_sel);
dc0313f4
G		 736}
737
738static void _rtl92cu_init_chipN_queue_priority(struct ieee80211_hw *hw,
739 bool wmm_enable,
740 u8 out_ep_num,
741 u8 queue_sel)
742{
743 switch (out_ep_num) {
744 case 1:
745 _rtl92cu_init_chipN_one_out_ep_priority(hw, wmm_enable,
746 queue_sel);
747 break;
748 case 2:
749 _rtl92cu_init_chipN_two_out_ep_priority(hw, wmm_enable,
750 queue_sel);
751 break;
752 case 3:
753 _rtl92cu_init_chipN_three_out_ep_priority(hw, wmm_enable,
754 queue_sel);
755 break;
756 default:
757 WARN_ON(1); /* Shall not reach here! */
758 break;
759 }
760}
761
762static void _rtl92cu_init_chipT_queue_priority(struct ieee80211_hw *hw,
763 bool wmm_enable,
764 u8 out_ep_num,
765 u8 queue_sel)
766{
9f219bd2 767 u8 hq_sele = 0;
dc0313f4
G		 768 struct rtl_priv *rtlpriv = rtl_priv(hw);
769
770 switch (out_ep_num) {
771 case 2: /* (TX_SELE_HQ|TX_SELE_LQ) */
772 if (!wmm_enable) /* typical setting */
773 hq_sele = HQSEL_VOQ | HQSEL_VIQ | HQSEL_MGTQ |
774 HQSEL_HIQ;
775 else /* for WMM */
776 hq_sele = HQSEL_VOQ | HQSEL_BEQ | HQSEL_MGTQ |
777 HQSEL_HIQ;
778 break;
779 case 1:
780 if (TX_SELE_LQ == queue_sel) {
781 /* map all endpoint to Low queue */
782 hq_sele = 0;
783 } else if (TX_SELE_HQ == queue_sel) {
784 /* map all endpoint to High queue */
785 hq_sele = HQSEL_VOQ | HQSEL_VIQ | HQSEL_BEQ |
786 HQSEL_BKQ | HQSEL_MGTQ | HQSEL_HIQ;
787 }
788 break;
789 default:
790 WARN_ON(1); /* Shall not reach here! */
791 break;
792 }
793 rtl_write_byte(rtlpriv, (REG_TRXDMA_CTRL+1), hq_sele);
f30d7507
JP		 794 RT_TRACE(rtlpriv, COMP_INIT, DBG_EMERG, "Tx queue select :0x%02x..\n",
795 hq_sele);
dc0313f4
G		 796}
797
798static void _rtl92cu_init_queue_priority(struct ieee80211_hw *hw,
799 bool wmm_enable,
800 u8 out_ep_num,
801 u8 queue_sel)
802{
803 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
804 if (IS_NORMAL_CHIP(rtlhal->version))
805 _rtl92cu_init_chipN_queue_priority(hw, wmm_enable, out_ep_num,
806 queue_sel);
807 else
808 _rtl92cu_init_chipT_queue_priority(hw, wmm_enable, out_ep_num,
809 queue_sel);
810}
811
812static void _rtl92cu_init_usb_aggregation(struct ieee80211_hw *hw)
813{
814}
815
816static void _rtl92cu_init_wmac_setting(struct ieee80211_hw *hw)
817{
818 u16 value16;
819
820 struct rtl_priv *rtlpriv = rtl_priv(hw);
821 struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
822
76c34f91 823 mac->rx_conf = (RCR_APM | RCR_AM | RCR_ADF | RCR_AB | RCR_APPFCS |
dc0313f4
G		 824 RCR_APP_ICV | RCR_AMF | RCR_HTC_LOC_CTRL |
825 RCR_APP_MIC | RCR_APP_PHYSTS | RCR_ACRC32);
826 rtl_write_dword(rtlpriv, REG_RCR, mac->rx_conf);
827 /* Accept all multicast address */
828 rtl_write_dword(rtlpriv, REG_MAR, 0xFFFFFFFF);
829 rtl_write_dword(rtlpriv, REG_MAR + 4, 0xFFFFFFFF);
830 /* Accept all management frames */
831 value16 = 0xFFFF;
832 rtl92c_set_mgt_filter(hw, value16);
833 /* Reject all control frame - default value is 0 */
834 rtl92c_set_ctrl_filter(hw, 0x0);
835 /* Accept all data frames */
836 value16 = 0xFFFF;
837 rtl92c_set_data_filter(hw, value16);
838}
839
840static int _rtl92cu_init_mac(struct ieee80211_hw *hw)
841{
842 struct rtl_priv *rtlpriv = rtl_priv(hw);
843 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
844 struct rtl_usb_priv *usb_priv = rtl_usbpriv(hw);
845 struct rtl_usb *rtlusb = rtl_usbdev(usb_priv);
846 int err = 0;
847 u32 boundary = 0;
848 u8 wmm_enable = false; /* TODO */
849 u8 out_ep_nums = rtlusb->out_ep_nums;
850 u8 queue_sel = rtlusb->out_queue_sel;
851 err = _rtl92cu_init_power_on(hw);
852
853 if (err) {
854 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
f30d7507 855 "Failed to init power on!\n");
dc0313f4
G		 856 return err;
857 }
858 if (!wmm_enable) {
859 boundary = TX_PAGE_BOUNDARY;
860 } else { /* for WMM */
861 boundary = (IS_NORMAL_CHIP(rtlhal->version))
862 ? WMM_CHIP_B_TX_PAGE_BOUNDARY
863 : WMM_CHIP_A_TX_PAGE_BOUNDARY;
864 }
865 if (false == rtl92c_init_llt_table(hw, boundary)) {
866 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
f30d7507 867 "Failed to init LLT Table!\n");
dc0313f4
G		 868 return -EINVAL;
869 }
870 _rtl92cu_init_queue_reserved_page(hw, wmm_enable, out_ep_nums,
871 queue_sel);
872 _rtl92c_init_trx_buffer(hw, wmm_enable);
873 _rtl92cu_init_queue_priority(hw, wmm_enable, out_ep_nums,
874 queue_sel);
875 /* Get Rx PHY status in order to report RSSI and others. */
876 rtl92c_init_driver_info_size(hw, RTL92C_DRIVER_INFO_SIZE);
877 rtl92c_init_interrupt(hw);
878 rtl92c_init_network_type(hw);
879 _rtl92cu_init_wmac_setting(hw);
880 rtl92c_init_adaptive_ctrl(hw);
881 rtl92c_init_edca(hw);
882 rtl92c_init_rate_fallback(hw);
883 rtl92c_init_retry_function(hw);
884 _rtl92cu_init_usb_aggregation(hw);
885 rtlpriv->cfg->ops->set_bw_mode(hw, NL80211_CHAN_HT20);
886 rtl92c_set_min_space(hw, IS_92C_SERIAL(rtlhal->version));
887 rtl92c_init_beacon_parameters(hw, rtlhal->version);
888 rtl92c_init_ampdu_aggregation(hw);
889 rtl92c_init_beacon_max_error(hw, true);
890 return err;
891}
892
893void rtl92cu_enable_hw_security_config(struct ieee80211_hw *hw)
894{
895 struct rtl_priv *rtlpriv = rtl_priv(hw);
896 u8 sec_reg_value = 0x0;
897 struct rtl_hal *rtlhal = rtl_hal(rtlpriv);
898
899 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
f30d7507
JP		 900 "PairwiseEncAlgorithm = %d GroupEncAlgorithm = %d\n",
901 rtlpriv->sec.pairwise_enc_algorithm,
902 rtlpriv->sec.group_enc_algorithm);
dc0313f4
G		 903 if (rtlpriv->cfg->mod_params->sw_crypto || rtlpriv->sec.use_sw_sec) {
904 RT_TRACE(rtlpriv, COMP_SEC, DBG_DMESG,
f30d7507 905 "not open sw encryption\n");
dc0313f4
G		 906 return;
907 }
908 sec_reg_value = SCR_TxEncEnable | SCR_RxDecEnable;
909 if (rtlpriv->sec.use_defaultkey) {
910 sec_reg_value |= SCR_TxUseDK;
911 sec_reg_value |= SCR_RxUseDK;
912 }
913 if (IS_NORMAL_CHIP(rtlhal->version))
914 sec_reg_value |= (SCR_RXBCUSEDK | SCR_TXBCUSEDK);
915 rtl_write_byte(rtlpriv, REG_CR + 1, 0x02);
f30d7507
JP		 916 RT_TRACE(rtlpriv, COMP_SEC, DBG_LOUD, "The SECR-value %x\n",
917 sec_reg_value);
dc0313f4
G		 918 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_WPA_CONFIG, &sec_reg_value);
919}
920
921static void _rtl92cu_hw_configure(struct ieee80211_hw *hw)
922{
923 struct rtl_priv *rtlpriv = rtl_priv(hw);
924 struct rtl_usb *rtlusb = rtl_usbdev(rtl_usbpriv(hw));
925
926 /* To Fix MAC loopback mode fail. */
927 rtl_write_byte(rtlpriv, REG_LDOHCI12_CTRL, 0x0f);
928 rtl_write_byte(rtlpriv, 0x15, 0xe9);
929 /* HW SEQ CTRL */
930 /* set 0x0 to 0xFF by tynli. Default enable HW SEQ NUM. */
931 rtl_write_byte(rtlpriv, REG_HWSEQ_CTRL, 0xFF);
932 /* fixed USB interface interference issue */
933 rtl_write_byte(rtlpriv, 0xfe40, 0xe0);
934 rtl_write_byte(rtlpriv, 0xfe41, 0x8d);
935 rtl_write_byte(rtlpriv, 0xfe42, 0x80);
936 rtlusb->reg_bcn_ctrl_val = 0x18;
937 rtl_write_byte(rtlpriv, REG_BCN_CTRL, (u8)rtlusb->reg_bcn_ctrl_val);
938}
939
940static void _InitPABias(struct ieee80211_hw *hw)
941{
942 struct rtl_priv *rtlpriv = rtl_priv(hw);
943 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
944 u8 pa_setting;
945
946 /* FIXED PA current issue */
947 pa_setting = efuse_read_1byte(hw, 0x1FA);
948 if (!(pa_setting & BIT(0))) {
949 rtl_set_rfreg(hw, RF90_PATH_A, 0x15, 0x0FFFFF, 0x0F406);
950 rtl_set_rfreg(hw, RF90_PATH_A, 0x15, 0x0FFFFF, 0x4F406);
951 rtl_set_rfreg(hw, RF90_PATH_A, 0x15, 0x0FFFFF, 0x8F406);
952 rtl_set_rfreg(hw, RF90_PATH_A, 0x15, 0x0FFFFF, 0xCF406);
953 }
954 if (!(pa_setting & BIT(1)) && IS_NORMAL_CHIP(rtlhal->version) &&
955 IS_92C_SERIAL(rtlhal->version)) {
956 rtl_set_rfreg(hw, RF90_PATH_B, 0x15, 0x0FFFFF, 0x0F406);
957 rtl_set_rfreg(hw, RF90_PATH_B, 0x15, 0x0FFFFF, 0x4F406);
958 rtl_set_rfreg(hw, RF90_PATH_B, 0x15, 0x0FFFFF, 0x8F406);
959 rtl_set_rfreg(hw, RF90_PATH_B, 0x15, 0x0FFFFF, 0xCF406);
960 }
961 if (!(pa_setting & BIT(4))) {
962 pa_setting = rtl_read_byte(rtlpriv, 0x16);
963 pa_setting &= 0x0F;
964 rtl_write_byte(rtlpriv, 0x16, pa_setting | 0x90);
965 }
966}
967
dc0313f4
G		 968static void _update_mac_setting(struct ieee80211_hw *hw)
969{
970 struct rtl_priv *rtlpriv = rtl_priv(hw);
971 struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
972
973 mac->rx_conf = rtl_read_dword(rtlpriv, REG_RCR);
974 mac->rx_mgt_filter = rtl_read_word(rtlpriv, REG_RXFLTMAP0);
975 mac->rx_ctrl_filter = rtl_read_word(rtlpriv, REG_RXFLTMAP1);
976 mac->rx_data_filter = rtl_read_word(rtlpriv, REG_RXFLTMAP2);
977}
978
979int rtl92cu_hw_init(struct ieee80211_hw *hw)
980{
981 struct rtl_priv *rtlpriv = rtl_priv(hw);
982 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
983 struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
984 struct rtl_phy *rtlphy = &(rtlpriv->phy);
985 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
986 int err = 0;
987 static bool iqk_initialized;
a53268be
LF		 988 unsigned long flags;
989
990 /* As this function can take a very long time (up to 350 ms)
991 * and can be called with irqs disabled, reenable the irqs
992 * to let the other devices continue being serviced.
993 *
994 * It is safe doing so since our own interrupts will only be enabled
995 * in a subsequent step.
996 */
997 local_save_flags(flags);
998 local_irq_enable();
dc0313f4
G		 999
1000 rtlhal->hw_type = HARDWARE_TYPE_RTL8192CU;
1001 err = _rtl92cu_init_mac(hw);
1002 if (err) {
f30d7507 1003 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG, "init mac failed!\n");
dc0313f4
G		 1004 return err;
1005 }
1006 err = rtl92c_download_fw(hw);
1007 if (err) {
1008 RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING,
f30d7507 1009 "Failed to download FW. Init HW without FW now..\n");
dc0313f4 1010 err = 1;
a53268be 1011 goto exit;
dc0313f4
G		 1012 }
1013 rtlhal->last_hmeboxnum = 0; /* h2c */
1014 _rtl92cu_phy_param_tab_init(hw);
1472d3a8
LF		 1015 rtl92cu_phy_mac_config(hw);
1016 rtl92cu_phy_bb_config(hw);
dc0313f4
G		 1017 rtlphy->rf_mode = RF_OP_BY_SW_3WIRE;
1018 rtl92c_phy_rf_config(hw);
1019 if (IS_VENDOR_UMC_A_CUT(rtlhal->version) &&
1020 !IS_92C_SERIAL(rtlhal->version)) {
1021 rtl_set_rfreg(hw, RF90_PATH_A, RF_RX_G1, MASKDWORD, 0x30255);
1022 rtl_set_rfreg(hw, RF90_PATH_A, RF_RX_G2, MASKDWORD, 0x50a00);
1023 }
1024 rtlphy->rfreg_chnlval[0] = rtl_get_rfreg(hw, (enum radio_path)0,
1025 RF_CHNLBW, RFREG_OFFSET_MASK);
1026 rtlphy->rfreg_chnlval[1] = rtl_get_rfreg(hw, (enum radio_path)1,
1027 RF_CHNLBW, RFREG_OFFSET_MASK);
1472d3a8 1028 rtl92cu_bb_block_on(hw);
dc0313f4
G		 1029 rtl_cam_reset_all_entry(hw);
1030 rtl92cu_enable_hw_security_config(hw);
1031 ppsc->rfpwr_state = ERFON;
1032 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_ETHER_ADDR, mac->mac_addr);
1033 if (ppsc->rfpwr_state == ERFON) {
1034 rtl92c_phy_set_rfpath_switch(hw, 1);
1035 if (iqk_initialized) {
d3af1ce1 1036 rtl92c_phy_iq_calibrate(hw, true);
dc0313f4
G		 1037 } else {
1038 rtl92c_phy_iq_calibrate(hw, false);
1039 iqk_initialized = true;
1040 }
1041 rtl92c_dm_check_txpower_tracking(hw);
1042 rtl92c_phy_lc_calibrate(hw);
1043 }
1044 _rtl92cu_hw_configure(hw);
1045 _InitPABias(hw);
dc0313f4
G		 1046 _update_mac_setting(hw);
1047 rtl92c_dm_init(hw);
a53268be
LF		 1048exit:
1049 local_irq_restore(flags);
dc0313f4
G		 1050 return err;
1051}
1052
1053static void _DisableRFAFEAndResetBB(struct ieee80211_hw *hw)
1054{
1055 struct rtl_priv *rtlpriv = rtl_priv(hw);
1056/**************************************
1057a. TXPAUSE 0x522[7:0] = 0xFF Pause MAC TX queue
1058b. RF path 0 offset 0x00 = 0x00 disable RF
1059c. APSD_CTRL 0x600[7:0] = 0x40
1060d. SYS_FUNC_EN 0x02[7:0] = 0x16 reset BB state machine
1061e. SYS_FUNC_EN 0x02[7:0] = 0x14 reset BB state machine
1062***************************************/
1063 u8 eRFPath = 0, value8 = 0;
1064 rtl_write_byte(rtlpriv, REG_TXPAUSE, 0xFF);
1065 rtl_set_rfreg(hw, (enum radio_path)eRFPath, 0x0, MASKBYTE0, 0x0);
1066
1067 value8 |= APSDOFF;
1068 rtl_write_byte(rtlpriv, REG_APSD_CTRL, value8); /*0x40*/
1069 value8 = 0;
1070 value8 |= (FEN_USBD | FEN_USBA | FEN_BB_GLB_RSTn);
1071 rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN, value8);/*0x16*/
1072 value8 &= (~FEN_BB_GLB_RSTn);
1073 rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN, value8); /*0x14*/
1074}
1075
1076static void _ResetDigitalProcedure1(struct ieee80211_hw *hw, bool bWithoutHWSM)
1077{
1078 struct rtl_priv *rtlpriv = rtl_priv(hw);
1079 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
1080
1081 if (rtlhal->fw_version <= 0x20) {
1082 /*****************************
1083 f. MCUFWDL 0x80[7:0]=0 reset MCU ready status
1084 g. SYS_FUNC_EN 0x02[10]= 0 reset MCU reg, (8051 reset)
1085 h. SYS_FUNC_EN 0x02[15-12]= 5 reset MAC reg, DCORE
1086 i. SYS_FUNC_EN 0x02[10]= 1 enable MCU reg, (8051 enable)
1087 ******************************/
1088 u16 valu16 = 0;
1089
1090 rtl_write_byte(rtlpriv, REG_MCUFWDL, 0);
1091 valu16 = rtl_read_word(rtlpriv, REG_SYS_FUNC_EN);
1092 rtl_write_word(rtlpriv, REG_SYS_FUNC_EN, (valu16 &
1093 (~FEN_CPUEN))); /* reset MCU ,8051 */
1094 valu16 = rtl_read_word(rtlpriv, REG_SYS_FUNC_EN)&0x0FFF;
1095 rtl_write_word(rtlpriv, REG_SYS_FUNC_EN, (valu16 |
1096 (FEN_HWPDN|FEN_ELDR))); /* reset MAC */
1097 valu16 = rtl_read_word(rtlpriv, REG_SYS_FUNC_EN);
1098 rtl_write_word(rtlpriv, REG_SYS_FUNC_EN, (valu16 |
1099 FEN_CPUEN)); /* enable MCU ,8051 */
1100 } else {
1101 u8 retry_cnts = 0;
1102
1103 /* IF fw in RAM code, do reset */
1104 if (rtl_read_byte(rtlpriv, REG_MCUFWDL) & BIT(1)) {
1105 /* reset MCU ready status */
1106 rtl_write_byte(rtlpriv, REG_MCUFWDL, 0);
b0302aba
LF		 1107 /* 8051 reset by self */
1108 rtl_write_byte(rtlpriv, REG_HMETFR+3, 0x20);
1109 while ((retry_cnts++ < 100) &&
1110 (FEN_CPUEN & rtl_read_word(rtlpriv,
1111 REG_SYS_FUNC_EN))) {
1112 udelay(50);
1113 }
1114 if (retry_cnts >= 100) {
1115 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
1116 "#####=> 8051 reset failed!.........................\n");
1117 /* if 8051 reset fail, reset MAC. */
1118 rtl_write_byte(rtlpriv,
1119 REG_SYS_FUNC_EN + 1,
1120 0x50);
1121 udelay(100);
dc0313f4
G		 1122 }
1123 }
1124 /* Reset MAC and Enable 8051 */
1125 rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN + 1, 0x54);
1126 rtl_write_byte(rtlpriv, REG_MCUFWDL, 0);
1127 }
1128 if (bWithoutHWSM) {
1129 /*****************************
1130 Without HW auto state machine
1131 g.SYS_CLKR 0x08[15:0] = 0x30A3 disable MAC clock
1132 h.AFE_PLL_CTRL 0x28[7:0] = 0x80 disable AFE PLL
1133 i.AFE_XTAL_CTRL 0x24[15:0] = 0x880F gated AFE DIG_CLOCK
1134 j.SYS_ISu_CTRL 0x00[7:0] = 0xF9 isolated digital to PON
1135 ******************************/
1136 rtl_write_word(rtlpriv, REG_SYS_CLKR, 0x70A3);
1137 rtl_write_byte(rtlpriv, REG_AFE_PLL_CTRL, 0x80);
1138 rtl_write_word(rtlpriv, REG_AFE_XTAL_CTRL, 0x880F);
1139 rtl_write_byte(rtlpriv, REG_SYS_ISO_CTRL, 0xF9);
1140 }
1141}
1142
1143static void _ResetDigitalProcedure2(struct ieee80211_hw *hw)
1144{
1145 struct rtl_priv *rtlpriv = rtl_priv(hw);
1146/*****************************
1147k. SYS_FUNC_EN 0x03[7:0] = 0x44 disable ELDR runction
1148l. SYS_CLKR 0x08[15:0] = 0x3083 disable ELDR clock
1149m. SYS_ISO_CTRL 0x01[7:0] = 0x83 isolated ELDR to PON
1150******************************/
1151 rtl_write_word(rtlpriv, REG_SYS_CLKR, 0x70A3);
1152 rtl_write_byte(rtlpriv, REG_SYS_ISO_CTRL+1, 0x82);
1153}
1154
1155static void _DisableGPIO(struct ieee80211_hw *hw)
1156{
1157 struct rtl_priv *rtlpriv = rtl_priv(hw);
1158/***************************************
1159j. GPIO_PIN_CTRL 0x44[31:0]=0x000
1160k. Value = GPIO_PIN_CTRL[7:0]
1161l. GPIO_PIN_CTRL 0x44[31:0] = 0x00FF0000 | (value <<8); write ext PIN level
1162m. GPIO_MUXCFG 0x42 [15:0] = 0x0780
1163n. LEDCFG 0x4C[15:0] = 0x8080
1164***************************************/
1165 u8 value8;
1166 u16 value16;
1167 u32 value32;
1168
1169 /* 1. Disable GPIO[7:0] */
1170 rtl_write_word(rtlpriv, REG_GPIO_PIN_CTRL+2, 0x0000);
1171 value32 = rtl_read_dword(rtlpriv, REG_GPIO_PIN_CTRL) & 0xFFFF00FF;
1172 value8 = (u8) (value32&0x000000FF);
1173 value32 |= ((value8<<8) | 0x00FF0000);
1174 rtl_write_dword(rtlpriv, REG_GPIO_PIN_CTRL, value32);
1175 /* 2. Disable GPIO[10:8] */
1176 rtl_write_byte(rtlpriv, REG_GPIO_MUXCFG+3, 0x00);
1177 value16 = rtl_read_word(rtlpriv, REG_GPIO_MUXCFG+2) & 0xFF0F;
1178 value8 = (u8) (value16&0x000F);
1179 value16 |= ((value8<<4) | 0x0780);
1180 rtl_write_word(rtlpriv, REG_GPIO_PIN_CTRL+2, value16);
1181 /* 3. Disable LED0 & 1 */
1182 rtl_write_word(rtlpriv, REG_LEDCFG0, 0x8080);
1183}
1184
1185static void _DisableAnalog(struct ieee80211_hw *hw, bool bWithoutHWSM)
1186{
1187 struct rtl_priv *rtlpriv = rtl_priv(hw);
1188 u16 value16 = 0;
1189 u8 value8 = 0;
1190
1191 if (bWithoutHWSM) {
1192 /*****************************
1193 n. LDOA15_CTRL 0x20[7:0] = 0x04 disable A15 power
1194 o. LDOV12D_CTRL 0x21[7:0] = 0x54 disable digital core power
1195 r. When driver call disable, the ASIC will turn off remaining
1196 clock automatically
1197 ******************************/
1198 rtl_write_byte(rtlpriv, REG_LDOA15_CTRL, 0x04);
1199 value8 = rtl_read_byte(rtlpriv, REG_LDOV12D_CTRL);
1200 value8 &= (~LDV12_EN);
1201 rtl_write_byte(rtlpriv, REG_LDOV12D_CTRL, value8);
1202 }
1203
1204/*****************************
1205h. SPS0_CTRL 0x11[7:0] = 0x23 enter PFM mode
1206i. APS_FSMCO 0x04[15:0] = 0x4802 set USB suspend
1207******************************/
1208 rtl_write_byte(rtlpriv, REG_SPS0_CTRL, 0x23);
1209 value16 |= (APDM_HOST | AFSM_HSUS | PFM_ALDN);
1210 rtl_write_word(rtlpriv, REG_APS_FSMCO, (u16)value16);
1211 rtl_write_byte(rtlpriv, REG_RSV_CTRL, 0x0E);
1212}
1213
1214static void _CardDisableHWSM(struct ieee80211_hw *hw)
1215{
1216 /* ==== RF Off Sequence ==== */
1217 _DisableRFAFEAndResetBB(hw);
1218 /* ==== Reset digital sequence ====== */
1219 _ResetDigitalProcedure1(hw, false);
1220 /* ==== Pull GPIO PIN to balance level and LED control ====== */
1221 _DisableGPIO(hw);
1222 /* ==== Disable analog sequence === */
1223 _DisableAnalog(hw, false);
1224}
1225
1226static void _CardDisableWithoutHWSM(struct ieee80211_hw *hw)
1227{
1228 /*==== RF Off Sequence ==== */
1229 _DisableRFAFEAndResetBB(hw);
1230 /* ==== Reset digital sequence ====== */
1231 _ResetDigitalProcedure1(hw, true);
1232 /* ==== Pull GPIO PIN to balance level and LED control ====== */
1233 _DisableGPIO(hw);
1234 /* ==== Reset digital sequence ====== */
1235 _ResetDigitalProcedure2(hw);
1236 /* ==== Disable analog sequence === */
1237 _DisableAnalog(hw, true);
1238}
1239
1240static void _rtl92cu_set_bcn_ctrl_reg(struct ieee80211_hw *hw,
1241 u8 set_bits, u8 clear_bits)
1242{
1243 struct rtl_priv *rtlpriv = rtl_priv(hw);
1244 struct rtl_usb *rtlusb = rtl_usbdev(rtl_usbpriv(hw));
1245
1246 rtlusb->reg_bcn_ctrl_val |= set_bits;
1247 rtlusb->reg_bcn_ctrl_val &= ~clear_bits;
1248 rtl_write_byte(rtlpriv, REG_BCN_CTRL, (u8) rtlusb->reg_bcn_ctrl_val);
1249}
1250
1251static void _rtl92cu_stop_tx_beacon(struct ieee80211_hw *hw)
1252{
1253 struct rtl_priv *rtlpriv = rtl_priv(hw);
1254 struct rtl_hal *rtlhal = rtl_hal(rtlpriv);
1255 u8 tmp1byte = 0;
1256 if (IS_NORMAL_CHIP(rtlhal->version)) {
1257 tmp1byte = rtl_read_byte(rtlpriv, REG_FWHW_TXQ_CTRL + 2);
1258 rtl_write_byte(rtlpriv, REG_FWHW_TXQ_CTRL + 2,
1259 tmp1byte & (~BIT(6)));
1260 rtl_write_byte(rtlpriv, REG_TBTT_PROHIBIT + 1, 0x64);
1261 tmp1byte = rtl_read_byte(rtlpriv, REG_TBTT_PROHIBIT + 2);
1262 tmp1byte &= ~(BIT(0));
1263 rtl_write_byte(rtlpriv, REG_TBTT_PROHIBIT + 2, tmp1byte);
1264 } else {
1265 rtl_write_byte(rtlpriv, REG_TXPAUSE,
1266 rtl_read_byte(rtlpriv, REG_TXPAUSE) | BIT(6));
1267 }
1268}
1269
1270static void _rtl92cu_resume_tx_beacon(struct ieee80211_hw *hw)
1271{
1272 struct rtl_priv *rtlpriv = rtl_priv(hw);
1273 struct rtl_hal *rtlhal = rtl_hal(rtlpriv);
1274 u8 tmp1byte = 0;
1275
1276 if (IS_NORMAL_CHIP(rtlhal->version)) {
1277 tmp1byte = rtl_read_byte(rtlpriv, REG_FWHW_TXQ_CTRL + 2);
1278 rtl_write_byte(rtlpriv, REG_FWHW_TXQ_CTRL + 2,
1279 tmp1byte | BIT(6));
1280 rtl_write_byte(rtlpriv, REG_TBTT_PROHIBIT + 1, 0xff);
1281 tmp1byte = rtl_read_byte(rtlpriv, REG_TBTT_PROHIBIT + 2);
1282 tmp1byte |= BIT(0);
1283 rtl_write_byte(rtlpriv, REG_TBTT_PROHIBIT + 2, tmp1byte);
1284 } else {
1285 rtl_write_byte(rtlpriv, REG_TXPAUSE,
1286 rtl_read_byte(rtlpriv, REG_TXPAUSE) & (~BIT(6)));
1287 }
1288}
1289
1290static void _rtl92cu_enable_bcn_sub_func(struct ieee80211_hw *hw)
1291{
1292 struct rtl_priv *rtlpriv = rtl_priv(hw);
1293 struct rtl_hal *rtlhal = rtl_hal(rtlpriv);
1294
1295 if (IS_NORMAL_CHIP(rtlhal->version))
1296 _rtl92cu_set_bcn_ctrl_reg(hw, 0, BIT(1));
1297 else
1298 _rtl92cu_set_bcn_ctrl_reg(hw, 0, BIT(4));
1299}
1300
1301static void _rtl92cu_disable_bcn_sub_func(struct ieee80211_hw *hw)
1302{
1303 struct rtl_priv *rtlpriv = rtl_priv(hw);
1304 struct rtl_hal *rtlhal = rtl_hal(rtlpriv);
1305
1306 if (IS_NORMAL_CHIP(rtlhal->version))
1307 _rtl92cu_set_bcn_ctrl_reg(hw, BIT(1), 0);
1308 else
1309 _rtl92cu_set_bcn_ctrl_reg(hw, BIT(4), 0);
1310}
1311
1312static int _rtl92cu_set_media_status(struct ieee80211_hw *hw,
1313 enum nl80211_iftype type)
1314{
1315 struct rtl_priv *rtlpriv = rtl_priv(hw);
1316 u8 bt_msr = rtl_read_byte(rtlpriv, MSR);
1317 enum led_ctl_mode ledaction = LED_CTL_NO_LINK;
1318
1319 bt_msr &= 0xfc;
1320 rtl_write_byte(rtlpriv, REG_BCN_MAX_ERR, 0xFF);
1321 if (type == NL80211_IFTYPE_UNSPECIFIED || type ==
1322 NL80211_IFTYPE_STATION) {
1323 _rtl92cu_stop_tx_beacon(hw);
1324 _rtl92cu_enable_bcn_sub_func(hw);
1325 } else if (type == NL80211_IFTYPE_ADHOC || type == NL80211_IFTYPE_AP) {
1326 _rtl92cu_resume_tx_beacon(hw);
1327 _rtl92cu_disable_bcn_sub_func(hw);
1328 } else {
f30d7507
JP		 1329 RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING,
1330 "Set HW_VAR_MEDIA_STATUS:No such media status(%x)\n",
1331 type);
dc0313f4
G		 1332 }
1333 switch (type) {
1334 case NL80211_IFTYPE_UNSPECIFIED:
1335 bt_msr |= MSR_NOLINK;
1336 ledaction = LED_CTL_LINK;
1337 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
f30d7507 1338 "Set Network type to NO LINK!\n");
dc0313f4
G		 1339 break;
1340 case NL80211_IFTYPE_ADHOC:
1341 bt_msr |= MSR_ADHOC;
1342 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
f30d7507 1343 "Set Network type to Ad Hoc!\n");
dc0313f4
G		 1344 break;
1345 case NL80211_IFTYPE_STATION:
1346 bt_msr |= MSR_INFRA;
1347 ledaction = LED_CTL_LINK;
1348 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
f30d7507 1349 "Set Network type to STA!\n");
dc0313f4
G		 1350 break;
1351 case NL80211_IFTYPE_AP:
1352 bt_msr |= MSR_AP;
1353 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
f30d7507 1354 "Set Network type to AP!\n");
dc0313f4
G		 1355 break;
1356 default:
1357 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
f30d7507 1358 "Network type %d not supported!\n", type);
dc0313f4
G		 1359 goto error_out;
1360 }
1361 rtl_write_byte(rtlpriv, (MSR), bt_msr);
1362 rtlpriv->cfg->ops->led_control(hw, ledaction);
1363 if ((bt_msr & 0xfc) == MSR_AP)
1364 rtl_write_byte(rtlpriv, REG_BCNTCFG + 1, 0x00);
1365 else
1366 rtl_write_byte(rtlpriv, REG_BCNTCFG + 1, 0x66);
1367 return 0;
1368error_out:
1369 return 1;
1370}
1371
1372void rtl92cu_card_disable(struct ieee80211_hw *hw)
1373{
1374 struct rtl_priv *rtlpriv = rtl_priv(hw);
1375 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
1376 struct rtl_usb *rtlusb = rtl_usbdev(rtl_usbpriv(hw));
1377 struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
1378 enum nl80211_iftype opmode;
1379
1380 mac->link_state = MAC80211_NOLINK;
1381 opmode = NL80211_IFTYPE_UNSPECIFIED;
1382 _rtl92cu_set_media_status(hw, opmode);
1383 rtlpriv->cfg->ops->led_control(hw, LED_CTL_POWER_OFF);
1384 RT_SET_PS_LEVEL(ppsc, RT_RF_OFF_LEVL_HALT_NIC);
1385 if (rtlusb->disableHWSM)
1386 _CardDisableHWSM(hw);
1387 else
1388 _CardDisableWithoutHWSM(hw);
1389}
1390
1391void rtl92cu_set_check_bssid(struct ieee80211_hw *hw, bool check_bssid)
dc0313f4
G		 1392{
1393 struct rtl_priv *rtlpriv = rtl_priv(hw);
dc0313f4 1394 struct rtl_hal *rtlhal = rtl_hal(rtlpriv);
e51048cd 1395 u32 reg_rcr;
dc0313f4 1396
9437a248
LF		 1397 if (rtlpriv->psc.rfpwr_state != ERFON)
1398 return;
1399
e51048cd
PW		 1400 rtlpriv->cfg->ops->get_hw_reg(hw, HW_VAR_RCR, (u8 *)(&reg_rcr));
1401
9437a248
LF		 1402 if (check_bssid) {
1403 u8 tmp;
dc0313f4 1404 if (IS_NORMAL_CHIP(rtlhal->version)) {
9437a248
LF		 1405 reg_rcr |= (RCR_CBSSID_DATA | RCR_CBSSID_BCN);
1406 tmp = BIT(4);
dc0313f4 1407 } else {
9437a248
LF		 1408 reg_rcr |= RCR_CBSSID;
1409 tmp = BIT(4) | BIT(5);
dc0313f4 1410 }
9437a248
LF		 1411 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_RCR,
1412 (u8 *) (&reg_rcr));
1413 _rtl92cu_set_bcn_ctrl_reg(hw, 0, tmp);
1414 } else {
1415 u8 tmp;
dc0313f4 1416 if (IS_NORMAL_CHIP(rtlhal->version)) {
9437a248
LF		 1417 reg_rcr &= ~(RCR_CBSSID_DATA | RCR_CBSSID_BCN);
1418 tmp = BIT(4);
dc0313f4 1419 } else {
9437a248
LF		 1420 reg_rcr &= ~RCR_CBSSID;
1421 tmp = BIT(4) | BIT(5);
dc0313f4 1422 }
9437a248
LF		 1423 reg_rcr &= (~(RCR_CBSSID_DATA | RCR_CBSSID_BCN));
1424 rtlpriv->cfg->ops->set_hw_reg(hw,
1425 HW_VAR_RCR, (u8 *) (&reg_rcr));
1426 _rtl92cu_set_bcn_ctrl_reg(hw, tmp, 0);
dc0313f4
G		 1427 }
1428}
1429
9437a248
LF		 1430/*========================================================================== */
1431
dc0313f4
G		 1432int rtl92cu_set_network_type(struct ieee80211_hw *hw, enum nl80211_iftype type)
1433{
9437a248
LF		 1434 struct rtl_priv *rtlpriv = rtl_priv(hw);
1435
dc0313f4
G		 1436 if (_rtl92cu_set_media_status(hw, type))
1437 return -EOPNOTSUPP;
9437a248
LF		 1438
1439 if (rtlpriv->mac80211.link_state == MAC80211_LINKED) {
1440 if (type != NL80211_IFTYPE_AP)
1441 rtl92cu_set_check_bssid(hw, true);
1442 } else {
1443 rtl92cu_set_check_bssid(hw, false);
1444 }
1445
dc0313f4
G		 1446 return 0;
1447}
1448
1449static void _InitBeaconParameters(struct ieee80211_hw *hw)
1450{
1451 struct rtl_priv *rtlpriv = rtl_priv(hw);
1452 struct rtl_hal *rtlhal = rtl_hal(rtlpriv);
1453
1454 rtl_write_word(rtlpriv, REG_BCN_CTRL, 0x1010);
1455
1456 /* TODO: Remove these magic number */
1457 rtl_write_word(rtlpriv, REG_TBTT_PROHIBIT, 0x6404);
1458 rtl_write_byte(rtlpriv, REG_DRVERLYINT, DRIVER_EARLY_INT_TIME);
1459 rtl_write_byte(rtlpriv, REG_BCNDMATIM, BCN_DMA_ATIME_INT_TIME);
1460 /* Change beacon AIFS to the largest number
1461 * beacause test chip does not contension before sending beacon. */
1462 if (IS_NORMAL_CHIP(rtlhal->version))
1463 rtl_write_word(rtlpriv, REG_BCNTCFG, 0x660F);
1464 else
1465 rtl_write_word(rtlpriv, REG_BCNTCFG, 0x66FF);
1466}
1467
1468static void _beacon_function_enable(struct ieee80211_hw *hw, bool Enable,
1469 bool Linked)
1470{
1471 struct rtl_priv *rtlpriv = rtl_priv(hw);
1472
1473 _rtl92cu_set_bcn_ctrl_reg(hw, (BIT(4) | BIT(3) | BIT(1)), 0x00);
1474 rtl_write_byte(rtlpriv, REG_RD_CTRL+1, 0x6F);
1475}
1476
1477void rtl92cu_set_beacon_related_registers(struct ieee80211_hw *hw)
1478{
1479
1480 struct rtl_priv *rtlpriv = rtl_priv(hw);
1481 struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
1482 u16 bcn_interval, atim_window;
1483 u32 value32;
1484
1485 bcn_interval = mac->beacon_interval;
1486 atim_window = 2; /*FIX MERGE */
1487 rtl_write_word(rtlpriv, REG_ATIMWND, atim_window);
1488 rtl_write_word(rtlpriv, REG_BCN_INTERVAL, bcn_interval);
1489 _InitBeaconParameters(hw);
1490 rtl_write_byte(rtlpriv, REG_SLOT, 0x09);
1491 /*
1492 * Force beacon frame transmission even after receiving beacon frame
1493 * from other ad hoc STA
1494 *
1495 *
1496 * Reset TSF Timer to zero, added by Roger. 2008.06.24
1497 */
1498 value32 = rtl_read_dword(rtlpriv, REG_TCR);
1499 value32 &= ~TSFRST;
1500 rtl_write_dword(rtlpriv, REG_TCR, value32);
1501 value32 |= TSFRST;
1502 rtl_write_dword(rtlpriv, REG_TCR, value32);
1503 RT_TRACE(rtlpriv, COMP_INIT|COMP_BEACON, DBG_LOUD,
f30d7507
JP		 1504 "SetBeaconRelatedRegisters8192CUsb(): Set TCR(%x)\n",
1505 value32);
dc0313f4
G		 1506 /* TODO: Modify later (Find the right parameters)
1507 * NOTE: Fix test chip's bug (about contention windows's randomness) */
1508 if ((mac->opmode == NL80211_IFTYPE_ADHOC) ||
1509 (mac->opmode == NL80211_IFTYPE_AP)) {
1510 rtl_write_byte(rtlpriv, REG_RXTSF_OFFSET_CCK, 0x50);
1511 rtl_write_byte(rtlpriv, REG_RXTSF_OFFSET_OFDM, 0x50);
1512 }
1513 _beacon_function_enable(hw, true, true);
1514}
1515
1516void rtl92cu_set_beacon_interval(struct ieee80211_hw *hw)
1517{
1518 struct rtl_priv *rtlpriv = rtl_priv(hw);
1519 struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
1520 u16 bcn_interval = mac->beacon_interval;
1521
f30d7507
JP		 1522 RT_TRACE(rtlpriv, COMP_BEACON, DBG_DMESG, "beacon_interval:%d\n",
1523 bcn_interval);
dc0313f4
G		 1524 rtl_write_word(rtlpriv, REG_BCN_INTERVAL, bcn_interval);
1525}
1526
1527void rtl92cu_update_interrupt_mask(struct ieee80211_hw *hw,
1528 u32 add_msr, u32 rm_msr)
1529{
1530}
1531
1532void rtl92cu_get_hw_reg(struct ieee80211_hw *hw, u8 variable, u8 *val)
1533{
1534 struct rtl_priv *rtlpriv = rtl_priv(hw);
1535 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
1536 struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
1537
1538 switch (variable) {
1539 case HW_VAR_RCR:
1540 *((u32 *)(val)) = mac->rx_conf;
1541 break;
1542 case HW_VAR_RF_STATE:
1543 *((enum rf_pwrstate *)(val)) = ppsc->rfpwr_state;
1544 break;
1545 case HW_VAR_FWLPS_RF_ON:{
1546 enum rf_pwrstate rfState;
1547 u32 val_rcr;
1548
1549 rtlpriv->cfg->ops->get_hw_reg(hw, HW_VAR_RF_STATE,
1550 (u8 *)(&rfState));
1551 if (rfState == ERFOFF) {
1552 *((bool *) (val)) = true;
1553 } else {
1554 val_rcr = rtl_read_dword(rtlpriv, REG_RCR);
1555 val_rcr &= 0x00070000;
1556 if (val_rcr)
1557 *((bool *) (val)) = false;
1558 else
1559 *((bool *) (val)) = true;
1560 }
1561 break;
1562 }
1563 case HW_VAR_FW_PSMODE_STATUS:
1564 *((bool *) (val)) = ppsc->fw_current_inpsmode;
1565 break;
1566 case HW_VAR_CORRECT_TSF:{
1567 u64 tsf;
1568 u32 *ptsf_low = (u32 *)&tsf;
1569 u32 *ptsf_high = ((u32 *)&tsf) + 1;
1570
1571 *ptsf_high = rtl_read_dword(rtlpriv, (REG_TSFTR + 4));
1572 *ptsf_low = rtl_read_dword(rtlpriv, REG_TSFTR);
1573 *((u64 *)(val)) = tsf;
1574 break;
1575 }
1576 case HW_VAR_MGT_FILTER:
1577 *((u16 *) (val)) = rtl_read_word(rtlpriv, REG_RXFLTMAP0);
1578 break;
1579 case HW_VAR_CTRL_FILTER:
1580 *((u16 *) (val)) = rtl_read_word(rtlpriv, REG_RXFLTMAP1);
1581 break;
1582 case HW_VAR_DATA_FILTER:
1583 *((u16 *) (val)) = rtl_read_word(rtlpriv, REG_RXFLTMAP2);
1584 break;
1585 default:
1586 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
f30d7507 1587 "switch case not processed\n");
dc0313f4
G		 1588 break;
1589 }
1590}
1591
1592void rtl92cu_set_hw_reg(struct ieee80211_hw *hw, u8 variable, u8 *val)
1593{
1594 struct rtl_priv *rtlpriv = rtl_priv(hw);
1595 struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
1596 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
1597 struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
1598 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
1599 struct rtl_usb *rtlusb = rtl_usbdev(rtl_usbpriv(hw));
1600 enum wireless_mode wirelessmode = mac->mode;
1601 u8 idx = 0;
1602
1603 switch (variable) {
1604 case HW_VAR_ETHER_ADDR:{
1605 for (idx = 0; idx < ETH_ALEN; idx++) {
1606 rtl_write_byte(rtlpriv, (REG_MACID + idx),
1607 val[idx]);
1608 }
1609 break;
1610 }
1611 case HW_VAR_BASIC_RATE:{
1612 u16 rate_cfg = ((u16 *) val)[0];
1613 u8 rate_index = 0;
1614
1615 rate_cfg &= 0x15f;
1616 /* TODO */
1617 /* if (mac->current_network.vender == HT_IOT_PEER_CISCO
1618 * && ((rate_cfg & 0x150) == 0)) {
1619 * rate_cfg |= 0x010;
1620 * } */
1621 rate_cfg |= 0x01;
1622 rtl_write_byte(rtlpriv, REG_RRSR, rate_cfg & 0xff);
1623 rtl_write_byte(rtlpriv, REG_RRSR + 1,
1624 (rate_cfg >> 8) & 0xff);
1625 while (rate_cfg > 0x1) {
1626 rate_cfg >>= 1;
1627 rate_index++;
1628 }
1629 rtl_write_byte(rtlpriv, REG_INIRTS_RATE_SEL,
1630 rate_index);
1631 break;
1632 }
1633 case HW_VAR_BSSID:{
1634 for (idx = 0; idx < ETH_ALEN; idx++) {
1635 rtl_write_byte(rtlpriv, (REG_BSSID + idx),
1636 val[idx]);
1637 }
1638 break;
1639 }
1640 case HW_VAR_SIFS:{
1641 rtl_write_byte(rtlpriv, REG_SIFS_CCK + 1, val[0]);
1642 rtl_write_byte(rtlpriv, REG_SIFS_OFDM + 1, val[1]);
1643 rtl_write_byte(rtlpriv, REG_SPEC_SIFS + 1, val[0]);
1644 rtl_write_byte(rtlpriv, REG_MAC_SPEC_SIFS + 1, val[0]);
1645 rtl_write_byte(rtlpriv, REG_R2T_SIFS+1, val[0]);
1646 rtl_write_byte(rtlpriv, REG_T2T_SIFS+1, val[0]);
f30d7507 1647 RT_TRACE(rtlpriv, COMP_MLME, DBG_LOUD, "HW_VAR_SIFS\n");
dc0313f4
G		 1648 break;
1649 }
1650 case HW_VAR_SLOT_TIME:{
1651 u8 e_aci;
1652 u8 QOS_MODE = 1;
1653
1654 rtl_write_byte(rtlpriv, REG_SLOT, val[0]);
1655 RT_TRACE(rtlpriv, COMP_MLME, DBG_LOUD,
f30d7507 1656 "HW_VAR_SLOT_TIME %x\n", val[0]);
dc0313f4
G		 1657 if (QOS_MODE) {
1658 for (e_aci = 0; e_aci < AC_MAX; e_aci++)
1659 rtlpriv->cfg->ops->set_hw_reg(hw,
1660 HW_VAR_AC_PARAM,
2c208890 1661 &e_aci);
dc0313f4
G		 1662 } else {
1663 u8 sifstime = 0;
1664 u8 u1bAIFS;
1665
1666 if (IS_WIRELESS_MODE_A(wirelessmode) ||
1667 IS_WIRELESS_MODE_N_24G(wirelessmode) ||
1668 IS_WIRELESS_MODE_N_5G(wirelessmode))
1669 sifstime = 16;
1670 else
1671 sifstime = 10;
1672 u1bAIFS = sifstime + (2 * val[0]);
1673 rtl_write_byte(rtlpriv, REG_EDCA_VO_PARAM,
1674 u1bAIFS);
1675 rtl_write_byte(rtlpriv, REG_EDCA_VI_PARAM,
1676 u1bAIFS);
1677 rtl_write_byte(rtlpriv, REG_EDCA_BE_PARAM,
1678 u1bAIFS);
1679 rtl_write_byte(rtlpriv, REG_EDCA_BK_PARAM,
1680 u1bAIFS);
1681 }
1682 break;
1683 }
1684 case HW_VAR_ACK_PREAMBLE:{
1685 u8 reg_tmp;
2c208890 1686 u8 short_preamble = (bool)*val;
dc0313f4
G		 1687 reg_tmp = 0;
1688 if (short_preamble)
1689 reg_tmp |= 0x80;
1690 rtl_write_byte(rtlpriv, REG_RRSR + 2, reg_tmp);
1691 break;
1692 }
1693 case HW_VAR_AMPDU_MIN_SPACE:{
1694 u8 min_spacing_to_set;
1695 u8 sec_min_space;
1696
2c208890 1697 min_spacing_to_set = *val;
dc0313f4
G		 1698 if (min_spacing_to_set <= 7) {
1699 switch (rtlpriv->sec.pairwise_enc_algorithm) {
1700 case NO_ENCRYPTION:
1701 case AESCCMP_ENCRYPTION:
1702 sec_min_space = 0;
1703 break;
1704 case WEP40_ENCRYPTION:
1705 case WEP104_ENCRYPTION:
1706 case TKIP_ENCRYPTION:
1707 sec_min_space = 6;
1708 break;
1709 default:
1710 sec_min_space = 7;
1711 break;
1712 }
1713 if (min_spacing_to_set < sec_min_space)
1714 min_spacing_to_set = sec_min_space;
1715 mac->min_space_cfg = ((mac->min_space_cfg &
1716 0xf8) |
1717 min_spacing_to_set);
1718 *val = min_spacing_to_set;
1719 RT_TRACE(rtlpriv, COMP_MLME, DBG_LOUD,
f30d7507
JP		 1720 "Set HW_VAR_AMPDU_MIN_SPACE: %#x\n",
1721 mac->min_space_cfg);
dc0313f4
G		 1722 rtl_write_byte(rtlpriv, REG_AMPDU_MIN_SPACE,
1723 mac->min_space_cfg);
1724 }
1725 break;
1726 }
1727 case HW_VAR_SHORTGI_DENSITY:{
1728 u8 density_to_set;
1729
2c208890 1730 density_to_set = *val;
dc0313f4
G		 1731 density_to_set &= 0x1f;
1732 mac->min_space_cfg &= 0x07;
1733 mac->min_space_cfg |= (density_to_set << 3);
1734 RT_TRACE(rtlpriv, COMP_MLME, DBG_LOUD,
f30d7507
JP		 1735 "Set HW_VAR_SHORTGI_DENSITY: %#x\n",
1736 mac->min_space_cfg);
dc0313f4
G		 1737 rtl_write_byte(rtlpriv, REG_AMPDU_MIN_SPACE,
1738 mac->min_space_cfg);
1739 break;
1740 }
1741 case HW_VAR_AMPDU_FACTOR:{
1742 u8 regtoset_normal[4] = {0x41, 0xa8, 0x72, 0xb9};
1743 u8 factor_toset;
1744 u8 *p_regtoset = NULL;
1745 u8 index = 0;
1746
1747 p_regtoset = regtoset_normal;
2c208890 1748 factor_toset = *val;
dc0313f4
G		 1749 if (factor_toset <= 3) {
1750 factor_toset = (1 << (factor_toset + 2));
1751 if (factor_toset > 0xf)
1752 factor_toset = 0xf;
1753 for (index = 0; index < 4; index++) {
1754 if ((p_regtoset[index] & 0xf0) >
1755 (factor_toset << 4))
1756 p_regtoset[index] =
1757 (p_regtoset[index] & 0x0f)
1758 | (factor_toset << 4);
1759 if ((p_regtoset[index] & 0x0f) >
1760 factor_toset)
1761 p_regtoset[index] =
1762 (p_regtoset[index] & 0xf0)
1763 | (factor_toset);
1764 rtl_write_byte(rtlpriv,
1765 (REG_AGGLEN_LMT + index),
1766 p_regtoset[index]);
1767 }
1768 RT_TRACE(rtlpriv, COMP_MLME, DBG_LOUD,
f30d7507
JP		 1769 "Set HW_VAR_AMPDU_FACTOR: %#x\n",
1770 factor_toset);
dc0313f4
G		 1771 }
1772 break;
1773 }
1774 case HW_VAR_AC_PARAM:{
2c208890 1775 u8 e_aci = *val;
dc0313f4
G		 1776 u32 u4b_ac_param;
1777 u16 cw_min = le16_to_cpu(mac->ac[e_aci].cw_min);
1778 u16 cw_max = le16_to_cpu(mac->ac[e_aci].cw_max);
1779 u16 tx_op = le16_to_cpu(mac->ac[e_aci].tx_op);
1780
1781 u4b_ac_param = (u32) mac->ac[e_aci].aifs;
1782 u4b_ac_param |= (u32) ((cw_min & 0xF) <<
1783 AC_PARAM_ECW_MIN_OFFSET);
1784 u4b_ac_param |= (u32) ((cw_max & 0xF) <<
1785 AC_PARAM_ECW_MAX_OFFSET);
1786 u4b_ac_param |= (u32) tx_op << AC_PARAM_TXOP_OFFSET;
1787 RT_TRACE(rtlpriv, COMP_MLME, DBG_LOUD,
f30d7507
JP		 1788 "queue:%x, ac_param:%x\n",
1789 e_aci, u4b_ac_param);
dc0313f4
G		 1790 switch (e_aci) {
1791 case AC1_BK:
1792 rtl_write_dword(rtlpriv, REG_EDCA_BK_PARAM,
1793 u4b_ac_param);
1794 break;
1795 case AC0_BE:
1796 rtl_write_dword(rtlpriv, REG_EDCA_BE_PARAM,
1797 u4b_ac_param);
1798 break;
1799 case AC2_VI:
1800 rtl_write_dword(rtlpriv, REG_EDCA_VI_PARAM,
1801 u4b_ac_param);
1802 break;
1803 case AC3_VO:
1804 rtl_write_dword(rtlpriv, REG_EDCA_VO_PARAM,
1805 u4b_ac_param);
1806 break;
1807 default:
9d833ed7
JP		 1808 RT_ASSERT(false,
1809 "SetHwReg8185(): invalid aci: %d !\n",
1810 e_aci);
dc0313f4
G		 1811 break;
1812 }
2cddad3c 1813 if (rtlusb->acm_method != EACMWAY2_SW)
dc0313f4 1814 rtlpriv->cfg->ops->set_hw_reg(hw,
2c208890 1815 HW_VAR_ACM_CTRL, &e_aci);
dc0313f4
G		 1816 break;
1817 }
1818 case HW_VAR_ACM_CTRL:{
2c208890 1819 u8 e_aci = *val;
dc0313f4
G		 1820 union aci_aifsn *p_aci_aifsn = (union aci_aifsn *)
1821 (&(mac->ac[0].aifs));
1822 u8 acm = p_aci_aifsn->f.acm;
1823 u8 acm_ctrl = rtl_read_byte(rtlpriv, REG_ACMHWCTRL);
1824
1825 acm_ctrl =
1826 acm_ctrl | ((rtlusb->acm_method == 2) ? 0x0 : 0x1);
1827 if (acm) {
1828 switch (e_aci) {
1829 case AC0_BE:
1830 acm_ctrl |= AcmHw_BeqEn;
1831 break;
1832 case AC2_VI:
1833 acm_ctrl |= AcmHw_ViqEn;
1834 break;
1835 case AC3_VO:
1836 acm_ctrl |= AcmHw_VoqEn;
1837 break;
1838 default:
1839 RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING,
f30d7507
JP		 1840 "HW_VAR_ACM_CTRL acm set failed: eACI is %d\n",
1841 acm);
dc0313f4
G		 1842 break;
1843 }
1844 } else {
1845 switch (e_aci) {
1846 case AC0_BE:
1847 acm_ctrl &= (~AcmHw_BeqEn);
1848 break;
1849 case AC2_VI:
1850 acm_ctrl &= (~AcmHw_ViqEn);
1851 break;
1852 case AC3_VO:
1853 acm_ctrl &= (~AcmHw_BeqEn);
1854 break;
1855 default:
1856 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
f30d7507 1857 "switch case not processed\n");
dc0313f4
G		 1858 break;
1859 }
1860 }
1861 RT_TRACE(rtlpriv, COMP_QOS, DBG_TRACE,
f30d7507
JP		 1862 "SetHwReg8190pci(): [HW_VAR_ACM_CTRL] Write 0x%X\n",
1863 acm_ctrl);
dc0313f4
G		 1864 rtl_write_byte(rtlpriv, REG_ACMHWCTRL, acm_ctrl);
1865 break;
1866 }
1867 case HW_VAR_RCR:{
1868 rtl_write_dword(rtlpriv, REG_RCR, ((u32 *) (val))[0]);
1869 mac->rx_conf = ((u32 *) (val))[0];
1870 RT_TRACE(rtlpriv, COMP_RECV, DBG_DMESG,
f30d7507 1871 "### Set RCR(0x%08x) ###\n", mac->rx_conf);
dc0313f4
G		 1872 break;
1873 }
1874 case HW_VAR_RETRY_LIMIT:{
2c208890 1875 u8 retry_limit = val[0];
dc0313f4
G		 1876
1877 rtl_write_word(rtlpriv, REG_RL,
1878 retry_limit << RETRY_LIMIT_SHORT_SHIFT |
1879 retry_limit << RETRY_LIMIT_LONG_SHIFT);
f30d7507
JP		 1880 RT_TRACE(rtlpriv, COMP_MLME, DBG_DMESG,
1881 "Set HW_VAR_RETRY_LIMIT(0x%08x)\n",
1882 retry_limit);
dc0313f4
G		 1883 break;
1884 }
1885 case HW_VAR_DUAL_TSF_RST:
1886 rtl_write_byte(rtlpriv, REG_DUAL_TSF_RST, (BIT(0) | BIT(1)));
1887 break;
1888 case HW_VAR_EFUSE_BYTES:
1889 rtlefuse->efuse_usedbytes = *((u16 *) val);
1890 break;
1891 case HW_VAR_EFUSE_USAGE:
2c208890 1892 rtlefuse->efuse_usedpercentage = *val;
dc0313f4
G		 1893 break;
1894 case HW_VAR_IO_CMD:
1895 rtl92c_phy_set_io_cmd(hw, (*(enum io_type *)val));
1896 break;
1897 case HW_VAR_WPA_CONFIG:
2c208890 1898 rtl_write_byte(rtlpriv, REG_SECCFG, *val);
dc0313f4
G		 1899 break;
1900 case HW_VAR_SET_RPWM:{
1901 u8 rpwm_val = rtl_read_byte(rtlpriv, REG_USB_HRPWM);
1902
1903 if (rpwm_val & BIT(7))
2c208890 1904 rtl_write_byte(rtlpriv, REG_USB_HRPWM, *val);
dc0313f4
G		 1905 else
1906 rtl_write_byte(rtlpriv, REG_USB_HRPWM,
2c208890 1907 *val | BIT(7));
dc0313f4
G		 1908 break;
1909 }
1910 case HW_VAR_H2C_FW_PWRMODE:{
2c208890 1911 u8 psmode = *val;
dc0313f4
G		 1912
1913 if ((psmode != FW_PS_ACTIVE_MODE) &&
1914 (!IS_92C_SERIAL(rtlhal->version)))
1915 rtl92c_dm_rf_saving(hw, true);
2c208890 1916 rtl92c_set_fw_pwrmode_cmd(hw, (*val));
dc0313f4
G		 1917 break;
1918 }
1919 case HW_VAR_FW_PSMODE_STATUS:
1920 ppsc->fw_current_inpsmode = *((bool *) val);
1921 break;
1922 case HW_VAR_H2C_FW_JOINBSSRPT:{
2c208890 1923 u8 mstatus = *val;
dc0313f4
G		 1924 u8 tmp_reg422;
1925 bool recover = false;
1926
1927 if (mstatus == RT_MEDIA_CONNECT) {
1928 rtlpriv->cfg->ops->set_hw_reg(hw,
1929 HW_VAR_AID, NULL);
1930 rtl_write_byte(rtlpriv, REG_CR + 1, 0x03);
1931 _rtl92cu_set_bcn_ctrl_reg(hw, 0, BIT(3));
1932 _rtl92cu_set_bcn_ctrl_reg(hw, BIT(4), 0);
1933 tmp_reg422 = rtl_read_byte(rtlpriv,
1934 REG_FWHW_TXQ_CTRL + 2);
1935 if (tmp_reg422 & BIT(6))
1936 recover = true;
1937 rtl_write_byte(rtlpriv, REG_FWHW_TXQ_CTRL + 2,
1938 tmp_reg422 & (~BIT(6)));
1939 rtl92c_set_fw_rsvdpagepkt(hw, 0);
1940 _rtl92cu_set_bcn_ctrl_reg(hw, BIT(3), 0);
1941 _rtl92cu_set_bcn_ctrl_reg(hw, 0, BIT(4));
1942 if (recover)
1943 rtl_write_byte(rtlpriv,
1944 REG_FWHW_TXQ_CTRL + 2,
1945 tmp_reg422 | BIT(6));
1946 rtl_write_byte(rtlpriv, REG_CR + 1, 0x02);
1947 }
2c208890 1948 rtl92c_set_fw_joinbss_report_cmd(hw, (*val));
dc0313f4
G		 1949 break;
1950 }
1951 case HW_VAR_AID:{
1952 u16 u2btmp;
1953
1954 u2btmp = rtl_read_word(rtlpriv, REG_BCN_PSR_RPT);
1955 u2btmp &= 0xC000;
1956 rtl_write_word(rtlpriv, REG_BCN_PSR_RPT,
1957 (u2btmp | mac->assoc_id));
1958 break;
1959 }
1960 case HW_VAR_CORRECT_TSF:{
2c208890 1961 u8 btype_ibss = val[0];
dc0313f4 1962
e10542c4 1963 if (btype_ibss)
dc0313f4
G		 1964 _rtl92cu_stop_tx_beacon(hw);
1965 _rtl92cu_set_bcn_ctrl_reg(hw, 0, BIT(3));
1966 rtl_write_dword(rtlpriv, REG_TSFTR, (u32)(mac->tsf &
1967 0xffffffff));
1968 rtl_write_dword(rtlpriv, REG_TSFTR + 4,
1969 (u32)((mac->tsf >> 32) & 0xffffffff));
1970 _rtl92cu_set_bcn_ctrl_reg(hw, BIT(3), 0);
e10542c4 1971 if (btype_ibss)
dc0313f4
G		 1972 _rtl92cu_resume_tx_beacon(hw);
1973 break;
1974 }
1975 case HW_VAR_MGT_FILTER:
1976 rtl_write_word(rtlpriv, REG_RXFLTMAP0, *(u16 *)val);
1977 break;
1978 case HW_VAR_CTRL_FILTER:
1979 rtl_write_word(rtlpriv, REG_RXFLTMAP1, *(u16 *)val);
1980 break;
1981 case HW_VAR_DATA_FILTER:
1982 rtl_write_word(rtlpriv, REG_RXFLTMAP2, *(u16 *)val);
1983 break;
1984 default:
f30d7507
JP		 1985 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
1986 "switch case not processed\n");
dc0313f4
G		 1987 break;
1988 }
1989}
1990
5b8df24e
LF		 1991static void rtl92cu_update_hal_rate_table(struct ieee80211_hw *hw,
1992 struct ieee80211_sta *sta)
dc0313f4
G		 1993{
1994 struct rtl_priv *rtlpriv = rtl_priv(hw);
1995 struct rtl_phy *rtlphy = &(rtlpriv->phy);
1996 struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
5b8df24e
LF		 1997 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
1998 u32 ratr_value;
dc0313f4
G		 1999 u8 ratr_index = 0;
2000 u8 nmode = mac->ht_enable;
5b8df24e
LF		 2001 u8 mimo_ps = IEEE80211_SMPS_OFF;
2002 u16 shortgi_rate;
2003 u32 tmp_ratr_value;
dc0313f4 2004 u8 curtxbw_40mhz = mac->bw_40;
5b8df24e
LF		 2005 u8 curshortgi_40mhz = (sta->ht_cap.cap & IEEE80211_HT_CAP_SGI_40) ?
2006 1 : 0;
2007 u8 curshortgi_20mhz = (sta->ht_cap.cap & IEEE80211_HT_CAP_SGI_20) ?
2008 1 : 0;
dc0313f4
G		 2009 enum wireless_mode wirelessmode = mac->mode;
2010
5b8df24e
LF		 2011 if (rtlhal->current_bandtype == BAND_ON_5G)
2012 ratr_value = sta->supp_rates[1] << 4;
2013 else
2014 ratr_value = sta->supp_rates[0];
2015 if (mac->opmode == NL80211_IFTYPE_ADHOC)
2016 ratr_value = 0xfff;
2017
2018 ratr_value |= (sta->ht_cap.mcs.rx_mask[1] << 20 |
2019 sta->ht_cap.mcs.rx_mask[0] << 12);
dc0313f4
G		 2020 switch (wirelessmode) {
2021 case WIRELESS_MODE_B:
2022 if (ratr_value & 0x0000000c)
2023 ratr_value &= 0x0000000d;
2024 else
2025 ratr_value &= 0x0000000f;
2026 break;
2027 case WIRELESS_MODE_G:
2028 ratr_value &= 0x00000FF5;
2029 break;
2030 case WIRELESS_MODE_N_24G:
2031 case WIRELESS_MODE_N_5G:
2032 nmode = 1;
5b8df24e 2033 if (mimo_ps == IEEE80211_SMPS_STATIC) {
dc0313f4
G		 2034 ratr_value &= 0x0007F005;
2035 } else {
2036 u32 ratr_mask;
2037
2038 if (get_rf_type(rtlphy) == RF_1T2R ||
2039 get_rf_type(rtlphy) == RF_1T1R)
2040 ratr_mask = 0x000ff005;
2041 else
2042 ratr_mask = 0x0f0ff005;
5b8df24e 2043
dc0313f4
G		 2044 ratr_value &= ratr_mask;
2045 }
2046 break;
2047 default:
2048 if (rtlphy->rf_type == RF_1T2R)
2049 ratr_value &= 0x000ff0ff;
2050 else
2051 ratr_value &= 0x0f0ff0ff;
5b8df24e 2052
dc0313f4
G		 2053 break;
2054 }
5b8df24e 2055
dc0313f4 2056 ratr_value &= 0x0FFFFFFF;
5b8df24e
LF		 2057
2058 if (nmode && ((curtxbw_40mhz &&
2059 curshortgi_40mhz) || (!curtxbw_40mhz &&
2060 curshortgi_20mhz))) {
2061
dc0313f4
G		 2062 ratr_value |= 0x10000000;
2063 tmp_ratr_value = (ratr_value >> 12);
5b8df24e 2064
dc0313f4
G		 2065 for (shortgi_rate = 15; shortgi_rate > 0; shortgi_rate--) {
2066 if ((1 << shortgi_rate) & tmp_ratr_value)
2067 break;
2068 }
5b8df24e 2069
dc0313f4 2070 shortgi_rate = (shortgi_rate << 12) | (shortgi_rate << 8) |
5b8df24e 2071 (shortgi_rate << 4) | (shortgi_rate);
dc0313f4 2072 }
5b8df24e 2073
dc0313f4 2074 rtl_write_dword(rtlpriv, REG_ARFR0 + ratr_index * 4, ratr_value);
5b8df24e
LF		 2075
2076 RT_TRACE(rtlpriv, COMP_RATR, DBG_DMESG, "%x\n",
2077 rtl_read_dword(rtlpriv, REG_ARFR0));
dc0313f4
G		 2078}
2079
5b8df24e
LF		 2080static void rtl92cu_update_hal_rate_mask(struct ieee80211_hw *hw,
2081 struct ieee80211_sta *sta,
2082 u8 rssi_level)
dc0313f4
G		 2083{
2084 struct rtl_priv *rtlpriv = rtl_priv(hw);
2085 struct rtl_phy *rtlphy = &(rtlpriv->phy);
2086 struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
5b8df24e
LF		 2087 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
2088 struct rtl_sta_info *sta_entry = NULL;
2089 u32 ratr_bitmap;
2090 u8 ratr_index;
2091 u8 curtxbw_40mhz = (sta->bandwidth >= IEEE80211_STA_RX_BW_40) ? 1 : 0;
2092 u8 curshortgi_40mhz = curtxbw_40mhz &&
2093 (sta->ht_cap.cap & IEEE80211_HT_CAP_SGI_40) ?
2094 1 : 0;
2095 u8 curshortgi_20mhz = (sta->ht_cap.cap & IEEE80211_HT_CAP_SGI_20) ?
2096 1 : 0;
2097 enum wireless_mode wirelessmode = 0;
dc0313f4
G		 2098 bool shortgi = false;
2099 u8 rate_mask[5];
2100 u8 macid = 0;
5b8df24e
LF		 2101 u8 mimo_ps = IEEE80211_SMPS_OFF;
2102
2103 sta_entry = (struct rtl_sta_info *) sta->drv_priv;
2104 wirelessmode = sta_entry->wireless_mode;
2105 if (mac->opmode == NL80211_IFTYPE_STATION ||
2106 mac->opmode == NL80211_IFTYPE_MESH_POINT)
2107 curtxbw_40mhz = mac->bw_40;
2108 else if (mac->opmode == NL80211_IFTYPE_AP ||
2109 mac->opmode == NL80211_IFTYPE_ADHOC)
2110 macid = sta->aid + 1;
2111
2112 if (rtlhal->current_bandtype == BAND_ON_5G)
2113 ratr_bitmap = sta->supp_rates[1] << 4;
2114 else
2115 ratr_bitmap = sta->supp_rates[0];
2116 if (mac->opmode == NL80211_IFTYPE_ADHOC)
2117 ratr_bitmap = 0xfff;
2118 ratr_bitmap |= (sta->ht_cap.mcs.rx_mask[1] << 20 |
2119 sta->ht_cap.mcs.rx_mask[0] << 12);
dc0313f4
G		 2120 switch (wirelessmode) {
2121 case WIRELESS_MODE_B:
2122 ratr_index = RATR_INX_WIRELESS_B;
2123 if (ratr_bitmap & 0x0000000c)
2124 ratr_bitmap &= 0x0000000d;
2125 else
2126 ratr_bitmap &= 0x0000000f;
2127 break;
2128 case WIRELESS_MODE_G:
2129 ratr_index = RATR_INX_WIRELESS_GB;
5b8df24e 2130
dc0313f4
G		 2131 if (rssi_level == 1)
2132 ratr_bitmap &= 0x00000f00;
2133 else if (rssi_level == 2)
2134 ratr_bitmap &= 0x00000ff0;
2135 else
2136 ratr_bitmap &= 0x00000ff5;
2137 break;
2138 case WIRELESS_MODE_A:
2139 ratr_index = RATR_INX_WIRELESS_A;
2140 ratr_bitmap &= 0x00000ff0;
2141 break;
2142 case WIRELESS_MODE_N_24G:
2143 case WIRELESS_MODE_N_5G:
2144 ratr_index = RATR_INX_WIRELESS_NGB;
5b8df24e
LF		 2145
2146 if (mimo_ps == IEEE80211_SMPS_STATIC) {
dc0313f4
G		 2147 if (rssi_level == 1)
2148 ratr_bitmap &= 0x00070000;
2149 else if (rssi_level == 2)
2150 ratr_bitmap &= 0x0007f000;
2151 else
2152 ratr_bitmap &= 0x0007f005;
2153 } else {
2154 if (rtlphy->rf_type == RF_1T2R ||
2155 rtlphy->rf_type == RF_1T1R) {
2156 if (curtxbw_40mhz) {
2157 if (rssi_level == 1)
2158 ratr_bitmap &= 0x000f0000;
2159 else if (rssi_level == 2)
2160 ratr_bitmap &= 0x000ff000;
2161 else
2162 ratr_bitmap &= 0x000ff015;
2163 } else {
2164 if (rssi_level == 1)
2165 ratr_bitmap &= 0x000f0000;
2166 else if (rssi_level == 2)
2167 ratr_bitmap &= 0x000ff000;
2168 else
2169 ratr_bitmap &= 0x000ff005;
2170 }
2171 } else {
2172 if (curtxbw_40mhz) {
2173 if (rssi_level == 1)
2174 ratr_bitmap &= 0x0f0f0000;
2175 else if (rssi_level == 2)
2176 ratr_bitmap &= 0x0f0ff000;
2177 else
2178 ratr_bitmap &= 0x0f0ff015;
2179 } else {
2180 if (rssi_level == 1)
2181 ratr_bitmap &= 0x0f0f0000;
2182 else if (rssi_level == 2)
2183 ratr_bitmap &= 0x0f0ff000;
2184 else
2185 ratr_bitmap &= 0x0f0ff005;
2186 }
2187 }
2188 }
5b8df24e 2189
dc0313f4
G		 2190 if ((curtxbw_40mhz && curshortgi_40mhz) ||
2191 (!curtxbw_40mhz && curshortgi_20mhz)) {
5b8df24e 2192
dc0313f4
G		 2193 if (macid == 0)
2194 shortgi = true;
2195 else if (macid == 1)
2196 shortgi = false;
2197 }
2198 break;
2199 default:
2200 ratr_index = RATR_INX_WIRELESS_NGB;
5b8df24e 2201
dc0313f4
G		 2202 if (rtlphy->rf_type == RF_1T2R)
2203 ratr_bitmap &= 0x000ff0ff;
2204 else
2205 ratr_bitmap &= 0x0f0ff0ff;
2206 break;
2207 }
5b8df24e
LF		 2208 sta_entry->ratr_index = ratr_index;
2209
2210 RT_TRACE(rtlpriv, COMP_RATR, DBG_DMESG,
2211 "ratr_bitmap :%x\n", ratr_bitmap);
2212 *(u32 *)&rate_mask = (ratr_bitmap & 0x0fffffff) |
2213 (ratr_index << 28);
dc0313f4 2214 rate_mask[4] = macid | (shortgi ? 0x20 : 0x00) | 0x80;
f30d7507 2215 RT_TRACE(rtlpriv, COMP_RATR, DBG_DMESG,
ed9f0ed3
AS		 2216 "Rate_index:%x, ratr_val:%x, %5phC\n",
2217 ratr_index, ratr_bitmap, rate_mask);
5b8df24e
LF		 2218 memcpy(rtlpriv->rate_mask, rate_mask, 5);
2219 /* rtl92c_fill_h2c_cmd() does USB I/O and will result in a
2220 * "scheduled while atomic" if called directly */
2221 schedule_work(&rtlpriv->works.fill_h2c_cmd);
2222
2223 if (macid != 0)
2224 sta_entry->ratr_index = ratr_index;
2225}
2226
2227void rtl92cu_update_hal_rate_tbl(struct ieee80211_hw *hw,
2228 struct ieee80211_sta *sta,
2229 u8 rssi_level)
2230{
2231 struct rtl_priv *rtlpriv = rtl_priv(hw);
2232
2233 if (rtlpriv->dm.useramask)
2234 rtl92cu_update_hal_rate_mask(hw, sta, rssi_level);
2235 else
2236 rtl92cu_update_hal_rate_table(hw, sta);
dc0313f4
G		 2237}
2238
2239void rtl92cu_update_channel_access_setting(struct ieee80211_hw *hw)
2240{
2241 struct rtl_priv *rtlpriv = rtl_priv(hw);
2242 struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
2243 u16 sifs_timer;
2244
2245 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_SLOT_TIME,
2c208890 2246 &mac->slot_time);
dc0313f4
G		 2247 if (!mac->ht_enable)
2248 sifs_timer = 0x0a0a;
2249 else
2250 sifs_timer = 0x0e0e;
2251 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_SIFS, (u8 *)&sifs_timer);
2252}
2253
2254bool rtl92cu_gpio_radio_on_off_checking(struct ieee80211_hw *hw, u8 * valid)
2255{
2256 struct rtl_priv *rtlpriv = rtl_priv(hw);
2257 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
2258 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
2259 enum rf_pwrstate e_rfpowerstate_toset, cur_rfstate;
2260 u8 u1tmp = 0;
2261 bool actuallyset = false;
2262 unsigned long flag = 0;
2263 /* to do - usb autosuspend */
2264 u8 usb_autosuspend = 0;
2265
2266 if (ppsc->swrf_processing)
2267 return false;
2268 spin_lock_irqsave(&rtlpriv->locks.rf_ps_lock, flag);
2269 if (ppsc->rfchange_inprogress) {
2270 spin_unlock_irqrestore(&rtlpriv->locks.rf_ps_lock, flag);
2271 return false;
2272 } else {
2273 ppsc->rfchange_inprogress = true;
2274 spin_unlock_irqrestore(&rtlpriv->locks.rf_ps_lock, flag);
2275 }
2276 cur_rfstate = ppsc->rfpwr_state;
2277 if (usb_autosuspend) {
2278 /* to do................... */
2279 } else {
2280 if (ppsc->pwrdown_mode) {
2281 u1tmp = rtl_read_byte(rtlpriv, REG_HSISR);
2282 e_rfpowerstate_toset = (u1tmp & BIT(7)) ?
2283 ERFOFF : ERFON;
2284 RT_TRACE(rtlpriv, COMP_POWER, DBG_DMESG,
f30d7507 2285 "pwrdown, 0x5c(BIT7)=%02x\n", u1tmp);
dc0313f4
G		 2286 } else {
2287 rtl_write_byte(rtlpriv, REG_MAC_PINMUX_CFG,
2288 rtl_read_byte(rtlpriv,
2289 REG_MAC_PINMUX_CFG) & ~(BIT(3)));
2290 u1tmp = rtl_read_byte(rtlpriv, REG_GPIO_IO_SEL);
2291 e_rfpowerstate_toset = (u1tmp & BIT(3)) ?
2292 ERFON : ERFOFF;
2293 RT_TRACE(rtlpriv, COMP_POWER, DBG_DMESG,
f30d7507 2294 "GPIO_IN=%02x\n", u1tmp);
dc0313f4 2295 }
f30d7507
JP		 2296 RT_TRACE(rtlpriv, COMP_POWER, DBG_LOUD, "N-SS RF =%x\n",
2297 e_rfpowerstate_toset);
dc0313f4
G		 2298 }
2299 if ((ppsc->hwradiooff) && (e_rfpowerstate_toset == ERFON)) {
f30d7507
JP		 2300 RT_TRACE(rtlpriv, COMP_POWER, DBG_LOUD,
2301 "GPIOChangeRF - HW Radio ON, RF ON\n");
dc0313f4
G		 2302 ppsc->hwradiooff = false;
2303 actuallyset = true;
2304 } else if ((!ppsc->hwradiooff) && (e_rfpowerstate_toset ==
2305 ERFOFF)) {
f30d7507
JP		 2306 RT_TRACE(rtlpriv, COMP_POWER, DBG_LOUD,
2307 "GPIOChangeRF - HW Radio OFF\n");
dc0313f4
G		 2308 ppsc->hwradiooff = true;
2309 actuallyset = true;
2310 } else {
f30d7507
JP		 2311 RT_TRACE(rtlpriv, COMP_POWER, DBG_LOUD,
2312 "pHalData->bHwRadioOff and eRfPowerStateToSet do not match: pHalData->bHwRadioOff %x, eRfPowerStateToSet %x\n",
2313 ppsc->hwradiooff, e_rfpowerstate_toset);
dc0313f4
G		 2314 }
2315 if (actuallyset) {
3db1cd5c 2316 ppsc->hwradiooff = true;
dc0313f4
G		 2317 if (e_rfpowerstate_toset == ERFON) {
2318 if ((ppsc->reg_rfps_level & RT_RF_OFF_LEVL_ASPM) &&
2319 RT_IN_PS_LEVEL(ppsc, RT_RF_OFF_LEVL_ASPM))
2320 RT_CLEAR_PS_LEVEL(ppsc, RT_RF_OFF_LEVL_ASPM);
2321 else if ((ppsc->reg_rfps_level & RT_RF_OFF_LEVL_PCI_D3)
2322 && RT_IN_PS_LEVEL(ppsc, RT_RF_OFF_LEVL_PCI_D3))
2323 RT_CLEAR_PS_LEVEL(ppsc, RT_RF_OFF_LEVL_PCI_D3);
2324 }
2325 spin_lock_irqsave(&rtlpriv->locks.rf_ps_lock, flag);
2326 ppsc->rfchange_inprogress = false;
2327 spin_unlock_irqrestore(&rtlpriv->locks.rf_ps_lock, flag);
2328 /* For power down module, we need to enable register block
2329 * contrl reg at 0x1c. Then enable power down control bit
2330 * of register 0x04 BIT4 and BIT15 as 1.
2331 */
2332 if (ppsc->pwrdown_mode && e_rfpowerstate_toset == ERFOFF) {
2333 /* Enable register area 0x0-0xc. */
2334 rtl_write_byte(rtlpriv, REG_RSV_CTRL, 0x0);
2335 if (IS_HARDWARE_TYPE_8723U(rtlhal)) {
2336 /*
2337 * We should configure HW PDn source for WiFi
2338 * ONLY, and then our HW will be set in
2339 * power-down mode if PDn source from all
2340 * functions are configured.
2341 */
2342 u1tmp = rtl_read_byte(rtlpriv,
2343 REG_MULTI_FUNC_CTRL);
2344 rtl_write_byte(rtlpriv, REG_MULTI_FUNC_CTRL,
2345 (u1tmp|WL_HWPDN_EN));
2346 } else {
2347 rtl_write_word(rtlpriv, REG_APS_FSMCO, 0x8812);
2348 }
2349 }
2350 if (e_rfpowerstate_toset == ERFOFF) {
2351 if (ppsc->reg_rfps_level & RT_RF_OFF_LEVL_ASPM)
2352 RT_SET_PS_LEVEL(ppsc, RT_RF_OFF_LEVL_ASPM);
2353 else if (ppsc->reg_rfps_level & RT_RF_OFF_LEVL_PCI_D3)
2354 RT_SET_PS_LEVEL(ppsc, RT_RF_OFF_LEVL_PCI_D3);
2355 }
2356 } else if (e_rfpowerstate_toset == ERFOFF || cur_rfstate == ERFOFF) {
2357 /* Enter D3 or ASPM after GPIO had been done. */
2358 if (ppsc->reg_rfps_level & RT_RF_OFF_LEVL_ASPM)
2359 RT_SET_PS_LEVEL(ppsc, RT_RF_OFF_LEVL_ASPM);
2360 else if (ppsc->reg_rfps_level & RT_RF_OFF_LEVL_PCI_D3)
2361 RT_SET_PS_LEVEL(ppsc, RT_RF_OFF_LEVL_PCI_D3);
2362 spin_lock_irqsave(&rtlpriv->locks.rf_ps_lock, flag);
2363 ppsc->rfchange_inprogress = false;
2364 spin_unlock_irqrestore(&rtlpriv->locks.rf_ps_lock, flag);
2365 } else {
2366 spin_lock_irqsave(&rtlpriv->locks.rf_ps_lock, flag);
2367 ppsc->rfchange_inprogress = false;
2368 spin_unlock_irqrestore(&rtlpriv->locks.rf_ps_lock, flag);
2369 }
2370 *valid = 1;
2371 return !ppsc->hwradiooff;
2372}
Linux kernel - Deliverables
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