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rtlwifi: rtl8723be: Update driver to match Realtek release of 06/28/14
[deliverable/linux.git] / drivers / net / wireless / rtlwifi / rtl8192cu / phy.c
CommitLineData
f0a39ae7
G		 1/******************************************************************************
2 *
c1d6604d 3 * Copyright(c) 2009-2012 Realtek Corporation.
f0a39ae7
G		 4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of version 2 of the GNU General Public License as
7 * published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details.
13 *
14 * You should have received a copy of the GNU General Public License along with
15 * this program; if not, write to the Free Software Foundation, Inc.,
16 * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
17 *
18 * The full GNU General Public License is included in this distribution in the
19 * file called LICENSE.
20 *
21 * Contact Information:
22 * wlanfae <wlanfae@realtek.com>
23 * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
24 * Hsinchu 300, Taiwan.
25 *
26 * Larry Finger <Larry.Finger@lwfinger.net>
27 *
28 *****************************************************************************/
29
30#include "../wifi.h"
31#include "../pci.h"
32#include "../ps.h"
25b13dbc 33#include "../core.h"
f0a39ae7
G		 34#include "reg.h"
35#include "def.h"
36#include "phy.h"
37#include "rf.h"
38#include "dm.h"
39#include "table.h"
40
1472d3a8 41u32 rtl92cu_phy_query_rf_reg(struct ieee80211_hw *hw,
d3bb1429 42 enum radio_path rfpath, u32 regaddr, u32 bitmask)
f0a39ae7
G		 43{
44 struct rtl_priv *rtlpriv = rtl_priv(hw);
45 u32 original_value, readback_value, bitshift;
46 struct rtl_phy *rtlphy = &(rtlpriv->phy);
47
f30d7507
JP		 48 RT_TRACE(rtlpriv, COMP_RF, DBG_TRACE,
49 "regaddr(%#x), rfpath(%#x), bitmask(%#x)\n",
50 regaddr, rfpath, bitmask);
f0a39ae7
G		 51 if (rtlphy->rf_mode != RF_OP_BY_FW) {
52 original_value = _rtl92c_phy_rf_serial_read(hw,
53 rfpath, regaddr);
54 } else {
55 original_value = _rtl92c_phy_fw_rf_serial_read(hw,
56 rfpath, regaddr);
57 }
58 bitshift = _rtl92c_phy_calculate_bit_shift(bitmask);
59 readback_value = (original_value & bitmask) >> bitshift;
60 RT_TRACE(rtlpriv, COMP_RF, DBG_TRACE,
f30d7507
JP		 61 "regaddr(%#x), rfpath(%#x), bitmask(%#x), original_value(%#x)\n",
62 regaddr, rfpath, bitmask, original_value);
f0a39ae7
G		 63 return readback_value;
64}
65
1472d3a8 66void rtl92cu_phy_set_rf_reg(struct ieee80211_hw *hw,
d3bb1429
LF		 67 enum radio_path rfpath,
68 u32 regaddr, u32 bitmask, u32 data)
f0a39ae7
G		 69{
70 struct rtl_priv *rtlpriv = rtl_priv(hw);
71 struct rtl_phy *rtlphy = &(rtlpriv->phy);
72 u32 original_value, bitshift;
73
74 RT_TRACE(rtlpriv, COMP_RF, DBG_TRACE,
f30d7507
JP		 75 "regaddr(%#x), bitmask(%#x), data(%#x), rfpath(%#x)\n",
76 regaddr, bitmask, data, rfpath);
f0a39ae7
G		 77 if (rtlphy->rf_mode != RF_OP_BY_FW) {
78 if (bitmask != RFREG_OFFSET_MASK) {
79 original_value = _rtl92c_phy_rf_serial_read(hw,
80 rfpath,
81 regaddr);
82 bitshift = _rtl92c_phy_calculate_bit_shift(bitmask);
83 data =
84 ((original_value & (~bitmask)) |
85 (data << bitshift));
86 }
87 _rtl92c_phy_rf_serial_write(hw, rfpath, regaddr, data);
88 } else {
89 if (bitmask != RFREG_OFFSET_MASK) {
90 original_value = _rtl92c_phy_fw_rf_serial_read(hw,
91 rfpath,
92 regaddr);
93 bitshift = _rtl92c_phy_calculate_bit_shift(bitmask);
94 data =
95 ((original_value & (~bitmask)) |
96 (data << bitshift));
97 }
98 _rtl92c_phy_fw_rf_serial_write(hw, rfpath, regaddr, data);
99 }
f30d7507
JP		 100 RT_TRACE(rtlpriv, COMP_RF, DBG_TRACE,
101 "regaddr(%#x), bitmask(%#x), data(%#x), rfpath(%#x)\n",
102 regaddr, bitmask, data, rfpath);
f0a39ae7
G		 103}
104
1472d3a8 105bool rtl92cu_phy_mac_config(struct ieee80211_hw *hw)
f0a39ae7
G		 106{
107 bool rtstatus;
108 struct rtl_priv *rtlpriv = rtl_priv(hw);
109 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
110 bool is92c = IS_92C_SERIAL(rtlhal->version);
111
1472d3a8 112 rtstatus = _rtl92cu_phy_config_mac_with_headerfile(hw);
f0a39ae7
G		 113 if (is92c && IS_HARDWARE_TYPE_8192CE(rtlhal))
114 rtl_write_byte(rtlpriv, 0x14, 0x71);
115 return rtstatus;
116}
117
1472d3a8 118bool rtl92cu_phy_bb_config(struct ieee80211_hw *hw)
f0a39ae7
G		 119{
120 bool rtstatus = true;
121 struct rtl_priv *rtlpriv = rtl_priv(hw);
122 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
123 u16 regval;
8a719208 124 u32 regval32;
f0a39ae7
G		 125 u8 b_reg_hwparafile = 1;
126
127 _rtl92c_phy_init_bb_rf_register_definition(hw);
128 regval = rtl_read_word(rtlpriv, REG_SYS_FUNC_EN);
129 rtl_write_word(rtlpriv, REG_SYS_FUNC_EN, regval | BIT(13) |
130 BIT(0) | BIT(1));
131 rtl_write_byte(rtlpriv, REG_AFE_PLL_CTRL, 0x83);
132 rtl_write_byte(rtlpriv, REG_AFE_PLL_CTRL + 1, 0xdb);
133 rtl_write_byte(rtlpriv, REG_RF_CTRL, RF_EN | RF_RSTB | RF_SDMRSTB);
134 if (IS_HARDWARE_TYPE_8192CE(rtlhal)) {
135 rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN, FEN_PPLL | FEN_PCIEA |
136 FEN_DIO_PCIE | FEN_BB_GLB_RSTn | FEN_BBRSTB);
137 } else if (IS_HARDWARE_TYPE_8192CU(rtlhal)) {
138 rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN, FEN_USBA | FEN_USBD |
139 FEN_BB_GLB_RSTn | FEN_BBRSTB);
f0a39ae7 140 }
8a719208
MCA		 141 regval32 = rtl_read_dword(rtlpriv, 0x87c);
142 rtl_write_dword(rtlpriv, 0x87c, regval32 & (~BIT(31)));
143 if (IS_HARDWARE_TYPE_8192CU(rtlhal))
144 rtl_write_byte(rtlpriv, REG_LDOHCI12_CTRL, 0x0f);
f0a39ae7
G		 145 rtl_write_byte(rtlpriv, REG_AFE_XTAL_CTRL + 1, 0x80);
146 if (b_reg_hwparafile == 1)
147 rtstatus = _rtl92c_phy_bb8192c_config_parafile(hw);
148 return rtstatus;
149}
150
1472d3a8 151bool _rtl92cu_phy_config_mac_with_headerfile(struct ieee80211_hw *hw)
f0a39ae7
G		 152{
153 struct rtl_priv *rtlpriv = rtl_priv(hw);
154 struct rtl_phy *rtlphy = &(rtlpriv->phy);
155 u32 i;
156 u32 arraylength;
157 u32 *ptrarray;
158
f30d7507 159 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE, "Read Rtl819XMACPHY_Array\n");
f0a39ae7
G		 160 arraylength = rtlphy->hwparam_tables[MAC_REG].length ;
161 ptrarray = rtlphy->hwparam_tables[MAC_REG].pdata;
f30d7507 162 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE, "Img:RTL8192CEMAC_2T_ARRAY\n");
f0a39ae7
G		 163 for (i = 0; i < arraylength; i = i + 2)
164 rtl_write_byte(rtlpriv, ptrarray[i], (u8) ptrarray[i + 1]);
165 return true;
166}
167
1472d3a8 168bool _rtl92cu_phy_config_bb_with_headerfile(struct ieee80211_hw *hw,
d3bb1429 169 u8 configtype)
f0a39ae7
G		 170{
171 int i;
172 u32 *phy_regarray_table;
173 u32 *agctab_array_table;
174 u16 phy_reg_arraylen, agctab_arraylen;
175 struct rtl_priv *rtlpriv = rtl_priv(hw);
176 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
177 struct rtl_phy *rtlphy = &(rtlpriv->phy);
178
179 if (IS_92C_SERIAL(rtlhal->version)) {
180 agctab_arraylen = rtlphy->hwparam_tables[AGCTAB_2T].length;
181 agctab_array_table = rtlphy->hwparam_tables[AGCTAB_2T].pdata;
182 phy_reg_arraylen = rtlphy->hwparam_tables[PHY_REG_2T].length;
183 phy_regarray_table = rtlphy->hwparam_tables[PHY_REG_2T].pdata;
184 } else {
185 agctab_arraylen = rtlphy->hwparam_tables[AGCTAB_1T].length;
186 agctab_array_table = rtlphy->hwparam_tables[AGCTAB_1T].pdata;
187 phy_reg_arraylen = rtlphy->hwparam_tables[PHY_REG_1T].length;
188 phy_regarray_table = rtlphy->hwparam_tables[PHY_REG_1T].pdata;
189 }
190 if (configtype == BASEBAND_CONFIG_PHY_REG) {
191 for (i = 0; i < phy_reg_arraylen; i = i + 2) {
25b13dbc 192 rtl_addr_delay(phy_regarray_table[i]);
f0a39ae7
G		 193 rtl_set_bbreg(hw, phy_regarray_table[i], MASKDWORD,
194 phy_regarray_table[i + 1]);
195 udelay(1);
196 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
f30d7507
JP		 197 "The phy_regarray_table[0] is %x Rtl819XPHY_REGArray[1] is %x\n",
198 phy_regarray_table[i],
199 phy_regarray_table[i + 1]);
f0a39ae7 200 }
f0a39ae7
G		 201 } else if (configtype == BASEBAND_CONFIG_AGC_TAB) {
202 for (i = 0; i < agctab_arraylen; i = i + 2) {
203 rtl_set_bbreg(hw, agctab_array_table[i], MASKDWORD,
204 agctab_array_table[i + 1]);
205 udelay(1);
206 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
f30d7507
JP		 207 "The agctab_array_table[0] is %x Rtl819XPHY_REGArray[1] is %x\n",
208 agctab_array_table[i],
209 agctab_array_table[i + 1]);
f0a39ae7
G		 210 }
211 }
212 return true;
213}
214
1472d3a8 215bool _rtl92cu_phy_config_bb_with_pgheaderfile(struct ieee80211_hw *hw,
d3bb1429 216 u8 configtype)
f0a39ae7
G		 217{
218 struct rtl_priv *rtlpriv = rtl_priv(hw);
219 struct rtl_phy *rtlphy = &(rtlpriv->phy);
220 int i;
221 u32 *phy_regarray_table_pg;
222 u16 phy_regarray_pg_len;
223
224 rtlphy->pwrgroup_cnt = 0;
225 phy_regarray_pg_len = rtlphy->hwparam_tables[PHY_REG_PG].length;
226 phy_regarray_table_pg = rtlphy->hwparam_tables[PHY_REG_PG].pdata;
227 if (configtype == BASEBAND_CONFIG_PHY_REG) {
228 for (i = 0; i < phy_regarray_pg_len; i = i + 3) {
25b13dbc 229 rtl_addr_delay(phy_regarray_table_pg[i]);
f0a39ae7
G		 230 _rtl92c_store_pwrIndex_diffrate_offset(hw,
231 phy_regarray_table_pg[i],
232 phy_regarray_table_pg[i + 1],
233 phy_regarray_table_pg[i + 2]);
234 }
235 } else {
236 RT_TRACE(rtlpriv, COMP_SEND, DBG_TRACE,
f30d7507 237 "configtype != BaseBand_Config_PHY_REG\n");
f0a39ae7
G		 238 }
239 return true;
240}
241
1472d3a8 242bool rtl92cu_phy_config_rf_with_headerfile(struct ieee80211_hw *hw,
f0a39ae7
G		 243 enum radio_path rfpath)
244{
245 int i;
246 u32 *radioa_array_table;
247 u32 *radiob_array_table;
248 u16 radioa_arraylen, radiob_arraylen;
249 struct rtl_priv *rtlpriv = rtl_priv(hw);
250 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
251 struct rtl_phy *rtlphy = &(rtlpriv->phy);
252
253 if (IS_92C_SERIAL(rtlhal->version)) {
254 radioa_arraylen = rtlphy->hwparam_tables[RADIOA_2T].length;
255 radioa_array_table = rtlphy->hwparam_tables[RADIOA_2T].pdata;
256 radiob_arraylen = rtlphy->hwparam_tables[RADIOB_2T].length;
257 radiob_array_table = rtlphy->hwparam_tables[RADIOB_2T].pdata;
258 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
f30d7507 259 "Radio_A:RTL8192CERADIOA_2TARRAY\n");
f0a39ae7 260 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
f30d7507 261 "Radio_B:RTL8192CE_RADIOB_2TARRAY\n");
f0a39ae7
G		 262 } else {
263 radioa_arraylen = rtlphy->hwparam_tables[RADIOA_1T].length;
264 radioa_array_table = rtlphy->hwparam_tables[RADIOA_1T].pdata;
265 radiob_arraylen = rtlphy->hwparam_tables[RADIOB_1T].length;
266 radiob_array_table = rtlphy->hwparam_tables[RADIOB_1T].pdata;
267 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
f30d7507 268 "Radio_A:RTL8192CE_RADIOA_1TARRAY\n");
f0a39ae7 269 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
f30d7507 270 "Radio_B:RTL8192CE_RADIOB_1TARRAY\n");
f0a39ae7 271 }
f30d7507 272 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE, "Radio No %x\n", rfpath);
f0a39ae7
G		 273 switch (rfpath) {
274 case RF90_PATH_A:
275 for (i = 0; i < radioa_arraylen; i = i + 2) {
25b13dbc
LF		 276 rtl_rfreg_delay(hw, rfpath, radioa_array_table[i],
277 RFREG_OFFSET_MASK,
278 radioa_array_table[i + 1]);
f0a39ae7 279 }
f0a39ae7
G		 280 break;
281 case RF90_PATH_B:
282 for (i = 0; i < radiob_arraylen; i = i + 2) {
25b13dbc
LF		 283 rtl_rfreg_delay(hw, rfpath, radiob_array_table[i],
284 RFREG_OFFSET_MASK,
285 radiob_array_table[i + 1]);
f0a39ae7
G		 286 }
287 break;
288 case RF90_PATH_C:
289 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
f30d7507 290 "switch case not processed\n");
f0a39ae7
G		 291 break;
292 case RF90_PATH_D:
293 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
f30d7507 294 "switch case not processed\n");
f0a39ae7 295 break;
25b13dbc
LF		 296 default:
297 break;
f0a39ae7
G		 298 }
299 return true;
300}
301
1472d3a8 302void rtl92cu_phy_set_bw_mode_callback(struct ieee80211_hw *hw)
f0a39ae7
G		 303{
304 struct rtl_priv *rtlpriv = rtl_priv(hw);
305 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
306 struct rtl_phy *rtlphy = &(rtlpriv->phy);
307 struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
308 u8 reg_bw_opmode;
309 u8 reg_prsr_rsc;
310
f30d7507
JP		 311 RT_TRACE(rtlpriv, COMP_SCAN, DBG_TRACE, "Switch to %s bandwidth\n",
312 rtlphy->current_chan_bw == HT_CHANNEL_WIDTH_20 ?
313 "20MHz" : "40MHz");
f0a39ae7
G		 314 if (is_hal_stop(rtlhal)) {
315 rtlphy->set_bwmode_inprogress = false;
316 return;
317 }
318 reg_bw_opmode = rtl_read_byte(rtlpriv, REG_BWOPMODE);
319 reg_prsr_rsc = rtl_read_byte(rtlpriv, REG_RRSR + 2);
320 switch (rtlphy->current_chan_bw) {
321 case HT_CHANNEL_WIDTH_20:
322 reg_bw_opmode |= BW_OPMODE_20MHZ;
323 rtl_write_byte(rtlpriv, REG_BWOPMODE, reg_bw_opmode);
324 break;
325 case HT_CHANNEL_WIDTH_20_40:
326 reg_bw_opmode &= ~BW_OPMODE_20MHZ;
327 rtl_write_byte(rtlpriv, REG_BWOPMODE, reg_bw_opmode);
328 reg_prsr_rsc =
329 (reg_prsr_rsc & 0x90) | (mac->cur_40_prime_sc << 5);
330 rtl_write_byte(rtlpriv, REG_RRSR + 2, reg_prsr_rsc);
331 break;
332 default:
333 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
f30d7507 334 "unknown bandwidth: %#X\n", rtlphy->current_chan_bw);
f0a39ae7
G		 335 break;
336 }
337 switch (rtlphy->current_chan_bw) {
338 case HT_CHANNEL_WIDTH_20:
339 rtl_set_bbreg(hw, RFPGA0_RFMOD, BRFMOD, 0x0);
340 rtl_set_bbreg(hw, RFPGA1_RFMOD, BRFMOD, 0x0);
341 rtl_set_bbreg(hw, RFPGA0_ANALOGPARAMETER2, BIT(10), 1);
342 break;
343 case HT_CHANNEL_WIDTH_20_40:
344 rtl_set_bbreg(hw, RFPGA0_RFMOD, BRFMOD, 0x1);
345 rtl_set_bbreg(hw, RFPGA1_RFMOD, BRFMOD, 0x1);
346 rtl_set_bbreg(hw, RCCK0_SYSTEM, BCCK_SIDEBAND,
347 (mac->cur_40_prime_sc >> 1));
348 rtl_set_bbreg(hw, ROFDM1_LSTF, 0xC00, mac->cur_40_prime_sc);
349 rtl_set_bbreg(hw, RFPGA0_ANALOGPARAMETER2, BIT(10), 0);
350 rtl_set_bbreg(hw, 0x818, (BIT(26) | BIT(27)),
351 (mac->cur_40_prime_sc ==
352 HAL_PRIME_CHNL_OFFSET_LOWER) ? 2 : 1);
353 break;
354 default:
355 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
f30d7507 356 "unknown bandwidth: %#X\n", rtlphy->current_chan_bw);
f0a39ae7
G		 357 break;
358 }
1472d3a8 359 rtl92cu_phy_rf6052_set_bandwidth(hw, rtlphy->current_chan_bw);
f0a39ae7 360 rtlphy->set_bwmode_inprogress = false;
f30d7507 361 RT_TRACE(rtlpriv, COMP_SCAN, DBG_TRACE, "<==\n");
f0a39ae7
G		 362}
363
1472d3a8 364void rtl92cu_bb_block_on(struct ieee80211_hw *hw)
f0a39ae7
G		 365{
366 struct rtl_priv *rtlpriv = rtl_priv(hw);
367
368 mutex_lock(&rtlpriv->io.bb_mutex);
369 rtl_set_bbreg(hw, RFPGA0_RFMOD, BCCKEN, 0x1);
370 rtl_set_bbreg(hw, RFPGA0_RFMOD, BOFDMEN, 0x1);
371 mutex_unlock(&rtlpriv->io.bb_mutex);
372}
373
1472d3a8 374void _rtl92cu_phy_lc_calibrate(struct ieee80211_hw *hw, bool is2t)
f0a39ae7
G		 375{
376 u8 tmpreg;
377 u32 rf_a_mode = 0, rf_b_mode = 0, lc_cal;
378 struct rtl_priv *rtlpriv = rtl_priv(hw);
379
380 tmpreg = rtl_read_byte(rtlpriv, 0xd03);
381
382 if ((tmpreg & 0x70) != 0)
383 rtl_write_byte(rtlpriv, 0xd03, tmpreg & 0x8F);
384 else
385 rtl_write_byte(rtlpriv, REG_TXPAUSE, 0xFF);
386
387 if ((tmpreg & 0x70) != 0) {
388 rf_a_mode = rtl_get_rfreg(hw, RF90_PATH_A, 0x00, MASK12BITS);
389 if (is2t)
390 rf_b_mode = rtl_get_rfreg(hw, RF90_PATH_B, 0x00,
391 MASK12BITS);
392 rtl_set_rfreg(hw, RF90_PATH_A, 0x00, MASK12BITS,
393 (rf_a_mode & 0x8FFFF) | 0x10000);
394 if (is2t)
395 rtl_set_rfreg(hw, RF90_PATH_B, 0x00, MASK12BITS,
396 (rf_b_mode & 0x8FFFF) | 0x10000);
397 }
398 lc_cal = rtl_get_rfreg(hw, RF90_PATH_A, 0x18, MASK12BITS);
399 rtl_set_rfreg(hw, RF90_PATH_A, 0x18, MASK12BITS, lc_cal | 0x08000);
400 mdelay(100);
401 if ((tmpreg & 0x70) != 0) {
402 rtl_write_byte(rtlpriv, 0xd03, tmpreg);
403 rtl_set_rfreg(hw, RF90_PATH_A, 0x00, MASK12BITS, rf_a_mode);
404 if (is2t)
405 rtl_set_rfreg(hw, RF90_PATH_B, 0x00, MASK12BITS,
406 rf_b_mode);
407 } else {
408 rtl_write_byte(rtlpriv, REG_TXPAUSE, 0x00);
409 }
410}
411
d3bb1429 412static bool _rtl92cu_phy_set_rf_power_state(struct ieee80211_hw *hw,
f0a39ae7
G		 413 enum rf_pwrstate rfpwr_state)
414{
415 struct rtl_priv *rtlpriv = rtl_priv(hw);
416 struct rtl_pci_priv *pcipriv = rtl_pcipriv(hw);
417 struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
418 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
419 bool bresult = true;
420 u8 i, queue_id;
421 struct rtl8192_tx_ring *ring = NULL;
422
f0a39ae7
G		 423 switch (rfpwr_state) {
424 case ERFON:
425 if ((ppsc->rfpwr_state == ERFOFF) &&
426 RT_IN_PS_LEVEL(ppsc, RT_RF_OFF_LEVL_HALT_NIC)) {
427 bool rtstatus;
428 u32 InitializeCount = 0;
429
430 do {
431 InitializeCount++;
432 RT_TRACE(rtlpriv, COMP_RF, DBG_DMESG,
f30d7507 433 "IPS Set eRf nic enable\n");
f0a39ae7 434 rtstatus = rtl_ps_enable_nic(hw);
23677ce3 435 } while (!rtstatus && (InitializeCount < 10));
f0a39ae7
G		 436 RT_CLEAR_PS_LEVEL(ppsc,
437 RT_RF_OFF_LEVL_HALT_NIC);
438 } else {
439 RT_TRACE(rtlpriv, COMP_RF, DBG_DMESG,
f30d7507
JP		 440 "Set ERFON sleeped:%d ms\n",
441 jiffies_to_msecs(jiffies -
442 ppsc->last_sleep_jiffies));
f0a39ae7
G		 443 ppsc->last_awake_jiffies = jiffies;
444 rtl92ce_phy_set_rf_on(hw);
445 }
446 if (mac->link_state == MAC80211_LINKED) {
447 rtlpriv->cfg->ops->led_control(hw,
448 LED_CTL_LINK);
449 } else {
450 rtlpriv->cfg->ops->led_control(hw,
451 LED_CTL_NO_LINK);
452 }
453 break;
454 case ERFOFF:
455 for (queue_id = 0, i = 0;
456 queue_id < RTL_PCI_MAX_TX_QUEUE_COUNT;) {
457 ring = &pcipriv->dev.tx_ring[queue_id];
458 if (skb_queue_len(&ring->queue) == 0 ||
459 queue_id == BEACON_QUEUE) {
460 queue_id++;
461 continue;
462 } else {
463 RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING,
f30d7507
JP		 464 "eRf Off/Sleep: %d times TcbBusyQueue[%d] =%d before doze!\n",
465 i + 1,
466 queue_id,
467 skb_queue_len(&ring->queue));
f0a39ae7
G		 468 udelay(10);
469 i++;
470 }
471 if (i >= MAX_DOZE_WAITING_TIMES_9x) {
472 RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING,
f30d7507
JP		 473 "ERFOFF: %d times TcbBusyQueue[%d] = %d !\n",
474 MAX_DOZE_WAITING_TIMES_9x,
475 queue_id,
476 skb_queue_len(&ring->queue));
f0a39ae7
G		 477 break;
478 }
479 }
480 if (ppsc->reg_rfps_level & RT_RF_OFF_LEVL_HALT_NIC) {
481 RT_TRACE(rtlpriv, COMP_RF, DBG_DMESG,
f30d7507 482 "IPS Set eRf nic disable\n");
f0a39ae7
G		 483 rtl_ps_disable_nic(hw);
484 RT_SET_PS_LEVEL(ppsc, RT_RF_OFF_LEVL_HALT_NIC);
485 } else {
486 if (ppsc->rfoff_reason == RF_CHANGE_BY_IPS) {
487 rtlpriv->cfg->ops->led_control(hw,
488 LED_CTL_NO_LINK);
489 } else {
490 rtlpriv->cfg->ops->led_control(hw,
491 LED_CTL_POWER_OFF);
492 }
493 }
494 break;
495 case ERFSLEEP:
496 if (ppsc->rfpwr_state == ERFOFF)
91ddff8a 497 return false;
f0a39ae7
G		 498 for (queue_id = 0, i = 0;
499 queue_id < RTL_PCI_MAX_TX_QUEUE_COUNT;) {
500 ring = &pcipriv->dev.tx_ring[queue_id];
501 if (skb_queue_len(&ring->queue) == 0) {
502 queue_id++;
503 continue;
504 } else {
505 RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING,
f30d7507
JP		 506 "eRf Off/Sleep: %d times TcbBusyQueue[%d] =%d before doze!\n",
507 i + 1, queue_id,
508 skb_queue_len(&ring->queue));
f0a39ae7
G		 509 udelay(10);
510 i++;
511 }
512 if (i >= MAX_DOZE_WAITING_TIMES_9x) {
513 RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING,
f30d7507
JP		 514 "ERFSLEEP: %d times TcbBusyQueue[%d] = %d !\n",
515 MAX_DOZE_WAITING_TIMES_9x,
516 queue_id,
517 skb_queue_len(&ring->queue));
f0a39ae7
G		 518 break;
519 }
520 }
521 RT_TRACE(rtlpriv, COMP_RF, DBG_DMESG,
f30d7507
JP		 522 "Set ERFSLEEP awaked:%d ms\n",
523 jiffies_to_msecs(jiffies - ppsc->last_awake_jiffies));
f0a39ae7 524 ppsc->last_sleep_jiffies = jiffies;
1472d3a8 525 _rtl92c_phy_set_rf_sleep(hw);
f0a39ae7
G		 526 break;
527 default:
528 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
f30d7507 529 "switch case not processed\n");
f0a39ae7
G		 530 bresult = false;
531 break;
532 }
533 if (bresult)
534 ppsc->rfpwr_state = rfpwr_state;
f0a39ae7
G		 535 return bresult;
536}
537
1472d3a8 538bool rtl92cu_phy_set_rf_power_state(struct ieee80211_hw *hw,
d3bb1429 539 enum rf_pwrstate rfpwr_state)
f0a39ae7
G		 540{
541 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
542 bool bresult = false;
543
544 if (rfpwr_state == ppsc->rfpwr_state)
545 return bresult;
1472d3a8 546 bresult = _rtl92cu_phy_set_rf_power_state(hw, rfpwr_state);
f0a39ae7
G		 547 return bresult;
548}
Linux kernel - Deliverables
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