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rtlwifi: Add headers for rtl8187cu
[deliverable/linux.git] / drivers / net / wireless / rtlwifi / rtl8192cu / trx.h
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18d30067
G		 1/******************************************************************************
2 *
3 * Copyright(c) 2009-2010 Realtek Corporation. All rights reserved.
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of version 2 of the GNU General Public License as
7 * published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details.
13 *
14 * You should have received a copy of the GNU General Public License along with
15 * this program; if not, write to the Free Software Foundation, Inc.,
16 * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
17 *
18 * The full GNU General Public License is included in this distribution in the
19 * file called LICENSE.
20 *
21 * Contact Information:
22 * wlanfae <wlanfae@realtek.com>
23 * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
24 * Hsinchu 300, Taiwan.
25 *
26 * Larry Finger <Larry.Finger@lwfinger.net>
27 *
28 *****************************************************************************/
29
30#ifndef __RTL92CU_TRX_H__
31#define __RTL92CU_TRX_H__
32
33#define RTL92C_USB_BULK_IN_NUM 1
34#define RTL92C_NUM_RX_URBS 8
35#define RTL92C_NUM_TX_URBS 32
36
37#define RTL92C_SIZE_MAX_RX_BUFFER 15360 /* 8192 */
38#define RX_DRV_INFO_SIZE_UNIT 8
39
40enum usb_rx_agg_mode {
41 USB_RX_AGG_DISABLE,
42 USB_RX_AGG_DMA,
43 USB_RX_AGG_USB,
44 USB_RX_AGG_DMA_USB
45};
46
47#define TX_SELE_HQ BIT(0) /* High Queue */
48#define TX_SELE_LQ BIT(1) /* Low Queue */
49#define TX_SELE_NQ BIT(2) /* Normal Queue */
50
51#define RTL_USB_TX_AGG_NUM_DESC 5
52
53#define RTL_USB_RX_AGG_PAGE_NUM 4
54#define RTL_USB_RX_AGG_PAGE_TIMEOUT 3
55
56#define RTL_USB_RX_AGG_BLOCK_NUM 5
57#define RTL_USB_RX_AGG_BLOCK_TIMEOUT 3
58
59/*======================== rx status =========================================*/
60
61struct rx_drv_info_92c {
62 /*
63 * Driver info contain PHY status and other variabel size info
64 * PHY Status content as below
65 */
66
67 /* DWORD 0 */
68 u8 gain_trsw[4];
69
70 /* DWORD 1 */
71 u8 pwdb_all;
72 u8 cfosho[4];
73
74 /* DWORD 2 */
75 u8 cfotail[4];
76
77 /* DWORD 3 */
78 s8 rxevm[2];
79 s8 rxsnr[4];
80
81 /* DWORD 4 */
82 u8 pdsnr[2];
83
84 /* DWORD 5 */
85 u8 csi_current[2];
86 u8 csi_target[2];
87
88 /* DWORD 6 */
89 u8 sigevm;
90 u8 max_ex_pwr;
91 u8 ex_intf_flag:1;
92 u8 sgi_en:1;
93 u8 rxsc:2;
94 u8 reserve:4;
95} __packed;
96
97/* Define a macro that takes a le32 word, converts it to host ordering,
98 * right shifts by a specified count, creates a mask of the specified
99 * bit count, and extracts that number of bits.
100 */
101
102#define SHIFT_AND_MASK_LE(__pdesc, __shift, __bits) \
103 ((le32_to_cpu(*(((__le32 *)(__pdesc)))) >> (__shift)) & \
104 BIT_LEN_MASK_32(__bits))
105
106/* Define a macro that clears a bit field in an le32 word and
107 * sets the specified value into that bit field. The resulting
108 * value remains in le32 ordering; however, it is properly converted
109 * to host ordering for the clear and set operations before conversion
110 * back to le32.
111 */
112
113#define SET_BITS_OFFSET_LE(__pdesc, __shift, __len, __val) \
114 (*(__le32 *)(__pdesc) = \
115 (cpu_to_le32((le32_to_cpu(*((__le32 *)(__pdesc))) & \
116 (~(BIT_OFFSET_LEN_MASK_32((__shift), __len)))) | \
117 (((u32)(__val) & BIT_LEN_MASK_32(__len)) << (__shift)))));
118
119/* macros to read various fields in RX descriptor */
120
121/* DWORD 0 */
122#define GET_RX_DESC_PKT_LEN(__rxdesc) \
123 SHIFT_AND_MASK_LE((__rxdesc), 0, 14)
124#define GET_RX_DESC_CRC32(__rxdesc) \
125 SHIFT_AND_MASK_LE(__rxdesc, 14, 1)
126#define GET_RX_DESC_ICV(__rxdesc) \
127 SHIFT_AND_MASK_LE(__rxdesc, 15, 1)
128#define GET_RX_DESC_DRVINFO_SIZE(__rxdesc) \
129 SHIFT_AND_MASK_LE(__rxdesc, 16, 4)
130#define GET_RX_DESC_SECURITY(__rxdesc) \
131 SHIFT_AND_MASK_LE(__rxdesc, 20, 3)
132#define GET_RX_DESC_QOS(__rxdesc) \
133 SHIFT_AND_MASK_LE(__rxdesc, 23, 1)
134#define GET_RX_DESC_SHIFT(__rxdesc) \
135 SHIFT_AND_MASK_LE(__rxdesc, 24, 2)
136#define GET_RX_DESC_PHY_STATUS(__rxdesc) \
137 SHIFT_AND_MASK_LE(__rxdesc, 26, 1)
138#define GET_RX_DESC_SWDEC(__rxdesc) \
139 SHIFT_AND_MASK_LE(__rxdesc, 27, 1)
140#define GET_RX_DESC_LAST_SEG(__rxdesc) \
141 SHIFT_AND_MASK_LE(__rxdesc, 28, 1)
142#define GET_RX_DESC_FIRST_SEG(__rxdesc) \
143 SHIFT_AND_MASK_LE(__rxdesc, 29, 1)
144#define GET_RX_DESC_EOR(__rxdesc) \
145 SHIFT_AND_MASK_LE(__rxdesc, 30, 1)
146#define GET_RX_DESC_OWN(__rxdesc) \
147 SHIFT_AND_MASK_LE(__rxdesc, 31, 1)
148
149/* DWORD 1 */
150#define GET_RX_DESC_MACID(__rxdesc) \
151 SHIFT_AND_MASK_LE(__rxdesc+4, 0, 5)
152#define GET_RX_DESC_TID(__rxdesc) \
153 SHIFT_AND_MASK_LE(__rxdesc+4, 5, 4)
154#define GET_RX_DESC_PAGGR(__rxdesc) \
155 SHIFT_AND_MASK_LE(__rxdesc+4, 14, 1)
156#define GET_RX_DESC_FAGGR(__rxdesc) \
157 SHIFT_AND_MASK_LE(__rxdesc+4, 15, 1)
158#define GET_RX_DESC_A1_FIT(__rxdesc) \
159 SHIFT_AND_MASK_LE(__rxdesc+4, 16, 4)
160#define GET_RX_DESC_A2_FIT(__rxdesc) \
161 SHIFT_AND_MASK_LE(__rxdesc+4, 20, 4)
162#define GET_RX_DESC_PAM(__rxdesc) \
163 SHIFT_AND_MASK_LE(__rxdesc+4, 24, 1)
164#define GET_RX_DESC_PWR(__rxdesc) \
165 SHIFT_AND_MASK_LE(__rxdesc+4, 25, 1)
166#define GET_RX_DESC_MORE_DATA(__rxdesc) \
167 SHIFT_AND_MASK_LE(__rxdesc+4, 26, 1)
168#define GET_RX_DESC_MORE_FRAG(__rxdesc) \
169 SHIFT_AND_MASK_LE(__rxdesc+4, 27, 1)
170#define GET_RX_DESC_TYPE(__rxdesc) \
171 SHIFT_AND_MASK_LE(__rxdesc+4, 28, 2)
172#define GET_RX_DESC_MC(__rxdesc) \
173 SHIFT_AND_MASK_LE(__rxdesc+4, 30, 1)
174#define GET_RX_DESC_BC(__rxdesc) \
175 SHIFT_AND_MASK_LE(__rxdesc+4, 31, 1)
176
177/* DWORD 2 */
178#define GET_RX_DESC_SEQ(__rxdesc) \
179 SHIFT_AND_MASK_LE(__rxdesc+8, 0, 12)
180#define GET_RX_DESC_FRAG(__rxdesc) \
181 SHIFT_AND_MASK_LE(__rxdesc+8, 12, 4)
182#define GET_RX_DESC_USB_AGG_PKTNUM(__rxdesc) \
183 SHIFT_AND_MASK_LE(__rxdesc+8, 16, 8)
184#define GET_RX_DESC_NEXT_IND(__rxdesc) \
185 SHIFT_AND_MASK_LE(__rxdesc+8, 30, 1)
186
187/* DWORD 3 */
188#define GET_RX_DESC_RX_MCS(__rxdesc) \
189 SHIFT_AND_MASK_LE(__rxdesc+12, 0, 6)
190#define GET_RX_DESC_RX_HT(__rxdesc) \
191 SHIFT_AND_MASK_LE(__rxdesc+12, 6, 1)
192#define GET_RX_DESC_AMSDU(__rxdesc) \
193 SHIFT_AND_MASK_LE(__rxdesc+12, 7, 1)
194#define GET_RX_DESC_SPLCP(__rxdesc) \
195 SHIFT_AND_MASK_LE(__rxdesc+12, 8, 1)
196#define GET_RX_DESC_BW(__rxdesc) \
197 SHIFT_AND_MASK_LE(__rxdesc+12, 9, 1)
198#define GET_RX_DESC_HTC(__rxdesc) \
199 SHIFT_AND_MASK_LE(__rxdesc+12, 10, 1)
200#define GET_RX_DESC_TCP_CHK_RPT(__rxdesc) \
201 SHIFT_AND_MASK_LE(__rxdesc+12, 11, 1)
202#define GET_RX_DESC_IP_CHK_RPT(__rxdesc) \
203 SHIFT_AND_MASK_LE(__rxdesc+12, 12, 1)
204#define GET_RX_DESC_TCP_CHK_VALID(__rxdesc) \
205 SHIFT_AND_MASK_LE(__rxdesc+12, 13, 1)
206#define GET_RX_DESC_HWPC_ERR(__rxdesc) \
207 SHIFT_AND_MASK_LE(__rxdesc+12, 14, 1)
208#define GET_RX_DESC_HWPC_IND(__rxdesc) \
209 SHIFT_AND_MASK_LE(__rxdesc+12, 15, 1)
210#define GET_RX_DESC_IV0(__rxdesc) \
211 SHIFT_AND_MASK_LE(__rxdesc+12, 16, 16)
212
213/* DWORD 4 */
214#define GET_RX_DESC_IV1(__rxdesc) \
215 SHIFT_AND_MASK_LE(__rxdesc+16, 0, 32)
216
217/* DWORD 5 */
218#define GET_RX_DESC_TSFL(__rxdesc) \
219 SHIFT_AND_MASK_LE(__rxdesc+20, 0, 32)
220
221/*======================= tx desc ============================================*/
222
223/* macros to set various fields in TX descriptor */
224
225/* Dword 0 */
226#define SET_TX_DESC_PKT_SIZE(__txdesc, __value) \
227 SET_BITS_OFFSET_LE(__txdesc, 0, 16, __value)
228#define SET_TX_DESC_OFFSET(__txdesc, __value) \
229 SET_BITS_OFFSET_LE(__txdesc, 16, 8, __value)
230#define SET_TX_DESC_BMC(__txdesc, __value) \
231 SET_BITS_OFFSET_LE(__txdesc, 24, 1, __value)
232#define SET_TX_DESC_HTC(__txdesc, __value) \
233 SET_BITS_OFFSET_LE(__txdesc, 25, 1, __value)
234#define SET_TX_DESC_LAST_SEG(__txdesc, __value) \
235 SET_BITS_OFFSET_LE(__txdesc, 26, 1, __value)
236#define SET_TX_DESC_FIRST_SEG(__txdesc, __value) \
237 SET_BITS_OFFSET_LE(__txdesc, 27, 1, __value)
238#define SET_TX_DESC_LINIP(__txdesc, __value) \
239 SET_BITS_OFFSET_LE(__txdesc, 28, 1, __value)
240#define SET_TX_DESC_NO_ACM(__txdesc, __value) \
241 SET_BITS_OFFSET_LE(__txdesc, 29, 1, __value)
242#define SET_TX_DESC_GF(__txdesc, __value) \
243 SET_BITS_OFFSET_LE(__txdesc, 30, 1, __value)
244#define SET_TX_DESC_OWN(__txdesc, __value) \
245 SET_BITS_OFFSET_LE(__txdesc, 31, 1, __value)
246
247
248/* Dword 1 */
249#define SET_TX_DESC_MACID(__txdesc, __value) \
250 SET_BITS_OFFSET_LE(__txdesc+4, 0, 5, __value)
251#define SET_TX_DESC_AGG_ENABLE(__txdesc, __value) \
252 SET_BITS_OFFSET_LE(__txdesc+4, 5, 1, __value)
253#define SET_TX_DESC_AGG_BREAK(__txdesc, __value) \
254 SET_BITS_OFFSET_LE(__txdesc+4, 6, 1, __value)
255#define SET_TX_DESC_RDG_ENABLE(__txdesc, __value) \
256 SET_BITS_OFFSET_LE(__txdesc+4, 7, 1, __value)
257#define SET_TX_DESC_QUEUE_SEL(__txdesc, __value) \
258 SET_BITS_OFFSET_LE(__txdesc+4, 8, 5, __value)
259#define SET_TX_DESC_RDG_NAV_EXT(__txdesc, __value) \
260 SET_BITS_OFFSET_LE(__txdesc+4, 13, 1, __value)
261#define SET_TX_DESC_LSIG_TXOP_EN(__txdesc, __value) \
262 SET_BITS_OFFSET_LE(__txdesc+4, 14, 1, __value)
263#define SET_TX_DESC_PIFS(__txdesc, __value) \
264 SET_BITS_OFFSET_LE(__txdesc+4, 15, 1, __value)
265#define SET_TX_DESC_RATE_ID(__txdesc, __value) \
266 SET_BITS_OFFSET_LE(__txdesc+4, 16, 4, __value)
267#define SET_TX_DESC_RA_BRSR_ID(__txdesc, __value) \
268 SET_BITS_OFFSET_LE(__txdesc+4, 16, 4, __value)
269#define SET_TX_DESC_NAV_USE_HDR(__txdesc, __value) \
270 SET_BITS_OFFSET_LE(__txdesc+4, 20, 1, __value)
271#define SET_TX_DESC_EN_DESC_ID(__txdesc, __value) \
272 SET_BITS_OFFSET_LE(__txdesc+4, 21, 1, __value)
273#define SET_TX_DESC_SEC_TYPE(__txdesc, __value) \
274 SET_BITS_OFFSET_LE(__txdesc+4, 22, 2, __value)
275#define SET_TX_DESC_PKT_OFFSET(__txdesc, __value) \
276 SET_BITS_OFFSET_LE(__txdesc+4, 26, 5, __value)
277
278/* Dword 2 */
279#define SET_TX_DESC_RTS_RC(__txdesc, __value) \
280 SET_BITS_OFFSET_LE(__txdesc+8, 0, 6, __value)
281#define SET_TX_DESC_DATA_RC(__txdesc, __value) \
282 SET_BITS_OFFSET_LE(__txdesc+8, 6, 6, __value)
283#define SET_TX_DESC_BAR_RTY_TH(__txdesc, __value) \
284 SET_BITS_OFFSET_LE(__txdesc+8, 14, 2, __value)
285#define SET_TX_DESC_MORE_FRAG(__txdesc, __value) \
286 SET_BITS_OFFSET_LE(__txdesc+8, 17, 1, __value)
287#define SET_TX_DESC_RAW(__txdesc, __value) \
288 SET_BITS_OFFSET_LE(__txdesc+8, 18, 1, __value)
289#define SET_TX_DESC_CCX(__txdesc, __value) \
290 SET_BITS_OFFSET_LE(__txdesc+8, 19, 1, __value)
291#define SET_TX_DESC_AMPDU_DENSITY(__txdesc, __value) \
292 SET_BITS_OFFSET_LE(__txdesc+8, 20, 3, __value)
293#define SET_TX_DESC_ANTSEL_A(__txdesc, __value) \
294 SET_BITS_OFFSET_LE(__txdesc+8, 24, 1, __value)
295#define SET_TX_DESC_ANTSEL_B(__txdesc, __value) \
296 SET_BITS_OFFSET_LE(__txdesc+8, 25, 1, __value)
297#define SET_TX_DESC_TX_ANT_CCK(__txdesc, __value) \
298 SET_BITS_OFFSET_LE(__txdesc+8, 26, 2, __value)
299#define SET_TX_DESC_TX_ANTL(__txdesc, __value) \
300 SET_BITS_OFFSET_LE(__txdesc+8, 28, 2, __value)
301#define SET_TX_DESC_TX_ANT_HT(__txdesc, __value) \
302 SET_BITS_OFFSET_LE(__txdesc+8, 30, 2, __value)
303
304/* Dword 3 */
305#define SET_TX_DESC_NEXT_HEAP_PAGE(__txdesc, __value) \
306 SET_BITS_OFFSET_LE(__txdesc+12, 0, 8, __value)
307#define SET_TX_DESC_TAIL_PAGE(__txdesc, __value) \
308 SET_BITS_OFFSET_LE(__txdesc+12, 8, 8, __value)
309#define SET_TX_DESC_SEQ(__txdesc, __value) \
310 SET_BITS_OFFSET_LE(__txdesc+12, 16, 12, __value)
311#define SET_TX_DESC_PKT_ID(__txdesc, __value) \
312 SET_BITS_OFFSET_LE(__txdesc+12, 28, 4, __value)
313
314/* Dword 4 */
315#define SET_TX_DESC_RTS_RATE(__txdesc, __value) \
316 SET_BITS_OFFSET_LE(__txdesc+16, 0, 5, __value)
317#define SET_TX_DESC_AP_DCFE(__txdesc, __value) \
318 SET_BITS_OFFSET_LE(__txdesc+16, 5, 1, __value)
319#define SET_TX_DESC_QOS(__txdesc, __value) \
320 SET_BITS_OFFSET_LE(__txdesc+16, 6, 1, __value)
321#define SET_TX_DESC_HWSEQ_EN(__txdesc, __value) \
322 SET_BITS_OFFSET_LE(__txdesc+16, 7, 1, __value)
323#define SET_TX_DESC_USE_RATE(__txdesc, __value) \
324 SET_BITS_OFFSET_LE(__txdesc+16, 8, 1, __value)
325#define SET_TX_DESC_DISABLE_RTS_FB(__txdesc, __value) \
326 SET_BITS_OFFSET_LE(__txdesc+16, 9, 1, __value)
327#define SET_TX_DESC_DISABLE_FB(__txdesc, __value) \
328 SET_BITS_OFFSET_LE(__txdesc+16, 10, 1, __value)
329#define SET_TX_DESC_CTS2SELF(__txdesc, __value) \
330 SET_BITS_OFFSET_LE(__txdesc+16, 11, 1, __value)
331#define SET_TX_DESC_RTS_ENABLE(__txdesc, __value) \
332 SET_BITS_OFFSET_LE(__txdesc+16, 12, 1, __value)
333#define SET_TX_DESC_HW_RTS_ENABLE(__txdesc, __value) \
334 SET_BITS_OFFSET_LE(__txdesc+16, 13, 1, __value)
335#define SET_TX_DESC_WAIT_DCTS(__txdesc, __value) \
336 SET_BITS_OFFSET_LE(__txdesc+16, 18, 1, __value)
337#define SET_TX_DESC_CTS2AP_EN(__txdesc, __value) \
338 SET_BITS_OFFSET_LE(__txdesc+16, 19, 1, __value)
339#define SET_TX_DESC_DATA_SC(__txdesc, __value) \
340 SET_BITS_OFFSET_LE(__txdesc+16, 20, 2, __value)
341#define SET_TX_DESC_DATA_STBC(__txdesc, __value) \
342 SET_BITS_OFFSET_LE(__txdesc+16, 22, 2, __value)
343#define SET_TX_DESC_DATA_SHORT(__txdesc, __value) \
344 SET_BITS_OFFSET_LE(__txdesc+16, 24, 1, __value)
345#define SET_TX_DESC_DATA_BW(__txdesc, __value) \
346 SET_BITS_OFFSET_LE(__txdesc+16, 25, 1, __value)
347#define SET_TX_DESC_RTS_SHORT(__txdesc, __value) \
348 SET_BITS_OFFSET_LE(__txdesc+16, 26, 1, __value)
349#define SET_TX_DESC_RTS_BW(__txdesc, __value) \
350 SET_BITS_OFFSET_LE(__txdesc+16, 27, 1, __value)
351#define SET_TX_DESC_RTS_SC(__txdesc, __value) \
352 SET_BITS_OFFSET_LE(__txdesc+16, 28, 2, __value)
353#define SET_TX_DESC_RTS_STBC(__txdesc, __value) \
354 SET_BITS_OFFSET_LE(__txdesc+16, 30, 2, __value)
355
356/* Dword 5 */
357#define SET_TX_DESC_TX_RATE(__pdesc, __val) \
358 SET_BITS_OFFSET_LE(__pdesc+20, 0, 6, __val)
359#define SET_TX_DESC_DATA_SHORTGI(__pdesc, __val) \
360 SET_BITS_OFFSET_LE(__pdesc+20, 6, 1, __val)
361#define SET_TX_DESC_CCX_TAG(__pdesc, __val) \
362 SET_BITS_OFFSET_LE(__pdesc+20, 7, 1, __val)
363#define SET_TX_DESC_DATA_RATE_FB_LIMIT(__txdesc, __value) \
364 SET_BITS_OFFSET_LE(__txdesc+20, 8, 5, __value)
365#define SET_TX_DESC_RTS_RATE_FB_LIMIT(__txdesc, __value) \
366 SET_BITS_OFFSET_LE(__txdesc+20, 13, 4, __value)
367#define SET_TX_DESC_RETRY_LIMIT_ENABLE(__txdesc, __value) \
368 SET_BITS_OFFSET_LE(__txdesc+20, 17, 1, __value)
369#define SET_TX_DESC_DATA_RETRY_LIMIT(__txdesc, __value) \
370 SET_BITS_OFFSET_LE(__txdesc+20, 18, 6, __value)
371#define SET_TX_DESC_USB_TXAGG_NUM(__txdesc, __value) \
372 SET_BITS_OFFSET_LE(__txdesc+20, 24, 8, __value)
373
374/* Dword 6 */
375#define SET_TX_DESC_TXAGC_A(__txdesc, __value) \
376 SET_BITS_OFFSET_LE(__txdesc+24, 0, 5, __value)
377#define SET_TX_DESC_TXAGC_B(__txdesc, __value) \
378 SET_BITS_OFFSET_LE(__txdesc+24, 5, 5, __value)
379#define SET_TX_DESC_USB_MAX_LEN(__txdesc, __value) \
380 SET_BITS_OFFSET_LE(__txdesc+24, 10, 1, __value)
381#define SET_TX_DESC_MAX_AGG_NUM(__txdesc, __value) \
382 SET_BITS_OFFSET_LE(__txdesc+24, 11, 5, __value)
383#define SET_TX_DESC_MCSG1_MAX_LEN(__txdesc, __value) \
384 SET_BITS_OFFSET_LE(__txdesc+24, 16, 4, __value)
385#define SET_TX_DESC_MCSG2_MAX_LEN(__txdesc, __value) \
386 SET_BITS_OFFSET_LE(__txdesc+24, 20, 4, __value)
387#define SET_TX_DESC_MCSG3_MAX_LEN(__txdesc, __value) \
388 SET_BITS_OFFSET_LE(__txdesc+24, 24, 4, __value)
389#define SET_TX_DESC_MCSG7_MAX_LEN(__txdesc, __value) \
390 SET_BITS_OFFSET_LE(__txdesc+24, 28, 4, __value)
391
392/* Dword 7 */
393#define SET_TX_DESC_TX_DESC_CHECKSUM(__txdesc, __value) \
394 SET_BITS_OFFSET_LE(__txdesc+28, 0, 16, __value)
395#define SET_TX_DESC_MCSG4_MAX_LEN(__txdesc, __value) \
396 SET_BITS_OFFSET_LE(__txdesc+28, 16, 4, __value)
397#define SET_TX_DESC_MCSG5_MAX_LEN(__txdesc, __value) \
398 SET_BITS_OFFSET_LE(__txdesc+28, 20, 4, __value)
399#define SET_TX_DESC_MCSG6_MAX_LEN(__txdesc, __value) \
400 SET_BITS_OFFSET_LE(__txdesc+28, 24, 4, __value)
401#define SET_TX_DESC_MCSG15_MAX_LEN(__txdesc, __value) \
402 SET_BITS_OFFSET_LE(__txdesc+28, 28, 4, __value)
403
404
405int rtl8192cu_endpoint_mapping(struct ieee80211_hw *hw);
406u16 rtl8192cu_mq_to_hwq(__le16 fc, u16 mac80211_queue_index);
407bool rtl92cu_rx_query_desc(struct ieee80211_hw *hw,
408 struct rtl_stats *stats,
409 struct ieee80211_rx_status *rx_status,
410 u8 *p_desc, struct sk_buff *skb);
411void rtl8192cu_rx_hdl(struct ieee80211_hw *hw, struct sk_buff * skb);
412void rtl8192c_rx_segregate_hdl(struct ieee80211_hw *, struct sk_buff *,
413 struct sk_buff_head *);
414void rtl8192c_tx_cleanup(struct ieee80211_hw *hw, struct sk_buff *skb);
415int rtl8192c_tx_post_hdl(struct ieee80211_hw *hw, struct urb *urb,
416 struct sk_buff *skb);
417struct sk_buff *rtl8192c_tx_aggregate_hdl(struct ieee80211_hw *,
418 struct sk_buff_head *);
419void rtl92cu_tx_fill_desc(struct ieee80211_hw *hw,
420 struct ieee80211_hdr *hdr, u8 *pdesc_tx,
421 struct ieee80211_tx_info *info, struct sk_buff *skb,
422 unsigned int queue_index);
423void rtl92cu_fill_fake_txdesc(struct ieee80211_hw *hw, u8 * pDesc,
424 u32 buffer_len, bool bIsPsPoll);
425void rtl92cu_tx_fill_cmddesc(struct ieee80211_hw *hw,
426 u8 *pdesc, bool b_firstseg,
427 bool b_lastseg, struct sk_buff *skb);
428bool rtl92cu_cmd_send_packet(struct ieee80211_hw *hw, struct sk_buff *skb);
429
430#endif
Linux kernel - Deliverables
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