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rtlwifi: rtl8192c: rtl8192ce: rtl8192cu: rtl8192de: rtl8723ae: Add changes required...
[deliverable/linux.git] / drivers / net / wireless / rtlwifi / rtl8192de / phy.c
CommitLineData
7274a8c2
CL		 1/******************************************************************************
2 *
6a57b08e 3 * Copyright(c) 2009-2012 Realtek Corporation.
7274a8c2
CL		 4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of version 2 of the GNU General Public License as
7 * published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details.
13 *
14 * You should have received a copy of the GNU General Public License along with
15 * this program; if not, write to the Free Software Foundation, Inc.,
16 * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
17 *
18 * The full GNU General Public License is included in this distribution in the
19 * file called LICENSE.
20 *
21 * Contact Information:
22 * wlanfae <wlanfae@realtek.com>
23 * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
24 * Hsinchu 300, Taiwan.
25 *
26 * Larry Finger <Larry.Finger@lwfinger.net>
27 *
28 *****************************************************************************/
29
30#include "../wifi.h"
31#include "../pci.h"
32#include "../ps.h"
33#include "reg.h"
34#include "def.h"
35#include "phy.h"
36#include "rf.h"
37#include "dm.h"
38#include "table.h"
39#include "sw.h"
40#include "hw.h"
41
42#define MAX_RF_IMR_INDEX 12
43#define MAX_RF_IMR_INDEX_NORMAL 13
44#define RF_REG_NUM_FOR_C_CUT_5G 6
45#define RF_REG_NUM_FOR_C_CUT_5G_INTERNALPA 7
46#define RF_REG_NUM_FOR_C_CUT_2G 5
47#define RF_CHNL_NUM_5G 19
48#define RF_CHNL_NUM_5G_40M 17
49#define TARGET_CHNL_NUM_5G 221
50#define TARGET_CHNL_NUM_2G 14
51#define CV_CURVE_CNT 64
52
53static u32 rf_reg_for_5g_swchnl_normal[MAX_RF_IMR_INDEX_NORMAL] = {
54 0, 0x2f, 0x30, 0x31, 0x32, 0x33, 0x34, 0x35, 0x36, 0x37, 0x38, 0x39, 0x0
55};
56
57static u8 rf_reg_for_c_cut_5g[RF_REG_NUM_FOR_C_CUT_5G] = {
58 RF_SYN_G1, RF_SYN_G2, RF_SYN_G3, RF_SYN_G4, RF_SYN_G5, RF_SYN_G6
59};
60
61static u8 rf_reg_for_c_cut_2g[RF_REG_NUM_FOR_C_CUT_2G] = {
62 RF_SYN_G1, RF_SYN_G2, RF_SYN_G3, RF_SYN_G7, RF_SYN_G8
63};
64
65static u8 rf_for_c_cut_5g_internal_pa[RF_REG_NUM_FOR_C_CUT_5G_INTERNALPA] = {
66 0x0B, 0x48, 0x49, 0x4B, 0x03, 0x04, 0x0E
67};
68
69static u32 rf_reg_mask_for_c_cut_2g[RF_REG_NUM_FOR_C_CUT_2G] = {
70 BIT(19) | BIT(18) | BIT(17) | BIT(14) | BIT(1),
71 BIT(10) | BIT(9),
72 BIT(18) | BIT(17) | BIT(16) | BIT(1),
73 BIT(2) | BIT(1),
74 BIT(15) | BIT(14) | BIT(13) | BIT(12) | BIT(11)
75};
76
77static u8 rf_chnl_5g[RF_CHNL_NUM_5G] = {
78 36, 40, 44, 48, 52, 56, 60, 64, 100, 104, 108,
79 112, 116, 120, 124, 128, 132, 136, 140
80};
81
82static u8 rf_chnl_5g_40m[RF_CHNL_NUM_5G_40M] = {
83 38, 42, 46, 50, 54, 58, 62, 102, 106, 110, 114,
84 118, 122, 126, 130, 134, 138
85};
86static u32 rf_reg_pram_c_5g[5][RF_REG_NUM_FOR_C_CUT_5G] = {
87 {0xE43BE, 0xFC638, 0x77C0A, 0xDE471, 0xd7110, 0x8EB04},
88 {0xE43BE, 0xFC078, 0xF7C1A, 0xE0C71, 0xD7550, 0xAEB04},
89 {0xE43BF, 0xFF038, 0xF7C0A, 0xDE471, 0xE5550, 0xAEB04},
90 {0xE43BF, 0xFF079, 0xF7C1A, 0xDE471, 0xE5550, 0xAEB04},
91 {0xE43BF, 0xFF038, 0xF7C1A, 0xDE471, 0xd7550, 0xAEB04}
92};
93
94static u32 rf_reg_param_for_c_cut_2g[3][RF_REG_NUM_FOR_C_CUT_2G] = {
95 {0x643BC, 0xFC038, 0x77C1A, 0x41289, 0x01840},
96 {0x643BC, 0xFC038, 0x07C1A, 0x41289, 0x01840},
97 {0x243BC, 0xFC438, 0x07C1A, 0x4128B, 0x0FC41}
98};
99
100static u32 rf_syn_g4_for_c_cut_2g = 0xD1C31 & 0x7FF;
101
102static u32 rf_pram_c_5g_int_pa[3][RF_REG_NUM_FOR_C_CUT_5G_INTERNALPA] = {
103 {0x01a00, 0x40443, 0x00eb5, 0x89bec, 0x94a12, 0x94a12, 0x94a12},
104 {0x01800, 0xc0443, 0x00730, 0x896ee, 0x94a52, 0x94a52, 0x94a52},
105 {0x01800, 0xc0443, 0x00730, 0x896ee, 0x94a12, 0x94a12, 0x94a12}
106};
107
108/* [mode][patha+b][reg] */
109static u32 rf_imr_param_normal[1][3][MAX_RF_IMR_INDEX_NORMAL] = {
110 {
111 /* channel 1-14. */
112 {
113 0x70000, 0x00ff0, 0x4400f, 0x00ff0, 0x0, 0x0, 0x0,
114 0x0, 0x0, 0x64888, 0xe266c, 0x00090, 0x22fff
115 },
116 /* path 36-64 */
117 {
118 0x70000, 0x22880, 0x4470f, 0x55880, 0x00070, 0x88000,
119 0x0, 0x88080, 0x70000, 0x64a82, 0xe466c, 0x00090,
120 0x32c9a
121 },
122 /* 100 -165 */
123 {
124 0x70000, 0x44880, 0x4477f, 0x77880, 0x00070, 0x88000,
125 0x0, 0x880b0, 0x0, 0x64b82, 0xe466c, 0x00090, 0x32c9a
126 }
127 }
128};
129
130static u32 curveindex_5g[TARGET_CHNL_NUM_5G] = {0};
131
132static u32 curveindex_2g[TARGET_CHNL_NUM_2G] = {0};
133
134static u32 targetchnl_5g[TARGET_CHNL_NUM_5G] = {
135 25141, 25116, 25091, 25066, 25041,
136 25016, 24991, 24966, 24941, 24917,
137 24892, 24867, 24843, 24818, 24794,
138 24770, 24765, 24721, 24697, 24672,
139 24648, 24624, 24600, 24576, 24552,
140 24528, 24504, 24480, 24457, 24433,
141 24409, 24385, 24362, 24338, 24315,
142 24291, 24268, 24245, 24221, 24198,
143 24175, 24151, 24128, 24105, 24082,
144 24059, 24036, 24013, 23990, 23967,
145 23945, 23922, 23899, 23876, 23854,
146 23831, 23809, 23786, 23764, 23741,
147 23719, 23697, 23674, 23652, 23630,
148 23608, 23586, 23564, 23541, 23519,
149 23498, 23476, 23454, 23432, 23410,
150 23388, 23367, 23345, 23323, 23302,
151 23280, 23259, 23237, 23216, 23194,
152 23173, 23152, 23130, 23109, 23088,
153 23067, 23046, 23025, 23003, 22982,
154 22962, 22941, 22920, 22899, 22878,
155 22857, 22837, 22816, 22795, 22775,
156 22754, 22733, 22713, 22692, 22672,
157 22652, 22631, 22611, 22591, 22570,
158 22550, 22530, 22510, 22490, 22469,
159 22449, 22429, 22409, 22390, 22370,
160 22350, 22336, 22310, 22290, 22271,
161 22251, 22231, 22212, 22192, 22173,
162 22153, 22134, 22114, 22095, 22075,
163 22056, 22037, 22017, 21998, 21979,
164 21960, 21941, 21921, 21902, 21883,
165 21864, 21845, 21826, 21807, 21789,
166 21770, 21751, 21732, 21713, 21695,
167 21676, 21657, 21639, 21620, 21602,
168 21583, 21565, 21546, 21528, 21509,
169 21491, 21473, 21454, 21436, 21418,
170 21400, 21381, 21363, 21345, 21327,
171 21309, 21291, 21273, 21255, 21237,
172 21219, 21201, 21183, 21166, 21148,
173 21130, 21112, 21095, 21077, 21059,
174 21042, 21024, 21007, 20989, 20972,
175 25679, 25653, 25627, 25601, 25575,
176 25549, 25523, 25497, 25471, 25446,
177 25420, 25394, 25369, 25343, 25318,
178 25292, 25267, 25242, 25216, 25191,
179 25166
180};
181
182/* channel 1~14 */
183static u32 targetchnl_2g[TARGET_CHNL_NUM_2G] = {
184 26084, 26030, 25976, 25923, 25869, 25816, 25764,
185 25711, 25658, 25606, 25554, 25502, 25451, 25328
186};
187
188static u32 _rtl92d_phy_calculate_bit_shift(u32 bitmask)
189{
190 u32 i;
191
192 for (i = 0; i <= 31; i++) {
193 if (((bitmask >> i) & 0x1) == 1)
194 break;
195 }
196
197 return i;
198}
199
200u32 rtl92d_phy_query_bb_reg(struct ieee80211_hw *hw, u32 regaddr, u32 bitmask)
201{
202 struct rtl_priv *rtlpriv = rtl_priv(hw);
203 struct rtl_hal *rtlhal = rtl_hal(rtlpriv);
204 u32 returnvalue, originalvalue, bitshift;
205 u8 dbi_direct;
206
f30d7507
JP		 207 RT_TRACE(rtlpriv, COMP_RF, DBG_TRACE, "regaddr(%#x), bitmask(%#x)\n",
208 regaddr, bitmask);
7274a8c2
CL		 209 if (rtlhal->during_mac1init_radioa || rtlhal->during_mac0init_radiob) {
210 /* mac1 use phy0 read radio_b. */
211 /* mac0 use phy1 read radio_b. */
212 if (rtlhal->during_mac1init_radioa)
213 dbi_direct = BIT(3);
214 else if (rtlhal->during_mac0init_radiob)
215 dbi_direct = BIT(3) | BIT(2);
216 originalvalue = rtl92de_read_dword_dbi(hw, (u16)regaddr,
217 dbi_direct);
218 } else {
219 originalvalue = rtl_read_dword(rtlpriv, regaddr);
220 }
221 bitshift = _rtl92d_phy_calculate_bit_shift(bitmask);
222 returnvalue = (originalvalue & bitmask) >> bitshift;
f30d7507
JP		 223 RT_TRACE(rtlpriv, COMP_RF, DBG_TRACE,
224 "BBR MASK=0x%x Addr[0x%x]=0x%x\n",
225 bitmask, regaddr, originalvalue);
7274a8c2
CL		 226 return returnvalue;
227}
228
229void rtl92d_phy_set_bb_reg(struct ieee80211_hw *hw,
230 u32 regaddr, u32 bitmask, u32 data)
231{
232 struct rtl_priv *rtlpriv = rtl_priv(hw);
233 struct rtl_hal *rtlhal = rtl_hal(rtlpriv);
234 u8 dbi_direct = 0;
235 u32 originalvalue, bitshift;
236
f30d7507
JP		 237 RT_TRACE(rtlpriv, COMP_RF, DBG_TRACE,
238 "regaddr(%#x), bitmask(%#x), data(%#x)\n",
239 regaddr, bitmask, data);
7274a8c2
CL		 240 if (rtlhal->during_mac1init_radioa)
241 dbi_direct = BIT(3);
242 else if (rtlhal->during_mac0init_radiob)
243 /* mac0 use phy1 write radio_b. */
244 dbi_direct = BIT(3) | BIT(2);
245 if (bitmask != BMASKDWORD) {
246 if (rtlhal->during_mac1init_radioa ||
247 rtlhal->during_mac0init_radiob)
248 originalvalue = rtl92de_read_dword_dbi(hw,
249 (u16) regaddr,
250 dbi_direct);
251 else
252 originalvalue = rtl_read_dword(rtlpriv, regaddr);
253 bitshift = _rtl92d_phy_calculate_bit_shift(bitmask);
254 data = ((originalvalue & (~bitmask)) | (data << bitshift));
255 }
256 if (rtlhal->during_mac1init_radioa || rtlhal->during_mac0init_radiob)
257 rtl92de_write_dword_dbi(hw, (u16) regaddr, data, dbi_direct);
258 else
259 rtl_write_dword(rtlpriv, regaddr, data);
f30d7507
JP		 260 RT_TRACE(rtlpriv, COMP_RF, DBG_TRACE,
261 "regaddr(%#x), bitmask(%#x), data(%#x)\n",
262 regaddr, bitmask, data);
7274a8c2
CL		 263}
264
265static u32 _rtl92d_phy_rf_serial_read(struct ieee80211_hw *hw,
266 enum radio_path rfpath, u32 offset)
267{
268
269 struct rtl_priv *rtlpriv = rtl_priv(hw);
270 struct rtl_phy *rtlphy = &(rtlpriv->phy);
271 struct bb_reg_def *pphyreg = &rtlphy->phyreg_def[rfpath];
272 u32 newoffset;
273 u32 tmplong, tmplong2;
274 u8 rfpi_enable = 0;
275 u32 retvalue;
276
277 newoffset = offset;
278 tmplong = rtl_get_bbreg(hw, RFPGA0_XA_HSSIPARAMETER2, BMASKDWORD);
279 if (rfpath == RF90_PATH_A)
280 tmplong2 = tmplong;
281 else
282 tmplong2 = rtl_get_bbreg(hw, pphyreg->rfhssi_para2, BMASKDWORD);
283 tmplong2 = (tmplong2 & (~BLSSIREADADDRESS)) |
284 (newoffset << 23) | BLSSIREADEDGE;
285 rtl_set_bbreg(hw, RFPGA0_XA_HSSIPARAMETER2, BMASKDWORD,
286 tmplong & (~BLSSIREADEDGE));
287 udelay(10);
288 rtl_set_bbreg(hw, pphyreg->rfhssi_para2, BMASKDWORD, tmplong2);
289 udelay(50);
290 udelay(50);
291 rtl_set_bbreg(hw, RFPGA0_XA_HSSIPARAMETER2, BMASKDWORD,
292 tmplong | BLSSIREADEDGE);
293 udelay(10);
294 if (rfpath == RF90_PATH_A)
295 rfpi_enable = (u8) rtl_get_bbreg(hw, RFPGA0_XA_HSSIPARAMETER1,
296 BIT(8));
297 else if (rfpath == RF90_PATH_B)
298 rfpi_enable = (u8) rtl_get_bbreg(hw, RFPGA0_XB_HSSIPARAMETER1,
299 BIT(8));
300 if (rfpi_enable)
da17fcff 301 retvalue = rtl_get_bbreg(hw, pphyreg->rf_rbpi,
7274a8c2
CL		 302 BLSSIREADBACKDATA);
303 else
da17fcff 304 retvalue = rtl_get_bbreg(hw, pphyreg->rf_rb,
7274a8c2 305 BLSSIREADBACKDATA);
f30d7507 306 RT_TRACE(rtlpriv, COMP_RF, DBG_TRACE, "RFR-%d Addr[0x%x] = 0x%x\n",
da17fcff 307 rfpath, pphyreg->rf_rb, retvalue);
7274a8c2
CL		 308 return retvalue;
309}
310
311static void _rtl92d_phy_rf_serial_write(struct ieee80211_hw *hw,
312 enum radio_path rfpath,
313 u32 offset, u32 data)
314{
315 u32 data_and_addr;
316 u32 newoffset;
317 struct rtl_priv *rtlpriv = rtl_priv(hw);
318 struct rtl_phy *rtlphy = &(rtlpriv->phy);
319 struct bb_reg_def *pphyreg = &rtlphy->phyreg_def[rfpath];
320
321 newoffset = offset;
322 /* T65 RF */
323 data_and_addr = ((newoffset << 20) | (data & 0x000fffff)) & 0x0fffffff;
324 rtl_set_bbreg(hw, pphyreg->rf3wire_offset, BMASKDWORD, data_and_addr);
f30d7507
JP		 325 RT_TRACE(rtlpriv, COMP_RF, DBG_TRACE, "RFW-%d Addr[0x%x]=0x%x\n",
326 rfpath, pphyreg->rf3wire_offset, data_and_addr);
7274a8c2
CL		 327}
328
329u32 rtl92d_phy_query_rf_reg(struct ieee80211_hw *hw,
330 enum radio_path rfpath, u32 regaddr, u32 bitmask)
331{
332 struct rtl_priv *rtlpriv = rtl_priv(hw);
333 u32 original_value, readback_value, bitshift;
334 unsigned long flags;
335
f30d7507
JP		 336 RT_TRACE(rtlpriv, COMP_RF, DBG_TRACE,
337 "regaddr(%#x), rfpath(%#x), bitmask(%#x)\n",
338 regaddr, rfpath, bitmask);
7274a8c2
CL		 339 spin_lock_irqsave(&rtlpriv->locks.rf_lock, flags);
340 original_value = _rtl92d_phy_rf_serial_read(hw, rfpath, regaddr);
341 bitshift = _rtl92d_phy_calculate_bit_shift(bitmask);
342 readback_value = (original_value & bitmask) >> bitshift;
343 spin_unlock_irqrestore(&rtlpriv->locks.rf_lock, flags);
f30d7507
JP		 344 RT_TRACE(rtlpriv, COMP_RF, DBG_TRACE,
345 "regaddr(%#x), rfpath(%#x), bitmask(%#x), original_value(%#x)\n",
346 regaddr, rfpath, bitmask, original_value);
7274a8c2
CL		 347 return readback_value;
348}
349
350void rtl92d_phy_set_rf_reg(struct ieee80211_hw *hw, enum radio_path rfpath,
351 u32 regaddr, u32 bitmask, u32 data)
352{
353 struct rtl_priv *rtlpriv = rtl_priv(hw);
354 struct rtl_phy *rtlphy = &(rtlpriv->phy);
355 u32 original_value, bitshift;
356 unsigned long flags;
357
358 RT_TRACE(rtlpriv, COMP_RF, DBG_TRACE,
f30d7507
JP		 359 "regaddr(%#x), bitmask(%#x), data(%#x), rfpath(%#x)\n",
360 regaddr, bitmask, data, rfpath);
7274a8c2
CL		 361 if (bitmask == 0)
362 return;
363 spin_lock_irqsave(&rtlpriv->locks.rf_lock, flags);
364 if (rtlphy->rf_mode != RF_OP_BY_FW) {
365 if (bitmask != BRFREGOFFSETMASK) {
366 original_value = _rtl92d_phy_rf_serial_read(hw,
367 rfpath, regaddr);
368 bitshift = _rtl92d_phy_calculate_bit_shift(bitmask);
369 data = ((original_value & (~bitmask)) |
370 (data << bitshift));
371 }
372 _rtl92d_phy_rf_serial_write(hw, rfpath, regaddr, data);
373 }
374 spin_unlock_irqrestore(&rtlpriv->locks.rf_lock, flags);
f30d7507
JP		 375 RT_TRACE(rtlpriv, COMP_RF, DBG_TRACE,
376 "regaddr(%#x), bitmask(%#x), data(%#x), rfpath(%#x)\n",
377 regaddr, bitmask, data, rfpath);
7274a8c2
CL		 378}
379
380bool rtl92d_phy_mac_config(struct ieee80211_hw *hw)
381{
382 struct rtl_priv *rtlpriv = rtl_priv(hw);
383 u32 i;
384 u32 arraylength;
385 u32 *ptrarray;
386
f30d7507 387 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE, "Read Rtl819XMACPHY_Array\n");
7274a8c2
CL		 388 arraylength = MAC_2T_ARRAYLENGTH;
389 ptrarray = rtl8192de_mac_2tarray;
f30d7507 390 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE, "Img:Rtl819XMAC_Array\n");
7274a8c2
CL		 391 for (i = 0; i < arraylength; i = i + 2)
392 rtl_write_byte(rtlpriv, ptrarray[i], (u8) ptrarray[i + 1]);
393 if (rtlpriv->rtlhal.macphymode == SINGLEMAC_SINGLEPHY) {
394 /* improve 2-stream TX EVM */
395 /* rtl_write_byte(rtlpriv, 0x14,0x71); */
396 /* AMPDU aggregation number 9 */
397 /* rtl_write_word(rtlpriv, REG_MAX_AGGR_NUM, MAX_AGGR_NUM); */
398 rtl_write_byte(rtlpriv, REG_MAX_AGGR_NUM, 0x0B);
399 } else {
400 /* 92D need to test to decide the num. */
401 rtl_write_byte(rtlpriv, REG_MAX_AGGR_NUM, 0x07);
402 }
403 return true;
404}
405
406static void _rtl92d_phy_init_bb_rf_register_definition(struct ieee80211_hw *hw)
407{
408 struct rtl_priv *rtlpriv = rtl_priv(hw);
409 struct rtl_phy *rtlphy = &(rtlpriv->phy);
410
411 /* RF Interface Sowrtware Control */
412 /* 16 LSBs if read 32-bit from 0x870 */
413 rtlphy->phyreg_def[RF90_PATH_A].rfintfs = RFPGA0_XAB_RFINTERFACESW;
414 /* 16 MSBs if read 32-bit from 0x870 (16-bit for 0x872) */
415 rtlphy->phyreg_def[RF90_PATH_B].rfintfs = RFPGA0_XAB_RFINTERFACESW;
416 /* 16 LSBs if read 32-bit from 0x874 */
417 rtlphy->phyreg_def[RF90_PATH_C].rfintfs = RFPGA0_XCD_RFINTERFACESW;
418 /* 16 MSBs if read 32-bit from 0x874 (16-bit for 0x876) */
419
420 rtlphy->phyreg_def[RF90_PATH_D].rfintfs = RFPGA0_XCD_RFINTERFACESW;
421 /* RF Interface Readback Value */
422 /* 16 LSBs if read 32-bit from 0x8E0 */
423 rtlphy->phyreg_def[RF90_PATH_A].rfintfi = RFPGA0_XAB_RFINTERFACERB;
424 /* 16 MSBs if read 32-bit from 0x8E0 (16-bit for 0x8E2) */
425 rtlphy->phyreg_def[RF90_PATH_B].rfintfi = RFPGA0_XAB_RFINTERFACERB;
426 /* 16 LSBs if read 32-bit from 0x8E4 */
427 rtlphy->phyreg_def[RF90_PATH_C].rfintfi = RFPGA0_XCD_RFINTERFACERB;
428 /* 16 MSBs if read 32-bit from 0x8E4 (16-bit for 0x8E6) */
429 rtlphy->phyreg_def[RF90_PATH_D].rfintfi = RFPGA0_XCD_RFINTERFACERB;
430
431 /* RF Interface Output (and Enable) */
432 /* 16 LSBs if read 32-bit from 0x860 */
433 rtlphy->phyreg_def[RF90_PATH_A].rfintfo = RFPGA0_XA_RFINTERFACEOE;
434 /* 16 LSBs if read 32-bit from 0x864 */
435 rtlphy->phyreg_def[RF90_PATH_B].rfintfo = RFPGA0_XB_RFINTERFACEOE;
436
437 /* RF Interface (Output and) Enable */
438 /* 16 MSBs if read 32-bit from 0x860 (16-bit for 0x862) */
439 rtlphy->phyreg_def[RF90_PATH_A].rfintfe = RFPGA0_XA_RFINTERFACEOE;
440 /* 16 MSBs if read 32-bit from 0x864 (16-bit for 0x866) */
441 rtlphy->phyreg_def[RF90_PATH_B].rfintfe = RFPGA0_XB_RFINTERFACEOE;
442
443 /* Addr of LSSI. Wirte RF register by driver */
444 /* LSSI Parameter */
445 rtlphy->phyreg_def[RF90_PATH_A].rf3wire_offset =
446 RFPGA0_XA_LSSIPARAMETER;
447 rtlphy->phyreg_def[RF90_PATH_B].rf3wire_offset =
448 RFPGA0_XB_LSSIPARAMETER;
449
450 /* RF parameter */
451 /* BB Band Select */
452 rtlphy->phyreg_def[RF90_PATH_A].rflssi_select = RFPGA0_XAB_RFPARAMETER;
453 rtlphy->phyreg_def[RF90_PATH_B].rflssi_select = RFPGA0_XAB_RFPARAMETER;
454 rtlphy->phyreg_def[RF90_PATH_C].rflssi_select = RFPGA0_XCD_RFPARAMETER;
455 rtlphy->phyreg_def[RF90_PATH_D].rflssi_select = RFPGA0_XCD_RFPARAMETER;
456
457 /* Tx AGC Gain Stage (same for all path. Should we remove this?) */
458 /* Tx gain stage */
459 rtlphy->phyreg_def[RF90_PATH_A].rftxgain_stage = RFPGA0_TXGAINSTAGE;
460 /* Tx gain stage */
461 rtlphy->phyreg_def[RF90_PATH_B].rftxgain_stage = RFPGA0_TXGAINSTAGE;
462 /* Tx gain stage */
463 rtlphy->phyreg_def[RF90_PATH_C].rftxgain_stage = RFPGA0_TXGAINSTAGE;
464 /* Tx gain stage */
465 rtlphy->phyreg_def[RF90_PATH_D].rftxgain_stage = RFPGA0_TXGAINSTAGE;
466
467 /* Tranceiver A~D HSSI Parameter-1 */
468 /* wire control parameter1 */
469 rtlphy->phyreg_def[RF90_PATH_A].rfhssi_para1 = RFPGA0_XA_HSSIPARAMETER1;
470 /* wire control parameter1 */
471 rtlphy->phyreg_def[RF90_PATH_B].rfhssi_para1 = RFPGA0_XB_HSSIPARAMETER1;
472
473 /* Tranceiver A~D HSSI Parameter-2 */
474 /* wire control parameter2 */
475 rtlphy->phyreg_def[RF90_PATH_A].rfhssi_para2 = RFPGA0_XA_HSSIPARAMETER2;
476 /* wire control parameter2 */
477 rtlphy->phyreg_def[RF90_PATH_B].rfhssi_para2 = RFPGA0_XB_HSSIPARAMETER2;
478
479 /* RF switch Control */
480 /* TR/Ant switch control */
da17fcff
LF		 481 rtlphy->phyreg_def[RF90_PATH_A].rfsw_ctrl = RFPGA0_XAB_SWITCHCONTROL;
482 rtlphy->phyreg_def[RF90_PATH_B].rfsw_ctrl = RFPGA0_XAB_SWITCHCONTROL;
483 rtlphy->phyreg_def[RF90_PATH_C].rfsw_ctrl = RFPGA0_XCD_SWITCHCONTROL;
484 rtlphy->phyreg_def[RF90_PATH_D].rfsw_ctrl = RFPGA0_XCD_SWITCHCONTROL;
7274a8c2
CL		 485
486 /* AGC control 1 */
487 rtlphy->phyreg_def[RF90_PATH_A].rfagc_control1 = ROFDM0_XAAGCCORE1;
488 rtlphy->phyreg_def[RF90_PATH_B].rfagc_control1 = ROFDM0_XBAGCCORE1;
489 rtlphy->phyreg_def[RF90_PATH_C].rfagc_control1 = ROFDM0_XCAGCCORE1;
490 rtlphy->phyreg_def[RF90_PATH_D].rfagc_control1 = ROFDM0_XDAGCCORE1;
491
492 /* AGC control 2 */
493 rtlphy->phyreg_def[RF90_PATH_A].rfagc_control2 = ROFDM0_XAAGCCORE2;
494 rtlphy->phyreg_def[RF90_PATH_B].rfagc_control2 = ROFDM0_XBAGCCORE2;
495 rtlphy->phyreg_def[RF90_PATH_C].rfagc_control2 = ROFDM0_XCAGCCORE2;
496 rtlphy->phyreg_def[RF90_PATH_D].rfagc_control2 = ROFDM0_XDAGCCORE2;
497
498 /* RX AFE control 1 */
da17fcff
LF		 499 rtlphy->phyreg_def[RF90_PATH_A].rfrxiq_imbal = ROFDM0_XARXIQIMBALANCE;
500 rtlphy->phyreg_def[RF90_PATH_B].rfrxiq_imbal = ROFDM0_XBRXIQIMBALANCE;
501 rtlphy->phyreg_def[RF90_PATH_C].rfrxiq_imbal = ROFDM0_XCRXIQIMBALANCE;
502 rtlphy->phyreg_def[RF90_PATH_D].rfrxiq_imbal = ROFDM0_XDRXIQIMBALANCE;
7274a8c2
CL		 503
504 /*RX AFE control 1 */
505 rtlphy->phyreg_def[RF90_PATH_A].rfrx_afe = ROFDM0_XARXAFE;
506 rtlphy->phyreg_def[RF90_PATH_B].rfrx_afe = ROFDM0_XBRXAFE;
507 rtlphy->phyreg_def[RF90_PATH_C].rfrx_afe = ROFDM0_XCRXAFE;
508 rtlphy->phyreg_def[RF90_PATH_D].rfrx_afe = ROFDM0_XDRXAFE;
509
510 /* Tx AFE control 1 */
da17fcff
LF		 511 rtlphy->phyreg_def[RF90_PATH_A].rftxiq_imbal = ROFDM0_XATxIQIMBALANCE;
512 rtlphy->phyreg_def[RF90_PATH_B].rftxiq_imbal = ROFDM0_XBTxIQIMBALANCE;
513 rtlphy->phyreg_def[RF90_PATH_C].rftxiq_imbal = ROFDM0_XCTxIQIMBALANCE;
514 rtlphy->phyreg_def[RF90_PATH_D].rftxiq_imbal = ROFDM0_XDTxIQIMBALANCE;
7274a8c2
CL		 515
516 /* Tx AFE control 2 */
517 rtlphy->phyreg_def[RF90_PATH_A].rftx_afe = ROFDM0_XATxAFE;
518 rtlphy->phyreg_def[RF90_PATH_B].rftx_afe = ROFDM0_XBTxAFE;
519 rtlphy->phyreg_def[RF90_PATH_C].rftx_afe = ROFDM0_XCTxAFE;
520 rtlphy->phyreg_def[RF90_PATH_D].rftx_afe = ROFDM0_XDTxAFE;
521
522 /* Tranceiver LSSI Readback SI mode */
da17fcff
LF		 523 rtlphy->phyreg_def[RF90_PATH_A].rf_rb = RFPGA0_XA_LSSIREADBACK;
524 rtlphy->phyreg_def[RF90_PATH_B].rf_rb = RFPGA0_XB_LSSIREADBACK;
525 rtlphy->phyreg_def[RF90_PATH_C].rf_rb = RFPGA0_XC_LSSIREADBACK;
526 rtlphy->phyreg_def[RF90_PATH_D].rf_rb = RFPGA0_XD_LSSIREADBACK;
7274a8c2
CL		 527
528 /* Tranceiver LSSI Readback PI mode */
da17fcff
LF		 529 rtlphy->phyreg_def[RF90_PATH_A].rf_rbpi = TRANSCEIVERA_HSPI_READBACK;
530 rtlphy->phyreg_def[RF90_PATH_B].rf_rbpi = TRANSCEIVERB_HSPI_READBACK;
7274a8c2
CL		 531}
532
533static bool _rtl92d_phy_config_bb_with_headerfile(struct ieee80211_hw *hw,
534 u8 configtype)
535{
536 int i;
537 u32 *phy_regarray_table;
538 u32 *agctab_array_table = NULL;
539 u32 *agctab_5garray_table;
540 u16 phy_reg_arraylen, agctab_arraylen = 0, agctab_5garraylen;
541 struct rtl_priv *rtlpriv = rtl_priv(hw);
542 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
543
544 /* Normal chip,Mac0 use AGC_TAB.txt for 2G and 5G band. */
545 if (rtlhal->interfaceindex == 0) {
546 agctab_arraylen = AGCTAB_ARRAYLENGTH;
547 agctab_array_table = rtl8192de_agctab_array;
548 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
f30d7507 549 " ===> phy:MAC0, Rtl819XAGCTAB_Array\n");
7274a8c2
CL		 550 } else {
551 if (rtlhal->current_bandtype == BAND_ON_2_4G) {
552 agctab_arraylen = AGCTAB_2G_ARRAYLENGTH;
553 agctab_array_table = rtl8192de_agctab_2garray;
554 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
f30d7507 555 " ===> phy:MAC1, Rtl819XAGCTAB_2GArray\n");
7274a8c2
CL		 556 } else {
557 agctab_5garraylen = AGCTAB_5G_ARRAYLENGTH;
558 agctab_5garray_table = rtl8192de_agctab_5garray;
559 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
f30d7507 560 " ===> phy:MAC1, Rtl819XAGCTAB_5GArray\n");
7274a8c2
CL		 561
562 }
563 }
564 phy_reg_arraylen = PHY_REG_2T_ARRAYLENGTH;
565 phy_regarray_table = rtl8192de_phy_reg_2tarray;
566 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
f30d7507 567 " ===> phy:Rtl819XPHY_REG_Array_PG\n");
7274a8c2
CL		 568 if (configtype == BASEBAND_CONFIG_PHY_REG) {
569 for (i = 0; i < phy_reg_arraylen; i = i + 2) {
570 if (phy_regarray_table[i] == 0xfe)
571 mdelay(50);
572 else if (phy_regarray_table[i] == 0xfd)
573 mdelay(5);
574 else if (phy_regarray_table[i] == 0xfc)
575 mdelay(1);
576 else if (phy_regarray_table[i] == 0xfb)
577 udelay(50);
578 else if (phy_regarray_table[i] == 0xfa)
579 udelay(5);
580 else if (phy_regarray_table[i] == 0xf9)
581 udelay(1);
582 rtl_set_bbreg(hw, phy_regarray_table[i], BMASKDWORD,
583 phy_regarray_table[i + 1]);
584 udelay(1);
585 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
f30d7507
JP		 586 "The phy_regarray_table[0] is %x Rtl819XPHY_REGArray[1] is %x\n",
587 phy_regarray_table[i],
588 phy_regarray_table[i + 1]);
7274a8c2
CL		 589 }
590 } else if (configtype == BASEBAND_CONFIG_AGC_TAB) {
591 if (rtlhal->interfaceindex == 0) {
592 for (i = 0; i < agctab_arraylen; i = i + 2) {
593 rtl_set_bbreg(hw, agctab_array_table[i],
594 BMASKDWORD,
595 agctab_array_table[i + 1]);
596 /* Add 1us delay between BB/RF register
597 * setting. */
598 udelay(1);
599 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
f30d7507 600 "The Rtl819XAGCTAB_Array_Table[0] is %ul Rtl819XPHY_REGArray[1] is %ul\n",
7274a8c2 601 agctab_array_table[i],
f30d7507 602 agctab_array_table[i + 1]);
7274a8c2
CL		 603 }
604 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
f30d7507 605 "Normal Chip, MAC0, load Rtl819XAGCTAB_Array\n");
7274a8c2
CL		 606 } else {
607 if (rtlhal->current_bandtype == BAND_ON_2_4G) {
608 for (i = 0; i < agctab_arraylen; i = i + 2) {
609 rtl_set_bbreg(hw, agctab_array_table[i],
610 BMASKDWORD,
611 agctab_array_table[i + 1]);
612 /* Add 1us delay between BB/RF register
613 * setting. */
614 udelay(1);
615 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
f30d7507 616 "The Rtl819XAGCTAB_Array_Table[0] is %ul Rtl819XPHY_REGArray[1] is %ul\n",
7274a8c2 617 agctab_array_table[i],
f30d7507 618 agctab_array_table[i + 1]);
7274a8c2
CL		 619 }
620 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
f30d7507 621 "Load Rtl819XAGCTAB_2GArray\n");
7274a8c2
CL		 622 } else {
623 for (i = 0; i < agctab_5garraylen; i = i + 2) {
624 rtl_set_bbreg(hw,
625 agctab_5garray_table[i],
626 BMASKDWORD,
627 agctab_5garray_table[i + 1]);
628 /* Add 1us delay between BB/RF registeri
629 * setting. */
630 udelay(1);
631 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
f30d7507 632 "The Rtl819XAGCTAB_5GArray_Table[0] is %ul Rtl819XPHY_REGArray[1] is %ul\n",
7274a8c2 633 agctab_5garray_table[i],
f30d7507 634 agctab_5garray_table[i + 1]);
7274a8c2
CL		 635 }
636 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
f30d7507 637 "Load Rtl819XAGCTAB_5GArray\n");
7274a8c2
CL		 638 }
639 }
640 }
641 return true;
642}
643
644static void _rtl92d_store_pwrindex_diffrate_offset(struct ieee80211_hw *hw,
645 u32 regaddr, u32 bitmask,
646 u32 data)
647{
648 struct rtl_priv *rtlpriv = rtl_priv(hw);
649 struct rtl_phy *rtlphy = &(rtlpriv->phy);
02b6ab0a
LF		 650 int index;
651
652 if (regaddr == RTXAGC_A_RATE18_06)
653 index = 0;
654 else if (regaddr == RTXAGC_A_RATE54_24)
655 index = 1;
656 else if (regaddr == RTXAGC_A_CCK1_MCS32)
657 index = 6;
658 else if (regaddr == RTXAGC_B_CCK11_A_CCK2_11 && bitmask == 0xffffff00)
659 index = 7;
660 else if (regaddr == RTXAGC_A_MCS03_MCS00)
661 index = 2;
662 else if (regaddr == RTXAGC_A_MCS07_MCS04)
663 index = 3;
664 else if (regaddr == RTXAGC_A_MCS11_MCS08)
665 index = 4;
666 else if (regaddr == RTXAGC_A_MCS15_MCS12)
667 index = 5;
668 else if (regaddr == RTXAGC_B_RATE18_06)
669 index = 8;
670 else if (regaddr == RTXAGC_B_RATE54_24)
671 index = 9;
672 else if (regaddr == RTXAGC_B_CCK1_55_MCS32)
673 index = 14;
674 else if (regaddr == RTXAGC_B_CCK11_A_CCK2_11 && bitmask == 0x000000ff)
675 index = 15;
676 else if (regaddr == RTXAGC_B_MCS03_MCS00)
677 index = 10;
678 else if (regaddr == RTXAGC_B_MCS07_MCS04)
679 index = 11;
680 else if (regaddr == RTXAGC_B_MCS11_MCS08)
681 index = 12;
682 else if (regaddr == RTXAGC_B_MCS15_MCS12)
683 index = 13;
684 else
685 return;
7274a8c2 686
da17fcff 687 rtlphy->mcs_offset[rtlphy->pwrgroup_cnt][index] = data;
02b6ab0a
LF		 688 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
689 "MCSTxPowerLevelOriginalOffset[%d][%d] = 0x%ulx\n",
690 rtlphy->pwrgroup_cnt, index,
da17fcff 691 rtlphy->mcs_offset[rtlphy->pwrgroup_cnt][index]);
02b6ab0a 692 if (index == 13)
7274a8c2 693 rtlphy->pwrgroup_cnt++;
7274a8c2
CL		 694}
695
696static bool _rtl92d_phy_config_bb_with_pgheaderfile(struct ieee80211_hw *hw,
697 u8 configtype)
698{
699 struct rtl_priv *rtlpriv = rtl_priv(hw);
700 int i;
701 u32 *phy_regarray_table_pg;
702 u16 phy_regarray_pg_len;
703
704 phy_regarray_pg_len = PHY_REG_ARRAY_PG_LENGTH;
705 phy_regarray_table_pg = rtl8192de_phy_reg_array_pg;
706 if (configtype == BASEBAND_CONFIG_PHY_REG) {
707 for (i = 0; i < phy_regarray_pg_len; i = i + 3) {
708 if (phy_regarray_table_pg[i] == 0xfe)
709 mdelay(50);
710 else if (phy_regarray_table_pg[i] == 0xfd)
711 mdelay(5);
712 else if (phy_regarray_table_pg[i] == 0xfc)
713 mdelay(1);
714 else if (phy_regarray_table_pg[i] == 0xfb)
715 udelay(50);
716 else if (phy_regarray_table_pg[i] == 0xfa)
717 udelay(5);
718 else if (phy_regarray_table_pg[i] == 0xf9)
719 udelay(1);
720 _rtl92d_store_pwrindex_diffrate_offset(hw,
721 phy_regarray_table_pg[i],
722 phy_regarray_table_pg[i + 1],
723 phy_regarray_table_pg[i + 2]);
724 }
725 } else {
726 RT_TRACE(rtlpriv, COMP_SEND, DBG_TRACE,
f30d7507 727 "configtype != BaseBand_Config_PHY_REG\n");
7274a8c2
CL		 728 }
729 return true;
730}
731
732static bool _rtl92d_phy_bb_config(struct ieee80211_hw *hw)
733{
734 struct rtl_priv *rtlpriv = rtl_priv(hw);
735 struct rtl_phy *rtlphy = &(rtlpriv->phy);
736 struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
737 bool rtstatus = true;
738
f30d7507 739 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE, "==>\n");
7274a8c2
CL		 740 rtstatus = _rtl92d_phy_config_bb_with_headerfile(hw,
741 BASEBAND_CONFIG_PHY_REG);
23677ce3 742 if (!rtstatus) {
f30d7507 743 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG, "Write BB Reg Fail!!\n");
7274a8c2
CL		 744 return false;
745 }
746
747 /* if (rtlphy->rf_type == RF_1T2R) {
748 * _rtl92c_phy_bb_config_1t(hw);
f30d7507 749 * RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE, "Config to 1T!!\n");
7274a8c2
CL		 750 *} */
751
752 if (rtlefuse->autoload_failflag == false) {
753 rtlphy->pwrgroup_cnt = 0;
754 rtstatus = _rtl92d_phy_config_bb_with_pgheaderfile(hw,
755 BASEBAND_CONFIG_PHY_REG);
756 }
23677ce3 757 if (!rtstatus) {
f30d7507 758 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG, "BB_PG Reg Fail!!\n");
7274a8c2
CL		 759 return false;
760 }
761 rtstatus = _rtl92d_phy_config_bb_with_headerfile(hw,
762 BASEBAND_CONFIG_AGC_TAB);
23677ce3 763 if (!rtstatus) {
f30d7507 764 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG, "AGC Table Fail\n");
7274a8c2
CL		 765 return false;
766 }
767 rtlphy->cck_high_power = (bool) (rtl_get_bbreg(hw,
768 RFPGA0_XA_HSSIPARAMETER2, 0x200));
769
770 return true;
771}
772
773bool rtl92d_phy_bb_config(struct ieee80211_hw *hw)
774{
775 struct rtl_priv *rtlpriv = rtl_priv(hw);
776 u16 regval;
777 u32 regvaldw;
778 u8 value;
779
780 _rtl92d_phy_init_bb_rf_register_definition(hw);
781 regval = rtl_read_word(rtlpriv, REG_SYS_FUNC_EN);
782 rtl_write_word(rtlpriv, REG_SYS_FUNC_EN,
783 regval | BIT(13) | BIT(0) | BIT(1));
784 rtl_write_byte(rtlpriv, REG_AFE_PLL_CTRL, 0x83);
785 rtl_write_byte(rtlpriv, REG_AFE_PLL_CTRL + 1, 0xdb);
786 /* 0x1f bit7 bit6 represent for mac0/mac1 driver ready */
787 value = rtl_read_byte(rtlpriv, REG_RF_CTRL);
788 rtl_write_byte(rtlpriv, REG_RF_CTRL, value | RF_EN | RF_RSTB |
789 RF_SDMRSTB);
790 rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN, FEN_PPLL | FEN_PCIEA |
791 FEN_DIO_PCIE | FEN_BB_GLB_RSTn | FEN_BBRSTB);
792 rtl_write_byte(rtlpriv, REG_AFE_XTAL_CTRL + 1, 0x80);
793 if (!(IS_92D_SINGLEPHY(rtlpriv->rtlhal.version))) {
794 regvaldw = rtl_read_dword(rtlpriv, REG_LEDCFG0);
795 rtl_write_dword(rtlpriv, REG_LEDCFG0, regvaldw | BIT(23));
796 }
797
798 return _rtl92d_phy_bb_config(hw);
799}
800
801bool rtl92d_phy_rf_config(struct ieee80211_hw *hw)
802{
803 return rtl92d_phy_rf6052_config(hw);
804}
805
806bool rtl92d_phy_config_rf_with_headerfile(struct ieee80211_hw *hw,
807 enum rf_content content,
808 enum radio_path rfpath)
809{
eb8b27ad 810 int i;
7274a8c2
CL		 811 u32 *radioa_array_table;
812 u32 *radiob_array_table;
813 u16 radioa_arraylen, radiob_arraylen;
814 struct rtl_priv *rtlpriv = rtl_priv(hw);
815
816 radioa_arraylen = RADIOA_2T_ARRAYLENGTH;
817 radioa_array_table = rtl8192de_radioa_2tarray;
818 radiob_arraylen = RADIOB_2T_ARRAYLENGTH;
819 radiob_array_table = rtl8192de_radiob_2tarray;
820 if (rtlpriv->efuse.internal_pa_5g[0]) {
821 radioa_arraylen = RADIOA_2T_INT_PA_ARRAYLENGTH;
822 radioa_array_table = rtl8192de_radioa_2t_int_paarray;
823 }
824 if (rtlpriv->efuse.internal_pa_5g[1]) {
825 radiob_arraylen = RADIOB_2T_INT_PA_ARRAYLENGTH;
826 radiob_array_table = rtl8192de_radiob_2t_int_paarray;
827 }
828 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
f30d7507 829 "PHY_ConfigRFWithHeaderFile() Radio_A:Rtl819XRadioA_1TArray\n");
7274a8c2 830 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
f30d7507
JP		 831 "PHY_ConfigRFWithHeaderFile() Radio_B:Rtl819XRadioB_1TArray\n");
832 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE, "Radio No %x\n", rfpath);
7274a8c2
CL		 833
834 /* this only happens when DMDP, mac0 start on 2.4G,
835 * mac1 start on 5G, mac 0 has to set phy0&phy1
836 * pathA or mac1 has to set phy0&phy1 pathA */
837 if ((content == radiob_txt) && (rfpath == RF90_PATH_A)) {
838 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
f30d7507 839 " ===> althougth Path A, we load radiob.txt\n");
7274a8c2
CL		 840 radioa_arraylen = radiob_arraylen;
841 radioa_array_table = radiob_array_table;
842 }
843 switch (rfpath) {
844 case RF90_PATH_A:
845 for (i = 0; i < radioa_arraylen; i = i + 2) {
846 if (radioa_array_table[i] == 0xfe) {
847 mdelay(50);
848 } else if (radioa_array_table[i] == 0xfd) {
849 /* delay_ms(5); */
eb8b27ad 850 mdelay(5);
7274a8c2
CL		 851 } else if (radioa_array_table[i] == 0xfc) {
852 /* delay_ms(1); */
eb8b27ad 853 mdelay(1);
7274a8c2
CL		 854 } else if (radioa_array_table[i] == 0xfb) {
855 udelay(50);
856 } else if (radioa_array_table[i] == 0xfa) {
857 udelay(5);
858 } else if (radioa_array_table[i] == 0xf9) {
859 udelay(1);
860 } else {
861 rtl_set_rfreg(hw, rfpath, radioa_array_table[i],
862 BRFREGOFFSETMASK,
863 radioa_array_table[i + 1]);
864 /* Add 1us delay between BB/RF register set. */
865 udelay(1);
866 }
867 }
868 break;
869 case RF90_PATH_B:
870 for (i = 0; i < radiob_arraylen; i = i + 2) {
871 if (radiob_array_table[i] == 0xfe) {
872 /* Delay specific ms. Only RF configuration
873 * requires delay. */
874 mdelay(50);
875 } else if (radiob_array_table[i] == 0xfd) {
876 /* delay_ms(5); */
eb8b27ad 877 mdelay(5);
7274a8c2
CL		 878 } else if (radiob_array_table[i] == 0xfc) {
879 /* delay_ms(1); */
eb8b27ad 880 mdelay(1);
7274a8c2
CL		 881 } else if (radiob_array_table[i] == 0xfb) {
882 udelay(50);
883 } else if (radiob_array_table[i] == 0xfa) {
884 udelay(5);
885 } else if (radiob_array_table[i] == 0xf9) {
886 udelay(1);
887 } else {
888 rtl_set_rfreg(hw, rfpath, radiob_array_table[i],
889 BRFREGOFFSETMASK,
890 radiob_array_table[i + 1]);
891 /* Add 1us delay between BB/RF register set. */
892 udelay(1);
893 }
894 }
895 break;
896 case RF90_PATH_C:
897 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
f30d7507 898 "switch case not processed\n");
7274a8c2
CL		 899 break;
900 case RF90_PATH_D:
901 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
f30d7507 902 "switch case not processed\n");
7274a8c2
CL		 903 break;
904 }
905 return true;
906}
907
908void rtl92d_phy_get_hw_reg_originalvalue(struct ieee80211_hw *hw)
909{
910 struct rtl_priv *rtlpriv = rtl_priv(hw);
911 struct rtl_phy *rtlphy = &(rtlpriv->phy);
912
913 rtlphy->default_initialgain[0] =
914 (u8) rtl_get_bbreg(hw, ROFDM0_XAAGCCORE1, BMASKBYTE0);
915 rtlphy->default_initialgain[1] =
916 (u8) rtl_get_bbreg(hw, ROFDM0_XBAGCCORE1, BMASKBYTE0);
917 rtlphy->default_initialgain[2] =
918 (u8) rtl_get_bbreg(hw, ROFDM0_XCAGCCORE1, BMASKBYTE0);
919 rtlphy->default_initialgain[3] =
920 (u8) rtl_get_bbreg(hw, ROFDM0_XDAGCCORE1, BMASKBYTE0);
921 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
f30d7507
JP		 922 "Default initial gain (c50=0x%x, c58=0x%x, c60=0x%x, c68=0x%x\n",
923 rtlphy->default_initialgain[0],
924 rtlphy->default_initialgain[1],
925 rtlphy->default_initialgain[2],
926 rtlphy->default_initialgain[3]);
7274a8c2
CL		 927 rtlphy->framesync = (u8)rtl_get_bbreg(hw, ROFDM0_RXDETECTOR3,
928 BMASKBYTE0);
929 rtlphy->framesync_c34 = rtl_get_bbreg(hw, ROFDM0_RXDETECTOR2,
930 BMASKDWORD);
931 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
f30d7507
JP		 932 "Default framesync (0x%x) = 0x%x\n",
933 ROFDM0_RXDETECTOR3, rtlphy->framesync);
7274a8c2
CL		 934}
935
936static void _rtl92d_get_txpower_index(struct ieee80211_hw *hw, u8 channel,
937 u8 *cckpowerlevel, u8 *ofdmpowerlevel)
938{
939 struct rtl_priv *rtlpriv = rtl_priv(hw);
940 struct rtl_phy *rtlphy = &(rtlpriv->phy);
941 struct rtl_hal *rtlhal = &(rtlpriv->rtlhal);
942 struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
943 u8 index = (channel - 1);
944
945 /* 1. CCK */
946 if (rtlhal->current_bandtype == BAND_ON_2_4G) {
947 /* RF-A */
948 cckpowerlevel[RF90_PATH_A] =
949 rtlefuse->txpwrlevel_cck[RF90_PATH_A][index];
950 /* RF-B */
951 cckpowerlevel[RF90_PATH_B] =
952 rtlefuse->txpwrlevel_cck[RF90_PATH_B][index];
953 } else {
954 cckpowerlevel[RF90_PATH_A] = 0;
955 cckpowerlevel[RF90_PATH_B] = 0;
956 }
957 /* 2. OFDM for 1S or 2S */
958 if (rtlphy->rf_type == RF_1T2R || rtlphy->rf_type == RF_1T1R) {
959 /* Read HT 40 OFDM TX power */
960 ofdmpowerlevel[RF90_PATH_A] =
961 rtlefuse->txpwrlevel_ht40_1s[RF90_PATH_A][index];
962 ofdmpowerlevel[RF90_PATH_B] =
963 rtlefuse->txpwrlevel_ht40_1s[RF90_PATH_B][index];
964 } else if (rtlphy->rf_type == RF_2T2R) {
965 /* Read HT 40 OFDM TX power */
966 ofdmpowerlevel[RF90_PATH_A] =
967 rtlefuse->txpwrlevel_ht40_2s[RF90_PATH_A][index];
968 ofdmpowerlevel[RF90_PATH_B] =
969 rtlefuse->txpwrlevel_ht40_2s[RF90_PATH_B][index];
970 }
971}
972
973static void _rtl92d_ccxpower_index_check(struct ieee80211_hw *hw,
974 u8 channel, u8 *cckpowerlevel, u8 *ofdmpowerlevel)
975{
976 struct rtl_priv *rtlpriv = rtl_priv(hw);
977 struct rtl_phy *rtlphy = &(rtlpriv->phy);
978
979 rtlphy->cur_cck_txpwridx = cckpowerlevel[0];
980 rtlphy->cur_ofdm24g_txpwridx = ofdmpowerlevel[0];
981}
982
983static u8 _rtl92c_phy_get_rightchnlplace(u8 chnl)
984{
985 u8 channel_5g[59] = {
986 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14,
987 36, 38, 40, 42, 44, 46, 48, 50, 52, 54, 56, 58,
988 60, 62, 64, 100, 102, 104, 106, 108, 110, 112,
989 114, 116, 118, 120, 122, 124, 126, 128,
990 130, 132, 134, 136, 138, 140, 149, 151,
991 153, 155, 157, 159, 161, 163, 165
992 };
993 u8 place = chnl;
994
995 if (chnl > 14) {
996 for (place = 14; place < sizeof(channel_5g); place++) {
997 if (channel_5g[place] == chnl) {
998 place++;
999 break;
1000 }
1001 }
1002 }
1003 return place;
1004}
1005
1006void rtl92d_phy_set_txpower_level(struct ieee80211_hw *hw, u8 channel)
1007{
1008 struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
1009 struct rtl_priv *rtlpriv = rtl_priv(hw);
1010 u8 cckpowerlevel[2], ofdmpowerlevel[2];
1011
23677ce3 1012 if (!rtlefuse->txpwr_fromeprom)
7274a8c2
CL		 1013 return;
1014 channel = _rtl92c_phy_get_rightchnlplace(channel);
1015 _rtl92d_get_txpower_index(hw, channel, &cckpowerlevel[0],
1016 &ofdmpowerlevel[0]);
1017 if (rtlpriv->rtlhal.current_bandtype == BAND_ON_2_4G)
1018 _rtl92d_ccxpower_index_check(hw, channel, &cckpowerlevel[0],
1019 &ofdmpowerlevel[0]);
1020 if (rtlpriv->rtlhal.current_bandtype == BAND_ON_2_4G)
1021 rtl92d_phy_rf6052_set_cck_txpower(hw, &cckpowerlevel[0]);
1022 rtl92d_phy_rf6052_set_ofdm_txpower(hw, &ofdmpowerlevel[0], channel);
1023}
1024
1025void rtl92d_phy_scan_operation_backup(struct ieee80211_hw *hw, u8 operation)
1026{
1027 struct rtl_priv *rtlpriv = rtl_priv(hw);
1028 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
1029 enum io_type iotype;
1030
1031 if (!is_hal_stop(rtlhal)) {
1032 switch (operation) {
1033 case SCAN_OPT_BACKUP:
1034 rtlhal->current_bandtypebackup =
1035 rtlhal->current_bandtype;
1036 iotype = IO_CMD_PAUSE_DM_BY_SCAN;
1037 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_IO_CMD,
1038 (u8 *)&iotype);
1039 break;
1040 case SCAN_OPT_RESTORE:
1041 iotype = IO_CMD_RESUME_DM_BY_SCAN;
1042 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_IO_CMD,
1043 (u8 *)&iotype);
1044 break;
1045 default:
1046 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
f30d7507 1047 "Unknown Scan Backup operation\n");
7274a8c2
CL		 1048 break;
1049 }
1050 }
1051}
1052
1053void rtl92d_phy_set_bw_mode(struct ieee80211_hw *hw,
1054 enum nl80211_channel_type ch_type)
1055{
1056 struct rtl_priv *rtlpriv = rtl_priv(hw);
1057 struct rtl_phy *rtlphy = &(rtlpriv->phy);
1058 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
1059 struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
1060 unsigned long flag = 0;
1061 u8 reg_prsr_rsc;
1062 u8 reg_bw_opmode;
1063
1064 if (rtlphy->set_bwmode_inprogress)
1065 return;
1066 if ((is_hal_stop(rtlhal)) || (RT_CANNOT_IO(hw))) {
1067 RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING,
f30d7507 1068 "FALSE driver sleep or unload\n");
7274a8c2
CL		 1069 return;
1070 }
1071 rtlphy->set_bwmode_inprogress = true;
f30d7507
JP		 1072 RT_TRACE(rtlpriv, COMP_SCAN, DBG_TRACE, "Switch to %s bandwidth\n",
1073 rtlphy->current_chan_bw == HT_CHANNEL_WIDTH_20 ?
1074 "20MHz" : "40MHz");
7274a8c2
CL		 1075 reg_bw_opmode = rtl_read_byte(rtlpriv, REG_BWOPMODE);
1076 reg_prsr_rsc = rtl_read_byte(rtlpriv, REG_RRSR + 2);
1077 switch (rtlphy->current_chan_bw) {
1078 case HT_CHANNEL_WIDTH_20:
1079 reg_bw_opmode |= BW_OPMODE_20MHZ;
1080 rtl_write_byte(rtlpriv, REG_BWOPMODE, reg_bw_opmode);
1081 break;
1082 case HT_CHANNEL_WIDTH_20_40:
1083 reg_bw_opmode &= ~BW_OPMODE_20MHZ;
1084 rtl_write_byte(rtlpriv, REG_BWOPMODE, reg_bw_opmode);
1085
1086 reg_prsr_rsc = (reg_prsr_rsc & 0x90) |
1087 (mac->cur_40_prime_sc << 5);
1088 rtl_write_byte(rtlpriv, REG_RRSR + 2, reg_prsr_rsc);
1089 break;
1090 default:
1091 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
f30d7507 1092 "unknown bandwidth: %#X\n", rtlphy->current_chan_bw);
7274a8c2
CL		 1093 break;
1094 }
1095 switch (rtlphy->current_chan_bw) {
1096 case HT_CHANNEL_WIDTH_20:
1097 rtl_set_bbreg(hw, RFPGA0_RFMOD, BRFMOD, 0x0);
1098 rtl_set_bbreg(hw, RFPGA1_RFMOD, BRFMOD, 0x0);
1099 /* SET BIT10 BIT11 for receive cck */
1100 rtl_set_bbreg(hw, RFPGA0_ANALOGPARAMETER2, BIT(10) |
1101 BIT(11), 3);
1102 break;
1103 case HT_CHANNEL_WIDTH_20_40:
1104 rtl_set_bbreg(hw, RFPGA0_RFMOD, BRFMOD, 0x1);
1105 rtl_set_bbreg(hw, RFPGA1_RFMOD, BRFMOD, 0x1);
1106 /* Set Control channel to upper or lower.
1107 * These settings are required only for 40MHz */
1108 if (rtlhal->current_bandtype == BAND_ON_2_4G) {
1109 rtl92d_acquire_cckandrw_pagea_ctl(hw, &flag);
1110 rtl_set_bbreg(hw, RCCK0_SYSTEM, BCCKSIDEBAND,
1111 (mac->cur_40_prime_sc >> 1));
1112 rtl92d_release_cckandrw_pagea_ctl(hw, &flag);
1113 }
1114 rtl_set_bbreg(hw, ROFDM1_LSTF, 0xC00, mac->cur_40_prime_sc);
1115 /* SET BIT10 BIT11 for receive cck */
1116 rtl_set_bbreg(hw, RFPGA0_ANALOGPARAMETER2, BIT(10) |
1117 BIT(11), 0);
1118 rtl_set_bbreg(hw, 0x818, (BIT(26) | BIT(27)),
1119 (mac->cur_40_prime_sc ==
1120 HAL_PRIME_CHNL_OFFSET_LOWER) ? 2 : 1);
1121 break;
1122 default:
1123 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
f30d7507 1124 "unknown bandwidth: %#X\n", rtlphy->current_chan_bw);
7274a8c2
CL		 1125 break;
1126
1127 }
1128 rtl92d_phy_rf6052_set_bandwidth(hw, rtlphy->current_chan_bw);
1129 rtlphy->set_bwmode_inprogress = false;
f30d7507 1130 RT_TRACE(rtlpriv, COMP_SCAN, DBG_TRACE, "<==\n");
7274a8c2
CL		 1131}
1132
1133static void _rtl92d_phy_stop_trx_before_changeband(struct ieee80211_hw *hw)
1134{
1135 rtl_set_bbreg(hw, RFPGA0_RFMOD, BCCKEN, 0);
1136 rtl_set_bbreg(hw, RFPGA0_RFMOD, BOFDMEN, 0);
1137 rtl_set_bbreg(hw, ROFDM0_TRXPATHENABLE, BMASKBYTE0, 0x00);
1138 rtl_set_bbreg(hw, ROFDM1_TRXPATHENABLE, BDWORD, 0x0);
1139}
1140
1141static void rtl92d_phy_switch_wirelessband(struct ieee80211_hw *hw, u8 band)
1142{
1143 struct rtl_priv *rtlpriv = rtl_priv(hw);
1144 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
eb8b27ad 1145 u8 value8;
7274a8c2 1146
f30d7507 1147 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, "==>\n");
7274a8c2
CL		 1148 rtlhal->bandset = band;
1149 rtlhal->current_bandtype = band;
1150 if (IS_92D_SINGLEPHY(rtlhal->version))
1151 rtlhal->bandset = BAND_ON_BOTH;
1152 /* stop RX/Tx */
1153 _rtl92d_phy_stop_trx_before_changeband(hw);
1154 /* reconfig BB/RF according to wireless mode */
1155 if (rtlhal->current_bandtype == BAND_ON_2_4G) {
1156 /* BB & RF Config */
f30d7507 1157 RT_TRACE(rtlpriv, COMP_CMD, DBG_DMESG, "====>2.4G\n");
7274a8c2
CL		 1158 if (rtlhal->interfaceindex == 1)
1159 _rtl92d_phy_config_bb_with_headerfile(hw,
1160 BASEBAND_CONFIG_AGC_TAB);
1161 } else {
1162 /* 5G band */
f30d7507 1163 RT_TRACE(rtlpriv, COMP_CMD, DBG_DMESG, "====>5G\n");
7274a8c2
CL		 1164 if (rtlhal->interfaceindex == 1)
1165 _rtl92d_phy_config_bb_with_headerfile(hw,
1166 BASEBAND_CONFIG_AGC_TAB);
1167 }
1168 rtl92d_update_bbrf_configuration(hw);
1169 if (rtlhal->current_bandtype == BAND_ON_2_4G)
1170 rtl_set_bbreg(hw, RFPGA0_RFMOD, BCCKEN, 0x1);
1171 rtl_set_bbreg(hw, RFPGA0_RFMOD, BOFDMEN, 0x1);
1172
1173 /* 20M BW. */
1174 /* rtl_set_bbreg(hw, RFPGA0_ANALOGPARAMETER2, BIT(10), 1); */
1175 rtlhal->reloadtxpowerindex = true;
1176 /* notice fw know band status 0x81[1]/0x53[1] = 0: 5G, 1: 2G */
1177 if (rtlhal->current_bandtype == BAND_ON_2_4G) {
1178 value8 = rtl_read_byte(rtlpriv, (rtlhal->interfaceindex ==
1179 0 ? REG_MAC0 : REG_MAC1));
1180 value8 |= BIT(1);
1181 rtl_write_byte(rtlpriv, (rtlhal->interfaceindex ==
1182 0 ? REG_MAC0 : REG_MAC1), value8);
1183 } else {
1184 value8 = rtl_read_byte(rtlpriv, (rtlhal->interfaceindex ==
1185 0 ? REG_MAC0 : REG_MAC1));
1186 value8 &= (~BIT(1));
1187 rtl_write_byte(rtlpriv, (rtlhal->interfaceindex ==
1188 0 ? REG_MAC0 : REG_MAC1), value8);
1189 }
eb8b27ad 1190 mdelay(1);
f30d7507 1191 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, "<==Switch Band OK\n");
7274a8c2
CL		 1192}
1193
1194static void _rtl92d_phy_reload_imr_setting(struct ieee80211_hw *hw,
1195 u8 channel, u8 rfpath)
1196{
1197 struct rtl_priv *rtlpriv = rtl_priv(hw);
1198 u32 imr_num = MAX_RF_IMR_INDEX;
1199 u32 rfmask = BRFREGOFFSETMASK;
1200 u8 group, i;
1201 unsigned long flag = 0;
1202
f30d7507 1203 RT_TRACE(rtlpriv, COMP_CMD, DBG_LOUD, "====>path %d\n", rfpath);
7274a8c2 1204 if (rtlpriv->rtlhal.current_bandtype == BAND_ON_5G) {
f30d7507 1205 RT_TRACE(rtlpriv, COMP_CMD, DBG_LOUD, "====>5G\n");
7274a8c2
CL		 1206 rtl_set_bbreg(hw, RFPGA0_RFMOD, BIT(25) | BIT(24), 0);
1207 rtl_set_bbreg(hw, RFPGA0_ANALOGPARAMETER4, 0x00f00000, 0xf);
1208 /* fc area 0xd2c */
1209 if (channel > 99)
1210 rtl_set_bbreg(hw, ROFDM1_CFOTRACKING, BIT(13) |
1211 BIT(14), 2);
1212 else
1213 rtl_set_bbreg(hw, ROFDM1_CFOTRACKING, BIT(13) |
1214 BIT(14), 1);
1215 /* leave 0 for channel1-14. */
1216 group = channel <= 64 ? 1 : 2;
1217 imr_num = MAX_RF_IMR_INDEX_NORMAL;
1218 for (i = 0; i < imr_num; i++)
1219 rtl_set_rfreg(hw, (enum radio_path)rfpath,
1220 rf_reg_for_5g_swchnl_normal[i], rfmask,
1221 rf_imr_param_normal[0][group][i]);
1222 rtl_set_bbreg(hw, RFPGA0_ANALOGPARAMETER4, 0x00f00000, 0);
1223 rtl_set_bbreg(hw, RFPGA0_RFMOD, BOFDMEN, 1);
1224 } else {
1225 /* G band. */
1226 RT_TRACE(rtlpriv, COMP_SCAN, DBG_LOUD,
f30d7507
JP		 1227 "Load RF IMR parameters for G band. IMR already setting %d\n",
1228 rtlpriv->rtlhal.load_imrandiqk_setting_for2g);
1229 RT_TRACE(rtlpriv, COMP_CMD, DBG_LOUD, "====>2.4G\n");
7274a8c2
CL		 1230 if (!rtlpriv->rtlhal.load_imrandiqk_setting_for2g) {
1231 RT_TRACE(rtlpriv, COMP_SCAN, DBG_LOUD,
f30d7507
JP		 1232 "Load RF IMR parameters for G band. %d\n",
1233 rfpath);
7274a8c2
CL		 1234 rtl92d_acquire_cckandrw_pagea_ctl(hw, &flag);
1235 rtl_set_bbreg(hw, RFPGA0_RFMOD, BIT(25) | BIT(24), 0);
1236 rtl_set_bbreg(hw, RFPGA0_ANALOGPARAMETER4,
1237 0x00f00000, 0xf);
1238 imr_num = MAX_RF_IMR_INDEX_NORMAL;
1239 for (i = 0; i < imr_num; i++) {
1240 rtl_set_rfreg(hw, (enum radio_path)rfpath,
1241 rf_reg_for_5g_swchnl_normal[i],
1242 BRFREGOFFSETMASK,
1243 rf_imr_param_normal[0][0][i]);
1244 }
1245 rtl_set_bbreg(hw, RFPGA0_ANALOGPARAMETER4,
1246 0x00f00000, 0);
1247 rtl_set_bbreg(hw, RFPGA0_RFMOD, BOFDMEN | BCCKEN, 3);
1248 rtl92d_release_cckandrw_pagea_ctl(hw, &flag);
1249 }
1250 }
f30d7507 1251 RT_TRACE(rtlpriv, COMP_CMD, DBG_LOUD, "<====\n");
7274a8c2
CL		 1252}
1253
1254static void _rtl92d_phy_enable_rf_env(struct ieee80211_hw *hw,
1255 u8 rfpath, u32 *pu4_regval)
1256{
1257 struct rtl_priv *rtlpriv = rtl_priv(hw);
1258 struct rtl_phy *rtlphy = &(rtlpriv->phy);
1259 struct bb_reg_def *pphyreg = &rtlphy->phyreg_def[rfpath];
1260
f30d7507 1261 RT_TRACE(rtlpriv, COMP_RF, DBG_LOUD, "====>\n");
7274a8c2
CL		 1262 /*----Store original RFENV control type----*/
1263 switch (rfpath) {
1264 case RF90_PATH_A:
1265 case RF90_PATH_C:
1266 *pu4_regval = rtl_get_bbreg(hw, pphyreg->rfintfs, BRFSI_RFENV);
1267 break;
1268 case RF90_PATH_B:
1269 case RF90_PATH_D:
1270 *pu4_regval =
1271 rtl_get_bbreg(hw, pphyreg->rfintfs, BRFSI_RFENV << 16);
1272 break;
1273 }
1274 /*----Set RF_ENV enable----*/
1275 rtl_set_bbreg(hw, pphyreg->rfintfe, BRFSI_RFENV << 16, 0x1);
1276 udelay(1);
1277 /*----Set RF_ENV output high----*/
1278 rtl_set_bbreg(hw, pphyreg->rfintfo, BRFSI_RFENV, 0x1);
1279 udelay(1);
1280 /* Set bit number of Address and Data for RF register */
1281 /* Set 1 to 4 bits for 8255 */
1282 rtl_set_bbreg(hw, pphyreg->rfhssi_para2, B3WIREADDRESSLENGTH, 0x0);
1283 udelay(1);
1284 /*Set 0 to 12 bits for 8255 */
1285 rtl_set_bbreg(hw, pphyreg->rfhssi_para2, B3WIREDATALENGTH, 0x0);
1286 udelay(1);
f30d7507 1287 RT_TRACE(rtlpriv, COMP_RF, DBG_LOUD, "<====\n");
7274a8c2
CL		 1288}
1289
1290static void _rtl92d_phy_restore_rf_env(struct ieee80211_hw *hw, u8 rfpath,
1291 u32 *pu4_regval)
1292{
1293 struct rtl_priv *rtlpriv = rtl_priv(hw);
1294 struct rtl_phy *rtlphy = &(rtlpriv->phy);
1295 struct bb_reg_def *pphyreg = &rtlphy->phyreg_def[rfpath];
1296
f30d7507 1297 RT_TRACE(rtlpriv, COMP_RF, DBG_LOUD, "=====>\n");
84d216c6 1298 /*----Restore RFENV control type----*/
7274a8c2
CL		 1299 switch (rfpath) {
1300 case RF90_PATH_A:
1301 case RF90_PATH_C:
1302 rtl_set_bbreg(hw, pphyreg->rfintfs, BRFSI_RFENV, *pu4_regval);
1303 break;
1304 case RF90_PATH_B:
1305 case RF90_PATH_D:
1306 rtl_set_bbreg(hw, pphyreg->rfintfs, BRFSI_RFENV << 16,
1307 *pu4_regval);
1308 break;
1309 }
f30d7507 1310 RT_TRACE(rtlpriv, COMP_RF, DBG_LOUD, "<=====\n");
7274a8c2
CL		 1311}
1312
1313static void _rtl92d_phy_switch_rf_setting(struct ieee80211_hw *hw, u8 channel)
1314{
1315 struct rtl_priv *rtlpriv = rtl_priv(hw);
1316 struct rtl_phy *rtlphy = &(rtlpriv->phy);
1317 struct rtl_hal *rtlhal = &(rtlpriv->rtlhal);
1318 u8 path = rtlhal->current_bandtype ==
1319 BAND_ON_5G ? RF90_PATH_A : RF90_PATH_B;
1320 u8 index = 0, i = 0, rfpath = RF90_PATH_A;
1321 bool need_pwr_down = false, internal_pa = false;
1322 u32 u4regvalue, mask = 0x1C000, value = 0, u4tmp, u4tmp2;
1323
f30d7507 1324 RT_TRACE(rtlpriv, COMP_CMD, DBG_LOUD, "====>\n");
7274a8c2
CL		 1325 /* config path A for 5G */
1326 if (rtlhal->current_bandtype == BAND_ON_5G) {
f30d7507 1327 RT_TRACE(rtlpriv, COMP_CMD, DBG_LOUD, "====>5G\n");
7274a8c2 1328 u4tmp = curveindex_5g[channel - 1];
4c48869f
JP		 1329 RTPRINT(rtlpriv, FINIT, INIT_IQK,
1330 "ver 1 set RF-A, 5G, 0x28 = 0x%x !!\n", u4tmp);
7274a8c2
CL		 1331 for (i = 0; i < RF_CHNL_NUM_5G; i++) {
1332 if (channel == rf_chnl_5g[i] && channel <= 140)
1333 index = 0;
1334 }
1335 for (i = 0; i < RF_CHNL_NUM_5G_40M; i++) {
1336 if (channel == rf_chnl_5g_40m[i] && channel <= 140)
1337 index = 1;
1338 }
1339 if (channel == 149 || channel == 155 || channel == 161)
1340 index = 2;
1341 else if (channel == 151 || channel == 153 || channel == 163
1342 || channel == 165)
1343 index = 3;
1344 else if (channel == 157 || channel == 159)
1345 index = 4;
1346
1347 if (rtlhal->macphymode == DUALMAC_DUALPHY
1348 && rtlhal->interfaceindex == 1) {
1349 need_pwr_down = rtl92d_phy_enable_anotherphy(hw, false);
1350 rtlhal->during_mac1init_radioa = true;
1351 /* asume no this case */
1352 if (need_pwr_down)
1353 _rtl92d_phy_enable_rf_env(hw, path,
1354 &u4regvalue);
1355 }
1356 for (i = 0; i < RF_REG_NUM_FOR_C_CUT_5G; i++) {
1357 if (i == 0 && (rtlhal->macphymode == DUALMAC_DUALPHY)) {
1358 rtl_set_rfreg(hw, (enum radio_path)path,
1359 rf_reg_for_c_cut_5g[i],
1360 BRFREGOFFSETMASK, 0xE439D);
1361 } else if (rf_reg_for_c_cut_5g[i] == RF_SYN_G4) {
1362 u4tmp2 = (rf_reg_pram_c_5g[index][i] &
1363 0x7FF) | (u4tmp << 11);
1364 if (channel == 36)
1365 u4tmp2 &= ~(BIT(7) | BIT(6));
1366 rtl_set_rfreg(hw, (enum radio_path)path,
1367 rf_reg_for_c_cut_5g[i],
1368 BRFREGOFFSETMASK, u4tmp2);
1369 } else {
1370 rtl_set_rfreg(hw, (enum radio_path)path,
1371 rf_reg_for_c_cut_5g[i],
1372 BRFREGOFFSETMASK,
1373 rf_reg_pram_c_5g[index][i]);
1374 }
1375 RT_TRACE(rtlpriv, COMP_RF, DBG_TRACE,
f30d7507
JP		 1376 "offset 0x%x value 0x%x path %d index %d readback 0x%x\n",
1377 rf_reg_for_c_cut_5g[i],
1378 rf_reg_pram_c_5g[index][i],
1379 path, index,
1380 rtl_get_rfreg(hw, (enum radio_path)path,
1381 rf_reg_for_c_cut_5g[i],
1382 BRFREGOFFSETMASK));
7274a8c2
CL		 1383 }
1384 if (need_pwr_down)
1385 _rtl92d_phy_restore_rf_env(hw, path, &u4regvalue);
1386 if (rtlhal->during_mac1init_radioa)
1387 rtl92d_phy_powerdown_anotherphy(hw, false);
1388 if (channel < 149)
1389 value = 0x07;
1390 else if (channel >= 149)
1391 value = 0x02;
1392 if (channel >= 36 && channel <= 64)
1393 index = 0;
1394 else if (channel >= 100 && channel <= 140)
1395 index = 1;
1396 else
1397 index = 2;
1398 for (rfpath = RF90_PATH_A; rfpath < rtlphy->num_total_rfpath;
1399 rfpath++) {
1400 if (rtlhal->macphymode == DUALMAC_DUALPHY &&
1401 rtlhal->interfaceindex == 1) /* MAC 1 5G */
1402 internal_pa = rtlpriv->efuse.internal_pa_5g[1];
1403 else
1404 internal_pa =
1405 rtlpriv->efuse.internal_pa_5g[rfpath];
1406 if (internal_pa) {
1407 for (i = 0;
1408 i < RF_REG_NUM_FOR_C_CUT_5G_INTERNALPA;
1409 i++) {
1410 rtl_set_rfreg(hw, rfpath,
1411 rf_for_c_cut_5g_internal_pa[i],
1412 BRFREGOFFSETMASK,
1413 rf_pram_c_5g_int_pa[index][i]);
1414 RT_TRACE(rtlpriv, COMP_RF, DBG_LOUD,
f30d7507 1415 "offset 0x%x value 0x%x path %d index %d\n",
7274a8c2
CL		 1416 rf_for_c_cut_5g_internal_pa[i],
1417 rf_pram_c_5g_int_pa[index][i],
f30d7507 1418 rfpath, index);
7274a8c2
CL		 1419 }
1420 } else {
1421 rtl_set_rfreg(hw, (enum radio_path)rfpath, 0x0B,
1422 mask, value);
1423 }
1424 }
1425 } else if (rtlhal->current_bandtype == BAND_ON_2_4G) {
f30d7507 1426 RT_TRACE(rtlpriv, COMP_CMD, DBG_LOUD, "====>2.4G\n");
7274a8c2 1427 u4tmp = curveindex_2g[channel - 1];
4c48869f
JP		 1428 RTPRINT(rtlpriv, FINIT, INIT_IQK,
1429 "ver 3 set RF-B, 2G, 0x28 = 0x%x !!\n", u4tmp);
7274a8c2
CL		 1430 if (channel == 1 || channel == 2 || channel == 4 || channel == 9
1431 || channel == 10 || channel == 11 || channel == 12)
1432 index = 0;
1433 else if (channel == 3 || channel == 13 || channel == 14)
1434 index = 1;
1435 else if (channel >= 5 && channel <= 8)
1436 index = 2;
1437 if (rtlhal->macphymode == DUALMAC_DUALPHY) {
1438 path = RF90_PATH_A;
1439 if (rtlhal->interfaceindex == 0) {
1440 need_pwr_down =
1441 rtl92d_phy_enable_anotherphy(hw, true);
1442 rtlhal->during_mac0init_radiob = true;
1443
1444 if (need_pwr_down)
1445 _rtl92d_phy_enable_rf_env(hw, path,
1446 &u4regvalue);
1447 }
1448 }
1449 for (i = 0; i < RF_REG_NUM_FOR_C_CUT_2G; i++) {
1450 if (rf_reg_for_c_cut_2g[i] == RF_SYN_G7)
1451 rtl_set_rfreg(hw, (enum radio_path)path,
1452 rf_reg_for_c_cut_2g[i],
1453 BRFREGOFFSETMASK,
1454 (rf_reg_param_for_c_cut_2g[index][i] |
1455 BIT(17)));
1456 else
1457 rtl_set_rfreg(hw, (enum radio_path)path,
1458 rf_reg_for_c_cut_2g[i],
1459 BRFREGOFFSETMASK,
1460 rf_reg_param_for_c_cut_2g
1461 [index][i]);
1462 RT_TRACE(rtlpriv, COMP_RF, DBG_TRACE,
f30d7507
JP		 1463 "offset 0x%x value 0x%x mak 0x%x path %d index %d readback 0x%x\n",
1464 rf_reg_for_c_cut_2g[i],
1465 rf_reg_param_for_c_cut_2g[index][i],
1466 rf_reg_mask_for_c_cut_2g[i], path, index,
1467 rtl_get_rfreg(hw, (enum radio_path)path,
1468 rf_reg_for_c_cut_2g[i],
1469 BRFREGOFFSETMASK));
7274a8c2
CL		 1470 }
1471 RTPRINT(rtlpriv, FINIT, INIT_IQK,
4c48869f
JP		 1472 "cosa ver 3 set RF-B, 2G, 0x28 = 0x%x !!\n",
1473 rf_syn_g4_for_c_cut_2g | (u4tmp << 11));
7274a8c2
CL		 1474
1475 rtl_set_rfreg(hw, (enum radio_path)path, RF_SYN_G4,
1476 BRFREGOFFSETMASK,
1477 rf_syn_g4_for_c_cut_2g | (u4tmp << 11));
1478 if (need_pwr_down)
1479 _rtl92d_phy_restore_rf_env(hw, path, &u4regvalue);
1480 if (rtlhal->during_mac0init_radiob)
1481 rtl92d_phy_powerdown_anotherphy(hw, true);
1482 }
f30d7507 1483 RT_TRACE(rtlpriv, COMP_CMD, DBG_LOUD, "<====\n");
7274a8c2
CL		 1484}
1485
1486u8 rtl92d_get_rightchnlplace_for_iqk(u8 chnl)
1487{
1488 u8 channel_all[59] = {
1489 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14,
1490 36, 38, 40, 42, 44, 46, 48, 50, 52, 54, 56, 58,
1491 60, 62, 64, 100, 102, 104, 106, 108, 110, 112,
1492 114, 116, 118, 120, 122, 124, 126, 128, 130,
1493 132, 134, 136, 138, 140, 149, 151, 153, 155,
1494 157, 159, 161, 163, 165
1495 };
1496 u8 place = chnl;
1497
1498 if (chnl > 14) {
1499 for (place = 14; place < sizeof(channel_all); place++) {
1500 if (channel_all[place] == chnl)
1501 return place - 13;
1502 }
1503 }
1504
1505 return 0;
1506}
1507
1508#define MAX_TOLERANCE 5
1509#define IQK_DELAY_TIME 1 /* ms */
1510#define MAX_TOLERANCE_92D 3
1511
1512/* bit0 = 1 => Tx OK, bit1 = 1 => Rx OK */
1513static u8 _rtl92d_phy_patha_iqk(struct ieee80211_hw *hw, bool configpathb)
1514{
1515 struct rtl_priv *rtlpriv = rtl_priv(hw);
1516 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
1517 u32 regeac, rege94, rege9c, regea4;
1518 u8 result = 0;
1519
4c48869f 1520 RTPRINT(rtlpriv, FINIT, INIT_IQK, "Path A IQK!\n");
7274a8c2 1521 /* path-A IQK setting */
4c48869f 1522 RTPRINT(rtlpriv, FINIT, INIT_IQK, "Path-A IQK setting!\n");
7274a8c2
CL		 1523 if (rtlhal->interfaceindex == 0) {
1524 rtl_set_bbreg(hw, 0xe30, BMASKDWORD, 0x10008c1f);
1525 rtl_set_bbreg(hw, 0xe34, BMASKDWORD, 0x10008c1f);
1526 } else {
1527 rtl_set_bbreg(hw, 0xe30, BMASKDWORD, 0x10008c22);
1528 rtl_set_bbreg(hw, 0xe34, BMASKDWORD, 0x10008c22);
1529 }
1530 rtl_set_bbreg(hw, 0xe38, BMASKDWORD, 0x82140102);
1531 rtl_set_bbreg(hw, 0xe3c, BMASKDWORD, 0x28160206);
1532 /* path-B IQK setting */
1533 if (configpathb) {
1534 rtl_set_bbreg(hw, 0xe50, BMASKDWORD, 0x10008c22);
1535 rtl_set_bbreg(hw, 0xe54, BMASKDWORD, 0x10008c22);
1536 rtl_set_bbreg(hw, 0xe58, BMASKDWORD, 0x82140102);
1537 rtl_set_bbreg(hw, 0xe5c, BMASKDWORD, 0x28160206);
1538 }
1539 /* LO calibration setting */
4c48869f 1540 RTPRINT(rtlpriv, FINIT, INIT_IQK, "LO calibration setting!\n");
7274a8c2
CL		 1541 rtl_set_bbreg(hw, 0xe4c, BMASKDWORD, 0x00462911);
1542 /* One shot, path A LOK & IQK */
4c48869f 1543 RTPRINT(rtlpriv, FINIT, INIT_IQK, "One shot, path A LOK & IQK!\n");
7274a8c2
CL		 1544 rtl_set_bbreg(hw, 0xe48, BMASKDWORD, 0xf9000000);
1545 rtl_set_bbreg(hw, 0xe48, BMASKDWORD, 0xf8000000);
1546 /* delay x ms */
1547 RTPRINT(rtlpriv, FINIT, INIT_IQK,
4c48869f
JP		 1548 "Delay %d ms for One shot, path A LOK & IQK\n",
1549 IQK_DELAY_TIME);
faeef8ac 1550 mdelay(IQK_DELAY_TIME);
7274a8c2
CL		 1551 /* Check failed */
1552 regeac = rtl_get_bbreg(hw, 0xeac, BMASKDWORD);
4c48869f 1553 RTPRINT(rtlpriv, FINIT, INIT_IQK, "0xeac = 0x%x\n", regeac);
7274a8c2 1554 rege94 = rtl_get_bbreg(hw, 0xe94, BMASKDWORD);
4c48869f 1555 RTPRINT(rtlpriv, FINIT, INIT_IQK, "0xe94 = 0x%x\n", rege94);
7274a8c2 1556 rege9c = rtl_get_bbreg(hw, 0xe9c, BMASKDWORD);
4c48869f 1557 RTPRINT(rtlpriv, FINIT, INIT_IQK, "0xe9c = 0x%x\n", rege9c);
7274a8c2 1558 regea4 = rtl_get_bbreg(hw, 0xea4, BMASKDWORD);
4c48869f 1559 RTPRINT(rtlpriv, FINIT, INIT_IQK, "0xea4 = 0x%x\n", regea4);
7274a8c2
CL		 1560 if (!(regeac & BIT(28)) && (((rege94 & 0x03FF0000) >> 16) != 0x142) &&
1561 (((rege9c & 0x03FF0000) >> 16) != 0x42))
1562 result |= 0x01;
1563 else /* if Tx not OK, ignore Rx */
1564 return result;
1565 /* if Tx is OK, check whether Rx is OK */
1566 if (!(regeac & BIT(27)) && (((regea4 & 0x03FF0000) >> 16) != 0x132) &&
1567 (((regeac & 0x03FF0000) >> 16) != 0x36))
1568 result |= 0x02;
1569 else
4c48869f 1570 RTPRINT(rtlpriv, FINIT, INIT_IQK, "Path A Rx IQK fail!!\n");
7274a8c2
CL		 1571 return result;
1572}
1573
1574/* bit0 = 1 => Tx OK, bit1 = 1 => Rx OK */
1575static u8 _rtl92d_phy_patha_iqk_5g_normal(struct ieee80211_hw *hw,
1576 bool configpathb)
1577{
1578 struct rtl_priv *rtlpriv = rtl_priv(hw);
1579 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
1580 struct rtl_phy *rtlphy = &(rtlpriv->phy);
1581 u32 regeac, rege94, rege9c, regea4;
1582 u8 result = 0;
1583 u8 i;
1584 u8 retrycount = 2;
1585 u32 TxOKBit = BIT(28), RxOKBit = BIT(27);
1586
1587 if (rtlhal->interfaceindex == 1) { /* PHY1 */
1588 TxOKBit = BIT(31);
1589 RxOKBit = BIT(30);
1590 }
4c48869f 1591 RTPRINT(rtlpriv, FINIT, INIT_IQK, "Path A IQK!\n");
7274a8c2 1592 /* path-A IQK setting */
4c48869f 1593 RTPRINT(rtlpriv, FINIT, INIT_IQK, "Path-A IQK setting!\n");
7274a8c2
CL		 1594 rtl_set_bbreg(hw, 0xe30, BMASKDWORD, 0x18008c1f);
1595 rtl_set_bbreg(hw, 0xe34, BMASKDWORD, 0x18008c1f);
1596 rtl_set_bbreg(hw, 0xe38, BMASKDWORD, 0x82140307);
1597 rtl_set_bbreg(hw, 0xe3c, BMASKDWORD, 0x68160960);
1598 /* path-B IQK setting */
1599 if (configpathb) {
1600 rtl_set_bbreg(hw, 0xe50, BMASKDWORD, 0x18008c2f);
1601 rtl_set_bbreg(hw, 0xe54, BMASKDWORD, 0x18008c2f);
1602 rtl_set_bbreg(hw, 0xe58, BMASKDWORD, 0x82110000);
1603 rtl_set_bbreg(hw, 0xe5c, BMASKDWORD, 0x68110000);
1604 }
1605 /* LO calibration setting */
4c48869f 1606 RTPRINT(rtlpriv, FINIT, INIT_IQK, "LO calibration setting!\n");
7274a8c2
CL		 1607 rtl_set_bbreg(hw, 0xe4c, BMASKDWORD, 0x00462911);
1608 /* path-A PA on */
1609 rtl_set_bbreg(hw, RFPGA0_XAB_RFINTERFACESW, BMASKDWORD, 0x07000f60);
1610 rtl_set_bbreg(hw, RFPGA0_XA_RFINTERFACEOE, BMASKDWORD, 0x66e60e30);
1611 for (i = 0; i < retrycount; i++) {
1612 /* One shot, path A LOK & IQK */
1613 RTPRINT(rtlpriv, FINIT, INIT_IQK,
4c48869f 1614 "One shot, path A LOK & IQK!\n");
7274a8c2
CL		 1615 rtl_set_bbreg(hw, 0xe48, BMASKDWORD, 0xf9000000);
1616 rtl_set_bbreg(hw, 0xe48, BMASKDWORD, 0xf8000000);
1617 /* delay x ms */
1618 RTPRINT(rtlpriv, FINIT, INIT_IQK,
4c48869f
JP		 1619 "Delay %d ms for One shot, path A LOK & IQK.\n",
1620 IQK_DELAY_TIME);
faeef8ac 1621 mdelay(IQK_DELAY_TIME * 10);
7274a8c2
CL		 1622 /* Check failed */
1623 regeac = rtl_get_bbreg(hw, 0xeac, BMASKDWORD);
4c48869f 1624 RTPRINT(rtlpriv, FINIT, INIT_IQK, "0xeac = 0x%x\n", regeac);
7274a8c2 1625 rege94 = rtl_get_bbreg(hw, 0xe94, BMASKDWORD);
4c48869f 1626 RTPRINT(rtlpriv, FINIT, INIT_IQK, "0xe94 = 0x%x\n", rege94);
7274a8c2 1627 rege9c = rtl_get_bbreg(hw, 0xe9c, BMASKDWORD);
4c48869f 1628 RTPRINT(rtlpriv, FINIT, INIT_IQK, "0xe9c = 0x%x\n", rege9c);
7274a8c2 1629 regea4 = rtl_get_bbreg(hw, 0xea4, BMASKDWORD);
4c48869f 1630 RTPRINT(rtlpriv, FINIT, INIT_IQK, "0xea4 = 0x%x\n", regea4);
7274a8c2
CL		 1631 if (!(regeac & TxOKBit) &&
1632 (((rege94 & 0x03FF0000) >> 16) != 0x142)) {
1633 result |= 0x01;
1634 } else { /* if Tx not OK, ignore Rx */
1635 RTPRINT(rtlpriv, FINIT, INIT_IQK,
4c48869f 1636 "Path A Tx IQK fail!!\n");
7274a8c2
CL		 1637 continue;
1638 }
1639
1640 /* if Tx is OK, check whether Rx is OK */
1641 if (!(regeac & RxOKBit) &&
1642 (((regea4 & 0x03FF0000) >> 16) != 0x132)) {
1643 result |= 0x02;
1644 break;
1645 } else {
1646 RTPRINT(rtlpriv, FINIT, INIT_IQK,
4c48869f 1647 "Path A Rx IQK fail!!\n");
7274a8c2
CL		 1648 }
1649 }
1650 /* path A PA off */
1651 rtl_set_bbreg(hw, RFPGA0_XAB_RFINTERFACESW, BMASKDWORD,
1652 rtlphy->iqk_bb_backup[0]);
1653 rtl_set_bbreg(hw, RFPGA0_XA_RFINTERFACEOE, BMASKDWORD,
1654 rtlphy->iqk_bb_backup[1]);
1655 return result;
1656}
1657
1658/* bit0 = 1 => Tx OK, bit1 = 1 => Rx OK */
1659static u8 _rtl92d_phy_pathb_iqk(struct ieee80211_hw *hw)
1660{
1661 struct rtl_priv *rtlpriv = rtl_priv(hw);
1662 u32 regeac, regeb4, regebc, regec4, regecc;
1663 u8 result = 0;
1664
4c48869f 1665 RTPRINT(rtlpriv, FINIT, INIT_IQK, "Path B IQK!\n");
7274a8c2 1666 /* One shot, path B LOK & IQK */
4c48869f 1667 RTPRINT(rtlpriv, FINIT, INIT_IQK, "One shot, path A LOK & IQK!\n");
7274a8c2
CL		 1668 rtl_set_bbreg(hw, 0xe60, BMASKDWORD, 0x00000002);
1669 rtl_set_bbreg(hw, 0xe60, BMASKDWORD, 0x00000000);
1670 /* delay x ms */
1671 RTPRINT(rtlpriv, FINIT, INIT_IQK,
4c48869f 1672 "Delay %d ms for One shot, path B LOK & IQK\n", IQK_DELAY_TIME);
faeef8ac 1673 mdelay(IQK_DELAY_TIME);
7274a8c2
CL		 1674 /* Check failed */
1675 regeac = rtl_get_bbreg(hw, 0xeac, BMASKDWORD);
4c48869f 1676 RTPRINT(rtlpriv, FINIT, INIT_IQK, "0xeac = 0x%x\n", regeac);
7274a8c2 1677 regeb4 = rtl_get_bbreg(hw, 0xeb4, BMASKDWORD);
4c48869f 1678 RTPRINT(rtlpriv, FINIT, INIT_IQK, "0xeb4 = 0x%x\n", regeb4);
7274a8c2 1679 regebc = rtl_get_bbreg(hw, 0xebc, BMASKDWORD);
4c48869f 1680 RTPRINT(rtlpriv, FINIT, INIT_IQK, "0xebc = 0x%x\n", regebc);
7274a8c2 1681 regec4 = rtl_get_bbreg(hw, 0xec4, BMASKDWORD);
4c48869f 1682 RTPRINT(rtlpriv, FINIT, INIT_IQK, "0xec4 = 0x%x\n", regec4);
7274a8c2 1683 regecc = rtl_get_bbreg(hw, 0xecc, BMASKDWORD);
4c48869f 1684 RTPRINT(rtlpriv, FINIT, INIT_IQK, "0xecc = 0x%x\n", regecc);
7274a8c2
CL		 1685 if (!(regeac & BIT(31)) && (((regeb4 & 0x03FF0000) >> 16) != 0x142) &&
1686 (((regebc & 0x03FF0000) >> 16) != 0x42))
1687 result |= 0x01;
1688 else
1689 return result;
1690 if (!(regeac & BIT(30)) && (((regec4 & 0x03FF0000) >> 16) != 0x132) &&
1691 (((regecc & 0x03FF0000) >> 16) != 0x36))
1692 result |= 0x02;
1693 else
4c48869f 1694 RTPRINT(rtlpriv, FINIT, INIT_IQK, "Path B Rx IQK fail!!\n");
7274a8c2
CL		 1695 return result;
1696}
1697
1698/* bit0 = 1 => Tx OK, bit1 = 1 => Rx OK */
1699static u8 _rtl92d_phy_pathb_iqk_5g_normal(struct ieee80211_hw *hw)
1700{
1701 struct rtl_priv *rtlpriv = rtl_priv(hw);
1702 struct rtl_phy *rtlphy = &(rtlpriv->phy);
1703 u32 regeac, regeb4, regebc, regec4, regecc;
1704 u8 result = 0;
1705 u8 i;
1706 u8 retrycount = 2;
1707
4c48869f 1708 RTPRINT(rtlpriv, FINIT, INIT_IQK, "Path B IQK!\n");
7274a8c2 1709 /* path-A IQK setting */
4c48869f 1710 RTPRINT(rtlpriv, FINIT, INIT_IQK, "Path-A IQK setting!\n");
7274a8c2
CL		 1711 rtl_set_bbreg(hw, 0xe30, BMASKDWORD, 0x18008c1f);
1712 rtl_set_bbreg(hw, 0xe34, BMASKDWORD, 0x18008c1f);
1713 rtl_set_bbreg(hw, 0xe38, BMASKDWORD, 0x82110000);
1714 rtl_set_bbreg(hw, 0xe3c, BMASKDWORD, 0x68110000);
1715
1716 /* path-B IQK setting */
1717 rtl_set_bbreg(hw, 0xe50, BMASKDWORD, 0x18008c2f);
1718 rtl_set_bbreg(hw, 0xe54, BMASKDWORD, 0x18008c2f);
1719 rtl_set_bbreg(hw, 0xe58, BMASKDWORD, 0x82140307);
1720 rtl_set_bbreg(hw, 0xe5c, BMASKDWORD, 0x68160960);
1721
1722 /* LO calibration setting */
4c48869f 1723 RTPRINT(rtlpriv, FINIT, INIT_IQK, "LO calibration setting!\n");
7274a8c2
CL		 1724 rtl_set_bbreg(hw, 0xe4c, BMASKDWORD, 0x00462911);
1725
1726 /* path-B PA on */
1727 rtl_set_bbreg(hw, RFPGA0_XAB_RFINTERFACESW, BMASKDWORD, 0x0f600700);
1728 rtl_set_bbreg(hw, RFPGA0_XB_RFINTERFACEOE, BMASKDWORD, 0x061f0d30);
1729
1730 for (i = 0; i < retrycount; i++) {
1731 /* One shot, path B LOK & IQK */
1732 RTPRINT(rtlpriv, FINIT, INIT_IQK,
4c48869f 1733 "One shot, path A LOK & IQK!\n");
7274a8c2
CL		 1734 rtl_set_bbreg(hw, 0xe48, BMASKDWORD, 0xfa000000);
1735 rtl_set_bbreg(hw, 0xe48, BMASKDWORD, 0xf8000000);
1736
1737 /* delay x ms */
1738 RTPRINT(rtlpriv, FINIT, INIT_IQK,
4c48869f 1739 "Delay %d ms for One shot, path B LOK & IQK.\n", 10);
faeef8ac 1740 mdelay(IQK_DELAY_TIME * 10);
7274a8c2
CL		 1741
1742 /* Check failed */
1743 regeac = rtl_get_bbreg(hw, 0xeac, BMASKDWORD);
4c48869f 1744 RTPRINT(rtlpriv, FINIT, INIT_IQK, "0xeac = 0x%x\n", regeac);
7274a8c2 1745 regeb4 = rtl_get_bbreg(hw, 0xeb4, BMASKDWORD);
4c48869f 1746 RTPRINT(rtlpriv, FINIT, INIT_IQK, "0xeb4 = 0x%x\n", regeb4);
7274a8c2 1747 regebc = rtl_get_bbreg(hw, 0xebc, BMASKDWORD);
4c48869f 1748 RTPRINT(rtlpriv, FINIT, INIT_IQK, "0xebc = 0x%x\n", regebc);
7274a8c2 1749 regec4 = rtl_get_bbreg(hw, 0xec4, BMASKDWORD);
4c48869f 1750 RTPRINT(rtlpriv, FINIT, INIT_IQK, "0xec4 = 0x%x\n", regec4);
7274a8c2 1751 regecc = rtl_get_bbreg(hw, 0xecc, BMASKDWORD);
4c48869f 1752 RTPRINT(rtlpriv, FINIT, INIT_IQK, "0xecc = 0x%x\n", regecc);
7274a8c2
CL		 1753 if (!(regeac & BIT(31)) &&
1754 (((regeb4 & 0x03FF0000) >> 16) != 0x142))
1755 result |= 0x01;
1756 else
1757 continue;
1758 if (!(regeac & BIT(30)) &&
1759 (((regec4 & 0x03FF0000) >> 16) != 0x132)) {
1760 result |= 0x02;
1761 break;
1762 } else {
1763 RTPRINT(rtlpriv, FINIT, INIT_IQK,
4c48869f 1764 "Path B Rx IQK fail!!\n");
7274a8c2
CL		 1765 }
1766 }
1767
1768 /* path B PA off */
1769 rtl_set_bbreg(hw, RFPGA0_XAB_RFINTERFACESW, BMASKDWORD,
1770 rtlphy->iqk_bb_backup[0]);
1771 rtl_set_bbreg(hw, RFPGA0_XB_RFINTERFACEOE, BMASKDWORD,
1772 rtlphy->iqk_bb_backup[2]);
1773 return result;
1774}
1775
1776static void _rtl92d_phy_save_adda_registers(struct ieee80211_hw *hw,
1777 u32 *adda_reg, u32 *adda_backup,
1778 u32 regnum)
1779{
1780 struct rtl_priv *rtlpriv = rtl_priv(hw);
1781 u32 i;
1782
4c48869f 1783 RTPRINT(rtlpriv, FINIT, INIT_IQK, "Save ADDA parameters.\n");
7274a8c2
CL		 1784 for (i = 0; i < regnum; i++)
1785 adda_backup[i] = rtl_get_bbreg(hw, adda_reg[i], BMASKDWORD);
1786}
1787
1788static void _rtl92d_phy_save_mac_registers(struct ieee80211_hw *hw,
1789 u32 *macreg, u32 *macbackup)
1790{
1791 struct rtl_priv *rtlpriv = rtl_priv(hw);
1792 u32 i;
1793
4c48869f 1794 RTPRINT(rtlpriv, FINIT, INIT_IQK, "Save MAC parameters.\n");
7274a8c2
CL		 1795 for (i = 0; i < (IQK_MAC_REG_NUM - 1); i++)
1796 macbackup[i] = rtl_read_byte(rtlpriv, macreg[i]);
1797 macbackup[i] = rtl_read_dword(rtlpriv, macreg[i]);
1798}
1799
1800static void _rtl92d_phy_reload_adda_registers(struct ieee80211_hw *hw,
1801 u32 *adda_reg, u32 *adda_backup,
1802 u32 regnum)
1803{
1804 struct rtl_priv *rtlpriv = rtl_priv(hw);
1805 u32 i;
1806
1807 RTPRINT(rtlpriv, FINIT, INIT_IQK,
4c48869f 1808 "Reload ADDA power saving parameters !\n");
7274a8c2
CL		 1809 for (i = 0; i < regnum; i++)
1810 rtl_set_bbreg(hw, adda_reg[i], BMASKDWORD, adda_backup[i]);
1811}
1812
1813static void _rtl92d_phy_reload_mac_registers(struct ieee80211_hw *hw,
1814 u32 *macreg, u32 *macbackup)
1815{
1816 struct rtl_priv *rtlpriv = rtl_priv(hw);
1817 u32 i;
1818
4c48869f 1819 RTPRINT(rtlpriv, FINIT, INIT_IQK, "Reload MAC parameters !\n");
7274a8c2
CL		 1820 for (i = 0; i < (IQK_MAC_REG_NUM - 1); i++)
1821 rtl_write_byte(rtlpriv, macreg[i], (u8) macbackup[i]);
1822 rtl_write_byte(rtlpriv, macreg[i], macbackup[i]);
1823}
1824
1825static void _rtl92d_phy_path_adda_on(struct ieee80211_hw *hw,
1826 u32 *adda_reg, bool patha_on, bool is2t)
1827{
1828 struct rtl_priv *rtlpriv = rtl_priv(hw);
1829 u32 pathon;
1830 u32 i;
1831
4c48869f 1832 RTPRINT(rtlpriv, FINIT, INIT_IQK, "ADDA ON.\n");
7274a8c2
CL		 1833 pathon = patha_on ? 0x04db25a4 : 0x0b1b25a4;
1834 if (patha_on)
1835 pathon = rtlpriv->rtlhal.interfaceindex == 0 ?
1836 0x04db25a4 : 0x0b1b25a4;
1837 for (i = 0; i < IQK_ADDA_REG_NUM; i++)
1838 rtl_set_bbreg(hw, adda_reg[i], BMASKDWORD, pathon);
1839}
1840
1841static void _rtl92d_phy_mac_setting_calibration(struct ieee80211_hw *hw,
1842 u32 *macreg, u32 *macbackup)
1843{
1844 struct rtl_priv *rtlpriv = rtl_priv(hw);
1845 u32 i;
1846
4c48869f 1847 RTPRINT(rtlpriv, FINIT, INIT_IQK, "MAC settings for Calibration.\n");
7274a8c2
CL		 1848 rtl_write_byte(rtlpriv, macreg[0], 0x3F);
1849
1850 for (i = 1; i < (IQK_MAC_REG_NUM - 1); i++)
1851 rtl_write_byte(rtlpriv, macreg[i], (u8)(macbackup[i] &
1852 (~BIT(3))));
1853 rtl_write_byte(rtlpriv, macreg[i], (u8) (macbackup[i] & (~BIT(5))));
1854}
1855
1856static void _rtl92d_phy_patha_standby(struct ieee80211_hw *hw)
1857{
1858 struct rtl_priv *rtlpriv = rtl_priv(hw);
4c48869f 1859 RTPRINT(rtlpriv, FINIT, INIT_IQK, "Path-A standby mode!\n");
7274a8c2
CL		 1860
1861 rtl_set_bbreg(hw, 0xe28, BMASKDWORD, 0x0);
1862 rtl_set_bbreg(hw, RFPGA0_XA_LSSIPARAMETER, BMASKDWORD, 0x00010000);
1863 rtl_set_bbreg(hw, 0xe28, BMASKDWORD, 0x80800000);
1864}
1865
1866static void _rtl92d_phy_pimode_switch(struct ieee80211_hw *hw, bool pi_mode)
1867{
1868 struct rtl_priv *rtlpriv = rtl_priv(hw);
1869 u32 mode;
1870
1871 RTPRINT(rtlpriv, FINIT, INIT_IQK,
4c48869f 1872 "BB Switch to %s mode!\n", pi_mode ? "PI" : "SI");
7274a8c2
CL		 1873 mode = pi_mode ? 0x01000100 : 0x01000000;
1874 rtl_set_bbreg(hw, 0x820, BMASKDWORD, mode);
1875 rtl_set_bbreg(hw, 0x828, BMASKDWORD, mode);
1876}
1877
1878static void _rtl92d_phy_iq_calibrate(struct ieee80211_hw *hw, long result[][8],
1879 u8 t, bool is2t)
1880{
1881 struct rtl_priv *rtlpriv = rtl_priv(hw);
1882 struct rtl_phy *rtlphy = &(rtlpriv->phy);
1883 u32 i;
1884 u8 patha_ok, pathb_ok;
1885 static u32 adda_reg[IQK_ADDA_REG_NUM] = {
1886 RFPGA0_XCD_SWITCHCONTROL, 0xe6c, 0xe70, 0xe74,
1887 0xe78, 0xe7c, 0xe80, 0xe84,
1888 0xe88, 0xe8c, 0xed0, 0xed4,
1889 0xed8, 0xedc, 0xee0, 0xeec
1890 };
1891 static u32 iqk_mac_reg[IQK_MAC_REG_NUM] = {
1892 0x522, 0x550, 0x551, 0x040
1893 };
1894 static u32 iqk_bb_reg[IQK_BB_REG_NUM] = {
1895 RFPGA0_XAB_RFINTERFACESW, RFPGA0_XA_RFINTERFACEOE,
1896 RFPGA0_XB_RFINTERFACEOE, ROFDM0_TRMUXPAR,
1897 RFPGA0_XCD_RFINTERFACESW, ROFDM0_TRXPATHENABLE,
1898 RFPGA0_RFMOD, RFPGA0_ANALOGPARAMETER4,
1899 ROFDM0_XAAGCCORE1, ROFDM0_XBAGCCORE1
1900 };
1901 const u32 retrycount = 2;
1902 u32 bbvalue;
1903
4c48869f 1904 RTPRINT(rtlpriv, FINIT, INIT_IQK, "IQK for 2.4G :Start!!!\n");
7274a8c2
CL		 1905 if (t == 0) {
1906 bbvalue = rtl_get_bbreg(hw, RFPGA0_RFMOD, BMASKDWORD);
4c48869f
JP		 1907 RTPRINT(rtlpriv, FINIT, INIT_IQK, "==>0x%08x\n", bbvalue);
1908 RTPRINT(rtlpriv, FINIT, INIT_IQK, "IQ Calibration for %s\n",
1909 is2t ? "2T2R" : "1T1R");
7274a8c2
CL		 1910
1911 /* Save ADDA parameters, turn Path A ADDA on */
1912 _rtl92d_phy_save_adda_registers(hw, adda_reg,
1913 rtlphy->adda_backup, IQK_ADDA_REG_NUM);
1914 _rtl92d_phy_save_mac_registers(hw, iqk_mac_reg,
1915 rtlphy->iqk_mac_backup);
1916 _rtl92d_phy_save_adda_registers(hw, iqk_bb_reg,
1917 rtlphy->iqk_bb_backup, IQK_BB_REG_NUM);
1918 }
1919 _rtl92d_phy_path_adda_on(hw, adda_reg, true, is2t);
1920 if (t == 0)
1921 rtlphy->rfpi_enable = (u8) rtl_get_bbreg(hw,
1922 RFPGA0_XA_HSSIPARAMETER1, BIT(8));
1923
1924 /* Switch BB to PI mode to do IQ Calibration. */
1925 if (!rtlphy->rfpi_enable)
1926 _rtl92d_phy_pimode_switch(hw, true);
1927
1928 rtl_set_bbreg(hw, RFPGA0_RFMOD, BIT(24), 0x00);
1929 rtl_set_bbreg(hw, ROFDM0_TRXPATHENABLE, BMASKDWORD, 0x03a05600);
1930 rtl_set_bbreg(hw, ROFDM0_TRMUXPAR, BMASKDWORD, 0x000800e4);
1931 rtl_set_bbreg(hw, RFPGA0_XCD_RFINTERFACESW, BMASKDWORD, 0x22204000);
1932 rtl_set_bbreg(hw, RFPGA0_ANALOGPARAMETER4, 0xf00000, 0x0f);
1933 if (is2t) {
1934 rtl_set_bbreg(hw, RFPGA0_XA_LSSIPARAMETER, BMASKDWORD,
1935 0x00010000);
1936 rtl_set_bbreg(hw, RFPGA0_XB_LSSIPARAMETER, BMASKDWORD,
1937 0x00010000);
1938 }
1939 /* MAC settings */
1940 _rtl92d_phy_mac_setting_calibration(hw, iqk_mac_reg,
1941 rtlphy->iqk_mac_backup);
1942 /* Page B init */
1943 rtl_set_bbreg(hw, 0xb68, BMASKDWORD, 0x0f600000);
1944 if (is2t)
1945 rtl_set_bbreg(hw, 0xb6c, BMASKDWORD, 0x0f600000);
1946 /* IQ calibration setting */
4c48869f 1947 RTPRINT(rtlpriv, FINIT, INIT_IQK, "IQK setting!\n");
7274a8c2
CL		 1948 rtl_set_bbreg(hw, 0xe28, BMASKDWORD, 0x80800000);
1949 rtl_set_bbreg(hw, 0xe40, BMASKDWORD, 0x01007c00);
1950 rtl_set_bbreg(hw, 0xe44, BMASKDWORD, 0x01004800);
1951 for (i = 0; i < retrycount; i++) {
1952 patha_ok = _rtl92d_phy_patha_iqk(hw, is2t);
1953 if (patha_ok == 0x03) {
1954 RTPRINT(rtlpriv, FINIT, INIT_IQK,
4c48869f 1955 "Path A IQK Success!!\n");
7274a8c2
CL		 1956 result[t][0] = (rtl_get_bbreg(hw, 0xe94, BMASKDWORD) &
1957 0x3FF0000) >> 16;
1958 result[t][1] = (rtl_get_bbreg(hw, 0xe9c, BMASKDWORD) &
1959 0x3FF0000) >> 16;
1960 result[t][2] = (rtl_get_bbreg(hw, 0xea4, BMASKDWORD) &
1961 0x3FF0000) >> 16;
1962 result[t][3] = (rtl_get_bbreg(hw, 0xeac, BMASKDWORD) &
1963 0x3FF0000) >> 16;
1964 break;
1965 } else if (i == (retrycount - 1) && patha_ok == 0x01) {
1966 /* Tx IQK OK */
1967 RTPRINT(rtlpriv, FINIT, INIT_IQK,
4c48869f 1968 "Path A IQK Only Tx Success!!\n");
7274a8c2
CL		 1969
1970 result[t][0] = (rtl_get_bbreg(hw, 0xe94, BMASKDWORD) &
1971 0x3FF0000) >> 16;
1972 result[t][1] = (rtl_get_bbreg(hw, 0xe9c, BMASKDWORD) &
1973 0x3FF0000) >> 16;
1974 }
1975 }
1976 if (0x00 == patha_ok)
4c48869f 1977 RTPRINT(rtlpriv, FINIT, INIT_IQK, "Path A IQK failed!!\n");
7274a8c2
CL		 1978 if (is2t) {
1979 _rtl92d_phy_patha_standby(hw);
1980 /* Turn Path B ADDA on */
1981 _rtl92d_phy_path_adda_on(hw, adda_reg, false, is2t);
1982 for (i = 0; i < retrycount; i++) {
1983 pathb_ok = _rtl92d_phy_pathb_iqk(hw);
1984 if (pathb_ok == 0x03) {
1985 RTPRINT(rtlpriv, FINIT, INIT_IQK,
4c48869f 1986 "Path B IQK Success!!\n");
7274a8c2
CL		 1987 result[t][4] = (rtl_get_bbreg(hw, 0xeb4,
1988 BMASKDWORD) & 0x3FF0000) >> 16;
1989 result[t][5] = (rtl_get_bbreg(hw, 0xebc,
1990 BMASKDWORD) & 0x3FF0000) >> 16;
1991 result[t][6] = (rtl_get_bbreg(hw, 0xec4,
1992 BMASKDWORD) & 0x3FF0000) >> 16;
1993 result[t][7] = (rtl_get_bbreg(hw, 0xecc,
1994 BMASKDWORD) & 0x3FF0000) >> 16;
1995 break;
1996 } else if (i == (retrycount - 1) && pathb_ok == 0x01) {
1997 /* Tx IQK OK */
1998 RTPRINT(rtlpriv, FINIT, INIT_IQK,
4c48869f 1999 "Path B Only Tx IQK Success!!\n");
7274a8c2
CL		 2000 result[t][4] = (rtl_get_bbreg(hw, 0xeb4,
2001 BMASKDWORD) & 0x3FF0000) >> 16;
2002 result[t][5] = (rtl_get_bbreg(hw, 0xebc,
2003 BMASKDWORD) & 0x3FF0000) >> 16;
2004 }
2005 }
2006 if (0x00 == pathb_ok)
2007 RTPRINT(rtlpriv, FINIT, INIT_IQK,
4c48869f 2008 "Path B IQK failed!!\n");
7274a8c2
CL		 2009 }
2010
2011 /* Back to BB mode, load original value */
2012 RTPRINT(rtlpriv, FINIT, INIT_IQK,
4c48869f 2013 "IQK:Back to BB mode, load original value!\n");
7274a8c2
CL		 2014
2015 rtl_set_bbreg(hw, 0xe28, BMASKDWORD, 0);
2016 if (t != 0) {
2017 /* Switch back BB to SI mode after finish IQ Calibration. */
2018 if (!rtlphy->rfpi_enable)
2019 _rtl92d_phy_pimode_switch(hw, false);
2020 /* Reload ADDA power saving parameters */
2021 _rtl92d_phy_reload_adda_registers(hw, adda_reg,
2022 rtlphy->adda_backup, IQK_ADDA_REG_NUM);
2023 /* Reload MAC parameters */
2024 _rtl92d_phy_reload_mac_registers(hw, iqk_mac_reg,
2025 rtlphy->iqk_mac_backup);
2026 if (is2t)
2027 _rtl92d_phy_reload_adda_registers(hw, iqk_bb_reg,
2028 rtlphy->iqk_bb_backup,
2029 IQK_BB_REG_NUM);
2030 else
2031 _rtl92d_phy_reload_adda_registers(hw, iqk_bb_reg,
2032 rtlphy->iqk_bb_backup,
2033 IQK_BB_REG_NUM - 1);
2034 /* load 0xe30 IQC default value */
2035 rtl_set_bbreg(hw, 0xe30, BMASKDWORD, 0x01008c00);
2036 rtl_set_bbreg(hw, 0xe34, BMASKDWORD, 0x01008c00);
2037 }
4c48869f 2038 RTPRINT(rtlpriv, FINIT, INIT_IQK, "<==\n");
7274a8c2
CL		 2039}
2040
2041static void _rtl92d_phy_iq_calibrate_5g_normal(struct ieee80211_hw *hw,
2042 long result[][8], u8 t)
2043{
2044 struct rtl_priv *rtlpriv = rtl_priv(hw);
2045 struct rtl_phy *rtlphy = &(rtlpriv->phy);
2046 struct rtl_hal *rtlhal = &(rtlpriv->rtlhal);
2047 u8 patha_ok, pathb_ok;
2048 static u32 adda_reg[IQK_ADDA_REG_NUM] = {
2049 RFPGA0_XCD_SWITCHCONTROL, 0xe6c, 0xe70, 0xe74,
2050 0xe78, 0xe7c, 0xe80, 0xe84,
2051 0xe88, 0xe8c, 0xed0, 0xed4,
2052 0xed8, 0xedc, 0xee0, 0xeec
2053 };
2054 static u32 iqk_mac_reg[IQK_MAC_REG_NUM] = {
2055 0x522, 0x550, 0x551, 0x040
2056 };
2057 static u32 iqk_bb_reg[IQK_BB_REG_NUM] = {
2058 RFPGA0_XAB_RFINTERFACESW, RFPGA0_XA_RFINTERFACEOE,
2059 RFPGA0_XB_RFINTERFACEOE, ROFDM0_TRMUXPAR,
2060 RFPGA0_XCD_RFINTERFACESW, ROFDM0_TRXPATHENABLE,
2061 RFPGA0_RFMOD, RFPGA0_ANALOGPARAMETER4,
2062 ROFDM0_XAAGCCORE1, ROFDM0_XBAGCCORE1
2063 };
2064 u32 bbvalue;
2065 bool is2t = IS_92D_SINGLEPHY(rtlhal->version);
2066
2067 /* Note: IQ calibration must be performed after loading
2068 * PHY_REG.txt , and radio_a, radio_b.txt */
2069
4c48869f 2070 RTPRINT(rtlpriv, FINIT, INIT_IQK, "IQK for 5G NORMAL:Start!!!\n");
faeef8ac 2071 mdelay(IQK_DELAY_TIME * 20);
7274a8c2
CL		 2072 if (t == 0) {
2073 bbvalue = rtl_get_bbreg(hw, RFPGA0_RFMOD, BMASKDWORD);
4c48869f
JP		 2074 RTPRINT(rtlpriv, FINIT, INIT_IQK, "==>0x%08x\n", bbvalue);
2075 RTPRINT(rtlpriv, FINIT, INIT_IQK, "IQ Calibration for %s\n",
2076 is2t ? "2T2R" : "1T1R");
7274a8c2
CL		 2077 /* Save ADDA parameters, turn Path A ADDA on */
2078 _rtl92d_phy_save_adda_registers(hw, adda_reg,
2079 rtlphy->adda_backup,
2080 IQK_ADDA_REG_NUM);
2081 _rtl92d_phy_save_mac_registers(hw, iqk_mac_reg,
2082 rtlphy->iqk_mac_backup);
2083 if (is2t)
2084 _rtl92d_phy_save_adda_registers(hw, iqk_bb_reg,
2085 rtlphy->iqk_bb_backup,
2086 IQK_BB_REG_NUM);
2087 else
2088 _rtl92d_phy_save_adda_registers(hw, iqk_bb_reg,
2089 rtlphy->iqk_bb_backup,
2090 IQK_BB_REG_NUM - 1);
2091 }
2092 _rtl92d_phy_path_adda_on(hw, adda_reg, true, is2t);
2093 /* MAC settings */
2094 _rtl92d_phy_mac_setting_calibration(hw, iqk_mac_reg,
2095 rtlphy->iqk_mac_backup);
2096 if (t == 0)
2097 rtlphy->rfpi_enable = (u8) rtl_get_bbreg(hw,
2098 RFPGA0_XA_HSSIPARAMETER1, BIT(8));
2099 /* Switch BB to PI mode to do IQ Calibration. */
2100 if (!rtlphy->rfpi_enable)
2101 _rtl92d_phy_pimode_switch(hw, true);
2102 rtl_set_bbreg(hw, RFPGA0_RFMOD, BIT(24), 0x00);
2103 rtl_set_bbreg(hw, ROFDM0_TRXPATHENABLE, BMASKDWORD, 0x03a05600);
2104 rtl_set_bbreg(hw, ROFDM0_TRMUXPAR, BMASKDWORD, 0x000800e4);
2105 rtl_set_bbreg(hw, RFPGA0_XCD_RFINTERFACESW, BMASKDWORD, 0x22208000);
2106 rtl_set_bbreg(hw, RFPGA0_ANALOGPARAMETER4, 0xf00000, 0x0f);
2107
2108 /* Page B init */
2109 rtl_set_bbreg(hw, 0xb68, BMASKDWORD, 0x0f600000);
2110 if (is2t)
2111 rtl_set_bbreg(hw, 0xb6c, BMASKDWORD, 0x0f600000);
2112 /* IQ calibration setting */
4c48869f 2113 RTPRINT(rtlpriv, FINIT, INIT_IQK, "IQK setting!\n");
7274a8c2
CL		 2114 rtl_set_bbreg(hw, 0xe28, BMASKDWORD, 0x80800000);
2115 rtl_set_bbreg(hw, 0xe40, BMASKDWORD, 0x10007c00);
2116 rtl_set_bbreg(hw, 0xe44, BMASKDWORD, 0x01004800);
2117 patha_ok = _rtl92d_phy_patha_iqk_5g_normal(hw, is2t);
2118 if (patha_ok == 0x03) {
4c48869f 2119 RTPRINT(rtlpriv, FINIT, INIT_IQK, "Path A IQK Success!!\n");
7274a8c2
CL		 2120 result[t][0] = (rtl_get_bbreg(hw, 0xe94, BMASKDWORD) &
2121 0x3FF0000) >> 16;
2122 result[t][1] = (rtl_get_bbreg(hw, 0xe9c, BMASKDWORD) &
2123 0x3FF0000) >> 16;
2124 result[t][2] = (rtl_get_bbreg(hw, 0xea4, BMASKDWORD) &
2125 0x3FF0000) >> 16;
2126 result[t][3] = (rtl_get_bbreg(hw, 0xeac, BMASKDWORD) &
2127 0x3FF0000) >> 16;
2128 } else if (patha_ok == 0x01) { /* Tx IQK OK */
2129 RTPRINT(rtlpriv, FINIT, INIT_IQK,
4c48869f 2130 "Path A IQK Only Tx Success!!\n");
7274a8c2
CL		 2131
2132 result[t][0] = (rtl_get_bbreg(hw, 0xe94, BMASKDWORD) &
2133 0x3FF0000) >> 16;
2134 result[t][1] = (rtl_get_bbreg(hw, 0xe9c, BMASKDWORD) &
2135 0x3FF0000) >> 16;
2136 } else {
4c48869f 2137 RTPRINT(rtlpriv, FINIT, INIT_IQK, "Path A IQK Fail!!\n");
7274a8c2
CL		 2138 }
2139 if (is2t) {
2140 /* _rtl92d_phy_patha_standby(hw); */
2141 /* Turn Path B ADDA on */
2142 _rtl92d_phy_path_adda_on(hw, adda_reg, false, is2t);
2143 pathb_ok = _rtl92d_phy_pathb_iqk_5g_normal(hw);
2144 if (pathb_ok == 0x03) {
2145 RTPRINT(rtlpriv, FINIT, INIT_IQK,
4c48869f 2146 "Path B IQK Success!!\n");
7274a8c2
CL		 2147 result[t][4] = (rtl_get_bbreg(hw, 0xeb4, BMASKDWORD) &
2148 0x3FF0000) >> 16;
2149 result[t][5] = (rtl_get_bbreg(hw, 0xebc, BMASKDWORD) &
2150 0x3FF0000) >> 16;
2151 result[t][6] = (rtl_get_bbreg(hw, 0xec4, BMASKDWORD) &
2152 0x3FF0000) >> 16;
2153 result[t][7] = (rtl_get_bbreg(hw, 0xecc, BMASKDWORD) &
2154 0x3FF0000) >> 16;
2155 } else if (pathb_ok == 0x01) { /* Tx IQK OK */
2156 RTPRINT(rtlpriv, FINIT, INIT_IQK,
4c48869f 2157 "Path B Only Tx IQK Success!!\n");
7274a8c2
CL		 2158 result[t][4] = (rtl_get_bbreg(hw, 0xeb4, BMASKDWORD) &
2159 0x3FF0000) >> 16;
2160 result[t][5] = (rtl_get_bbreg(hw, 0xebc, BMASKDWORD) &
2161 0x3FF0000) >> 16;
2162 } else {
2163 RTPRINT(rtlpriv, FINIT, INIT_IQK,
4c48869f 2164 "Path B IQK failed!!\n");
7274a8c2
CL		 2165 }
2166 }
2167
2168 /* Back to BB mode, load original value */
2169 RTPRINT(rtlpriv, FINIT, INIT_IQK,
4c48869f 2170 "IQK:Back to BB mode, load original value!\n");
7274a8c2
CL		 2171 rtl_set_bbreg(hw, 0xe28, BMASKDWORD, 0);
2172 if (t != 0) {
2173 if (is2t)
2174 _rtl92d_phy_reload_adda_registers(hw, iqk_bb_reg,
2175 rtlphy->iqk_bb_backup,
2176 IQK_BB_REG_NUM);
2177 else
2178 _rtl92d_phy_reload_adda_registers(hw, iqk_bb_reg,
2179 rtlphy->iqk_bb_backup,
2180 IQK_BB_REG_NUM - 1);
2181 /* Reload MAC parameters */
2182 _rtl92d_phy_reload_mac_registers(hw, iqk_mac_reg,
2183 rtlphy->iqk_mac_backup);
2184 /* Switch back BB to SI mode after finish IQ Calibration. */
2185 if (!rtlphy->rfpi_enable)
2186 _rtl92d_phy_pimode_switch(hw, false);
2187 /* Reload ADDA power saving parameters */
2188 _rtl92d_phy_reload_adda_registers(hw, adda_reg,
2189 rtlphy->adda_backup,
2190 IQK_ADDA_REG_NUM);
2191 }
4c48869f 2192 RTPRINT(rtlpriv, FINIT, INIT_IQK, "<==\n");
7274a8c2
CL		 2193}
2194
2195static bool _rtl92d_phy_simularity_compare(struct ieee80211_hw *hw,
2196 long result[][8], u8 c1, u8 c2)
2197{
2198 struct rtl_priv *rtlpriv = rtl_priv(hw);
2199 struct rtl_hal *rtlhal = &(rtlpriv->rtlhal);
2200 u32 i, j, diff, sim_bitmap, bound;
2201 u8 final_candidate[2] = {0xFF, 0xFF}; /* for path A and path B */
2202 bool bresult = true;
2203 bool is2t = IS_92D_SINGLEPHY(rtlhal->version);
2204
2205 if (is2t)
2206 bound = 8;
2207 else
2208 bound = 4;
2209 sim_bitmap = 0;
2210 for (i = 0; i < bound; i++) {
2211 diff = (result[c1][i] > result[c2][i]) ? (result[c1][i] -
2212 result[c2][i]) : (result[c2][i] - result[c1][i]);
2213 if (diff > MAX_TOLERANCE_92D) {
2214 if ((i == 2 || i == 6) && !sim_bitmap) {
2215 if (result[c1][i] + result[c1][i + 1] == 0)
2216 final_candidate[(i / 4)] = c2;
2217 else if (result[c2][i] + result[c2][i + 1] == 0)
2218 final_candidate[(i / 4)] = c1;
2219 else
2220 sim_bitmap = sim_bitmap | (1 << i);
2221 } else {
2222 sim_bitmap = sim_bitmap | (1 << i);
2223 }
2224 }
2225 }
2226 if (sim_bitmap == 0) {
2227 for (i = 0; i < (bound / 4); i++) {
2228 if (final_candidate[i] != 0xFF) {
2229 for (j = i * 4; j < (i + 1) * 4 - 2; j++)
2230 result[3][j] =
2231 result[final_candidate[i]][j];
2232 bresult = false;
2233 }
2234 }
2235 return bresult;
2236 }
2237 if (!(sim_bitmap & 0x0F)) { /* path A OK */
2238 for (i = 0; i < 4; i++)
2239 result[3][i] = result[c1][i];
2240 } else if (!(sim_bitmap & 0x03)) { /* path A, Tx OK */
2241 for (i = 0; i < 2; i++)
2242 result[3][i] = result[c1][i];
2243 }
2244 if (!(sim_bitmap & 0xF0) && is2t) { /* path B OK */
2245 for (i = 4; i < 8; i++)
2246 result[3][i] = result[c1][i];
2247 } else if (!(sim_bitmap & 0x30)) { /* path B, Tx OK */
2248 for (i = 4; i < 6; i++)
2249 result[3][i] = result[c1][i];
2250 }
2251 return false;
2252}
2253
2254static void _rtl92d_phy_patha_fill_iqk_matrix(struct ieee80211_hw *hw,
2255 bool iqk_ok, long result[][8],
2256 u8 final_candidate, bool txonly)
2257{
2258 struct rtl_priv *rtlpriv = rtl_priv(hw);
2259 struct rtl_hal *rtlhal = &(rtlpriv->rtlhal);
2260 u32 oldval_0, val_x, tx0_a, reg;
2261 long val_y, tx0_c;
2262 bool is2t = IS_92D_SINGLEPHY(rtlhal->version) ||
2263 rtlhal->macphymode == DUALMAC_DUALPHY;
2264
2265 RTPRINT(rtlpriv, FINIT, INIT_IQK,
4c48869f 2266 "Path A IQ Calibration %s !\n", iqk_ok ? "Success" : "Failed");
7274a8c2
CL		 2267 if (final_candidate == 0xFF) {
2268 return;
2269 } else if (iqk_ok) {
2270 oldval_0 = (rtl_get_bbreg(hw, ROFDM0_XATxIQIMBALANCE,
2271 BMASKDWORD) >> 22) & 0x3FF; /* OFDM0_D */
2272 val_x = result[final_candidate][0];
2273 if ((val_x & 0x00000200) != 0)
2274 val_x = val_x | 0xFFFFFC00;
2275 tx0_a = (val_x * oldval_0) >> 8;
4c48869f
JP		 2276 RTPRINT(rtlpriv, FINIT, INIT_IQK,
2277 "X = 0x%x, tx0_a = 0x%x, oldval_0 0x%x\n",
2278 val_x, tx0_a, oldval_0);
7274a8c2
CL		 2279 rtl_set_bbreg(hw, ROFDM0_XATxIQIMBALANCE, 0x3FF, tx0_a);
2280 rtl_set_bbreg(hw, ROFDM0_ECCATHRESHOLD, BIT(24),
2281 ((val_x * oldval_0 >> 7) & 0x1));
2282 val_y = result[final_candidate][1];
2283 if ((val_y & 0x00000200) != 0)
2284 val_y = val_y | 0xFFFFFC00;
2285 /* path B IQK result + 3 */
2286 if (rtlhal->interfaceindex == 1 &&
2287 rtlhal->current_bandtype == BAND_ON_5G)
2288 val_y += 3;
2289 tx0_c = (val_y * oldval_0) >> 8;
4c48869f
JP		 2290 RTPRINT(rtlpriv, FINIT, INIT_IQK,
2291 "Y = 0x%lx, tx0_c = 0x%lx\n",
2292 val_y, tx0_c);
7274a8c2
CL		 2293 rtl_set_bbreg(hw, ROFDM0_XCTxAFE, 0xF0000000,
2294 ((tx0_c & 0x3C0) >> 6));
2295 rtl_set_bbreg(hw, ROFDM0_XATxIQIMBALANCE, 0x003F0000,
2296 (tx0_c & 0x3F));
2297 if (is2t)
2298 rtl_set_bbreg(hw, ROFDM0_ECCATHRESHOLD, BIT(26),
2299 ((val_y * oldval_0 >> 7) & 0x1));
4c48869f
JP		 2300 RTPRINT(rtlpriv, FINIT, INIT_IQK, "0xC80 = 0x%x\n",
2301 rtl_get_bbreg(hw, ROFDM0_XATxIQIMBALANCE,
2302 BMASKDWORD));
7274a8c2 2303 if (txonly) {
4c48869f 2304 RTPRINT(rtlpriv, FINIT, INIT_IQK, "only Tx OK\n");
7274a8c2
CL		 2305 return;
2306 }
2307 reg = result[final_candidate][2];
2308 rtl_set_bbreg(hw, ROFDM0_XARXIQIMBALANCE, 0x3FF, reg);
2309 reg = result[final_candidate][3] & 0x3F;
2310 rtl_set_bbreg(hw, ROFDM0_XARXIQIMBALANCE, 0xFC00, reg);
2311 reg = (result[final_candidate][3] >> 6) & 0xF;
2312 rtl_set_bbreg(hw, 0xca0, 0xF0000000, reg);
2313 }
2314}
2315
2316static void _rtl92d_phy_pathb_fill_iqk_matrix(struct ieee80211_hw *hw,
2317 bool iqk_ok, long result[][8], u8 final_candidate, bool txonly)
2318{
2319 struct rtl_priv *rtlpriv = rtl_priv(hw);
2320 struct rtl_hal *rtlhal = &(rtlpriv->rtlhal);
2321 u32 oldval_1, val_x, tx1_a, reg;
2322 long val_y, tx1_c;
2323
4c48869f
JP		 2324 RTPRINT(rtlpriv, FINIT, INIT_IQK, "Path B IQ Calibration %s !\n",
2325 iqk_ok ? "Success" : "Failed");
7274a8c2
CL		 2326 if (final_candidate == 0xFF) {
2327 return;
2328 } else if (iqk_ok) {
2329 oldval_1 = (rtl_get_bbreg(hw, ROFDM0_XBTxIQIMBALANCE,
2330 BMASKDWORD) >> 22) & 0x3FF;
2331 val_x = result[final_candidate][4];
2332 if ((val_x & 0x00000200) != 0)
2333 val_x = val_x | 0xFFFFFC00;
2334 tx1_a = (val_x * oldval_1) >> 8;
4c48869f
JP		 2335 RTPRINT(rtlpriv, FINIT, INIT_IQK, "X = 0x%x, tx1_a = 0x%x\n",
2336 val_x, tx1_a);
7274a8c2
CL		 2337 rtl_set_bbreg(hw, ROFDM0_XBTxIQIMBALANCE, 0x3FF, tx1_a);
2338 rtl_set_bbreg(hw, ROFDM0_ECCATHRESHOLD, BIT(28),
2339 ((val_x * oldval_1 >> 7) & 0x1));
2340 val_y = result[final_candidate][5];
2341 if ((val_y & 0x00000200) != 0)
2342 val_y = val_y | 0xFFFFFC00;
2343 if (rtlhal->current_bandtype == BAND_ON_5G)
2344 val_y += 3;
2345 tx1_c = (val_y * oldval_1) >> 8;
4c48869f
JP		 2346 RTPRINT(rtlpriv, FINIT, INIT_IQK, "Y = 0x%lx, tx1_c = 0x%lx\n",
2347 val_y, tx1_c);
7274a8c2
CL		 2348 rtl_set_bbreg(hw, ROFDM0_XDTxAFE, 0xF0000000,
2349 ((tx1_c & 0x3C0) >> 6));
2350 rtl_set_bbreg(hw, ROFDM0_XBTxIQIMBALANCE, 0x003F0000,
2351 (tx1_c & 0x3F));
2352 rtl_set_bbreg(hw, ROFDM0_ECCATHRESHOLD, BIT(30),
2353 ((val_y * oldval_1 >> 7) & 0x1));
2354 if (txonly)
2355 return;
2356 reg = result[final_candidate][6];
2357 rtl_set_bbreg(hw, ROFDM0_XBRXIQIMBALANCE, 0x3FF, reg);
2358 reg = result[final_candidate][7] & 0x3F;
2359 rtl_set_bbreg(hw, ROFDM0_XBRXIQIMBALANCE, 0xFC00, reg);
2360 reg = (result[final_candidate][7] >> 6) & 0xF;
2361 rtl_set_bbreg(hw, ROFDM0_AGCRSSITABLE, 0x0000F000, reg);
2362 }
2363}
2364
2365void rtl92d_phy_iq_calibrate(struct ieee80211_hw *hw)
2366{
2367 struct rtl_priv *rtlpriv = rtl_priv(hw);
2368 struct rtl_phy *rtlphy = &(rtlpriv->phy);
2369 struct rtl_hal *rtlhal = &(rtlpriv->rtlhal);
2370 long result[4][8];
2371 u8 i, final_candidate, indexforchannel;
2372 bool patha_ok, pathb_ok;
2373 long rege94, rege9c, regea4, regeac, regeb4;
2374 long regebc, regec4, regecc, regtmp = 0;
2375 bool is12simular, is13simular, is23simular;
2376 unsigned long flag = 0;
2377
2378 RTPRINT(rtlpriv, FINIT, INIT_IQK,
4c48869f 2379 "IQK:Start!!!channel %d\n", rtlphy->current_channel);
7274a8c2
CL		 2380 for (i = 0; i < 8; i++) {
2381 result[0][i] = 0;
2382 result[1][i] = 0;
2383 result[2][i] = 0;
2384 result[3][i] = 0;
2385 }
2386 final_candidate = 0xff;
2387 patha_ok = false;
2388 pathb_ok = false;
2389 is12simular = false;
2390 is23simular = false;
2391 is13simular = false;
2392 RTPRINT(rtlpriv, FINIT, INIT_IQK,
4c48869f 2393 "IQK !!!currentband %d\n", rtlhal->current_bandtype);
7274a8c2
CL		 2394 rtl92d_acquire_cckandrw_pagea_ctl(hw, &flag);
2395 for (i = 0; i < 3; i++) {
2396 if (rtlhal->current_bandtype == BAND_ON_5G) {
2397 _rtl92d_phy_iq_calibrate_5g_normal(hw, result, i);
2398 } else if (rtlhal->current_bandtype == BAND_ON_2_4G) {
2399 if (IS_92D_SINGLEPHY(rtlhal->version))
2400 _rtl92d_phy_iq_calibrate(hw, result, i, true);
2401 else
2402 _rtl92d_phy_iq_calibrate(hw, result, i, false);
2403 }
2404 if (i == 1) {
2405 is12simular = _rtl92d_phy_simularity_compare(hw, result,
2406 0, 1);
2407 if (is12simular) {
2408 final_candidate = 0;
2409 break;
2410 }
2411 }
2412 if (i == 2) {
2413 is13simular = _rtl92d_phy_simularity_compare(hw, result,
2414 0, 2);
2415 if (is13simular) {
2416 final_candidate = 0;
2417 break;
2418 }
2419 is23simular = _rtl92d_phy_simularity_compare(hw, result,
2420 1, 2);
2421 if (is23simular) {
2422 final_candidate = 1;
2423 } else {
2424 for (i = 0; i < 8; i++)
2425 regtmp += result[3][i];
2426
2427 if (regtmp != 0)
2428 final_candidate = 3;
2429 else
2430 final_candidate = 0xFF;
2431 }
2432 }
2433 }
2434 rtl92d_release_cckandrw_pagea_ctl(hw, &flag);
2435 for (i = 0; i < 4; i++) {
2436 rege94 = result[i][0];
2437 rege9c = result[i][1];
2438 regea4 = result[i][2];
2439 regeac = result[i][3];
2440 regeb4 = result[i][4];
2441 regebc = result[i][5];
2442 regec4 = result[i][6];
2443 regecc = result[i][7];
2444 RTPRINT(rtlpriv, FINIT, INIT_IQK,
4c48869f 2445 "IQK: rege94=%lx rege9c=%lx regea4=%lx regeac=%lx regeb4=%lx regebc=%lx regec4=%lx regecc=%lx\n",
7274a8c2 2446 rege94, rege9c, regea4, regeac, regeb4, regebc, regec4,
4c48869f 2447 regecc);
7274a8c2
CL		 2448 }
2449 if (final_candidate != 0xff) {
2450 rtlphy->reg_e94 = rege94 = result[final_candidate][0];
2451 rtlphy->reg_e9c = rege9c = result[final_candidate][1];
2452 regea4 = result[final_candidate][2];
2453 regeac = result[final_candidate][3];
2454 rtlphy->reg_eb4 = regeb4 = result[final_candidate][4];
2455 rtlphy->reg_ebc = regebc = result[final_candidate][5];
2456 regec4 = result[final_candidate][6];
2457 regecc = result[final_candidate][7];
2458 RTPRINT(rtlpriv, FINIT, INIT_IQK,
4c48869f 2459 "IQK: final_candidate is %x\n", final_candidate);
7274a8c2 2460 RTPRINT(rtlpriv, FINIT, INIT_IQK,
4c48869f 2461 "IQK: rege94=%lx rege9c=%lx regea4=%lx regeac=%lx regeb4=%lx regebc=%lx regec4=%lx regecc=%lx\n",
7274a8c2 2462 rege94, rege9c, regea4, regeac, regeb4, regebc, regec4,
4c48869f 2463 regecc);
7274a8c2
CL		 2464 patha_ok = pathb_ok = true;
2465 } else {
2466 rtlphy->reg_e94 = rtlphy->reg_eb4 = 0x100; /* X default value */
2467 rtlphy->reg_e9c = rtlphy->reg_ebc = 0x0; /* Y default value */
2468 }
2469 if ((rege94 != 0) /*&&(regea4 != 0) */)
2470 _rtl92d_phy_patha_fill_iqk_matrix(hw, patha_ok, result,
2471 final_candidate, (regea4 == 0));
2472 if (IS_92D_SINGLEPHY(rtlhal->version)) {
2473 if ((regeb4 != 0) /*&&(regec4 != 0) */)
2474 _rtl92d_phy_pathb_fill_iqk_matrix(hw, pathb_ok, result,
2475 final_candidate, (regec4 == 0));
2476 }
2477 if (final_candidate != 0xFF) {
2478 indexforchannel = rtl92d_get_rightchnlplace_for_iqk(
2479 rtlphy->current_channel);
2480
2481 for (i = 0; i < IQK_MATRIX_REG_NUM; i++)
e6deaf81 2482 rtlphy->iqk_matrix[indexforchannel].
7274a8c2 2483 value[0][i] = result[final_candidate][i];
e6deaf81 2484 rtlphy->iqk_matrix[indexforchannel].iqk_done =
7274a8c2
CL		 2485 true;
2486
2487 RT_TRACE(rtlpriv, COMP_SCAN | COMP_MLME, DBG_LOUD,
f30d7507 2488 "IQK OK indexforchannel %d\n", indexforchannel);
7274a8c2
CL		 2489 }
2490}
2491
2492void rtl92d_phy_reload_iqk_setting(struct ieee80211_hw *hw, u8 channel)
2493{
2494 struct rtl_priv *rtlpriv = rtl_priv(hw);
2495 struct rtl_phy *rtlphy = &(rtlpriv->phy);
2496 struct rtl_hal *rtlhal = &(rtlpriv->rtlhal);
2497 u8 indexforchannel;
2498
f30d7507 2499 RT_TRACE(rtlpriv, COMP_CMD, DBG_LOUD, "channel %d\n", channel);
7274a8c2
CL		 2500 /*------Do IQK for normal chip and test chip 5G band------- */
2501 indexforchannel = rtl92d_get_rightchnlplace_for_iqk(channel);
f30d7507
JP		 2502 RT_TRACE(rtlpriv, COMP_CMD, DBG_LOUD, "indexforchannel %d done %d\n",
2503 indexforchannel,
e6deaf81
LF		 2504 rtlphy->iqk_matrix[indexforchannel].iqk_done);
2505 if (0 && !rtlphy->iqk_matrix[indexforchannel].iqk_done &&
7274a8c2
CL		 2506 rtlphy->need_iqk) {
2507 /* Re Do IQK. */
2508 RT_TRACE(rtlpriv, COMP_SCAN | COMP_INIT, DBG_LOUD,
f30d7507 2509 "Do IQK Matrix reg for channel:%d....\n", channel);
7274a8c2
CL		 2510 rtl92d_phy_iq_calibrate(hw);
2511 } else {
2512 /* Just load the value. */
2513 /* 2G band just load once. */
2514 if (((!rtlhal->load_imrandiqk_setting_for2g) &&
2515 indexforchannel == 0) || indexforchannel > 0) {
2516 RT_TRACE(rtlpriv, COMP_SCAN, DBG_LOUD,
f30d7507
JP		 2517 "Just Read IQK Matrix reg for channel:%d....\n",
2518 channel);
e6deaf81 2519 if ((rtlphy->iqk_matrix[indexforchannel].
7274a8c2
CL		 2520 value[0] != NULL)
2521 /*&&(regea4 != 0) */)
2522 _rtl92d_phy_patha_fill_iqk_matrix(hw, true,
e6deaf81 2523 rtlphy->iqk_matrix[
7274a8c2 2524 indexforchannel].value, 0,
e6deaf81 2525 (rtlphy->iqk_matrix[
7274a8c2
CL		 2526 indexforchannel].value[0][2] == 0));
2527 if (IS_92D_SINGLEPHY(rtlhal->version)) {
e6deaf81 2528 if ((rtlphy->iqk_matrix[
7274a8c2
CL		 2529 indexforchannel].value[0][4] != 0)
2530 /*&&(regec4 != 0) */)
2531 _rtl92d_phy_pathb_fill_iqk_matrix(hw,
2532 true,
e6deaf81 2533 rtlphy->iqk_matrix[
7274a8c2 2534 indexforchannel].value, 0,
e6deaf81 2535 (rtlphy->iqk_matrix[
7274a8c2
CL		 2536 indexforchannel].value[0][6]
2537 == 0));
2538 }
2539 }
2540 }
2541 rtlphy->need_iqk = false;
f30d7507 2542 RT_TRACE(rtlpriv, COMP_CMD, DBG_LOUD, "<====\n");
7274a8c2
CL		 2543}
2544
2545static u32 _rtl92d_phy_get_abs(u32 val1, u32 val2)
2546{
2547 u32 ret;
2548
2549 if (val1 >= val2)
2550 ret = val1 - val2;
2551 else
2552 ret = val2 - val1;
2553 return ret;
2554}
2555
2556static bool _rtl92d_is_legal_5g_channel(struct ieee80211_hw *hw, u8 channel)
2557{
2558
2559 int i;
2560 u8 channel_5g[45] = {
2561 36, 38, 40, 42, 44, 46, 48, 50, 52, 54, 56, 58,
2562 60, 62, 64, 100, 102, 104, 106, 108, 110, 112,
2563 114, 116, 118, 120, 122, 124, 126, 128, 130, 132,
2564 134, 136, 138, 140, 149, 151, 153, 155, 157, 159,
2565 161, 163, 165
2566 };
2567
2568 for (i = 0; i < sizeof(channel_5g); i++)
2569 if (channel == channel_5g[i])
2570 return true;
2571 return false;
2572}
2573
2574static void _rtl92d_phy_calc_curvindex(struct ieee80211_hw *hw,
2575 u32 *targetchnl, u32 * curvecount_val,
2576 bool is5g, u32 *curveindex)
2577{
2578 struct rtl_priv *rtlpriv = rtl_priv(hw);
2579 u32 smallest_abs_val = 0xffffffff, u4tmp;
2580 u8 i, j;
2581 u8 chnl_num = is5g ? TARGET_CHNL_NUM_5G : TARGET_CHNL_NUM_2G;
2582
2583 for (i = 0; i < chnl_num; i++) {
2584 if (is5g && !_rtl92d_is_legal_5g_channel(hw, i + 1))
2585 continue;
2586 curveindex[i] = 0;
2587 for (j = 0; j < (CV_CURVE_CNT * 2); j++) {
2588 u4tmp = _rtl92d_phy_get_abs(targetchnl[i],
2589 curvecount_val[j]);
2590
2591 if (u4tmp < smallest_abs_val) {
2592 curveindex[i] = j;
2593 smallest_abs_val = u4tmp;
2594 }
2595 }
2596 smallest_abs_val = 0xffffffff;
4c48869f
JP		 2597 RTPRINT(rtlpriv, FINIT, INIT_IQK, "curveindex[%d] = %x\n",
2598 i, curveindex[i]);
7274a8c2
CL		 2599 }
2600}
2601
2602static void _rtl92d_phy_reload_lck_setting(struct ieee80211_hw *hw,
2603 u8 channel)
2604{
2605 struct rtl_priv *rtlpriv = rtl_priv(hw);
2606 u8 erfpath = rtlpriv->rtlhal.current_bandtype ==
2607 BAND_ON_5G ? RF90_PATH_A :
2608 IS_92D_SINGLEPHY(rtlpriv->rtlhal.version) ?
2609 RF90_PATH_B : RF90_PATH_A;
2610 u32 u4tmp = 0, u4regvalue = 0;
2611 bool bneed_powerdown_radio = false;
2612
f30d7507 2613 RT_TRACE(rtlpriv, COMP_CMD, DBG_LOUD, "path %d\n", erfpath);
4c48869f
JP		 2614 RTPRINT(rtlpriv, FINIT, INIT_IQK, "band type = %d\n",
2615 rtlpriv->rtlhal.current_bandtype);
2616 RTPRINT(rtlpriv, FINIT, INIT_IQK, "channel = %d\n", channel);
7274a8c2
CL		 2617 if (rtlpriv->rtlhal.current_bandtype == BAND_ON_5G) {/* Path-A for 5G */
2618 u4tmp = curveindex_5g[channel-1];
2619 RTPRINT(rtlpriv, FINIT, INIT_IQK,
4c48869f 2620 "ver 1 set RF-A, 5G, 0x28 = 0x%ulx !!\n", u4tmp);
7274a8c2
CL		 2621 if (rtlpriv->rtlhal.macphymode == DUALMAC_DUALPHY &&
2622 rtlpriv->rtlhal.interfaceindex == 1) {
2623 bneed_powerdown_radio =
2624 rtl92d_phy_enable_anotherphy(hw, false);
2625 rtlpriv->rtlhal.during_mac1init_radioa = true;
2626 /* asume no this case */
2627 if (bneed_powerdown_radio)
2628 _rtl92d_phy_enable_rf_env(hw, erfpath,
2629 &u4regvalue);
2630 }
2631 rtl_set_rfreg(hw, erfpath, RF_SYN_G4, 0x3f800, u4tmp);
2632 if (bneed_powerdown_radio)
2633 _rtl92d_phy_restore_rf_env(hw, erfpath, &u4regvalue);
2634 if (rtlpriv->rtlhal.during_mac1init_radioa)
2635 rtl92d_phy_powerdown_anotherphy(hw, false);
2636 } else if (rtlpriv->rtlhal.current_bandtype == BAND_ON_2_4G) {
2637 u4tmp = curveindex_2g[channel-1];
2638 RTPRINT(rtlpriv, FINIT, INIT_IQK,
4c48869f 2639 "ver 3 set RF-B, 2G, 0x28 = 0x%ulx !!\n", u4tmp);
7274a8c2
CL		 2640 if (rtlpriv->rtlhal.macphymode == DUALMAC_DUALPHY &&
2641 rtlpriv->rtlhal.interfaceindex == 0) {
2642 bneed_powerdown_radio =
2643 rtl92d_phy_enable_anotherphy(hw, true);
2644 rtlpriv->rtlhal.during_mac0init_radiob = true;
2645 if (bneed_powerdown_radio)
2646 _rtl92d_phy_enable_rf_env(hw, erfpath,
2647 &u4regvalue);
2648 }
2649 rtl_set_rfreg(hw, erfpath, RF_SYN_G4, 0x3f800, u4tmp);
2650 RTPRINT(rtlpriv, FINIT, INIT_IQK,
4c48869f
JP		 2651 "ver 3 set RF-B, 2G, 0x28 = 0x%ulx !!\n",
2652 rtl_get_rfreg(hw, erfpath, RF_SYN_G4, 0x3f800));
7274a8c2
CL		 2653 if (bneed_powerdown_radio)
2654 _rtl92d_phy_restore_rf_env(hw, erfpath, &u4regvalue);
2655 if (rtlpriv->rtlhal.during_mac0init_radiob)
2656 rtl92d_phy_powerdown_anotherphy(hw, true);
2657 }
f30d7507 2658 RT_TRACE(rtlpriv, COMP_CMD, DBG_LOUD, "<====\n");
7274a8c2
CL		 2659}
2660
2661static void _rtl92d_phy_lc_calibrate_sw(struct ieee80211_hw *hw, bool is2t)
2662{
2663 struct rtl_priv *rtlpriv = rtl_priv(hw);
2664 struct rtl_hal *rtlhal = &(rtlpriv->rtlhal);
2665 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
2666 u8 tmpreg, index, rf_mode[2];
2667 u8 path = is2t ? 2 : 1;
2668 u8 i;
2669 u32 u4tmp, offset;
2670 u32 curvecount_val[CV_CURVE_CNT * 2] = {0};
2671 u16 timeout = 800, timecount = 0;
2672
2673 /* Check continuous TX and Packet TX */
2674 tmpreg = rtl_read_byte(rtlpriv, 0xd03);
2675 /* if Deal with contisuous TX case, disable all continuous TX */
2676 /* if Deal with Packet TX case, block all queues */
2677 if ((tmpreg & 0x70) != 0)
2678 rtl_write_byte(rtlpriv, 0xd03, tmpreg & 0x8F);
2679 else
2680 rtl_write_byte(rtlpriv, REG_TXPAUSE, 0xFF);
2681 rtl_set_bbreg(hw, RFPGA0_ANALOGPARAMETER4, 0xF00000, 0x0F);
2682 for (index = 0; index < path; index++) {
2683 /* 1. Read original RF mode */
2684 offset = index == 0 ? ROFDM0_XAAGCCORE1 : ROFDM0_XBAGCCORE1;
2685 rf_mode[index] = rtl_read_byte(rtlpriv, offset);
2686 /* 2. Set RF mode = standby mode */
2687 rtl_set_rfreg(hw, (enum radio_path)index, RF_AC,
2688 BRFREGOFFSETMASK, 0x010000);
2689 if (rtlpci->init_ready) {
2690 /* switch CV-curve control by LC-calibration */
2691 rtl_set_rfreg(hw, (enum radio_path)index, RF_SYN_G7,
2692 BIT(17), 0x0);
2693 /* 4. Set LC calibration begin */
2694 rtl_set_rfreg(hw, (enum radio_path)index, RF_CHNLBW,
2695 0x08000, 0x01);
2696 }
2697 u4tmp = rtl_get_rfreg(hw, (enum radio_path)index, RF_SYN_G6,
2698 BRFREGOFFSETMASK);
2699 while ((!(u4tmp & BIT(11))) && timecount <= timeout) {
2700 mdelay(50);
2701 timecount += 50;
2702 u4tmp = rtl_get_rfreg(hw, (enum radio_path)index,
2703 RF_SYN_G6, BRFREGOFFSETMASK);
2704 }
2705 RTPRINT(rtlpriv, FINIT, INIT_IQK,
4c48869f 2706 "PHY_LCK finish delay for %d ms=2\n", timecount);
7274a8c2
CL		 2707 u4tmp = rtl_get_rfreg(hw, index, RF_SYN_G4, BRFREGOFFSETMASK);
2708 if (index == 0 && rtlhal->interfaceindex == 0) {
2709 RTPRINT(rtlpriv, FINIT, INIT_IQK,
4c48869f 2710 "path-A / 5G LCK\n");
7274a8c2
CL		 2711 } else {
2712 RTPRINT(rtlpriv, FINIT, INIT_IQK,
4c48869f 2713 "path-B / 2.4G LCK\n");
7274a8c2
CL		 2714 }
2715 memset(&curvecount_val[0], 0, CV_CURVE_CNT * 2);
2716 /* Set LC calibration off */
2717 rtl_set_rfreg(hw, (enum radio_path)index, RF_CHNLBW,
2718 0x08000, 0x0);
4c48869f 2719 RTPRINT(rtlpriv, FINIT, INIT_IQK, "set RF 0x18[15] = 0\n");
7274a8c2
CL		 2720 /* save Curve-counting number */
2721 for (i = 0; i < CV_CURVE_CNT; i++) {
2722 u32 readval = 0, readval2 = 0;
2723 rtl_set_rfreg(hw, (enum radio_path)index, 0x3F,
2724 0x7f, i);
2725
2726 rtl_set_rfreg(hw, (enum radio_path)index, 0x4D,
2727 BRFREGOFFSETMASK, 0x0);
2728 readval = rtl_get_rfreg(hw, (enum radio_path)index,
2729 0x4F, BRFREGOFFSETMASK);
2730 curvecount_val[2 * i + 1] = (readval & 0xfffe0) >> 5;
2731 /* reg 0x4f [4:0] */
2732 /* reg 0x50 [19:10] */
2733 readval2 = rtl_get_rfreg(hw, (enum radio_path)index,
2734 0x50, 0xffc00);
2735 curvecount_val[2 * i] = (((readval & 0x1F) << 10) |
2736 readval2);
2737 }
2738 if (index == 0 && rtlhal->interfaceindex == 0)
2739 _rtl92d_phy_calc_curvindex(hw, targetchnl_5g,
2740 curvecount_val,
2741 true, curveindex_5g);
2742 else
2743 _rtl92d_phy_calc_curvindex(hw, targetchnl_2g,
2744 curvecount_val,
2745 false, curveindex_2g);
2746 /* switch CV-curve control mode */
2747 rtl_set_rfreg(hw, (enum radio_path)index, RF_SYN_G7,
2748 BIT(17), 0x1);
2749 }
2750
2751 /* Restore original situation */
2752 for (index = 0; index < path; index++) {
2753 offset = index == 0 ? ROFDM0_XAAGCCORE1 : ROFDM0_XBAGCCORE1;
2754 rtl_write_byte(rtlpriv, offset, 0x50);
2755 rtl_write_byte(rtlpriv, offset, rf_mode[index]);
2756 }
2757 if ((tmpreg & 0x70) != 0)
2758 rtl_write_byte(rtlpriv, 0xd03, tmpreg);
2759 else /*Deal with Packet TX case */
2760 rtl_write_byte(rtlpriv, REG_TXPAUSE, 0x00);
2761 rtl_set_bbreg(hw, RFPGA0_ANALOGPARAMETER4, 0xF00000, 0x00);
2762 _rtl92d_phy_reload_lck_setting(hw, rtlpriv->phy.current_channel);
2763}
2764
2765static void _rtl92d_phy_lc_calibrate(struct ieee80211_hw *hw, bool is2t)
2766{
2767 struct rtl_priv *rtlpriv = rtl_priv(hw);
2768
4c48869f 2769 RTPRINT(rtlpriv, FINIT, INIT_IQK, "cosa PHY_LCK ver=2\n");
7274a8c2
CL		 2770 _rtl92d_phy_lc_calibrate_sw(hw, is2t);
2771}
2772
2773void rtl92d_phy_lc_calibrate(struct ieee80211_hw *hw)
2774{
2775 struct rtl_priv *rtlpriv = rtl_priv(hw);
2776 struct rtl_phy *rtlphy = &(rtlpriv->phy);
2777 struct rtl_hal *rtlhal = &(rtlpriv->rtlhal);
2778 u32 timeout = 2000, timecount = 0;
2779
2780 while (rtlpriv->mac80211.act_scanning && timecount < timeout) {
2781 udelay(50);
2782 timecount += 50;
2783 }
2784
2785 rtlphy->lck_inprogress = true;
2786 RTPRINT(rtlpriv, FINIT, INIT_IQK,
4c48869f
JP		 2787 "LCK:Start!!! currentband %x delay %d ms\n",
2788 rtlhal->current_bandtype, timecount);
7274a8c2
CL		 2789 if (IS_92D_SINGLEPHY(rtlhal->version)) {
2790 _rtl92d_phy_lc_calibrate(hw, true);
2791 } else {
2792 /* For 1T1R */
2793 _rtl92d_phy_lc_calibrate(hw, false);
2794 }
2795 rtlphy->lck_inprogress = false;
4c48869f 2796 RTPRINT(rtlpriv, FINIT, INIT_IQK, "LCK:Finish!!!\n");
7274a8c2
CL		 2797}
2798
2799void rtl92d_phy_ap_calibrate(struct ieee80211_hw *hw, char delta)
2800{
2801 return;
2802}
2803
2804static bool _rtl92d_phy_set_sw_chnl_cmdarray(struct swchnlcmd *cmdtable,
2805 u32 cmdtableidx, u32 cmdtablesz, enum swchnlcmd_id cmdid,
2806 u32 para1, u32 para2, u32 msdelay)
2807{
2808 struct swchnlcmd *pcmd;
2809
2810 if (cmdtable == NULL) {
9d833ed7 2811 RT_ASSERT(false, "cmdtable cannot be NULL\n");
7274a8c2
CL		 2812 return false;
2813 }
2814 if (cmdtableidx >= cmdtablesz)
2815 return false;
2816
2817 pcmd = cmdtable + cmdtableidx;
2818 pcmd->cmdid = cmdid;
2819 pcmd->para1 = para1;
2820 pcmd->para2 = para2;
2821 pcmd->msdelay = msdelay;
2822 return true;
2823}
2824
2825void rtl92d_phy_reset_iqk_result(struct ieee80211_hw *hw)
2826{
2827 struct rtl_priv *rtlpriv = rtl_priv(hw);
2828 struct rtl_phy *rtlphy = &(rtlpriv->phy);
2829 u8 i;
2830
2831 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
f30d7507 2832 "settings regs %d default regs %d\n",
e6deaf81 2833 (int)(sizeof(rtlphy->iqk_matrix) /
f30d7507
JP		 2834 sizeof(struct iqk_matrix_regs)),
2835 IQK_MATRIX_REG_NUM);
7274a8c2
CL		 2836 /* 0xe94, 0xe9c, 0xea4, 0xeac, 0xeb4, 0xebc, 0xec4, 0xecc */
2837 for (i = 0; i < IQK_MATRIX_SETTINGS_NUM; i++) {
e6deaf81
LF		 2838 rtlphy->iqk_matrix[i].value[0][0] = 0x100;
2839 rtlphy->iqk_matrix[i].value[0][2] = 0x100;
2840 rtlphy->iqk_matrix[i].value[0][4] = 0x100;
2841 rtlphy->iqk_matrix[i].value[0][6] = 0x100;
2842 rtlphy->iqk_matrix[i].value[0][1] = 0x0;
2843 rtlphy->iqk_matrix[i].value[0][3] = 0x0;
2844 rtlphy->iqk_matrix[i].value[0][5] = 0x0;
2845 rtlphy->iqk_matrix[i].value[0][7] = 0x0;
2846 rtlphy->iqk_matrix[i].iqk_done = false;
7274a8c2
CL		 2847 }
2848}
2849
2850static bool _rtl92d_phy_sw_chnl_step_by_step(struct ieee80211_hw *hw,
2851 u8 channel, u8 *stage, u8 *step,
2852 u32 *delay)
2853{
2854 struct rtl_priv *rtlpriv = rtl_priv(hw);
2855 struct rtl_phy *rtlphy = &(rtlpriv->phy);
2856 struct swchnlcmd precommoncmd[MAX_PRECMD_CNT];
2857 u32 precommoncmdcnt;
2858 struct swchnlcmd postcommoncmd[MAX_POSTCMD_CNT];
2859 u32 postcommoncmdcnt;
2860 struct swchnlcmd rfdependcmd[MAX_RFDEPENDCMD_CNT];
2861 u32 rfdependcmdcnt;
2862 struct swchnlcmd *currentcmd = NULL;
2863 u8 rfpath;
2864 u8 num_total_rfpath = rtlphy->num_total_rfpath;
2865
2866 precommoncmdcnt = 0;
2867 _rtl92d_phy_set_sw_chnl_cmdarray(precommoncmd, precommoncmdcnt++,
2868 MAX_PRECMD_CNT,
2869 CMDID_SET_TXPOWEROWER_LEVEL, 0, 0, 0);
2870 _rtl92d_phy_set_sw_chnl_cmdarray(precommoncmd, precommoncmdcnt++,
2871 MAX_PRECMD_CNT, CMDID_END, 0, 0, 0);
2872 postcommoncmdcnt = 0;
2873 _rtl92d_phy_set_sw_chnl_cmdarray(postcommoncmd, postcommoncmdcnt++,
2874 MAX_POSTCMD_CNT, CMDID_END, 0, 0, 0);
2875 rfdependcmdcnt = 0;
2876 _rtl92d_phy_set_sw_chnl_cmdarray(rfdependcmd, rfdependcmdcnt++,
2877 MAX_RFDEPENDCMD_CNT, CMDID_RF_WRITEREG,
2878 RF_CHNLBW, channel, 0);
2879 _rtl92d_phy_set_sw_chnl_cmdarray(rfdependcmd, rfdependcmdcnt++,
2880 MAX_RFDEPENDCMD_CNT, CMDID_END,
2881 0, 0, 0);
2882
2883 do {
2884 switch (*stage) {
2885 case 0:
2886 currentcmd = &precommoncmd[*step];
2887 break;
2888 case 1:
2889 currentcmd = &rfdependcmd[*step];
2890 break;
2891 case 2:
2892 currentcmd = &postcommoncmd[*step];
2893 break;
2894 }
2895 if (currentcmd->cmdid == CMDID_END) {
2896 if ((*stage) == 2) {
2897 return true;
2898 } else {
2899 (*stage)++;
2900 (*step) = 0;
2901 continue;
2902 }
2903 }
2904 switch (currentcmd->cmdid) {
2905 case CMDID_SET_TXPOWEROWER_LEVEL:
2906 rtl92d_phy_set_txpower_level(hw, channel);
2907 break;
2908 case CMDID_WRITEPORT_ULONG:
2909 rtl_write_dword(rtlpriv, currentcmd->para1,
2910 currentcmd->para2);
2911 break;
2912 case CMDID_WRITEPORT_USHORT:
2913 rtl_write_word(rtlpriv, currentcmd->para1,
2914 (u16)currentcmd->para2);
2915 break;
2916 case CMDID_WRITEPORT_UCHAR:
2917 rtl_write_byte(rtlpriv, currentcmd->para1,
2918 (u8)currentcmd->para2);
2919 break;
2920 case CMDID_RF_WRITEREG:
2921 for (rfpath = 0; rfpath < num_total_rfpath; rfpath++) {
2922 rtlphy->rfreg_chnlval[rfpath] =
2923 ((rtlphy->rfreg_chnlval[rfpath] &
2924 0xffffff00) | currentcmd->para2);
2925 if (rtlpriv->rtlhal.current_bandtype ==
2926 BAND_ON_5G) {
2927 if (currentcmd->para2 > 99)
2928 rtlphy->rfreg_chnlval[rfpath] =
2929 rtlphy->rfreg_chnlval
2930 [rfpath] | (BIT(18));
2931 else
2932 rtlphy->rfreg_chnlval[rfpath] =
2933 rtlphy->rfreg_chnlval
2934 [rfpath] & (~BIT(18));
2935 rtlphy->rfreg_chnlval[rfpath] |=
2936 (BIT(16) | BIT(8));
2937 } else {
2938 rtlphy->rfreg_chnlval[rfpath] &=
2939 ~(BIT(8) | BIT(16) | BIT(18));
2940 }
2941 rtl_set_rfreg(hw, (enum radio_path)rfpath,
2942 currentcmd->para1,
2943 BRFREGOFFSETMASK,
2944 rtlphy->rfreg_chnlval[rfpath]);
2945 _rtl92d_phy_reload_imr_setting(hw, channel,
2946 rfpath);
2947 }
2948 _rtl92d_phy_switch_rf_setting(hw, channel);
2949 /* do IQK when all parameters are ready */
2950 rtl92d_phy_reload_iqk_setting(hw, channel);
2951 break;
2952 default:
2953 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
f30d7507 2954 "switch case not processed\n");
7274a8c2
CL		 2955 break;
2956 }
2957 break;
2958 } while (true);
2959 (*delay) = currentcmd->msdelay;
2960 (*step)++;
2961 return false;
2962}
2963
2964u8 rtl92d_phy_sw_chnl(struct ieee80211_hw *hw)
2965{
2966 struct rtl_priv *rtlpriv = rtl_priv(hw);
2967 struct rtl_phy *rtlphy = &(rtlpriv->phy);
2968 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
2969 u32 delay;
2970 u32 timeout = 1000, timecount = 0;
2971 u8 channel = rtlphy->current_channel;
2972 u32 ret_value;
2973
2974 if (rtlphy->sw_chnl_inprogress)
2975 return 0;
2976 if (rtlphy->set_bwmode_inprogress)
2977 return 0;
2978
2979 if ((is_hal_stop(rtlhal)) || (RT_CANNOT_IO(hw))) {
2980 RT_TRACE(rtlpriv, COMP_CHAN, DBG_LOUD,
f30d7507 2981 "sw_chnl_inprogress false driver sleep or unload\n");
7274a8c2
CL		 2982 return 0;
2983 }
2984 while (rtlphy->lck_inprogress && timecount < timeout) {
2985 mdelay(50);
2986 timecount += 50;
2987 }
2988 if (rtlhal->macphymode == SINGLEMAC_SINGLEPHY &&
2989 rtlhal->bandset == BAND_ON_BOTH) {
2990 ret_value = rtl_get_bbreg(hw, RFPGA0_XAB_RFPARAMETER,
2991 BMASKDWORD);
2992 if (rtlphy->current_channel > 14 && !(ret_value & BIT(0)))
2993 rtl92d_phy_switch_wirelessband(hw, BAND_ON_5G);
2994 else if (rtlphy->current_channel <= 14 && (ret_value & BIT(0)))
2995 rtl92d_phy_switch_wirelessband(hw, BAND_ON_2_4G);
2996 }
2997 switch (rtlhal->current_bandtype) {
2998 case BAND_ON_5G:
2999 /* Get first channel error when change between
3000 * 5G and 2.4G band. */
3001 if (channel <= 14)
3002 return 0;
9d833ed7 3003 RT_ASSERT((channel > 14), "5G but channel<=14\n");
7274a8c2
CL		 3004 break;
3005 case BAND_ON_2_4G:
3006 /* Get first channel error when change between
3007 * 5G and 2.4G band. */
3008 if (channel > 14)
3009 return 0;
9d833ed7 3010 RT_ASSERT((channel <= 14), "2G but channel>14\n");
7274a8c2
CL		 3011 break;
3012 default:
9d833ed7
JP		 3013 RT_ASSERT(false, "Invalid WirelessMode(%#x)!!\n",
3014 rtlpriv->mac80211.mode);
7274a8c2
CL		 3015 break;
3016 }
3017 rtlphy->sw_chnl_inprogress = true;
3018 if (channel == 0)
3019 channel = 1;
3020 rtlphy->sw_chnl_stage = 0;
3021 rtlphy->sw_chnl_step = 0;
3022 RT_TRACE(rtlpriv, COMP_SCAN, DBG_TRACE,
f30d7507 3023 "switch to channel%d\n", rtlphy->current_channel);
7274a8c2
CL		 3024
3025 do {
3026 if (!rtlphy->sw_chnl_inprogress)
3027 break;
3028 if (!_rtl92d_phy_sw_chnl_step_by_step(hw,
3029 rtlphy->current_channel,
3030 &rtlphy->sw_chnl_stage, &rtlphy->sw_chnl_step, &delay)) {
3031 if (delay > 0)
3032 mdelay(delay);
3033 else
3034 continue;
3035 } else {
3036 rtlphy->sw_chnl_inprogress = false;
3037 }
3038 break;
3039 } while (true);
f30d7507 3040 RT_TRACE(rtlpriv, COMP_SCAN, DBG_TRACE, "<==\n");
7274a8c2
CL		 3041 rtlphy->sw_chnl_inprogress = false;
3042 return 1;
3043}
3044
3045static void rtl92d_phy_set_io(struct ieee80211_hw *hw)
3046{
3047 struct rtl_priv *rtlpriv = rtl_priv(hw);
c21916ec 3048 struct dig_t *de_digtable = &rtlpriv->dm_digtable;
7274a8c2
CL		 3049 struct rtl_phy *rtlphy = &(rtlpriv->phy);
3050
3051 RT_TRACE(rtlpriv, COMP_CMD, DBG_TRACE,
f30d7507
JP		 3052 "--->Cmd(%#x), set_io_inprogress(%d)\n",
3053 rtlphy->current_io_type, rtlphy->set_io_inprogress);
7274a8c2
CL		 3054 switch (rtlphy->current_io_type) {
3055 case IO_CMD_RESUME_DM_BY_SCAN:
c21916ec 3056 de_digtable->cur_igvalue = rtlphy->initgain_backup.xaagccore1;
7274a8c2
CL		 3057 rtl92d_dm_write_dig(hw);
3058 rtl92d_phy_set_txpower_level(hw, rtlphy->current_channel);
3059 break;
3060 case IO_CMD_PAUSE_DM_BY_SCAN:
c21916ec
LF		 3061 rtlphy->initgain_backup.xaagccore1 = de_digtable->cur_igvalue;
3062 de_digtable->cur_igvalue = 0x37;
7274a8c2
CL		 3063 rtl92d_dm_write_dig(hw);
3064 break;
3065 default:
3066 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
f30d7507 3067 "switch case not processed\n");
7274a8c2
CL		 3068 break;
3069 }
3070 rtlphy->set_io_inprogress = false;
f30d7507
JP		 3071 RT_TRACE(rtlpriv, COMP_CMD, DBG_TRACE, "<---(%#x)\n",
3072 rtlphy->current_io_type);
7274a8c2
CL		 3073}
3074
3075bool rtl92d_phy_set_io_cmd(struct ieee80211_hw *hw, enum io_type iotype)
3076{
3077 struct rtl_priv *rtlpriv = rtl_priv(hw);
3078 struct rtl_phy *rtlphy = &(rtlpriv->phy);
3079 bool postprocessing = false;
3080
3081 RT_TRACE(rtlpriv, COMP_CMD, DBG_TRACE,
f30d7507
JP		 3082 "-->IO Cmd(%#x), set_io_inprogress(%d)\n",
3083 iotype, rtlphy->set_io_inprogress);
7274a8c2
CL		 3084 do {
3085 switch (iotype) {
3086 case IO_CMD_RESUME_DM_BY_SCAN:
3087 RT_TRACE(rtlpriv, COMP_CMD, DBG_TRACE,
f30d7507 3088 "[IO CMD] Resume DM after scan\n");
7274a8c2
CL		 3089 postprocessing = true;
3090 break;
3091 case IO_CMD_PAUSE_DM_BY_SCAN:
3092 RT_TRACE(rtlpriv, COMP_CMD, DBG_TRACE,
f30d7507 3093 "[IO CMD] Pause DM before scan\n");
7274a8c2
CL		 3094 postprocessing = true;
3095 break;
3096 default:
3097 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
f30d7507 3098 "switch case not processed\n");
7274a8c2
CL		 3099 break;
3100 }
3101 } while (false);
3102 if (postprocessing && !rtlphy->set_io_inprogress) {
3103 rtlphy->set_io_inprogress = true;
3104 rtlphy->current_io_type = iotype;
3105 } else {
3106 return false;
3107 }
3108 rtl92d_phy_set_io(hw);
f30d7507 3109 RT_TRACE(rtlpriv, COMP_CMD, DBG_TRACE, "<--IO Type(%#x)\n", iotype);
7274a8c2
CL		 3110 return true;
3111}
3112
3113static void _rtl92d_phy_set_rfon(struct ieee80211_hw *hw)
3114{
3115 struct rtl_priv *rtlpriv = rtl_priv(hw);
3116
3117 /* a. SYS_CLKR 0x08[11] = 1 restore MAC clock */
3118 /* b. SPS_CTRL 0x11[7:0] = 0x2b */
3119 if (rtlpriv->rtlhal.macphymode == SINGLEMAC_SINGLEPHY)
3120 rtl_write_byte(rtlpriv, REG_SPS0_CTRL, 0x2b);
3121 /* c. For PCIE: SYS_FUNC_EN 0x02[7:0] = 0xE3 enable BB TRX function */
3122 rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN, 0xE3);
3123 /* RF_ON_EXCEP(d~g): */
3124 /* d. APSD_CTRL 0x600[7:0] = 0x00 */
3125 rtl_write_byte(rtlpriv, REG_APSD_CTRL, 0x00);
3126 /* e. SYS_FUNC_EN 0x02[7:0] = 0xE2 reset BB TRX function again */
3127 /* f. SYS_FUNC_EN 0x02[7:0] = 0xE3 enable BB TRX function*/
3128 rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN, 0xE2);
3129 rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN, 0xE3);
3130 /* g. txpause 0x522[7:0] = 0x00 enable mac tx queue */
3131 rtl_write_byte(rtlpriv, REG_TXPAUSE, 0x00);
3132}
3133
3134static void _rtl92d_phy_set_rfsleep(struct ieee80211_hw *hw)
3135{
3136 struct rtl_priv *rtlpriv = rtl_priv(hw);
3137 u32 u4btmp;
3138 u8 delay = 5;
3139
3140 /* a. TXPAUSE 0x522[7:0] = 0xFF Pause MAC TX queue */
3141 rtl_write_byte(rtlpriv, REG_TXPAUSE, 0xFF);
3142 /* b. RF path 0 offset 0x00 = 0x00 disable RF */
3143 rtl_set_rfreg(hw, RF90_PATH_A, 0x00, BRFREGOFFSETMASK, 0x00);
3144 /* c. APSD_CTRL 0x600[7:0] = 0x40 */
3145 rtl_write_byte(rtlpriv, REG_APSD_CTRL, 0x40);
3146 /* d. APSD_CTRL 0x600[7:0] = 0x00
3147 * APSD_CTRL 0x600[7:0] = 0x00
3148 * RF path 0 offset 0x00 = 0x00
3149 * APSD_CTRL 0x600[7:0] = 0x40
3150 * */
3151 u4btmp = rtl_get_rfreg(hw, RF90_PATH_A, 0, BRFREGOFFSETMASK);
3152 while (u4btmp != 0 && delay > 0) {
3153 rtl_write_byte(rtlpriv, REG_APSD_CTRL, 0x0);
3154 rtl_set_rfreg(hw, RF90_PATH_A, 0x00, BRFREGOFFSETMASK, 0x00);
3155 rtl_write_byte(rtlpriv, REG_APSD_CTRL, 0x40);
3156 u4btmp = rtl_get_rfreg(hw, RF90_PATH_A, 0, BRFREGOFFSETMASK);
3157 delay--;
3158 }
3159 if (delay == 0) {
3160 /* Jump out the LPS turn off sequence to RF_ON_EXCEP */
3161 rtl_write_byte(rtlpriv, REG_APSD_CTRL, 0x00);
3162
3163 rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN, 0xE2);
3164 rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN, 0xE3);
3165 rtl_write_byte(rtlpriv, REG_TXPAUSE, 0x00);
3166 RT_TRACE(rtlpriv, COMP_POWER, DBG_LOUD,
f30d7507 3167 "Fail !!! Switch RF timeout\n");
7274a8c2
CL		 3168 return;
3169 }
3170 /* e. For PCIE: SYS_FUNC_EN 0x02[7:0] = 0xE2 reset BB TRX function */
3171 rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN, 0xE2);
3172 /* f. SPS_CTRL 0x11[7:0] = 0x22 */
3173 if (rtlpriv->rtlhal.macphymode == SINGLEMAC_SINGLEPHY)
3174 rtl_write_byte(rtlpriv, REG_SPS0_CTRL, 0x22);
3175 /* g. SYS_CLKR 0x08[11] = 0 gated MAC clock */
3176}
3177
3178bool rtl92d_phy_set_rf_power_state(struct ieee80211_hw *hw,
3179 enum rf_pwrstate rfpwr_state)
3180{
3181
3182 bool bresult = true;
3183 struct rtl_priv *rtlpriv = rtl_priv(hw);
3184 struct rtl_pci_priv *pcipriv = rtl_pcipriv(hw);
3185 struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
3186 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
3187 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
3188 u8 i, queue_id;
3189 struct rtl8192_tx_ring *ring = NULL;
3190
3191 if (rfpwr_state == ppsc->rfpwr_state)
3192 return false;
3193 switch (rfpwr_state) {
3194 case ERFON:
3195 if ((ppsc->rfpwr_state == ERFOFF) &&
3196 RT_IN_PS_LEVEL(ppsc, RT_RF_OFF_LEVL_HALT_NIC)) {
3197 bool rtstatus;
3198 u32 InitializeCount = 0;
3199 do {
3200 InitializeCount++;
3201 RT_TRACE(rtlpriv, COMP_RF, DBG_DMESG,
f30d7507 3202 "IPS Set eRf nic enable\n");
7274a8c2 3203 rtstatus = rtl_ps_enable_nic(hw);
23677ce3 3204 } while (!rtstatus && (InitializeCount < 10));
7274a8c2
CL		 3205
3206 RT_CLEAR_PS_LEVEL(ppsc,
3207 RT_RF_OFF_LEVL_HALT_NIC);
3208 } else {
3209 RT_TRACE(rtlpriv, COMP_POWER, DBG_DMESG,
f30d7507 3210 "awake, sleeped:%d ms state_inap:%x\n",
7274a8c2 3211 jiffies_to_msecs(jiffies -
f30d7507
JP		 3212 ppsc->last_sleep_jiffies),
3213 rtlpriv->psc.state_inap);
7274a8c2
CL		 3214 ppsc->last_awake_jiffies = jiffies;
3215 _rtl92d_phy_set_rfon(hw);
3216 }
3217
3218 if (mac->link_state == MAC80211_LINKED)
3219 rtlpriv->cfg->ops->led_control(hw,
3220 LED_CTL_LINK);
3221 else
3222 rtlpriv->cfg->ops->led_control(hw,
3223 LED_CTL_NO_LINK);
3224 break;
3225 case ERFOFF:
3226 if (ppsc->reg_rfps_level & RT_RF_OFF_LEVL_HALT_NIC) {
3227 RT_TRACE(rtlpriv, COMP_RF, DBG_DMESG,
f30d7507 3228 "IPS Set eRf nic disable\n");
7274a8c2
CL		 3229 rtl_ps_disable_nic(hw);
3230 RT_SET_PS_LEVEL(ppsc, RT_RF_OFF_LEVL_HALT_NIC);
3231 } else {
3232 if (ppsc->rfoff_reason == RF_CHANGE_BY_IPS)
3233 rtlpriv->cfg->ops->led_control(hw,
3234 LED_CTL_NO_LINK);
3235 else
3236 rtlpriv->cfg->ops->led_control(hw,
3237 LED_CTL_POWER_OFF);
3238 }
3239 break;
3240 case ERFSLEEP:
3241 if (ppsc->rfpwr_state == ERFOFF)
91ddff8a 3242 return false;
7274a8c2
CL		 3243
3244 for (queue_id = 0, i = 0;
3245 queue_id < RTL_PCI_MAX_TX_QUEUE_COUNT;) {
3246 ring = &pcipriv->dev.tx_ring[queue_id];
3247 if (skb_queue_len(&ring->queue) == 0 ||
3248 queue_id == BEACON_QUEUE) {
3249 queue_id++;
3250 continue;
3251 } else if (rtlpci->pdev->current_state != PCI_D0) {
3252 RT_TRACE(rtlpriv, COMP_POWER, DBG_LOUD,
f30d7507
JP		 3253 "eRf Off/Sleep: %d times TcbBusyQueue[%d] !=0 but lower power state!\n",
3254 i + 1, queue_id);
7274a8c2
CL		 3255 break;
3256 } else {
3257 RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING,
f30d7507
JP		 3258 "eRf Off/Sleep: %d times TcbBusyQueue[%d] =%d before doze!\n",
3259 i + 1, queue_id,
3260 skb_queue_len(&ring->queue));
7274a8c2
CL		 3261 udelay(10);
3262 i++;
3263 }
3264
3265 if (i >= MAX_DOZE_WAITING_TIMES_9x) {
3266 RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING,
f30d7507
JP		 3267 "ERFOFF: %d times TcbBusyQueue[%d] = %d !\n",
3268 MAX_DOZE_WAITING_TIMES_9x, queue_id,
3269 skb_queue_len(&ring->queue));
7274a8c2
CL		 3270 break;
3271 }
3272 }
3273 RT_TRACE(rtlpriv, COMP_POWER, DBG_DMESG,
f30d7507
JP		 3274 "Set rfsleep awaked:%d ms\n",
3275 jiffies_to_msecs(jiffies - ppsc->last_awake_jiffies));
3276 RT_TRACE(rtlpriv, COMP_POWER, DBG_DMESG,
3277 "sleep awaked:%d ms state_inap:%x\n",
3278 jiffies_to_msecs(jiffies -
3279 ppsc->last_awake_jiffies),
3280 rtlpriv->psc.state_inap);
7274a8c2
CL		 3281 ppsc->last_sleep_jiffies = jiffies;
3282 _rtl92d_phy_set_rfsleep(hw);
3283 break;
3284 default:
3285 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
f30d7507 3286 "switch case not processed\n");
7274a8c2
CL		 3287 bresult = false;
3288 break;
3289 }
3290 if (bresult)
3291 ppsc->rfpwr_state = rfpwr_state;
3292 return bresult;
3293}
3294
3295void rtl92d_phy_config_macphymode(struct ieee80211_hw *hw)
3296{
3297 struct rtl_priv *rtlpriv = rtl_priv(hw);
3298 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
3299 u8 offset = REG_MAC_PHY_CTRL_NORMAL;
3300
3301 switch (rtlhal->macphymode) {
3302 case DUALMAC_DUALPHY:
3303 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
f30d7507 3304 "MacPhyMode: DUALMAC_DUALPHY\n");
7274a8c2
CL		 3305 rtl_write_byte(rtlpriv, offset, 0xF3);
3306 break;
3307 case SINGLEMAC_SINGLEPHY:
3308 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
f30d7507 3309 "MacPhyMode: SINGLEMAC_SINGLEPHY\n");
7274a8c2
CL		 3310 rtl_write_byte(rtlpriv, offset, 0xF4);
3311 break;
3312 case DUALMAC_SINGLEPHY:
3313 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
f30d7507 3314 "MacPhyMode: DUALMAC_SINGLEPHY\n");
7274a8c2
CL		 3315 rtl_write_byte(rtlpriv, offset, 0xF1);
3316 break;
3317 }
3318}
3319
3320void rtl92d_phy_config_macphymode_info(struct ieee80211_hw *hw)
3321{
3322 struct rtl_priv *rtlpriv = rtl_priv(hw);
3323 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
3324 struct rtl_phy *rtlphy = &(rtlpriv->phy);
3325
3326 switch (rtlhal->macphymode) {
3327 case DUALMAC_SINGLEPHY:
3328 rtlphy->rf_type = RF_2T2R;
f1b00f4d 3329 rtlhal->version |= RF_TYPE_2T2R;
7274a8c2
CL		 3330 rtlhal->bandset = BAND_ON_BOTH;
3331 rtlhal->current_bandtype = BAND_ON_2_4G;
3332 break;
3333
3334 case SINGLEMAC_SINGLEPHY:
3335 rtlphy->rf_type = RF_2T2R;
f1b00f4d 3336 rtlhal->version |= RF_TYPE_2T2R;
7274a8c2
CL		 3337 rtlhal->bandset = BAND_ON_BOTH;
3338 rtlhal->current_bandtype = BAND_ON_2_4G;
3339 break;
3340
3341 case DUALMAC_DUALPHY:
3342 rtlphy->rf_type = RF_1T1R;
f1b00f4d 3343 rtlhal->version &= RF_TYPE_1T1R;
7274a8c2
CL		 3344 /* Now we let MAC0 run on 5G band. */
3345 if (rtlhal->interfaceindex == 0) {
3346 rtlhal->bandset = BAND_ON_5G;
3347 rtlhal->current_bandtype = BAND_ON_5G;
3348 } else {
3349 rtlhal->bandset = BAND_ON_2_4G;
3350 rtlhal->current_bandtype = BAND_ON_2_4G;
3351 }
3352 break;
3353 default:
3354 break;
3355 }
3356}
3357
3358u8 rtl92d_get_chnlgroup_fromarray(u8 chnl)
3359{
3360 u8 group;
3361 u8 channel_info[59] = {
3362 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14,
3363 36, 38, 40, 42, 44, 46, 48, 50, 52, 54, 56,
3364 58, 60, 62, 64, 100, 102, 104, 106, 108,
3365 110, 112, 114, 116, 118, 120, 122, 124,
3366 126, 128, 130, 132, 134, 136, 138, 140,
3367 149, 151, 153, 155, 157, 159, 161, 163,
3368 165
3369 };
3370
3371 if (channel_info[chnl] <= 3)
3372 group = 0;
3373 else if (channel_info[chnl] <= 9)
3374 group = 1;
3375 else if (channel_info[chnl] <= 14)
3376 group = 2;
3377 else if (channel_info[chnl] <= 44)
3378 group = 3;
3379 else if (channel_info[chnl] <= 54)
3380 group = 4;
3381 else if (channel_info[chnl] <= 64)
3382 group = 5;
3383 else if (channel_info[chnl] <= 112)
3384 group = 6;
3385 else if (channel_info[chnl] <= 126)
3386 group = 7;
3387 else if (channel_info[chnl] <= 140)
3388 group = 8;
3389 else if (channel_info[chnl] <= 153)
3390 group = 9;
3391 else if (channel_info[chnl] <= 159)
3392 group = 10;
3393 else
3394 group = 11;
3395 return group;
3396}
3397
3398void rtl92d_phy_set_poweron(struct ieee80211_hw *hw)
3399{
3400 struct rtl_priv *rtlpriv = rtl_priv(hw);
3401 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
3402 unsigned long flags;
3403 u8 value8;
3404 u16 i;
3405 u32 mac_reg = (rtlhal->interfaceindex == 0 ? REG_MAC0 : REG_MAC1);
3406
3407 /* notice fw know band status 0x81[1]/0x53[1] = 0: 5G, 1: 2G */
3408 if (rtlhal->current_bandtype == BAND_ON_2_4G) {
3409 value8 = rtl_read_byte(rtlpriv, mac_reg);
3410 value8 |= BIT(1);
3411 rtl_write_byte(rtlpriv, mac_reg, value8);
3412 } else {
3413 value8 = rtl_read_byte(rtlpriv, mac_reg);
3414 value8 &= (~BIT(1));
3415 rtl_write_byte(rtlpriv, mac_reg, value8);
3416 }
3417
3418 if (rtlhal->macphymode == SINGLEMAC_SINGLEPHY) {
3419 value8 = rtl_read_byte(rtlpriv, REG_MAC0);
3420 rtl_write_byte(rtlpriv, REG_MAC0, value8 | MAC0_ON);
3421 } else {
3422 spin_lock_irqsave(&globalmutex_power, flags);
3423 if (rtlhal->interfaceindex == 0) {
3424 value8 = rtl_read_byte(rtlpriv, REG_MAC0);
3425 rtl_write_byte(rtlpriv, REG_MAC0, value8 | MAC0_ON);
3426 } else {
3427 value8 = rtl_read_byte(rtlpriv, REG_MAC1);
3428 rtl_write_byte(rtlpriv, REG_MAC1, value8 | MAC1_ON);
3429 }
3430 value8 = rtl_read_byte(rtlpriv, REG_POWER_OFF_IN_PROCESS);
3431 spin_unlock_irqrestore(&globalmutex_power, flags);
3432 for (i = 0; i < 200; i++) {
3433 if ((value8 & BIT(7)) == 0) {
3434 break;
3435 } else {
3436 udelay(500);
3437 spin_lock_irqsave(&globalmutex_power, flags);
3438 value8 = rtl_read_byte(rtlpriv,
3439 REG_POWER_OFF_IN_PROCESS);
3440 spin_unlock_irqrestore(&globalmutex_power,
3441 flags);
3442 }
3443 }
3444 if (i == 200)
9d833ed7 3445 RT_ASSERT(false, "Another mac power off over time\n");
7274a8c2
CL		 3446 }
3447}
3448
3449void rtl92d_phy_config_maccoexist_rfpage(struct ieee80211_hw *hw)
3450{
3451 struct rtl_priv *rtlpriv = rtl_priv(hw);
3452
3453 switch (rtlpriv->rtlhal.macphymode) {
3454 case DUALMAC_DUALPHY:
3455 rtl_write_byte(rtlpriv, REG_DMC, 0x0);
3456 rtl_write_byte(rtlpriv, REG_RX_PKT_LIMIT, 0x08);
3457 rtl_write_word(rtlpriv, REG_TRXFF_BNDY + 2, 0x13ff);
3458 break;
3459 case DUALMAC_SINGLEPHY:
3460 rtl_write_byte(rtlpriv, REG_DMC, 0xf8);
3461 rtl_write_byte(rtlpriv, REG_RX_PKT_LIMIT, 0x08);
3462 rtl_write_word(rtlpriv, REG_TRXFF_BNDY + 2, 0x13ff);
3463 break;
3464 case SINGLEMAC_SINGLEPHY:
3465 rtl_write_byte(rtlpriv, REG_DMC, 0x0);
3466 rtl_write_byte(rtlpriv, REG_RX_PKT_LIMIT, 0x10);
3467 rtl_write_word(rtlpriv, (REG_TRXFF_BNDY + 2), 0x27FF);
3468 break;
3469 default:
3470 break;
3471 }
3472}
3473
3474void rtl92d_update_bbrf_configuration(struct ieee80211_hw *hw)
3475{
3476 struct rtl_priv *rtlpriv = rtl_priv(hw);
3477 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
3478 struct rtl_phy *rtlphy = &(rtlpriv->phy);
3479 struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
3480 u8 rfpath, i;
3481
f30d7507 3482 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, "==>\n");
7274a8c2
CL		 3483 /* r_select_5G for path_A/B 0 for 2.4G, 1 for 5G */
3484 if (rtlhal->current_bandtype == BAND_ON_2_4G) {
3485 /* r_select_5G for path_A/B,0x878 */
3486 rtl_set_bbreg(hw, RFPGA0_XAB_RFPARAMETER, BIT(0), 0x0);
3487 rtl_set_bbreg(hw, RFPGA0_XAB_RFPARAMETER, BIT(15), 0x0);
3488 if (rtlhal->macphymode != DUALMAC_DUALPHY) {
3489 rtl_set_bbreg(hw, RFPGA0_XAB_RFPARAMETER, BIT(16), 0x0);
3490 rtl_set_bbreg(hw, RFPGA0_XAB_RFPARAMETER, BIT(31), 0x0);
3491 }
3492 /* rssi_table_select:index 0 for 2.4G.1~3 for 5G,0xc78 */
3493 rtl_set_bbreg(hw, ROFDM0_AGCRSSITABLE, BIT(6) | BIT(7), 0x0);
3494 /* fc_area 0xd2c */
3495 rtl_set_bbreg(hw, ROFDM1_CFOTRACKING, BIT(14) | BIT(13), 0x0);
3496 /* 5G LAN ON */
3497 rtl_set_bbreg(hw, 0xB30, 0x00F00000, 0xa);
3498 /* TX BB gain shift*1,Just for testchip,0xc80,0xc88 */
3499 rtl_set_bbreg(hw, ROFDM0_XATxIQIMBALANCE, BMASKDWORD,
3500 0x40000100);
3501 rtl_set_bbreg(hw, ROFDM0_XBTxIQIMBALANCE, BMASKDWORD,
3502 0x40000100);
3503 if (rtlhal->macphymode == DUALMAC_DUALPHY) {
3504 rtl_set_bbreg(hw, RFPGA0_XAB_RFINTERFACESW,
3505 BIT(10) | BIT(6) | BIT(5),
3506 ((rtlefuse->eeprom_c9 & BIT(3)) >> 3) |
3507 (rtlefuse->eeprom_c9 & BIT(1)) |
3508 ((rtlefuse->eeprom_cc & BIT(1)) << 4));
3509 rtl_set_bbreg(hw, RFPGA0_XA_RFINTERFACEOE,
3510 BIT(10) | BIT(6) | BIT(5),
3511 ((rtlefuse->eeprom_c9 & BIT(2)) >> 2) |
3512 ((rtlefuse->eeprom_c9 & BIT(0)) << 1) |
3513 ((rtlefuse->eeprom_cc & BIT(0)) << 5));
3514 rtl_set_bbreg(hw, RFPGA0_XAB_RFPARAMETER, BIT(15), 0);
3515 } else {
3516 rtl_set_bbreg(hw, RFPGA0_XAB_RFINTERFACESW,
3517 BIT(26) | BIT(22) | BIT(21) | BIT(10) |
3518 BIT(6) | BIT(5),
3519 ((rtlefuse->eeprom_c9 & BIT(3)) >> 3) |
3520 (rtlefuse->eeprom_c9 & BIT(1)) |
3521 ((rtlefuse->eeprom_cc & BIT(1)) << 4) |
3522 ((rtlefuse->eeprom_c9 & BIT(7)) << 9) |
3523 ((rtlefuse->eeprom_c9 & BIT(5)) << 12) |
3524 ((rtlefuse->eeprom_cc & BIT(3)) << 18));
3525 rtl_set_bbreg(hw, RFPGA0_XA_RFINTERFACEOE,
3526 BIT(10) | BIT(6) | BIT(5),
3527 ((rtlefuse->eeprom_c9 & BIT(2)) >> 2) |
3528 ((rtlefuse->eeprom_c9 & BIT(0)) << 1) |
3529 ((rtlefuse->eeprom_cc & BIT(0)) << 5));
3530 rtl_set_bbreg(hw, RFPGA0_XB_RFINTERFACEOE,
3531 BIT(10) | BIT(6) | BIT(5),
3532 ((rtlefuse->eeprom_c9 & BIT(6)) >> 6) |
3533 ((rtlefuse->eeprom_c9 & BIT(4)) >> 3) |
3534 ((rtlefuse->eeprom_cc & BIT(2)) << 3));
3535 rtl_set_bbreg(hw, RFPGA0_XAB_RFPARAMETER,
3536 BIT(31) | BIT(15), 0);
3537 }
3538 /* 1.5V_LDO */
3539 } else {
3540 /* r_select_5G for path_A/B */
3541 rtl_set_bbreg(hw, RFPGA0_XAB_RFPARAMETER, BIT(0), 0x1);
3542 rtl_set_bbreg(hw, RFPGA0_XAB_RFPARAMETER, BIT(15), 0x1);
3543 if (rtlhal->macphymode != DUALMAC_DUALPHY) {
3544 rtl_set_bbreg(hw, RFPGA0_XAB_RFPARAMETER, BIT(16), 0x1);
3545 rtl_set_bbreg(hw, RFPGA0_XAB_RFPARAMETER, BIT(31), 0x1);
3546 }
3547 /* rssi_table_select:index 0 for 2.4G.1~3 for 5G */
3548 rtl_set_bbreg(hw, ROFDM0_AGCRSSITABLE, BIT(6) | BIT(7), 0x1);
3549 /* fc_area */
3550 rtl_set_bbreg(hw, ROFDM1_CFOTRACKING, BIT(14) | BIT(13), 0x1);
3551 /* 5G LAN ON */
3552 rtl_set_bbreg(hw, 0xB30, 0x00F00000, 0x0);
3553 /* TX BB gain shift,Just for testchip,0xc80,0xc88 */
3554 if (rtlefuse->internal_pa_5g[0])
3555 rtl_set_bbreg(hw, ROFDM0_XATxIQIMBALANCE, BMASKDWORD,
3556 0x2d4000b5);
3557 else
3558 rtl_set_bbreg(hw, ROFDM0_XATxIQIMBALANCE, BMASKDWORD,
3559 0x20000080);
3560 if (rtlefuse->internal_pa_5g[1])
3561 rtl_set_bbreg(hw, ROFDM0_XBTxIQIMBALANCE, BMASKDWORD,
3562 0x2d4000b5);
3563 else
3564 rtl_set_bbreg(hw, ROFDM0_XBTxIQIMBALANCE, BMASKDWORD,
3565 0x20000080);
3566 if (rtlhal->macphymode == DUALMAC_DUALPHY) {
3567 rtl_set_bbreg(hw, RFPGA0_XAB_RFINTERFACESW,
3568 BIT(10) | BIT(6) | BIT(5),
3569 (rtlefuse->eeprom_cc & BIT(5)));
3570 rtl_set_bbreg(hw, RFPGA0_XA_RFINTERFACEOE, BIT(10),
3571 ((rtlefuse->eeprom_cc & BIT(4)) >> 4));
3572 rtl_set_bbreg(hw, RFPGA0_XAB_RFPARAMETER, BIT(15),
3573 (rtlefuse->eeprom_cc & BIT(4)) >> 4);
3574 } else {
3575 rtl_set_bbreg(hw, RFPGA0_XAB_RFINTERFACESW,
3576 BIT(26) | BIT(22) | BIT(21) | BIT(10) |
3577 BIT(6) | BIT(5),
3578 (rtlefuse->eeprom_cc & BIT(5)) |
3579 ((rtlefuse->eeprom_cc & BIT(7)) << 14));
3580 rtl_set_bbreg(hw, RFPGA0_XA_RFINTERFACEOE, BIT(10),
3581 ((rtlefuse->eeprom_cc & BIT(4)) >> 4));
3582 rtl_set_bbreg(hw, RFPGA0_XB_RFINTERFACEOE, BIT(10),
3583 ((rtlefuse->eeprom_cc & BIT(6)) >> 6));
3584 rtl_set_bbreg(hw, RFPGA0_XAB_RFPARAMETER,
3585 BIT(31) | BIT(15),
3586 ((rtlefuse->eeprom_cc & BIT(4)) >> 4) |
3587 ((rtlefuse->eeprom_cc & BIT(6)) << 10));
3588 }
3589 }
3590 /* update IQK related settings */
3591 rtl_set_bbreg(hw, ROFDM0_XARXIQIMBALANCE, BMASKDWORD, 0x40000100);
3592 rtl_set_bbreg(hw, ROFDM0_XBRXIQIMBALANCE, BMASKDWORD, 0x40000100);
3593 rtl_set_bbreg(hw, ROFDM0_XCTxAFE, 0xF0000000, 0x00);
3594 rtl_set_bbreg(hw, ROFDM0_ECCATHRESHOLD, BIT(30) | BIT(28) |
3595 BIT(26) | BIT(24), 0x00);
3596 rtl_set_bbreg(hw, ROFDM0_XDTxAFE, 0xF0000000, 0x00);
3597 rtl_set_bbreg(hw, 0xca0, 0xF0000000, 0x00);
3598 rtl_set_bbreg(hw, ROFDM0_AGCRSSITABLE, 0x0000F000, 0x00);
3599
3600 /* Update RF */
3601 for (rfpath = RF90_PATH_A; rfpath < rtlphy->num_total_rfpath;
3602 rfpath++) {
3603 if (rtlhal->current_bandtype == BAND_ON_2_4G) {
3604 /* MOD_AG for RF paht_A 0x18 BIT8,BIT16 */
3605 rtl_set_rfreg(hw, rfpath, RF_CHNLBW, BIT(8) | BIT(16) |
3606 BIT(18), 0);
3607 /* RF0x0b[16:14] =3b'111 */
3608 rtl_set_rfreg(hw, (enum radio_path)rfpath, 0x0B,
3609 0x1c000, 0x07);
3610 } else {
3611 /* MOD_AG for RF paht_A 0x18 BIT8,BIT16 */
3612 rtl_set_rfreg(hw, rfpath, RF_CHNLBW, BIT(8) |
3613 BIT(16) | BIT(18),
3614 (BIT(16) | BIT(8)) >> 8);
3615 }
3616 }
3617 /* Update for all band. */
3618 /* DMDP */
3619 if (rtlphy->rf_type == RF_1T1R) {
3620 /* Use antenna 0,0xc04,0xd04 */
3621 rtl_set_bbreg(hw, ROFDM0_TRXPATHENABLE, BMASKBYTE0, 0x11);
3622 rtl_set_bbreg(hw, ROFDM1_TRXPATHENABLE, BDWORD, 0x1);
3623
3624 /* enable ad/da clock1 for dual-phy reg0x888 */
3625 if (rtlhal->interfaceindex == 0) {
3626 rtl_set_bbreg(hw, RFPGA0_ADDALLOCKEN, BIT(12) |
3627 BIT(13), 0x3);
3628 } else {
3629 rtl92d_phy_enable_anotherphy(hw, false);
3630 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
f30d7507 3631 "MAC1 use DBI to update 0x888\n");
7274a8c2
CL		 3632 /* 0x888 */
3633 rtl92de_write_dword_dbi(hw, RFPGA0_ADDALLOCKEN,
3634 rtl92de_read_dword_dbi(hw,
3635 RFPGA0_ADDALLOCKEN,
3636 BIT(3)) | BIT(12) | BIT(13),
3637 BIT(3));
3638 rtl92d_phy_powerdown_anotherphy(hw, false);
3639 }
3640 } else {
3641 /* Single PHY */
3642 /* Use antenna 0 & 1,0xc04,0xd04 */
3643 rtl_set_bbreg(hw, ROFDM0_TRXPATHENABLE, BMASKBYTE0, 0x33);
3644 rtl_set_bbreg(hw, ROFDM1_TRXPATHENABLE, BDWORD, 0x3);
3645 /* disable ad/da clock1,0x888 */
3646 rtl_set_bbreg(hw, RFPGA0_ADDALLOCKEN, BIT(12) | BIT(13), 0);
3647 }
3648 for (rfpath = RF90_PATH_A; rfpath < rtlphy->num_total_rfpath;
3649 rfpath++) {
3650 rtlphy->rfreg_chnlval[rfpath] = rtl_get_rfreg(hw, rfpath,
3651 RF_CHNLBW, BRFREGOFFSETMASK);
3652 rtlphy->reg_rf3c[rfpath] = rtl_get_rfreg(hw, rfpath, 0x3C,
3653 BRFREGOFFSETMASK);
3654 }
3655 for (i = 0; i < 2; i++)
f30d7507
JP		 3656 RT_TRACE(rtlpriv, COMP_RF, DBG_LOUD, "RF 0x18 = 0x%x\n",
3657 rtlphy->rfreg_chnlval[i]);
3658 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, "<==\n");
7274a8c2
CL		 3659
3660}
3661
3662bool rtl92d_phy_check_poweroff(struct ieee80211_hw *hw)
3663{
3664 struct rtl_priv *rtlpriv = rtl_priv(hw);
3665 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
3666 u8 u1btmp;
3667 unsigned long flags;
3668
3669 if (rtlhal->macphymode == SINGLEMAC_SINGLEPHY) {
3670 u1btmp = rtl_read_byte(rtlpriv, REG_MAC0);
3671 rtl_write_byte(rtlpriv, REG_MAC0, u1btmp & (~MAC0_ON));
3672 return true;
3673 }
3674 spin_lock_irqsave(&globalmutex_power, flags);
3675 if (rtlhal->interfaceindex == 0) {
3676 u1btmp = rtl_read_byte(rtlpriv, REG_MAC0);
3677 rtl_write_byte(rtlpriv, REG_MAC0, u1btmp & (~MAC0_ON));
3678 u1btmp = rtl_read_byte(rtlpriv, REG_MAC1);
3679 u1btmp &= MAC1_ON;
3680 } else {
3681 u1btmp = rtl_read_byte(rtlpriv, REG_MAC1);
3682 rtl_write_byte(rtlpriv, REG_MAC1, u1btmp & (~MAC1_ON));
3683 u1btmp = rtl_read_byte(rtlpriv, REG_MAC0);
3684 u1btmp &= MAC0_ON;
3685 }
3686 if (u1btmp) {
3687 spin_unlock_irqrestore(&globalmutex_power, flags);
3688 return false;
3689 }
3690 u1btmp = rtl_read_byte(rtlpriv, REG_POWER_OFF_IN_PROCESS);
3691 u1btmp |= BIT(7);
3692 rtl_write_byte(rtlpriv, REG_POWER_OFF_IN_PROCESS, u1btmp);
3693 spin_unlock_irqrestore(&globalmutex_power, flags);
3694 return true;
3695}
Linux kernel - Deliverables
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