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rtlwifi: rtl8192se: Use write barrier when assigning ownership
[deliverable/linux.git] / drivers / net / wireless / rtlwifi / rtl8192se / hw.c
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CL		 1/******************************************************************************
2 *
3 * Copyright(c) 2009-2010 Realtek Corporation.
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of version 2 of the GNU General Public License as
7 * published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details.
13 *
14 * You should have received a copy of the GNU General Public License along with
15 * this program; if not, write to the Free Software Foundation, Inc.,
16 * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
17 *
18 * The full GNU General Public License is included in this distribution in the
19 * file called LICENSE.
20 *
21 * Contact Information:
22 * wlanfae <wlanfae@realtek.com>
23 * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
24 * Hsinchu 300, Taiwan.
25 *
26 * Larry Finger <Larry.Finger@lwfinger.net>
27 *
28 *****************************************************************************/
29
30#include "../wifi.h"
31#include "../efuse.h"
32#include "../base.h"
33#include "../regd.h"
34#include "../cam.h"
35#include "../ps.h"
36#include "../pci.h"
37#include "reg.h"
38#include "def.h"
39#include "phy.h"
40#include "dm.h"
41#include "fw.h"
42#include "led.h"
43#include "hw.h"
44
45void rtl92se_get_hw_reg(struct ieee80211_hw *hw, u8 variable, u8 *val)
46{
47 struct rtl_priv *rtlpriv = rtl_priv(hw);
48 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
49 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
50
51 switch (variable) {
52 case HW_VAR_RCR: {
53 *((u32 *) (val)) = rtlpci->receive_config;
54 break;
55 }
56 case HW_VAR_RF_STATE: {
57 *((enum rf_pwrstate *)(val)) = ppsc->rfpwr_state;
58 break;
59 }
60 case HW_VAR_FW_PSMODE_STATUS: {
61 *((bool *) (val)) = ppsc->fw_current_inpsmode;
62 break;
63 }
64 case HW_VAR_CORRECT_TSF: {
65 u64 tsf;
66 u32 *ptsf_low = (u32 *)&tsf;
67 u32 *ptsf_high = ((u32 *)&tsf) + 1;
68
69 *ptsf_high = rtl_read_dword(rtlpriv, (TSFR + 4));
70 *ptsf_low = rtl_read_dword(rtlpriv, TSFR);
71
72 *((u64 *) (val)) = tsf;
73
74 break;
75 }
76 case HW_VAR_MRC: {
77 *((bool *)(val)) = rtlpriv->dm.current_mrc_switch;
78 break;
79 }
80 default: {
81 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
82 ("switch case not process\n"));
83 break;
84 }
85 }
86}
87
88void rtl92se_set_hw_reg(struct ieee80211_hw *hw, u8 variable, u8 *val)
89{
90 struct rtl_priv *rtlpriv = rtl_priv(hw);
91 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
92 struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
93 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
94 struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
95 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
96
97 switch (variable) {
98 case HW_VAR_ETHER_ADDR:{
99 rtl_write_dword(rtlpriv, IDR0, ((u32 *)(val))[0]);
100 rtl_write_word(rtlpriv, IDR4, ((u16 *)(val + 4))[0]);
101 break;
102 }
103 case HW_VAR_BASIC_RATE:{
104 u16 rate_cfg = ((u16 *) val)[0];
105 u8 rate_index = 0;
106
107 if (rtlhal->version == VERSION_8192S_ACUT)
108 rate_cfg = rate_cfg & 0x150;
109 else
110 rate_cfg = rate_cfg & 0x15f;
111
112 rate_cfg |= 0x01;
113
114 rtl_write_byte(rtlpriv, RRSR, rate_cfg & 0xff);
115 rtl_write_byte(rtlpriv, RRSR + 1,
116 (rate_cfg >> 8) & 0xff);
117
118 while (rate_cfg > 0x1) {
119 rate_cfg = (rate_cfg >> 1);
120 rate_index++;
121 }
122 rtl_write_byte(rtlpriv, INIRTSMCS_SEL, rate_index);
123
124 break;
125 }
126 case HW_VAR_BSSID:{
127 rtl_write_dword(rtlpriv, BSSIDR, ((u32 *)(val))[0]);
128 rtl_write_word(rtlpriv, BSSIDR + 4,
129 ((u16 *)(val + 4))[0]);
130 break;
131 }
132 case HW_VAR_SIFS:{
133 rtl_write_byte(rtlpriv, SIFS_OFDM, val[0]);
134 rtl_write_byte(rtlpriv, SIFS_OFDM + 1, val[1]);
135 break;
136 }
137 case HW_VAR_SLOT_TIME:{
138 u8 e_aci;
139
140 RT_TRACE(rtlpriv, COMP_MLME, DBG_LOUD,
141 ("HW_VAR_SLOT_TIME %x\n", val[0]));
142
143 rtl_write_byte(rtlpriv, SLOT_TIME, val[0]);
144
145 for (e_aci = 0; e_aci < AC_MAX; e_aci++) {
146 rtlpriv->cfg->ops->set_hw_reg(hw,
147 HW_VAR_AC_PARAM,
148 (u8 *)(&e_aci));
149 }
150 break;
151 }
152 case HW_VAR_ACK_PREAMBLE:{
153 u8 reg_tmp;
154 u8 short_preamble = (bool) (*(u8 *) val);
155 reg_tmp = (mac->cur_40_prime_sc) << 5;
156 if (short_preamble)
157 reg_tmp |= 0x80;
158
159 rtl_write_byte(rtlpriv, RRSR + 2, reg_tmp);
160 break;
161 }
162 case HW_VAR_AMPDU_MIN_SPACE:{
163 u8 min_spacing_to_set;
164 u8 sec_min_space;
165
166 min_spacing_to_set = *((u8 *)val);
167 if (min_spacing_to_set <= 7) {
168 if (rtlpriv->sec.pairwise_enc_algorithm ==
169 NO_ENCRYPTION)
170 sec_min_space = 0;
171 else
172 sec_min_space = 1;
173
174 if (min_spacing_to_set < sec_min_space)
175 min_spacing_to_set = sec_min_space;
176 if (min_spacing_to_set > 5)
177 min_spacing_to_set = 5;
178
179 mac->min_space_cfg =
180 ((mac->min_space_cfg & 0xf8) |
181 min_spacing_to_set);
182
183 *val = min_spacing_to_set;
184
185 RT_TRACE(rtlpriv, COMP_MLME, DBG_LOUD,
186 ("Set HW_VAR_AMPDU_MIN_SPACE: %#x\n",
187 mac->min_space_cfg));
188
189 rtl_write_byte(rtlpriv, AMPDU_MIN_SPACE,
190 mac->min_space_cfg);
191 }
192 break;
193 }
194 case HW_VAR_SHORTGI_DENSITY:{
195 u8 density_to_set;
196
197 density_to_set = *((u8 *) val);
198 mac->min_space_cfg = rtlpriv->rtlhal.minspace_cfg;
199 mac->min_space_cfg |= (density_to_set << 3);
200
201 RT_TRACE(rtlpriv, COMP_MLME, DBG_LOUD,
202 ("Set HW_VAR_SHORTGI_DENSITY: %#x\n",
203 mac->min_space_cfg));
204
205 rtl_write_byte(rtlpriv, AMPDU_MIN_SPACE,
206 mac->min_space_cfg);
207
208 break;
209 }
210 case HW_VAR_AMPDU_FACTOR:{
211 u8 factor_toset;
212 u8 regtoset;
213 u8 factorlevel[18] = {
214 2, 4, 4, 7, 7, 13, 13,
215 13, 2, 7, 7, 13, 13,
216 15, 15, 15, 15, 0};
217 u8 index = 0;
218
219 factor_toset = *((u8 *) val);
220 if (factor_toset <= 3) {
221 factor_toset = (1 << (factor_toset + 2));
222 if (factor_toset > 0xf)
223 factor_toset = 0xf;
224
225 for (index = 0; index < 17; index++) {
226 if (factorlevel[index] > factor_toset)
227 factorlevel[index] =
228 factor_toset;
229 }
230
231 for (index = 0; index < 8; index++) {
232 regtoset = ((factorlevel[index * 2]) |
233 (factorlevel[index *
234 2 + 1] << 4));
235 rtl_write_byte(rtlpriv,
236 AGGLEN_LMT_L + index,
237 regtoset);
238 }
239
240 regtoset = ((factorlevel[16]) |
241 (factorlevel[17] << 4));
242 rtl_write_byte(rtlpriv, AGGLEN_LMT_H, regtoset);
243
244 RT_TRACE(rtlpriv, COMP_MLME, DBG_LOUD,
245 ("Set HW_VAR_AMPDU_FACTOR: %#x\n",
246 factor_toset));
247 }
248 break;
249 }
250 case HW_VAR_AC_PARAM:{
251 u8 e_aci = *((u8 *) val);
252 rtl92s_dm_init_edca_turbo(hw);
253
254 if (rtlpci->acm_method != eAcmWay2_SW)
255 rtlpriv->cfg->ops->set_hw_reg(hw,
256 HW_VAR_ACM_CTRL,
257 (u8 *)(&e_aci));
258 break;
259 }
260 case HW_VAR_ACM_CTRL:{
261 u8 e_aci = *((u8 *) val);
262 union aci_aifsn *p_aci_aifsn = (union aci_aifsn *)(&(
263 mac->ac[0].aifs));
264 u8 acm = p_aci_aifsn->f.acm;
265 u8 acm_ctrl = rtl_read_byte(rtlpriv, AcmHwCtrl);
266
267 acm_ctrl = acm_ctrl | ((rtlpci->acm_method == 2) ?
268 0x0 : 0x1);
269
270 if (acm) {
271 switch (e_aci) {
272 case AC0_BE:
273 acm_ctrl |= AcmHw_BeqEn;
274 break;
275 case AC2_VI:
276 acm_ctrl |= AcmHw_ViqEn;
277 break;
278 case AC3_VO:
279 acm_ctrl |= AcmHw_VoqEn;
280 break;
281 default:
282 RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING,
283 ("HW_VAR_ACM_CTRL acm set "
284 "failed: eACI is %d\n", acm));
285 break;
286 }
287 } else {
288 switch (e_aci) {
289 case AC0_BE:
290 acm_ctrl &= (~AcmHw_BeqEn);
291 break;
292 case AC2_VI:
293 acm_ctrl &= (~AcmHw_ViqEn);
294 break;
295 case AC3_VO:
296 acm_ctrl &= (~AcmHw_BeqEn);
297 break;
298 default:
299 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
300 ("switch case not process\n"));
301 break;
302 }
303 }
304
305 RT_TRACE(rtlpriv, COMP_QOS, DBG_TRACE,
306 ("HW_VAR_ACM_CTRL Write 0x%X\n", acm_ctrl));
307 rtl_write_byte(rtlpriv, AcmHwCtrl, acm_ctrl);
308 break;
309 }
310 case HW_VAR_RCR:{
311 rtl_write_dword(rtlpriv, RCR, ((u32 *) (val))[0]);
312 rtlpci->receive_config = ((u32 *) (val))[0];
313 break;
314 }
315 case HW_VAR_RETRY_LIMIT:{
316 u8 retry_limit = ((u8 *) (val))[0];
317
318 rtl_write_word(rtlpriv, RETRY_LIMIT,
319 retry_limit << RETRY_LIMIT_SHORT_SHIFT |
320 retry_limit << RETRY_LIMIT_LONG_SHIFT);
321 break;
322 }
323 case HW_VAR_DUAL_TSF_RST: {
324 break;
325 }
326 case HW_VAR_EFUSE_BYTES: {
327 rtlefuse->efuse_usedbytes = *((u16 *) val);
328 break;
329 }
330 case HW_VAR_EFUSE_USAGE: {
331 rtlefuse->efuse_usedpercentage = *((u8 *) val);
332 break;
333 }
334 case HW_VAR_IO_CMD: {
335 break;
336 }
337 case HW_VAR_WPA_CONFIG: {
338 rtl_write_byte(rtlpriv, REG_SECR, *((u8 *) val));
339 break;
340 }
341 case HW_VAR_SET_RPWM:{
342 break;
343 }
344 case HW_VAR_H2C_FW_PWRMODE:{
345 break;
346 }
347 case HW_VAR_FW_PSMODE_STATUS: {
348 ppsc->fw_current_inpsmode = *((bool *) val);
349 break;
350 }
351 case HW_VAR_H2C_FW_JOINBSSRPT:{
352 break;
353 }
354 case HW_VAR_AID:{
355 break;
356 }
357 case HW_VAR_CORRECT_TSF:{
358 break;
359 }
360 case HW_VAR_MRC: {
361 bool bmrc_toset = *((bool *)val);
362 u8 u1bdata = 0;
363
364 if (bmrc_toset) {
365 rtl_set_bbreg(hw, ROFDM0_TRXPATHENABLE,
366 MASKBYTE0, 0x33);
367 u1bdata = (u8)rtl_get_bbreg(hw,
368 ROFDM1_TRXPATHENABLE,
369 MASKBYTE0);
370 rtl_set_bbreg(hw, ROFDM1_TRXPATHENABLE,
371 MASKBYTE0,
372 ((u1bdata & 0xf0) | 0x03));
373 u1bdata = (u8)rtl_get_bbreg(hw,
374 ROFDM0_TRXPATHENABLE,
375 MASKBYTE1);
376 rtl_set_bbreg(hw, ROFDM0_TRXPATHENABLE,
377 MASKBYTE1,
378 (u1bdata | 0x04));
379
380 /* Update current settings. */
381 rtlpriv->dm.current_mrc_switch = bmrc_toset;
382 } else {
383 rtl_set_bbreg(hw, ROFDM0_TRXPATHENABLE,
384 MASKBYTE0, 0x13);
385 u1bdata = (u8)rtl_get_bbreg(hw,
386 ROFDM1_TRXPATHENABLE,
387 MASKBYTE0);
388 rtl_set_bbreg(hw, ROFDM1_TRXPATHENABLE,
389 MASKBYTE0,
390 ((u1bdata & 0xf0) | 0x01));
391 u1bdata = (u8)rtl_get_bbreg(hw,
392 ROFDM0_TRXPATHENABLE,
393 MASKBYTE1);
394 rtl_set_bbreg(hw, ROFDM0_TRXPATHENABLE,
395 MASKBYTE1, (u1bdata & 0xfb));
396
397 /* Update current settings. */
398 rtlpriv->dm.current_mrc_switch = bmrc_toset;
399 }
400
401 break;
402 }
403 default:
404 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
405 ("switch case not process\n"));
406 break;
407 }
408
409}
410
411void rtl92se_enable_hw_security_config(struct ieee80211_hw *hw)
412{
413 struct rtl_priv *rtlpriv = rtl_priv(hw);
414 u8 sec_reg_value = 0x0;
415
416 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, ("PairwiseEncAlgorithm = %d "
417 "GroupEncAlgorithm = %d\n",
418 rtlpriv->sec.pairwise_enc_algorithm,
419 rtlpriv->sec.group_enc_algorithm));
420
421 if (rtlpriv->cfg->mod_params->sw_crypto || rtlpriv->sec.use_sw_sec) {
422 RT_TRACE(rtlpriv, COMP_SEC, DBG_DMESG,
423 ("not open hw encryption\n"));
424 return;
425 }
426
427 sec_reg_value = SCR_TXENCENABLE | SCR_RXENCENABLE;
428
429 if (rtlpriv->sec.use_defaultkey) {
430 sec_reg_value |= SCR_TXUSEDK;
431 sec_reg_value |= SCR_RXUSEDK;
432 }
433
434 RT_TRACE(rtlpriv, COMP_SEC, DBG_LOUD, ("The SECR-value %x\n",
435 sec_reg_value));
436
437 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_WPA_CONFIG, &sec_reg_value);
438
439}
440
441static u8 _rtl92ce_halset_sysclk(struct ieee80211_hw *hw, u8 data)
442{
443 struct rtl_priv *rtlpriv = rtl_priv(hw);
444 u8 waitcount = 100;
445 bool bresult = false;
446 u8 tmpvalue;
447
448 rtl_write_byte(rtlpriv, SYS_CLKR + 1, data);
449
450 /* Wait the MAC synchronized. */
451 udelay(400);
452
453 /* Check if it is set ready. */
454 tmpvalue = rtl_read_byte(rtlpriv, SYS_CLKR + 1);
455 bresult = ((tmpvalue & BIT(7)) == (data & BIT(7)));
456
457 if ((data & (BIT(6) | BIT(7))) == false) {
458 waitcount = 100;
459 tmpvalue = 0;
460
461 while (1) {
462 waitcount--;
463
464 tmpvalue = rtl_read_byte(rtlpriv, SYS_CLKR + 1);
465 if ((tmpvalue & BIT(6)))
466 break;
467
468 printk(KERN_ERR "wait for BIT(6) return value %x\n",
469 tmpvalue);
470 if (waitcount == 0)
471 break;
472
473 udelay(10);
474 }
475
476 if (waitcount == 0)
477 bresult = false;
478 else
479 bresult = true;
480 }
481
482 return bresult;
483}
484
485void rtl8192se_gpiobit3_cfg_inputmode(struct ieee80211_hw *hw)
486{
487 struct rtl_priv *rtlpriv = rtl_priv(hw);
488 u8 u1tmp;
489
490 /* The following config GPIO function */
491 rtl_write_byte(rtlpriv, MAC_PINMUX_CFG, (GPIOMUX_EN | GPIOSEL_GPIO));
492 u1tmp = rtl_read_byte(rtlpriv, GPIO_IO_SEL);
493
494 /* config GPIO3 to input */
495 u1tmp &= HAL_8192S_HW_GPIO_OFF_MASK;
496 rtl_write_byte(rtlpriv, GPIO_IO_SEL, u1tmp);
497
498}
499
500static u8 _rtl92se_rf_onoff_detect(struct ieee80211_hw *hw)
501{
502 struct rtl_priv *rtlpriv = rtl_priv(hw);
503 u8 u1tmp;
504 u8 retval = ERFON;
505
506 /* The following config GPIO function */
507 rtl_write_byte(rtlpriv, MAC_PINMUX_CFG, (GPIOMUX_EN | GPIOSEL_GPIO));
508 u1tmp = rtl_read_byte(rtlpriv, GPIO_IO_SEL);
509
510 /* config GPIO3 to input */
511 u1tmp &= HAL_8192S_HW_GPIO_OFF_MASK;
512 rtl_write_byte(rtlpriv, GPIO_IO_SEL, u1tmp);
513
514 /* On some of the platform, driver cannot read correct
515 * value without delay between Write_GPIO_SEL and Read_GPIO_IN */
516 mdelay(10);
517
518 /* check GPIO3 */
519 u1tmp = rtl_read_byte(rtlpriv, GPIO_IN);
520 retval = (u1tmp & HAL_8192S_HW_GPIO_OFF_BIT) ? ERFON : ERFOFF;
521
522 return retval;
523}
524
525static void _rtl92se_macconfig_before_fwdownload(struct ieee80211_hw *hw)
526{
527 struct rtl_priv *rtlpriv = rtl_priv(hw);
528 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
529 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
530
531 u8 i;
532 u8 tmpu1b;
533 u16 tmpu2b;
534 u8 pollingcnt = 20;
535
536 if (rtlpci->first_init) {
537 /* Reset PCIE Digital */
538 tmpu1b = rtl_read_byte(rtlpriv, REG_SYS_FUNC_EN + 1);
539 tmpu1b &= 0xFE;
540 rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN + 1, tmpu1b);
541 udelay(1);
542 rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN + 1, tmpu1b | BIT(0));
543 }
544
545 /* Switch to SW IO control */
546 tmpu1b = rtl_read_byte(rtlpriv, (SYS_CLKR + 1));
547 if (tmpu1b & BIT(7)) {
548 tmpu1b &= ~(BIT(6) | BIT(7));
549
550 /* Set failed, return to prevent hang. */
551 if (!_rtl92ce_halset_sysclk(hw, tmpu1b))
552 return;
553 }
554
555 rtl_write_byte(rtlpriv, AFE_PLL_CTRL, 0x0);
556 udelay(50);
557 rtl_write_byte(rtlpriv, LDOA15_CTRL, 0x34);
558 udelay(50);
559
560 /* Clear FW RPWM for FW control LPS.*/
561 rtl_write_byte(rtlpriv, RPWM, 0x0);
562
563 /* Reset MAC-IO and CPU and Core Digital BIT(10)/11/15 */
564 tmpu1b = rtl_read_byte(rtlpriv, REG_SYS_FUNC_EN + 1);
565 tmpu1b &= 0x73;
566 rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN + 1, tmpu1b);
567 /* wait for BIT 10/11/15 to pull high automatically!! */
568 mdelay(1);
569
570 rtl_write_byte(rtlpriv, CMDR, 0);
571 rtl_write_byte(rtlpriv, TCR, 0);
572
573 /* Data sheet not define 0x562!!! Copy from WMAC!!!!! */
574 tmpu1b = rtl_read_byte(rtlpriv, 0x562);
575 tmpu1b |= 0x08;
576 rtl_write_byte(rtlpriv, 0x562, tmpu1b);
577 tmpu1b &= ~(BIT(3));
578 rtl_write_byte(rtlpriv, 0x562, tmpu1b);
579
580 /* Enable AFE clock source */
581 tmpu1b = rtl_read_byte(rtlpriv, AFE_XTAL_CTRL);
582 rtl_write_byte(rtlpriv, AFE_XTAL_CTRL, (tmpu1b | 0x01));
583 /* Delay 1.5ms */
584 mdelay(2);
585 tmpu1b = rtl_read_byte(rtlpriv, AFE_XTAL_CTRL + 1);
586 rtl_write_byte(rtlpriv, AFE_XTAL_CTRL + 1, (tmpu1b & 0xfb));
587
588 /* Enable AFE Macro Block's Bandgap */
589 tmpu1b = rtl_read_byte(rtlpriv, AFE_MISC);
590 rtl_write_byte(rtlpriv, AFE_MISC, (tmpu1b | BIT(0)));
591 mdelay(1);
592
593 /* Enable AFE Mbias */
594 tmpu1b = rtl_read_byte(rtlpriv, AFE_MISC);
595 rtl_write_byte(rtlpriv, AFE_MISC, (tmpu1b | 0x02));
596 mdelay(1);
597
598 /* Enable LDOA15 block */
599 tmpu1b = rtl_read_byte(rtlpriv, LDOA15_CTRL);
600 rtl_write_byte(rtlpriv, LDOA15_CTRL, (tmpu1b | BIT(0)));
601
602 /* Set Digital Vdd to Retention isolation Path. */
603 tmpu2b = rtl_read_word(rtlpriv, REG_SYS_ISO_CTRL);
604 rtl_write_word(rtlpriv, REG_SYS_ISO_CTRL, (tmpu2b | BIT(11)));
605
606 /* For warm reboot NIC disappera bug. */
607 tmpu2b = rtl_read_word(rtlpriv, REG_SYS_FUNC_EN);
608 rtl_write_word(rtlpriv, REG_SYS_FUNC_EN, (tmpu2b | BIT(13)));
609
610 rtl_write_byte(rtlpriv, REG_SYS_ISO_CTRL + 1, 0x68);
611
612 /* Enable AFE PLL Macro Block */
613 /* We need to delay 100u before enabling PLL. */
614 udelay(200);
615 tmpu1b = rtl_read_byte(rtlpriv, AFE_PLL_CTRL);
616 rtl_write_byte(rtlpriv, AFE_PLL_CTRL, (tmpu1b | BIT(0) | BIT(4)));
617
618 /* for divider reset */
619 udelay(100);
620 rtl_write_byte(rtlpriv, AFE_PLL_CTRL, (tmpu1b | BIT(0) |
621 BIT(4) | BIT(6)));
622 udelay(10);
623 rtl_write_byte(rtlpriv, AFE_PLL_CTRL, (tmpu1b | BIT(0) | BIT(4)));
624 udelay(10);
625
626 /* Enable MAC 80MHZ clock */
627 tmpu1b = rtl_read_byte(rtlpriv, AFE_PLL_CTRL + 1);
628 rtl_write_byte(rtlpriv, AFE_PLL_CTRL + 1, (tmpu1b | BIT(0)));
629 mdelay(1);
630
631 /* Release isolation AFE PLL & MD */
632 rtl_write_byte(rtlpriv, REG_SYS_ISO_CTRL, 0xA6);
633
634 /* Enable MAC clock */
635 tmpu2b = rtl_read_word(rtlpriv, SYS_CLKR);
636 rtl_write_word(rtlpriv, SYS_CLKR, (tmpu2b | BIT(12) | BIT(11)));
637
638 /* Enable Core digital and enable IOREG R/W */
639 tmpu2b = rtl_read_word(rtlpriv, REG_SYS_FUNC_EN);
640 rtl_write_word(rtlpriv, REG_SYS_FUNC_EN, (tmpu2b | BIT(11)));
641
642 tmpu1b = rtl_read_byte(rtlpriv, REG_SYS_FUNC_EN + 1);
643 rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN + 1, tmpu1b & ~(BIT(7)));
644
645 /* enable REG_EN */
646 rtl_write_word(rtlpriv, REG_SYS_FUNC_EN, (tmpu2b | BIT(11) | BIT(15)));
647
648 /* Switch the control path. */
649 tmpu2b = rtl_read_word(rtlpriv, SYS_CLKR);
650 rtl_write_word(rtlpriv, SYS_CLKR, (tmpu2b & (~BIT(2))));
651
652 tmpu1b = rtl_read_byte(rtlpriv, (SYS_CLKR + 1));
653 tmpu1b = ((tmpu1b | BIT(7)) & (~BIT(6)));
654 if (!_rtl92ce_halset_sysclk(hw, tmpu1b))
655 return; /* Set failed, return to prevent hang. */
656
657 rtl_write_word(rtlpriv, CMDR, 0x07FC);
658
659 /* MH We must enable the section of code to prevent load IMEM fail. */
660 /* Load MAC register from WMAc temporarily We simulate macreg. */
661 /* txt HW will provide MAC txt later */
662 rtl_write_byte(rtlpriv, 0x6, 0x30);
663 rtl_write_byte(rtlpriv, 0x49, 0xf0);
664
665 rtl_write_byte(rtlpriv, 0x4b, 0x81);
666
667 rtl_write_byte(rtlpriv, 0xb5, 0x21);
668
669 rtl_write_byte(rtlpriv, 0xdc, 0xff);
670 rtl_write_byte(rtlpriv, 0xdd, 0xff);
671 rtl_write_byte(rtlpriv, 0xde, 0xff);
672 rtl_write_byte(rtlpriv, 0xdf, 0xff);
673
674 rtl_write_byte(rtlpriv, 0x11a, 0x00);
675 rtl_write_byte(rtlpriv, 0x11b, 0x00);
676
677 for (i = 0; i < 32; i++)
678 rtl_write_byte(rtlpriv, INIMCS_SEL + i, 0x1b);
679
680 rtl_write_byte(rtlpriv, 0x236, 0xff);
681
682 rtl_write_byte(rtlpriv, 0x503, 0x22);
683
684 if (ppsc->support_aspm && !ppsc->support_backdoor)
685 rtl_write_byte(rtlpriv, 0x560, 0x40);
686 else
687 rtl_write_byte(rtlpriv, 0x560, 0x00);
688
689 rtl_write_byte(rtlpriv, DBG_PORT, 0x91);
690
691 /* Set RX Desc Address */
692 rtl_write_dword(rtlpriv, RDQDA, rtlpci->rx_ring[RX_MPDU_QUEUE].dma);
693 rtl_write_dword(rtlpriv, RCDA, rtlpci->rx_ring[RX_CMD_QUEUE].dma);
694
695 /* Set TX Desc Address */
696 rtl_write_dword(rtlpriv, TBKDA, rtlpci->tx_ring[BK_QUEUE].dma);
697 rtl_write_dword(rtlpriv, TBEDA, rtlpci->tx_ring[BE_QUEUE].dma);
698 rtl_write_dword(rtlpriv, TVIDA, rtlpci->tx_ring[VI_QUEUE].dma);
699 rtl_write_dword(rtlpriv, TVODA, rtlpci->tx_ring[VO_QUEUE].dma);
700 rtl_write_dword(rtlpriv, TBDA, rtlpci->tx_ring[BEACON_QUEUE].dma);
701 rtl_write_dword(rtlpriv, TCDA, rtlpci->tx_ring[TXCMD_QUEUE].dma);
702 rtl_write_dword(rtlpriv, TMDA, rtlpci->tx_ring[MGNT_QUEUE].dma);
703 rtl_write_dword(rtlpriv, THPDA, rtlpci->tx_ring[HIGH_QUEUE].dma);
704 rtl_write_dword(rtlpriv, HDA, rtlpci->tx_ring[HCCA_QUEUE].dma);
705
706 rtl_write_word(rtlpriv, CMDR, 0x37FC);
707
708 /* To make sure that TxDMA can ready to download FW. */
709 /* We should reset TxDMA if IMEM RPT was not ready. */
710 do {
711 tmpu1b = rtl_read_byte(rtlpriv, TCR);
712 if ((tmpu1b & TXDMA_INIT_VALUE) == TXDMA_INIT_VALUE)
713 break;
714
715 udelay(5);
716 } while (pollingcnt--);
717
718 if (pollingcnt <= 0) {
719 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
720 ("Polling TXDMA_INIT_VALUE "
721 "timeout!! Current TCR(%#x)\n", tmpu1b));
722 tmpu1b = rtl_read_byte(rtlpriv, CMDR);
723 rtl_write_byte(rtlpriv, CMDR, tmpu1b & (~TXDMA_EN));
724 udelay(2);
725 /* Reset TxDMA */
726 rtl_write_byte(rtlpriv, CMDR, tmpu1b | TXDMA_EN);
727 }
728
729 /* After MACIO reset,we must refresh LED state. */
730 if ((ppsc->rfoff_reason == RF_CHANGE_BY_IPS) ||
731 (ppsc->rfoff_reason == 0)) {
732 struct rtl_pci_priv *pcipriv = rtl_pcipriv(hw);
733 struct rtl_led *pLed0 = &(pcipriv->ledctl.sw_led0);
734 enum rf_pwrstate rfpwr_state_toset;
735 rfpwr_state_toset = _rtl92se_rf_onoff_detect(hw);
736
737 if (rfpwr_state_toset == ERFON)
738 rtl92se_sw_led_on(hw, pLed0);
739 }
740}
741
742static void _rtl92se_macconfig_after_fwdownload(struct ieee80211_hw *hw)
743{
744 struct rtl_priv *rtlpriv = rtl_priv(hw);
745 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
746 struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
747 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
748 u8 i;
749 u16 tmpu2b;
750
751 /* 1. System Configure Register (Offset: 0x0000 - 0x003F) */
752
753 /* 2. Command Control Register (Offset: 0x0040 - 0x004F) */
754 /* Turn on 0x40 Command register */
755 rtl_write_word(rtlpriv, CMDR, (BBRSTN | BB_GLB_RSTN |
756 SCHEDULE_EN | MACRXEN | MACTXEN | DDMA_EN | FW2HW_EN |
757 RXDMA_EN | TXDMA_EN | HCI_RXDMA_EN | HCI_TXDMA_EN));
758
759 /* Set TCR TX DMA pre 2 FULL enable bit */
760 rtl_write_dword(rtlpriv, TCR, rtl_read_dword(rtlpriv, TCR) |
761 TXDMAPRE2FULL);
762
763 /* Set RCR */
764 rtl_write_dword(rtlpriv, RCR, rtlpci->receive_config);
765
766 /* 3. MACID Setting Register (Offset: 0x0050 - 0x007F) */
767
768 /* 4. Timing Control Register (Offset: 0x0080 - 0x009F) */
769 /* Set CCK/OFDM SIFS */
770 /* CCK SIFS shall always be 10us. */
771 rtl_write_word(rtlpriv, SIFS_CCK, 0x0a0a);
772 rtl_write_word(rtlpriv, SIFS_OFDM, 0x1010);
773
774 /* Set AckTimeout */
775 rtl_write_byte(rtlpriv, ACK_TIMEOUT, 0x40);
776
777 /* Beacon related */
778 rtl_write_word(rtlpriv, BCN_INTERVAL, 100);
779 rtl_write_word(rtlpriv, ATIMWND, 2);
780
781 /* 5. FIFO Control Register (Offset: 0x00A0 - 0x015F) */
782 /* 5.1 Initialize Number of Reserved Pages in Firmware Queue */
783 /* Firmware allocate now, associate with FW internal setting.!!! */
784
785 /* 5.2 Setting TX/RX page size 0/1/2/3/4=64/128/256/512/1024 */
786 /* 5.3 Set driver info, we only accept PHY status now. */
787 /* 5.4 Set RXDMA arbitration to control RXDMA/MAC/FW R/W for RXFIFO */
788 rtl_write_byte(rtlpriv, RXDMA, rtl_read_byte(rtlpriv, RXDMA) | BIT(6));
789
790 /* 6. Adaptive Control Register (Offset: 0x0160 - 0x01CF) */
791 /* Set RRSR to all legacy rate and HT rate
792 * CCK rate is supported by default.
793 * CCK rate will be filtered out only when associated
794 * AP does not support it.
795 * Only enable ACK rate to OFDM 24M
796 * Disable RRSR for CCK rate in A-Cut */
797
798 if (rtlhal->version == VERSION_8192S_ACUT)
799 rtl_write_byte(rtlpriv, RRSR, 0xf0);
800 else if (rtlhal->version == VERSION_8192S_BCUT)
801 rtl_write_byte(rtlpriv, RRSR, 0xff);
802 rtl_write_byte(rtlpriv, RRSR + 1, 0x01);
803 rtl_write_byte(rtlpriv, RRSR + 2, 0x00);
804
805 /* A-Cut IC do not support CCK rate. We forbid ARFR to */
806 /* fallback to CCK rate */
807 for (i = 0; i < 8; i++) {
808 /*Disable RRSR for CCK rate in A-Cut */
809 if (rtlhal->version == VERSION_8192S_ACUT)
810 rtl_write_dword(rtlpriv, ARFR0 + i * 4, 0x1f0ff0f0);
811 }
812
813 /* Different rate use different AMPDU size */
814 /* MCS32/ MCS15_SG use max AMPDU size 15*2=30K */
815 rtl_write_byte(rtlpriv, AGGLEN_LMT_H, 0x0f);
816 /* MCS0/1/2/3 use max AMPDU size 4*2=8K */
817 rtl_write_word(rtlpriv, AGGLEN_LMT_L, 0x7442);
818 /* MCS4/5 use max AMPDU size 8*2=16K 6/7 use 10*2=20K */
819 rtl_write_word(rtlpriv, AGGLEN_LMT_L + 2, 0xddd7);
820 /* MCS8/9 use max AMPDU size 8*2=16K 10/11 use 10*2=20K */
821 rtl_write_word(rtlpriv, AGGLEN_LMT_L + 4, 0xd772);
822 /* MCS12/13/14/15 use max AMPDU size 15*2=30K */
823 rtl_write_word(rtlpriv, AGGLEN_LMT_L + 6, 0xfffd);
824
825 /* Set Data / Response auto rate fallack retry count */
826 rtl_write_dword(rtlpriv, DARFRC, 0x04010000);
827 rtl_write_dword(rtlpriv, DARFRC + 4, 0x09070605);
828 rtl_write_dword(rtlpriv, RARFRC, 0x04010000);
829 rtl_write_dword(rtlpriv, RARFRC + 4, 0x09070605);
830
831 /* 7. EDCA Setting Register (Offset: 0x01D0 - 0x01FF) */
832 /* Set all rate to support SG */
833 rtl_write_word(rtlpriv, SG_RATE, 0xFFFF);
834
835 /* 8. WMAC, BA, and CCX related Register (Offset: 0x0200 - 0x023F) */
836 /* Set NAV protection length */
837 rtl_write_word(rtlpriv, NAV_PROT_LEN, 0x0080);
838 /* CF-END Threshold */
839 rtl_write_byte(rtlpriv, CFEND_TH, 0xFF);
840 /* Set AMPDU minimum space */
841 rtl_write_byte(rtlpriv, AMPDU_MIN_SPACE, 0x07);
842 /* Set TXOP stall control for several queue/HI/BCN/MGT/ */
843 rtl_write_byte(rtlpriv, TXOP_STALL_CTRL, 0x00);
844
845 /* 9. Security Control Register (Offset: 0x0240 - 0x025F) */
846 /* 10. Power Save Control Register (Offset: 0x0260 - 0x02DF) */
847 /* 11. General Purpose Register (Offset: 0x02E0 - 0x02FF) */
848 /* 12. Host Interrupt Status Register (Offset: 0x0300 - 0x030F) */
849 /* 13. Test Mode and Debug Control Register (Offset: 0x0310 - 0x034F) */
850
851 /* 14. Set driver info, we only accept PHY status now. */
852 rtl_write_byte(rtlpriv, RXDRVINFO_SZ, 4);
853
854 /* 15. For EEPROM R/W Workaround */
855 /* 16. For EFUSE to share REG_SYS_FUNC_EN with EEPROM!!! */
856 tmpu2b = rtl_read_byte(rtlpriv, REG_SYS_FUNC_EN);
857 rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN, tmpu2b | BIT(13));
858 tmpu2b = rtl_read_byte(rtlpriv, REG_SYS_ISO_CTRL);
859 rtl_write_byte(rtlpriv, REG_SYS_ISO_CTRL, tmpu2b & (~BIT(8)));
860
861 /* 17. For EFUSE */
862 /* We may R/W EFUSE in EEPROM mode */
863 if (rtlefuse->epromtype == EEPROM_BOOT_EFUSE) {
864 u8 tempval;
865
866 tempval = rtl_read_byte(rtlpriv, REG_SYS_ISO_CTRL + 1);
867 tempval &= 0xFE;
868 rtl_write_byte(rtlpriv, REG_SYS_ISO_CTRL + 1, tempval);
869
870 /* Change Program timing */
871 rtl_write_byte(rtlpriv, REG_EFUSE_CTRL + 3, 0x72);
872 RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG, ("EFUSE CONFIG OK\n"));
873 }
874
875 RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG, ("OK\n"));
876
877}
878
879static void _rtl92se_hw_configure(struct ieee80211_hw *hw)
880{
881 struct rtl_priv *rtlpriv = rtl_priv(hw);
882 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
883 struct rtl_phy *rtlphy = &(rtlpriv->phy);
884 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
885
886 u8 reg_bw_opmode = 0;
78d57372 887 u32 reg_rrsr = 0;
24284531
CL		 888 u8 regtmp = 0;
889
890 reg_bw_opmode = BW_OPMODE_20MHZ;
24284531
CL		 891 reg_rrsr = RATE_ALL_CCK | RATE_ALL_OFDM_AG;
892
893 regtmp = rtl_read_byte(rtlpriv, INIRTSMCS_SEL);
894 reg_rrsr = ((reg_rrsr & 0x000fffff) << 8) | regtmp;
895 rtl_write_dword(rtlpriv, INIRTSMCS_SEL, reg_rrsr);
896 rtl_write_byte(rtlpriv, BW_OPMODE, reg_bw_opmode);
897
898 /* Set Retry Limit here */
899 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_RETRY_LIMIT,
900 (u8 *)(&rtlpci->shortretry_limit));
901
902 rtl_write_byte(rtlpriv, MLT, 0x8f);
903
904 /* For Min Spacing configuration. */
905 switch (rtlphy->rf_type) {
906 case RF_1T2R:
907 case RF_1T1R:
908 rtlhal->minspace_cfg = (MAX_MSS_DENSITY_1T << 3);
909 break;
910 case RF_2T2R:
911 case RF_2T2R_GREEN:
912 rtlhal->minspace_cfg = (MAX_MSS_DENSITY_2T << 3);
913 break;
914 }
915 rtl_write_byte(rtlpriv, AMPDU_MIN_SPACE, rtlhal->minspace_cfg);
916}
917
918int rtl92se_hw_init(struct ieee80211_hw *hw)
919{
920 struct rtl_priv *rtlpriv = rtl_priv(hw);
921 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
922 struct rtl_phy *rtlphy = &(rtlpriv->phy);
923 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
924 struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
925 u8 tmp_byte = 0;
926
927 bool rtstatus = true;
928 u8 tmp_u1b;
929 int err = false;
930 u8 i;
931 int wdcapra_add[] = {
932 EDCAPARA_BE, EDCAPARA_BK,
933 EDCAPARA_VI, EDCAPARA_VO};
934 u8 secr_value = 0x0;
935
936 rtlpci->being_init_adapter = true;
937
938 rtlpriv->intf_ops->disable_aspm(hw);
939
940 /* 1. MAC Initialize */
941 /* Before FW download, we have to set some MAC register */
942 _rtl92se_macconfig_before_fwdownload(hw);
943
944 rtlhal->version = (enum version_8192s)((rtl_read_dword(rtlpriv,
945 PMC_FSM) >> 16) & 0xF);
946
947 rtl8192se_gpiobit3_cfg_inputmode(hw);
948
949 /* 2. download firmware */
950 rtstatus = rtl92s_download_fw(hw);
951 if (!rtstatus) {
952 RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING,
953 ("Failed to download FW. "
954 "Init HW without FW now.., Please copy FW into"
955 "/lib/firmware/rtlwifi\n"));
956 rtlhal->fw_ready = false;
957 } else {
958 rtlhal->fw_ready = true;
959 }
960
961 /* After FW download, we have to reset MAC register */
962 _rtl92se_macconfig_after_fwdownload(hw);
963
964 /*Retrieve default FW Cmd IO map. */
965 rtlhal->fwcmd_iomap = rtl_read_word(rtlpriv, LBUS_MON_ADDR);
966 rtlhal->fwcmd_ioparam = rtl_read_dword(rtlpriv, LBUS_ADDR_MASK);
967
968 /* 3. Initialize MAC/PHY Config by MACPHY_reg.txt */
969 if (rtl92s_phy_mac_config(hw) != true) {
970 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG, ("MAC Config failed\n"));
971 return rtstatus;
972 }
973
974 /* Make sure BB/RF write OK. We should prevent enter IPS. radio off. */
975 /* We must set flag avoid BB/RF config period later!! */
976 rtl_write_dword(rtlpriv, CMDR, 0x37FC);
977
978 /* 4. Initialize BB After MAC Config PHY_reg.txt, AGC_Tab.txt */
979 if (rtl92s_phy_bb_config(hw) != true) {
980 RT_TRACE(rtlpriv, COMP_INIT, DBG_EMERG, ("BB Config failed\n"));
981 return rtstatus;
982 }
983
984 /* 5. Initiailze RF RAIO_A.txt RF RAIO_B.txt */
985 /* Before initalizing RF. We can not use FW to do RF-R/W. */
986
987 rtlphy->rf_mode = RF_OP_BY_SW_3WIRE;
988
989 /* RF Power Save */
990#if 0
991 /* H/W or S/W RF OFF before sleep. */
992 if (rtlpriv->psc.rfoff_reason > RF_CHANGE_BY_PS) {
993 u32 rfoffreason = rtlpriv->psc.rfoff_reason;
994
995 rtlpriv->psc.rfoff_reason = RF_CHANGE_BY_INIT;
996 rtlpriv->psc.rfpwr_state = ERFON;
997 rtl_ps_set_rf_state(hw, ERFOFF, rfoffreason, true);
998 } else {
999 /* gpio radio on/off is out of adapter start */
1000 if (rtlpriv->psc.hwradiooff == false) {
1001 rtlpriv->psc.rfpwr_state = ERFON;
1002 rtlpriv->psc.rfoff_reason = 0;
1003 }
1004 }
1005#endif
1006
1007 /* Before RF-R/W we must execute the IO from Scott's suggestion. */
1008 rtl_write_byte(rtlpriv, AFE_XTAL_CTRL + 1, 0xDB);
1009 if (rtlhal->version == VERSION_8192S_ACUT)
1010 rtl_write_byte(rtlpriv, SPS1_CTRL + 3, 0x07);
1011 else
1012 rtl_write_byte(rtlpriv, RF_CTRL, 0x07);
1013
1014 if (rtl92s_phy_rf_config(hw) != true) {
1015 RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG, ("RF Config failed\n"));
1016 return rtstatus;
1017 }
1018
1019 /* After read predefined TXT, we must set BB/MAC/RF
1020 * register as our requirement */
1021
1022 rtlphy->rfreg_chnlval[0] = rtl92s_phy_query_rf_reg(hw,
1023 (enum radio_path)0,
1024 RF_CHNLBW,
1025 RFREG_OFFSET_MASK);
1026 rtlphy->rfreg_chnlval[1] = rtl92s_phy_query_rf_reg(hw,
1027 (enum radio_path)1,
1028 RF_CHNLBW,
1029 RFREG_OFFSET_MASK);
1030
1031 /*---- Set CCK and OFDM Block "ON"----*/
1032 rtl_set_bbreg(hw, RFPGA0_RFMOD, BCCKEN, 0x1);
1033 rtl_set_bbreg(hw, RFPGA0_RFMOD, BOFDMEN, 0x1);
1034
1035 /*3 Set Hardware(Do nothing now) */
1036 _rtl92se_hw_configure(hw);
1037
1038 /* Read EEPROM TX power index and PHY_REG_PG.txt to capture correct */
1039 /* TX power index for different rate set. */
1040 /* Get original hw reg values */
1041 rtl92s_phy_get_hw_reg_originalvalue(hw);
1042 /* Write correct tx power index */
1043 rtl92s_phy_set_txpower(hw, rtlphy->current_channel);
1044
1045 /* We must set MAC address after firmware download. */
1046 for (i = 0; i < 6; i++)
1047 rtl_write_byte(rtlpriv, MACIDR0 + i, rtlefuse->dev_addr[i]);
1048
1049 /* EEPROM R/W workaround */
1050 tmp_u1b = rtl_read_byte(rtlpriv, MAC_PINMUX_CFG);
1051 rtl_write_byte(rtlpriv, MAC_PINMUX_CFG, tmp_u1b & (~BIT(3)));
1052
1053 rtl_write_byte(rtlpriv, 0x4d, 0x0);
1054
1055 if (hal_get_firmwareversion(rtlpriv) >= 0x49) {
1056 tmp_byte = rtl_read_byte(rtlpriv, FW_RSVD_PG_CRTL) & (~BIT(4));
1057 tmp_byte = tmp_byte | BIT(5);
1058 rtl_write_byte(rtlpriv, FW_RSVD_PG_CRTL, tmp_byte);
1059 rtl_write_dword(rtlpriv, TXDESC_MSK, 0xFFFFCFFF);
1060 }
1061
1062 /* We enable high power and RA related mechanism after NIC
1063 * initialized. */
1064 rtl92s_phy_set_fw_cmd(hw, FW_CMD_RA_INIT);
1065
1066 /* Add to prevent ASPM bug. */
1067 /* Always enable hst and NIC clock request. */
1068 rtl92s_phy_switch_ephy_parameter(hw);
1069
1070 /* Security related
1071 * 1. Clear all H/W keys.
1072 * 2. Enable H/W encryption/decryption. */
1073 rtl_cam_reset_all_entry(hw);
1074 secr_value |= SCR_TXENCENABLE;
1075 secr_value |= SCR_RXENCENABLE;
1076 secr_value |= SCR_NOSKMC;
1077 rtl_write_byte(rtlpriv, REG_SECR, secr_value);
1078
1079 for (i = 0; i < 4; i++)
1080 rtl_write_dword(rtlpriv, wdcapra_add[i], 0x5e4322);
1081
1082 if (rtlphy->rf_type == RF_1T2R) {
1083 bool mrc2set = true;
1084 /* Turn on B-Path */
1085 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_MRC, (u8 *)&mrc2set);
1086 }
1087
1088 rtlpriv->cfg->ops->led_control(hw, LED_CTL_POWER_ON);
1089 rtl92s_dm_init(hw);
1090 rtlpci->being_init_adapter = false;
1091
1092 return err;
1093}
1094
1095void rtl92se_set_mac_addr(struct rtl_io *io, const u8 * addr)
1096{
1097}
1098
1099void rtl92se_set_check_bssid(struct ieee80211_hw *hw, bool check_bssid)
1100{
1101 struct rtl_priv *rtlpriv = rtl_priv(hw);
1102 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
1103 u32 reg_rcr = rtlpci->receive_config;
1104
1105 if (rtlpriv->psc.rfpwr_state != ERFON)
1106 return;
1107
1108 if (check_bssid == true) {
1109 reg_rcr |= (RCR_CBSSID);
1110 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_RCR, (u8 *)(&reg_rcr));
1111 } else if (check_bssid == false) {
1112 reg_rcr &= (~RCR_CBSSID);
1113 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_RCR, (u8 *)(&reg_rcr));
1114 }
1115
1116}
1117
1118static int _rtl92se_set_media_status(struct ieee80211_hw *hw,
1119 enum nl80211_iftype type)
1120{
1121 struct rtl_priv *rtlpriv = rtl_priv(hw);
1122 u8 bt_msr = rtl_read_byte(rtlpriv, MSR);
24284531
CL		 1123 u32 temp;
1124 bt_msr &= ~MSR_LINK_MASK;
1125
1126 switch (type) {
1127 case NL80211_IFTYPE_UNSPECIFIED:
1128 bt_msr |= (MSR_LINK_NONE << MSR_LINK_SHIFT);
24284531
CL		 1129 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
1130 ("Set Network type to NO LINK!\n"));
1131 break;
1132 case NL80211_IFTYPE_ADHOC:
1133 bt_msr |= (MSR_LINK_ADHOC << MSR_LINK_SHIFT);
1134 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
1135 ("Set Network type to Ad Hoc!\n"));
1136 break;
1137 case NL80211_IFTYPE_STATION:
1138 bt_msr |= (MSR_LINK_MANAGED << MSR_LINK_SHIFT);
24284531
CL		 1139 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
1140 ("Set Network type to STA!\n"));
1141 break;
1142 case NL80211_IFTYPE_AP:
1143 bt_msr |= (MSR_LINK_MASTER << MSR_LINK_SHIFT);
1144 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
1145 ("Set Network type to AP!\n"));
1146 break;
1147 default:
1148 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
1149 ("Network type %d not support!\n", type));
1150 return 1;
1151 break;
1152
1153 }
1154
1155 rtl_write_byte(rtlpriv, (MSR), bt_msr);
1156
1157 temp = rtl_read_dword(rtlpriv, TCR);
1158 rtl_write_dword(rtlpriv, TCR, temp & (~BIT(8)));
1159 rtl_write_dword(rtlpriv, TCR, temp | BIT(8));
1160
1161
1162 return 0;
1163}
1164
1165/* HW_VAR_MEDIA_STATUS & HW_VAR_CECHK_BSSID */
1166int rtl92se_set_network_type(struct ieee80211_hw *hw, enum nl80211_iftype type)
1167{
1168 struct rtl_priv *rtlpriv = rtl_priv(hw);
1169
1170 if (_rtl92se_set_media_status(hw, type))
1171 return -EOPNOTSUPP;
1172
1173 if (rtlpriv->mac80211.link_state == MAC80211_LINKED) {
1174 if (type != NL80211_IFTYPE_AP)
1175 rtl92se_set_check_bssid(hw, true);
1176 } else {
1177 rtl92se_set_check_bssid(hw, false);
1178 }
1179
1180 return 0;
1181}
1182
1183/* don't set REG_EDCA_BE_PARAM here because mac80211 will send pkt when scan */
1184void rtl92se_set_qos(struct ieee80211_hw *hw, int aci)
1185{
1186 struct rtl_priv *rtlpriv = rtl_priv(hw);
1187 rtl92s_dm_init_edca_turbo(hw);
1188
1189 switch (aci) {
1190 case AC1_BK:
1191 rtl_write_dword(rtlpriv, EDCAPARA_BK, 0xa44f);
1192 break;
1193 case AC0_BE:
1194 /* rtl_write_dword(rtlpriv, EDCAPARA_BE, u4b_ac_param); */
1195 break;
1196 case AC2_VI:
1197 rtl_write_dword(rtlpriv, EDCAPARA_VI, 0x5e4322);
1198 break;
1199 case AC3_VO:
1200 rtl_write_dword(rtlpriv, EDCAPARA_VO, 0x2f3222);
1201 break;
1202 default:
1203 RT_ASSERT(false, ("invalid aci: %d !\n", aci));
1204 break;
1205 }
1206}
1207
1208void rtl92se_enable_interrupt(struct ieee80211_hw *hw)
1209{
1210 struct rtl_priv *rtlpriv = rtl_priv(hw);
1211 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
1212
1213 rtl_write_dword(rtlpriv, INTA_MASK, rtlpci->irq_mask[0]);
1214 /* Support Bit 32-37(Assign as Bit 0-5) interrupt setting now */
1215 rtl_write_dword(rtlpriv, INTA_MASK + 4, rtlpci->irq_mask[1] & 0x3F);
1216
1217 rtlpci->irq_enabled = true;
1218}
1219
1220void rtl92se_disable_interrupt(struct ieee80211_hw *hw)
1221{
1222 struct rtl_priv *rtlpriv = rtl_priv(hw);
1223 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
1224
1225 rtl_write_dword(rtlpriv, INTA_MASK, 0);
1226 rtl_write_dword(rtlpriv, INTA_MASK + 4, 0);
1227
1228 rtlpci->irq_enabled = false;
1229}
1230
1231
1232static u8 _rtl92s_set_sysclk(struct ieee80211_hw *hw, u8 data)
1233{
1234 struct rtl_priv *rtlpriv = rtl_priv(hw);
1235 u8 waitcnt = 100;
1236 bool result = false;
1237 u8 tmp;
1238
1239 rtl_write_byte(rtlpriv, SYS_CLKR + 1, data);
1240
1241 /* Wait the MAC synchronized. */
1242 udelay(400);
1243
1244 /* Check if it is set ready. */
1245 tmp = rtl_read_byte(rtlpriv, SYS_CLKR + 1);
1246 result = ((tmp & BIT(7)) == (data & BIT(7)));
1247
1248 if ((data & (BIT(6) | BIT(7))) == false) {
1249 waitcnt = 100;
1250 tmp = 0;
1251
1252 while (1) {
1253 waitcnt--;
1254 tmp = rtl_read_byte(rtlpriv, SYS_CLKR + 1);
1255
1256 if ((tmp & BIT(6)))
1257 break;
1258
1259 printk(KERN_ERR "wait for BIT(6) return value %x\n",
1260 tmp);
1261
1262 if (waitcnt == 0)
1263 break;
1264 udelay(10);
1265 }
1266
1267 if (waitcnt == 0)
1268 result = false;
1269 else
1270 result = true;
1271 }
1272
1273 return result;
1274}
1275
1276static void _rtl92s_phy_set_rfhalt(struct ieee80211_hw *hw)
1277{
1278 struct rtl_priv *rtlpriv = rtl_priv(hw);
1279 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
1280 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
1281 u8 u1btmp;
1282
1283 if (rtlhal->driver_going2unload)
1284 rtl_write_byte(rtlpriv, 0x560, 0x0);
1285
1286 /* Power save for BB/RF */
1287 u1btmp = rtl_read_byte(rtlpriv, LDOV12D_CTRL);
1288 u1btmp |= BIT(0);
1289 rtl_write_byte(rtlpriv, LDOV12D_CTRL, u1btmp);
1290 rtl_write_byte(rtlpriv, SPS1_CTRL, 0x0);
1291 rtl_write_byte(rtlpriv, TXPAUSE, 0xFF);
1292 rtl_write_word(rtlpriv, CMDR, 0x57FC);
1293 udelay(100);
1294 rtl_write_word(rtlpriv, CMDR, 0x77FC);
1295 rtl_write_byte(rtlpriv, PHY_CCA, 0x0);
1296 udelay(10);
1297 rtl_write_word(rtlpriv, CMDR, 0x37FC);
1298 udelay(10);
1299 rtl_write_word(rtlpriv, CMDR, 0x77FC);
1300 udelay(10);
1301 rtl_write_word(rtlpriv, CMDR, 0x57FC);
1302 rtl_write_word(rtlpriv, CMDR, 0x0000);
1303
1304 if (rtlhal->driver_going2unload) {
1305 u1btmp = rtl_read_byte(rtlpriv, (REG_SYS_FUNC_EN + 1));
1306 u1btmp &= ~(BIT(0));
1307 rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN + 1, u1btmp);
1308 }
1309
1310 u1btmp = rtl_read_byte(rtlpriv, (SYS_CLKR + 1));
1311
1312 /* Add description. After switch control path. register
1313 * after page1 will be invisible. We can not do any IO
1314 * for register>0x40. After resume&MACIO reset, we need
1315 * to remember previous reg content. */
1316 if (u1btmp & BIT(7)) {
1317 u1btmp &= ~(BIT(6) | BIT(7));
1318 if (!_rtl92s_set_sysclk(hw, u1btmp)) {
1319 printk(KERN_ERR "Switch ctrl path fail\n");
1320 return;
1321 }
1322 }
1323
1324 /* Power save for MAC */
1325 if (ppsc->rfoff_reason == RF_CHANGE_BY_IPS &&
1326 !rtlhal->driver_going2unload) {
1327 /* enable LED function */
1328 rtl_write_byte(rtlpriv, 0x03, 0xF9);
1329 /* SW/HW radio off or halt adapter!! For example S3/S4 */
1330 } else {
1331 /* LED function disable. Power range is about 8mA now. */
1332 /* if write 0xF1 disconnet_pci power
1333 * ifconfig wlan0 down power are both high 35:70 */
1334 /* if write oxF9 disconnet_pci power
1335 * ifconfig wlan0 down power are both low 12:45*/
1336 rtl_write_byte(rtlpriv, 0x03, 0xF9);
1337 }
1338
1339 rtl_write_byte(rtlpriv, SYS_CLKR + 1, 0x70);
1340 rtl_write_byte(rtlpriv, AFE_PLL_CTRL + 1, 0x68);
1341 rtl_write_byte(rtlpriv, AFE_PLL_CTRL, 0x00);
1342 rtl_write_byte(rtlpriv, LDOA15_CTRL, 0x34);
1343 rtl_write_byte(rtlpriv, AFE_XTAL_CTRL, 0x0E);
1344 RT_SET_PS_LEVEL(ppsc, RT_RF_OFF_LEVL_HALT_NIC);
1345
1346}
1347
1348static void _rtl92se_gen_refreshledstate(struct ieee80211_hw *hw)
1349{
1350 struct rtl_priv *rtlpriv = rtl_priv(hw);
1351 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
1352 struct rtl_pci_priv *pcipriv = rtl_pcipriv(hw);
1353 struct rtl_led *pLed0 = &(pcipriv->ledctl.sw_led0);
1354
1355 if (rtlpci->up_first_time == 1)
1356 return;
1357
1358 if (rtlpriv->psc.rfoff_reason == RF_CHANGE_BY_IPS)
1359 rtl92se_sw_led_on(hw, pLed0);
1360 else
1361 rtl92se_sw_led_off(hw, pLed0);
1362}
1363
1364
1365static void _rtl92se_power_domain_init(struct ieee80211_hw *hw)
1366{
1367 struct rtl_priv *rtlpriv = rtl_priv(hw);
1368 u16 tmpu2b;
1369 u8 tmpu1b;
1370
1371 rtlpriv->psc.pwrdomain_protect = true;
1372
1373 tmpu1b = rtl_read_byte(rtlpriv, (SYS_CLKR + 1));
1374 if (tmpu1b & BIT(7)) {
1375 tmpu1b &= ~(BIT(6) | BIT(7));
1376 if (!_rtl92s_set_sysclk(hw, tmpu1b)) {
1377 rtlpriv->psc.pwrdomain_protect = false;
1378 return;
1379 }
1380 }
1381
1382 rtl_write_byte(rtlpriv, AFE_PLL_CTRL, 0x0);
1383 rtl_write_byte(rtlpriv, LDOA15_CTRL, 0x34);
1384
1385 /* Reset MAC-IO and CPU and Core Digital BIT10/11/15 */
1386 tmpu1b = rtl_read_byte(rtlpriv, SYS_FUNC_EN + 1);
1387
1388 /* If IPS we need to turn LED on. So we not
1389 * not disable BIT 3/7 of reg3. */
1390 if (rtlpriv->psc.rfoff_reason & (RF_CHANGE_BY_IPS | RF_CHANGE_BY_HW))
1391 tmpu1b &= 0xFB;
1392 else
1393 tmpu1b &= 0x73;
1394
1395 rtl_write_byte(rtlpriv, SYS_FUNC_EN + 1, tmpu1b);
1396 /* wait for BIT 10/11/15 to pull high automatically!! */
1397 mdelay(1);
1398
1399 rtl_write_byte(rtlpriv, CMDR, 0);
1400 rtl_write_byte(rtlpriv, TCR, 0);
1401
1402 /* Data sheet not define 0x562!!! Copy from WMAC!!!!! */
1403 tmpu1b = rtl_read_byte(rtlpriv, 0x562);
1404 tmpu1b |= 0x08;
1405 rtl_write_byte(rtlpriv, 0x562, tmpu1b);
1406 tmpu1b &= ~(BIT(3));
1407 rtl_write_byte(rtlpriv, 0x562, tmpu1b);
1408
1409 /* Enable AFE clock source */
1410 tmpu1b = rtl_read_byte(rtlpriv, AFE_XTAL_CTRL);
1411 rtl_write_byte(rtlpriv, AFE_XTAL_CTRL, (tmpu1b | 0x01));
1412 /* Delay 1.5ms */
1413 udelay(1500);
1414 tmpu1b = rtl_read_byte(rtlpriv, AFE_XTAL_CTRL + 1);
1415 rtl_write_byte(rtlpriv, AFE_XTAL_CTRL + 1, (tmpu1b & 0xfb));
1416
1417 /* Enable AFE Macro Block's Bandgap */
1418 tmpu1b = rtl_read_byte(rtlpriv, AFE_MISC);
1419 rtl_write_byte(rtlpriv, AFE_MISC, (tmpu1b | BIT(0)));
1420 mdelay(1);
1421
1422 /* Enable AFE Mbias */
1423 tmpu1b = rtl_read_byte(rtlpriv, AFE_MISC);
1424 rtl_write_byte(rtlpriv, AFE_MISC, (tmpu1b | 0x02));
1425 mdelay(1);
1426
1427 /* Enable LDOA15 block */
1428 tmpu1b = rtl_read_byte(rtlpriv, LDOA15_CTRL);
1429 rtl_write_byte(rtlpriv, LDOA15_CTRL, (tmpu1b | BIT(0)));
1430
1431 /* Set Digital Vdd to Retention isolation Path. */
1432 tmpu2b = rtl_read_word(rtlpriv, SYS_ISO_CTRL);
1433 rtl_write_word(rtlpriv, SYS_ISO_CTRL, (tmpu2b | BIT(11)));
1434
1435
1436 /* For warm reboot NIC disappera bug. */
1437 tmpu2b = rtl_read_word(rtlpriv, SYS_FUNC_EN);
1438 rtl_write_word(rtlpriv, SYS_FUNC_EN, (tmpu2b | BIT(13)));
1439
1440 rtl_write_byte(rtlpriv, SYS_ISO_CTRL + 1, 0x68);
1441
1442 /* Enable AFE PLL Macro Block */
1443 tmpu1b = rtl_read_byte(rtlpriv, AFE_PLL_CTRL);
1444 rtl_write_byte(rtlpriv, AFE_PLL_CTRL, (tmpu1b | BIT(0) | BIT(4)));
1445 /* Enable MAC 80MHZ clock */
1446 tmpu1b = rtl_read_byte(rtlpriv, AFE_PLL_CTRL + 1);
1447 rtl_write_byte(rtlpriv, AFE_PLL_CTRL + 1, (tmpu1b | BIT(0)));
1448 mdelay(1);
1449
1450 /* Release isolation AFE PLL & MD */
1451 rtl_write_byte(rtlpriv, SYS_ISO_CTRL, 0xA6);
1452
1453 /* Enable MAC clock */
1454 tmpu2b = rtl_read_word(rtlpriv, SYS_CLKR);
1455 rtl_write_word(rtlpriv, SYS_CLKR, (tmpu2b | BIT(12) | BIT(11)));
1456
1457 /* Enable Core digital and enable IOREG R/W */
1458 tmpu2b = rtl_read_word(rtlpriv, SYS_FUNC_EN);
1459 rtl_write_word(rtlpriv, SYS_FUNC_EN, (tmpu2b | BIT(11)));
1460 /* enable REG_EN */
1461 rtl_write_word(rtlpriv, SYS_FUNC_EN, (tmpu2b | BIT(11) | BIT(15)));
1462
1463 /* Switch the control path. */
1464 tmpu2b = rtl_read_word(rtlpriv, SYS_CLKR);
1465 rtl_write_word(rtlpriv, SYS_CLKR, (tmpu2b & (~BIT(2))));
1466
1467 tmpu1b = rtl_read_byte(rtlpriv, (SYS_CLKR + 1));
1468 tmpu1b = ((tmpu1b | BIT(7)) & (~BIT(6)));
1469 if (!_rtl92s_set_sysclk(hw, tmpu1b)) {
1470 rtlpriv->psc.pwrdomain_protect = false;
1471 return;
1472 }
1473
1474 rtl_write_word(rtlpriv, CMDR, 0x37FC);
1475
1476 /* After MACIO reset,we must refresh LED state. */
1477 _rtl92se_gen_refreshledstate(hw);
1478
1479 rtlpriv->psc.pwrdomain_protect = false;
1480}
1481
1482void rtl92se_card_disable(struct ieee80211_hw *hw)
1483{
1484 struct rtl_priv *rtlpriv = rtl_priv(hw);
1485 struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
1486 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
1487 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
1488 enum nl80211_iftype opmode;
1489 u8 wait = 30;
1490
1491 rtlpriv->intf_ops->enable_aspm(hw);
1492
1493 if (rtlpci->driver_is_goingto_unload ||
1494 ppsc->rfoff_reason > RF_CHANGE_BY_PS)
1495 rtlpriv->cfg->ops->led_control(hw, LED_CTL_POWER_OFF);
1496
1497 /* we should chnge GPIO to input mode
1498 * this will drop away current about 25mA*/
1499 rtl8192se_gpiobit3_cfg_inputmode(hw);
1500
1501 /* this is very important for ips power save */
1502 while (wait-- >= 10 && rtlpriv->psc.pwrdomain_protect) {
1503 if (rtlpriv->psc.pwrdomain_protect)
1504 mdelay(20);
1505 else
1506 break;
1507 }
1508
1509 mac->link_state = MAC80211_NOLINK;
1510 opmode = NL80211_IFTYPE_UNSPECIFIED;
1511 _rtl92se_set_media_status(hw, opmode);
1512
1513 _rtl92s_phy_set_rfhalt(hw);
1514 udelay(100);
1515}
1516
1517void rtl92se_interrupt_recognized(struct ieee80211_hw *hw, u32 *p_inta,
1518 u32 *p_intb)
1519{
1520 struct rtl_priv *rtlpriv = rtl_priv(hw);
1521 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
1522
1523 *p_inta = rtl_read_dword(rtlpriv, ISR) & rtlpci->irq_mask[0];
1524 rtl_write_dword(rtlpriv, ISR, *p_inta);
1525
1526 *p_intb = rtl_read_dword(rtlpriv, ISR + 4) & rtlpci->irq_mask[1];
1527 rtl_write_dword(rtlpriv, ISR + 4, *p_intb);
1528}
1529
1530void rtl92se_set_beacon_related_registers(struct ieee80211_hw *hw)
1531{
1532 struct rtl_priv *rtlpriv = rtl_priv(hw);
1533 struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
1534 u16 bcntime_cfg = 0;
1535 u16 bcn_cw = 6, bcn_ifs = 0xf;
1536 u16 atim_window = 2;
1537
1538 /* ATIM Window (in unit of TU). */
1539 rtl_write_word(rtlpriv, ATIMWND, atim_window);
1540
1541 /* Beacon interval (in unit of TU). */
1542 rtl_write_word(rtlpriv, BCN_INTERVAL, mac->beacon_interval);
1543
1544 /* DrvErlyInt (in unit of TU). (Time to send
1545 * interrupt to notify driver to change
1546 * beacon content) */
1547 rtl_write_word(rtlpriv, BCN_DRV_EARLY_INT, 10 << 4);
1548
1549 /* BcnDMATIM(in unit of us). Indicates the
1550 * time before TBTT to perform beacon queue DMA */
1551 rtl_write_word(rtlpriv, BCN_DMATIME, 256);
1552
1553 /* Force beacon frame transmission even
1554 * after receiving beacon frame from
1555 * other ad hoc STA */
1556 rtl_write_byte(rtlpriv, BCN_ERR_THRESH, 100);
1557
1558 /* Beacon Time Configuration */
1559 if (mac->opmode == NL80211_IFTYPE_ADHOC)
1560 bcntime_cfg |= (bcn_cw << BCN_TCFG_CW_SHIFT);
1561
1562 /* TODO: bcn_ifs may required to be changed on ASIC */
1563 bcntime_cfg |= bcn_ifs << BCN_TCFG_IFS;
1564
1565 /*for beacon changed */
1566 rtl92s_phy_set_beacon_hwreg(hw, mac->beacon_interval);
1567}
1568
1569void rtl92se_set_beacon_interval(struct ieee80211_hw *hw)
1570{
1571 struct rtl_priv *rtlpriv = rtl_priv(hw);
1572 struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
1573 u16 bcn_interval = mac->beacon_interval;
1574
1575 /* Beacon interval (in unit of TU). */
1576 rtl_write_word(rtlpriv, BCN_INTERVAL, bcn_interval);
1577 /* 2008.10.24 added by tynli for beacon changed. */
1578 rtl92s_phy_set_beacon_hwreg(hw, bcn_interval);
1579}
1580
1581void rtl92se_update_interrupt_mask(struct ieee80211_hw *hw,
1582 u32 add_msr, u32 rm_msr)
1583{
1584 struct rtl_priv *rtlpriv = rtl_priv(hw);
1585 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
1586
1587 RT_TRACE(rtlpriv, COMP_INTR, DBG_LOUD,
1588 ("add_msr:%x, rm_msr:%x\n", add_msr, rm_msr));
1589
1590 if (add_msr)
1591 rtlpci->irq_mask[0] |= add_msr;
1592
1593 if (rm_msr)
1594 rtlpci->irq_mask[0] &= (~rm_msr);
1595
1596 rtl92se_disable_interrupt(hw);
1597 rtl92se_enable_interrupt(hw);
1598}
1599
1600static void _rtl8192se_get_IC_Inferiority(struct ieee80211_hw *hw)
1601{
1602 struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
1603 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
1604 u8 efuse_id;
1605
1606 rtlhal->ic_class = IC_INFERIORITY_A;
1607
1608 /* Only retrieving while using EFUSE. */
1609 if ((rtlefuse->epromtype == EEPROM_BOOT_EFUSE) &&
1610 !rtlefuse->autoload_failflag) {
1611 efuse_id = efuse_read_1byte(hw, EFUSE_IC_ID_OFFSET);
1612
1613 if (efuse_id == 0xfe)
1614 rtlhal->ic_class = IC_INFERIORITY_B;
1615 }
1616}
1617
1618static void _rtl92se_read_adapter_info(struct ieee80211_hw *hw)
1619{
1620 struct rtl_priv *rtlpriv = rtl_priv(hw);
1621 struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
1622 struct rtl_phy *rtlphy = &(rtlpriv->phy);
1623 u16 i, usvalue;
1624 u16 eeprom_id;
1625 u8 tempval;
1626 u8 hwinfo[HWSET_MAX_SIZE_92S];
1627 u8 rf_path, index;
1628
1629 if (rtlefuse->epromtype == EEPROM_93C46) {
1630 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
1631 ("RTL819X Not boot from eeprom, check it !!"));
1632 } else if (rtlefuse->epromtype == EEPROM_BOOT_EFUSE) {
1633 rtl_efuse_shadow_map_update(hw);
1634
1635 memcpy((void *)hwinfo, (void *)
1636 &rtlefuse->efuse_map[EFUSE_INIT_MAP][0],
1637 HWSET_MAX_SIZE_92S);
1638 }
1639
1640 RT_PRINT_DATA(rtlpriv, COMP_INIT, DBG_DMESG, ("MAP\n"),
1641 hwinfo, HWSET_MAX_SIZE_92S);
1642
1643 eeprom_id = *((u16 *)&hwinfo[0]);
1644 if (eeprom_id != RTL8190_EEPROM_ID) {
1645 RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING,
1646 ("EEPROM ID(%#x) is invalid!!\n", eeprom_id));
1647 rtlefuse->autoload_failflag = true;
1648 } else {
1649 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, ("Autoload OK\n"));
1650 rtlefuse->autoload_failflag = false;
1651 }
1652
1653 if (rtlefuse->autoload_failflag == true)
1654 return;
1655
1656 _rtl8192se_get_IC_Inferiority(hw);
1657
1658 /* Read IC Version && Channel Plan */
1659 /* VID, DID SE 0xA-D */
1660 rtlefuse->eeprom_vid = *(u16 *)&hwinfo[EEPROM_VID];
1661 rtlefuse->eeprom_did = *(u16 *)&hwinfo[EEPROM_DID];
1662 rtlefuse->eeprom_svid = *(u16 *)&hwinfo[EEPROM_SVID];
1663 rtlefuse->eeprom_smid = *(u16 *)&hwinfo[EEPROM_SMID];
1664 rtlefuse->eeprom_version = *(u16 *)&hwinfo[EEPROM_VERSION];
1665
1666 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
1667 ("EEPROMId = 0x%4x\n", eeprom_id));
1668 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
1669 ("EEPROM VID = 0x%4x\n", rtlefuse->eeprom_vid));
1670 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
1671 ("EEPROM DID = 0x%4x\n", rtlefuse->eeprom_did));
1672 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
1673 ("EEPROM SVID = 0x%4x\n", rtlefuse->eeprom_svid));
1674 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
1675 ("EEPROM SMID = 0x%4x\n", rtlefuse->eeprom_smid));
1676
1677 for (i = 0; i < 6; i += 2) {
1678 usvalue = *(u16 *)&hwinfo[EEPROM_MAC_ADDR + i];
1679 *((u16 *) (&rtlefuse->dev_addr[i])) = usvalue;
1680 }
1681
1682 for (i = 0; i < 6; i++)
1683 rtl_write_byte(rtlpriv, MACIDR0 + i, rtlefuse->dev_addr[i]);
1684
1685 RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG,
1686 (MAC_FMT "\n", MAC_ARG(rtlefuse->dev_addr)));
1687
1688 /* Get Tx Power Level by Channel */
1689 /* Read Tx power of Channel 1 ~ 14 from EEPROM. */
1690 /* 92S suupport RF A & B */
1691 for (rf_path = 0; rf_path < 2; rf_path++) {
1692 for (i = 0; i < 3; i++) {
1693 /* Read CCK RF A & B Tx power */
1694 rtlefuse->eeprom_chnlarea_txpwr_cck[rf_path][i] =
1695 hwinfo[EEPROM_TXPOWERBASE + rf_path * 3 + i];
1696
1697 /* Read OFDM RF A & B Tx power for 1T */
1698 rtlefuse->eeprom_chnlarea_txpwr_ht40_1s[rf_path][i] =
1699 hwinfo[EEPROM_TXPOWERBASE + 6 + rf_path * 3 + i];
1700
1701 /* Read OFDM RF A & B Tx power for 2T */
1702 rtlefuse->eeprom_chnlarea_txpwr_ht40_2sdiif[rf_path][i]
1703 = hwinfo[EEPROM_TXPOWERBASE + 12 +
1704 rf_path * 3 + i];
1705 }
1706 }
1707
1708 for (rf_path = 0; rf_path < 2; rf_path++)
1709 for (i = 0; i < 3; i++)
1710 RTPRINT(rtlpriv, FINIT, INIT_EEPROM,
1711 ("RF(%d) EEPROM CCK Area(%d) = 0x%x\n", rf_path,
1712 i, rtlefuse->eeprom_chnlarea_txpwr_cck
1713 [rf_path][i]));
1714 for (rf_path = 0; rf_path < 2; rf_path++)
1715 for (i = 0; i < 3; i++)
1716 RTPRINT(rtlpriv, FINIT, INIT_EEPROM,
1717 ("RF(%d) EEPROM HT40 1S Area(%d) = 0x%x\n",
1718 rf_path, i,
1719 rtlefuse->eeprom_chnlarea_txpwr_ht40_1s
1720 [rf_path][i]));
1721 for (rf_path = 0; rf_path < 2; rf_path++)
1722 for (i = 0; i < 3; i++)
1723 RTPRINT(rtlpriv, FINIT, INIT_EEPROM,
1724 ("RF(%d) EEPROM HT40 2S Diff Area(%d) = 0x%x\n",
1725 rf_path, i,
1726 rtlefuse->eeprom_chnlarea_txpwr_ht40_2sdiif
1727 [rf_path][i]));
1728
1729 for (rf_path = 0; rf_path < 2; rf_path++) {
1730
1731 /* Assign dedicated channel tx power */
1732 for (i = 0; i < 14; i++) {
1733 /* channel 1~3 use the same Tx Power Level. */
1734 if (i < 3)
1735 index = 0;
1736 /* Channel 4-8 */
1737 else if (i < 8)
1738 index = 1;
1739 /* Channel 9-14 */
1740 else
1741 index = 2;
1742
1743 /* Record A & B CCK /OFDM - 1T/2T Channel area
1744 * tx power */
1745 rtlefuse->txpwrlevel_cck[rf_path][i] =
1746 rtlefuse->eeprom_chnlarea_txpwr_cck
1747 [rf_path][index];
1748 rtlefuse->txpwrlevel_ht40_1s[rf_path][i] =
1749 rtlefuse->eeprom_chnlarea_txpwr_ht40_1s
1750 [rf_path][index];
1751 rtlefuse->txpwrlevel_ht40_2s[rf_path][i] =
1752 rtlefuse->eeprom_chnlarea_txpwr_ht40_2sdiif
1753 [rf_path][index];
1754 }
1755
1756 for (i = 0; i < 14; i++) {
1757 RTPRINT(rtlpriv, FINIT, INIT_TxPower,
1758 ("RF(%d)-Ch(%d) [CCK / HT40_1S / HT40_2S] = "
1759 "[0x%x / 0x%x / 0x%x]\n", rf_path, i,
1760 rtlefuse->txpwrlevel_cck[rf_path][i],
1761 rtlefuse->txpwrlevel_ht40_1s[rf_path][i],
1762 rtlefuse->txpwrlevel_ht40_2s[rf_path][i]));
1763 }
1764 }
1765
1766 for (rf_path = 0; rf_path < 2; rf_path++) {
1767 for (i = 0; i < 3; i++) {
1768 /* Read Power diff limit. */
1769 rtlefuse->eeprom_pwrgroup[rf_path][i] =
1770 hwinfo[EEPROM_TXPWRGROUP + rf_path * 3 + i];
1771 }
1772 }
1773
1774 for (rf_path = 0; rf_path < 2; rf_path++) {
1775 /* Fill Pwr group */
1776 for (i = 0; i < 14; i++) {
1777 /* Chanel 1-3 */
1778 if (i < 3)
1779 index = 0;
1780 /* Channel 4-8 */
1781 else if (i < 8)
1782 index = 1;
1783 /* Channel 9-13 */
1784 else
1785 index = 2;
1786
1787 rtlefuse->pwrgroup_ht20[rf_path][i] =
1788 (rtlefuse->eeprom_pwrgroup[rf_path][index] &
1789 0xf);
1790 rtlefuse->pwrgroup_ht40[rf_path][i] =
1791 ((rtlefuse->eeprom_pwrgroup[rf_path][index] &
1792 0xf0) >> 4);
1793
1794 RTPRINT(rtlpriv, FINIT, INIT_TxPower,
1795 ("RF-%d pwrgroup_ht20[%d] = 0x%x\n",
1796 rf_path, i,
1797 rtlefuse->pwrgroup_ht20[rf_path][i]));
1798 RTPRINT(rtlpriv, FINIT, INIT_TxPower,
1799 ("RF-%d pwrgroup_ht40[%d] = 0x%x\n",
1800 rf_path, i,
1801 rtlefuse->pwrgroup_ht40[rf_path][i]));
1802 }
1803 }
1804
1805 for (i = 0; i < 14; i++) {
1806 /* Read tx power difference between HT OFDM 20/40 MHZ */
1807 /* channel 1-3 */
1808 if (i < 3)
1809 index = 0;
1810 /* Channel 4-8 */
1811 else if (i < 8)
1812 index = 1;
1813 /* Channel 9-14 */
1814 else
1815 index = 2;
1816
1817 tempval = (*(u8 *)&hwinfo[EEPROM_TX_PWR_HT20_DIFF +
1818 index]) & 0xff;
1819 rtlefuse->txpwr_ht20diff[RF90_PATH_A][i] = (tempval & 0xF);
1820 rtlefuse->txpwr_ht20diff[RF90_PATH_B][i] =
1821 ((tempval >> 4) & 0xF);
1822
1823 /* Read OFDM<->HT tx power diff */
1824 /* Channel 1-3 */
1825 if (i < 3)
1826 index = 0;
1827 /* Channel 4-8 */
1828 else if (i < 8)
1829 index = 0x11;
1830 /* Channel 9-14 */
1831 else
1832 index = 1;
1833
1834 tempval = (*(u8 *)&hwinfo[EEPROM_TX_PWR_OFDM_DIFF + index])
1835 & 0xff;
1836 rtlefuse->txpwr_legacyhtdiff[RF90_PATH_A][i] =
1837 (tempval & 0xF);
1838 rtlefuse->txpwr_legacyhtdiff[RF90_PATH_B][i] =
1839 ((tempval >> 4) & 0xF);
1840
1841 tempval = (*(u8 *)&hwinfo[TX_PWR_SAFETY_CHK]);
1842 rtlefuse->txpwr_safetyflag = (tempval & 0x01);
1843 }
1844
1845 rtlefuse->eeprom_regulatory = 0;
1846 if (rtlefuse->eeprom_version >= 2) {
1847 /* BIT(0)~2 */
1848 if (rtlefuse->eeprom_version >= 4)
1849 rtlefuse->eeprom_regulatory =
1850 (hwinfo[EEPROM_REGULATORY] & 0x7);
1851 else /* BIT(0) */
1852 rtlefuse->eeprom_regulatory =
1853 (hwinfo[EEPROM_REGULATORY] & 0x1);
1854 }
1855 RTPRINT(rtlpriv, FINIT, INIT_TxPower,
1856 ("eeprom_regulatory = 0x%x\n", rtlefuse->eeprom_regulatory));
1857
1858 for (i = 0; i < 14; i++)
1859 RTPRINT(rtlpriv, FINIT, INIT_TxPower,
1860 ("RF-A Ht20 to HT40 Diff[%d] = 0x%x\n", i,
1861 rtlefuse->txpwr_ht20diff[RF90_PATH_A][i]));
1862 for (i = 0; i < 14; i++)
1863 RTPRINT(rtlpriv, FINIT, INIT_TxPower,
1864 ("RF-A Legacy to Ht40 Diff[%d] = 0x%x\n", i,
1865 rtlefuse->txpwr_legacyhtdiff[RF90_PATH_A][i]));
1866 for (i = 0; i < 14; i++)
1867 RTPRINT(rtlpriv, FINIT, INIT_TxPower,
1868 ("RF-B Ht20 to HT40 Diff[%d] = 0x%x\n", i,
1869 rtlefuse->txpwr_ht20diff[RF90_PATH_B][i]));
1870 for (i = 0; i < 14; i++)
1871 RTPRINT(rtlpriv, FINIT, INIT_TxPower,
1872 ("RF-B Legacy to HT40 Diff[%d] = 0x%x\n", i,
1873 rtlefuse->txpwr_legacyhtdiff[RF90_PATH_B][i]));
1874
1875 RTPRINT(rtlpriv, FINIT, INIT_TxPower, ("TxPwrSafetyFlag = %d\n",
1876 rtlefuse->txpwr_safetyflag));
1877
1878 /* Read RF-indication and Tx Power gain
1879 * index diff of legacy to HT OFDM rate. */
1880 tempval = (*(u8 *)&hwinfo[EEPROM_RFIND_POWERDIFF]) & 0xff;
1881 rtlefuse->eeprom_txpowerdiff = tempval;
1882 rtlefuse->legacy_httxpowerdiff =
1883 rtlefuse->txpwr_legacyhtdiff[RF90_PATH_A][0];
1884
1885 RTPRINT(rtlpriv, FINIT, INIT_TxPower, ("TxPowerDiff = %#x\n",
1886 rtlefuse->eeprom_txpowerdiff));
1887
1888 /* Get TSSI value for each path. */
1889 usvalue = *(u16 *)&hwinfo[EEPROM_TSSI_A];
1890 rtlefuse->eeprom_tssi[RF90_PATH_A] = (u8)((usvalue & 0xff00) >> 8);
1891 usvalue = *(u8 *)&hwinfo[EEPROM_TSSI_B];
1892 rtlefuse->eeprom_tssi[RF90_PATH_B] = (u8)(usvalue & 0xff);
1893
1894 RTPRINT(rtlpriv, FINIT, INIT_TxPower, ("TSSI_A = 0x%x, TSSI_B = 0x%x\n",
1895 rtlefuse->eeprom_tssi[RF90_PATH_A],
1896 rtlefuse->eeprom_tssi[RF90_PATH_B]));
1897
1898 /* Read antenna tx power offset of B/C/D to A from EEPROM */
1899 /* and read ThermalMeter from EEPROM */
1900 tempval = *(u8 *)&hwinfo[EEPROM_THERMALMETER];
1901 rtlefuse->eeprom_thermalmeter = tempval;
1902 RTPRINT(rtlpriv, FINIT, INIT_TxPower, ("thermalmeter = 0x%x\n",
1903 rtlefuse->eeprom_thermalmeter));
1904
1905 /* ThermalMeter, BIT(0)~3 for RFIC1, BIT(4)~7 for RFIC2 */
1906 rtlefuse->thermalmeter[0] = (rtlefuse->eeprom_thermalmeter & 0x1f);
1907 rtlefuse->tssi_13dbm = rtlefuse->eeprom_thermalmeter * 100;
1908
1909 /* Read CrystalCap from EEPROM */
1910 tempval = (*(u8 *)&hwinfo[EEPROM_CRYSTALCAP]) >> 4;
1911 rtlefuse->eeprom_crystalcap = tempval;
1912 /* CrystalCap, BIT(12)~15 */
1913 rtlefuse->crystalcap = rtlefuse->eeprom_crystalcap;
1914
1915 /* Read IC Version && Channel Plan */
1916 /* Version ID, Channel plan */
1917 rtlefuse->eeprom_channelplan = *(u8 *)&hwinfo[EEPROM_CHANNELPLAN];
1918 rtlefuse->txpwr_fromeprom = true;
1919 RTPRINT(rtlpriv, FINIT, INIT_TxPower, ("EEPROM ChannelPlan = 0x%4x\n",
1920 rtlefuse->eeprom_channelplan));
1921
1922 /* Read Customer ID or Board Type!!! */
1923 tempval = *(u8 *)&hwinfo[EEPROM_BOARDTYPE];
1924 /* Change RF type definition */
1925 if (tempval == 0)
1926 rtlphy->rf_type = RF_2T2R;
1927 else if (tempval == 1)
1928 rtlphy->rf_type = RF_1T2R;
1929 else if (tempval == 2)
1930 rtlphy->rf_type = RF_1T2R;
1931 else if (tempval == 3)
1932 rtlphy->rf_type = RF_1T1R;
1933
1934 /* 1T2R but 1SS (1x1 receive combining) */
1935 rtlefuse->b1x1_recvcombine = false;
1936 if (rtlphy->rf_type == RF_1T2R) {
1937 tempval = rtl_read_byte(rtlpriv, 0x07);
1938 if (!(tempval & BIT(0))) {
1939 rtlefuse->b1x1_recvcombine = true;
1940 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
1941 ("RF_TYPE=1T2R but only 1SS\n"));
1942 }
1943 }
1944 rtlefuse->b1ss_support = rtlefuse->b1x1_recvcombine;
1945 rtlefuse->eeprom_oemid = *(u8 *)&hwinfo[EEPROM_CUSTOMID];
1946
1947 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, ("EEPROM Customer ID: 0x%2x",
1948 rtlefuse->eeprom_oemid));
1949
1950 /* set channel paln to world wide 13 */
1951 rtlefuse->channel_plan = COUNTRY_CODE_WORLD_WIDE_13;
1952}
1953
1954void rtl92se_read_eeprom_info(struct ieee80211_hw *hw)
1955{
1956 struct rtl_priv *rtlpriv = rtl_priv(hw);
1957 struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
1958 u8 tmp_u1b = 0;
1959
1960 tmp_u1b = rtl_read_byte(rtlpriv, EPROM_CMD);
1961
1962 if (tmp_u1b & BIT(4)) {
1963 RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG, ("Boot from EEPROM\n"));
1964 rtlefuse->epromtype = EEPROM_93C46;
1965 } else {
1966 RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG, ("Boot from EFUSE\n"));
1967 rtlefuse->epromtype = EEPROM_BOOT_EFUSE;
1968 }
1969
1970 if (tmp_u1b & BIT(5)) {
1971 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, ("Autoload OK\n"));
1972 rtlefuse->autoload_failflag = false;
1973 _rtl92se_read_adapter_info(hw);
1974 } else {
1975 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG, ("Autoload ERR!!\n"));
1976 rtlefuse->autoload_failflag = true;
1977 }
1978}
1979
1980static void rtl92se_update_hal_rate_table(struct ieee80211_hw *hw,
1981 struct ieee80211_sta *sta)
1982{
1983 struct rtl_priv *rtlpriv = rtl_priv(hw);
1984 struct rtl_phy *rtlphy = &(rtlpriv->phy);
1985 struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
1986 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
1987 u32 ratr_value;
1988 u8 ratr_index = 0;
1989 u8 nmode = mac->ht_enable;
1990 u8 mimo_ps = IEEE80211_SMPS_OFF;
1991 u16 shortgi_rate = 0;
1992 u32 tmp_ratr_value = 0;
1993 u8 curtxbw_40mhz = mac->bw_40;
1994 u8 curshortgi_40mhz = (sta->ht_cap.cap & IEEE80211_HT_CAP_SGI_40) ?
1995 1 : 0;
1996 u8 curshortgi_20mhz = (sta->ht_cap.cap & IEEE80211_HT_CAP_SGI_20) ?
1997 1 : 0;
1998 enum wireless_mode wirelessmode = mac->mode;
1999
2000 if (rtlhal->current_bandtype == BAND_ON_5G)
2001 ratr_value = sta->supp_rates[1] << 4;
2002 else
2003 ratr_value = sta->supp_rates[0];
2004 ratr_value |= (sta->ht_cap.mcs.rx_mask[1] << 20 |
2005 sta->ht_cap.mcs.rx_mask[0] << 12);
2006 switch (wirelessmode) {
2007 case WIRELESS_MODE_B:
2008 ratr_value &= 0x0000000D;
2009 break;
2010 case WIRELESS_MODE_G:
2011 ratr_value &= 0x00000FF5;
2012 break;
2013 case WIRELESS_MODE_N_24G:
2014 case WIRELESS_MODE_N_5G:
2015 nmode = 1;
2016 if (mimo_ps == IEEE80211_SMPS_STATIC) {
2017 ratr_value &= 0x0007F005;
2018 } else {
2019 u32 ratr_mask;
2020
2021 if (get_rf_type(rtlphy) == RF_1T2R ||
2022 get_rf_type(rtlphy) == RF_1T1R) {
2023 if (curtxbw_40mhz)
2024 ratr_mask = 0x000ff015;
2025 else
2026 ratr_mask = 0x000ff005;
2027 } else {
2028 if (curtxbw_40mhz)
2029 ratr_mask = 0x0f0ff015;
2030 else
2031 ratr_mask = 0x0f0ff005;
2032 }
2033
2034 ratr_value &= ratr_mask;
2035 }
2036 break;
2037 default:
2038 if (rtlphy->rf_type == RF_1T2R)
2039 ratr_value &= 0x000ff0ff;
2040 else
2041 ratr_value &= 0x0f0ff0ff;
2042
2043 break;
2044 }
2045
2046 if (rtlpriv->rtlhal.version >= VERSION_8192S_BCUT)
2047 ratr_value &= 0x0FFFFFFF;
2048 else if (rtlpriv->rtlhal.version == VERSION_8192S_ACUT)
2049 ratr_value &= 0x0FFFFFF0;
2050
2051 if (nmode && ((curtxbw_40mhz &&
2052 curshortgi_40mhz) || (!curtxbw_40mhz &&
2053 curshortgi_20mhz))) {
2054
2055 ratr_value |= 0x10000000;
2056 tmp_ratr_value = (ratr_value >> 12);
2057
2058 for (shortgi_rate = 15; shortgi_rate > 0; shortgi_rate--) {
2059 if ((1 << shortgi_rate) & tmp_ratr_value)
2060 break;
2061 }
2062
2063 shortgi_rate = (shortgi_rate << 12) | (shortgi_rate << 8) |
2064 (shortgi_rate << 4) | (shortgi_rate);
2065
2066 rtl_write_byte(rtlpriv, SG_RATE, shortgi_rate);
2067 }
2068
2069 rtl_write_dword(rtlpriv, ARFR0 + ratr_index * 4, ratr_value);
2070 if (ratr_value & 0xfffff000)
2071 rtl92s_phy_set_fw_cmd(hw, FW_CMD_RA_REFRESH_N);
2072 else
2073 rtl92s_phy_set_fw_cmd(hw, FW_CMD_RA_REFRESH_BG);
2074
2075 RT_TRACE(rtlpriv, COMP_RATR, DBG_DMESG,
2076 ("%x\n", rtl_read_dword(rtlpriv, ARFR0)));
2077}
2078
2079static void rtl92se_update_hal_rate_mask(struct ieee80211_hw *hw,
2080 struct ieee80211_sta *sta,
2081 u8 rssi_level)
2082{
2083 struct rtl_priv *rtlpriv = rtl_priv(hw);
2084 struct rtl_phy *rtlphy = &(rtlpriv->phy);
2085 struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
2086 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
2087 struct rtl_sta_info *sta_entry = NULL;
2088 u32 ratr_bitmap;
2089 u8 ratr_index = 0;
2090 u8 curtxbw_40mhz = (sta->ht_cap.cap & IEEE80211_HT_CAP_SUP_WIDTH_20_40)
2091 ? 1 : 0;
2092 u8 curshortgi_40mhz = (sta->ht_cap.cap & IEEE80211_HT_CAP_SGI_40) ?
2093 1 : 0;
2094 u8 curshortgi_20mhz = (sta->ht_cap.cap & IEEE80211_HT_CAP_SGI_20) ?
2095 1 : 0;
2096 enum wireless_mode wirelessmode = 0;
2097 bool shortgi = false;
2098 u32 ratr_value = 0;
2099 u8 shortgi_rate = 0;
2100 u32 mask = 0;
2101 u32 band = 0;
2102 bool bmulticast = false;
2103 u8 macid = 0;
2104 u8 mimo_ps = IEEE80211_SMPS_OFF;
2105
2106 sta_entry = (struct rtl_sta_info *) sta->drv_priv;
2107 wirelessmode = sta_entry->wireless_mode;
2108 if (mac->opmode == NL80211_IFTYPE_STATION)
2109 curtxbw_40mhz = mac->bw_40;
2110 else if (mac->opmode == NL80211_IFTYPE_AP ||
2111 mac->opmode == NL80211_IFTYPE_ADHOC)
2112 macid = sta->aid + 1;
2113
2114 if (rtlhal->current_bandtype == BAND_ON_5G)
2115 ratr_bitmap = sta->supp_rates[1] << 4;
2116 else
2117 ratr_bitmap = sta->supp_rates[0];
2118 ratr_bitmap |= (sta->ht_cap.mcs.rx_mask[1] << 20 |
2119 sta->ht_cap.mcs.rx_mask[0] << 12);
2120 switch (wirelessmode) {
2121 case WIRELESS_MODE_B:
2122 band |= WIRELESS_11B;
2123 ratr_index = RATR_INX_WIRELESS_B;
2124 if (ratr_bitmap & 0x0000000c)
2125 ratr_bitmap &= 0x0000000d;
2126 else
2127 ratr_bitmap &= 0x0000000f;
2128 break;
2129 case WIRELESS_MODE_G:
2130 band |= (WIRELESS_11G | WIRELESS_11B);
2131 ratr_index = RATR_INX_WIRELESS_GB;
2132
2133 if (rssi_level == 1)
2134 ratr_bitmap &= 0x00000f00;
2135 else if (rssi_level == 2)
2136 ratr_bitmap &= 0x00000ff0;
2137 else
2138 ratr_bitmap &= 0x00000ff5;
2139 break;
2140 case WIRELESS_MODE_A:
2141 band |= WIRELESS_11A;
2142 ratr_index = RATR_INX_WIRELESS_A;
2143 ratr_bitmap &= 0x00000ff0;
2144 break;
2145 case WIRELESS_MODE_N_24G:
2146 case WIRELESS_MODE_N_5G:
2147 band |= (WIRELESS_11N | WIRELESS_11G | WIRELESS_11B);
2148 ratr_index = RATR_INX_WIRELESS_NGB;
2149
2150 if (mimo_ps == IEEE80211_SMPS_STATIC) {
2151 if (rssi_level == 1)
2152 ratr_bitmap &= 0x00070000;
2153 else if (rssi_level == 2)
2154 ratr_bitmap &= 0x0007f000;
2155 else
2156 ratr_bitmap &= 0x0007f005;
2157 } else {
2158 if (rtlphy->rf_type == RF_1T2R ||
2159 rtlphy->rf_type == RF_1T1R) {
2160 if (rssi_level == 1) {
2161 ratr_bitmap &= 0x000f0000;
2162 } else if (rssi_level == 3) {
2163 ratr_bitmap &= 0x000fc000;
2164 } else if (rssi_level == 5) {
2165 ratr_bitmap &= 0x000ff000;
2166 } else {
2167 if (curtxbw_40mhz)
2168 ratr_bitmap &= 0x000ff015;
2169 else
2170 ratr_bitmap &= 0x000ff005;
2171 }
2172 } else {
2173 if (rssi_level == 1) {
2174 ratr_bitmap &= 0x0f8f0000;
2175 } else if (rssi_level == 3) {
2176 ratr_bitmap &= 0x0f8fc000;
2177 } else if (rssi_level == 5) {
2178 ratr_bitmap &= 0x0f8ff000;
2179 } else {
2180 if (curtxbw_40mhz)
2181 ratr_bitmap &= 0x0f8ff015;
2182 else
2183 ratr_bitmap &= 0x0f8ff005;
2184 }
2185 }
2186 }
2187
2188 if ((curtxbw_40mhz && curshortgi_40mhz) ||
2189 (!curtxbw_40mhz && curshortgi_20mhz)) {
2190 if (macid == 0)
2191 shortgi = true;
2192 else if (macid == 1)
2193 shortgi = false;
2194 }
2195 break;
2196 default:
2197 band |= (WIRELESS_11N | WIRELESS_11G | WIRELESS_11B);
2198 ratr_index = RATR_INX_WIRELESS_NGB;
2199
2200 if (rtlphy->rf_type == RF_1T2R)
2201 ratr_bitmap &= 0x000ff0ff;
2202 else
2203 ratr_bitmap &= 0x0f8ff0ff;
2204 break;
2205 }
2206
2207 if (rtlpriv->rtlhal.version >= VERSION_8192S_BCUT)
2208 ratr_bitmap &= 0x0FFFFFFF;
2209 else if (rtlpriv->rtlhal.version == VERSION_8192S_ACUT)
2210 ratr_bitmap &= 0x0FFFFFF0;
2211
2212 if (shortgi) {
2213 ratr_bitmap |= 0x10000000;
2214 /* Get MAX MCS available. */
2215 ratr_value = (ratr_bitmap >> 12);
2216 for (shortgi_rate = 15; shortgi_rate > 0; shortgi_rate--) {
2217 if ((1 << shortgi_rate) & ratr_value)
2218 break;
2219 }
2220
2221 shortgi_rate = (shortgi_rate << 12) | (shortgi_rate << 8) |
2222 (shortgi_rate << 4) | (shortgi_rate);
2223 rtl_write_byte(rtlpriv, SG_RATE, shortgi_rate);
2224 }
2225
2226 mask |= (bmulticast ? 1 : 0) << 9 | (macid & 0x1f) << 4 | (band & 0xf);
2227
2228 RT_TRACE(rtlpriv, COMP_RATR, DBG_TRACE, ("mask = %x, bitmap = %x\n",
2229 mask, ratr_bitmap));
2230 rtl_write_dword(rtlpriv, 0x2c4, ratr_bitmap);
2231 rtl_write_dword(rtlpriv, WFM5, (FW_RA_UPDATE_MASK | (mask << 8)));
2232
2233 if (macid != 0)
2234 sta_entry->ratr_index = ratr_index;
2235}
2236
2237void rtl92se_update_hal_rate_tbl(struct ieee80211_hw *hw,
2238 struct ieee80211_sta *sta, u8 rssi_level)
2239{
2240 struct rtl_priv *rtlpriv = rtl_priv(hw);
2241
2242 if (rtlpriv->dm.useramask)
2243 rtl92se_update_hal_rate_mask(hw, sta, rssi_level);
2244 else
2245 rtl92se_update_hal_rate_table(hw, sta);
2246}
2247
2248void rtl92se_update_channel_access_setting(struct ieee80211_hw *hw)
2249{
2250 struct rtl_priv *rtlpriv = rtl_priv(hw);
2251 struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
2252 u16 sifs_timer;
2253
2254 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_SLOT_TIME,
2255 (u8 *)&mac->slot_time);
2256 sifs_timer = 0x0e0e;
2257 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_SIFS, (u8 *)&sifs_timer);
2258
2259}
2260
2261/* this ifunction is for RFKILL, it's different with windows,
2262 * because UI will disable wireless when GPIO Radio Off.
2263 * And here we not check or Disable/Enable ASPM like windows*/
2264bool rtl92se_gpio_radio_on_off_checking(struct ieee80211_hw *hw, u8 *valid)
2265{
2266 struct rtl_priv *rtlpriv = rtl_priv(hw);
2267 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
2268 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
78d57372 2269 enum rf_pwrstate rfpwr_toset /*, cur_rfstate */;
24284531
CL		 2270 unsigned long flag = 0;
2271 bool actuallyset = false;
2272 bool turnonbypowerdomain = false;
2273
2274 /* just 8191se can check gpio before firstup, 92c/92d have fixed it */
2275 if ((rtlpci->up_first_time == 1) || (rtlpci->being_init_adapter))
2276 return false;
2277
2278 if (ppsc->swrf_processing)
2279 return false;
2280
2281 spin_lock_irqsave(&rtlpriv->locks.rf_ps_lock, flag);
2282 if (ppsc->rfchange_inprogress) {
2283 spin_unlock_irqrestore(&rtlpriv->locks.rf_ps_lock, flag);
2284 return false;
2285 } else {
2286 ppsc->rfchange_inprogress = true;
2287 spin_unlock_irqrestore(&rtlpriv->locks.rf_ps_lock, flag);
2288 }
2289
78d57372 2290 /* cur_rfstate = ppsc->rfpwr_state;*/
24284531
CL		 2291
2292 /* because after _rtl92s_phy_set_rfhalt, all power
2293 * closed, so we must open some power for GPIO check,
2294 * or we will always check GPIO RFOFF here,
2295 * And we should close power after GPIO check */
2296 if (RT_IN_PS_LEVEL(ppsc, RT_RF_OFF_LEVL_HALT_NIC)) {
2297 _rtl92se_power_domain_init(hw);
2298 turnonbypowerdomain = true;
2299 }
2300
2301 rfpwr_toset = _rtl92se_rf_onoff_detect(hw);
2302
2303 if ((ppsc->hwradiooff == true) && (rfpwr_toset == ERFON)) {
2304 RT_TRACE(rtlpriv, COMP_RF, DBG_DMESG,
2305 ("RFKILL-HW Radio ON, RF ON\n"));
2306
2307 rfpwr_toset = ERFON;
2308 ppsc->hwradiooff = false;
2309 actuallyset = true;
2310 } else if ((ppsc->hwradiooff == false) && (rfpwr_toset == ERFOFF)) {
2311 RT_TRACE(rtlpriv, COMP_RF, DBG_DMESG,
2312 ("RFKILL-HW Radio OFF, RF OFF\n"));
2313
2314 rfpwr_toset = ERFOFF;
2315 ppsc->hwradiooff = true;
2316 actuallyset = true;
2317 }
2318
2319 if (actuallyset) {
2320 spin_lock_irqsave(&rtlpriv->locks.rf_ps_lock, flag);
2321 ppsc->rfchange_inprogress = false;
2322 spin_unlock_irqrestore(&rtlpriv->locks.rf_ps_lock, flag);
2323
2324 /* this not include ifconfig wlan0 down case */
2325 /* } else if (rfpwr_toset == ERFOFF || cur_rfstate == ERFOFF) { */
2326 } else {
2327 /* because power_domain_init may be happen when
2328 * _rtl92s_phy_set_rfhalt, this will open some powers
2329 * and cause current increasing about 40 mA for ips,
2330 * rfoff and ifconfig down, so we set
2331 * _rtl92s_phy_set_rfhalt again here */
2332 if (ppsc->reg_rfps_level & RT_RF_OFF_LEVL_HALT_NIC &&
2333 turnonbypowerdomain) {
2334 _rtl92s_phy_set_rfhalt(hw);
2335 RT_SET_PS_LEVEL(ppsc, RT_RF_OFF_LEVL_HALT_NIC);
2336 }
2337
2338 spin_lock_irqsave(&rtlpriv->locks.rf_ps_lock, flag);
2339 ppsc->rfchange_inprogress = false;
2340 spin_unlock_irqrestore(&rtlpriv->locks.rf_ps_lock, flag);
2341 }
2342
2343 *valid = 1;
2344 return !ppsc->hwradiooff;
2345
2346}
2347
2348/* Is_wepkey just used for WEP used as group & pairwise key
2349 * if pairwise is AES ang group is WEP Is_wepkey == false.*/
2350void rtl92se_set_key(struct ieee80211_hw *hw, u32 key_index, u8 *p_macaddr,
2351 bool is_group, u8 enc_algo, bool is_wepkey, bool clear_all)
2352{
2353 struct rtl_priv *rtlpriv = rtl_priv(hw);
2354 struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
2355 struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
2356 u8 *macaddr = p_macaddr;
2357
2358 u32 entry_id = 0;
2359 bool is_pairwise = false;
2360
2361 static u8 cam_const_addr[4][6] = {
2362 {0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
2363 {0x00, 0x00, 0x00, 0x00, 0x00, 0x01},
2364 {0x00, 0x00, 0x00, 0x00, 0x00, 0x02},
2365 {0x00, 0x00, 0x00, 0x00, 0x00, 0x03}
2366 };
2367 static u8 cam_const_broad[] = {
2368 0xff, 0xff, 0xff, 0xff, 0xff, 0xff
2369 };
2370
2371 if (clear_all) {
2372 u8 idx = 0;
2373 u8 cam_offset = 0;
2374 u8 clear_number = 5;
2375
2376 RT_TRACE(rtlpriv, COMP_SEC, DBG_DMESG, ("clear_all\n"));
2377
2378 for (idx = 0; idx < clear_number; idx++) {
2379 rtl_cam_mark_invalid(hw, cam_offset + idx);
2380 rtl_cam_empty_entry(hw, cam_offset + idx);
2381
2382 if (idx < 5) {
2383 memset(rtlpriv->sec.key_buf[idx], 0,
2384 MAX_KEY_LEN);
2385 rtlpriv->sec.key_len[idx] = 0;
2386 }
2387 }
2388
2389 } else {
2390 switch (enc_algo) {
2391 case WEP40_ENCRYPTION:
2392 enc_algo = CAM_WEP40;
2393 break;
2394 case WEP104_ENCRYPTION:
2395 enc_algo = CAM_WEP104;
2396 break;
2397 case TKIP_ENCRYPTION:
2398 enc_algo = CAM_TKIP;
2399 break;
2400 case AESCCMP_ENCRYPTION:
2401 enc_algo = CAM_AES;
2402 break;
2403 default:
2404 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
2405 ("switch case not process\n"));
2406 enc_algo = CAM_TKIP;
2407 break;
2408 }
2409
2410 if (is_wepkey || rtlpriv->sec.use_defaultkey) {
2411 macaddr = cam_const_addr[key_index];
2412 entry_id = key_index;
2413 } else {
2414 if (is_group) {
2415 macaddr = cam_const_broad;
2416 entry_id = key_index;
2417 } else {
2418 if (mac->opmode == NL80211_IFTYPE_AP) {
2419 entry_id = rtl_cam_get_free_entry(hw,
2420 p_macaddr);
2421 if (entry_id >= TOTAL_CAM_ENTRY) {
2422 RT_TRACE(rtlpriv,
2423 COMP_SEC, DBG_EMERG,
2424 ("Can not find free hw"
2425 " security cam entry\n"));
2426 return;
2427 }
2428 } else {
2429 entry_id = CAM_PAIRWISE_KEY_POSITION;
2430 }
2431
2432 key_index = PAIRWISE_KEYIDX;
2433 is_pairwise = true;
2434 }
2435 }
2436
2437 if (rtlpriv->sec.key_len[key_index] == 0) {
2438 RT_TRACE(rtlpriv, COMP_SEC, DBG_DMESG,
2439 ("delete one entry, entry_id is %d\n",
2440 entry_id));
2441 if (mac->opmode == NL80211_IFTYPE_AP)
2442 rtl_cam_del_entry(hw, p_macaddr);
2443 rtl_cam_delete_one_entry(hw, p_macaddr, entry_id);
2444 } else {
2445 RT_TRACE(rtlpriv, COMP_SEC, DBG_LOUD,
2446 ("The insert KEY length is %d\n",
2447 rtlpriv->sec.key_len[PAIRWISE_KEYIDX]));
2448 RT_TRACE(rtlpriv, COMP_SEC, DBG_LOUD,
2449 ("The insert KEY is %x %x\n",
2450 rtlpriv->sec.key_buf[0][0],
2451 rtlpriv->sec.key_buf[0][1]));
2452
2453 RT_TRACE(rtlpriv, COMP_SEC, DBG_DMESG,
2454 ("add one entry\n"));
2455 if (is_pairwise) {
2456 RT_PRINT_DATA(rtlpriv, COMP_SEC, DBG_LOUD,
2457 "Pairwiase Key content :",
2458 rtlpriv->sec.pairwise_key,
2459 rtlpriv->sec.key_len[PAIRWISE_KEYIDX]);
2460
2461 RT_TRACE(rtlpriv, COMP_SEC, DBG_DMESG,
2462 ("set Pairwiase key\n"));
2463
2464 rtl_cam_add_one_entry(hw, macaddr, key_index,
2465 entry_id, enc_algo,
2466 CAM_CONFIG_NO_USEDK,
2467 rtlpriv->sec.key_buf[key_index]);
2468 } else {
2469 RT_TRACE(rtlpriv, COMP_SEC, DBG_DMESG,
2470 ("set group key\n"));
2471
2472 if (mac->opmode == NL80211_IFTYPE_ADHOC) {
2473 rtl_cam_add_one_entry(hw,
2474 rtlefuse->dev_addr,
2475 PAIRWISE_KEYIDX,
2476 CAM_PAIRWISE_KEY_POSITION,
2477 enc_algo, CAM_CONFIG_NO_USEDK,
2478 rtlpriv->sec.key_buf[entry_id]);
2479 }
2480
2481 rtl_cam_add_one_entry(hw, macaddr, key_index,
2482 entry_id, enc_algo,
2483 CAM_CONFIG_NO_USEDK,
2484 rtlpriv->sec.key_buf[entry_id]);
2485 }
2486
2487 }
2488 }
2489}
2490
2491void rtl92se_suspend(struct ieee80211_hw *hw)
2492{
2493 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
2494
2495 rtlpci->up_first_time = true;
2496}
2497
2498void rtl92se_resume(struct ieee80211_hw *hw)
2499{
2500 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
2501 u32 val;
2502
2503 pci_read_config_dword(rtlpci->pdev, 0x40, &val);
2504 if ((val & 0x0000ff00) != 0)
2505 pci_write_config_dword(rtlpci->pdev, 0x40,
2506 val & 0xffff00ff);
2507}
Linux kernel - Deliverables
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