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rtlwifi: avoid accessing RCR directly
[deliverable/linux.git] / drivers / net / wireless / rtlwifi / rtl8192se / hw.c
CommitLineData
24284531
CL		 1/******************************************************************************
2 *
ca742cd9 3 * Copyright(c) 2009-2012 Realtek Corporation.
24284531
CL		 4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of version 2 of the GNU General Public License as
7 * published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details.
13 *
14 * You should have received a copy of the GNU General Public License along with
15 * this program; if not, write to the Free Software Foundation, Inc.,
16 * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
17 *
18 * The full GNU General Public License is included in this distribution in the
19 * file called LICENSE.
20 *
21 * Contact Information:
22 * wlanfae <wlanfae@realtek.com>
23 * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
24 * Hsinchu 300, Taiwan.
25 *
26 * Larry Finger <Larry.Finger@lwfinger.net>
27 *
28 *****************************************************************************/
29
30#include "../wifi.h"
31#include "../efuse.h"
32#include "../base.h"
33#include "../regd.h"
34#include "../cam.h"
35#include "../ps.h"
36#include "../pci.h"
37#include "reg.h"
38#include "def.h"
39#include "phy.h"
40#include "dm.h"
41#include "fw.h"
42#include "led.h"
43#include "hw.h"
44
45void rtl92se_get_hw_reg(struct ieee80211_hw *hw, u8 variable, u8 *val)
46{
47 struct rtl_priv *rtlpriv = rtl_priv(hw);
48 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
49 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
50
51 switch (variable) {
52 case HW_VAR_RCR: {
53 *((u32 *) (val)) = rtlpci->receive_config;
54 break;
55 }
56 case HW_VAR_RF_STATE: {
57 *((enum rf_pwrstate *)(val)) = ppsc->rfpwr_state;
58 break;
59 }
60 case HW_VAR_FW_PSMODE_STATUS: {
61 *((bool *) (val)) = ppsc->fw_current_inpsmode;
62 break;
63 }
64 case HW_VAR_CORRECT_TSF: {
65 u64 tsf;
66 u32 *ptsf_low = (u32 *)&tsf;
67 u32 *ptsf_high = ((u32 *)&tsf) + 1;
68
69 *ptsf_high = rtl_read_dword(rtlpriv, (TSFR + 4));
70 *ptsf_low = rtl_read_dword(rtlpriv, TSFR);
71
72 *((u64 *) (val)) = tsf;
73
74 break;
75 }
76 case HW_VAR_MRC: {
77 *((bool *)(val)) = rtlpriv->dm.current_mrc_switch;
78 break;
79 }
80 default: {
f30d7507
JP		 81 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
82 "switch case not processed\n");
24284531
CL		 83 break;
84 }
85 }
86}
87
88void rtl92se_set_hw_reg(struct ieee80211_hw *hw, u8 variable, u8 *val)
89{
90 struct rtl_priv *rtlpriv = rtl_priv(hw);
91 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
92 struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
93 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
94 struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
95 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
96
97 switch (variable) {
98 case HW_VAR_ETHER_ADDR:{
99 rtl_write_dword(rtlpriv, IDR0, ((u32 *)(val))[0]);
100 rtl_write_word(rtlpriv, IDR4, ((u16 *)(val + 4))[0]);
101 break;
102 }
103 case HW_VAR_BASIC_RATE:{
104 u16 rate_cfg = ((u16 *) val)[0];
105 u8 rate_index = 0;
106
107 if (rtlhal->version == VERSION_8192S_ACUT)
108 rate_cfg = rate_cfg & 0x150;
109 else
110 rate_cfg = rate_cfg & 0x15f;
111
112 rate_cfg |= 0x01;
113
114 rtl_write_byte(rtlpriv, RRSR, rate_cfg & 0xff);
115 rtl_write_byte(rtlpriv, RRSR + 1,
116 (rate_cfg >> 8) & 0xff);
117
118 while (rate_cfg > 0x1) {
119 rate_cfg = (rate_cfg >> 1);
120 rate_index++;
121 }
122 rtl_write_byte(rtlpriv, INIRTSMCS_SEL, rate_index);
123
124 break;
125 }
126 case HW_VAR_BSSID:{
127 rtl_write_dword(rtlpriv, BSSIDR, ((u32 *)(val))[0]);
128 rtl_write_word(rtlpriv, BSSIDR + 4,
129 ((u16 *)(val + 4))[0]);
130 break;
131 }
132 case HW_VAR_SIFS:{
133 rtl_write_byte(rtlpriv, SIFS_OFDM, val[0]);
134 rtl_write_byte(rtlpriv, SIFS_OFDM + 1, val[1]);
135 break;
136 }
137 case HW_VAR_SLOT_TIME:{
138 u8 e_aci;
139
140 RT_TRACE(rtlpriv, COMP_MLME, DBG_LOUD,
f30d7507 141 "HW_VAR_SLOT_TIME %x\n", val[0]);
24284531
CL		 142
143 rtl_write_byte(rtlpriv, SLOT_TIME, val[0]);
144
145 for (e_aci = 0; e_aci < AC_MAX; e_aci++) {
146 rtlpriv->cfg->ops->set_hw_reg(hw,
147 HW_VAR_AC_PARAM,
2c208890 148 (&e_aci));
24284531
CL		 149 }
150 break;
151 }
152 case HW_VAR_ACK_PREAMBLE:{
153 u8 reg_tmp;
2c208890 154 u8 short_preamble = (bool) (*val);
24284531
CL		 155 reg_tmp = (mac->cur_40_prime_sc) << 5;
156 if (short_preamble)
157 reg_tmp |= 0x80;
158
159 rtl_write_byte(rtlpriv, RRSR + 2, reg_tmp);
160 break;
161 }
162 case HW_VAR_AMPDU_MIN_SPACE:{
163 u8 min_spacing_to_set;
164 u8 sec_min_space;
165
2c208890 166 min_spacing_to_set = *val;
24284531
CL		 167 if (min_spacing_to_set <= 7) {
168 if (rtlpriv->sec.pairwise_enc_algorithm ==
169 NO_ENCRYPTION)
170 sec_min_space = 0;
171 else
172 sec_min_space = 1;
173
174 if (min_spacing_to_set < sec_min_space)
175 min_spacing_to_set = sec_min_space;
176 if (min_spacing_to_set > 5)
177 min_spacing_to_set = 5;
178
179 mac->min_space_cfg =
180 ((mac->min_space_cfg & 0xf8) |
181 min_spacing_to_set);
182
183 *val = min_spacing_to_set;
184
185 RT_TRACE(rtlpriv, COMP_MLME, DBG_LOUD,
f30d7507
JP		 186 "Set HW_VAR_AMPDU_MIN_SPACE: %#x\n",
187 mac->min_space_cfg);
24284531
CL		 188
189 rtl_write_byte(rtlpriv, AMPDU_MIN_SPACE,
190 mac->min_space_cfg);
191 }
192 break;
193 }
194 case HW_VAR_SHORTGI_DENSITY:{
195 u8 density_to_set;
196
2c208890 197 density_to_set = *val;
24284531
CL		 198 mac->min_space_cfg = rtlpriv->rtlhal.minspace_cfg;
199 mac->min_space_cfg |= (density_to_set << 3);
200
201 RT_TRACE(rtlpriv, COMP_MLME, DBG_LOUD,
f30d7507
JP		 202 "Set HW_VAR_SHORTGI_DENSITY: %#x\n",
203 mac->min_space_cfg);
24284531
CL		 204
205 rtl_write_byte(rtlpriv, AMPDU_MIN_SPACE,
206 mac->min_space_cfg);
207
208 break;
209 }
210 case HW_VAR_AMPDU_FACTOR:{
211 u8 factor_toset;
212 u8 regtoset;
213 u8 factorlevel[18] = {
214 2, 4, 4, 7, 7, 13, 13,
215 13, 2, 7, 7, 13, 13,
216 15, 15, 15, 15, 0};
217 u8 index = 0;
218
2c208890 219 factor_toset = *val;
24284531
CL		 220 if (factor_toset <= 3) {
221 factor_toset = (1 << (factor_toset + 2));
222 if (factor_toset > 0xf)
223 factor_toset = 0xf;
224
225 for (index = 0; index < 17; index++) {
226 if (factorlevel[index] > factor_toset)
227 factorlevel[index] =
228 factor_toset;
229 }
230
231 for (index = 0; index < 8; index++) {
232 regtoset = ((factorlevel[index * 2]) |
233 (factorlevel[index *
234 2 + 1] << 4));
235 rtl_write_byte(rtlpriv,
236 AGGLEN_LMT_L + index,
237 regtoset);
238 }
239
240 regtoset = ((factorlevel[16]) |
241 (factorlevel[17] << 4));
242 rtl_write_byte(rtlpriv, AGGLEN_LMT_H, regtoset);
243
244 RT_TRACE(rtlpriv, COMP_MLME, DBG_LOUD,
f30d7507
JP		 245 "Set HW_VAR_AMPDU_FACTOR: %#x\n",
246 factor_toset);
24284531
CL		 247 }
248 break;
249 }
250 case HW_VAR_AC_PARAM:{
2c208890 251 u8 e_aci = *val;
24284531
CL		 252 rtl92s_dm_init_edca_turbo(hw);
253
254 if (rtlpci->acm_method != eAcmWay2_SW)
255 rtlpriv->cfg->ops->set_hw_reg(hw,
256 HW_VAR_ACM_CTRL,
2c208890 257 &e_aci);
24284531
CL		 258 break;
259 }
260 case HW_VAR_ACM_CTRL:{
2c208890 261 u8 e_aci = *val;
24284531
CL		 262 union aci_aifsn *p_aci_aifsn = (union aci_aifsn *)(&(
263 mac->ac[0].aifs));
264 u8 acm = p_aci_aifsn->f.acm;
265 u8 acm_ctrl = rtl_read_byte(rtlpriv, AcmHwCtrl);
266
267 acm_ctrl = acm_ctrl | ((rtlpci->acm_method == 2) ?
268 0x0 : 0x1);
269
270 if (acm) {
271 switch (e_aci) {
272 case AC0_BE:
273 acm_ctrl |= AcmHw_BeqEn;
274 break;
275 case AC2_VI:
276 acm_ctrl |= AcmHw_ViqEn;
277 break;
278 case AC3_VO:
279 acm_ctrl |= AcmHw_VoqEn;
280 break;
281 default:
282 RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING,
f30d7507
JP		 283 "HW_VAR_ACM_CTRL acm set failed: eACI is %d\n",
284 acm);
24284531
CL		 285 break;
286 }
287 } else {
288 switch (e_aci) {
289 case AC0_BE:
290 acm_ctrl &= (~AcmHw_BeqEn);
291 break;
292 case AC2_VI:
293 acm_ctrl &= (~AcmHw_ViqEn);
294 break;
295 case AC3_VO:
296 acm_ctrl &= (~AcmHw_BeqEn);
297 break;
298 default:
299 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
f30d7507 300 "switch case not processed\n");
24284531
CL		 301 break;
302 }
303 }
304
305 RT_TRACE(rtlpriv, COMP_QOS, DBG_TRACE,
f30d7507 306 "HW_VAR_ACM_CTRL Write 0x%X\n", acm_ctrl);
24284531
CL		 307 rtl_write_byte(rtlpriv, AcmHwCtrl, acm_ctrl);
308 break;
309 }
310 case HW_VAR_RCR:{
311 rtl_write_dword(rtlpriv, RCR, ((u32 *) (val))[0]);
312 rtlpci->receive_config = ((u32 *) (val))[0];
313 break;
314 }
315 case HW_VAR_RETRY_LIMIT:{
2c208890 316 u8 retry_limit = val[0];
24284531
CL		 317
318 rtl_write_word(rtlpriv, RETRY_LIMIT,
319 retry_limit << RETRY_LIMIT_SHORT_SHIFT |
320 retry_limit << RETRY_LIMIT_LONG_SHIFT);
321 break;
322 }
323 case HW_VAR_DUAL_TSF_RST: {
324 break;
325 }
326 case HW_VAR_EFUSE_BYTES: {
327 rtlefuse->efuse_usedbytes = *((u16 *) val);
328 break;
329 }
330 case HW_VAR_EFUSE_USAGE: {
2c208890 331 rtlefuse->efuse_usedpercentage = *val;
24284531
CL		 332 break;
333 }
334 case HW_VAR_IO_CMD: {
335 break;
336 }
337 case HW_VAR_WPA_CONFIG: {
2c208890 338 rtl_write_byte(rtlpriv, REG_SECR, *val);
24284531
CL		 339 break;
340 }
341 case HW_VAR_SET_RPWM:{
342 break;
343 }
344 case HW_VAR_H2C_FW_PWRMODE:{
345 break;
346 }
347 case HW_VAR_FW_PSMODE_STATUS: {
348 ppsc->fw_current_inpsmode = *((bool *) val);
349 break;
350 }
351 case HW_VAR_H2C_FW_JOINBSSRPT:{
352 break;
353 }
354 case HW_VAR_AID:{
355 break;
356 }
357 case HW_VAR_CORRECT_TSF:{
358 break;
359 }
360 case HW_VAR_MRC: {
361 bool bmrc_toset = *((bool *)val);
362 u8 u1bdata = 0;
363
364 if (bmrc_toset) {
365 rtl_set_bbreg(hw, ROFDM0_TRXPATHENABLE,
366 MASKBYTE0, 0x33);
367 u1bdata = (u8)rtl_get_bbreg(hw,
368 ROFDM1_TRXPATHENABLE,
369 MASKBYTE0);
370 rtl_set_bbreg(hw, ROFDM1_TRXPATHENABLE,
371 MASKBYTE0,
372 ((u1bdata & 0xf0) | 0x03));
373 u1bdata = (u8)rtl_get_bbreg(hw,
374 ROFDM0_TRXPATHENABLE,
375 MASKBYTE1);
376 rtl_set_bbreg(hw, ROFDM0_TRXPATHENABLE,
377 MASKBYTE1,
378 (u1bdata | 0x04));
379
380 /* Update current settings. */
381 rtlpriv->dm.current_mrc_switch = bmrc_toset;
382 } else {
383 rtl_set_bbreg(hw, ROFDM0_TRXPATHENABLE,
384 MASKBYTE0, 0x13);
385 u1bdata = (u8)rtl_get_bbreg(hw,
386 ROFDM1_TRXPATHENABLE,
387 MASKBYTE0);
388 rtl_set_bbreg(hw, ROFDM1_TRXPATHENABLE,
389 MASKBYTE0,
390 ((u1bdata & 0xf0) | 0x01));
391 u1bdata = (u8)rtl_get_bbreg(hw,
392 ROFDM0_TRXPATHENABLE,
393 MASKBYTE1);
394 rtl_set_bbreg(hw, ROFDM0_TRXPATHENABLE,
395 MASKBYTE1, (u1bdata & 0xfb));
396
397 /* Update current settings. */
398 rtlpriv->dm.current_mrc_switch = bmrc_toset;
399 }
400
401 break;
402 }
2455c92c
LF		 403 case HW_VAR_FW_LPS_ACTION: {
404 bool enter_fwlps = *((bool *)val);
405 u8 rpwm_val, fw_pwrmode;
406 bool fw_current_inps;
407
408 if (enter_fwlps) {
409 rpwm_val = 0x02; /* RF off */
410 fw_current_inps = true;
411 rtlpriv->cfg->ops->set_hw_reg(hw,
412 HW_VAR_FW_PSMODE_STATUS,
413 (u8 *)(&fw_current_inps));
414 rtlpriv->cfg->ops->set_hw_reg(hw,
415 HW_VAR_H2C_FW_PWRMODE,
416 (u8 *)(&ppsc->fwctrl_psmode));
417
418 rtlpriv->cfg->ops->set_hw_reg(hw,
419 HW_VAR_SET_RPWM,
420 (u8 *)(&rpwm_val));
421 } else {
422 rpwm_val = 0x0C; /* RF on */
423 fw_pwrmode = FW_PS_ACTIVE_MODE;
424 fw_current_inps = false;
425 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_SET_RPWM,
426 (u8 *)(&rpwm_val));
427 rtlpriv->cfg->ops->set_hw_reg(hw,
428 HW_VAR_H2C_FW_PWRMODE,
429 (u8 *)(&fw_pwrmode));
430
431 rtlpriv->cfg->ops->set_hw_reg(hw,
432 HW_VAR_FW_PSMODE_STATUS,
433 (u8 *)(&fw_current_inps));
434 }
435 break; }
24284531
CL		 436 default:
437 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
f30d7507 438 "switch case not processed\n");
24284531
CL		 439 break;
440 }
441
442}
443
444void rtl92se_enable_hw_security_config(struct ieee80211_hw *hw)
445{
446 struct rtl_priv *rtlpriv = rtl_priv(hw);
447 u8 sec_reg_value = 0x0;
448
f30d7507
JP		 449 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
450 "PairwiseEncAlgorithm = %d GroupEncAlgorithm = %d\n",
24284531 451 rtlpriv->sec.pairwise_enc_algorithm,
f30d7507 452 rtlpriv->sec.group_enc_algorithm);
24284531
CL		 453
454 if (rtlpriv->cfg->mod_params->sw_crypto || rtlpriv->sec.use_sw_sec) {
455 RT_TRACE(rtlpriv, COMP_SEC, DBG_DMESG,
f30d7507 456 "not open hw encryption\n");
24284531
CL		 457 return;
458 }
459
460 sec_reg_value = SCR_TXENCENABLE | SCR_RXENCENABLE;
461
462 if (rtlpriv->sec.use_defaultkey) {
463 sec_reg_value |= SCR_TXUSEDK;
464 sec_reg_value |= SCR_RXUSEDK;
465 }
466
f30d7507
JP		 467 RT_TRACE(rtlpriv, COMP_SEC, DBG_LOUD, "The SECR-value %x\n",
468 sec_reg_value);
24284531
CL		 469
470 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_WPA_CONFIG, &sec_reg_value);
471
472}
473
2455c92c 474static u8 _rtl92se_halset_sysclk(struct ieee80211_hw *hw, u8 data)
24284531
CL		 475{
476 struct rtl_priv *rtlpriv = rtl_priv(hw);
477 u8 waitcount = 100;
478 bool bresult = false;
479 u8 tmpvalue;
480
481 rtl_write_byte(rtlpriv, SYS_CLKR + 1, data);
482
483 /* Wait the MAC synchronized. */
484 udelay(400);
485
486 /* Check if it is set ready. */
487 tmpvalue = rtl_read_byte(rtlpriv, SYS_CLKR + 1);
488 bresult = ((tmpvalue & BIT(7)) == (data & BIT(7)));
489
490 if ((data & (BIT(6) | BIT(7))) == false) {
491 waitcount = 100;
492 tmpvalue = 0;
493
494 while (1) {
495 waitcount--;
496
497 tmpvalue = rtl_read_byte(rtlpriv, SYS_CLKR + 1);
498 if ((tmpvalue & BIT(6)))
499 break;
500
292b1192 501 pr_err("wait for BIT(6) return value %x\n", tmpvalue);
24284531
CL		 502 if (waitcount == 0)
503 break;
504
505 udelay(10);
506 }
507
508 if (waitcount == 0)
509 bresult = false;
510 else
511 bresult = true;
512 }
513
514 return bresult;
515}
516
517void rtl8192se_gpiobit3_cfg_inputmode(struct ieee80211_hw *hw)
518{
519 struct rtl_priv *rtlpriv = rtl_priv(hw);
520 u8 u1tmp;
521
522 /* The following config GPIO function */
523 rtl_write_byte(rtlpriv, MAC_PINMUX_CFG, (GPIOMUX_EN | GPIOSEL_GPIO));
524 u1tmp = rtl_read_byte(rtlpriv, GPIO_IO_SEL);
525
526 /* config GPIO3 to input */
527 u1tmp &= HAL_8192S_HW_GPIO_OFF_MASK;
528 rtl_write_byte(rtlpriv, GPIO_IO_SEL, u1tmp);
529
530}
531
532static u8 _rtl92se_rf_onoff_detect(struct ieee80211_hw *hw)
533{
534 struct rtl_priv *rtlpriv = rtl_priv(hw);
535 u8 u1tmp;
536 u8 retval = ERFON;
537
538 /* The following config GPIO function */
539 rtl_write_byte(rtlpriv, MAC_PINMUX_CFG, (GPIOMUX_EN | GPIOSEL_GPIO));
540 u1tmp = rtl_read_byte(rtlpriv, GPIO_IO_SEL);
541
542 /* config GPIO3 to input */
543 u1tmp &= HAL_8192S_HW_GPIO_OFF_MASK;
544 rtl_write_byte(rtlpriv, GPIO_IO_SEL, u1tmp);
545
546 /* On some of the platform, driver cannot read correct
547 * value without delay between Write_GPIO_SEL and Read_GPIO_IN */
548 mdelay(10);
549
550 /* check GPIO3 */
7101f404 551 u1tmp = rtl_read_byte(rtlpriv, GPIO_IN_SE);
24284531
CL		 552 retval = (u1tmp & HAL_8192S_HW_GPIO_OFF_BIT) ? ERFON : ERFOFF;
553
554 return retval;
555}
556
557static void _rtl92se_macconfig_before_fwdownload(struct ieee80211_hw *hw)
558{
559 struct rtl_priv *rtlpriv = rtl_priv(hw);
560 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
561 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
562
563 u8 i;
564 u8 tmpu1b;
565 u16 tmpu2b;
566 u8 pollingcnt = 20;
567
568 if (rtlpci->first_init) {
569 /* Reset PCIE Digital */
570 tmpu1b = rtl_read_byte(rtlpriv, REG_SYS_FUNC_EN + 1);
571 tmpu1b &= 0xFE;
572 rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN + 1, tmpu1b);
573 udelay(1);
574 rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN + 1, tmpu1b | BIT(0));
575 }
576
577 /* Switch to SW IO control */
578 tmpu1b = rtl_read_byte(rtlpriv, (SYS_CLKR + 1));
579 if (tmpu1b & BIT(7)) {
580 tmpu1b &= ~(BIT(6) | BIT(7));
581
582 /* Set failed, return to prevent hang. */
2455c92c 583 if (!_rtl92se_halset_sysclk(hw, tmpu1b))
24284531
CL		 584 return;
585 }
586
587 rtl_write_byte(rtlpriv, AFE_PLL_CTRL, 0x0);
588 udelay(50);
589 rtl_write_byte(rtlpriv, LDOA15_CTRL, 0x34);
590 udelay(50);
591
592 /* Clear FW RPWM for FW control LPS.*/
593 rtl_write_byte(rtlpriv, RPWM, 0x0);
594
595 /* Reset MAC-IO and CPU and Core Digital BIT(10)/11/15 */
596 tmpu1b = rtl_read_byte(rtlpriv, REG_SYS_FUNC_EN + 1);
597 tmpu1b &= 0x73;
598 rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN + 1, tmpu1b);
599 /* wait for BIT 10/11/15 to pull high automatically!! */
600 mdelay(1);
601
602 rtl_write_byte(rtlpriv, CMDR, 0);
603 rtl_write_byte(rtlpriv, TCR, 0);
604
605 /* Data sheet not define 0x562!!! Copy from WMAC!!!!! */
606 tmpu1b = rtl_read_byte(rtlpriv, 0x562);
607 tmpu1b |= 0x08;
608 rtl_write_byte(rtlpriv, 0x562, tmpu1b);
609 tmpu1b &= ~(BIT(3));
610 rtl_write_byte(rtlpriv, 0x562, tmpu1b);
611
612 /* Enable AFE clock source */
613 tmpu1b = rtl_read_byte(rtlpriv, AFE_XTAL_CTRL);
614 rtl_write_byte(rtlpriv, AFE_XTAL_CTRL, (tmpu1b | 0x01));
615 /* Delay 1.5ms */
616 mdelay(2);
617 tmpu1b = rtl_read_byte(rtlpriv, AFE_XTAL_CTRL + 1);
618 rtl_write_byte(rtlpriv, AFE_XTAL_CTRL + 1, (tmpu1b & 0xfb));
619
620 /* Enable AFE Macro Block's Bandgap */
621 tmpu1b = rtl_read_byte(rtlpriv, AFE_MISC);
622 rtl_write_byte(rtlpriv, AFE_MISC, (tmpu1b | BIT(0)));
623 mdelay(1);
624
625 /* Enable AFE Mbias */
626 tmpu1b = rtl_read_byte(rtlpriv, AFE_MISC);
627 rtl_write_byte(rtlpriv, AFE_MISC, (tmpu1b | 0x02));
628 mdelay(1);
629
630 /* Enable LDOA15 block */
631 tmpu1b = rtl_read_byte(rtlpriv, LDOA15_CTRL);
632 rtl_write_byte(rtlpriv, LDOA15_CTRL, (tmpu1b | BIT(0)));
633
634 /* Set Digital Vdd to Retention isolation Path. */
635 tmpu2b = rtl_read_word(rtlpriv, REG_SYS_ISO_CTRL);
636 rtl_write_word(rtlpriv, REG_SYS_ISO_CTRL, (tmpu2b | BIT(11)));
637
638 /* For warm reboot NIC disappera bug. */
639 tmpu2b = rtl_read_word(rtlpriv, REG_SYS_FUNC_EN);
640 rtl_write_word(rtlpriv, REG_SYS_FUNC_EN, (tmpu2b | BIT(13)));
641
642 rtl_write_byte(rtlpriv, REG_SYS_ISO_CTRL + 1, 0x68);
643
644 /* Enable AFE PLL Macro Block */
645 /* We need to delay 100u before enabling PLL. */
646 udelay(200);
647 tmpu1b = rtl_read_byte(rtlpriv, AFE_PLL_CTRL);
648 rtl_write_byte(rtlpriv, AFE_PLL_CTRL, (tmpu1b | BIT(0) | BIT(4)));
649
650 /* for divider reset */
651 udelay(100);
652 rtl_write_byte(rtlpriv, AFE_PLL_CTRL, (tmpu1b | BIT(0) |
653 BIT(4) | BIT(6)));
654 udelay(10);
655 rtl_write_byte(rtlpriv, AFE_PLL_CTRL, (tmpu1b | BIT(0) | BIT(4)));
656 udelay(10);
657
658 /* Enable MAC 80MHZ clock */
659 tmpu1b = rtl_read_byte(rtlpriv, AFE_PLL_CTRL + 1);
660 rtl_write_byte(rtlpriv, AFE_PLL_CTRL + 1, (tmpu1b | BIT(0)));
661 mdelay(1);
662
663 /* Release isolation AFE PLL & MD */
664 rtl_write_byte(rtlpriv, REG_SYS_ISO_CTRL, 0xA6);
665
666 /* Enable MAC clock */
667 tmpu2b = rtl_read_word(rtlpriv, SYS_CLKR);
668 rtl_write_word(rtlpriv, SYS_CLKR, (tmpu2b | BIT(12) | BIT(11)));
669
670 /* Enable Core digital and enable IOREG R/W */
671 tmpu2b = rtl_read_word(rtlpriv, REG_SYS_FUNC_EN);
672 rtl_write_word(rtlpriv, REG_SYS_FUNC_EN, (tmpu2b | BIT(11)));
673
674 tmpu1b = rtl_read_byte(rtlpriv, REG_SYS_FUNC_EN + 1);
675 rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN + 1, tmpu1b & ~(BIT(7)));
676
677 /* enable REG_EN */
678 rtl_write_word(rtlpriv, REG_SYS_FUNC_EN, (tmpu2b | BIT(11) | BIT(15)));
679
680 /* Switch the control path. */
681 tmpu2b = rtl_read_word(rtlpriv, SYS_CLKR);
682 rtl_write_word(rtlpriv, SYS_CLKR, (tmpu2b & (~BIT(2))));
683
684 tmpu1b = rtl_read_byte(rtlpriv, (SYS_CLKR + 1));
685 tmpu1b = ((tmpu1b | BIT(7)) & (~BIT(6)));
2455c92c 686 if (!_rtl92se_halset_sysclk(hw, tmpu1b))
24284531
CL		 687 return; /* Set failed, return to prevent hang. */
688
689 rtl_write_word(rtlpriv, CMDR, 0x07FC);
690
691 /* MH We must enable the section of code to prevent load IMEM fail. */
692 /* Load MAC register from WMAc temporarily We simulate macreg. */
693 /* txt HW will provide MAC txt later */
694 rtl_write_byte(rtlpriv, 0x6, 0x30);
695 rtl_write_byte(rtlpriv, 0x49, 0xf0);
696
697 rtl_write_byte(rtlpriv, 0x4b, 0x81);
698
699 rtl_write_byte(rtlpriv, 0xb5, 0x21);
700
701 rtl_write_byte(rtlpriv, 0xdc, 0xff);
702 rtl_write_byte(rtlpriv, 0xdd, 0xff);
703 rtl_write_byte(rtlpriv, 0xde, 0xff);
704 rtl_write_byte(rtlpriv, 0xdf, 0xff);
705
706 rtl_write_byte(rtlpriv, 0x11a, 0x00);
707 rtl_write_byte(rtlpriv, 0x11b, 0x00);
708
709 for (i = 0; i < 32; i++)
710 rtl_write_byte(rtlpriv, INIMCS_SEL + i, 0x1b);
711
712 rtl_write_byte(rtlpriv, 0x236, 0xff);
713
714 rtl_write_byte(rtlpriv, 0x503, 0x22);
715
716 if (ppsc->support_aspm && !ppsc->support_backdoor)
717 rtl_write_byte(rtlpriv, 0x560, 0x40);
718 else
719 rtl_write_byte(rtlpriv, 0x560, 0x00);
720
721 rtl_write_byte(rtlpriv, DBG_PORT, 0x91);
722
723 /* Set RX Desc Address */
724 rtl_write_dword(rtlpriv, RDQDA, rtlpci->rx_ring[RX_MPDU_QUEUE].dma);
725 rtl_write_dword(rtlpriv, RCDA, rtlpci->rx_ring[RX_CMD_QUEUE].dma);
726
727 /* Set TX Desc Address */
728 rtl_write_dword(rtlpriv, TBKDA, rtlpci->tx_ring[BK_QUEUE].dma);
729 rtl_write_dword(rtlpriv, TBEDA, rtlpci->tx_ring[BE_QUEUE].dma);
730 rtl_write_dword(rtlpriv, TVIDA, rtlpci->tx_ring[VI_QUEUE].dma);
731 rtl_write_dword(rtlpriv, TVODA, rtlpci->tx_ring[VO_QUEUE].dma);
732 rtl_write_dword(rtlpriv, TBDA, rtlpci->tx_ring[BEACON_QUEUE].dma);
733 rtl_write_dword(rtlpriv, TCDA, rtlpci->tx_ring[TXCMD_QUEUE].dma);
734 rtl_write_dword(rtlpriv, TMDA, rtlpci->tx_ring[MGNT_QUEUE].dma);
735 rtl_write_dword(rtlpriv, THPDA, rtlpci->tx_ring[HIGH_QUEUE].dma);
736 rtl_write_dword(rtlpriv, HDA, rtlpci->tx_ring[HCCA_QUEUE].dma);
737
738 rtl_write_word(rtlpriv, CMDR, 0x37FC);
739
740 /* To make sure that TxDMA can ready to download FW. */
741 /* We should reset TxDMA if IMEM RPT was not ready. */
742 do {
743 tmpu1b = rtl_read_byte(rtlpriv, TCR);
744 if ((tmpu1b & TXDMA_INIT_VALUE) == TXDMA_INIT_VALUE)
745 break;
746
747 udelay(5);
748 } while (pollingcnt--);
749
750 if (pollingcnt <= 0) {
751 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
f30d7507
JP		 752 "Polling TXDMA_INIT_VALUE timeout!! Current TCR(%#x)\n",
753 tmpu1b);
24284531
CL		 754 tmpu1b = rtl_read_byte(rtlpriv, CMDR);
755 rtl_write_byte(rtlpriv, CMDR, tmpu1b & (~TXDMA_EN));
756 udelay(2);
757 /* Reset TxDMA */
758 rtl_write_byte(rtlpriv, CMDR, tmpu1b | TXDMA_EN);
759 }
760
761 /* After MACIO reset,we must refresh LED state. */
762 if ((ppsc->rfoff_reason == RF_CHANGE_BY_IPS) ||
763 (ppsc->rfoff_reason == 0)) {
764 struct rtl_pci_priv *pcipriv = rtl_pcipriv(hw);
765 struct rtl_led *pLed0 = &(pcipriv->ledctl.sw_led0);
766 enum rf_pwrstate rfpwr_state_toset;
767 rfpwr_state_toset = _rtl92se_rf_onoff_detect(hw);
768
769 if (rfpwr_state_toset == ERFON)
770 rtl92se_sw_led_on(hw, pLed0);
771 }
772}
773
774static void _rtl92se_macconfig_after_fwdownload(struct ieee80211_hw *hw)
775{
776 struct rtl_priv *rtlpriv = rtl_priv(hw);
777 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
778 struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
779 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
780 u8 i;
781 u16 tmpu2b;
782
783 /* 1. System Configure Register (Offset: 0x0000 - 0x003F) */
784
785 /* 2. Command Control Register (Offset: 0x0040 - 0x004F) */
786 /* Turn on 0x40 Command register */
787 rtl_write_word(rtlpriv, CMDR, (BBRSTN | BB_GLB_RSTN |
788 SCHEDULE_EN | MACRXEN | MACTXEN | DDMA_EN | FW2HW_EN |
789 RXDMA_EN | TXDMA_EN | HCI_RXDMA_EN | HCI_TXDMA_EN));
790
791 /* Set TCR TX DMA pre 2 FULL enable bit */
792 rtl_write_dword(rtlpriv, TCR, rtl_read_dword(rtlpriv, TCR) |
793 TXDMAPRE2FULL);
794
795 /* Set RCR */
796 rtl_write_dword(rtlpriv, RCR, rtlpci->receive_config);
797
798 /* 3. MACID Setting Register (Offset: 0x0050 - 0x007F) */
799
800 /* 4. Timing Control Register (Offset: 0x0080 - 0x009F) */
801 /* Set CCK/OFDM SIFS */
802 /* CCK SIFS shall always be 10us. */
803 rtl_write_word(rtlpriv, SIFS_CCK, 0x0a0a);
804 rtl_write_word(rtlpriv, SIFS_OFDM, 0x1010);
805
806 /* Set AckTimeout */
807 rtl_write_byte(rtlpriv, ACK_TIMEOUT, 0x40);
808
809 /* Beacon related */
810 rtl_write_word(rtlpriv, BCN_INTERVAL, 100);
811 rtl_write_word(rtlpriv, ATIMWND, 2);
812
813 /* 5. FIFO Control Register (Offset: 0x00A0 - 0x015F) */
814 /* 5.1 Initialize Number of Reserved Pages in Firmware Queue */
815 /* Firmware allocate now, associate with FW internal setting.!!! */
816
817 /* 5.2 Setting TX/RX page size 0/1/2/3/4=64/128/256/512/1024 */
818 /* 5.3 Set driver info, we only accept PHY status now. */
819 /* 5.4 Set RXDMA arbitration to control RXDMA/MAC/FW R/W for RXFIFO */
820 rtl_write_byte(rtlpriv, RXDMA, rtl_read_byte(rtlpriv, RXDMA) | BIT(6));
821
822 /* 6. Adaptive Control Register (Offset: 0x0160 - 0x01CF) */
823 /* Set RRSR to all legacy rate and HT rate
824 * CCK rate is supported by default.
825 * CCK rate will be filtered out only when associated
826 * AP does not support it.
827 * Only enable ACK rate to OFDM 24M
828 * Disable RRSR for CCK rate in A-Cut */
829
830 if (rtlhal->version == VERSION_8192S_ACUT)
831 rtl_write_byte(rtlpriv, RRSR, 0xf0);
832 else if (rtlhal->version == VERSION_8192S_BCUT)
833 rtl_write_byte(rtlpriv, RRSR, 0xff);
834 rtl_write_byte(rtlpriv, RRSR + 1, 0x01);
835 rtl_write_byte(rtlpriv, RRSR + 2, 0x00);
836
837 /* A-Cut IC do not support CCK rate. We forbid ARFR to */
838 /* fallback to CCK rate */
839 for (i = 0; i < 8; i++) {
840 /*Disable RRSR for CCK rate in A-Cut */
841 if (rtlhal->version == VERSION_8192S_ACUT)
842 rtl_write_dword(rtlpriv, ARFR0 + i * 4, 0x1f0ff0f0);
843 }
844
845 /* Different rate use different AMPDU size */
846 /* MCS32/ MCS15_SG use max AMPDU size 15*2=30K */
847 rtl_write_byte(rtlpriv, AGGLEN_LMT_H, 0x0f);
848 /* MCS0/1/2/3 use max AMPDU size 4*2=8K */
849 rtl_write_word(rtlpriv, AGGLEN_LMT_L, 0x7442);
850 /* MCS4/5 use max AMPDU size 8*2=16K 6/7 use 10*2=20K */
851 rtl_write_word(rtlpriv, AGGLEN_LMT_L + 2, 0xddd7);
852 /* MCS8/9 use max AMPDU size 8*2=16K 10/11 use 10*2=20K */
853 rtl_write_word(rtlpriv, AGGLEN_LMT_L + 4, 0xd772);
854 /* MCS12/13/14/15 use max AMPDU size 15*2=30K */
855 rtl_write_word(rtlpriv, AGGLEN_LMT_L + 6, 0xfffd);
856
857 /* Set Data / Response auto rate fallack retry count */
858 rtl_write_dword(rtlpriv, DARFRC, 0x04010000);
859 rtl_write_dword(rtlpriv, DARFRC + 4, 0x09070605);
860 rtl_write_dword(rtlpriv, RARFRC, 0x04010000);
861 rtl_write_dword(rtlpriv, RARFRC + 4, 0x09070605);
862
863 /* 7. EDCA Setting Register (Offset: 0x01D0 - 0x01FF) */
864 /* Set all rate to support SG */
865 rtl_write_word(rtlpriv, SG_RATE, 0xFFFF);
866
867 /* 8. WMAC, BA, and CCX related Register (Offset: 0x0200 - 0x023F) */
868 /* Set NAV protection length */
869 rtl_write_word(rtlpriv, NAV_PROT_LEN, 0x0080);
870 /* CF-END Threshold */
871 rtl_write_byte(rtlpriv, CFEND_TH, 0xFF);
872 /* Set AMPDU minimum space */
873 rtl_write_byte(rtlpriv, AMPDU_MIN_SPACE, 0x07);
874 /* Set TXOP stall control for several queue/HI/BCN/MGT/ */
875 rtl_write_byte(rtlpriv, TXOP_STALL_CTRL, 0x00);
876
877 /* 9. Security Control Register (Offset: 0x0240 - 0x025F) */
878 /* 10. Power Save Control Register (Offset: 0x0260 - 0x02DF) */
879 /* 11. General Purpose Register (Offset: 0x02E0 - 0x02FF) */
880 /* 12. Host Interrupt Status Register (Offset: 0x0300 - 0x030F) */
881 /* 13. Test Mode and Debug Control Register (Offset: 0x0310 - 0x034F) */
882
883 /* 14. Set driver info, we only accept PHY status now. */
884 rtl_write_byte(rtlpriv, RXDRVINFO_SZ, 4);
885
886 /* 15. For EEPROM R/W Workaround */
887 /* 16. For EFUSE to share REG_SYS_FUNC_EN with EEPROM!!! */
888 tmpu2b = rtl_read_byte(rtlpriv, REG_SYS_FUNC_EN);
889 rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN, tmpu2b | BIT(13));
890 tmpu2b = rtl_read_byte(rtlpriv, REG_SYS_ISO_CTRL);
891 rtl_write_byte(rtlpriv, REG_SYS_ISO_CTRL, tmpu2b & (~BIT(8)));
892
893 /* 17. For EFUSE */
894 /* We may R/W EFUSE in EEPROM mode */
895 if (rtlefuse->epromtype == EEPROM_BOOT_EFUSE) {
896 u8 tempval;
897
898 tempval = rtl_read_byte(rtlpriv, REG_SYS_ISO_CTRL + 1);
899 tempval &= 0xFE;
900 rtl_write_byte(rtlpriv, REG_SYS_ISO_CTRL + 1, tempval);
901
902 /* Change Program timing */
903 rtl_write_byte(rtlpriv, REG_EFUSE_CTRL + 3, 0x72);
f30d7507 904 RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG, "EFUSE CONFIG OK\n");
24284531
CL		 905 }
906
f30d7507 907 RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG, "OK\n");
24284531
CL		 908
909}
910
911static void _rtl92se_hw_configure(struct ieee80211_hw *hw)
912{
913 struct rtl_priv *rtlpriv = rtl_priv(hw);
914 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
915 struct rtl_phy *rtlphy = &(rtlpriv->phy);
916 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
917
918 u8 reg_bw_opmode = 0;
78d57372 919 u32 reg_rrsr = 0;
24284531
CL		 920 u8 regtmp = 0;
921
922 reg_bw_opmode = BW_OPMODE_20MHZ;
24284531
CL		 923 reg_rrsr = RATE_ALL_CCK | RATE_ALL_OFDM_AG;
924
925 regtmp = rtl_read_byte(rtlpriv, INIRTSMCS_SEL);
926 reg_rrsr = ((reg_rrsr & 0x000fffff) << 8) | regtmp;
927 rtl_write_dword(rtlpriv, INIRTSMCS_SEL, reg_rrsr);
928 rtl_write_byte(rtlpriv, BW_OPMODE, reg_bw_opmode);
929
930 /* Set Retry Limit here */
931 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_RETRY_LIMIT,
932 (u8 *)(&rtlpci->shortretry_limit));
933
934 rtl_write_byte(rtlpriv, MLT, 0x8f);
935
936 /* For Min Spacing configuration. */
937 switch (rtlphy->rf_type) {
938 case RF_1T2R:
939 case RF_1T1R:
940 rtlhal->minspace_cfg = (MAX_MSS_DENSITY_1T << 3);
941 break;
942 case RF_2T2R:
943 case RF_2T2R_GREEN:
944 rtlhal->minspace_cfg = (MAX_MSS_DENSITY_2T << 3);
945 break;
946 }
947 rtl_write_byte(rtlpriv, AMPDU_MIN_SPACE, rtlhal->minspace_cfg);
948}
949
950int rtl92se_hw_init(struct ieee80211_hw *hw)
951{
952 struct rtl_priv *rtlpriv = rtl_priv(hw);
953 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
954 struct rtl_phy *rtlphy = &(rtlpriv->phy);
955 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
956 struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
957 u8 tmp_byte = 0;
958
959 bool rtstatus = true;
960 u8 tmp_u1b;
961 int err = false;
962 u8 i;
963 int wdcapra_add[] = {
964 EDCAPARA_BE, EDCAPARA_BK,
965 EDCAPARA_VI, EDCAPARA_VO};
966 u8 secr_value = 0x0;
967
968 rtlpci->being_init_adapter = true;
969
970 rtlpriv->intf_ops->disable_aspm(hw);
971
972 /* 1. MAC Initialize */
973 /* Before FW download, we have to set some MAC register */
974 _rtl92se_macconfig_before_fwdownload(hw);
975
976 rtlhal->version = (enum version_8192s)((rtl_read_dword(rtlpriv,
977 PMC_FSM) >> 16) & 0xF);
978
979 rtl8192se_gpiobit3_cfg_inputmode(hw);
980
981 /* 2. download firmware */
982 rtstatus = rtl92s_download_fw(hw);
983 if (!rtstatus) {
984 RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING,
b0302aba
LF		 985 "Failed to download FW. Init HW without FW now... "
986 "Please copy FW into /lib/firmware/rtlwifi\n");
987 return 1;
24284531
CL		 988 }
989
990 /* After FW download, we have to reset MAC register */
991 _rtl92se_macconfig_after_fwdownload(hw);
992
993 /*Retrieve default FW Cmd IO map. */
994 rtlhal->fwcmd_iomap = rtl_read_word(rtlpriv, LBUS_MON_ADDR);
995 rtlhal->fwcmd_ioparam = rtl_read_dword(rtlpriv, LBUS_ADDR_MASK);
996
997 /* 3. Initialize MAC/PHY Config by MACPHY_reg.txt */
23677ce3 998 if (!rtl92s_phy_mac_config(hw)) {
f30d7507 999 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG, "MAC Config failed\n");
24284531
CL		 1000 return rtstatus;
1001 }
1002
2455c92c
LF		 1003 /* because last function modify RCR, so we update
1004 * rcr var here, or TP will unstable for receive_config
1005 * is wrong, RX RCR_ACRC32 will cause TP unstabel & Rx
1006 * RCR_APP_ICV will cause mac80211 unassoc for cisco 1252
1007 */
1008 rtlpci->receive_config = rtl_read_dword(rtlpriv, RCR);
1009 rtlpci->receive_config &= ~(RCR_ACRC32 | RCR_AICV);
1010 rtl_write_dword(rtlpriv, RCR, rtlpci->receive_config);
1011
24284531
CL		 1012 /* Make sure BB/RF write OK. We should prevent enter IPS. radio off. */
1013 /* We must set flag avoid BB/RF config period later!! */
1014 rtl_write_dword(rtlpriv, CMDR, 0x37FC);
1015
1016 /* 4. Initialize BB After MAC Config PHY_reg.txt, AGC_Tab.txt */
23677ce3 1017 if (!rtl92s_phy_bb_config(hw)) {
f30d7507 1018 RT_TRACE(rtlpriv, COMP_INIT, DBG_EMERG, "BB Config failed\n");
24284531
CL		 1019 return rtstatus;
1020 }
1021
1022 /* 5. Initiailze RF RAIO_A.txt RF RAIO_B.txt */
1023 /* Before initalizing RF. We can not use FW to do RF-R/W. */
1024
1025 rtlphy->rf_mode = RF_OP_BY_SW_3WIRE;
1026
24284531
CL		 1027 /* Before RF-R/W we must execute the IO from Scott's suggestion. */
1028 rtl_write_byte(rtlpriv, AFE_XTAL_CTRL + 1, 0xDB);
1029 if (rtlhal->version == VERSION_8192S_ACUT)
1030 rtl_write_byte(rtlpriv, SPS1_CTRL + 3, 0x07);
1031 else
1032 rtl_write_byte(rtlpriv, RF_CTRL, 0x07);
1033
23677ce3 1034 if (!rtl92s_phy_rf_config(hw)) {
f30d7507 1035 RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG, "RF Config failed\n");
24284531
CL		 1036 return rtstatus;
1037 }
1038
1039 /* After read predefined TXT, we must set BB/MAC/RF
1040 * register as our requirement */
1041
1042 rtlphy->rfreg_chnlval[0] = rtl92s_phy_query_rf_reg(hw,
1043 (enum radio_path)0,
1044 RF_CHNLBW,
1045 RFREG_OFFSET_MASK);
1046 rtlphy->rfreg_chnlval[1] = rtl92s_phy_query_rf_reg(hw,
1047 (enum radio_path)1,
1048 RF_CHNLBW,
1049 RFREG_OFFSET_MASK);
1050
1051 /*---- Set CCK and OFDM Block "ON"----*/
1052 rtl_set_bbreg(hw, RFPGA0_RFMOD, BCCKEN, 0x1);
1053 rtl_set_bbreg(hw, RFPGA0_RFMOD, BOFDMEN, 0x1);
1054
1055 /*3 Set Hardware(Do nothing now) */
1056 _rtl92se_hw_configure(hw);
1057
1058 /* Read EEPROM TX power index and PHY_REG_PG.txt to capture correct */
1059 /* TX power index for different rate set. */
1060 /* Get original hw reg values */
1061 rtl92s_phy_get_hw_reg_originalvalue(hw);
1062 /* Write correct tx power index */
1063 rtl92s_phy_set_txpower(hw, rtlphy->current_channel);
1064
1065 /* We must set MAC address after firmware download. */
1066 for (i = 0; i < 6; i++)
1067 rtl_write_byte(rtlpriv, MACIDR0 + i, rtlefuse->dev_addr[i]);
1068
1069 /* EEPROM R/W workaround */
1070 tmp_u1b = rtl_read_byte(rtlpriv, MAC_PINMUX_CFG);
1071 rtl_write_byte(rtlpriv, MAC_PINMUX_CFG, tmp_u1b & (~BIT(3)));
1072
1073 rtl_write_byte(rtlpriv, 0x4d, 0x0);
1074
1075 if (hal_get_firmwareversion(rtlpriv) >= 0x49) {
1076 tmp_byte = rtl_read_byte(rtlpriv, FW_RSVD_PG_CRTL) & (~BIT(4));
1077 tmp_byte = tmp_byte | BIT(5);
1078 rtl_write_byte(rtlpriv, FW_RSVD_PG_CRTL, tmp_byte);
1079 rtl_write_dword(rtlpriv, TXDESC_MSK, 0xFFFFCFFF);
1080 }
1081
1082 /* We enable high power and RA related mechanism after NIC
1083 * initialized. */
2455c92c
LF		 1084 if (hal_get_firmwareversion(rtlpriv) >= 0x35) {
1085 /* Fw v.53 and later. */
1086 rtl92s_phy_set_fw_cmd(hw, FW_CMD_RA_INIT);
1087 } else if (hal_get_firmwareversion(rtlpriv) == 0x34) {
1088 /* Fw v.52. */
1089 rtl_write_dword(rtlpriv, WFM5, FW_RA_INIT);
1090 rtl92s_phy_chk_fwcmd_iodone(hw);
1091 } else {
1092 /* Compatible earlier FW version. */
1093 rtl_write_dword(rtlpriv, WFM5, FW_RA_RESET);
1094 rtl92s_phy_chk_fwcmd_iodone(hw);
1095 rtl_write_dword(rtlpriv, WFM5, FW_RA_ACTIVE);
1096 rtl92s_phy_chk_fwcmd_iodone(hw);
1097 rtl_write_dword(rtlpriv, WFM5, FW_RA_REFRESH);
1098 rtl92s_phy_chk_fwcmd_iodone(hw);
1099 }
24284531
CL		 1100
1101 /* Add to prevent ASPM bug. */
1102 /* Always enable hst and NIC clock request. */
1103 rtl92s_phy_switch_ephy_parameter(hw);
1104
1105 /* Security related
1106 * 1. Clear all H/W keys.
1107 * 2. Enable H/W encryption/decryption. */
1108 rtl_cam_reset_all_entry(hw);
1109 secr_value |= SCR_TXENCENABLE;
1110 secr_value |= SCR_RXENCENABLE;
1111 secr_value |= SCR_NOSKMC;
1112 rtl_write_byte(rtlpriv, REG_SECR, secr_value);
1113
1114 for (i = 0; i < 4; i++)
1115 rtl_write_dword(rtlpriv, wdcapra_add[i], 0x5e4322);
1116
1117 if (rtlphy->rf_type == RF_1T2R) {
1118 bool mrc2set = true;
1119 /* Turn on B-Path */
1120 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_MRC, (u8 *)&mrc2set);
1121 }
1122
1123 rtlpriv->cfg->ops->led_control(hw, LED_CTL_POWER_ON);
1124 rtl92s_dm_init(hw);
1125 rtlpci->being_init_adapter = false;
1126
1127 return err;
1128}
1129
dac67975 1130void rtl92se_set_mac_addr(struct rtl_io *io, const u8 *addr)
24284531 1131{
dac67975 1132 /* This is a stub. */
24284531
CL		 1133}
1134
1135void rtl92se_set_check_bssid(struct ieee80211_hw *hw, bool check_bssid)
1136{
1137 struct rtl_priv *rtlpriv = rtl_priv(hw);
e51048cd 1138 u32 reg_rcr;
24284531
CL		 1139
1140 if (rtlpriv->psc.rfpwr_state != ERFON)
1141 return;
1142
e51048cd
PW		 1143 rtlpriv->cfg->ops->get_hw_reg(hw, HW_VAR_RCR, (u8 *)(&reg_rcr));
1144
e10542c4 1145 if (check_bssid) {
24284531
CL		 1146 reg_rcr |= (RCR_CBSSID);
1147 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_RCR, (u8 *)(&reg_rcr));
23677ce3 1148 } else if (!check_bssid) {
24284531
CL		 1149 reg_rcr &= (~RCR_CBSSID);
1150 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_RCR, (u8 *)(&reg_rcr));
1151 }
1152
1153}
1154
1155static int _rtl92se_set_media_status(struct ieee80211_hw *hw,
1156 enum nl80211_iftype type)
1157{
1158 struct rtl_priv *rtlpriv = rtl_priv(hw);
1159 u8 bt_msr = rtl_read_byte(rtlpriv, MSR);
24284531
CL		 1160 u32 temp;
1161 bt_msr &= ~MSR_LINK_MASK;
1162
1163 switch (type) {
1164 case NL80211_IFTYPE_UNSPECIFIED:
1165 bt_msr |= (MSR_LINK_NONE << MSR_LINK_SHIFT);
24284531 1166 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
f30d7507 1167 "Set Network type to NO LINK!\n");
24284531
CL		 1168 break;
1169 case NL80211_IFTYPE_ADHOC:
1170 bt_msr |= (MSR_LINK_ADHOC << MSR_LINK_SHIFT);
1171 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
f30d7507 1172 "Set Network type to Ad Hoc!\n");
24284531
CL		 1173 break;
1174 case NL80211_IFTYPE_STATION:
1175 bt_msr |= (MSR_LINK_MANAGED << MSR_LINK_SHIFT);
24284531 1176 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
f30d7507 1177 "Set Network type to STA!\n");
24284531
CL		 1178 break;
1179 case NL80211_IFTYPE_AP:
1180 bt_msr |= (MSR_LINK_MASTER << MSR_LINK_SHIFT);
1181 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
f30d7507 1182 "Set Network type to AP!\n");
24284531
CL		 1183 break;
1184 default:
1185 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
f30d7507 1186 "Network type %d not supported!\n", type);
24284531
CL		 1187 return 1;
1188 break;
1189
1190 }
1191
1192 rtl_write_byte(rtlpriv, (MSR), bt_msr);
1193
1194 temp = rtl_read_dword(rtlpriv, TCR);
1195 rtl_write_dword(rtlpriv, TCR, temp & (~BIT(8)));
1196 rtl_write_dword(rtlpriv, TCR, temp | BIT(8));
1197
1198
1199 return 0;
1200}
1201
1202/* HW_VAR_MEDIA_STATUS & HW_VAR_CECHK_BSSID */
1203int rtl92se_set_network_type(struct ieee80211_hw *hw, enum nl80211_iftype type)
1204{
1205 struct rtl_priv *rtlpriv = rtl_priv(hw);
1206
1207 if (_rtl92se_set_media_status(hw, type))
1208 return -EOPNOTSUPP;
1209
1210 if (rtlpriv->mac80211.link_state == MAC80211_LINKED) {
1211 if (type != NL80211_IFTYPE_AP)
1212 rtl92se_set_check_bssid(hw, true);
1213 } else {
1214 rtl92se_set_check_bssid(hw, false);
1215 }
1216
1217 return 0;
1218}
1219
1220/* don't set REG_EDCA_BE_PARAM here because mac80211 will send pkt when scan */
1221void rtl92se_set_qos(struct ieee80211_hw *hw, int aci)
1222{
1223 struct rtl_priv *rtlpriv = rtl_priv(hw);
1224 rtl92s_dm_init_edca_turbo(hw);
1225
1226 switch (aci) {
1227 case AC1_BK:
1228 rtl_write_dword(rtlpriv, EDCAPARA_BK, 0xa44f);
1229 break;
1230 case AC0_BE:
1231 /* rtl_write_dword(rtlpriv, EDCAPARA_BE, u4b_ac_param); */
1232 break;
1233 case AC2_VI:
1234 rtl_write_dword(rtlpriv, EDCAPARA_VI, 0x5e4322);
1235 break;
1236 case AC3_VO:
1237 rtl_write_dword(rtlpriv, EDCAPARA_VO, 0x2f3222);
1238 break;
1239 default:
9d833ed7 1240 RT_ASSERT(false, "invalid aci: %d !\n", aci);
24284531
CL		 1241 break;
1242 }
1243}
1244
1245void rtl92se_enable_interrupt(struct ieee80211_hw *hw)
1246{
1247 struct rtl_priv *rtlpriv = rtl_priv(hw);
1248 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
1249
1250 rtl_write_dword(rtlpriv, INTA_MASK, rtlpci->irq_mask[0]);
1251 /* Support Bit 32-37(Assign as Bit 0-5) interrupt setting now */
1252 rtl_write_dword(rtlpriv, INTA_MASK + 4, rtlpci->irq_mask[1] & 0x3F);
24284531
CL		 1253}
1254
1255void rtl92se_disable_interrupt(struct ieee80211_hw *hw)
1256{
b0302aba
LF		 1257 struct rtl_priv *rtlpriv;
1258 struct rtl_pci *rtlpci;
24284531 1259
b0302aba
LF		 1260 rtlpriv = rtl_priv(hw);
1261 /* if firmware not available, no interrupts */
1262 if (!rtlpriv || !rtlpriv->max_fw_size)
1263 return;
1264 rtlpci = rtl_pcidev(rtl_pcipriv(hw));
24284531
CL		 1265 rtl_write_dword(rtlpriv, INTA_MASK, 0);
1266 rtl_write_dword(rtlpriv, INTA_MASK + 4, 0);
1267
049436b9 1268 synchronize_irq(rtlpci->pdev->irq);
24284531
CL		 1269}
1270
24284531
CL		 1271static u8 _rtl92s_set_sysclk(struct ieee80211_hw *hw, u8 data)
1272{
1273 struct rtl_priv *rtlpriv = rtl_priv(hw);
1274 u8 waitcnt = 100;
1275 bool result = false;
1276 u8 tmp;
1277
1278 rtl_write_byte(rtlpriv, SYS_CLKR + 1, data);
1279
1280 /* Wait the MAC synchronized. */
1281 udelay(400);
1282
1283 /* Check if it is set ready. */
1284 tmp = rtl_read_byte(rtlpriv, SYS_CLKR + 1);
1285 result = ((tmp & BIT(7)) == (data & BIT(7)));
1286
1287 if ((data & (BIT(6) | BIT(7))) == false) {
1288 waitcnt = 100;
1289 tmp = 0;
1290
1291 while (1) {
1292 waitcnt--;
1293 tmp = rtl_read_byte(rtlpriv, SYS_CLKR + 1);
1294
1295 if ((tmp & BIT(6)))
1296 break;
1297
292b1192 1298 pr_err("wait for BIT(6) return value %x\n", tmp);
24284531
CL		 1299
1300 if (waitcnt == 0)
1301 break;
1302 udelay(10);
1303 }
1304
1305 if (waitcnt == 0)
1306 result = false;
1307 else
1308 result = true;
1309 }
1310
1311 return result;
1312}
1313
1314static void _rtl92s_phy_set_rfhalt(struct ieee80211_hw *hw)
1315{
1316 struct rtl_priv *rtlpriv = rtl_priv(hw);
1317 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
1318 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
1319 u8 u1btmp;
1320
1321 if (rtlhal->driver_going2unload)
1322 rtl_write_byte(rtlpriv, 0x560, 0x0);
1323
1324 /* Power save for BB/RF */
1325 u1btmp = rtl_read_byte(rtlpriv, LDOV12D_CTRL);
1326 u1btmp |= BIT(0);
1327 rtl_write_byte(rtlpriv, LDOV12D_CTRL, u1btmp);
1328 rtl_write_byte(rtlpriv, SPS1_CTRL, 0x0);
1329 rtl_write_byte(rtlpriv, TXPAUSE, 0xFF);
1330 rtl_write_word(rtlpriv, CMDR, 0x57FC);
1331 udelay(100);
1332 rtl_write_word(rtlpriv, CMDR, 0x77FC);
1333 rtl_write_byte(rtlpriv, PHY_CCA, 0x0);
1334 udelay(10);
1335 rtl_write_word(rtlpriv, CMDR, 0x37FC);
1336 udelay(10);
1337 rtl_write_word(rtlpriv, CMDR, 0x77FC);
1338 udelay(10);
1339 rtl_write_word(rtlpriv, CMDR, 0x57FC);
1340 rtl_write_word(rtlpriv, CMDR, 0x0000);
1341
1342 if (rtlhal->driver_going2unload) {
1343 u1btmp = rtl_read_byte(rtlpriv, (REG_SYS_FUNC_EN + 1));
1344 u1btmp &= ~(BIT(0));
1345 rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN + 1, u1btmp);
1346 }
1347
1348 u1btmp = rtl_read_byte(rtlpriv, (SYS_CLKR + 1));
1349
1350 /* Add description. After switch control path. register
1351 * after page1 will be invisible. We can not do any IO
1352 * for register>0x40. After resume&MACIO reset, we need
1353 * to remember previous reg content. */
1354 if (u1btmp & BIT(7)) {
1355 u1btmp &= ~(BIT(6) | BIT(7));
1356 if (!_rtl92s_set_sysclk(hw, u1btmp)) {
292b1192 1357 pr_err("Switch ctrl path fail\n");
24284531
CL		 1358 return;
1359 }
1360 }
1361
1362 /* Power save for MAC */
1363 if (ppsc->rfoff_reason == RF_CHANGE_BY_IPS &&
1364 !rtlhal->driver_going2unload) {
1365 /* enable LED function */
1366 rtl_write_byte(rtlpriv, 0x03, 0xF9);
1367 /* SW/HW radio off or halt adapter!! For example S3/S4 */
1368 } else {
1369 /* LED function disable. Power range is about 8mA now. */
1370 /* if write 0xF1 disconnet_pci power
1371 * ifconfig wlan0 down power are both high 35:70 */
1372 /* if write oxF9 disconnet_pci power
1373 * ifconfig wlan0 down power are both low 12:45*/
1374 rtl_write_byte(rtlpriv, 0x03, 0xF9);
1375 }
1376
1377 rtl_write_byte(rtlpriv, SYS_CLKR + 1, 0x70);
1378 rtl_write_byte(rtlpriv, AFE_PLL_CTRL + 1, 0x68);
1379 rtl_write_byte(rtlpriv, AFE_PLL_CTRL, 0x00);
1380 rtl_write_byte(rtlpriv, LDOA15_CTRL, 0x34);
1381 rtl_write_byte(rtlpriv, AFE_XTAL_CTRL, 0x0E);
1382 RT_SET_PS_LEVEL(ppsc, RT_RF_OFF_LEVL_HALT_NIC);
1383
1384}
1385
1386static void _rtl92se_gen_refreshledstate(struct ieee80211_hw *hw)
1387{
1388 struct rtl_priv *rtlpriv = rtl_priv(hw);
1389 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
1390 struct rtl_pci_priv *pcipriv = rtl_pcipriv(hw);
1391 struct rtl_led *pLed0 = &(pcipriv->ledctl.sw_led0);
1392
1393 if (rtlpci->up_first_time == 1)
1394 return;
1395
1396 if (rtlpriv->psc.rfoff_reason == RF_CHANGE_BY_IPS)
1397 rtl92se_sw_led_on(hw, pLed0);
1398 else
1399 rtl92se_sw_led_off(hw, pLed0);
1400}
1401
1402
1403static void _rtl92se_power_domain_init(struct ieee80211_hw *hw)
1404{
1405 struct rtl_priv *rtlpriv = rtl_priv(hw);
1406 u16 tmpu2b;
1407 u8 tmpu1b;
1408
1409 rtlpriv->psc.pwrdomain_protect = true;
1410
1411 tmpu1b = rtl_read_byte(rtlpriv, (SYS_CLKR + 1));
1412 if (tmpu1b & BIT(7)) {
1413 tmpu1b &= ~(BIT(6) | BIT(7));
1414 if (!_rtl92s_set_sysclk(hw, tmpu1b)) {
1415 rtlpriv->psc.pwrdomain_protect = false;
1416 return;
1417 }
1418 }
1419
1420 rtl_write_byte(rtlpriv, AFE_PLL_CTRL, 0x0);
1421 rtl_write_byte(rtlpriv, LDOA15_CTRL, 0x34);
1422
1423 /* Reset MAC-IO and CPU and Core Digital BIT10/11/15 */
5c079d88 1424 tmpu1b = rtl_read_byte(rtlpriv, REG_SYS_FUNC_EN + 1);
24284531
CL		 1425
1426 /* If IPS we need to turn LED on. So we not
1427 * not disable BIT 3/7 of reg3. */
1428 if (rtlpriv->psc.rfoff_reason & (RF_CHANGE_BY_IPS | RF_CHANGE_BY_HW))
1429 tmpu1b &= 0xFB;
1430 else
1431 tmpu1b &= 0x73;
1432
5c079d88 1433 rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN + 1, tmpu1b);
24284531
CL		 1434 /* wait for BIT 10/11/15 to pull high automatically!! */
1435 mdelay(1);
1436
1437 rtl_write_byte(rtlpriv, CMDR, 0);
1438 rtl_write_byte(rtlpriv, TCR, 0);
1439
1440 /* Data sheet not define 0x562!!! Copy from WMAC!!!!! */
1441 tmpu1b = rtl_read_byte(rtlpriv, 0x562);
1442 tmpu1b |= 0x08;
1443 rtl_write_byte(rtlpriv, 0x562, tmpu1b);
1444 tmpu1b &= ~(BIT(3));
1445 rtl_write_byte(rtlpriv, 0x562, tmpu1b);
1446
1447 /* Enable AFE clock source */
1448 tmpu1b = rtl_read_byte(rtlpriv, AFE_XTAL_CTRL);
1449 rtl_write_byte(rtlpriv, AFE_XTAL_CTRL, (tmpu1b | 0x01));
1450 /* Delay 1.5ms */
1451 udelay(1500);
1452 tmpu1b = rtl_read_byte(rtlpriv, AFE_XTAL_CTRL + 1);
1453 rtl_write_byte(rtlpriv, AFE_XTAL_CTRL + 1, (tmpu1b & 0xfb));
1454
1455 /* Enable AFE Macro Block's Bandgap */
1456 tmpu1b = rtl_read_byte(rtlpriv, AFE_MISC);
1457 rtl_write_byte(rtlpriv, AFE_MISC, (tmpu1b | BIT(0)));
1458 mdelay(1);
1459
1460 /* Enable AFE Mbias */
1461 tmpu1b = rtl_read_byte(rtlpriv, AFE_MISC);
1462 rtl_write_byte(rtlpriv, AFE_MISC, (tmpu1b | 0x02));
1463 mdelay(1);
1464
1465 /* Enable LDOA15 block */
1466 tmpu1b = rtl_read_byte(rtlpriv, LDOA15_CTRL);
1467 rtl_write_byte(rtlpriv, LDOA15_CTRL, (tmpu1b | BIT(0)));
1468
1469 /* Set Digital Vdd to Retention isolation Path. */
5c079d88
CL		 1470 tmpu2b = rtl_read_word(rtlpriv, REG_SYS_ISO_CTRL);
1471 rtl_write_word(rtlpriv, REG_SYS_ISO_CTRL, (tmpu2b | BIT(11)));
24284531
CL		 1472
1473
1474 /* For warm reboot NIC disappera bug. */
5c079d88
CL		 1475 tmpu2b = rtl_read_word(rtlpriv, REG_SYS_FUNC_EN);
1476 rtl_write_word(rtlpriv, REG_SYS_FUNC_EN, (tmpu2b | BIT(13)));
24284531 1477
5c079d88 1478 rtl_write_byte(rtlpriv, REG_SYS_ISO_CTRL + 1, 0x68);
24284531
CL		 1479
1480 /* Enable AFE PLL Macro Block */
1481 tmpu1b = rtl_read_byte(rtlpriv, AFE_PLL_CTRL);
1482 rtl_write_byte(rtlpriv, AFE_PLL_CTRL, (tmpu1b | BIT(0) | BIT(4)));
1483 /* Enable MAC 80MHZ clock */
1484 tmpu1b = rtl_read_byte(rtlpriv, AFE_PLL_CTRL + 1);
1485 rtl_write_byte(rtlpriv, AFE_PLL_CTRL + 1, (tmpu1b | BIT(0)));
1486 mdelay(1);
1487
1488 /* Release isolation AFE PLL & MD */
5c079d88 1489 rtl_write_byte(rtlpriv, REG_SYS_ISO_CTRL, 0xA6);
24284531
CL		 1490
1491 /* Enable MAC clock */
1492 tmpu2b = rtl_read_word(rtlpriv, SYS_CLKR);
1493 rtl_write_word(rtlpriv, SYS_CLKR, (tmpu2b | BIT(12) | BIT(11)));
1494
1495 /* Enable Core digital and enable IOREG R/W */
5c079d88
CL		 1496 tmpu2b = rtl_read_word(rtlpriv, REG_SYS_FUNC_EN);
1497 rtl_write_word(rtlpriv, REG_SYS_FUNC_EN, (tmpu2b | BIT(11)));
24284531 1498 /* enable REG_EN */
5c079d88 1499 rtl_write_word(rtlpriv, REG_SYS_FUNC_EN, (tmpu2b | BIT(11) | BIT(15)));
24284531
CL		 1500
1501 /* Switch the control path. */
1502 tmpu2b = rtl_read_word(rtlpriv, SYS_CLKR);
1503 rtl_write_word(rtlpriv, SYS_CLKR, (tmpu2b & (~BIT(2))));
1504
1505 tmpu1b = rtl_read_byte(rtlpriv, (SYS_CLKR + 1));
1506 tmpu1b = ((tmpu1b | BIT(7)) & (~BIT(6)));
1507 if (!_rtl92s_set_sysclk(hw, tmpu1b)) {
1508 rtlpriv->psc.pwrdomain_protect = false;
1509 return;
1510 }
1511
1512 rtl_write_word(rtlpriv, CMDR, 0x37FC);
1513
1514 /* After MACIO reset,we must refresh LED state. */
1515 _rtl92se_gen_refreshledstate(hw);
1516
1517 rtlpriv->psc.pwrdomain_protect = false;
1518}
1519
1520void rtl92se_card_disable(struct ieee80211_hw *hw)
1521{
1522 struct rtl_priv *rtlpriv = rtl_priv(hw);
1523 struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
1524 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
1525 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
1526 enum nl80211_iftype opmode;
1527 u8 wait = 30;
1528
1529 rtlpriv->intf_ops->enable_aspm(hw);
1530
1531 if (rtlpci->driver_is_goingto_unload ||
1532 ppsc->rfoff_reason > RF_CHANGE_BY_PS)
1533 rtlpriv->cfg->ops->led_control(hw, LED_CTL_POWER_OFF);
1534
1535 /* we should chnge GPIO to input mode
1536 * this will drop away current about 25mA*/
1537 rtl8192se_gpiobit3_cfg_inputmode(hw);
1538
1539 /* this is very important for ips power save */
1540 while (wait-- >= 10 && rtlpriv->psc.pwrdomain_protect) {
1541 if (rtlpriv->psc.pwrdomain_protect)
1542 mdelay(20);
1543 else
1544 break;
1545 }
1546
1547 mac->link_state = MAC80211_NOLINK;
1548 opmode = NL80211_IFTYPE_UNSPECIFIED;
1549 _rtl92se_set_media_status(hw, opmode);
1550
1551 _rtl92s_phy_set_rfhalt(hw);
1552 udelay(100);
1553}
1554
1555void rtl92se_interrupt_recognized(struct ieee80211_hw *hw, u32 *p_inta,
1556 u32 *p_intb)
1557{
1558 struct rtl_priv *rtlpriv = rtl_priv(hw);
1559 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
1560
1561 *p_inta = rtl_read_dword(rtlpriv, ISR) & rtlpci->irq_mask[0];
1562 rtl_write_dword(rtlpriv, ISR, *p_inta);
1563
1564 *p_intb = rtl_read_dword(rtlpriv, ISR + 4) & rtlpci->irq_mask[1];
1565 rtl_write_dword(rtlpriv, ISR + 4, *p_intb);
1566}
1567
1568void rtl92se_set_beacon_related_registers(struct ieee80211_hw *hw)
1569{
1570 struct rtl_priv *rtlpriv = rtl_priv(hw);
1571 struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
1572 u16 bcntime_cfg = 0;
1573 u16 bcn_cw = 6, bcn_ifs = 0xf;
1574 u16 atim_window = 2;
1575
1576 /* ATIM Window (in unit of TU). */
1577 rtl_write_word(rtlpriv, ATIMWND, atim_window);
1578
1579 /* Beacon interval (in unit of TU). */
1580 rtl_write_word(rtlpriv, BCN_INTERVAL, mac->beacon_interval);
1581
1582 /* DrvErlyInt (in unit of TU). (Time to send
1583 * interrupt to notify driver to change
1584 * beacon content) */
1585 rtl_write_word(rtlpriv, BCN_DRV_EARLY_INT, 10 << 4);
1586
1587 /* BcnDMATIM(in unit of us). Indicates the
1588 * time before TBTT to perform beacon queue DMA */
1589 rtl_write_word(rtlpriv, BCN_DMATIME, 256);
1590
1591 /* Force beacon frame transmission even
1592 * after receiving beacon frame from
1593 * other ad hoc STA */
1594 rtl_write_byte(rtlpriv, BCN_ERR_THRESH, 100);
1595
1596 /* Beacon Time Configuration */
1597 if (mac->opmode == NL80211_IFTYPE_ADHOC)
1598 bcntime_cfg |= (bcn_cw << BCN_TCFG_CW_SHIFT);
1599
1600 /* TODO: bcn_ifs may required to be changed on ASIC */
1601 bcntime_cfg |= bcn_ifs << BCN_TCFG_IFS;
1602
1603 /*for beacon changed */
1604 rtl92s_phy_set_beacon_hwreg(hw, mac->beacon_interval);
1605}
1606
1607void rtl92se_set_beacon_interval(struct ieee80211_hw *hw)
1608{
1609 struct rtl_priv *rtlpriv = rtl_priv(hw);
1610 struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
1611 u16 bcn_interval = mac->beacon_interval;
1612
1613 /* Beacon interval (in unit of TU). */
1614 rtl_write_word(rtlpriv, BCN_INTERVAL, bcn_interval);
1615 /* 2008.10.24 added by tynli for beacon changed. */
1616 rtl92s_phy_set_beacon_hwreg(hw, bcn_interval);
1617}
1618
1619void rtl92se_update_interrupt_mask(struct ieee80211_hw *hw,
1620 u32 add_msr, u32 rm_msr)
1621{
1622 struct rtl_priv *rtlpriv = rtl_priv(hw);
1623 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
1624
f30d7507
JP		 1625 RT_TRACE(rtlpriv, COMP_INTR, DBG_LOUD, "add_msr:%x, rm_msr:%x\n",
1626 add_msr, rm_msr);
24284531
CL		 1627
1628 if (add_msr)
1629 rtlpci->irq_mask[0] |= add_msr;
1630
1631 if (rm_msr)
1632 rtlpci->irq_mask[0] &= (~rm_msr);
1633
1634 rtl92se_disable_interrupt(hw);
1635 rtl92se_enable_interrupt(hw);
1636}
1637
1638static void _rtl8192se_get_IC_Inferiority(struct ieee80211_hw *hw)
1639{
1640 struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
1641 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
1642 u8 efuse_id;
1643
1644 rtlhal->ic_class = IC_INFERIORITY_A;
1645
1646 /* Only retrieving while using EFUSE. */
1647 if ((rtlefuse->epromtype == EEPROM_BOOT_EFUSE) &&
1648 !rtlefuse->autoload_failflag) {
1649 efuse_id = efuse_read_1byte(hw, EFUSE_IC_ID_OFFSET);
1650
1651 if (efuse_id == 0xfe)
1652 rtlhal->ic_class = IC_INFERIORITY_B;
1653 }
1654}
1655
1656static void _rtl92se_read_adapter_info(struct ieee80211_hw *hw)
1657{
1658 struct rtl_priv *rtlpriv = rtl_priv(hw);
1659 struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
1660 struct rtl_phy *rtlphy = &(rtlpriv->phy);
1661 u16 i, usvalue;
1662 u16 eeprom_id;
1663 u8 tempval;
1664 u8 hwinfo[HWSET_MAX_SIZE_92S];
1665 u8 rf_path, index;
1666
1667 if (rtlefuse->epromtype == EEPROM_93C46) {
1668 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
f30d7507 1669 "RTL819X Not boot from eeprom, check it !!\n");
24284531
CL		 1670 } else if (rtlefuse->epromtype == EEPROM_BOOT_EFUSE) {
1671 rtl_efuse_shadow_map_update(hw);
1672
1673 memcpy((void *)hwinfo, (void *)
1674 &rtlefuse->efuse_map[EFUSE_INIT_MAP][0],
1675 HWSET_MAX_SIZE_92S);
1676 }
1677
af08687b 1678 RT_PRINT_DATA(rtlpriv, COMP_INIT, DBG_DMESG, "MAP",
24284531
CL		 1679 hwinfo, HWSET_MAX_SIZE_92S);
1680
1681 eeprom_id = *((u16 *)&hwinfo[0]);
1682 if (eeprom_id != RTL8190_EEPROM_ID) {
1683 RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING,
f30d7507 1684 "EEPROM ID(%#x) is invalid!!\n", eeprom_id);
24284531
CL		 1685 rtlefuse->autoload_failflag = true;
1686 } else {
f30d7507 1687 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, "Autoload OK\n");
24284531
CL		 1688 rtlefuse->autoload_failflag = false;
1689 }
1690
e10542c4 1691 if (rtlefuse->autoload_failflag)
24284531
CL		 1692 return;
1693
1694 _rtl8192se_get_IC_Inferiority(hw);
1695
1696 /* Read IC Version && Channel Plan */
1697 /* VID, DID SE 0xA-D */
1698 rtlefuse->eeprom_vid = *(u16 *)&hwinfo[EEPROM_VID];
1699 rtlefuse->eeprom_did = *(u16 *)&hwinfo[EEPROM_DID];
1700 rtlefuse->eeprom_svid = *(u16 *)&hwinfo[EEPROM_SVID];
1701 rtlefuse->eeprom_smid = *(u16 *)&hwinfo[EEPROM_SMID];
1702 rtlefuse->eeprom_version = *(u16 *)&hwinfo[EEPROM_VERSION];
1703
1704 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
f30d7507 1705 "EEPROMId = 0x%4x\n", eeprom_id);
24284531 1706 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
f30d7507 1707 "EEPROM VID = 0x%4x\n", rtlefuse->eeprom_vid);
24284531 1708 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
f30d7507 1709 "EEPROM DID = 0x%4x\n", rtlefuse->eeprom_did);
24284531 1710 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
f30d7507 1711 "EEPROM SVID = 0x%4x\n", rtlefuse->eeprom_svid);
24284531 1712 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
f30d7507 1713 "EEPROM SMID = 0x%4x\n", rtlefuse->eeprom_smid);
24284531
CL		 1714
1715 for (i = 0; i < 6; i += 2) {
1716 usvalue = *(u16 *)&hwinfo[EEPROM_MAC_ADDR + i];
1717 *((u16 *) (&rtlefuse->dev_addr[i])) = usvalue;
1718 }
1719
1720 for (i = 0; i < 6; i++)
1721 rtl_write_byte(rtlpriv, MACIDR0 + i, rtlefuse->dev_addr[i]);
1722
f30d7507 1723 RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG, "%pM\n", rtlefuse->dev_addr);
24284531
CL		 1724
1725 /* Get Tx Power Level by Channel */
1726 /* Read Tx power of Channel 1 ~ 14 from EEPROM. */
1727 /* 92S suupport RF A & B */
1728 for (rf_path = 0; rf_path < 2; rf_path++) {
1729 for (i = 0; i < 3; i++) {
1730 /* Read CCK RF A & B Tx power */
1731 rtlefuse->eeprom_chnlarea_txpwr_cck[rf_path][i] =
1732 hwinfo[EEPROM_TXPOWERBASE + rf_path * 3 + i];
1733
1734 /* Read OFDM RF A & B Tx power for 1T */
1735 rtlefuse->eeprom_chnlarea_txpwr_ht40_1s[rf_path][i] =
1736 hwinfo[EEPROM_TXPOWERBASE + 6 + rf_path * 3 + i];
1737
1738 /* Read OFDM RF A & B Tx power for 2T */
da17fcff 1739 rtlefuse->eprom_chnl_txpwr_ht40_2sdf[rf_path][i]
24284531
CL		 1740 = hwinfo[EEPROM_TXPOWERBASE + 12 +
1741 rf_path * 3 + i];
1742 }
1743 }
1744
1745 for (rf_path = 0; rf_path < 2; rf_path++)
1746 for (i = 0; i < 3; i++)
1747 RTPRINT(rtlpriv, FINIT, INIT_EEPROM,
4c48869f
JP		 1748 "RF(%d) EEPROM CCK Area(%d) = 0x%x\n",
1749 rf_path, i,
1750 rtlefuse->eeprom_chnlarea_txpwr_cck
1751 [rf_path][i]);
24284531
CL		 1752 for (rf_path = 0; rf_path < 2; rf_path++)
1753 for (i = 0; i < 3; i++)
1754 RTPRINT(rtlpriv, FINIT, INIT_EEPROM,
4c48869f
JP		 1755 "RF(%d) EEPROM HT40 1S Area(%d) = 0x%x\n",
1756 rf_path, i,
1757 rtlefuse->eeprom_chnlarea_txpwr_ht40_1s
1758 [rf_path][i]);
24284531
CL		 1759 for (rf_path = 0; rf_path < 2; rf_path++)
1760 for (i = 0; i < 3; i++)
1761 RTPRINT(rtlpriv, FINIT, INIT_EEPROM,
4c48869f
JP		 1762 "RF(%d) EEPROM HT40 2S Diff Area(%d) = 0x%x\n",
1763 rf_path, i,
da17fcff 1764 rtlefuse->eprom_chnl_txpwr_ht40_2sdf
4c48869f 1765 [rf_path][i]);
24284531
CL		 1766
1767 for (rf_path = 0; rf_path < 2; rf_path++) {
1768
1769 /* Assign dedicated channel tx power */
1770 for (i = 0; i < 14; i++) {
1771 /* channel 1~3 use the same Tx Power Level. */
1772 if (i < 3)
1773 index = 0;
1774 /* Channel 4-8 */
1775 else if (i < 8)
1776 index = 1;
1777 /* Channel 9-14 */
1778 else
1779 index = 2;
1780
1781 /* Record A & B CCK /OFDM - 1T/2T Channel area
1782 * tx power */
1783 rtlefuse->txpwrlevel_cck[rf_path][i] =
1784 rtlefuse->eeprom_chnlarea_txpwr_cck
1785 [rf_path][index];
1786 rtlefuse->txpwrlevel_ht40_1s[rf_path][i] =
1787 rtlefuse->eeprom_chnlarea_txpwr_ht40_1s
1788 [rf_path][index];
1789 rtlefuse->txpwrlevel_ht40_2s[rf_path][i] =
da17fcff 1790 rtlefuse->eprom_chnl_txpwr_ht40_2sdf
24284531
CL		 1791 [rf_path][index];
1792 }
1793
1794 for (i = 0; i < 14; i++) {
e6deaf81 1795 RTPRINT(rtlpriv, FINIT, INIT_TXPOWER,
4c48869f
JP		 1796 "RF(%d)-Ch(%d) [CCK / HT40_1S / HT40_2S] = [0x%x / 0x%x / 0x%x]\n",
1797 rf_path, i,
1798 rtlefuse->txpwrlevel_cck[rf_path][i],
1799 rtlefuse->txpwrlevel_ht40_1s[rf_path][i],
1800 rtlefuse->txpwrlevel_ht40_2s[rf_path][i]);
24284531
CL		 1801 }
1802 }
1803
1804 for (rf_path = 0; rf_path < 2; rf_path++) {
1805 for (i = 0; i < 3; i++) {
1806 /* Read Power diff limit. */
1807 rtlefuse->eeprom_pwrgroup[rf_path][i] =
1808 hwinfo[EEPROM_TXPWRGROUP + rf_path * 3 + i];
1809 }
1810 }
1811
1812 for (rf_path = 0; rf_path < 2; rf_path++) {
1813 /* Fill Pwr group */
1814 for (i = 0; i < 14; i++) {
1815 /* Chanel 1-3 */
1816 if (i < 3)
1817 index = 0;
1818 /* Channel 4-8 */
1819 else if (i < 8)
1820 index = 1;
1821 /* Channel 9-13 */
1822 else
1823 index = 2;
1824
1825 rtlefuse->pwrgroup_ht20[rf_path][i] =
1826 (rtlefuse->eeprom_pwrgroup[rf_path][index] &
1827 0xf);
1828 rtlefuse->pwrgroup_ht40[rf_path][i] =
1829 ((rtlefuse->eeprom_pwrgroup[rf_path][index] &
1830 0xf0) >> 4);
1831
e6deaf81 1832 RTPRINT(rtlpriv, FINIT, INIT_TXPOWER,
4c48869f
JP		 1833 "RF-%d pwrgroup_ht20[%d] = 0x%x\n",
1834 rf_path, i,
1835 rtlefuse->pwrgroup_ht20[rf_path][i]);
e6deaf81 1836 RTPRINT(rtlpriv, FINIT, INIT_TXPOWER,
4c48869f
JP		 1837 "RF-%d pwrgroup_ht40[%d] = 0x%x\n",
1838 rf_path, i,
1839 rtlefuse->pwrgroup_ht40[rf_path][i]);
24284531
CL		 1840 }
1841 }
1842
1843 for (i = 0; i < 14; i++) {
1844 /* Read tx power difference between HT OFDM 20/40 MHZ */
1845 /* channel 1-3 */
1846 if (i < 3)
1847 index = 0;
1848 /* Channel 4-8 */
1849 else if (i < 8)
1850 index = 1;
1851 /* Channel 9-14 */
1852 else
1853 index = 2;
1854
2c208890 1855 tempval = hwinfo[EEPROM_TX_PWR_HT20_DIFF + index] & 0xff;
24284531
CL		 1856 rtlefuse->txpwr_ht20diff[RF90_PATH_A][i] = (tempval & 0xF);
1857 rtlefuse->txpwr_ht20diff[RF90_PATH_B][i] =
1858 ((tempval >> 4) & 0xF);
1859
1860 /* Read OFDM<->HT tx power diff */
1861 /* Channel 1-3 */
1862 if (i < 3)
1863 index = 0;
1864 /* Channel 4-8 */
1865 else if (i < 8)
1866 index = 0x11;
1867 /* Channel 9-14 */
1868 else
1869 index = 1;
1870
2c208890 1871 tempval = hwinfo[EEPROM_TX_PWR_OFDM_DIFF + index] & 0xff;
24284531
CL		 1872 rtlefuse->txpwr_legacyhtdiff[RF90_PATH_A][i] =
1873 (tempval & 0xF);
1874 rtlefuse->txpwr_legacyhtdiff[RF90_PATH_B][i] =
1875 ((tempval >> 4) & 0xF);
1876
2c208890 1877 tempval = hwinfo[TX_PWR_SAFETY_CHK];
24284531
CL		 1878 rtlefuse->txpwr_safetyflag = (tempval & 0x01);
1879 }
1880
1881 rtlefuse->eeprom_regulatory = 0;
1882 if (rtlefuse->eeprom_version >= 2) {
1883 /* BIT(0)~2 */
1884 if (rtlefuse->eeprom_version >= 4)
1885 rtlefuse->eeprom_regulatory =
1886 (hwinfo[EEPROM_REGULATORY] & 0x7);
1887 else /* BIT(0) */
1888 rtlefuse->eeprom_regulatory =
1889 (hwinfo[EEPROM_REGULATORY] & 0x1);
1890 }
e6deaf81 1891 RTPRINT(rtlpriv, FINIT, INIT_TXPOWER,
4c48869f 1892 "eeprom_regulatory = 0x%x\n", rtlefuse->eeprom_regulatory);
24284531
CL		 1893
1894 for (i = 0; i < 14; i++)
e6deaf81 1895 RTPRINT(rtlpriv, FINIT, INIT_TXPOWER,
4c48869f
JP		 1896 "RF-A Ht20 to HT40 Diff[%d] = 0x%x\n",
1897 i, rtlefuse->txpwr_ht20diff[RF90_PATH_A][i]);
24284531 1898 for (i = 0; i < 14; i++)
e6deaf81 1899 RTPRINT(rtlpriv, FINIT, INIT_TXPOWER,
4c48869f
JP		 1900 "RF-A Legacy to Ht40 Diff[%d] = 0x%x\n",
1901 i, rtlefuse->txpwr_legacyhtdiff[RF90_PATH_A][i]);
24284531 1902 for (i = 0; i < 14; i++)
e6deaf81 1903 RTPRINT(rtlpriv, FINIT, INIT_TXPOWER,
4c48869f
JP		 1904 "RF-B Ht20 to HT40 Diff[%d] = 0x%x\n",
1905 i, rtlefuse->txpwr_ht20diff[RF90_PATH_B][i]);
24284531 1906 for (i = 0; i < 14; i++)
e6deaf81 1907 RTPRINT(rtlpriv, FINIT, INIT_TXPOWER,
4c48869f
JP		 1908 "RF-B Legacy to HT40 Diff[%d] = 0x%x\n",
1909 i, rtlefuse->txpwr_legacyhtdiff[RF90_PATH_B][i]);
24284531 1910
e6deaf81 1911 RTPRINT(rtlpriv, FINIT, INIT_TXPOWER,
4c48869f 1912 "TxPwrSafetyFlag = %d\n", rtlefuse->txpwr_safetyflag);
24284531
CL		 1913
1914 /* Read RF-indication and Tx Power gain
1915 * index diff of legacy to HT OFDM rate. */
2c208890 1916 tempval = hwinfo[EEPROM_RFIND_POWERDIFF] & 0xff;
24284531
CL		 1917 rtlefuse->eeprom_txpowerdiff = tempval;
1918 rtlefuse->legacy_httxpowerdiff =
1919 rtlefuse->txpwr_legacyhtdiff[RF90_PATH_A][0];
1920
e6deaf81 1921 RTPRINT(rtlpriv, FINIT, INIT_TXPOWER,
4c48869f 1922 "TxPowerDiff = %#x\n", rtlefuse->eeprom_txpowerdiff);
24284531
CL		 1923
1924 /* Get TSSI value for each path. */
1925 usvalue = *(u16 *)&hwinfo[EEPROM_TSSI_A];
1926 rtlefuse->eeprom_tssi[RF90_PATH_A] = (u8)((usvalue & 0xff00) >> 8);
2c208890 1927 usvalue = hwinfo[EEPROM_TSSI_B];
24284531
CL		 1928 rtlefuse->eeprom_tssi[RF90_PATH_B] = (u8)(usvalue & 0xff);
1929
e6deaf81 1930 RTPRINT(rtlpriv, FINIT, INIT_TXPOWER, "TSSI_A = 0x%x, TSSI_B = 0x%x\n",
4c48869f
JP		 1931 rtlefuse->eeprom_tssi[RF90_PATH_A],
1932 rtlefuse->eeprom_tssi[RF90_PATH_B]);
24284531
CL		 1933
1934 /* Read antenna tx power offset of B/C/D to A from EEPROM */
1935 /* and read ThermalMeter from EEPROM */
2c208890 1936 tempval = hwinfo[EEPROM_THERMALMETER];
24284531 1937 rtlefuse->eeprom_thermalmeter = tempval;
e6deaf81 1938 RTPRINT(rtlpriv, FINIT, INIT_TXPOWER,
4c48869f 1939 "thermalmeter = 0x%x\n", rtlefuse->eeprom_thermalmeter);
24284531
CL		 1940
1941 /* ThermalMeter, BIT(0)~3 for RFIC1, BIT(4)~7 for RFIC2 */
1942 rtlefuse->thermalmeter[0] = (rtlefuse->eeprom_thermalmeter & 0x1f);
1943 rtlefuse->tssi_13dbm = rtlefuse->eeprom_thermalmeter * 100;
1944
1945 /* Read CrystalCap from EEPROM */
2c208890 1946 tempval = hwinfo[EEPROM_CRYSTALCAP] >> 4;
24284531
CL		 1947 rtlefuse->eeprom_crystalcap = tempval;
1948 /* CrystalCap, BIT(12)~15 */
1949 rtlefuse->crystalcap = rtlefuse->eeprom_crystalcap;
1950
1951 /* Read IC Version && Channel Plan */
1952 /* Version ID, Channel plan */
2c208890 1953 rtlefuse->eeprom_channelplan = hwinfo[EEPROM_CHANNELPLAN];
24284531 1954 rtlefuse->txpwr_fromeprom = true;
e6deaf81 1955 RTPRINT(rtlpriv, FINIT, INIT_TXPOWER,
4c48869f 1956 "EEPROM ChannelPlan = 0x%4x\n", rtlefuse->eeprom_channelplan);
24284531
CL		 1957
1958 /* Read Customer ID or Board Type!!! */
2c208890 1959 tempval = hwinfo[EEPROM_BOARDTYPE];
24284531
CL		 1960 /* Change RF type definition */
1961 if (tempval == 0)
1962 rtlphy->rf_type = RF_2T2R;
1963 else if (tempval == 1)
1964 rtlphy->rf_type = RF_1T2R;
1965 else if (tempval == 2)
1966 rtlphy->rf_type = RF_1T2R;
1967 else if (tempval == 3)
1968 rtlphy->rf_type = RF_1T1R;
1969
1970 /* 1T2R but 1SS (1x1 receive combining) */
1971 rtlefuse->b1x1_recvcombine = false;
1972 if (rtlphy->rf_type == RF_1T2R) {
1973 tempval = rtl_read_byte(rtlpriv, 0x07);
1974 if (!(tempval & BIT(0))) {
1975 rtlefuse->b1x1_recvcombine = true;
1976 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
f30d7507 1977 "RF_TYPE=1T2R but only 1SS\n");
24284531
CL		 1978 }
1979 }
1980 rtlefuse->b1ss_support = rtlefuse->b1x1_recvcombine;
2c208890 1981 rtlefuse->eeprom_oemid = *&hwinfo[EEPROM_CUSTOMID];
24284531 1982
f30d7507
JP		 1983 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, "EEPROM Customer ID: 0x%2x",
1984 rtlefuse->eeprom_oemid);
24284531
CL		 1985
1986 /* set channel paln to world wide 13 */
1987 rtlefuse->channel_plan = COUNTRY_CODE_WORLD_WIDE_13;
1988}
1989
1990void rtl92se_read_eeprom_info(struct ieee80211_hw *hw)
1991{
1992 struct rtl_priv *rtlpriv = rtl_priv(hw);
1993 struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
1994 u8 tmp_u1b = 0;
1995
1996 tmp_u1b = rtl_read_byte(rtlpriv, EPROM_CMD);
1997
1998 if (tmp_u1b & BIT(4)) {
f30d7507 1999 RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG, "Boot from EEPROM\n");
24284531
CL		 2000 rtlefuse->epromtype = EEPROM_93C46;
2001 } else {
f30d7507 2002 RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG, "Boot from EFUSE\n");
24284531
CL		 2003 rtlefuse->epromtype = EEPROM_BOOT_EFUSE;
2004 }
2005
2006 if (tmp_u1b & BIT(5)) {
f30d7507 2007 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, "Autoload OK\n");
24284531
CL		 2008 rtlefuse->autoload_failflag = false;
2009 _rtl92se_read_adapter_info(hw);
2010 } else {
f30d7507 2011 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG, "Autoload ERR!!\n");
24284531
CL		 2012 rtlefuse->autoload_failflag = true;
2013 }
2014}
2015
2016static void rtl92se_update_hal_rate_table(struct ieee80211_hw *hw,
2017 struct ieee80211_sta *sta)
2018{
2019 struct rtl_priv *rtlpriv = rtl_priv(hw);
2020 struct rtl_phy *rtlphy = &(rtlpriv->phy);
2021 struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
2022 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
2023 u32 ratr_value;
2024 u8 ratr_index = 0;
2025 u8 nmode = mac->ht_enable;
2026 u8 mimo_ps = IEEE80211_SMPS_OFF;
2027 u16 shortgi_rate = 0;
2028 u32 tmp_ratr_value = 0;
2029 u8 curtxbw_40mhz = mac->bw_40;
2030 u8 curshortgi_40mhz = (sta->ht_cap.cap & IEEE80211_HT_CAP_SGI_40) ?
2031 1 : 0;
2032 u8 curshortgi_20mhz = (sta->ht_cap.cap & IEEE80211_HT_CAP_SGI_20) ?
2033 1 : 0;
2034 enum wireless_mode wirelessmode = mac->mode;
2035
2036 if (rtlhal->current_bandtype == BAND_ON_5G)
2037 ratr_value = sta->supp_rates[1] << 4;
2038 else
2039 ratr_value = sta->supp_rates[0];
2455c92c
LF		 2040 if (mac->opmode == NL80211_IFTYPE_ADHOC)
2041 ratr_value = 0xfff;
24284531
CL		 2042 ratr_value |= (sta->ht_cap.mcs.rx_mask[1] << 20 |
2043 sta->ht_cap.mcs.rx_mask[0] << 12);
2044 switch (wirelessmode) {
2045 case WIRELESS_MODE_B:
2046 ratr_value &= 0x0000000D;
2047 break;
2048 case WIRELESS_MODE_G:
2049 ratr_value &= 0x00000FF5;
2050 break;
2051 case WIRELESS_MODE_N_24G:
2052 case WIRELESS_MODE_N_5G:
2053 nmode = 1;
2054 if (mimo_ps == IEEE80211_SMPS_STATIC) {
2055 ratr_value &= 0x0007F005;
2056 } else {
2057 u32 ratr_mask;
2058
2059 if (get_rf_type(rtlphy) == RF_1T2R ||
2060 get_rf_type(rtlphy) == RF_1T1R) {
2061 if (curtxbw_40mhz)
2062 ratr_mask = 0x000ff015;
2063 else
2064 ratr_mask = 0x000ff005;
2065 } else {
2066 if (curtxbw_40mhz)
2067 ratr_mask = 0x0f0ff015;
2068 else
2069 ratr_mask = 0x0f0ff005;
2070 }
2071
2072 ratr_value &= ratr_mask;
2073 }
2074 break;
2075 default:
2076 if (rtlphy->rf_type == RF_1T2R)
2077 ratr_value &= 0x000ff0ff;
2078 else
2079 ratr_value &= 0x0f0ff0ff;
2080
2081 break;
2082 }
2083
2084 if (rtlpriv->rtlhal.version >= VERSION_8192S_BCUT)
2085 ratr_value &= 0x0FFFFFFF;
2086 else if (rtlpriv->rtlhal.version == VERSION_8192S_ACUT)
2087 ratr_value &= 0x0FFFFFF0;
2088
2089 if (nmode && ((curtxbw_40mhz &&
2090 curshortgi_40mhz) || (!curtxbw_40mhz &&
2091 curshortgi_20mhz))) {
2092
2093 ratr_value |= 0x10000000;
2094 tmp_ratr_value = (ratr_value >> 12);
2095
2096 for (shortgi_rate = 15; shortgi_rate > 0; shortgi_rate--) {
2097 if ((1 << shortgi_rate) & tmp_ratr_value)
2098 break;
2099 }
2100
2101 shortgi_rate = (shortgi_rate << 12) | (shortgi_rate << 8) |
2102 (shortgi_rate << 4) | (shortgi_rate);
2103
2104 rtl_write_byte(rtlpriv, SG_RATE, shortgi_rate);
2105 }
2106
2107 rtl_write_dword(rtlpriv, ARFR0 + ratr_index * 4, ratr_value);
2108 if (ratr_value & 0xfffff000)
2109 rtl92s_phy_set_fw_cmd(hw, FW_CMD_RA_REFRESH_N);
2110 else
2111 rtl92s_phy_set_fw_cmd(hw, FW_CMD_RA_REFRESH_BG);
2112
f30d7507
JP		 2113 RT_TRACE(rtlpriv, COMP_RATR, DBG_DMESG, "%x\n",
2114 rtl_read_dword(rtlpriv, ARFR0));
24284531
CL		 2115}
2116
2117static void rtl92se_update_hal_rate_mask(struct ieee80211_hw *hw,
2118 struct ieee80211_sta *sta,
2119 u8 rssi_level)
2120{
2121 struct rtl_priv *rtlpriv = rtl_priv(hw);
2122 struct rtl_phy *rtlphy = &(rtlpriv->phy);
2123 struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
2124 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
2125 struct rtl_sta_info *sta_entry = NULL;
2126 u32 ratr_bitmap;
2127 u8 ratr_index = 0;
e1a0c6b3 2128 u8 curtxbw_40mhz = (sta->bandwidth >= IEEE80211_STA_RX_BW_40) ? 1 : 0;
24284531
CL		 2129 u8 curshortgi_40mhz = (sta->ht_cap.cap & IEEE80211_HT_CAP_SGI_40) ?
2130 1 : 0;
2131 u8 curshortgi_20mhz = (sta->ht_cap.cap & IEEE80211_HT_CAP_SGI_20) ?
2132 1 : 0;
2133 enum wireless_mode wirelessmode = 0;
2134 bool shortgi = false;
2135 u32 ratr_value = 0;
2136 u8 shortgi_rate = 0;
2137 u32 mask = 0;
2138 u32 band = 0;
2139 bool bmulticast = false;
2140 u8 macid = 0;
2141 u8 mimo_ps = IEEE80211_SMPS_OFF;
2142
2143 sta_entry = (struct rtl_sta_info *) sta->drv_priv;
2144 wirelessmode = sta_entry->wireless_mode;
2145 if (mac->opmode == NL80211_IFTYPE_STATION)
2146 curtxbw_40mhz = mac->bw_40;
2147 else if (mac->opmode == NL80211_IFTYPE_AP ||
2148 mac->opmode == NL80211_IFTYPE_ADHOC)
2149 macid = sta->aid + 1;
2150
2151 if (rtlhal->current_bandtype == BAND_ON_5G)
2152 ratr_bitmap = sta->supp_rates[1] << 4;
2153 else
2154 ratr_bitmap = sta->supp_rates[0];
2455c92c
LF		 2155 if (mac->opmode == NL80211_IFTYPE_ADHOC)
2156 ratr_bitmap = 0xfff;
24284531
CL		 2157 ratr_bitmap |= (sta->ht_cap.mcs.rx_mask[1] << 20 |
2158 sta->ht_cap.mcs.rx_mask[0] << 12);
2159 switch (wirelessmode) {
2160 case WIRELESS_MODE_B:
2161 band |= WIRELESS_11B;
2162 ratr_index = RATR_INX_WIRELESS_B;
2163 if (ratr_bitmap & 0x0000000c)
2164 ratr_bitmap &= 0x0000000d;
2165 else
2166 ratr_bitmap &= 0x0000000f;
2167 break;
2168 case WIRELESS_MODE_G:
2169 band |= (WIRELESS_11G | WIRELESS_11B);
2170 ratr_index = RATR_INX_WIRELESS_GB;
2171
2172 if (rssi_level == 1)
2173 ratr_bitmap &= 0x00000f00;
2174 else if (rssi_level == 2)
2175 ratr_bitmap &= 0x00000ff0;
2176 else
2177 ratr_bitmap &= 0x00000ff5;
2178 break;
2179 case WIRELESS_MODE_A:
2180 band |= WIRELESS_11A;
2181 ratr_index = RATR_INX_WIRELESS_A;
2182 ratr_bitmap &= 0x00000ff0;
2183 break;
2184 case WIRELESS_MODE_N_24G:
2185 case WIRELESS_MODE_N_5G:
2186 band |= (WIRELESS_11N | WIRELESS_11G | WIRELESS_11B);
2187 ratr_index = RATR_INX_WIRELESS_NGB;
2188
2189 if (mimo_ps == IEEE80211_SMPS_STATIC) {
2190 if (rssi_level == 1)
2191 ratr_bitmap &= 0x00070000;
2192 else if (rssi_level == 2)
2193 ratr_bitmap &= 0x0007f000;
2194 else
2195 ratr_bitmap &= 0x0007f005;
2196 } else {
2197 if (rtlphy->rf_type == RF_1T2R ||
2198 rtlphy->rf_type == RF_1T1R) {
2199 if (rssi_level == 1) {
2200 ratr_bitmap &= 0x000f0000;
2201 } else if (rssi_level == 3) {
2202 ratr_bitmap &= 0x000fc000;
2203 } else if (rssi_level == 5) {
2204 ratr_bitmap &= 0x000ff000;
2205 } else {
2206 if (curtxbw_40mhz)
2207 ratr_bitmap &= 0x000ff015;
2208 else
2209 ratr_bitmap &= 0x000ff005;
2210 }
2211 } else {
2212 if (rssi_level == 1) {
2213 ratr_bitmap &= 0x0f8f0000;
2214 } else if (rssi_level == 3) {
2215 ratr_bitmap &= 0x0f8fc000;
2216 } else if (rssi_level == 5) {
2217 ratr_bitmap &= 0x0f8ff000;
2218 } else {
2219 if (curtxbw_40mhz)
2220 ratr_bitmap &= 0x0f8ff015;
2221 else
2222 ratr_bitmap &= 0x0f8ff005;
2223 }
2224 }
2225 }
2226
2227 if ((curtxbw_40mhz && curshortgi_40mhz) ||
2228 (!curtxbw_40mhz && curshortgi_20mhz)) {
2229 if (macid == 0)
2230 shortgi = true;
2231 else if (macid == 1)
2232 shortgi = false;
2233 }
2234 break;
2235 default:
2236 band |= (WIRELESS_11N | WIRELESS_11G | WIRELESS_11B);
2237 ratr_index = RATR_INX_WIRELESS_NGB;
2238
2239 if (rtlphy->rf_type == RF_1T2R)
2240 ratr_bitmap &= 0x000ff0ff;
2241 else
2242 ratr_bitmap &= 0x0f8ff0ff;
2243 break;
2244 }
2455c92c 2245 sta_entry->ratr_index = ratr_index;
24284531
CL		 2246
2247 if (rtlpriv->rtlhal.version >= VERSION_8192S_BCUT)
2248 ratr_bitmap &= 0x0FFFFFFF;
2249 else if (rtlpriv->rtlhal.version == VERSION_8192S_ACUT)
2250 ratr_bitmap &= 0x0FFFFFF0;
2251
2252 if (shortgi) {
2253 ratr_bitmap |= 0x10000000;
2254 /* Get MAX MCS available. */
2255 ratr_value = (ratr_bitmap >> 12);
2256 for (shortgi_rate = 15; shortgi_rate > 0; shortgi_rate--) {
2257 if ((1 << shortgi_rate) & ratr_value)
2258 break;
2259 }
2260
2261 shortgi_rate = (shortgi_rate << 12) | (shortgi_rate << 8) |
2262 (shortgi_rate << 4) | (shortgi_rate);
2263 rtl_write_byte(rtlpriv, SG_RATE, shortgi_rate);
2264 }
2265
2266 mask |= (bmulticast ? 1 : 0) << 9 | (macid & 0x1f) << 4 | (band & 0xf);
2267
f30d7507
JP		 2268 RT_TRACE(rtlpriv, COMP_RATR, DBG_TRACE, "mask = %x, bitmap = %x\n",
2269 mask, ratr_bitmap);
24284531
CL		 2270 rtl_write_dword(rtlpriv, 0x2c4, ratr_bitmap);
2271 rtl_write_dword(rtlpriv, WFM5, (FW_RA_UPDATE_MASK | (mask << 8)));
2272
2273 if (macid != 0)
2274 sta_entry->ratr_index = ratr_index;
2275}
2276
2277void rtl92se_update_hal_rate_tbl(struct ieee80211_hw *hw,
2278 struct ieee80211_sta *sta, u8 rssi_level)
2279{
2280 struct rtl_priv *rtlpriv = rtl_priv(hw);
2281
2282 if (rtlpriv->dm.useramask)
2283 rtl92se_update_hal_rate_mask(hw, sta, rssi_level);
2284 else
2285 rtl92se_update_hal_rate_table(hw, sta);
2286}
2287
2288void rtl92se_update_channel_access_setting(struct ieee80211_hw *hw)
2289{
2290 struct rtl_priv *rtlpriv = rtl_priv(hw);
2291 struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
2292 u16 sifs_timer;
2293
2294 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_SLOT_TIME,
2c208890 2295 &mac->slot_time);
24284531
CL		 2296 sifs_timer = 0x0e0e;
2297 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_SIFS, (u8 *)&sifs_timer);
2298
2299}
2300
2301/* this ifunction is for RFKILL, it's different with windows,
2302 * because UI will disable wireless when GPIO Radio Off.
2303 * And here we not check or Disable/Enable ASPM like windows*/
2304bool rtl92se_gpio_radio_on_off_checking(struct ieee80211_hw *hw, u8 *valid)
2305{
2306 struct rtl_priv *rtlpriv = rtl_priv(hw);
2307 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
2308 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
78d57372 2309 enum rf_pwrstate rfpwr_toset /*, cur_rfstate */;
24284531
CL		 2310 unsigned long flag = 0;
2311 bool actuallyset = false;
2312 bool turnonbypowerdomain = false;
2313
2314 /* just 8191se can check gpio before firstup, 92c/92d have fixed it */
2315 if ((rtlpci->up_first_time == 1) || (rtlpci->being_init_adapter))
2316 return false;
2317
2318 if (ppsc->swrf_processing)
2319 return false;
2320
2321 spin_lock_irqsave(&rtlpriv->locks.rf_ps_lock, flag);
2322 if (ppsc->rfchange_inprogress) {
2323 spin_unlock_irqrestore(&rtlpriv->locks.rf_ps_lock, flag);
2324 return false;
2325 } else {
2326 ppsc->rfchange_inprogress = true;
2327 spin_unlock_irqrestore(&rtlpriv->locks.rf_ps_lock, flag);
2328 }
2329
78d57372 2330 /* cur_rfstate = ppsc->rfpwr_state;*/
24284531
CL		 2331
2332 /* because after _rtl92s_phy_set_rfhalt, all power
2333 * closed, so we must open some power for GPIO check,
2334 * or we will always check GPIO RFOFF here,
2335 * And we should close power after GPIO check */
2336 if (RT_IN_PS_LEVEL(ppsc, RT_RF_OFF_LEVL_HALT_NIC)) {
2337 _rtl92se_power_domain_init(hw);
2338 turnonbypowerdomain = true;
2339 }
2340
2341 rfpwr_toset = _rtl92se_rf_onoff_detect(hw);
2342
e10542c4 2343 if ((ppsc->hwradiooff) && (rfpwr_toset == ERFON)) {
24284531 2344 RT_TRACE(rtlpriv, COMP_RF, DBG_DMESG,
f30d7507 2345 "RFKILL-HW Radio ON, RF ON\n");
24284531
CL		 2346
2347 rfpwr_toset = ERFON;
2348 ppsc->hwradiooff = false;
2349 actuallyset = true;
23677ce3 2350 } else if ((!ppsc->hwradiooff) && (rfpwr_toset == ERFOFF)) {
f30d7507
JP		 2351 RT_TRACE(rtlpriv, COMP_RF,
2352 DBG_DMESG, "RFKILL-HW Radio OFF, RF OFF\n");
24284531
CL		 2353
2354 rfpwr_toset = ERFOFF;
2355 ppsc->hwradiooff = true;
2356 actuallyset = true;
2357 }
2358
2359 if (actuallyset) {
2360 spin_lock_irqsave(&rtlpriv->locks.rf_ps_lock, flag);
2361 ppsc->rfchange_inprogress = false;
2362 spin_unlock_irqrestore(&rtlpriv->locks.rf_ps_lock, flag);
2363
2364 /* this not include ifconfig wlan0 down case */
2365 /* } else if (rfpwr_toset == ERFOFF || cur_rfstate == ERFOFF) { */
2366 } else {
2367 /* because power_domain_init may be happen when
2368 * _rtl92s_phy_set_rfhalt, this will open some powers
2369 * and cause current increasing about 40 mA for ips,
2370 * rfoff and ifconfig down, so we set
2371 * _rtl92s_phy_set_rfhalt again here */
2372 if (ppsc->reg_rfps_level & RT_RF_OFF_LEVL_HALT_NIC &&
2373 turnonbypowerdomain) {
2374 _rtl92s_phy_set_rfhalt(hw);
2375 RT_SET_PS_LEVEL(ppsc, RT_RF_OFF_LEVL_HALT_NIC);
2376 }
2377
2378 spin_lock_irqsave(&rtlpriv->locks.rf_ps_lock, flag);
2379 ppsc->rfchange_inprogress = false;
2380 spin_unlock_irqrestore(&rtlpriv->locks.rf_ps_lock, flag);
2381 }
2382
2383 *valid = 1;
2384 return !ppsc->hwradiooff;
2385
2386}
2387
2388/* Is_wepkey just used for WEP used as group & pairwise key
2389 * if pairwise is AES ang group is WEP Is_wepkey == false.*/
2390void rtl92se_set_key(struct ieee80211_hw *hw, u32 key_index, u8 *p_macaddr,
2391 bool is_group, u8 enc_algo, bool is_wepkey, bool clear_all)
2392{
2393 struct rtl_priv *rtlpriv = rtl_priv(hw);
2394 struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
2395 struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
2396 u8 *macaddr = p_macaddr;
2397
2398 u32 entry_id = 0;
2399 bool is_pairwise = false;
2400
2401 static u8 cam_const_addr[4][6] = {
2402 {0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
2403 {0x00, 0x00, 0x00, 0x00, 0x00, 0x01},
2404 {0x00, 0x00, 0x00, 0x00, 0x00, 0x02},
2405 {0x00, 0x00, 0x00, 0x00, 0x00, 0x03}
2406 };
2407 static u8 cam_const_broad[] = {
2408 0xff, 0xff, 0xff, 0xff, 0xff, 0xff
2409 };
2410
2411 if (clear_all) {
2412 u8 idx = 0;
2413 u8 cam_offset = 0;
2414 u8 clear_number = 5;
2415
f30d7507 2416 RT_TRACE(rtlpriv, COMP_SEC, DBG_DMESG, "clear_all\n");
24284531
CL		 2417
2418 for (idx = 0; idx < clear_number; idx++) {
2419 rtl_cam_mark_invalid(hw, cam_offset + idx);
2420 rtl_cam_empty_entry(hw, cam_offset + idx);
2421
2422 if (idx < 5) {
2423 memset(rtlpriv->sec.key_buf[idx], 0,
2424 MAX_KEY_LEN);
2425 rtlpriv->sec.key_len[idx] = 0;
2426 }
2427 }
2428
2429 } else {
2430 switch (enc_algo) {
2431 case WEP40_ENCRYPTION:
2432 enc_algo = CAM_WEP40;
2433 break;
2434 case WEP104_ENCRYPTION:
2435 enc_algo = CAM_WEP104;
2436 break;
2437 case TKIP_ENCRYPTION:
2438 enc_algo = CAM_TKIP;
2439 break;
2440 case AESCCMP_ENCRYPTION:
2441 enc_algo = CAM_AES;
2442 break;
2443 default:
2444 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
f30d7507 2445 "switch case not processed\n");
24284531
CL		 2446 enc_algo = CAM_TKIP;
2447 break;
2448 }
2449
2450 if (is_wepkey || rtlpriv->sec.use_defaultkey) {
2451 macaddr = cam_const_addr[key_index];
2452 entry_id = key_index;
2453 } else {
2454 if (is_group) {
2455 macaddr = cam_const_broad;
2456 entry_id = key_index;
2457 } else {
2458 if (mac->opmode == NL80211_IFTYPE_AP) {
2459 entry_id = rtl_cam_get_free_entry(hw,
2460 p_macaddr);
2461 if (entry_id >= TOTAL_CAM_ENTRY) {
2462 RT_TRACE(rtlpriv,
f30d7507
JP		 2463 COMP_SEC, DBG_EMERG,
2464 "Can not find free hw security cam entry\n");
24284531
CL		 2465 return;
2466 }
2467 } else {
2468 entry_id = CAM_PAIRWISE_KEY_POSITION;
2469 }
2470
2471 key_index = PAIRWISE_KEYIDX;
2472 is_pairwise = true;
2473 }
2474 }
2475
2476 if (rtlpriv->sec.key_len[key_index] == 0) {
2477 RT_TRACE(rtlpriv, COMP_SEC, DBG_DMESG,
f30d7507
JP		 2478 "delete one entry, entry_id is %d\n",
2479 entry_id);
24284531
CL		 2480 if (mac->opmode == NL80211_IFTYPE_AP)
2481 rtl_cam_del_entry(hw, p_macaddr);
2482 rtl_cam_delete_one_entry(hw, p_macaddr, entry_id);
2483 } else {
24284531 2484 RT_TRACE(rtlpriv, COMP_SEC, DBG_DMESG,
f30d7507 2485 "add one entry\n");
24284531 2486 if (is_pairwise) {
24284531 2487 RT_TRACE(rtlpriv, COMP_SEC, DBG_DMESG,
f30d7507 2488 "set Pairwise key\n");
24284531
CL		 2489
2490 rtl_cam_add_one_entry(hw, macaddr, key_index,
2491 entry_id, enc_algo,
2492 CAM_CONFIG_NO_USEDK,
2493 rtlpriv->sec.key_buf[key_index]);
2494 } else {
2495 RT_TRACE(rtlpriv, COMP_SEC, DBG_DMESG,
f30d7507 2496 "set group key\n");
24284531
CL		 2497
2498 if (mac->opmode == NL80211_IFTYPE_ADHOC) {
2499 rtl_cam_add_one_entry(hw,
2500 rtlefuse->dev_addr,
2501 PAIRWISE_KEYIDX,
2502 CAM_PAIRWISE_KEY_POSITION,
2503 enc_algo, CAM_CONFIG_NO_USEDK,
2504 rtlpriv->sec.key_buf[entry_id]);
2505 }
2506
2507 rtl_cam_add_one_entry(hw, macaddr, key_index,
2508 entry_id, enc_algo,
2509 CAM_CONFIG_NO_USEDK,
2510 rtlpriv->sec.key_buf[entry_id]);
2511 }
2512
2513 }
2514 }
2515}
2516
2517void rtl92se_suspend(struct ieee80211_hw *hw)
2518{
2519 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
2520
2521 rtlpci->up_first_time = true;
2522}
2523
2524void rtl92se_resume(struct ieee80211_hw *hw)
2525{
2526 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
2527 u32 val;
2528
2529 pci_read_config_dword(rtlpci->pdev, 0x40, &val);
2530 if ((val & 0x0000ff00) != 0)
2531 pci_write_config_dword(rtlpci->pdev, 0x40,
2532 val & 0xffff00ff);
2533}
2455c92c
LF		 2534
2535/* Turn on AAP (RCR:bit 0) for promicuous mode. */
2536void rtl92se_allow_all_destaddr(struct ieee80211_hw *hw,
2537 bool allow_all_da, bool write_into_reg)
2538{
2539 struct rtl_priv *rtlpriv = rtl_priv(hw);
2540 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
2541
2542 if (allow_all_da) /* Set BIT0 */
2543 rtlpci->receive_config |= RCR_AAP;
2544 else /* Clear BIT0 */
2545 rtlpci->receive_config &= ~RCR_AAP;
2546
2547 if (write_into_reg)
2548 rtl_write_dword(rtlpriv, RCR, rtlpci->receive_config);
2549
2550 RT_TRACE(rtlpriv, COMP_TURBO | COMP_INIT, DBG_LOUD,
2551 "receive_config=0x%08X, write_into_reg=%d\n",
2552 rtlpci->receive_config, write_into_reg);
2553}
Linux kernel - Deliverables
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