projects / deliverable / linux.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
ath9k: Print the correct channel mode
[deliverable/linux.git] / drivers / net / wireless / rtlwifi / rtl8192se / hw.c
CommitLineData
24284531
CL		 1/******************************************************************************
2 *
ca742cd9 3 * Copyright(c) 2009-2012 Realtek Corporation.
24284531
CL		 4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of version 2 of the GNU General Public License as
7 * published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details.
13 *
14 * You should have received a copy of the GNU General Public License along with
15 * this program; if not, write to the Free Software Foundation, Inc.,
16 * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
17 *
18 * The full GNU General Public License is included in this distribution in the
19 * file called LICENSE.
20 *
21 * Contact Information:
22 * wlanfae <wlanfae@realtek.com>
23 * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
24 * Hsinchu 300, Taiwan.
25 *
26 * Larry Finger <Larry.Finger@lwfinger.net>
27 *
28 *****************************************************************************/
29
30#include "../wifi.h"
31#include "../efuse.h"
32#include "../base.h"
33#include "../regd.h"
34#include "../cam.h"
35#include "../ps.h"
36#include "../pci.h"
37#include "reg.h"
38#include "def.h"
39#include "phy.h"
40#include "dm.h"
41#include "fw.h"
42#include "led.h"
43#include "hw.h"
44
45void rtl92se_get_hw_reg(struct ieee80211_hw *hw, u8 variable, u8 *val)
46{
47 struct rtl_priv *rtlpriv = rtl_priv(hw);
48 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
49 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
50
51 switch (variable) {
52 case HW_VAR_RCR: {
53 *((u32 *) (val)) = rtlpci->receive_config;
54 break;
55 }
56 case HW_VAR_RF_STATE: {
57 *((enum rf_pwrstate *)(val)) = ppsc->rfpwr_state;
58 break;
59 }
60 case HW_VAR_FW_PSMODE_STATUS: {
61 *((bool *) (val)) = ppsc->fw_current_inpsmode;
62 break;
63 }
64 case HW_VAR_CORRECT_TSF: {
65 u64 tsf;
66 u32 *ptsf_low = (u32 *)&tsf;
67 u32 *ptsf_high = ((u32 *)&tsf) + 1;
68
69 *ptsf_high = rtl_read_dword(rtlpriv, (TSFR + 4));
70 *ptsf_low = rtl_read_dword(rtlpriv, TSFR);
71
72 *((u64 *) (val)) = tsf;
73
74 break;
75 }
76 case HW_VAR_MRC: {
77 *((bool *)(val)) = rtlpriv->dm.current_mrc_switch;
78 break;
79 }
80 default: {
f30d7507
JP		 81 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
82 "switch case not processed\n");
24284531
CL		 83 break;
84 }
85 }
86}
87
88void rtl92se_set_hw_reg(struct ieee80211_hw *hw, u8 variable, u8 *val)
89{
90 struct rtl_priv *rtlpriv = rtl_priv(hw);
91 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
92 struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
93 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
94 struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
95 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
96
97 switch (variable) {
98 case HW_VAR_ETHER_ADDR:{
99 rtl_write_dword(rtlpriv, IDR0, ((u32 *)(val))[0]);
100 rtl_write_word(rtlpriv, IDR4, ((u16 *)(val + 4))[0]);
101 break;
102 }
103 case HW_VAR_BASIC_RATE:{
104 u16 rate_cfg = ((u16 *) val)[0];
105 u8 rate_index = 0;
106
107 if (rtlhal->version == VERSION_8192S_ACUT)
108 rate_cfg = rate_cfg & 0x150;
109 else
110 rate_cfg = rate_cfg & 0x15f;
111
112 rate_cfg |= 0x01;
113
114 rtl_write_byte(rtlpriv, RRSR, rate_cfg & 0xff);
115 rtl_write_byte(rtlpriv, RRSR + 1,
116 (rate_cfg >> 8) & 0xff);
117
118 while (rate_cfg > 0x1) {
119 rate_cfg = (rate_cfg >> 1);
120 rate_index++;
121 }
122 rtl_write_byte(rtlpriv, INIRTSMCS_SEL, rate_index);
123
124 break;
125 }
126 case HW_VAR_BSSID:{
127 rtl_write_dword(rtlpriv, BSSIDR, ((u32 *)(val))[0]);
128 rtl_write_word(rtlpriv, BSSIDR + 4,
129 ((u16 *)(val + 4))[0]);
130 break;
131 }
132 case HW_VAR_SIFS:{
133 rtl_write_byte(rtlpriv, SIFS_OFDM, val[0]);
134 rtl_write_byte(rtlpriv, SIFS_OFDM + 1, val[1]);
135 break;
136 }
137 case HW_VAR_SLOT_TIME:{
138 u8 e_aci;
139
140 RT_TRACE(rtlpriv, COMP_MLME, DBG_LOUD,
f30d7507 141 "HW_VAR_SLOT_TIME %x\n", val[0]);
24284531
CL		 142
143 rtl_write_byte(rtlpriv, SLOT_TIME, val[0]);
144
145 for (e_aci = 0; e_aci < AC_MAX; e_aci++) {
146 rtlpriv->cfg->ops->set_hw_reg(hw,
147 HW_VAR_AC_PARAM,
148 (u8 *)(&e_aci));
149 }
150 break;
151 }
152 case HW_VAR_ACK_PREAMBLE:{
153 u8 reg_tmp;
154 u8 short_preamble = (bool) (*(u8 *) val);
155 reg_tmp = (mac->cur_40_prime_sc) << 5;
156 if (short_preamble)
157 reg_tmp |= 0x80;
158
159 rtl_write_byte(rtlpriv, RRSR + 2, reg_tmp);
160 break;
161 }
162 case HW_VAR_AMPDU_MIN_SPACE:{
163 u8 min_spacing_to_set;
164 u8 sec_min_space;
165
166 min_spacing_to_set = *((u8 *)val);
167 if (min_spacing_to_set <= 7) {
168 if (rtlpriv->sec.pairwise_enc_algorithm ==
169 NO_ENCRYPTION)
170 sec_min_space = 0;
171 else
172 sec_min_space = 1;
173
174 if (min_spacing_to_set < sec_min_space)
175 min_spacing_to_set = sec_min_space;
176 if (min_spacing_to_set > 5)
177 min_spacing_to_set = 5;
178
179 mac->min_space_cfg =
180 ((mac->min_space_cfg & 0xf8) |
181 min_spacing_to_set);
182
183 *val = min_spacing_to_set;
184
185 RT_TRACE(rtlpriv, COMP_MLME, DBG_LOUD,
f30d7507
JP		 186 "Set HW_VAR_AMPDU_MIN_SPACE: %#x\n",
187 mac->min_space_cfg);
24284531
CL		 188
189 rtl_write_byte(rtlpriv, AMPDU_MIN_SPACE,
190 mac->min_space_cfg);
191 }
192 break;
193 }
194 case HW_VAR_SHORTGI_DENSITY:{
195 u8 density_to_set;
196
197 density_to_set = *((u8 *) val);
198 mac->min_space_cfg = rtlpriv->rtlhal.minspace_cfg;
199 mac->min_space_cfg |= (density_to_set << 3);
200
201 RT_TRACE(rtlpriv, COMP_MLME, DBG_LOUD,
f30d7507
JP		 202 "Set HW_VAR_SHORTGI_DENSITY: %#x\n",
203 mac->min_space_cfg);
24284531
CL		 204
205 rtl_write_byte(rtlpriv, AMPDU_MIN_SPACE,
206 mac->min_space_cfg);
207
208 break;
209 }
210 case HW_VAR_AMPDU_FACTOR:{
211 u8 factor_toset;
212 u8 regtoset;
213 u8 factorlevel[18] = {
214 2, 4, 4, 7, 7, 13, 13,
215 13, 2, 7, 7, 13, 13,
216 15, 15, 15, 15, 0};
217 u8 index = 0;
218
219 factor_toset = *((u8 *) val);
220 if (factor_toset <= 3) {
221 factor_toset = (1 << (factor_toset + 2));
222 if (factor_toset > 0xf)
223 factor_toset = 0xf;
224
225 for (index = 0; index < 17; index++) {
226 if (factorlevel[index] > factor_toset)
227 factorlevel[index] =
228 factor_toset;
229 }
230
231 for (index = 0; index < 8; index++) {
232 regtoset = ((factorlevel[index * 2]) |
233 (factorlevel[index *
234 2 + 1] << 4));
235 rtl_write_byte(rtlpriv,
236 AGGLEN_LMT_L + index,
237 regtoset);
238 }
239
240 regtoset = ((factorlevel[16]) |
241 (factorlevel[17] << 4));
242 rtl_write_byte(rtlpriv, AGGLEN_LMT_H, regtoset);
243
244 RT_TRACE(rtlpriv, COMP_MLME, DBG_LOUD,
f30d7507
JP		 245 "Set HW_VAR_AMPDU_FACTOR: %#x\n",
246 factor_toset);
24284531
CL		 247 }
248 break;
249 }
250 case HW_VAR_AC_PARAM:{
251 u8 e_aci = *((u8 *) val);
252 rtl92s_dm_init_edca_turbo(hw);
253
254 if (rtlpci->acm_method != eAcmWay2_SW)
255 rtlpriv->cfg->ops->set_hw_reg(hw,
256 HW_VAR_ACM_CTRL,
257 (u8 *)(&e_aci));
258 break;
259 }
260 case HW_VAR_ACM_CTRL:{
261 u8 e_aci = *((u8 *) val);
262 union aci_aifsn *p_aci_aifsn = (union aci_aifsn *)(&(
263 mac->ac[0].aifs));
264 u8 acm = p_aci_aifsn->f.acm;
265 u8 acm_ctrl = rtl_read_byte(rtlpriv, AcmHwCtrl);
266
267 acm_ctrl = acm_ctrl | ((rtlpci->acm_method == 2) ?
268 0x0 : 0x1);
269
270 if (acm) {
271 switch (e_aci) {
272 case AC0_BE:
273 acm_ctrl |= AcmHw_BeqEn;
274 break;
275 case AC2_VI:
276 acm_ctrl |= AcmHw_ViqEn;
277 break;
278 case AC3_VO:
279 acm_ctrl |= AcmHw_VoqEn;
280 break;
281 default:
282 RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING,
f30d7507
JP		 283 "HW_VAR_ACM_CTRL acm set failed: eACI is %d\n",
284 acm);
24284531
CL		 285 break;
286 }
287 } else {
288 switch (e_aci) {
289 case AC0_BE:
290 acm_ctrl &= (~AcmHw_BeqEn);
291 break;
292 case AC2_VI:
293 acm_ctrl &= (~AcmHw_ViqEn);
294 break;
295 case AC3_VO:
296 acm_ctrl &= (~AcmHw_BeqEn);
297 break;
298 default:
299 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
f30d7507 300 "switch case not processed\n");
24284531
CL		 301 break;
302 }
303 }
304
305 RT_TRACE(rtlpriv, COMP_QOS, DBG_TRACE,
f30d7507 306 "HW_VAR_ACM_CTRL Write 0x%X\n", acm_ctrl);
24284531
CL		 307 rtl_write_byte(rtlpriv, AcmHwCtrl, acm_ctrl);
308 break;
309 }
310 case HW_VAR_RCR:{
311 rtl_write_dword(rtlpriv, RCR, ((u32 *) (val))[0]);
312 rtlpci->receive_config = ((u32 *) (val))[0];
313 break;
314 }
315 case HW_VAR_RETRY_LIMIT:{
316 u8 retry_limit = ((u8 *) (val))[0];
317
318 rtl_write_word(rtlpriv, RETRY_LIMIT,
319 retry_limit << RETRY_LIMIT_SHORT_SHIFT |
320 retry_limit << RETRY_LIMIT_LONG_SHIFT);
321 break;
322 }
323 case HW_VAR_DUAL_TSF_RST: {
324 break;
325 }
326 case HW_VAR_EFUSE_BYTES: {
327 rtlefuse->efuse_usedbytes = *((u16 *) val);
328 break;
329 }
330 case HW_VAR_EFUSE_USAGE: {
331 rtlefuse->efuse_usedpercentage = *((u8 *) val);
332 break;
333 }
334 case HW_VAR_IO_CMD: {
335 break;
336 }
337 case HW_VAR_WPA_CONFIG: {
338 rtl_write_byte(rtlpriv, REG_SECR, *((u8 *) val));
339 break;
340 }
341 case HW_VAR_SET_RPWM:{
342 break;
343 }
344 case HW_VAR_H2C_FW_PWRMODE:{
345 break;
346 }
347 case HW_VAR_FW_PSMODE_STATUS: {
348 ppsc->fw_current_inpsmode = *((bool *) val);
349 break;
350 }
351 case HW_VAR_H2C_FW_JOINBSSRPT:{
352 break;
353 }
354 case HW_VAR_AID:{
355 break;
356 }
357 case HW_VAR_CORRECT_TSF:{
358 break;
359 }
360 case HW_VAR_MRC: {
361 bool bmrc_toset = *((bool *)val);
362 u8 u1bdata = 0;
363
364 if (bmrc_toset) {
365 rtl_set_bbreg(hw, ROFDM0_TRXPATHENABLE,
366 MASKBYTE0, 0x33);
367 u1bdata = (u8)rtl_get_bbreg(hw,
368 ROFDM1_TRXPATHENABLE,
369 MASKBYTE0);
370 rtl_set_bbreg(hw, ROFDM1_TRXPATHENABLE,
371 MASKBYTE0,
372 ((u1bdata & 0xf0) | 0x03));
373 u1bdata = (u8)rtl_get_bbreg(hw,
374 ROFDM0_TRXPATHENABLE,
375 MASKBYTE1);
376 rtl_set_bbreg(hw, ROFDM0_TRXPATHENABLE,
377 MASKBYTE1,
378 (u1bdata | 0x04));
379
380 /* Update current settings. */
381 rtlpriv->dm.current_mrc_switch = bmrc_toset;
382 } else {
383 rtl_set_bbreg(hw, ROFDM0_TRXPATHENABLE,
384 MASKBYTE0, 0x13);
385 u1bdata = (u8)rtl_get_bbreg(hw,
386 ROFDM1_TRXPATHENABLE,
387 MASKBYTE0);
388 rtl_set_bbreg(hw, ROFDM1_TRXPATHENABLE,
389 MASKBYTE0,
390 ((u1bdata & 0xf0) | 0x01));
391 u1bdata = (u8)rtl_get_bbreg(hw,
392 ROFDM0_TRXPATHENABLE,
393 MASKBYTE1);
394 rtl_set_bbreg(hw, ROFDM0_TRXPATHENABLE,
395 MASKBYTE1, (u1bdata & 0xfb));
396
397 /* Update current settings. */
398 rtlpriv->dm.current_mrc_switch = bmrc_toset;
399 }
400
401 break;
402 }
403 default:
404 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
f30d7507 405 "switch case not processed\n");
24284531
CL		 406 break;
407 }
408
409}
410
411void rtl92se_enable_hw_security_config(struct ieee80211_hw *hw)
412{
413 struct rtl_priv *rtlpriv = rtl_priv(hw);
414 u8 sec_reg_value = 0x0;
415
f30d7507
JP		 416 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
417 "PairwiseEncAlgorithm = %d GroupEncAlgorithm = %d\n",
24284531 418 rtlpriv->sec.pairwise_enc_algorithm,
f30d7507 419 rtlpriv->sec.group_enc_algorithm);
24284531
CL		 420
421 if (rtlpriv->cfg->mod_params->sw_crypto || rtlpriv->sec.use_sw_sec) {
422 RT_TRACE(rtlpriv, COMP_SEC, DBG_DMESG,
f30d7507 423 "not open hw encryption\n");
24284531
CL		 424 return;
425 }
426
427 sec_reg_value = SCR_TXENCENABLE | SCR_RXENCENABLE;
428
429 if (rtlpriv->sec.use_defaultkey) {
430 sec_reg_value |= SCR_TXUSEDK;
431 sec_reg_value |= SCR_RXUSEDK;
432 }
433
f30d7507
JP		 434 RT_TRACE(rtlpriv, COMP_SEC, DBG_LOUD, "The SECR-value %x\n",
435 sec_reg_value);
24284531
CL		 436
437 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_WPA_CONFIG, &sec_reg_value);
438
439}
440
441static u8 _rtl92ce_halset_sysclk(struct ieee80211_hw *hw, u8 data)
442{
443 struct rtl_priv *rtlpriv = rtl_priv(hw);
444 u8 waitcount = 100;
445 bool bresult = false;
446 u8 tmpvalue;
447
448 rtl_write_byte(rtlpriv, SYS_CLKR + 1, data);
449
450 /* Wait the MAC synchronized. */
451 udelay(400);
452
453 /* Check if it is set ready. */
454 tmpvalue = rtl_read_byte(rtlpriv, SYS_CLKR + 1);
455 bresult = ((tmpvalue & BIT(7)) == (data & BIT(7)));
456
457 if ((data & (BIT(6) | BIT(7))) == false) {
458 waitcount = 100;
459 tmpvalue = 0;
460
461 while (1) {
462 waitcount--;
463
464 tmpvalue = rtl_read_byte(rtlpriv, SYS_CLKR + 1);
465 if ((tmpvalue & BIT(6)))
466 break;
467
292b1192 468 pr_err("wait for BIT(6) return value %x\n", tmpvalue);
24284531
CL		 469 if (waitcount == 0)
470 break;
471
472 udelay(10);
473 }
474
475 if (waitcount == 0)
476 bresult = false;
477 else
478 bresult = true;
479 }
480
481 return bresult;
482}
483
484void rtl8192se_gpiobit3_cfg_inputmode(struct ieee80211_hw *hw)
485{
486 struct rtl_priv *rtlpriv = rtl_priv(hw);
487 u8 u1tmp;
488
489 /* The following config GPIO function */
490 rtl_write_byte(rtlpriv, MAC_PINMUX_CFG, (GPIOMUX_EN | GPIOSEL_GPIO));
491 u1tmp = rtl_read_byte(rtlpriv, GPIO_IO_SEL);
492
493 /* config GPIO3 to input */
494 u1tmp &= HAL_8192S_HW_GPIO_OFF_MASK;
495 rtl_write_byte(rtlpriv, GPIO_IO_SEL, u1tmp);
496
497}
498
499static u8 _rtl92se_rf_onoff_detect(struct ieee80211_hw *hw)
500{
501 struct rtl_priv *rtlpriv = rtl_priv(hw);
502 u8 u1tmp;
503 u8 retval = ERFON;
504
505 /* The following config GPIO function */
506 rtl_write_byte(rtlpriv, MAC_PINMUX_CFG, (GPIOMUX_EN | GPIOSEL_GPIO));
507 u1tmp = rtl_read_byte(rtlpriv, GPIO_IO_SEL);
508
509 /* config GPIO3 to input */
510 u1tmp &= HAL_8192S_HW_GPIO_OFF_MASK;
511 rtl_write_byte(rtlpriv, GPIO_IO_SEL, u1tmp);
512
513 /* On some of the platform, driver cannot read correct
514 * value without delay between Write_GPIO_SEL and Read_GPIO_IN */
515 mdelay(10);
516
517 /* check GPIO3 */
7101f404 518 u1tmp = rtl_read_byte(rtlpriv, GPIO_IN_SE);
24284531
CL		 519 retval = (u1tmp & HAL_8192S_HW_GPIO_OFF_BIT) ? ERFON : ERFOFF;
520
521 return retval;
522}
523
524static void _rtl92se_macconfig_before_fwdownload(struct ieee80211_hw *hw)
525{
526 struct rtl_priv *rtlpriv = rtl_priv(hw);
527 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
528 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
529
530 u8 i;
531 u8 tmpu1b;
532 u16 tmpu2b;
533 u8 pollingcnt = 20;
534
535 if (rtlpci->first_init) {
536 /* Reset PCIE Digital */
537 tmpu1b = rtl_read_byte(rtlpriv, REG_SYS_FUNC_EN + 1);
538 tmpu1b &= 0xFE;
539 rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN + 1, tmpu1b);
540 udelay(1);
541 rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN + 1, tmpu1b | BIT(0));
542 }
543
544 /* Switch to SW IO control */
545 tmpu1b = rtl_read_byte(rtlpriv, (SYS_CLKR + 1));
546 if (tmpu1b & BIT(7)) {
547 tmpu1b &= ~(BIT(6) | BIT(7));
548
549 /* Set failed, return to prevent hang. */
550 if (!_rtl92ce_halset_sysclk(hw, tmpu1b))
551 return;
552 }
553
554 rtl_write_byte(rtlpriv, AFE_PLL_CTRL, 0x0);
555 udelay(50);
556 rtl_write_byte(rtlpriv, LDOA15_CTRL, 0x34);
557 udelay(50);
558
559 /* Clear FW RPWM for FW control LPS.*/
560 rtl_write_byte(rtlpriv, RPWM, 0x0);
561
562 /* Reset MAC-IO and CPU and Core Digital BIT(10)/11/15 */
563 tmpu1b = rtl_read_byte(rtlpriv, REG_SYS_FUNC_EN + 1);
564 tmpu1b &= 0x73;
565 rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN + 1, tmpu1b);
566 /* wait for BIT 10/11/15 to pull high automatically!! */
567 mdelay(1);
568
569 rtl_write_byte(rtlpriv, CMDR, 0);
570 rtl_write_byte(rtlpriv, TCR, 0);
571
572 /* Data sheet not define 0x562!!! Copy from WMAC!!!!! */
573 tmpu1b = rtl_read_byte(rtlpriv, 0x562);
574 tmpu1b |= 0x08;
575 rtl_write_byte(rtlpriv, 0x562, tmpu1b);
576 tmpu1b &= ~(BIT(3));
577 rtl_write_byte(rtlpriv, 0x562, tmpu1b);
578
579 /* Enable AFE clock source */
580 tmpu1b = rtl_read_byte(rtlpriv, AFE_XTAL_CTRL);
581 rtl_write_byte(rtlpriv, AFE_XTAL_CTRL, (tmpu1b | 0x01));
582 /* Delay 1.5ms */
583 mdelay(2);
584 tmpu1b = rtl_read_byte(rtlpriv, AFE_XTAL_CTRL + 1);
585 rtl_write_byte(rtlpriv, AFE_XTAL_CTRL + 1, (tmpu1b & 0xfb));
586
587 /* Enable AFE Macro Block's Bandgap */
588 tmpu1b = rtl_read_byte(rtlpriv, AFE_MISC);
589 rtl_write_byte(rtlpriv, AFE_MISC, (tmpu1b | BIT(0)));
590 mdelay(1);
591
592 /* Enable AFE Mbias */
593 tmpu1b = rtl_read_byte(rtlpriv, AFE_MISC);
594 rtl_write_byte(rtlpriv, AFE_MISC, (tmpu1b | 0x02));
595 mdelay(1);
596
597 /* Enable LDOA15 block */
598 tmpu1b = rtl_read_byte(rtlpriv, LDOA15_CTRL);
599 rtl_write_byte(rtlpriv, LDOA15_CTRL, (tmpu1b | BIT(0)));
600
601 /* Set Digital Vdd to Retention isolation Path. */
602 tmpu2b = rtl_read_word(rtlpriv, REG_SYS_ISO_CTRL);
603 rtl_write_word(rtlpriv, REG_SYS_ISO_CTRL, (tmpu2b | BIT(11)));
604
605 /* For warm reboot NIC disappera bug. */
606 tmpu2b = rtl_read_word(rtlpriv, REG_SYS_FUNC_EN);
607 rtl_write_word(rtlpriv, REG_SYS_FUNC_EN, (tmpu2b | BIT(13)));
608
609 rtl_write_byte(rtlpriv, REG_SYS_ISO_CTRL + 1, 0x68);
610
611 /* Enable AFE PLL Macro Block */
612 /* We need to delay 100u before enabling PLL. */
613 udelay(200);
614 tmpu1b = rtl_read_byte(rtlpriv, AFE_PLL_CTRL);
615 rtl_write_byte(rtlpriv, AFE_PLL_CTRL, (tmpu1b | BIT(0) | BIT(4)));
616
617 /* for divider reset */
618 udelay(100);
619 rtl_write_byte(rtlpriv, AFE_PLL_CTRL, (tmpu1b | BIT(0) |
620 BIT(4) | BIT(6)));
621 udelay(10);
622 rtl_write_byte(rtlpriv, AFE_PLL_CTRL, (tmpu1b | BIT(0) | BIT(4)));
623 udelay(10);
624
625 /* Enable MAC 80MHZ clock */
626 tmpu1b = rtl_read_byte(rtlpriv, AFE_PLL_CTRL + 1);
627 rtl_write_byte(rtlpriv, AFE_PLL_CTRL + 1, (tmpu1b | BIT(0)));
628 mdelay(1);
629
630 /* Release isolation AFE PLL & MD */
631 rtl_write_byte(rtlpriv, REG_SYS_ISO_CTRL, 0xA6);
632
633 /* Enable MAC clock */
634 tmpu2b = rtl_read_word(rtlpriv, SYS_CLKR);
635 rtl_write_word(rtlpriv, SYS_CLKR, (tmpu2b | BIT(12) | BIT(11)));
636
637 /* Enable Core digital and enable IOREG R/W */
638 tmpu2b = rtl_read_word(rtlpriv, REG_SYS_FUNC_EN);
639 rtl_write_word(rtlpriv, REG_SYS_FUNC_EN, (tmpu2b | BIT(11)));
640
641 tmpu1b = rtl_read_byte(rtlpriv, REG_SYS_FUNC_EN + 1);
642 rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN + 1, tmpu1b & ~(BIT(7)));
643
644 /* enable REG_EN */
645 rtl_write_word(rtlpriv, REG_SYS_FUNC_EN, (tmpu2b | BIT(11) | BIT(15)));
646
647 /* Switch the control path. */
648 tmpu2b = rtl_read_word(rtlpriv, SYS_CLKR);
649 rtl_write_word(rtlpriv, SYS_CLKR, (tmpu2b & (~BIT(2))));
650
651 tmpu1b = rtl_read_byte(rtlpriv, (SYS_CLKR + 1));
652 tmpu1b = ((tmpu1b | BIT(7)) & (~BIT(6)));
653 if (!_rtl92ce_halset_sysclk(hw, tmpu1b))
654 return; /* Set failed, return to prevent hang. */
655
656 rtl_write_word(rtlpriv, CMDR, 0x07FC);
657
658 /* MH We must enable the section of code to prevent load IMEM fail. */
659 /* Load MAC register from WMAc temporarily We simulate macreg. */
660 /* txt HW will provide MAC txt later */
661 rtl_write_byte(rtlpriv, 0x6, 0x30);
662 rtl_write_byte(rtlpriv, 0x49, 0xf0);
663
664 rtl_write_byte(rtlpriv, 0x4b, 0x81);
665
666 rtl_write_byte(rtlpriv, 0xb5, 0x21);
667
668 rtl_write_byte(rtlpriv, 0xdc, 0xff);
669 rtl_write_byte(rtlpriv, 0xdd, 0xff);
670 rtl_write_byte(rtlpriv, 0xde, 0xff);
671 rtl_write_byte(rtlpriv, 0xdf, 0xff);
672
673 rtl_write_byte(rtlpriv, 0x11a, 0x00);
674 rtl_write_byte(rtlpriv, 0x11b, 0x00);
675
676 for (i = 0; i < 32; i++)
677 rtl_write_byte(rtlpriv, INIMCS_SEL + i, 0x1b);
678
679 rtl_write_byte(rtlpriv, 0x236, 0xff);
680
681 rtl_write_byte(rtlpriv, 0x503, 0x22);
682
683 if (ppsc->support_aspm && !ppsc->support_backdoor)
684 rtl_write_byte(rtlpriv, 0x560, 0x40);
685 else
686 rtl_write_byte(rtlpriv, 0x560, 0x00);
687
688 rtl_write_byte(rtlpriv, DBG_PORT, 0x91);
689
690 /* Set RX Desc Address */
691 rtl_write_dword(rtlpriv, RDQDA, rtlpci->rx_ring[RX_MPDU_QUEUE].dma);
692 rtl_write_dword(rtlpriv, RCDA, rtlpci->rx_ring[RX_CMD_QUEUE].dma);
693
694 /* Set TX Desc Address */
695 rtl_write_dword(rtlpriv, TBKDA, rtlpci->tx_ring[BK_QUEUE].dma);
696 rtl_write_dword(rtlpriv, TBEDA, rtlpci->tx_ring[BE_QUEUE].dma);
697 rtl_write_dword(rtlpriv, TVIDA, rtlpci->tx_ring[VI_QUEUE].dma);
698 rtl_write_dword(rtlpriv, TVODA, rtlpci->tx_ring[VO_QUEUE].dma);
699 rtl_write_dword(rtlpriv, TBDA, rtlpci->tx_ring[BEACON_QUEUE].dma);
700 rtl_write_dword(rtlpriv, TCDA, rtlpci->tx_ring[TXCMD_QUEUE].dma);
701 rtl_write_dword(rtlpriv, TMDA, rtlpci->tx_ring[MGNT_QUEUE].dma);
702 rtl_write_dword(rtlpriv, THPDA, rtlpci->tx_ring[HIGH_QUEUE].dma);
703 rtl_write_dword(rtlpriv, HDA, rtlpci->tx_ring[HCCA_QUEUE].dma);
704
705 rtl_write_word(rtlpriv, CMDR, 0x37FC);
706
707 /* To make sure that TxDMA can ready to download FW. */
708 /* We should reset TxDMA if IMEM RPT was not ready. */
709 do {
710 tmpu1b = rtl_read_byte(rtlpriv, TCR);
711 if ((tmpu1b & TXDMA_INIT_VALUE) == TXDMA_INIT_VALUE)
712 break;
713
714 udelay(5);
715 } while (pollingcnt--);
716
717 if (pollingcnt <= 0) {
718 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
f30d7507
JP		 719 "Polling TXDMA_INIT_VALUE timeout!! Current TCR(%#x)\n",
720 tmpu1b);
24284531
CL		 721 tmpu1b = rtl_read_byte(rtlpriv, CMDR);
722 rtl_write_byte(rtlpriv, CMDR, tmpu1b & (~TXDMA_EN));
723 udelay(2);
724 /* Reset TxDMA */
725 rtl_write_byte(rtlpriv, CMDR, tmpu1b | TXDMA_EN);
726 }
727
728 /* After MACIO reset,we must refresh LED state. */
729 if ((ppsc->rfoff_reason == RF_CHANGE_BY_IPS) ||
730 (ppsc->rfoff_reason == 0)) {
731 struct rtl_pci_priv *pcipriv = rtl_pcipriv(hw);
732 struct rtl_led *pLed0 = &(pcipriv->ledctl.sw_led0);
733 enum rf_pwrstate rfpwr_state_toset;
734 rfpwr_state_toset = _rtl92se_rf_onoff_detect(hw);
735
736 if (rfpwr_state_toset == ERFON)
737 rtl92se_sw_led_on(hw, pLed0);
738 }
739}
740
741static void _rtl92se_macconfig_after_fwdownload(struct ieee80211_hw *hw)
742{
743 struct rtl_priv *rtlpriv = rtl_priv(hw);
744 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
745 struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
746 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
747 u8 i;
748 u16 tmpu2b;
749
750 /* 1. System Configure Register (Offset: 0x0000 - 0x003F) */
751
752 /* 2. Command Control Register (Offset: 0x0040 - 0x004F) */
753 /* Turn on 0x40 Command register */
754 rtl_write_word(rtlpriv, CMDR, (BBRSTN | BB_GLB_RSTN |
755 SCHEDULE_EN | MACRXEN | MACTXEN | DDMA_EN | FW2HW_EN |
756 RXDMA_EN | TXDMA_EN | HCI_RXDMA_EN | HCI_TXDMA_EN));
757
758 /* Set TCR TX DMA pre 2 FULL enable bit */
759 rtl_write_dword(rtlpriv, TCR, rtl_read_dword(rtlpriv, TCR) |
760 TXDMAPRE2FULL);
761
762 /* Set RCR */
763 rtl_write_dword(rtlpriv, RCR, rtlpci->receive_config);
764
765 /* 3. MACID Setting Register (Offset: 0x0050 - 0x007F) */
766
767 /* 4. Timing Control Register (Offset: 0x0080 - 0x009F) */
768 /* Set CCK/OFDM SIFS */
769 /* CCK SIFS shall always be 10us. */
770 rtl_write_word(rtlpriv, SIFS_CCK, 0x0a0a);
771 rtl_write_word(rtlpriv, SIFS_OFDM, 0x1010);
772
773 /* Set AckTimeout */
774 rtl_write_byte(rtlpriv, ACK_TIMEOUT, 0x40);
775
776 /* Beacon related */
777 rtl_write_word(rtlpriv, BCN_INTERVAL, 100);
778 rtl_write_word(rtlpriv, ATIMWND, 2);
779
780 /* 5. FIFO Control Register (Offset: 0x00A0 - 0x015F) */
781 /* 5.1 Initialize Number of Reserved Pages in Firmware Queue */
782 /* Firmware allocate now, associate with FW internal setting.!!! */
783
784 /* 5.2 Setting TX/RX page size 0/1/2/3/4=64/128/256/512/1024 */
785 /* 5.3 Set driver info, we only accept PHY status now. */
786 /* 5.4 Set RXDMA arbitration to control RXDMA/MAC/FW R/W for RXFIFO */
787 rtl_write_byte(rtlpriv, RXDMA, rtl_read_byte(rtlpriv, RXDMA) | BIT(6));
788
789 /* 6. Adaptive Control Register (Offset: 0x0160 - 0x01CF) */
790 /* Set RRSR to all legacy rate and HT rate
791 * CCK rate is supported by default.
792 * CCK rate will be filtered out only when associated
793 * AP does not support it.
794 * Only enable ACK rate to OFDM 24M
795 * Disable RRSR for CCK rate in A-Cut */
796
797 if (rtlhal->version == VERSION_8192S_ACUT)
798 rtl_write_byte(rtlpriv, RRSR, 0xf0);
799 else if (rtlhal->version == VERSION_8192S_BCUT)
800 rtl_write_byte(rtlpriv, RRSR, 0xff);
801 rtl_write_byte(rtlpriv, RRSR + 1, 0x01);
802 rtl_write_byte(rtlpriv, RRSR + 2, 0x00);
803
804 /* A-Cut IC do not support CCK rate. We forbid ARFR to */
805 /* fallback to CCK rate */
806 for (i = 0; i < 8; i++) {
807 /*Disable RRSR for CCK rate in A-Cut */
808 if (rtlhal->version == VERSION_8192S_ACUT)
809 rtl_write_dword(rtlpriv, ARFR0 + i * 4, 0x1f0ff0f0);
810 }
811
812 /* Different rate use different AMPDU size */
813 /* MCS32/ MCS15_SG use max AMPDU size 15*2=30K */
814 rtl_write_byte(rtlpriv, AGGLEN_LMT_H, 0x0f);
815 /* MCS0/1/2/3 use max AMPDU size 4*2=8K */
816 rtl_write_word(rtlpriv, AGGLEN_LMT_L, 0x7442);
817 /* MCS4/5 use max AMPDU size 8*2=16K 6/7 use 10*2=20K */
818 rtl_write_word(rtlpriv, AGGLEN_LMT_L + 2, 0xddd7);
819 /* MCS8/9 use max AMPDU size 8*2=16K 10/11 use 10*2=20K */
820 rtl_write_word(rtlpriv, AGGLEN_LMT_L + 4, 0xd772);
821 /* MCS12/13/14/15 use max AMPDU size 15*2=30K */
822 rtl_write_word(rtlpriv, AGGLEN_LMT_L + 6, 0xfffd);
823
824 /* Set Data / Response auto rate fallack retry count */
825 rtl_write_dword(rtlpriv, DARFRC, 0x04010000);
826 rtl_write_dword(rtlpriv, DARFRC + 4, 0x09070605);
827 rtl_write_dword(rtlpriv, RARFRC, 0x04010000);
828 rtl_write_dword(rtlpriv, RARFRC + 4, 0x09070605);
829
830 /* 7. EDCA Setting Register (Offset: 0x01D0 - 0x01FF) */
831 /* Set all rate to support SG */
832 rtl_write_word(rtlpriv, SG_RATE, 0xFFFF);
833
834 /* 8. WMAC, BA, and CCX related Register (Offset: 0x0200 - 0x023F) */
835 /* Set NAV protection length */
836 rtl_write_word(rtlpriv, NAV_PROT_LEN, 0x0080);
837 /* CF-END Threshold */
838 rtl_write_byte(rtlpriv, CFEND_TH, 0xFF);
839 /* Set AMPDU minimum space */
840 rtl_write_byte(rtlpriv, AMPDU_MIN_SPACE, 0x07);
841 /* Set TXOP stall control for several queue/HI/BCN/MGT/ */
842 rtl_write_byte(rtlpriv, TXOP_STALL_CTRL, 0x00);
843
844 /* 9. Security Control Register (Offset: 0x0240 - 0x025F) */
845 /* 10. Power Save Control Register (Offset: 0x0260 - 0x02DF) */
846 /* 11. General Purpose Register (Offset: 0x02E0 - 0x02FF) */
847 /* 12. Host Interrupt Status Register (Offset: 0x0300 - 0x030F) */
848 /* 13. Test Mode and Debug Control Register (Offset: 0x0310 - 0x034F) */
849
850 /* 14. Set driver info, we only accept PHY status now. */
851 rtl_write_byte(rtlpriv, RXDRVINFO_SZ, 4);
852
853 /* 15. For EEPROM R/W Workaround */
854 /* 16. For EFUSE to share REG_SYS_FUNC_EN with EEPROM!!! */
855 tmpu2b = rtl_read_byte(rtlpriv, REG_SYS_FUNC_EN);
856 rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN, tmpu2b | BIT(13));
857 tmpu2b = rtl_read_byte(rtlpriv, REG_SYS_ISO_CTRL);
858 rtl_write_byte(rtlpriv, REG_SYS_ISO_CTRL, tmpu2b & (~BIT(8)));
859
860 /* 17. For EFUSE */
861 /* We may R/W EFUSE in EEPROM mode */
862 if (rtlefuse->epromtype == EEPROM_BOOT_EFUSE) {
863 u8 tempval;
864
865 tempval = rtl_read_byte(rtlpriv, REG_SYS_ISO_CTRL + 1);
866 tempval &= 0xFE;
867 rtl_write_byte(rtlpriv, REG_SYS_ISO_CTRL + 1, tempval);
868
869 /* Change Program timing */
870 rtl_write_byte(rtlpriv, REG_EFUSE_CTRL + 3, 0x72);
f30d7507 871 RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG, "EFUSE CONFIG OK\n");
24284531
CL		 872 }
873
f30d7507 874 RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG, "OK\n");
24284531
CL		 875
876}
877
878static void _rtl92se_hw_configure(struct ieee80211_hw *hw)
879{
880 struct rtl_priv *rtlpriv = rtl_priv(hw);
881 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
882 struct rtl_phy *rtlphy = &(rtlpriv->phy);
883 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
884
885 u8 reg_bw_opmode = 0;
78d57372 886 u32 reg_rrsr = 0;
24284531
CL		 887 u8 regtmp = 0;
888
889 reg_bw_opmode = BW_OPMODE_20MHZ;
24284531
CL		 890 reg_rrsr = RATE_ALL_CCK | RATE_ALL_OFDM_AG;
891
892 regtmp = rtl_read_byte(rtlpriv, INIRTSMCS_SEL);
893 reg_rrsr = ((reg_rrsr & 0x000fffff) << 8) | regtmp;
894 rtl_write_dword(rtlpriv, INIRTSMCS_SEL, reg_rrsr);
895 rtl_write_byte(rtlpriv, BW_OPMODE, reg_bw_opmode);
896
897 /* Set Retry Limit here */
898 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_RETRY_LIMIT,
899 (u8 *)(&rtlpci->shortretry_limit));
900
901 rtl_write_byte(rtlpriv, MLT, 0x8f);
902
903 /* For Min Spacing configuration. */
904 switch (rtlphy->rf_type) {
905 case RF_1T2R:
906 case RF_1T1R:
907 rtlhal->minspace_cfg = (MAX_MSS_DENSITY_1T << 3);
908 break;
909 case RF_2T2R:
910 case RF_2T2R_GREEN:
911 rtlhal->minspace_cfg = (MAX_MSS_DENSITY_2T << 3);
912 break;
913 }
914 rtl_write_byte(rtlpriv, AMPDU_MIN_SPACE, rtlhal->minspace_cfg);
915}
916
917int rtl92se_hw_init(struct ieee80211_hw *hw)
918{
919 struct rtl_priv *rtlpriv = rtl_priv(hw);
920 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
921 struct rtl_phy *rtlphy = &(rtlpriv->phy);
922 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
923 struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
924 u8 tmp_byte = 0;
925
926 bool rtstatus = true;
927 u8 tmp_u1b;
928 int err = false;
929 u8 i;
930 int wdcapra_add[] = {
931 EDCAPARA_BE, EDCAPARA_BK,
932 EDCAPARA_VI, EDCAPARA_VO};
933 u8 secr_value = 0x0;
934
935 rtlpci->being_init_adapter = true;
936
937 rtlpriv->intf_ops->disable_aspm(hw);
938
939 /* 1. MAC Initialize */
940 /* Before FW download, we have to set some MAC register */
941 _rtl92se_macconfig_before_fwdownload(hw);
942
943 rtlhal->version = (enum version_8192s)((rtl_read_dword(rtlpriv,
944 PMC_FSM) >> 16) & 0xF);
945
946 rtl8192se_gpiobit3_cfg_inputmode(hw);
947
948 /* 2. download firmware */
949 rtstatus = rtl92s_download_fw(hw);
950 if (!rtstatus) {
951 RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING,
f30d7507 952 "Failed to download FW. Init HW without FW now... Please copy FW into /lib/firmware/rtlwifi\n");
24284531
CL		 953 rtlhal->fw_ready = false;
954 } else {
955 rtlhal->fw_ready = true;
956 }
957
958 /* After FW download, we have to reset MAC register */
959 _rtl92se_macconfig_after_fwdownload(hw);
960
961 /*Retrieve default FW Cmd IO map. */
962 rtlhal->fwcmd_iomap = rtl_read_word(rtlpriv, LBUS_MON_ADDR);
963 rtlhal->fwcmd_ioparam = rtl_read_dword(rtlpriv, LBUS_ADDR_MASK);
964
965 /* 3. Initialize MAC/PHY Config by MACPHY_reg.txt */
966 if (rtl92s_phy_mac_config(hw) != true) {
f30d7507 967 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG, "MAC Config failed\n");
24284531
CL		 968 return rtstatus;
969 }
970
971 /* Make sure BB/RF write OK. We should prevent enter IPS. radio off. */
972 /* We must set flag avoid BB/RF config period later!! */
973 rtl_write_dword(rtlpriv, CMDR, 0x37FC);
974
975 /* 4. Initialize BB After MAC Config PHY_reg.txt, AGC_Tab.txt */
976 if (rtl92s_phy_bb_config(hw) != true) {
f30d7507 977 RT_TRACE(rtlpriv, COMP_INIT, DBG_EMERG, "BB Config failed\n");
24284531
CL		 978 return rtstatus;
979 }
980
981 /* 5. Initiailze RF RAIO_A.txt RF RAIO_B.txt */
982 /* Before initalizing RF. We can not use FW to do RF-R/W. */
983
984 rtlphy->rf_mode = RF_OP_BY_SW_3WIRE;
985
986 /* RF Power Save */
987#if 0
988 /* H/W or S/W RF OFF before sleep. */
989 if (rtlpriv->psc.rfoff_reason > RF_CHANGE_BY_PS) {
990 u32 rfoffreason = rtlpriv->psc.rfoff_reason;
991
992 rtlpriv->psc.rfoff_reason = RF_CHANGE_BY_INIT;
993 rtlpriv->psc.rfpwr_state = ERFON;
4b9d8d67
MM		 994 /* FIXME: check spinlocks if this block is uncommented */
995 rtl_ps_set_rf_state(hw, ERFOFF, rfoffreason);
24284531
CL		 996 } else {
997 /* gpio radio on/off is out of adapter start */
998 if (rtlpriv->psc.hwradiooff == false) {
999 rtlpriv->psc.rfpwr_state = ERFON;
1000 rtlpriv->psc.rfoff_reason = 0;
1001 }
1002 }
1003#endif
1004
1005 /* Before RF-R/W we must execute the IO from Scott's suggestion. */
1006 rtl_write_byte(rtlpriv, AFE_XTAL_CTRL + 1, 0xDB);
1007 if (rtlhal->version == VERSION_8192S_ACUT)
1008 rtl_write_byte(rtlpriv, SPS1_CTRL + 3, 0x07);
1009 else
1010 rtl_write_byte(rtlpriv, RF_CTRL, 0x07);
1011
1012 if (rtl92s_phy_rf_config(hw) != true) {
f30d7507 1013 RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG, "RF Config failed\n");
24284531
CL		 1014 return rtstatus;
1015 }
1016
1017 /* After read predefined TXT, we must set BB/MAC/RF
1018 * register as our requirement */
1019
1020 rtlphy->rfreg_chnlval[0] = rtl92s_phy_query_rf_reg(hw,
1021 (enum radio_path)0,
1022 RF_CHNLBW,
1023 RFREG_OFFSET_MASK);
1024 rtlphy->rfreg_chnlval[1] = rtl92s_phy_query_rf_reg(hw,
1025 (enum radio_path)1,
1026 RF_CHNLBW,
1027 RFREG_OFFSET_MASK);
1028
1029 /*---- Set CCK and OFDM Block "ON"----*/
1030 rtl_set_bbreg(hw, RFPGA0_RFMOD, BCCKEN, 0x1);
1031 rtl_set_bbreg(hw, RFPGA0_RFMOD, BOFDMEN, 0x1);
1032
1033 /*3 Set Hardware(Do nothing now) */
1034 _rtl92se_hw_configure(hw);
1035
1036 /* Read EEPROM TX power index and PHY_REG_PG.txt to capture correct */
1037 /* TX power index for different rate set. */
1038 /* Get original hw reg values */
1039 rtl92s_phy_get_hw_reg_originalvalue(hw);
1040 /* Write correct tx power index */
1041 rtl92s_phy_set_txpower(hw, rtlphy->current_channel);
1042
1043 /* We must set MAC address after firmware download. */
1044 for (i = 0; i < 6; i++)
1045 rtl_write_byte(rtlpriv, MACIDR0 + i, rtlefuse->dev_addr[i]);
1046
1047 /* EEPROM R/W workaround */
1048 tmp_u1b = rtl_read_byte(rtlpriv, MAC_PINMUX_CFG);
1049 rtl_write_byte(rtlpriv, MAC_PINMUX_CFG, tmp_u1b & (~BIT(3)));
1050
1051 rtl_write_byte(rtlpriv, 0x4d, 0x0);
1052
1053 if (hal_get_firmwareversion(rtlpriv) >= 0x49) {
1054 tmp_byte = rtl_read_byte(rtlpriv, FW_RSVD_PG_CRTL) & (~BIT(4));
1055 tmp_byte = tmp_byte | BIT(5);
1056 rtl_write_byte(rtlpriv, FW_RSVD_PG_CRTL, tmp_byte);
1057 rtl_write_dword(rtlpriv, TXDESC_MSK, 0xFFFFCFFF);
1058 }
1059
1060 /* We enable high power and RA related mechanism after NIC
1061 * initialized. */
1062 rtl92s_phy_set_fw_cmd(hw, FW_CMD_RA_INIT);
1063
1064 /* Add to prevent ASPM bug. */
1065 /* Always enable hst and NIC clock request. */
1066 rtl92s_phy_switch_ephy_parameter(hw);
1067
1068 /* Security related
1069 * 1. Clear all H/W keys.
1070 * 2. Enable H/W encryption/decryption. */
1071 rtl_cam_reset_all_entry(hw);
1072 secr_value |= SCR_TXENCENABLE;
1073 secr_value |= SCR_RXENCENABLE;
1074 secr_value |= SCR_NOSKMC;
1075 rtl_write_byte(rtlpriv, REG_SECR, secr_value);
1076
1077 for (i = 0; i < 4; i++)
1078 rtl_write_dword(rtlpriv, wdcapra_add[i], 0x5e4322);
1079
1080 if (rtlphy->rf_type == RF_1T2R) {
1081 bool mrc2set = true;
1082 /* Turn on B-Path */
1083 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_MRC, (u8 *)&mrc2set);
1084 }
1085
1086 rtlpriv->cfg->ops->led_control(hw, LED_CTL_POWER_ON);
1087 rtl92s_dm_init(hw);
1088 rtlpci->being_init_adapter = false;
1089
1090 return err;
1091}
1092
1093void rtl92se_set_mac_addr(struct rtl_io *io, const u8 * addr)
1094{
1095}
1096
1097void rtl92se_set_check_bssid(struct ieee80211_hw *hw, bool check_bssid)
1098{
1099 struct rtl_priv *rtlpriv = rtl_priv(hw);
1100 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
1101 u32 reg_rcr = rtlpci->receive_config;
1102
1103 if (rtlpriv->psc.rfpwr_state != ERFON)
1104 return;
1105
e10542c4 1106 if (check_bssid) {
24284531
CL		 1107 reg_rcr |= (RCR_CBSSID);
1108 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_RCR, (u8 *)(&reg_rcr));
1109 } else if (check_bssid == false) {
1110 reg_rcr &= (~RCR_CBSSID);
1111 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_RCR, (u8 *)(&reg_rcr));
1112 }
1113
1114}
1115
1116static int _rtl92se_set_media_status(struct ieee80211_hw *hw,
1117 enum nl80211_iftype type)
1118{
1119 struct rtl_priv *rtlpriv = rtl_priv(hw);
1120 u8 bt_msr = rtl_read_byte(rtlpriv, MSR);
24284531
CL		 1121 u32 temp;
1122 bt_msr &= ~MSR_LINK_MASK;
1123
1124 switch (type) {
1125 case NL80211_IFTYPE_UNSPECIFIED:
1126 bt_msr |= (MSR_LINK_NONE << MSR_LINK_SHIFT);
24284531 1127 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
f30d7507 1128 "Set Network type to NO LINK!\n");
24284531
CL		 1129 break;
1130 case NL80211_IFTYPE_ADHOC:
1131 bt_msr |= (MSR_LINK_ADHOC << MSR_LINK_SHIFT);
1132 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
f30d7507 1133 "Set Network type to Ad Hoc!\n");
24284531
CL		 1134 break;
1135 case NL80211_IFTYPE_STATION:
1136 bt_msr |= (MSR_LINK_MANAGED << MSR_LINK_SHIFT);
24284531 1137 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
f30d7507 1138 "Set Network type to STA!\n");
24284531
CL		 1139 break;
1140 case NL80211_IFTYPE_AP:
1141 bt_msr |= (MSR_LINK_MASTER << MSR_LINK_SHIFT);
1142 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
f30d7507 1143 "Set Network type to AP!\n");
24284531
CL		 1144 break;
1145 default:
1146 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
f30d7507 1147 "Network type %d not supported!\n", type);
24284531
CL		 1148 return 1;
1149 break;
1150
1151 }
1152
1153 rtl_write_byte(rtlpriv, (MSR), bt_msr);
1154
1155 temp = rtl_read_dword(rtlpriv, TCR);
1156 rtl_write_dword(rtlpriv, TCR, temp & (~BIT(8)));
1157 rtl_write_dword(rtlpriv, TCR, temp | BIT(8));
1158
1159
1160 return 0;
1161}
1162
1163/* HW_VAR_MEDIA_STATUS & HW_VAR_CECHK_BSSID */
1164int rtl92se_set_network_type(struct ieee80211_hw *hw, enum nl80211_iftype type)
1165{
1166 struct rtl_priv *rtlpriv = rtl_priv(hw);
1167
1168 if (_rtl92se_set_media_status(hw, type))
1169 return -EOPNOTSUPP;
1170
1171 if (rtlpriv->mac80211.link_state == MAC80211_LINKED) {
1172 if (type != NL80211_IFTYPE_AP)
1173 rtl92se_set_check_bssid(hw, true);
1174 } else {
1175 rtl92se_set_check_bssid(hw, false);
1176 }
1177
1178 return 0;
1179}
1180
1181/* don't set REG_EDCA_BE_PARAM here because mac80211 will send pkt when scan */
1182void rtl92se_set_qos(struct ieee80211_hw *hw, int aci)
1183{
1184 struct rtl_priv *rtlpriv = rtl_priv(hw);
1185 rtl92s_dm_init_edca_turbo(hw);
1186
1187 switch (aci) {
1188 case AC1_BK:
1189 rtl_write_dword(rtlpriv, EDCAPARA_BK, 0xa44f);
1190 break;
1191 case AC0_BE:
1192 /* rtl_write_dword(rtlpriv, EDCAPARA_BE, u4b_ac_param); */
1193 break;
1194 case AC2_VI:
1195 rtl_write_dword(rtlpriv, EDCAPARA_VI, 0x5e4322);
1196 break;
1197 case AC3_VO:
1198 rtl_write_dword(rtlpriv, EDCAPARA_VO, 0x2f3222);
1199 break;
1200 default:
9d833ed7 1201 RT_ASSERT(false, "invalid aci: %d !\n", aci);
24284531
CL		 1202 break;
1203 }
1204}
1205
1206void rtl92se_enable_interrupt(struct ieee80211_hw *hw)
1207{
1208 struct rtl_priv *rtlpriv = rtl_priv(hw);
1209 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
1210
1211 rtl_write_dword(rtlpriv, INTA_MASK, rtlpci->irq_mask[0]);
1212 /* Support Bit 32-37(Assign as Bit 0-5) interrupt setting now */
1213 rtl_write_dword(rtlpriv, INTA_MASK + 4, rtlpci->irq_mask[1] & 0x3F);
24284531
CL		 1214}
1215
1216void rtl92se_disable_interrupt(struct ieee80211_hw *hw)
1217{
1218 struct rtl_priv *rtlpriv = rtl_priv(hw);
1219 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
1220
1221 rtl_write_dword(rtlpriv, INTA_MASK, 0);
1222 rtl_write_dword(rtlpriv, INTA_MASK + 4, 0);
1223
049436b9 1224 synchronize_irq(rtlpci->pdev->irq);
24284531
CL		 1225}
1226
1227
1228static u8 _rtl92s_set_sysclk(struct ieee80211_hw *hw, u8 data)
1229{
1230 struct rtl_priv *rtlpriv = rtl_priv(hw);
1231 u8 waitcnt = 100;
1232 bool result = false;
1233 u8 tmp;
1234
1235 rtl_write_byte(rtlpriv, SYS_CLKR + 1, data);
1236
1237 /* Wait the MAC synchronized. */
1238 udelay(400);
1239
1240 /* Check if it is set ready. */
1241 tmp = rtl_read_byte(rtlpriv, SYS_CLKR + 1);
1242 result = ((tmp & BIT(7)) == (data & BIT(7)));
1243
1244 if ((data & (BIT(6) | BIT(7))) == false) {
1245 waitcnt = 100;
1246 tmp = 0;
1247
1248 while (1) {
1249 waitcnt--;
1250 tmp = rtl_read_byte(rtlpriv, SYS_CLKR + 1);
1251
1252 if ((tmp & BIT(6)))
1253 break;
1254
292b1192 1255 pr_err("wait for BIT(6) return value %x\n", tmp);
24284531
CL		 1256
1257 if (waitcnt == 0)
1258 break;
1259 udelay(10);
1260 }
1261
1262 if (waitcnt == 0)
1263 result = false;
1264 else
1265 result = true;
1266 }
1267
1268 return result;
1269}
1270
1271static void _rtl92s_phy_set_rfhalt(struct ieee80211_hw *hw)
1272{
1273 struct rtl_priv *rtlpriv = rtl_priv(hw);
1274 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
1275 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
1276 u8 u1btmp;
1277
1278 if (rtlhal->driver_going2unload)
1279 rtl_write_byte(rtlpriv, 0x560, 0x0);
1280
1281 /* Power save for BB/RF */
1282 u1btmp = rtl_read_byte(rtlpriv, LDOV12D_CTRL);
1283 u1btmp |= BIT(0);
1284 rtl_write_byte(rtlpriv, LDOV12D_CTRL, u1btmp);
1285 rtl_write_byte(rtlpriv, SPS1_CTRL, 0x0);
1286 rtl_write_byte(rtlpriv, TXPAUSE, 0xFF);
1287 rtl_write_word(rtlpriv, CMDR, 0x57FC);
1288 udelay(100);
1289 rtl_write_word(rtlpriv, CMDR, 0x77FC);
1290 rtl_write_byte(rtlpriv, PHY_CCA, 0x0);
1291 udelay(10);
1292 rtl_write_word(rtlpriv, CMDR, 0x37FC);
1293 udelay(10);
1294 rtl_write_word(rtlpriv, CMDR, 0x77FC);
1295 udelay(10);
1296 rtl_write_word(rtlpriv, CMDR, 0x57FC);
1297 rtl_write_word(rtlpriv, CMDR, 0x0000);
1298
1299 if (rtlhal->driver_going2unload) {
1300 u1btmp = rtl_read_byte(rtlpriv, (REG_SYS_FUNC_EN + 1));
1301 u1btmp &= ~(BIT(0));
1302 rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN + 1, u1btmp);
1303 }
1304
1305 u1btmp = rtl_read_byte(rtlpriv, (SYS_CLKR + 1));
1306
1307 /* Add description. After switch control path. register
1308 * after page1 will be invisible. We can not do any IO
1309 * for register>0x40. After resume&MACIO reset, we need
1310 * to remember previous reg content. */
1311 if (u1btmp & BIT(7)) {
1312 u1btmp &= ~(BIT(6) | BIT(7));
1313 if (!_rtl92s_set_sysclk(hw, u1btmp)) {
292b1192 1314 pr_err("Switch ctrl path fail\n");
24284531
CL		 1315 return;
1316 }
1317 }
1318
1319 /* Power save for MAC */
1320 if (ppsc->rfoff_reason == RF_CHANGE_BY_IPS &&
1321 !rtlhal->driver_going2unload) {
1322 /* enable LED function */
1323 rtl_write_byte(rtlpriv, 0x03, 0xF9);
1324 /* SW/HW radio off or halt adapter!! For example S3/S4 */
1325 } else {
1326 /* LED function disable. Power range is about 8mA now. */
1327 /* if write 0xF1 disconnet_pci power
1328 * ifconfig wlan0 down power are both high 35:70 */
1329 /* if write oxF9 disconnet_pci power
1330 * ifconfig wlan0 down power are both low 12:45*/
1331 rtl_write_byte(rtlpriv, 0x03, 0xF9);
1332 }
1333
1334 rtl_write_byte(rtlpriv, SYS_CLKR + 1, 0x70);
1335 rtl_write_byte(rtlpriv, AFE_PLL_CTRL + 1, 0x68);
1336 rtl_write_byte(rtlpriv, AFE_PLL_CTRL, 0x00);
1337 rtl_write_byte(rtlpriv, LDOA15_CTRL, 0x34);
1338 rtl_write_byte(rtlpriv, AFE_XTAL_CTRL, 0x0E);
1339 RT_SET_PS_LEVEL(ppsc, RT_RF_OFF_LEVL_HALT_NIC);
1340
1341}
1342
1343static void _rtl92se_gen_refreshledstate(struct ieee80211_hw *hw)
1344{
1345 struct rtl_priv *rtlpriv = rtl_priv(hw);
1346 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
1347 struct rtl_pci_priv *pcipriv = rtl_pcipriv(hw);
1348 struct rtl_led *pLed0 = &(pcipriv->ledctl.sw_led0);
1349
1350 if (rtlpci->up_first_time == 1)
1351 return;
1352
1353 if (rtlpriv->psc.rfoff_reason == RF_CHANGE_BY_IPS)
1354 rtl92se_sw_led_on(hw, pLed0);
1355 else
1356 rtl92se_sw_led_off(hw, pLed0);
1357}
1358
1359
1360static void _rtl92se_power_domain_init(struct ieee80211_hw *hw)
1361{
1362 struct rtl_priv *rtlpriv = rtl_priv(hw);
1363 u16 tmpu2b;
1364 u8 tmpu1b;
1365
1366 rtlpriv->psc.pwrdomain_protect = true;
1367
1368 tmpu1b = rtl_read_byte(rtlpriv, (SYS_CLKR + 1));
1369 if (tmpu1b & BIT(7)) {
1370 tmpu1b &= ~(BIT(6) | BIT(7));
1371 if (!_rtl92s_set_sysclk(hw, tmpu1b)) {
1372 rtlpriv->psc.pwrdomain_protect = false;
1373 return;
1374 }
1375 }
1376
1377 rtl_write_byte(rtlpriv, AFE_PLL_CTRL, 0x0);
1378 rtl_write_byte(rtlpriv, LDOA15_CTRL, 0x34);
1379
1380 /* Reset MAC-IO and CPU and Core Digital BIT10/11/15 */
5c079d88 1381 tmpu1b = rtl_read_byte(rtlpriv, REG_SYS_FUNC_EN + 1);
24284531
CL		 1382
1383 /* If IPS we need to turn LED on. So we not
1384 * not disable BIT 3/7 of reg3. */
1385 if (rtlpriv->psc.rfoff_reason & (RF_CHANGE_BY_IPS | RF_CHANGE_BY_HW))
1386 tmpu1b &= 0xFB;
1387 else
1388 tmpu1b &= 0x73;
1389
5c079d88 1390 rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN + 1, tmpu1b);
24284531
CL		 1391 /* wait for BIT 10/11/15 to pull high automatically!! */
1392 mdelay(1);
1393
1394 rtl_write_byte(rtlpriv, CMDR, 0);
1395 rtl_write_byte(rtlpriv, TCR, 0);
1396
1397 /* Data sheet not define 0x562!!! Copy from WMAC!!!!! */
1398 tmpu1b = rtl_read_byte(rtlpriv, 0x562);
1399 tmpu1b |= 0x08;
1400 rtl_write_byte(rtlpriv, 0x562, tmpu1b);
1401 tmpu1b &= ~(BIT(3));
1402 rtl_write_byte(rtlpriv, 0x562, tmpu1b);
1403
1404 /* Enable AFE clock source */
1405 tmpu1b = rtl_read_byte(rtlpriv, AFE_XTAL_CTRL);
1406 rtl_write_byte(rtlpriv, AFE_XTAL_CTRL, (tmpu1b | 0x01));
1407 /* Delay 1.5ms */
1408 udelay(1500);
1409 tmpu1b = rtl_read_byte(rtlpriv, AFE_XTAL_CTRL + 1);
1410 rtl_write_byte(rtlpriv, AFE_XTAL_CTRL + 1, (tmpu1b & 0xfb));
1411
1412 /* Enable AFE Macro Block's Bandgap */
1413 tmpu1b = rtl_read_byte(rtlpriv, AFE_MISC);
1414 rtl_write_byte(rtlpriv, AFE_MISC, (tmpu1b | BIT(0)));
1415 mdelay(1);
1416
1417 /* Enable AFE Mbias */
1418 tmpu1b = rtl_read_byte(rtlpriv, AFE_MISC);
1419 rtl_write_byte(rtlpriv, AFE_MISC, (tmpu1b | 0x02));
1420 mdelay(1);
1421
1422 /* Enable LDOA15 block */
1423 tmpu1b = rtl_read_byte(rtlpriv, LDOA15_CTRL);
1424 rtl_write_byte(rtlpriv, LDOA15_CTRL, (tmpu1b | BIT(0)));
1425
1426 /* Set Digital Vdd to Retention isolation Path. */
5c079d88
CL		 1427 tmpu2b = rtl_read_word(rtlpriv, REG_SYS_ISO_CTRL);
1428 rtl_write_word(rtlpriv, REG_SYS_ISO_CTRL, (tmpu2b | BIT(11)));
24284531
CL		 1429
1430
1431 /* For warm reboot NIC disappera bug. */
5c079d88
CL		 1432 tmpu2b = rtl_read_word(rtlpriv, REG_SYS_FUNC_EN);
1433 rtl_write_word(rtlpriv, REG_SYS_FUNC_EN, (tmpu2b | BIT(13)));
24284531 1434
5c079d88 1435 rtl_write_byte(rtlpriv, REG_SYS_ISO_CTRL + 1, 0x68);
24284531
CL		 1436
1437 /* Enable AFE PLL Macro Block */
1438 tmpu1b = rtl_read_byte(rtlpriv, AFE_PLL_CTRL);
1439 rtl_write_byte(rtlpriv, AFE_PLL_CTRL, (tmpu1b | BIT(0) | BIT(4)));
1440 /* Enable MAC 80MHZ clock */
1441 tmpu1b = rtl_read_byte(rtlpriv, AFE_PLL_CTRL + 1);
1442 rtl_write_byte(rtlpriv, AFE_PLL_CTRL + 1, (tmpu1b | BIT(0)));
1443 mdelay(1);
1444
1445 /* Release isolation AFE PLL & MD */
5c079d88 1446 rtl_write_byte(rtlpriv, REG_SYS_ISO_CTRL, 0xA6);
24284531
CL		 1447
1448 /* Enable MAC clock */
1449 tmpu2b = rtl_read_word(rtlpriv, SYS_CLKR);
1450 rtl_write_word(rtlpriv, SYS_CLKR, (tmpu2b | BIT(12) | BIT(11)));
1451
1452 /* Enable Core digital and enable IOREG R/W */
5c079d88
CL		 1453 tmpu2b = rtl_read_word(rtlpriv, REG_SYS_FUNC_EN);
1454 rtl_write_word(rtlpriv, REG_SYS_FUNC_EN, (tmpu2b | BIT(11)));
24284531 1455 /* enable REG_EN */
5c079d88 1456 rtl_write_word(rtlpriv, REG_SYS_FUNC_EN, (tmpu2b | BIT(11) | BIT(15)));
24284531
CL		 1457
1458 /* Switch the control path. */
1459 tmpu2b = rtl_read_word(rtlpriv, SYS_CLKR);
1460 rtl_write_word(rtlpriv, SYS_CLKR, (tmpu2b & (~BIT(2))));
1461
1462 tmpu1b = rtl_read_byte(rtlpriv, (SYS_CLKR + 1));
1463 tmpu1b = ((tmpu1b | BIT(7)) & (~BIT(6)));
1464 if (!_rtl92s_set_sysclk(hw, tmpu1b)) {
1465 rtlpriv->psc.pwrdomain_protect = false;
1466 return;
1467 }
1468
1469 rtl_write_word(rtlpriv, CMDR, 0x37FC);
1470
1471 /* After MACIO reset,we must refresh LED state. */
1472 _rtl92se_gen_refreshledstate(hw);
1473
1474 rtlpriv->psc.pwrdomain_protect = false;
1475}
1476
1477void rtl92se_card_disable(struct ieee80211_hw *hw)
1478{
1479 struct rtl_priv *rtlpriv = rtl_priv(hw);
1480 struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
1481 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
1482 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
1483 enum nl80211_iftype opmode;
1484 u8 wait = 30;
1485
1486 rtlpriv->intf_ops->enable_aspm(hw);
1487
1488 if (rtlpci->driver_is_goingto_unload ||
1489 ppsc->rfoff_reason > RF_CHANGE_BY_PS)
1490 rtlpriv->cfg->ops->led_control(hw, LED_CTL_POWER_OFF);
1491
1492 /* we should chnge GPIO to input mode
1493 * this will drop away current about 25mA*/
1494 rtl8192se_gpiobit3_cfg_inputmode(hw);
1495
1496 /* this is very important for ips power save */
1497 while (wait-- >= 10 && rtlpriv->psc.pwrdomain_protect) {
1498 if (rtlpriv->psc.pwrdomain_protect)
1499 mdelay(20);
1500 else
1501 break;
1502 }
1503
1504 mac->link_state = MAC80211_NOLINK;
1505 opmode = NL80211_IFTYPE_UNSPECIFIED;
1506 _rtl92se_set_media_status(hw, opmode);
1507
1508 _rtl92s_phy_set_rfhalt(hw);
1509 udelay(100);
1510}
1511
1512void rtl92se_interrupt_recognized(struct ieee80211_hw *hw, u32 *p_inta,
1513 u32 *p_intb)
1514{
1515 struct rtl_priv *rtlpriv = rtl_priv(hw);
1516 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
1517
1518 *p_inta = rtl_read_dword(rtlpriv, ISR) & rtlpci->irq_mask[0];
1519 rtl_write_dword(rtlpriv, ISR, *p_inta);
1520
1521 *p_intb = rtl_read_dword(rtlpriv, ISR + 4) & rtlpci->irq_mask[1];
1522 rtl_write_dword(rtlpriv, ISR + 4, *p_intb);
1523}
1524
1525void rtl92se_set_beacon_related_registers(struct ieee80211_hw *hw)
1526{
1527 struct rtl_priv *rtlpriv = rtl_priv(hw);
1528 struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
1529 u16 bcntime_cfg = 0;
1530 u16 bcn_cw = 6, bcn_ifs = 0xf;
1531 u16 atim_window = 2;
1532
1533 /* ATIM Window (in unit of TU). */
1534 rtl_write_word(rtlpriv, ATIMWND, atim_window);
1535
1536 /* Beacon interval (in unit of TU). */
1537 rtl_write_word(rtlpriv, BCN_INTERVAL, mac->beacon_interval);
1538
1539 /* DrvErlyInt (in unit of TU). (Time to send
1540 * interrupt to notify driver to change
1541 * beacon content) */
1542 rtl_write_word(rtlpriv, BCN_DRV_EARLY_INT, 10 << 4);
1543
1544 /* BcnDMATIM(in unit of us). Indicates the
1545 * time before TBTT to perform beacon queue DMA */
1546 rtl_write_word(rtlpriv, BCN_DMATIME, 256);
1547
1548 /* Force beacon frame transmission even
1549 * after receiving beacon frame from
1550 * other ad hoc STA */
1551 rtl_write_byte(rtlpriv, BCN_ERR_THRESH, 100);
1552
1553 /* Beacon Time Configuration */
1554 if (mac->opmode == NL80211_IFTYPE_ADHOC)
1555 bcntime_cfg |= (bcn_cw << BCN_TCFG_CW_SHIFT);
1556
1557 /* TODO: bcn_ifs may required to be changed on ASIC */
1558 bcntime_cfg |= bcn_ifs << BCN_TCFG_IFS;
1559
1560 /*for beacon changed */
1561 rtl92s_phy_set_beacon_hwreg(hw, mac->beacon_interval);
1562}
1563
1564void rtl92se_set_beacon_interval(struct ieee80211_hw *hw)
1565{
1566 struct rtl_priv *rtlpriv = rtl_priv(hw);
1567 struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
1568 u16 bcn_interval = mac->beacon_interval;
1569
1570 /* Beacon interval (in unit of TU). */
1571 rtl_write_word(rtlpriv, BCN_INTERVAL, bcn_interval);
1572 /* 2008.10.24 added by tynli for beacon changed. */
1573 rtl92s_phy_set_beacon_hwreg(hw, bcn_interval);
1574}
1575
1576void rtl92se_update_interrupt_mask(struct ieee80211_hw *hw,
1577 u32 add_msr, u32 rm_msr)
1578{
1579 struct rtl_priv *rtlpriv = rtl_priv(hw);
1580 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
1581
f30d7507
JP		 1582 RT_TRACE(rtlpriv, COMP_INTR, DBG_LOUD, "add_msr:%x, rm_msr:%x\n",
1583 add_msr, rm_msr);
24284531
CL		 1584
1585 if (add_msr)
1586 rtlpci->irq_mask[0] |= add_msr;
1587
1588 if (rm_msr)
1589 rtlpci->irq_mask[0] &= (~rm_msr);
1590
1591 rtl92se_disable_interrupt(hw);
1592 rtl92se_enable_interrupt(hw);
1593}
1594
1595static void _rtl8192se_get_IC_Inferiority(struct ieee80211_hw *hw)
1596{
1597 struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
1598 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
1599 u8 efuse_id;
1600
1601 rtlhal->ic_class = IC_INFERIORITY_A;
1602
1603 /* Only retrieving while using EFUSE. */
1604 if ((rtlefuse->epromtype == EEPROM_BOOT_EFUSE) &&
1605 !rtlefuse->autoload_failflag) {
1606 efuse_id = efuse_read_1byte(hw, EFUSE_IC_ID_OFFSET);
1607
1608 if (efuse_id == 0xfe)
1609 rtlhal->ic_class = IC_INFERIORITY_B;
1610 }
1611}
1612
1613static void _rtl92se_read_adapter_info(struct ieee80211_hw *hw)
1614{
1615 struct rtl_priv *rtlpriv = rtl_priv(hw);
1616 struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
1617 struct rtl_phy *rtlphy = &(rtlpriv->phy);
1618 u16 i, usvalue;
1619 u16 eeprom_id;
1620 u8 tempval;
1621 u8 hwinfo[HWSET_MAX_SIZE_92S];
1622 u8 rf_path, index;
1623
1624 if (rtlefuse->epromtype == EEPROM_93C46) {
1625 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
f30d7507 1626 "RTL819X Not boot from eeprom, check it !!\n");
24284531
CL		 1627 } else if (rtlefuse->epromtype == EEPROM_BOOT_EFUSE) {
1628 rtl_efuse_shadow_map_update(hw);
1629
1630 memcpy((void *)hwinfo, (void *)
1631 &rtlefuse->efuse_map[EFUSE_INIT_MAP][0],
1632 HWSET_MAX_SIZE_92S);
1633 }
1634
af08687b 1635 RT_PRINT_DATA(rtlpriv, COMP_INIT, DBG_DMESG, "MAP",
24284531
CL		 1636 hwinfo, HWSET_MAX_SIZE_92S);
1637
1638 eeprom_id = *((u16 *)&hwinfo[0]);
1639 if (eeprom_id != RTL8190_EEPROM_ID) {
1640 RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING,
f30d7507 1641 "EEPROM ID(%#x) is invalid!!\n", eeprom_id);
24284531
CL		 1642 rtlefuse->autoload_failflag = true;
1643 } else {
f30d7507 1644 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, "Autoload OK\n");
24284531
CL		 1645 rtlefuse->autoload_failflag = false;
1646 }
1647
e10542c4 1648 if (rtlefuse->autoload_failflag)
24284531
CL		 1649 return;
1650
1651 _rtl8192se_get_IC_Inferiority(hw);
1652
1653 /* Read IC Version && Channel Plan */
1654 /* VID, DID SE 0xA-D */
1655 rtlefuse->eeprom_vid = *(u16 *)&hwinfo[EEPROM_VID];
1656 rtlefuse->eeprom_did = *(u16 *)&hwinfo[EEPROM_DID];
1657 rtlefuse->eeprom_svid = *(u16 *)&hwinfo[EEPROM_SVID];
1658 rtlefuse->eeprom_smid = *(u16 *)&hwinfo[EEPROM_SMID];
1659 rtlefuse->eeprom_version = *(u16 *)&hwinfo[EEPROM_VERSION];
1660
1661 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
f30d7507 1662 "EEPROMId = 0x%4x\n", eeprom_id);
24284531 1663 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
f30d7507 1664 "EEPROM VID = 0x%4x\n", rtlefuse->eeprom_vid);
24284531 1665 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
f30d7507 1666 "EEPROM DID = 0x%4x\n", rtlefuse->eeprom_did);
24284531 1667 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
f30d7507 1668 "EEPROM SVID = 0x%4x\n", rtlefuse->eeprom_svid);
24284531 1669 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
f30d7507 1670 "EEPROM SMID = 0x%4x\n", rtlefuse->eeprom_smid);
24284531
CL		 1671
1672 for (i = 0; i < 6; i += 2) {
1673 usvalue = *(u16 *)&hwinfo[EEPROM_MAC_ADDR + i];
1674 *((u16 *) (&rtlefuse->dev_addr[i])) = usvalue;
1675 }
1676
1677 for (i = 0; i < 6; i++)
1678 rtl_write_byte(rtlpriv, MACIDR0 + i, rtlefuse->dev_addr[i]);
1679
f30d7507 1680 RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG, "%pM\n", rtlefuse->dev_addr);
24284531
CL		 1681
1682 /* Get Tx Power Level by Channel */
1683 /* Read Tx power of Channel 1 ~ 14 from EEPROM. */
1684 /* 92S suupport RF A & B */
1685 for (rf_path = 0; rf_path < 2; rf_path++) {
1686 for (i = 0; i < 3; i++) {
1687 /* Read CCK RF A & B Tx power */
1688 rtlefuse->eeprom_chnlarea_txpwr_cck[rf_path][i] =
1689 hwinfo[EEPROM_TXPOWERBASE + rf_path * 3 + i];
1690
1691 /* Read OFDM RF A & B Tx power for 1T */
1692 rtlefuse->eeprom_chnlarea_txpwr_ht40_1s[rf_path][i] =
1693 hwinfo[EEPROM_TXPOWERBASE + 6 + rf_path * 3 + i];
1694
1695 /* Read OFDM RF A & B Tx power for 2T */
1696 rtlefuse->eeprom_chnlarea_txpwr_ht40_2sdiif[rf_path][i]
1697 = hwinfo[EEPROM_TXPOWERBASE + 12 +
1698 rf_path * 3 + i];
1699 }
1700 }
1701
1702 for (rf_path = 0; rf_path < 2; rf_path++)
1703 for (i = 0; i < 3; i++)
1704 RTPRINT(rtlpriv, FINIT, INIT_EEPROM,
4c48869f
JP		 1705 "RF(%d) EEPROM CCK Area(%d) = 0x%x\n",
1706 rf_path, i,
1707 rtlefuse->eeprom_chnlarea_txpwr_cck
1708 [rf_path][i]);
24284531
CL		 1709 for (rf_path = 0; rf_path < 2; rf_path++)
1710 for (i = 0; i < 3; i++)
1711 RTPRINT(rtlpriv, FINIT, INIT_EEPROM,
4c48869f
JP		 1712 "RF(%d) EEPROM HT40 1S Area(%d) = 0x%x\n",
1713 rf_path, i,
1714 rtlefuse->eeprom_chnlarea_txpwr_ht40_1s
1715 [rf_path][i]);
24284531
CL		 1716 for (rf_path = 0; rf_path < 2; rf_path++)
1717 for (i = 0; i < 3; i++)
1718 RTPRINT(rtlpriv, FINIT, INIT_EEPROM,
4c48869f
JP		 1719 "RF(%d) EEPROM HT40 2S Diff Area(%d) = 0x%x\n",
1720 rf_path, i,
1721 rtlefuse->eeprom_chnlarea_txpwr_ht40_2sdiif
1722 [rf_path][i]);
24284531
CL		 1723
1724 for (rf_path = 0; rf_path < 2; rf_path++) {
1725
1726 /* Assign dedicated channel tx power */
1727 for (i = 0; i < 14; i++) {
1728 /* channel 1~3 use the same Tx Power Level. */
1729 if (i < 3)
1730 index = 0;
1731 /* Channel 4-8 */
1732 else if (i < 8)
1733 index = 1;
1734 /* Channel 9-14 */
1735 else
1736 index = 2;
1737
1738 /* Record A & B CCK /OFDM - 1T/2T Channel area
1739 * tx power */
1740 rtlefuse->txpwrlevel_cck[rf_path][i] =
1741 rtlefuse->eeprom_chnlarea_txpwr_cck
1742 [rf_path][index];
1743 rtlefuse->txpwrlevel_ht40_1s[rf_path][i] =
1744 rtlefuse->eeprom_chnlarea_txpwr_ht40_1s
1745 [rf_path][index];
1746 rtlefuse->txpwrlevel_ht40_2s[rf_path][i] =
1747 rtlefuse->eeprom_chnlarea_txpwr_ht40_2sdiif
1748 [rf_path][index];
1749 }
1750
1751 for (i = 0; i < 14; i++) {
1752 RTPRINT(rtlpriv, FINIT, INIT_TxPower,
4c48869f
JP		 1753 "RF(%d)-Ch(%d) [CCK / HT40_1S / HT40_2S] = [0x%x / 0x%x / 0x%x]\n",
1754 rf_path, i,
1755 rtlefuse->txpwrlevel_cck[rf_path][i],
1756 rtlefuse->txpwrlevel_ht40_1s[rf_path][i],
1757 rtlefuse->txpwrlevel_ht40_2s[rf_path][i]);
24284531
CL		 1758 }
1759 }
1760
1761 for (rf_path = 0; rf_path < 2; rf_path++) {
1762 for (i = 0; i < 3; i++) {
1763 /* Read Power diff limit. */
1764 rtlefuse->eeprom_pwrgroup[rf_path][i] =
1765 hwinfo[EEPROM_TXPWRGROUP + rf_path * 3 + i];
1766 }
1767 }
1768
1769 for (rf_path = 0; rf_path < 2; rf_path++) {
1770 /* Fill Pwr group */
1771 for (i = 0; i < 14; i++) {
1772 /* Chanel 1-3 */
1773 if (i < 3)
1774 index = 0;
1775 /* Channel 4-8 */
1776 else if (i < 8)
1777 index = 1;
1778 /* Channel 9-13 */
1779 else
1780 index = 2;
1781
1782 rtlefuse->pwrgroup_ht20[rf_path][i] =
1783 (rtlefuse->eeprom_pwrgroup[rf_path][index] &
1784 0xf);
1785 rtlefuse->pwrgroup_ht40[rf_path][i] =
1786 ((rtlefuse->eeprom_pwrgroup[rf_path][index] &
1787 0xf0) >> 4);
1788
1789 RTPRINT(rtlpriv, FINIT, INIT_TxPower,
4c48869f
JP		 1790 "RF-%d pwrgroup_ht20[%d] = 0x%x\n",
1791 rf_path, i,
1792 rtlefuse->pwrgroup_ht20[rf_path][i]);
24284531 1793 RTPRINT(rtlpriv, FINIT, INIT_TxPower,
4c48869f
JP		 1794 "RF-%d pwrgroup_ht40[%d] = 0x%x\n",
1795 rf_path, i,
1796 rtlefuse->pwrgroup_ht40[rf_path][i]);
24284531
CL		 1797 }
1798 }
1799
1800 for (i = 0; i < 14; i++) {
1801 /* Read tx power difference between HT OFDM 20/40 MHZ */
1802 /* channel 1-3 */
1803 if (i < 3)
1804 index = 0;
1805 /* Channel 4-8 */
1806 else if (i < 8)
1807 index = 1;
1808 /* Channel 9-14 */
1809 else
1810 index = 2;
1811
1812 tempval = (*(u8 *)&hwinfo[EEPROM_TX_PWR_HT20_DIFF +
1813 index]) & 0xff;
1814 rtlefuse->txpwr_ht20diff[RF90_PATH_A][i] = (tempval & 0xF);
1815 rtlefuse->txpwr_ht20diff[RF90_PATH_B][i] =
1816 ((tempval >> 4) & 0xF);
1817
1818 /* Read OFDM<->HT tx power diff */
1819 /* Channel 1-3 */
1820 if (i < 3)
1821 index = 0;
1822 /* Channel 4-8 */
1823 else if (i < 8)
1824 index = 0x11;
1825 /* Channel 9-14 */
1826 else
1827 index = 1;
1828
1829 tempval = (*(u8 *)&hwinfo[EEPROM_TX_PWR_OFDM_DIFF + index])
1830 & 0xff;
1831 rtlefuse->txpwr_legacyhtdiff[RF90_PATH_A][i] =
1832 (tempval & 0xF);
1833 rtlefuse->txpwr_legacyhtdiff[RF90_PATH_B][i] =
1834 ((tempval >> 4) & 0xF);
1835
1836 tempval = (*(u8 *)&hwinfo[TX_PWR_SAFETY_CHK]);
1837 rtlefuse->txpwr_safetyflag = (tempval & 0x01);
1838 }
1839
1840 rtlefuse->eeprom_regulatory = 0;
1841 if (rtlefuse->eeprom_version >= 2) {
1842 /* BIT(0)~2 */
1843 if (rtlefuse->eeprom_version >= 4)
1844 rtlefuse->eeprom_regulatory =
1845 (hwinfo[EEPROM_REGULATORY] & 0x7);
1846 else /* BIT(0) */
1847 rtlefuse->eeprom_regulatory =
1848 (hwinfo[EEPROM_REGULATORY] & 0x1);
1849 }
1850 RTPRINT(rtlpriv, FINIT, INIT_TxPower,
4c48869f 1851 "eeprom_regulatory = 0x%x\n", rtlefuse->eeprom_regulatory);
24284531
CL		 1852
1853 for (i = 0; i < 14; i++)
1854 RTPRINT(rtlpriv, FINIT, INIT_TxPower,
4c48869f
JP		 1855 "RF-A Ht20 to HT40 Diff[%d] = 0x%x\n",
1856 i, rtlefuse->txpwr_ht20diff[RF90_PATH_A][i]);
24284531
CL		 1857 for (i = 0; i < 14; i++)
1858 RTPRINT(rtlpriv, FINIT, INIT_TxPower,
4c48869f
JP		 1859 "RF-A Legacy to Ht40 Diff[%d] = 0x%x\n",
1860 i, rtlefuse->txpwr_legacyhtdiff[RF90_PATH_A][i]);
24284531
CL		 1861 for (i = 0; i < 14; i++)
1862 RTPRINT(rtlpriv, FINIT, INIT_TxPower,
4c48869f
JP		 1863 "RF-B Ht20 to HT40 Diff[%d] = 0x%x\n",
1864 i, rtlefuse->txpwr_ht20diff[RF90_PATH_B][i]);
24284531
CL		 1865 for (i = 0; i < 14; i++)
1866 RTPRINT(rtlpriv, FINIT, INIT_TxPower,
4c48869f
JP		 1867 "RF-B Legacy to HT40 Diff[%d] = 0x%x\n",
1868 i, rtlefuse->txpwr_legacyhtdiff[RF90_PATH_B][i]);
24284531 1869
4c48869f
JP		 1870 RTPRINT(rtlpriv, FINIT, INIT_TxPower,
1871 "TxPwrSafetyFlag = %d\n", rtlefuse->txpwr_safetyflag);
24284531
CL		 1872
1873 /* Read RF-indication and Tx Power gain
1874 * index diff of legacy to HT OFDM rate. */
1875 tempval = (*(u8 *)&hwinfo[EEPROM_RFIND_POWERDIFF]) & 0xff;
1876 rtlefuse->eeprom_txpowerdiff = tempval;
1877 rtlefuse->legacy_httxpowerdiff =
1878 rtlefuse->txpwr_legacyhtdiff[RF90_PATH_A][0];
1879
4c48869f
JP		 1880 RTPRINT(rtlpriv, FINIT, INIT_TxPower,
1881 "TxPowerDiff = %#x\n", rtlefuse->eeprom_txpowerdiff);
24284531
CL		 1882
1883 /* Get TSSI value for each path. */
1884 usvalue = *(u16 *)&hwinfo[EEPROM_TSSI_A];
1885 rtlefuse->eeprom_tssi[RF90_PATH_A] = (u8)((usvalue & 0xff00) >> 8);
1886 usvalue = *(u8 *)&hwinfo[EEPROM_TSSI_B];
1887 rtlefuse->eeprom_tssi[RF90_PATH_B] = (u8)(usvalue & 0xff);
1888
4c48869f
JP		 1889 RTPRINT(rtlpriv, FINIT, INIT_TxPower, "TSSI_A = 0x%x, TSSI_B = 0x%x\n",
1890 rtlefuse->eeprom_tssi[RF90_PATH_A],
1891 rtlefuse->eeprom_tssi[RF90_PATH_B]);
24284531
CL		 1892
1893 /* Read antenna tx power offset of B/C/D to A from EEPROM */
1894 /* and read ThermalMeter from EEPROM */
1895 tempval = *(u8 *)&hwinfo[EEPROM_THERMALMETER];
1896 rtlefuse->eeprom_thermalmeter = tempval;
4c48869f
JP		 1897 RTPRINT(rtlpriv, FINIT, INIT_TxPower,
1898 "thermalmeter = 0x%x\n", rtlefuse->eeprom_thermalmeter);
24284531
CL		 1899
1900 /* ThermalMeter, BIT(0)~3 for RFIC1, BIT(4)~7 for RFIC2 */
1901 rtlefuse->thermalmeter[0] = (rtlefuse->eeprom_thermalmeter & 0x1f);
1902 rtlefuse->tssi_13dbm = rtlefuse->eeprom_thermalmeter * 100;
1903
1904 /* Read CrystalCap from EEPROM */
1905 tempval = (*(u8 *)&hwinfo[EEPROM_CRYSTALCAP]) >> 4;
1906 rtlefuse->eeprom_crystalcap = tempval;
1907 /* CrystalCap, BIT(12)~15 */
1908 rtlefuse->crystalcap = rtlefuse->eeprom_crystalcap;
1909
1910 /* Read IC Version && Channel Plan */
1911 /* Version ID, Channel plan */
1912 rtlefuse->eeprom_channelplan = *(u8 *)&hwinfo[EEPROM_CHANNELPLAN];
1913 rtlefuse->txpwr_fromeprom = true;
4c48869f
JP		 1914 RTPRINT(rtlpriv, FINIT, INIT_TxPower,
1915 "EEPROM ChannelPlan = 0x%4x\n", rtlefuse->eeprom_channelplan);
24284531
CL		 1916
1917 /* Read Customer ID or Board Type!!! */
1918 tempval = *(u8 *)&hwinfo[EEPROM_BOARDTYPE];
1919 /* Change RF type definition */
1920 if (tempval == 0)
1921 rtlphy->rf_type = RF_2T2R;
1922 else if (tempval == 1)
1923 rtlphy->rf_type = RF_1T2R;
1924 else if (tempval == 2)
1925 rtlphy->rf_type = RF_1T2R;
1926 else if (tempval == 3)
1927 rtlphy->rf_type = RF_1T1R;
1928
1929 /* 1T2R but 1SS (1x1 receive combining) */
1930 rtlefuse->b1x1_recvcombine = false;
1931 if (rtlphy->rf_type == RF_1T2R) {
1932 tempval = rtl_read_byte(rtlpriv, 0x07);
1933 if (!(tempval & BIT(0))) {
1934 rtlefuse->b1x1_recvcombine = true;
1935 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
f30d7507 1936 "RF_TYPE=1T2R but only 1SS\n");
24284531
CL		 1937 }
1938 }
1939 rtlefuse->b1ss_support = rtlefuse->b1x1_recvcombine;
1940 rtlefuse->eeprom_oemid = *(u8 *)&hwinfo[EEPROM_CUSTOMID];
1941
f30d7507
JP		 1942 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, "EEPROM Customer ID: 0x%2x",
1943 rtlefuse->eeprom_oemid);
24284531
CL		 1944
1945 /* set channel paln to world wide 13 */
1946 rtlefuse->channel_plan = COUNTRY_CODE_WORLD_WIDE_13;
1947}
1948
1949void rtl92se_read_eeprom_info(struct ieee80211_hw *hw)
1950{
1951 struct rtl_priv *rtlpriv = rtl_priv(hw);
1952 struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
1953 u8 tmp_u1b = 0;
1954
1955 tmp_u1b = rtl_read_byte(rtlpriv, EPROM_CMD);
1956
1957 if (tmp_u1b & BIT(4)) {
f30d7507 1958 RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG, "Boot from EEPROM\n");
24284531
CL		 1959 rtlefuse->epromtype = EEPROM_93C46;
1960 } else {
f30d7507 1961 RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG, "Boot from EFUSE\n");
24284531
CL		 1962 rtlefuse->epromtype = EEPROM_BOOT_EFUSE;
1963 }
1964
1965 if (tmp_u1b & BIT(5)) {
f30d7507 1966 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, "Autoload OK\n");
24284531
CL		 1967 rtlefuse->autoload_failflag = false;
1968 _rtl92se_read_adapter_info(hw);
1969 } else {
f30d7507 1970 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG, "Autoload ERR!!\n");
24284531
CL		 1971 rtlefuse->autoload_failflag = true;
1972 }
1973}
1974
1975static void rtl92se_update_hal_rate_table(struct ieee80211_hw *hw,
1976 struct ieee80211_sta *sta)
1977{
1978 struct rtl_priv *rtlpriv = rtl_priv(hw);
1979 struct rtl_phy *rtlphy = &(rtlpriv->phy);
1980 struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
1981 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
1982 u32 ratr_value;
1983 u8 ratr_index = 0;
1984 u8 nmode = mac->ht_enable;
1985 u8 mimo_ps = IEEE80211_SMPS_OFF;
1986 u16 shortgi_rate = 0;
1987 u32 tmp_ratr_value = 0;
1988 u8 curtxbw_40mhz = mac->bw_40;
1989 u8 curshortgi_40mhz = (sta->ht_cap.cap & IEEE80211_HT_CAP_SGI_40) ?
1990 1 : 0;
1991 u8 curshortgi_20mhz = (sta->ht_cap.cap & IEEE80211_HT_CAP_SGI_20) ?
1992 1 : 0;
1993 enum wireless_mode wirelessmode = mac->mode;
1994
1995 if (rtlhal->current_bandtype == BAND_ON_5G)
1996 ratr_value = sta->supp_rates[1] << 4;
1997 else
1998 ratr_value = sta->supp_rates[0];
1999 ratr_value |= (sta->ht_cap.mcs.rx_mask[1] << 20 |
2000 sta->ht_cap.mcs.rx_mask[0] << 12);
2001 switch (wirelessmode) {
2002 case WIRELESS_MODE_B:
2003 ratr_value &= 0x0000000D;
2004 break;
2005 case WIRELESS_MODE_G:
2006 ratr_value &= 0x00000FF5;
2007 break;
2008 case WIRELESS_MODE_N_24G:
2009 case WIRELESS_MODE_N_5G:
2010 nmode = 1;
2011 if (mimo_ps == IEEE80211_SMPS_STATIC) {
2012 ratr_value &= 0x0007F005;
2013 } else {
2014 u32 ratr_mask;
2015
2016 if (get_rf_type(rtlphy) == RF_1T2R ||
2017 get_rf_type(rtlphy) == RF_1T1R) {
2018 if (curtxbw_40mhz)
2019 ratr_mask = 0x000ff015;
2020 else
2021 ratr_mask = 0x000ff005;
2022 } else {
2023 if (curtxbw_40mhz)
2024 ratr_mask = 0x0f0ff015;
2025 else
2026 ratr_mask = 0x0f0ff005;
2027 }
2028
2029 ratr_value &= ratr_mask;
2030 }
2031 break;
2032 default:
2033 if (rtlphy->rf_type == RF_1T2R)
2034 ratr_value &= 0x000ff0ff;
2035 else
2036 ratr_value &= 0x0f0ff0ff;
2037
2038 break;
2039 }
2040
2041 if (rtlpriv->rtlhal.version >= VERSION_8192S_BCUT)
2042 ratr_value &= 0x0FFFFFFF;
2043 else if (rtlpriv->rtlhal.version == VERSION_8192S_ACUT)
2044 ratr_value &= 0x0FFFFFF0;
2045
2046 if (nmode && ((curtxbw_40mhz &&
2047 curshortgi_40mhz) || (!curtxbw_40mhz &&
2048 curshortgi_20mhz))) {
2049
2050 ratr_value |= 0x10000000;
2051 tmp_ratr_value = (ratr_value >> 12);
2052
2053 for (shortgi_rate = 15; shortgi_rate > 0; shortgi_rate--) {
2054 if ((1 << shortgi_rate) & tmp_ratr_value)
2055 break;
2056 }
2057
2058 shortgi_rate = (shortgi_rate << 12) | (shortgi_rate << 8) |
2059 (shortgi_rate << 4) | (shortgi_rate);
2060
2061 rtl_write_byte(rtlpriv, SG_RATE, shortgi_rate);
2062 }
2063
2064 rtl_write_dword(rtlpriv, ARFR0 + ratr_index * 4, ratr_value);
2065 if (ratr_value & 0xfffff000)
2066 rtl92s_phy_set_fw_cmd(hw, FW_CMD_RA_REFRESH_N);
2067 else
2068 rtl92s_phy_set_fw_cmd(hw, FW_CMD_RA_REFRESH_BG);
2069
f30d7507
JP		 2070 RT_TRACE(rtlpriv, COMP_RATR, DBG_DMESG, "%x\n",
2071 rtl_read_dword(rtlpriv, ARFR0));
24284531
CL		 2072}
2073
2074static void rtl92se_update_hal_rate_mask(struct ieee80211_hw *hw,
2075 struct ieee80211_sta *sta,
2076 u8 rssi_level)
2077{
2078 struct rtl_priv *rtlpriv = rtl_priv(hw);
2079 struct rtl_phy *rtlphy = &(rtlpriv->phy);
2080 struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
2081 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
2082 struct rtl_sta_info *sta_entry = NULL;
2083 u32 ratr_bitmap;
2084 u8 ratr_index = 0;
2085 u8 curtxbw_40mhz = (sta->ht_cap.cap & IEEE80211_HT_CAP_SUP_WIDTH_20_40)
2086 ? 1 : 0;
2087 u8 curshortgi_40mhz = (sta->ht_cap.cap & IEEE80211_HT_CAP_SGI_40) ?
2088 1 : 0;
2089 u8 curshortgi_20mhz = (sta->ht_cap.cap & IEEE80211_HT_CAP_SGI_20) ?
2090 1 : 0;
2091 enum wireless_mode wirelessmode = 0;
2092 bool shortgi = false;
2093 u32 ratr_value = 0;
2094 u8 shortgi_rate = 0;
2095 u32 mask = 0;
2096 u32 band = 0;
2097 bool bmulticast = false;
2098 u8 macid = 0;
2099 u8 mimo_ps = IEEE80211_SMPS_OFF;
2100
2101 sta_entry = (struct rtl_sta_info *) sta->drv_priv;
2102 wirelessmode = sta_entry->wireless_mode;
2103 if (mac->opmode == NL80211_IFTYPE_STATION)
2104 curtxbw_40mhz = mac->bw_40;
2105 else if (mac->opmode == NL80211_IFTYPE_AP ||
2106 mac->opmode == NL80211_IFTYPE_ADHOC)
2107 macid = sta->aid + 1;
2108
2109 if (rtlhal->current_bandtype == BAND_ON_5G)
2110 ratr_bitmap = sta->supp_rates[1] << 4;
2111 else
2112 ratr_bitmap = sta->supp_rates[0];
2113 ratr_bitmap |= (sta->ht_cap.mcs.rx_mask[1] << 20 |
2114 sta->ht_cap.mcs.rx_mask[0] << 12);
2115 switch (wirelessmode) {
2116 case WIRELESS_MODE_B:
2117 band |= WIRELESS_11B;
2118 ratr_index = RATR_INX_WIRELESS_B;
2119 if (ratr_bitmap & 0x0000000c)
2120 ratr_bitmap &= 0x0000000d;
2121 else
2122 ratr_bitmap &= 0x0000000f;
2123 break;
2124 case WIRELESS_MODE_G:
2125 band |= (WIRELESS_11G | WIRELESS_11B);
2126 ratr_index = RATR_INX_WIRELESS_GB;
2127
2128 if (rssi_level == 1)
2129 ratr_bitmap &= 0x00000f00;
2130 else if (rssi_level == 2)
2131 ratr_bitmap &= 0x00000ff0;
2132 else
2133 ratr_bitmap &= 0x00000ff5;
2134 break;
2135 case WIRELESS_MODE_A:
2136 band |= WIRELESS_11A;
2137 ratr_index = RATR_INX_WIRELESS_A;
2138 ratr_bitmap &= 0x00000ff0;
2139 break;
2140 case WIRELESS_MODE_N_24G:
2141 case WIRELESS_MODE_N_5G:
2142 band |= (WIRELESS_11N | WIRELESS_11G | WIRELESS_11B);
2143 ratr_index = RATR_INX_WIRELESS_NGB;
2144
2145 if (mimo_ps == IEEE80211_SMPS_STATIC) {
2146 if (rssi_level == 1)
2147 ratr_bitmap &= 0x00070000;
2148 else if (rssi_level == 2)
2149 ratr_bitmap &= 0x0007f000;
2150 else
2151 ratr_bitmap &= 0x0007f005;
2152 } else {
2153 if (rtlphy->rf_type == RF_1T2R ||
2154 rtlphy->rf_type == RF_1T1R) {
2155 if (rssi_level == 1) {
2156 ratr_bitmap &= 0x000f0000;
2157 } else if (rssi_level == 3) {
2158 ratr_bitmap &= 0x000fc000;
2159 } else if (rssi_level == 5) {
2160 ratr_bitmap &= 0x000ff000;
2161 } else {
2162 if (curtxbw_40mhz)
2163 ratr_bitmap &= 0x000ff015;
2164 else
2165 ratr_bitmap &= 0x000ff005;
2166 }
2167 } else {
2168 if (rssi_level == 1) {
2169 ratr_bitmap &= 0x0f8f0000;
2170 } else if (rssi_level == 3) {
2171 ratr_bitmap &= 0x0f8fc000;
2172 } else if (rssi_level == 5) {
2173 ratr_bitmap &= 0x0f8ff000;
2174 } else {
2175 if (curtxbw_40mhz)
2176 ratr_bitmap &= 0x0f8ff015;
2177 else
2178 ratr_bitmap &= 0x0f8ff005;
2179 }
2180 }
2181 }
2182
2183 if ((curtxbw_40mhz && curshortgi_40mhz) ||
2184 (!curtxbw_40mhz && curshortgi_20mhz)) {
2185 if (macid == 0)
2186 shortgi = true;
2187 else if (macid == 1)
2188 shortgi = false;
2189 }
2190 break;
2191 default:
2192 band |= (WIRELESS_11N | WIRELESS_11G | WIRELESS_11B);
2193 ratr_index = RATR_INX_WIRELESS_NGB;
2194
2195 if (rtlphy->rf_type == RF_1T2R)
2196 ratr_bitmap &= 0x000ff0ff;
2197 else
2198 ratr_bitmap &= 0x0f8ff0ff;
2199 break;
2200 }
2201
2202 if (rtlpriv->rtlhal.version >= VERSION_8192S_BCUT)
2203 ratr_bitmap &= 0x0FFFFFFF;
2204 else if (rtlpriv->rtlhal.version == VERSION_8192S_ACUT)
2205 ratr_bitmap &= 0x0FFFFFF0;
2206
2207 if (shortgi) {
2208 ratr_bitmap |= 0x10000000;
2209 /* Get MAX MCS available. */
2210 ratr_value = (ratr_bitmap >> 12);
2211 for (shortgi_rate = 15; shortgi_rate > 0; shortgi_rate--) {
2212 if ((1 << shortgi_rate) & ratr_value)
2213 break;
2214 }
2215
2216 shortgi_rate = (shortgi_rate << 12) | (shortgi_rate << 8) |
2217 (shortgi_rate << 4) | (shortgi_rate);
2218 rtl_write_byte(rtlpriv, SG_RATE, shortgi_rate);
2219 }
2220
2221 mask |= (bmulticast ? 1 : 0) << 9 | (macid & 0x1f) << 4 | (band & 0xf);
2222
f30d7507
JP		 2223 RT_TRACE(rtlpriv, COMP_RATR, DBG_TRACE, "mask = %x, bitmap = %x\n",
2224 mask, ratr_bitmap);
24284531
CL		 2225 rtl_write_dword(rtlpriv, 0x2c4, ratr_bitmap);
2226 rtl_write_dword(rtlpriv, WFM5, (FW_RA_UPDATE_MASK | (mask << 8)));
2227
2228 if (macid != 0)
2229 sta_entry->ratr_index = ratr_index;
2230}
2231
2232void rtl92se_update_hal_rate_tbl(struct ieee80211_hw *hw,
2233 struct ieee80211_sta *sta, u8 rssi_level)
2234{
2235 struct rtl_priv *rtlpriv = rtl_priv(hw);
2236
2237 if (rtlpriv->dm.useramask)
2238 rtl92se_update_hal_rate_mask(hw, sta, rssi_level);
2239 else
2240 rtl92se_update_hal_rate_table(hw, sta);
2241}
2242
2243void rtl92se_update_channel_access_setting(struct ieee80211_hw *hw)
2244{
2245 struct rtl_priv *rtlpriv = rtl_priv(hw);
2246 struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
2247 u16 sifs_timer;
2248
2249 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_SLOT_TIME,
2250 (u8 *)&mac->slot_time);
2251 sifs_timer = 0x0e0e;
2252 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_SIFS, (u8 *)&sifs_timer);
2253
2254}
2255
2256/* this ifunction is for RFKILL, it's different with windows,
2257 * because UI will disable wireless when GPIO Radio Off.
2258 * And here we not check or Disable/Enable ASPM like windows*/
2259bool rtl92se_gpio_radio_on_off_checking(struct ieee80211_hw *hw, u8 *valid)
2260{
2261 struct rtl_priv *rtlpriv = rtl_priv(hw);
2262 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
2263 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
78d57372 2264 enum rf_pwrstate rfpwr_toset /*, cur_rfstate */;
24284531
CL		 2265 unsigned long flag = 0;
2266 bool actuallyset = false;
2267 bool turnonbypowerdomain = false;
2268
2269 /* just 8191se can check gpio before firstup, 92c/92d have fixed it */
2270 if ((rtlpci->up_first_time == 1) || (rtlpci->being_init_adapter))
2271 return false;
2272
2273 if (ppsc->swrf_processing)
2274 return false;
2275
2276 spin_lock_irqsave(&rtlpriv->locks.rf_ps_lock, flag);
2277 if (ppsc->rfchange_inprogress) {
2278 spin_unlock_irqrestore(&rtlpriv->locks.rf_ps_lock, flag);
2279 return false;
2280 } else {
2281 ppsc->rfchange_inprogress = true;
2282 spin_unlock_irqrestore(&rtlpriv->locks.rf_ps_lock, flag);
2283 }
2284
78d57372 2285 /* cur_rfstate = ppsc->rfpwr_state;*/
24284531
CL		 2286
2287 /* because after _rtl92s_phy_set_rfhalt, all power
2288 * closed, so we must open some power for GPIO check,
2289 * or we will always check GPIO RFOFF here,
2290 * And we should close power after GPIO check */
2291 if (RT_IN_PS_LEVEL(ppsc, RT_RF_OFF_LEVL_HALT_NIC)) {
2292 _rtl92se_power_domain_init(hw);
2293 turnonbypowerdomain = true;
2294 }
2295
2296 rfpwr_toset = _rtl92se_rf_onoff_detect(hw);
2297
e10542c4 2298 if ((ppsc->hwradiooff) && (rfpwr_toset == ERFON)) {
24284531 2299 RT_TRACE(rtlpriv, COMP_RF, DBG_DMESG,
f30d7507 2300 "RFKILL-HW Radio ON, RF ON\n");
24284531
CL		 2301
2302 rfpwr_toset = ERFON;
2303 ppsc->hwradiooff = false;
2304 actuallyset = true;
2305 } else if ((ppsc->hwradiooff == false) && (rfpwr_toset == ERFOFF)) {
f30d7507
JP		 2306 RT_TRACE(rtlpriv, COMP_RF,
2307 DBG_DMESG, "RFKILL-HW Radio OFF, RF OFF\n");
24284531
CL		 2308
2309 rfpwr_toset = ERFOFF;
2310 ppsc->hwradiooff = true;
2311 actuallyset = true;
2312 }
2313
2314 if (actuallyset) {
2315 spin_lock_irqsave(&rtlpriv->locks.rf_ps_lock, flag);
2316 ppsc->rfchange_inprogress = false;
2317 spin_unlock_irqrestore(&rtlpriv->locks.rf_ps_lock, flag);
2318
2319 /* this not include ifconfig wlan0 down case */
2320 /* } else if (rfpwr_toset == ERFOFF || cur_rfstate == ERFOFF) { */
2321 } else {
2322 /* because power_domain_init may be happen when
2323 * _rtl92s_phy_set_rfhalt, this will open some powers
2324 * and cause current increasing about 40 mA for ips,
2325 * rfoff and ifconfig down, so we set
2326 * _rtl92s_phy_set_rfhalt again here */
2327 if (ppsc->reg_rfps_level & RT_RF_OFF_LEVL_HALT_NIC &&
2328 turnonbypowerdomain) {
2329 _rtl92s_phy_set_rfhalt(hw);
2330 RT_SET_PS_LEVEL(ppsc, RT_RF_OFF_LEVL_HALT_NIC);
2331 }
2332
2333 spin_lock_irqsave(&rtlpriv->locks.rf_ps_lock, flag);
2334 ppsc->rfchange_inprogress = false;
2335 spin_unlock_irqrestore(&rtlpriv->locks.rf_ps_lock, flag);
2336 }
2337
2338 *valid = 1;
2339 return !ppsc->hwradiooff;
2340
2341}
2342
2343/* Is_wepkey just used for WEP used as group & pairwise key
2344 * if pairwise is AES ang group is WEP Is_wepkey == false.*/
2345void rtl92se_set_key(struct ieee80211_hw *hw, u32 key_index, u8 *p_macaddr,
2346 bool is_group, u8 enc_algo, bool is_wepkey, bool clear_all)
2347{
2348 struct rtl_priv *rtlpriv = rtl_priv(hw);
2349 struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
2350 struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
2351 u8 *macaddr = p_macaddr;
2352
2353 u32 entry_id = 0;
2354 bool is_pairwise = false;
2355
2356 static u8 cam_const_addr[4][6] = {
2357 {0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
2358 {0x00, 0x00, 0x00, 0x00, 0x00, 0x01},
2359 {0x00, 0x00, 0x00, 0x00, 0x00, 0x02},
2360 {0x00, 0x00, 0x00, 0x00, 0x00, 0x03}
2361 };
2362 static u8 cam_const_broad[] = {
2363 0xff, 0xff, 0xff, 0xff, 0xff, 0xff
2364 };
2365
2366 if (clear_all) {
2367 u8 idx = 0;
2368 u8 cam_offset = 0;
2369 u8 clear_number = 5;
2370
f30d7507 2371 RT_TRACE(rtlpriv, COMP_SEC, DBG_DMESG, "clear_all\n");
24284531
CL		 2372
2373 for (idx = 0; idx < clear_number; idx++) {
2374 rtl_cam_mark_invalid(hw, cam_offset + idx);
2375 rtl_cam_empty_entry(hw, cam_offset + idx);
2376
2377 if (idx < 5) {
2378 memset(rtlpriv->sec.key_buf[idx], 0,
2379 MAX_KEY_LEN);
2380 rtlpriv->sec.key_len[idx] = 0;
2381 }
2382 }
2383
2384 } else {
2385 switch (enc_algo) {
2386 case WEP40_ENCRYPTION:
2387 enc_algo = CAM_WEP40;
2388 break;
2389 case WEP104_ENCRYPTION:
2390 enc_algo = CAM_WEP104;
2391 break;
2392 case TKIP_ENCRYPTION:
2393 enc_algo = CAM_TKIP;
2394 break;
2395 case AESCCMP_ENCRYPTION:
2396 enc_algo = CAM_AES;
2397 break;
2398 default:
2399 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
f30d7507 2400 "switch case not processed\n");
24284531
CL		 2401 enc_algo = CAM_TKIP;
2402 break;
2403 }
2404
2405 if (is_wepkey || rtlpriv->sec.use_defaultkey) {
2406 macaddr = cam_const_addr[key_index];
2407 entry_id = key_index;
2408 } else {
2409 if (is_group) {
2410 macaddr = cam_const_broad;
2411 entry_id = key_index;
2412 } else {
2413 if (mac->opmode == NL80211_IFTYPE_AP) {
2414 entry_id = rtl_cam_get_free_entry(hw,
2415 p_macaddr);
2416 if (entry_id >= TOTAL_CAM_ENTRY) {
2417 RT_TRACE(rtlpriv,
f30d7507
JP		 2418 COMP_SEC, DBG_EMERG,
2419 "Can not find free hw security cam entry\n");
24284531
CL		 2420 return;
2421 }
2422 } else {
2423 entry_id = CAM_PAIRWISE_KEY_POSITION;
2424 }
2425
2426 key_index = PAIRWISE_KEYIDX;
2427 is_pairwise = true;
2428 }
2429 }
2430
2431 if (rtlpriv->sec.key_len[key_index] == 0) {
2432 RT_TRACE(rtlpriv, COMP_SEC, DBG_DMESG,
f30d7507
JP		 2433 "delete one entry, entry_id is %d\n",
2434 entry_id);
24284531
CL		 2435 if (mac->opmode == NL80211_IFTYPE_AP)
2436 rtl_cam_del_entry(hw, p_macaddr);
2437 rtl_cam_delete_one_entry(hw, p_macaddr, entry_id);
2438 } else {
2439 RT_TRACE(rtlpriv, COMP_SEC, DBG_LOUD,
f30d7507
JP		 2440 "The insert KEY length is %d\n",
2441 rtlpriv->sec.key_len[PAIRWISE_KEYIDX]);
24284531 2442 RT_TRACE(rtlpriv, COMP_SEC, DBG_LOUD,
f30d7507
JP		 2443 "The insert KEY is %x %x\n",
2444 rtlpriv->sec.key_buf[0][0],
2445 rtlpriv->sec.key_buf[0][1]);
24284531
CL		 2446
2447 RT_TRACE(rtlpriv, COMP_SEC, DBG_DMESG,
f30d7507 2448 "add one entry\n");
24284531
CL		 2449 if (is_pairwise) {
2450 RT_PRINT_DATA(rtlpriv, COMP_SEC, DBG_LOUD,
f30d7507
JP		 2451 "Pairwise Key content",
2452 rtlpriv->sec.pairwise_key,
2453 rtlpriv->sec.
2454 key_len[PAIRWISE_KEYIDX]);
24284531
CL		 2455
2456 RT_TRACE(rtlpriv, COMP_SEC, DBG_DMESG,
f30d7507 2457 "set Pairwise key\n");
24284531
CL		 2458
2459 rtl_cam_add_one_entry(hw, macaddr, key_index,
2460 entry_id, enc_algo,
2461 CAM_CONFIG_NO_USEDK,
2462 rtlpriv->sec.key_buf[key_index]);
2463 } else {
2464 RT_TRACE(rtlpriv, COMP_SEC, DBG_DMESG,
f30d7507 2465 "set group key\n");
24284531
CL		 2466
2467 if (mac->opmode == NL80211_IFTYPE_ADHOC) {
2468 rtl_cam_add_one_entry(hw,
2469 rtlefuse->dev_addr,
2470 PAIRWISE_KEYIDX,
2471 CAM_PAIRWISE_KEY_POSITION,
2472 enc_algo, CAM_CONFIG_NO_USEDK,
2473 rtlpriv->sec.key_buf[entry_id]);
2474 }
2475
2476 rtl_cam_add_one_entry(hw, macaddr, key_index,
2477 entry_id, enc_algo,
2478 CAM_CONFIG_NO_USEDK,
2479 rtlpriv->sec.key_buf[entry_id]);
2480 }
2481
2482 }
2483 }
2484}
2485
2486void rtl92se_suspend(struct ieee80211_hw *hw)
2487{
2488 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
2489
2490 rtlpci->up_first_time = true;
2491}
2492
2493void rtl92se_resume(struct ieee80211_hw *hw)
2494{
2495 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
2496 u32 val;
2497
2498 pci_read_config_dword(rtlpci->pdev, 0x40, &val);
2499 if ((val & 0x0000ff00) != 0)
2500 pci_write_config_dword(rtlpci->pdev, 0x40,
2501 val & 0xffff00ff);
2502}
Linux kernel - Deliverables
This page took 0.196533 seconds and 5 git commands to generate.