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rtlwifi: Move pr_fmt macros to a single location
[deliverable/linux.git] / drivers / net / wireless / rtlwifi / rtl8192se / phy.c
CommitLineData
d1585316
CL		 1/******************************************************************************
2 *
ca742cd9 3 * Copyright(c) 2009-2012 Realtek Corporation.
d1585316
CL		 4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of version 2 of the GNU General Public License as
7 * published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details.
13 *
14 * You should have received a copy of the GNU General Public License along with
15 * this program; if not, write to the Free Software Foundation, Inc.,
16 * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
17 *
18 * The full GNU General Public License is included in this distribution in the
19 * file called LICENSE.
20 *
21 * Contact Information:
22 * wlanfae <wlanfae@realtek.com>
23 * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
24 * Hsinchu 300, Taiwan.
25 *
26 * Larry Finger <Larry.Finger@lwfinger.net>
27 *
28 *****************************************************************************/
29
30#include "../wifi.h"
31#include "../pci.h"
32#include "../ps.h"
33#include "reg.h"
34#include "def.h"
35#include "phy.h"
36#include "rf.h"
37#include "dm.h"
38#include "fw.h"
39#include "hw.h"
40#include "table.h"
41
42static u32 _rtl92s_phy_calculate_bit_shift(u32 bitmask)
43{
44 u32 i;
45
46 for (i = 0; i <= 31; i++) {
47 if (((bitmask >> i) & 0x1) == 1)
48 break;
49 }
50
51 return i;
52}
53
54u32 rtl92s_phy_query_bb_reg(struct ieee80211_hw *hw, u32 regaddr, u32 bitmask)
55{
56 struct rtl_priv *rtlpriv = rtl_priv(hw);
57 u32 returnvalue = 0, originalvalue, bitshift;
58
f30d7507
JP		 59 RT_TRACE(rtlpriv, COMP_RF, DBG_TRACE, "regaddr(%#x), bitmask(%#x)\n",
60 regaddr, bitmask);
d1585316
CL		 61
62 originalvalue = rtl_read_dword(rtlpriv, regaddr);
63 bitshift = _rtl92s_phy_calculate_bit_shift(bitmask);
64 returnvalue = (originalvalue & bitmask) >> bitshift;
65
f30d7507
JP		 66 RT_TRACE(rtlpriv, COMP_RF, DBG_TRACE, "BBR MASK=0x%x Addr[0x%x]=0x%x\n",
67 bitmask, regaddr, originalvalue);
d1585316
CL		 68
69 return returnvalue;
70
71}
72
73void rtl92s_phy_set_bb_reg(struct ieee80211_hw *hw, u32 regaddr, u32 bitmask,
74 u32 data)
75{
76 struct rtl_priv *rtlpriv = rtl_priv(hw);
77 u32 originalvalue, bitshift;
78
f30d7507
JP		 79 RT_TRACE(rtlpriv, COMP_RF, DBG_TRACE,
80 "regaddr(%#x), bitmask(%#x), data(%#x)\n",
81 regaddr, bitmask, data);
d1585316
CL		 82
83 if (bitmask != MASKDWORD) {
84 originalvalue = rtl_read_dword(rtlpriv, regaddr);
85 bitshift = _rtl92s_phy_calculate_bit_shift(bitmask);
86 data = ((originalvalue & (~bitmask)) | (data << bitshift));
87 }
88
89 rtl_write_dword(rtlpriv, regaddr, data);
90
f30d7507
JP		 91 RT_TRACE(rtlpriv, COMP_RF, DBG_TRACE,
92 "regaddr(%#x), bitmask(%#x), data(%#x)\n",
93 regaddr, bitmask, data);
d1585316
CL		 94
95}
96
97static u32 _rtl92s_phy_rf_serial_read(struct ieee80211_hw *hw,
98 enum radio_path rfpath, u32 offset)
99{
100
101 struct rtl_priv *rtlpriv = rtl_priv(hw);
102 struct rtl_phy *rtlphy = &(rtlpriv->phy);
103 struct bb_reg_def *pphyreg = &rtlphy->phyreg_def[rfpath];
104 u32 newoffset;
105 u32 tmplong, tmplong2;
106 u8 rfpi_enable = 0;
107 u32 retvalue = 0;
108
109 offset &= 0x3f;
110 newoffset = offset;
111
112 tmplong = rtl_get_bbreg(hw, RFPGA0_XA_HSSIPARAMETER2, MASKDWORD);
113
114 if (rfpath == RF90_PATH_A)
115 tmplong2 = tmplong;
116 else
117 tmplong2 = rtl_get_bbreg(hw, pphyreg->rfhssi_para2, MASKDWORD);
118
119 tmplong2 = (tmplong2 & (~BLSSI_READADDRESS)) | (newoffset << 23) |
120 BLSSI_READEDGE;
121
122 rtl_set_bbreg(hw, RFPGA0_XA_HSSIPARAMETER2, MASKDWORD,
123 tmplong & (~BLSSI_READEDGE));
124
125 mdelay(1);
126
127 rtl_set_bbreg(hw, pphyreg->rfhssi_para2, MASKDWORD, tmplong2);
128 mdelay(1);
129
130 rtl_set_bbreg(hw, RFPGA0_XA_HSSIPARAMETER2, MASKDWORD, tmplong |
131 BLSSI_READEDGE);
132 mdelay(1);
133
134 if (rfpath == RF90_PATH_A)
135 rfpi_enable = (u8)rtl_get_bbreg(hw, RFPGA0_XA_HSSIPARAMETER1,
136 BIT(8));
137 else if (rfpath == RF90_PATH_B)
138 rfpi_enable = (u8)rtl_get_bbreg(hw, RFPGA0_XB_HSSIPARAMETER1,
139 BIT(8));
140
141 if (rfpi_enable)
142 retvalue = rtl_get_bbreg(hw, pphyreg->rflssi_readbackpi,
143 BLSSI_READBACK_DATA);
144 else
145 retvalue = rtl_get_bbreg(hw, pphyreg->rflssi_readback,
146 BLSSI_READBACK_DATA);
147
148 retvalue = rtl_get_bbreg(hw, pphyreg->rflssi_readback,
149 BLSSI_READBACK_DATA);
150
f30d7507
JP		 151 RT_TRACE(rtlpriv, COMP_RF, DBG_TRACE, "RFR-%d Addr[0x%x]=0x%x\n",
152 rfpath, pphyreg->rflssi_readback, retvalue);
d1585316
CL		 153
154 return retvalue;
155
156}
157
158static void _rtl92s_phy_rf_serial_write(struct ieee80211_hw *hw,
159 enum radio_path rfpath, u32 offset,
160 u32 data)
161{
162 struct rtl_priv *rtlpriv = rtl_priv(hw);
163 struct rtl_phy *rtlphy = &(rtlpriv->phy);
164 struct bb_reg_def *pphyreg = &rtlphy->phyreg_def[rfpath];
165 u32 data_and_addr = 0;
166 u32 newoffset;
167
168 offset &= 0x3f;
169 newoffset = offset;
170
171 data_and_addr = ((newoffset << 20) | (data & 0x000fffff)) & 0x0fffffff;
172 rtl_set_bbreg(hw, pphyreg->rf3wire_offset, MASKDWORD, data_and_addr);
173
f30d7507
JP		 174 RT_TRACE(rtlpriv, COMP_RF, DBG_TRACE, "RFW-%d Addr[0x%x]=0x%x\n",
175 rfpath, pphyreg->rf3wire_offset, data_and_addr);
d1585316
CL		 176}
177
178
179u32 rtl92s_phy_query_rf_reg(struct ieee80211_hw *hw, enum radio_path rfpath,
180 u32 regaddr, u32 bitmask)
181{
182 struct rtl_priv *rtlpriv = rtl_priv(hw);
183 u32 original_value, readback_value, bitshift;
d1585316 184
f30d7507
JP		 185 RT_TRACE(rtlpriv, COMP_RF, DBG_TRACE,
186 "regaddr(%#x), rfpath(%#x), bitmask(%#x)\n",
187 regaddr, rfpath, bitmask);
d1585316 188
312d5479 189 spin_lock(&rtlpriv->locks.rf_lock);
d1585316
CL		 190
191 original_value = _rtl92s_phy_rf_serial_read(hw, rfpath, regaddr);
192
193 bitshift = _rtl92s_phy_calculate_bit_shift(bitmask);
194 readback_value = (original_value & bitmask) >> bitshift;
195
312d5479 196 spin_unlock(&rtlpriv->locks.rf_lock);
d1585316 197
f30d7507
JP		 198 RT_TRACE(rtlpriv, COMP_RF, DBG_TRACE,
199 "regaddr(%#x), rfpath(%#x), bitmask(%#x), original_value(%#x)\n",
200 regaddr, rfpath, bitmask, original_value);
d1585316
CL		 201
202 return readback_value;
203}
204
205void rtl92s_phy_set_rf_reg(struct ieee80211_hw *hw, enum radio_path rfpath,
206 u32 regaddr, u32 bitmask, u32 data)
207{
208 struct rtl_priv *rtlpriv = rtl_priv(hw);
209 struct rtl_phy *rtlphy = &(rtlpriv->phy);
210 u32 original_value, bitshift;
d1585316
CL		 211
212 if (!((rtlphy->rf_pathmap >> rfpath) & 0x1))
213 return;
214
f30d7507
JP		 215 RT_TRACE(rtlpriv, COMP_RF, DBG_TRACE,
216 "regaddr(%#x), bitmask(%#x), data(%#x), rfpath(%#x)\n",
217 regaddr, bitmask, data, rfpath);
d1585316 218
312d5479 219 spin_lock(&rtlpriv->locks.rf_lock);
d1585316
CL		 220
221 if (bitmask != RFREG_OFFSET_MASK) {
222 original_value = _rtl92s_phy_rf_serial_read(hw, rfpath,
223 regaddr);
224 bitshift = _rtl92s_phy_calculate_bit_shift(bitmask);
225 data = ((original_value & (~bitmask)) | (data << bitshift));
226 }
227
228 _rtl92s_phy_rf_serial_write(hw, rfpath, regaddr, data);
229
312d5479 230 spin_unlock(&rtlpriv->locks.rf_lock);
d1585316 231
f30d7507
JP		 232 RT_TRACE(rtlpriv, COMP_RF, DBG_TRACE,
233 "regaddr(%#x), bitmask(%#x), data(%#x), rfpath(%#x)\n",
234 regaddr, bitmask, data, rfpath);
d1585316
CL		 235
236}
237
238void rtl92s_phy_scan_operation_backup(struct ieee80211_hw *hw,
239 u8 operation)
240{
241 struct rtl_priv *rtlpriv = rtl_priv(hw);
242 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
243
244 if (!is_hal_stop(rtlhal)) {
245 switch (operation) {
246 case SCAN_OPT_BACKUP:
247 rtl92s_phy_set_fw_cmd(hw, FW_CMD_PAUSE_DM_BY_SCAN);
248 break;
249 case SCAN_OPT_RESTORE:
250 rtl92s_phy_set_fw_cmd(hw, FW_CMD_RESUME_DM_BY_SCAN);
251 break;
252 default:
253 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
f30d7507 254 "Unknown operation\n");
d1585316
CL		 255 break;
256 }
257 }
258}
259
260void rtl92s_phy_set_bw_mode(struct ieee80211_hw *hw,
261 enum nl80211_channel_type ch_type)
262{
263 struct rtl_priv *rtlpriv = rtl_priv(hw);
264 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
265 struct rtl_phy *rtlphy = &(rtlpriv->phy);
266 struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
267 u8 reg_bw_opmode;
d1585316 268
f30d7507
JP		 269 RT_TRACE(rtlpriv, COMP_SCAN, DBG_TRACE, "Switch to %s bandwidth\n",
270 rtlphy->current_chan_bw == HT_CHANNEL_WIDTH_20 ?
271 "20MHz" : "40MHz");
d1585316
CL		 272
273 if (rtlphy->set_bwmode_inprogress)
274 return;
275 if (is_hal_stop(rtlhal))
276 return;
277
278 rtlphy->set_bwmode_inprogress = true;
279
280 reg_bw_opmode = rtl_read_byte(rtlpriv, BW_OPMODE);
78d57372
LF		 281 /* dummy read */
282 rtl_read_byte(rtlpriv, RRSR + 2);
d1585316
CL		 283
284 switch (rtlphy->current_chan_bw) {
285 case HT_CHANNEL_WIDTH_20:
286 reg_bw_opmode |= BW_OPMODE_20MHZ;
287 rtl_write_byte(rtlpriv, BW_OPMODE, reg_bw_opmode);
288 break;
289 case HT_CHANNEL_WIDTH_20_40:
290 reg_bw_opmode &= ~BW_OPMODE_20MHZ;
291 rtl_write_byte(rtlpriv, BW_OPMODE, reg_bw_opmode);
292 break;
293 default:
294 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
f30d7507 295 "unknown bandwidth: %#X\n", rtlphy->current_chan_bw);
d1585316
CL		 296 break;
297 }
298
299 switch (rtlphy->current_chan_bw) {
300 case HT_CHANNEL_WIDTH_20:
301 rtl_set_bbreg(hw, RFPGA0_RFMOD, BRFMOD, 0x0);
302 rtl_set_bbreg(hw, RFPGA1_RFMOD, BRFMOD, 0x0);
303
304 if (rtlhal->version >= VERSION_8192S_BCUT)
305 rtl_write_byte(rtlpriv, RFPGA0_ANALOGPARAMETER2, 0x58);
306 break;
307 case HT_CHANNEL_WIDTH_20_40:
308 rtl_set_bbreg(hw, RFPGA0_RFMOD, BRFMOD, 0x1);
309 rtl_set_bbreg(hw, RFPGA1_RFMOD, BRFMOD, 0x1);
310
311 rtl_set_bbreg(hw, RCCK0_SYSTEM, BCCK_SIDEBAND,
312 (mac->cur_40_prime_sc >> 1));
313 rtl_set_bbreg(hw, ROFDM1_LSTF, 0xC00, mac->cur_40_prime_sc);
314
315 if (rtlhal->version >= VERSION_8192S_BCUT)
316 rtl_write_byte(rtlpriv, RFPGA0_ANALOGPARAMETER2, 0x18);
317 break;
318 default:
319 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
f30d7507 320 "unknown bandwidth: %#X\n", rtlphy->current_chan_bw);
d1585316
CL		 321 break;
322 }
323
324 rtl92s_phy_rf6052_set_bandwidth(hw, rtlphy->current_chan_bw);
325 rtlphy->set_bwmode_inprogress = false;
f30d7507 326 RT_TRACE(rtlpriv, COMP_SCAN, DBG_TRACE, "<==\n");
d1585316
CL		 327}
328
329static bool _rtl92s_phy_set_sw_chnl_cmdarray(struct swchnlcmd *cmdtable,
330 u32 cmdtableidx, u32 cmdtablesz, enum swchnlcmd_id cmdid,
331 u32 para1, u32 para2, u32 msdelay)
332{
333 struct swchnlcmd *pcmd;
334
335 if (cmdtable == NULL) {
9d833ed7 336 RT_ASSERT(false, "cmdtable cannot be NULL\n");
d1585316
CL		 337 return false;
338 }
339
340 if (cmdtableidx >= cmdtablesz)
341 return false;
342
343 pcmd = cmdtable + cmdtableidx;
344 pcmd->cmdid = cmdid;
345 pcmd->para1 = para1;
346 pcmd->para2 = para2;
347 pcmd->msdelay = msdelay;
348
349 return true;
350}
351
352static bool _rtl92s_phy_sw_chnl_step_by_step(struct ieee80211_hw *hw,
353 u8 channel, u8 *stage, u8 *step, u32 *delay)
354{
355 struct rtl_priv *rtlpriv = rtl_priv(hw);
356 struct rtl_phy *rtlphy = &(rtlpriv->phy);
357 struct swchnlcmd precommoncmd[MAX_PRECMD_CNT];
358 u32 precommoncmdcnt;
359 struct swchnlcmd postcommoncmd[MAX_POSTCMD_CNT];
360 u32 postcommoncmdcnt;
361 struct swchnlcmd rfdependcmd[MAX_RFDEPENDCMD_CNT];
362 u32 rfdependcmdcnt;
363 struct swchnlcmd *currentcmd = NULL;
364 u8 rfpath;
365 u8 num_total_rfpath = rtlphy->num_total_rfpath;
366
367 precommoncmdcnt = 0;
368 _rtl92s_phy_set_sw_chnl_cmdarray(precommoncmd, precommoncmdcnt++,
369 MAX_PRECMD_CNT, CMDID_SET_TXPOWEROWER_LEVEL, 0, 0, 0);
370 _rtl92s_phy_set_sw_chnl_cmdarray(precommoncmd, precommoncmdcnt++,
371 MAX_PRECMD_CNT, CMDID_END, 0, 0, 0);
372
373 postcommoncmdcnt = 0;
374
375 _rtl92s_phy_set_sw_chnl_cmdarray(postcommoncmd, postcommoncmdcnt++,
376 MAX_POSTCMD_CNT, CMDID_END, 0, 0, 0);
377
378 rfdependcmdcnt = 0;
379
380 RT_ASSERT((channel >= 1 && channel <= 14),
9d833ed7 381 "invalid channel for Zebra: %d\n", channel);
d1585316
CL		 382
383 _rtl92s_phy_set_sw_chnl_cmdarray(rfdependcmd, rfdependcmdcnt++,
384 MAX_RFDEPENDCMD_CNT, CMDID_RF_WRITEREG,
385 RF_CHNLBW, channel, 10);
386
387 _rtl92s_phy_set_sw_chnl_cmdarray(rfdependcmd, rfdependcmdcnt++,
388 MAX_RFDEPENDCMD_CNT, CMDID_END, 0, 0, 0);
389
390 do {
391 switch (*stage) {
392 case 0:
393 currentcmd = &precommoncmd[*step];
394 break;
395 case 1:
396 currentcmd = &rfdependcmd[*step];
397 break;
398 case 2:
399 currentcmd = &postcommoncmd[*step];
400 break;
401 }
402
403 if (currentcmd->cmdid == CMDID_END) {
404 if ((*stage) == 2) {
405 return true;
406 } else {
407 (*stage)++;
408 (*step) = 0;
409 continue;
410 }
411 }
412
413 switch (currentcmd->cmdid) {
414 case CMDID_SET_TXPOWEROWER_LEVEL:
415 rtl92s_phy_set_txpower(hw, channel);
416 break;
417 case CMDID_WRITEPORT_ULONG:
418 rtl_write_dword(rtlpriv, currentcmd->para1,
419 currentcmd->para2);
420 break;
421 case CMDID_WRITEPORT_USHORT:
422 rtl_write_word(rtlpriv, currentcmd->para1,
423 (u16)currentcmd->para2);
424 break;
425 case CMDID_WRITEPORT_UCHAR:
426 rtl_write_byte(rtlpriv, currentcmd->para1,
427 (u8)currentcmd->para2);
428 break;
429 case CMDID_RF_WRITEREG:
430 for (rfpath = 0; rfpath < num_total_rfpath; rfpath++) {
431 rtlphy->rfreg_chnlval[rfpath] =
432 ((rtlphy->rfreg_chnlval[rfpath] &
433 0xfffffc00) | currentcmd->para2);
434 rtl_set_rfreg(hw, (enum radio_path)rfpath,
435 currentcmd->para1,
436 RFREG_OFFSET_MASK,
437 rtlphy->rfreg_chnlval[rfpath]);
438 }
439 break;
440 default:
441 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
f30d7507 442 "switch case not processed\n");
d1585316
CL		 443 break;
444 }
445
446 break;
447 } while (true);
448
449 (*delay) = currentcmd->msdelay;
450 (*step)++;
451 return false;
452}
453
454u8 rtl92s_phy_sw_chnl(struct ieee80211_hw *hw)
455{
456 struct rtl_priv *rtlpriv = rtl_priv(hw);
457 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
458 struct rtl_phy *rtlphy = &(rtlpriv->phy);
459 u32 delay;
460 bool ret;
461
f30d7507
JP		 462 RT_TRACE(rtlpriv, COMP_SCAN, DBG_TRACE, "switch to channel%d\n",
463 rtlphy->current_channel);
d1585316
CL		 464
465 if (rtlphy->sw_chnl_inprogress)
466 return 0;
467
468 if (rtlphy->set_bwmode_inprogress)
469 return 0;
470
471 if (is_hal_stop(rtlhal))
472 return 0;
473
474 rtlphy->sw_chnl_inprogress = true;
475 rtlphy->sw_chnl_stage = 0;
476 rtlphy->sw_chnl_step = 0;
477
478 do {
479 if (!rtlphy->sw_chnl_inprogress)
480 break;
481
482 ret = _rtl92s_phy_sw_chnl_step_by_step(hw,
483 rtlphy->current_channel,
484 &rtlphy->sw_chnl_stage,
485 &rtlphy->sw_chnl_step, &delay);
486 if (!ret) {
487 if (delay > 0)
488 mdelay(delay);
489 else
490 continue;
491 } else {
492 rtlphy->sw_chnl_inprogress = false;
493 }
494 break;
495 } while (true);
496
497 rtlphy->sw_chnl_inprogress = false;
498
f30d7507 499 RT_TRACE(rtlpriv, COMP_SCAN, DBG_TRACE, "<==\n");
d1585316
CL		 500
501 return 1;
502}
503
504static void _rtl92se_phy_set_rf_sleep(struct ieee80211_hw *hw)
505{
506 struct rtl_priv *rtlpriv = rtl_priv(hw);
507 u8 u1btmp;
508
509 u1btmp = rtl_read_byte(rtlpriv, LDOV12D_CTRL);
510 u1btmp |= BIT(0);
511
512 rtl_write_byte(rtlpriv, LDOV12D_CTRL, u1btmp);
513 rtl_write_byte(rtlpriv, SPS1_CTRL, 0x0);
514 rtl_write_byte(rtlpriv, TXPAUSE, 0xFF);
515 rtl_write_word(rtlpriv, CMDR, 0x57FC);
516 udelay(100);
517
518 rtl_write_word(rtlpriv, CMDR, 0x77FC);
519 rtl_write_byte(rtlpriv, PHY_CCA, 0x0);
520 udelay(10);
521
522 rtl_write_word(rtlpriv, CMDR, 0x37FC);
523 udelay(10);
524
525 rtl_write_word(rtlpriv, CMDR, 0x77FC);
526 udelay(10);
527
528 rtl_write_word(rtlpriv, CMDR, 0x57FC);
529
530 /* we should chnge GPIO to input mode
531 * this will drop away current about 25mA*/
532 rtl8192se_gpiobit3_cfg_inputmode(hw);
533}
534
535bool rtl92s_phy_set_rf_power_state(struct ieee80211_hw *hw,
536 enum rf_pwrstate rfpwr_state)
537{
538 struct rtl_priv *rtlpriv = rtl_priv(hw);
539 struct rtl_pci_priv *pcipriv = rtl_pcipriv(hw);
540 struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
541 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
542 bool bresult = true;
543 u8 i, queue_id;
544 struct rtl8192_tx_ring *ring = NULL;
545
546 if (rfpwr_state == ppsc->rfpwr_state)
547 return false;
548
d1585316
CL		 549 switch (rfpwr_state) {
550 case ERFON:{
551 if ((ppsc->rfpwr_state == ERFOFF) &&
552 RT_IN_PS_LEVEL(ppsc, RT_RF_OFF_LEVL_HALT_NIC)) {
553
554 bool rtstatus;
555 u32 InitializeCount = 0;
556 do {
557 InitializeCount++;
558 RT_TRACE(rtlpriv, COMP_RF, DBG_DMESG,
f30d7507 559 "IPS Set eRf nic enable\n");
d1585316
CL		 560 rtstatus = rtl_ps_enable_nic(hw);
561 } while ((rtstatus != true) &&
562 (InitializeCount < 10));
563
564 RT_CLEAR_PS_LEVEL(ppsc,
565 RT_RF_OFF_LEVL_HALT_NIC);
566 } else {
567 RT_TRACE(rtlpriv, COMP_POWER, DBG_DMESG,
f30d7507
JP		 568 "awake, sleeped:%d ms state_inap:%x\n",
569 jiffies_to_msecs(jiffies -
570 ppsc->
571 last_sleep_jiffies),
572 rtlpriv->psc.state_inap);
d1585316
CL		 573 ppsc->last_awake_jiffies = jiffies;
574 rtl_write_word(rtlpriv, CMDR, 0x37FC);
575 rtl_write_byte(rtlpriv, TXPAUSE, 0x00);
576 rtl_write_byte(rtlpriv, PHY_CCA, 0x3);
577 }
578
579 if (mac->link_state == MAC80211_LINKED)
580 rtlpriv->cfg->ops->led_control(hw,
581 LED_CTL_LINK);
582 else
583 rtlpriv->cfg->ops->led_control(hw,
584 LED_CTL_NO_LINK);
585 break;
586 }
587 case ERFOFF:{
588 if (ppsc->reg_rfps_level & RT_RF_OFF_LEVL_HALT_NIC) {
589 RT_TRACE(rtlpriv, COMP_RF, DBG_DMESG,
f30d7507 590 "IPS Set eRf nic disable\n");
d1585316
CL		 591 rtl_ps_disable_nic(hw);
592 RT_SET_PS_LEVEL(ppsc, RT_RF_OFF_LEVL_HALT_NIC);
593 } else {
594 if (ppsc->rfoff_reason == RF_CHANGE_BY_IPS)
595 rtlpriv->cfg->ops->led_control(hw,
596 LED_CTL_NO_LINK);
597 else
598 rtlpriv->cfg->ops->led_control(hw,
599 LED_CTL_POWER_OFF);
600 }
601 break;
602 }
603 case ERFSLEEP:
604 if (ppsc->rfpwr_state == ERFOFF)
91ddff8a 605 return false;
d1585316
CL		 606
607 for (queue_id = 0, i = 0;
608 queue_id < RTL_PCI_MAX_TX_QUEUE_COUNT;) {
609 ring = &pcipriv->dev.tx_ring[queue_id];
610 if (skb_queue_len(&ring->queue) == 0 ||
611 queue_id == BEACON_QUEUE) {
612 queue_id++;
613 continue;
614 } else {
615 RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING,
f30d7507
JP		 616 "eRf Off/Sleep: %d times TcbBusyQueue[%d] = %d before doze!\n",
617 i + 1, queue_id,
618 skb_queue_len(&ring->queue));
d1585316
CL		 619
620 udelay(10);
621 i++;
622 }
623
624 if (i >= MAX_DOZE_WAITING_TIMES_9x) {
625 RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING,
f30d7507 626 "ERFOFF: %d times TcbBusyQueue[%d] = %d !\n",
d1585316
CL		 627 MAX_DOZE_WAITING_TIMES_9x,
628 queue_id,
f30d7507 629 skb_queue_len(&ring->queue));
d1585316
CL		 630 break;
631 }
632 }
633
634 RT_TRACE(rtlpriv, COMP_POWER, DBG_DMESG,
f30d7507 635 "Set ERFSLEEP awaked:%d ms\n",
d1585316 636 jiffies_to_msecs(jiffies -
f30d7507 637 ppsc->last_awake_jiffies));
d1585316
CL		 638
639 RT_TRACE(rtlpriv, COMP_POWER, DBG_DMESG,
f30d7507
JP		 640 "sleep awaked:%d ms state_inap:%x\n",
641 jiffies_to_msecs(jiffies -
642 ppsc->last_awake_jiffies),
643 rtlpriv->psc.state_inap);
d1585316
CL		 644 ppsc->last_sleep_jiffies = jiffies;
645 _rtl92se_phy_set_rf_sleep(hw);
646 break;
647 default:
648 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
f30d7507 649 "switch case not processed\n");
d1585316
CL		 650 bresult = false;
651 break;
652 }
653
654 if (bresult)
655 ppsc->rfpwr_state = rfpwr_state;
656
d1585316
CL		 657 return bresult;
658}
659
660static bool _rtl92s_phy_config_rfpa_bias_current(struct ieee80211_hw *hw,
661 enum radio_path rfpath)
662{
663 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
664 bool rtstatus = true;
665 u32 tmpval = 0;
666
667 /* If inferiority IC, we have to increase the PA bias current */
668 if (rtlhal->ic_class != IC_INFERIORITY_A) {
669 tmpval = rtl92s_phy_query_rf_reg(hw, rfpath, RF_IPA, 0xf);
670 rtl92s_phy_set_rf_reg(hw, rfpath, RF_IPA, 0xf, tmpval + 1);
671 }
672
673 return rtstatus;
674}
675
676static void _rtl92s_store_pwrindex_diffrate_offset(struct ieee80211_hw *hw,
677 u32 reg_addr, u32 bitmask, u32 data)
678{
679 struct rtl_priv *rtlpriv = rtl_priv(hw);
680 struct rtl_phy *rtlphy = &(rtlpriv->phy);
681
682 if (reg_addr == RTXAGC_RATE18_06)
683 rtlphy->mcs_txpwrlevel_origoffset[rtlphy->pwrgroup_cnt][0] =
684 data;
685 if (reg_addr == RTXAGC_RATE54_24)
686 rtlphy->mcs_txpwrlevel_origoffset[rtlphy->pwrgroup_cnt][1] =
687 data;
688 if (reg_addr == RTXAGC_CCK_MCS32)
689 rtlphy->mcs_txpwrlevel_origoffset[rtlphy->pwrgroup_cnt][6] =
690 data;
691 if (reg_addr == RTXAGC_MCS03_MCS00)
692 rtlphy->mcs_txpwrlevel_origoffset[rtlphy->pwrgroup_cnt][2] =
693 data;
694 if (reg_addr == RTXAGC_MCS07_MCS04)
695 rtlphy->mcs_txpwrlevel_origoffset[rtlphy->pwrgroup_cnt][3] =
696 data;
697 if (reg_addr == RTXAGC_MCS11_MCS08)
698 rtlphy->mcs_txpwrlevel_origoffset[rtlphy->pwrgroup_cnt][4] =
699 data;
700 if (reg_addr == RTXAGC_MCS15_MCS12) {
701 rtlphy->mcs_txpwrlevel_origoffset[rtlphy->pwrgroup_cnt][5] =
702 data;
703 rtlphy->pwrgroup_cnt++;
704 }
705}
706
707static void _rtl92s_phy_init_register_definition(struct ieee80211_hw *hw)
708{
709 struct rtl_priv *rtlpriv = rtl_priv(hw);
710 struct rtl_phy *rtlphy = &(rtlpriv->phy);
711
712 /*RF Interface Sowrtware Control */
713 rtlphy->phyreg_def[RF90_PATH_A].rfintfs = RFPGA0_XAB_RFINTERFACESW;
714 rtlphy->phyreg_def[RF90_PATH_B].rfintfs = RFPGA0_XAB_RFINTERFACESW;
715 rtlphy->phyreg_def[RF90_PATH_C].rfintfs = RFPGA0_XCD_RFINTERFACESW;
716 rtlphy->phyreg_def[RF90_PATH_D].rfintfs = RFPGA0_XCD_RFINTERFACESW;
717
718 /* RF Interface Readback Value */
719 rtlphy->phyreg_def[RF90_PATH_A].rfintfi = RFPGA0_XAB_RFINTERFACERB;
720 rtlphy->phyreg_def[RF90_PATH_B].rfintfi = RFPGA0_XAB_RFINTERFACERB;
721 rtlphy->phyreg_def[RF90_PATH_C].rfintfi = RFPGA0_XCD_RFINTERFACERB;
722 rtlphy->phyreg_def[RF90_PATH_D].rfintfi = RFPGA0_XCD_RFINTERFACERB;
723
724 /* RF Interface Output (and Enable) */
725 rtlphy->phyreg_def[RF90_PATH_A].rfintfo = RFPGA0_XA_RFINTERFACEOE;
726 rtlphy->phyreg_def[RF90_PATH_B].rfintfo = RFPGA0_XB_RFINTERFACEOE;
727 rtlphy->phyreg_def[RF90_PATH_C].rfintfo = RFPGA0_XC_RFINTERFACEOE;
728 rtlphy->phyreg_def[RF90_PATH_D].rfintfo = RFPGA0_XD_RFINTERFACEOE;
729
730 /* RF Interface (Output and) Enable */
731 rtlphy->phyreg_def[RF90_PATH_A].rfintfe = RFPGA0_XA_RFINTERFACEOE;
732 rtlphy->phyreg_def[RF90_PATH_B].rfintfe = RFPGA0_XB_RFINTERFACEOE;
733 rtlphy->phyreg_def[RF90_PATH_C].rfintfe = RFPGA0_XC_RFINTERFACEOE;
734 rtlphy->phyreg_def[RF90_PATH_D].rfintfe = RFPGA0_XD_RFINTERFACEOE;
735
736 /* Addr of LSSI. Wirte RF register by driver */
737 rtlphy->phyreg_def[RF90_PATH_A].rf3wire_offset =
738 RFPGA0_XA_LSSIPARAMETER;
739 rtlphy->phyreg_def[RF90_PATH_B].rf3wire_offset =
740 RFPGA0_XB_LSSIPARAMETER;
741 rtlphy->phyreg_def[RF90_PATH_C].rf3wire_offset =
742 RFPGA0_XC_LSSIPARAMETER;
743 rtlphy->phyreg_def[RF90_PATH_D].rf3wire_offset =
744 RFPGA0_XD_LSSIPARAMETER;
745
746 /* RF parameter */
747 rtlphy->phyreg_def[RF90_PATH_A].rflssi_select = RFPGA0_XAB_RFPARAMETER;
748 rtlphy->phyreg_def[RF90_PATH_B].rflssi_select = RFPGA0_XAB_RFPARAMETER;
749 rtlphy->phyreg_def[RF90_PATH_C].rflssi_select = RFPGA0_XCD_RFPARAMETER;
750 rtlphy->phyreg_def[RF90_PATH_D].rflssi_select = RFPGA0_XCD_RFPARAMETER;
751
752 /* Tx AGC Gain Stage (same for all path. Should we remove this?) */
753 rtlphy->phyreg_def[RF90_PATH_A].rftxgain_stage = RFPGA0_TXGAINSTAGE;
754 rtlphy->phyreg_def[RF90_PATH_B].rftxgain_stage = RFPGA0_TXGAINSTAGE;
755 rtlphy->phyreg_def[RF90_PATH_C].rftxgain_stage = RFPGA0_TXGAINSTAGE;
756 rtlphy->phyreg_def[RF90_PATH_D].rftxgain_stage = RFPGA0_TXGAINSTAGE;
757
758 /* Tranceiver A~D HSSI Parameter-1 */
759 rtlphy->phyreg_def[RF90_PATH_A].rfhssi_para1 = RFPGA0_XA_HSSIPARAMETER1;
760 rtlphy->phyreg_def[RF90_PATH_B].rfhssi_para1 = RFPGA0_XB_HSSIPARAMETER1;
761 rtlphy->phyreg_def[RF90_PATH_C].rfhssi_para1 = RFPGA0_XC_HSSIPARAMETER1;
762 rtlphy->phyreg_def[RF90_PATH_D].rfhssi_para1 = RFPGA0_XD_HSSIPARAMETER1;
763
764 /* Tranceiver A~D HSSI Parameter-2 */
765 rtlphy->phyreg_def[RF90_PATH_A].rfhssi_para2 = RFPGA0_XA_HSSIPARAMETER2;
766 rtlphy->phyreg_def[RF90_PATH_B].rfhssi_para2 = RFPGA0_XB_HSSIPARAMETER2;
767 rtlphy->phyreg_def[RF90_PATH_C].rfhssi_para2 = RFPGA0_XC_HSSIPARAMETER2;
768 rtlphy->phyreg_def[RF90_PATH_D].rfhssi_para2 = RFPGA0_XD_HSSIPARAMETER2;
769
770 /* RF switch Control */
771 rtlphy->phyreg_def[RF90_PATH_A].rfswitch_control =
772 RFPGA0_XAB_SWITCHCONTROL;
773 rtlphy->phyreg_def[RF90_PATH_B].rfswitch_control =
774 RFPGA0_XAB_SWITCHCONTROL;
775 rtlphy->phyreg_def[RF90_PATH_C].rfswitch_control =
776 RFPGA0_XCD_SWITCHCONTROL;
777 rtlphy->phyreg_def[RF90_PATH_D].rfswitch_control =
778 RFPGA0_XCD_SWITCHCONTROL;
779
780 /* AGC control 1 */
781 rtlphy->phyreg_def[RF90_PATH_A].rfagc_control1 = ROFDM0_XAAGCCORE1;
782 rtlphy->phyreg_def[RF90_PATH_B].rfagc_control1 = ROFDM0_XBAGCCORE1;
783 rtlphy->phyreg_def[RF90_PATH_C].rfagc_control1 = ROFDM0_XCAGCCORE1;
784 rtlphy->phyreg_def[RF90_PATH_D].rfagc_control1 = ROFDM0_XDAGCCORE1;
785
786 /* AGC control 2 */
787 rtlphy->phyreg_def[RF90_PATH_A].rfagc_control2 = ROFDM0_XAAGCCORE2;
788 rtlphy->phyreg_def[RF90_PATH_B].rfagc_control2 = ROFDM0_XBAGCCORE2;
789 rtlphy->phyreg_def[RF90_PATH_C].rfagc_control2 = ROFDM0_XCAGCCORE2;
790 rtlphy->phyreg_def[RF90_PATH_D].rfagc_control2 = ROFDM0_XDAGCCORE2;
791
792 /* RX AFE control 1 */
793 rtlphy->phyreg_def[RF90_PATH_A].rfrxiq_imbalance =
794 ROFDM0_XARXIQIMBALANCE;
795 rtlphy->phyreg_def[RF90_PATH_B].rfrxiq_imbalance =
796 ROFDM0_XBRXIQIMBALANCE;
797 rtlphy->phyreg_def[RF90_PATH_C].rfrxiq_imbalance =
798 ROFDM0_XCRXIQIMBALANCE;
799 rtlphy->phyreg_def[RF90_PATH_D].rfrxiq_imbalance =
800 ROFDM0_XDRXIQIMBALANCE;
801
802 /* RX AFE control 1 */
803 rtlphy->phyreg_def[RF90_PATH_A].rfrx_afe = ROFDM0_XARXAFE;
804 rtlphy->phyreg_def[RF90_PATH_B].rfrx_afe = ROFDM0_XBRXAFE;
805 rtlphy->phyreg_def[RF90_PATH_C].rfrx_afe = ROFDM0_XCRXAFE;
806 rtlphy->phyreg_def[RF90_PATH_D].rfrx_afe = ROFDM0_XDRXAFE;
807
808 /* Tx AFE control 1 */
809 rtlphy->phyreg_def[RF90_PATH_A].rftxiq_imbalance =
810 ROFDM0_XATXIQIMBALANCE;
811 rtlphy->phyreg_def[RF90_PATH_B].rftxiq_imbalance =
812 ROFDM0_XBTXIQIMBALANCE;
813 rtlphy->phyreg_def[RF90_PATH_C].rftxiq_imbalance =
814 ROFDM0_XCTXIQIMBALANCE;
815 rtlphy->phyreg_def[RF90_PATH_D].rftxiq_imbalance =
816 ROFDM0_XDTXIQIMBALANCE;
817
818 /* Tx AFE control 2 */
819 rtlphy->phyreg_def[RF90_PATH_A].rftx_afe = ROFDM0_XATXAFE;
820 rtlphy->phyreg_def[RF90_PATH_B].rftx_afe = ROFDM0_XBTXAFE;
821 rtlphy->phyreg_def[RF90_PATH_C].rftx_afe = ROFDM0_XCTXAFE;
822 rtlphy->phyreg_def[RF90_PATH_D].rftx_afe = ROFDM0_XDTXAFE;
823
824 /* Tranceiver LSSI Readback */
825 rtlphy->phyreg_def[RF90_PATH_A].rflssi_readback =
826 RFPGA0_XA_LSSIREADBACK;
827 rtlphy->phyreg_def[RF90_PATH_B].rflssi_readback =
828 RFPGA0_XB_LSSIREADBACK;
829 rtlphy->phyreg_def[RF90_PATH_C].rflssi_readback =
830 RFPGA0_XC_LSSIREADBACK;
831 rtlphy->phyreg_def[RF90_PATH_D].rflssi_readback =
832 RFPGA0_XD_LSSIREADBACK;
833
834 /* Tranceiver LSSI Readback PI mode */
835 rtlphy->phyreg_def[RF90_PATH_A].rflssi_readbackpi =
836 TRANSCEIVERA_HSPI_READBACK;
837 rtlphy->phyreg_def[RF90_PATH_B].rflssi_readbackpi =
838 TRANSCEIVERB_HSPI_READBACK;
839}
840
841
842static bool _rtl92s_phy_config_bb(struct ieee80211_hw *hw, u8 configtype)
843{
844 int i;
845 u32 *phy_reg_table;
846 u32 *agc_table;
847 u16 phy_reg_len, agc_len;
848
849 agc_len = AGCTAB_ARRAYLENGTH;
850 agc_table = rtl8192seagctab_array;
851 /* Default RF_type: 2T2R */
852 phy_reg_len = PHY_REG_2T2RARRAYLENGTH;
853 phy_reg_table = rtl8192sephy_reg_2t2rarray;
854
855 if (configtype == BASEBAND_CONFIG_PHY_REG) {
856 for (i = 0; i < phy_reg_len; i = i + 2) {
857 if (phy_reg_table[i] == 0xfe)
858 mdelay(50);
859 else if (phy_reg_table[i] == 0xfd)
860 mdelay(5);
861 else if (phy_reg_table[i] == 0xfc)
862 mdelay(1);
863 else if (phy_reg_table[i] == 0xfb)
864 udelay(50);
865 else if (phy_reg_table[i] == 0xfa)
866 udelay(5);
867 else if (phy_reg_table[i] == 0xf9)
868 udelay(1);
869
870 /* Add delay for ECS T20 & LG malow platform, */
871 udelay(1);
872
873 rtl92s_phy_set_bb_reg(hw, phy_reg_table[i], MASKDWORD,
874 phy_reg_table[i + 1]);
875 }
876 } else if (configtype == BASEBAND_CONFIG_AGC_TAB) {
877 for (i = 0; i < agc_len; i = i + 2) {
878 rtl92s_phy_set_bb_reg(hw, agc_table[i], MASKDWORD,
879 agc_table[i + 1]);
880
881 /* Add delay for ECS T20 & LG malow platform */
882 udelay(1);
883 }
884 }
885
886 return true;
887}
888
889static bool _rtl92s_phy_set_bb_to_diff_rf(struct ieee80211_hw *hw,
890 u8 configtype)
891{
892 struct rtl_priv *rtlpriv = rtl_priv(hw);
893 struct rtl_phy *rtlphy = &(rtlpriv->phy);
894 u32 *phy_regarray2xtxr_table;
895 u16 phy_regarray2xtxr_len;
896 int i;
897
898 if (rtlphy->rf_type == RF_1T1R) {
899 phy_regarray2xtxr_table = rtl8192sephy_changeto_1t1rarray;
900 phy_regarray2xtxr_len = PHY_CHANGETO_1T1RARRAYLENGTH;
901 } else if (rtlphy->rf_type == RF_1T2R) {
902 phy_regarray2xtxr_table = rtl8192sephy_changeto_1t2rarray;
903 phy_regarray2xtxr_len = PHY_CHANGETO_1T2RARRAYLENGTH;
904 } else {
905 return false;
906 }
907
908 if (configtype == BASEBAND_CONFIG_PHY_REG) {
909 for (i = 0; i < phy_regarray2xtxr_len; i = i + 3) {
910 if (phy_regarray2xtxr_table[i] == 0xfe)
911 mdelay(50);
912 else if (phy_regarray2xtxr_table[i] == 0xfd)
913 mdelay(5);
914 else if (phy_regarray2xtxr_table[i] == 0xfc)
915 mdelay(1);
916 else if (phy_regarray2xtxr_table[i] == 0xfb)
917 udelay(50);
918 else if (phy_regarray2xtxr_table[i] == 0xfa)
919 udelay(5);
920 else if (phy_regarray2xtxr_table[i] == 0xf9)
921 udelay(1);
922
923 rtl92s_phy_set_bb_reg(hw, phy_regarray2xtxr_table[i],
924 phy_regarray2xtxr_table[i + 1],
925 phy_regarray2xtxr_table[i + 2]);
926 }
927 }
928
929 return true;
930}
931
932static bool _rtl92s_phy_config_bb_with_pg(struct ieee80211_hw *hw,
933 u8 configtype)
934{
935 int i;
936 u32 *phy_table_pg;
937 u16 phy_pg_len;
938
939 phy_pg_len = PHY_REG_ARRAY_PGLENGTH;
940 phy_table_pg = rtl8192sephy_reg_array_pg;
941
942 if (configtype == BASEBAND_CONFIG_PHY_REG) {
943 for (i = 0; i < phy_pg_len; i = i + 3) {
944 if (phy_table_pg[i] == 0xfe)
945 mdelay(50);
946 else if (phy_table_pg[i] == 0xfd)
947 mdelay(5);
948 else if (phy_table_pg[i] == 0xfc)
949 mdelay(1);
950 else if (phy_table_pg[i] == 0xfb)
951 udelay(50);
952 else if (phy_table_pg[i] == 0xfa)
953 udelay(5);
954 else if (phy_table_pg[i] == 0xf9)
955 udelay(1);
956
957 _rtl92s_store_pwrindex_diffrate_offset(hw,
958 phy_table_pg[i],
959 phy_table_pg[i + 1],
960 phy_table_pg[i + 2]);
961 rtl92s_phy_set_bb_reg(hw, phy_table_pg[i],
962 phy_table_pg[i + 1],
963 phy_table_pg[i + 2]);
964 }
965 }
966
967 return true;
968}
969
970static bool _rtl92s_phy_bb_config_parafile(struct ieee80211_hw *hw)
971{
972 struct rtl_priv *rtlpriv = rtl_priv(hw);
973 struct rtl_phy *rtlphy = &(rtlpriv->phy);
974 struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
975 bool rtstatus = true;
976
977 /* 1. Read PHY_REG.TXT BB INIT!! */
978 /* We will separate as 1T1R/1T2R/1T2R_GREEN/2T2R */
979 if (rtlphy->rf_type == RF_1T2R || rtlphy->rf_type == RF_2T2R ||
980 rtlphy->rf_type == RF_1T1R || rtlphy->rf_type == RF_2T2R_GREEN) {
981 rtstatus = _rtl92s_phy_config_bb(hw, BASEBAND_CONFIG_PHY_REG);
982
983 if (rtlphy->rf_type != RF_2T2R &&
984 rtlphy->rf_type != RF_2T2R_GREEN)
985 /* so we should reconfig BB reg with the right
986 * PHY parameters. */
987 rtstatus = _rtl92s_phy_set_bb_to_diff_rf(hw,
988 BASEBAND_CONFIG_PHY_REG);
989 } else {
990 rtstatus = false;
991 }
992
993 if (rtstatus != true) {
994 RT_TRACE(rtlpriv, COMP_INIT, DBG_EMERG,
f30d7507 995 "Write BB Reg Fail!!\n");
d1585316
CL		 996 goto phy_BB8190_Config_ParaFile_Fail;
997 }
998
999 /* 2. If EEPROM or EFUSE autoload OK, We must config by
1000 * PHY_REG_PG.txt */
1001 if (rtlefuse->autoload_failflag == false) {
1002 rtlphy->pwrgroup_cnt = 0;
1003
1004 rtstatus = _rtl92s_phy_config_bb_with_pg(hw,
1005 BASEBAND_CONFIG_PHY_REG);
1006 }
1007 if (rtstatus != true) {
1008 RT_TRACE(rtlpriv, COMP_INIT, DBG_EMERG,
f30d7507 1009 "_rtl92s_phy_bb_config_parafile(): BB_PG Reg Fail!!\n");
d1585316
CL		 1010 goto phy_BB8190_Config_ParaFile_Fail;
1011 }
1012
1013 /* 3. BB AGC table Initialization */
1014 rtstatus = _rtl92s_phy_config_bb(hw, BASEBAND_CONFIG_AGC_TAB);
1015
1016 if (rtstatus != true) {
292b1192 1017 pr_err("%s(): AGC Table Fail\n", __func__);
d1585316
CL		 1018 goto phy_BB8190_Config_ParaFile_Fail;
1019 }
1020
1021 /* Check if the CCK HighPower is turned ON. */
1022 /* This is used to calculate PWDB. */
1023 rtlphy->cck_high_power = (bool)(rtl92s_phy_query_bb_reg(hw,
1024 RFPGA0_XA_HSSIPARAMETER2, 0x200));
1025
1026phy_BB8190_Config_ParaFile_Fail:
1027 return rtstatus;
1028}
1029
1030u8 rtl92s_phy_config_rf(struct ieee80211_hw *hw, enum radio_path rfpath)
1031{
1032 struct rtl_priv *rtlpriv = rtl_priv(hw);
1033 struct rtl_phy *rtlphy = &(rtlpriv->phy);
1034 int i;
1035 bool rtstatus = true;
1036 u32 *radio_a_table;
1037 u32 *radio_b_table;
1038 u16 radio_a_tblen, radio_b_tblen;
1039
1040 radio_a_tblen = RADIOA_1T_ARRAYLENGTH;
1041 radio_a_table = rtl8192seradioa_1t_array;
1042
1043 /* Using Green mode array table for RF_2T2R_GREEN */
1044 if (rtlphy->rf_type == RF_2T2R_GREEN) {
1045 radio_b_table = rtl8192seradiob_gm_array;
1046 radio_b_tblen = RADIOB_GM_ARRAYLENGTH;
1047 } else {
1048 radio_b_table = rtl8192seradiob_array;
1049 radio_b_tblen = RADIOB_ARRAYLENGTH;
1050 }
1051
f30d7507 1052 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, "Radio No %x\n", rfpath);
d1585316
CL		 1053 rtstatus = true;
1054
1055 switch (rfpath) {
1056 case RF90_PATH_A:
1057 for (i = 0; i < radio_a_tblen; i = i + 2) {
1058 if (radio_a_table[i] == 0xfe)
1059 /* Delay specific ms. Only RF configuration
1060 * requires delay. */
1061 mdelay(50);
1062 else if (radio_a_table[i] == 0xfd)
1063 mdelay(5);
1064 else if (radio_a_table[i] == 0xfc)
1065 mdelay(1);
1066 else if (radio_a_table[i] == 0xfb)
1067 udelay(50);
1068 else if (radio_a_table[i] == 0xfa)
1069 udelay(5);
1070 else if (radio_a_table[i] == 0xf9)
1071 udelay(1);
1072 else
1073 rtl92s_phy_set_rf_reg(hw, rfpath,
1074 radio_a_table[i],
1075 MASK20BITS,
1076 radio_a_table[i + 1]);
1077
1078 /* Add delay for ECS T20 & LG malow platform */
1079 udelay(1);
1080 }
1081
1082 /* PA Bias current for inferiority IC */
1083 _rtl92s_phy_config_rfpa_bias_current(hw, rfpath);
1084 break;
1085 case RF90_PATH_B:
1086 for (i = 0; i < radio_b_tblen; i = i + 2) {
1087 if (radio_b_table[i] == 0xfe)
1088 /* Delay specific ms. Only RF configuration
1089 * requires delay.*/
1090 mdelay(50);
1091 else if (radio_b_table[i] == 0xfd)
1092 mdelay(5);
1093 else if (radio_b_table[i] == 0xfc)
1094 mdelay(1);
1095 else if (radio_b_table[i] == 0xfb)
1096 udelay(50);
1097 else if (radio_b_table[i] == 0xfa)
1098 udelay(5);
1099 else if (radio_b_table[i] == 0xf9)
1100 udelay(1);
1101 else
1102 rtl92s_phy_set_rf_reg(hw, rfpath,
1103 radio_b_table[i],
1104 MASK20BITS,
1105 radio_b_table[i + 1]);
1106
1107 /* Add delay for ECS T20 & LG malow platform */
1108 udelay(1);
1109 }
1110 break;
1111 case RF90_PATH_C:
1112 ;
1113 break;
1114 case RF90_PATH_D:
1115 ;
1116 break;
1117 default:
1118 break;
1119 }
1120
1121 return rtstatus;
1122}
1123
1124
1125bool rtl92s_phy_mac_config(struct ieee80211_hw *hw)
1126{
1127 struct rtl_priv *rtlpriv = rtl_priv(hw);
1128 u32 i;
1129 u32 arraylength;
1130 u32 *ptraArray;
1131
1132 arraylength = MAC_2T_ARRAYLENGTH;
1133 ptraArray = rtl8192semac_2t_array;
1134
1135 for (i = 0; i < arraylength; i = i + 2)
1136 rtl_write_byte(rtlpriv, ptraArray[i], (u8)ptraArray[i + 1]);
1137
1138 return true;
1139}
1140
1141
1142bool rtl92s_phy_bb_config(struct ieee80211_hw *hw)
1143{
1144 struct rtl_priv *rtlpriv = rtl_priv(hw);
1145 struct rtl_phy *rtlphy = &(rtlpriv->phy);
1146 bool rtstatus = true;
1147 u8 pathmap, index, rf_num = 0;
1148 u8 path1, path2;
1149
1150 _rtl92s_phy_init_register_definition(hw);
1151
1152 /* Config BB and AGC */
1153 rtstatus = _rtl92s_phy_bb_config_parafile(hw);
1154
1155
1156 /* Check BB/RF confiuration setting. */
1157 /* We only need to configure RF which is turned on. */
1158 path1 = (u8)(rtl92s_phy_query_bb_reg(hw, RFPGA0_TXINFO, 0xf));
1159 mdelay(10);
1160 path2 = (u8)(rtl92s_phy_query_bb_reg(hw, ROFDM0_TRXPATHENABLE, 0xf));
1161 pathmap = path1 | path2;
1162
1163 rtlphy->rf_pathmap = pathmap;
1164 for (index = 0; index < 4; index++) {
1165 if ((pathmap >> index) & 0x1)
1166 rf_num++;
1167 }
1168
1169 if ((rtlphy->rf_type == RF_1T1R && rf_num != 1) ||
1170 (rtlphy->rf_type == RF_1T2R && rf_num != 2) ||
1171 (rtlphy->rf_type == RF_2T2R && rf_num != 2) ||
1172 (rtlphy->rf_type == RF_2T2R_GREEN && rf_num != 2)) {
1173 RT_TRACE(rtlpriv, COMP_INIT, DBG_EMERG,
f30d7507
JP		 1174 "RF_Type(%x) does not match RF_Num(%x)!!\n",
1175 rtlphy->rf_type, rf_num);
d1585316 1176 RT_TRACE(rtlpriv, COMP_INIT, DBG_EMERG,
f30d7507
JP		 1177 "path1 0x%x, path2 0x%x, pathmap 0x%x\n",
1178 path1, path2, pathmap);
d1585316
CL		 1179 }
1180
1181 return rtstatus;
1182}
1183
1184bool rtl92s_phy_rf_config(struct ieee80211_hw *hw)
1185{
1186 struct rtl_priv *rtlpriv = rtl_priv(hw);
1187 struct rtl_phy *rtlphy = &(rtlpriv->phy);
1188
1189 /* Initialize general global value */
1190 if (rtlphy->rf_type == RF_1T1R)
1191 rtlphy->num_total_rfpath = 1;
1192 else
1193 rtlphy->num_total_rfpath = 2;
1194
1195 /* Config BB and RF */
1196 return rtl92s_phy_rf6052_config(hw);
1197}
1198
1199void rtl92s_phy_get_hw_reg_originalvalue(struct ieee80211_hw *hw)
1200{
1201 struct rtl_priv *rtlpriv = rtl_priv(hw);
1202 struct rtl_phy *rtlphy = &(rtlpriv->phy);
1203
1204 /* read rx initial gain */
1205 rtlphy->default_initialgain[0] = rtl_get_bbreg(hw,
1206 ROFDM0_XAAGCCORE1, MASKBYTE0);
1207 rtlphy->default_initialgain[1] = rtl_get_bbreg(hw,
1208 ROFDM0_XBAGCCORE1, MASKBYTE0);
1209 rtlphy->default_initialgain[2] = rtl_get_bbreg(hw,
1210 ROFDM0_XCAGCCORE1, MASKBYTE0);
1211 rtlphy->default_initialgain[3] = rtl_get_bbreg(hw,
1212 ROFDM0_XDAGCCORE1, MASKBYTE0);
f30d7507
JP		 1213 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
1214 "Default initial gain (c50=0x%x, c58=0x%x, c60=0x%x, c68=0x%x)\n",
d1585316
CL		 1215 rtlphy->default_initialgain[0],
1216 rtlphy->default_initialgain[1],
1217 rtlphy->default_initialgain[2],
f30d7507 1218 rtlphy->default_initialgain[3]);
d1585316
CL		 1219
1220 /* read framesync */
1221 rtlphy->framesync = rtl_get_bbreg(hw, ROFDM0_RXDETECTOR3, MASKBYTE0);
1222 rtlphy->framesync_c34 = rtl_get_bbreg(hw, ROFDM0_RXDETECTOR2,
1223 MASKDWORD);
1224 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
f30d7507
JP		 1225 "Default framesync (0x%x) = 0x%x\n",
1226 ROFDM0_RXDETECTOR3, rtlphy->framesync);
d1585316
CL		 1227
1228}
1229
1230static void _rtl92s_phy_get_txpower_index(struct ieee80211_hw *hw, u8 channel,
1231 u8 *cckpowerlevel, u8 *ofdmpowerLevel)
1232{
1233 struct rtl_priv *rtlpriv = rtl_priv(hw);
1234 struct rtl_phy *rtlphy = &(rtlpriv->phy);
1235 struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
1236 u8 index = (channel - 1);
1237
1238 /* 1. CCK */
1239 /* RF-A */
1240 cckpowerlevel[0] = rtlefuse->txpwrlevel_cck[0][index];
1241 /* RF-B */
1242 cckpowerlevel[1] = rtlefuse->txpwrlevel_cck[1][index];
1243
1244 /* 2. OFDM for 1T or 2T */
1245 if (rtlphy->rf_type == RF_1T2R || rtlphy->rf_type == RF_1T1R) {
1246 /* Read HT 40 OFDM TX power */
1247 ofdmpowerLevel[0] = rtlefuse->txpwrlevel_ht40_1s[0][index];
1248 ofdmpowerLevel[1] = rtlefuse->txpwrlevel_ht40_1s[1][index];
1249 } else if (rtlphy->rf_type == RF_2T2R) {
1250 /* Read HT 40 OFDM TX power */
1251 ofdmpowerLevel[0] = rtlefuse->txpwrlevel_ht40_2s[0][index];
1252 ofdmpowerLevel[1] = rtlefuse->txpwrlevel_ht40_2s[1][index];
1253 }
1254}
1255
1256static void _rtl92s_phy_ccxpower_indexcheck(struct ieee80211_hw *hw,
1257 u8 channel, u8 *cckpowerlevel, u8 *ofdmpowerlevel)
1258{
1259 struct rtl_priv *rtlpriv = rtl_priv(hw);
1260 struct rtl_phy *rtlphy = &(rtlpriv->phy);
1261
1262 rtlphy->cur_cck_txpwridx = cckpowerlevel[0];
1263 rtlphy->cur_ofdm24g_txpwridx = ofdmpowerlevel[0];
1264}
1265
1266void rtl92s_phy_set_txpower(struct ieee80211_hw *hw, u8 channel)
1267{
1268 struct rtl_priv *rtlpriv = rtl_priv(hw);
1269 struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
1270 /* [0]:RF-A, [1]:RF-B */
1271 u8 cckpowerlevel[2], ofdmpowerLevel[2];
1272
1273 if (rtlefuse->txpwr_fromeprom == false)
1274 return;
1275
1276 /* Mainly we use RF-A Tx Power to write the Tx Power registers,
1277 * but the RF-B Tx Power must be calculated by the antenna diff.
1278 * So we have to rewrite Antenna gain offset register here.
1279 * Please refer to BB register 0x80c
1280 * 1. For CCK.
1281 * 2. For OFDM 1T or 2T */
1282 _rtl92s_phy_get_txpower_index(hw, channel, &cckpowerlevel[0],
1283 &ofdmpowerLevel[0]);
1284
1285 RT_TRACE(rtlpriv, COMP_POWER, DBG_LOUD,
f30d7507
JP		 1286 "Channel-%d, cckPowerLevel (A / B) = 0x%x / 0x%x, ofdmPowerLevel (A / B) = 0x%x / 0x%x\n",
1287 channel, cckpowerlevel[0], cckpowerlevel[1],
1288 ofdmpowerLevel[0], ofdmpowerLevel[1]);
d1585316
CL		 1289
1290 _rtl92s_phy_ccxpower_indexcheck(hw, channel, &cckpowerlevel[0],
1291 &ofdmpowerLevel[0]);
1292
1293 rtl92s_phy_rf6052_set_ccktxpower(hw, cckpowerlevel[0]);
1294 rtl92s_phy_rf6052_set_ofdmtxpower(hw, &ofdmpowerLevel[0], channel);
1295
1296}
1297
1298void rtl92s_phy_chk_fwcmd_iodone(struct ieee80211_hw *hw)
1299{
1300 struct rtl_priv *rtlpriv = rtl_priv(hw);
1301 u16 pollingcnt = 10000;
1302 u32 tmpvalue;
1303
1304 /* Make sure that CMD IO has be accepted by FW. */
1305 do {
1306 udelay(10);
1307
1308 tmpvalue = rtl_read_dword(rtlpriv, WFM5);
1309 if (tmpvalue == 0)
1310 break;
1311 } while (--pollingcnt);
1312
1313 if (pollingcnt == 0)
f30d7507 1314 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG, "Set FW Cmd fail!!\n");
d1585316
CL		 1315}
1316
1317
1318static void _rtl92s_phy_set_fwcmd_io(struct ieee80211_hw *hw)
1319{
1320 struct rtl_priv *rtlpriv = rtl_priv(hw);
1321 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
1322 struct rtl_phy *rtlphy = &(rtlpriv->phy);
1323 u32 input, current_aid = 0;
1324
1325 if (is_hal_stop(rtlhal))
1326 return;
1327
1328 /* We re-map RA related CMD IO to combinational ones */
1329 /* if FW version is v.52 or later. */
1330 switch (rtlhal->current_fwcmd_io) {
1331 case FW_CMD_RA_REFRESH_N:
1332 rtlhal->current_fwcmd_io = FW_CMD_RA_REFRESH_N_COMB;
1333 break;
1334 case FW_CMD_RA_REFRESH_BG:
1335 rtlhal->current_fwcmd_io = FW_CMD_RA_REFRESH_BG_COMB;
1336 break;
1337 default:
1338 break;
1339 }
1340
1341 switch (rtlhal->current_fwcmd_io) {
1342 case FW_CMD_RA_RESET:
f30d7507 1343 RT_TRACE(rtlpriv, COMP_CMD, DBG_DMESG, "FW_CMD_RA_RESET\n");
d1585316
CL		 1344 rtl_write_dword(rtlpriv, WFM5, FW_RA_RESET);
1345 rtl92s_phy_chk_fwcmd_iodone(hw);
1346 break;
1347 case FW_CMD_RA_ACTIVE:
f30d7507 1348 RT_TRACE(rtlpriv, COMP_CMD, DBG_DMESG, "FW_CMD_RA_ACTIVE\n");
d1585316
CL		 1349 rtl_write_dword(rtlpriv, WFM5, FW_RA_ACTIVE);
1350 rtl92s_phy_chk_fwcmd_iodone(hw);
1351 break;
1352 case FW_CMD_RA_REFRESH_N:
f30d7507 1353 RT_TRACE(rtlpriv, COMP_CMD, DBG_DMESG, "FW_CMD_RA_REFRESH_N\n");
d1585316
CL		 1354 input = FW_RA_REFRESH;
1355 rtl_write_dword(rtlpriv, WFM5, input);
1356 rtl92s_phy_chk_fwcmd_iodone(hw);
1357 rtl_write_dword(rtlpriv, WFM5, FW_RA_ENABLE_RSSI_MASK);
1358 rtl92s_phy_chk_fwcmd_iodone(hw);
1359 break;
1360 case FW_CMD_RA_REFRESH_BG:
1361 RT_TRACE(rtlpriv, COMP_CMD, DBG_DMESG,
f30d7507 1362 "FW_CMD_RA_REFRESH_BG\n");
d1585316
CL		 1363 rtl_write_dword(rtlpriv, WFM5, FW_RA_REFRESH);
1364 rtl92s_phy_chk_fwcmd_iodone(hw);
1365 rtl_write_dword(rtlpriv, WFM5, FW_RA_DISABLE_RSSI_MASK);
1366 rtl92s_phy_chk_fwcmd_iodone(hw);
1367 break;
1368 case FW_CMD_RA_REFRESH_N_COMB:
1369 RT_TRACE(rtlpriv, COMP_CMD, DBG_DMESG,
f30d7507 1370 "FW_CMD_RA_REFRESH_N_COMB\n");
d1585316
CL		 1371 input = FW_RA_IOT_N_COMB;
1372 rtl_write_dword(rtlpriv, WFM5, input);
1373 rtl92s_phy_chk_fwcmd_iodone(hw);
1374 break;
1375 case FW_CMD_RA_REFRESH_BG_COMB:
1376 RT_TRACE(rtlpriv, COMP_CMD, DBG_DMESG,
f30d7507 1377 "FW_CMD_RA_REFRESH_BG_COMB\n");
d1585316
CL		 1378 input = FW_RA_IOT_BG_COMB;
1379 rtl_write_dword(rtlpriv, WFM5, input);
1380 rtl92s_phy_chk_fwcmd_iodone(hw);
1381 break;
1382 case FW_CMD_IQK_ENABLE:
f30d7507 1383 RT_TRACE(rtlpriv, COMP_CMD, DBG_DMESG, "FW_CMD_IQK_ENABLE\n");
d1585316
CL		 1384 rtl_write_dword(rtlpriv, WFM5, FW_IQK_ENABLE);
1385 rtl92s_phy_chk_fwcmd_iodone(hw);
1386 break;
1387 case FW_CMD_PAUSE_DM_BY_SCAN:
1388 /* Lower initial gain */
1389 rtl_set_bbreg(hw, ROFDM0_XAAGCCORE1, MASKBYTE0, 0x17);
1390 rtl_set_bbreg(hw, ROFDM0_XBAGCCORE1, MASKBYTE0, 0x17);
1391 /* CCA threshold */
1392 rtl_set_bbreg(hw, RCCK0_CCA, MASKBYTE2, 0x40);
1393 break;
1394 case FW_CMD_RESUME_DM_BY_SCAN:
1395 /* CCA threshold */
1396 rtl_set_bbreg(hw, RCCK0_CCA, MASKBYTE2, 0xcd);
1397 rtl92s_phy_set_txpower(hw, rtlphy->current_channel);
1398 break;
1399 case FW_CMD_HIGH_PWR_DISABLE:
1400 if (rtlpriv->dm.dm_flag & HAL_DM_HIPWR_DISABLE)
1401 break;
1402
1403 /* Lower initial gain */
1404 rtl_set_bbreg(hw, ROFDM0_XAAGCCORE1, MASKBYTE0, 0x17);
1405 rtl_set_bbreg(hw, ROFDM0_XBAGCCORE1, MASKBYTE0, 0x17);
1406 /* CCA threshold */
1407 rtl_set_bbreg(hw, RCCK0_CCA, MASKBYTE2, 0x40);
1408 break;
1409 case FW_CMD_HIGH_PWR_ENABLE:
1410 if ((rtlpriv->dm.dm_flag & HAL_DM_HIPWR_DISABLE) ||
e10542c4 1411 rtlpriv->dm.dynamic_txpower_enable)
d1585316
CL		 1412 break;
1413
1414 /* CCA threshold */
1415 rtl_set_bbreg(hw, RCCK0_CCA, MASKBYTE2, 0xcd);
1416 break;
1417 case FW_CMD_LPS_ENTER:
f30d7507 1418 RT_TRACE(rtlpriv, COMP_CMD, DBG_DMESG, "FW_CMD_LPS_ENTER\n");
d1585316
CL		 1419 current_aid = rtlpriv->mac80211.assoc_id;
1420 rtl_write_dword(rtlpriv, WFM5, (FW_LPS_ENTER |
1421 ((current_aid | 0xc000) << 8)));
1422 rtl92s_phy_chk_fwcmd_iodone(hw);
1423 /* FW set TXOP disable here, so disable EDCA
1424 * turbo mode until driver leave LPS */
1425 break;
1426 case FW_CMD_LPS_LEAVE:
f30d7507 1427 RT_TRACE(rtlpriv, COMP_CMD, DBG_DMESG, "FW_CMD_LPS_LEAVE\n");
d1585316
CL		 1428 rtl_write_dword(rtlpriv, WFM5, FW_LPS_LEAVE);
1429 rtl92s_phy_chk_fwcmd_iodone(hw);
1430 break;
1431 case FW_CMD_ADD_A2_ENTRY:
f30d7507 1432 RT_TRACE(rtlpriv, COMP_CMD, DBG_DMESG, "FW_CMD_ADD_A2_ENTRY\n");
d1585316
CL		 1433 rtl_write_dword(rtlpriv, WFM5, FW_ADD_A2_ENTRY);
1434 rtl92s_phy_chk_fwcmd_iodone(hw);
1435 break;
1436 case FW_CMD_CTRL_DM_BY_DRIVER:
1437 RT_TRACE(rtlpriv, COMP_CMD, DBG_LOUD,
f30d7507 1438 "FW_CMD_CTRL_DM_BY_DRIVER\n");
d1585316
CL		 1439 rtl_write_dword(rtlpriv, WFM5, FW_CTRL_DM_BY_DRIVER);
1440 rtl92s_phy_chk_fwcmd_iodone(hw);
1441 break;
1442
1443 default:
1444 break;
1445 }
1446
1447 rtl92s_phy_chk_fwcmd_iodone(hw);
1448
1449 /* Clear FW CMD operation flag. */
1450 rtlhal->set_fwcmd_inprogress = false;
1451}
1452
1453bool rtl92s_phy_set_fw_cmd(struct ieee80211_hw *hw, enum fwcmd_iotype fw_cmdio)
1454{
1455 struct rtl_priv *rtlpriv = rtl_priv(hw);
1456 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
1457 struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
1458 u32 fw_param = FW_CMD_IO_PARA_QUERY(rtlpriv);
1459 u16 fw_cmdmap = FW_CMD_IO_QUERY(rtlpriv);
1460 bool bPostProcessing = false;
1461
1462 RT_TRACE(rtlpriv, COMP_CMD, DBG_LOUD,
f30d7507
JP		 1463 "Set FW Cmd(%#x), set_fwcmd_inprogress(%d)\n",
1464 fw_cmdio, rtlhal->set_fwcmd_inprogress);
d1585316
CL		 1465
1466 do {
1467 /* We re-map to combined FW CMD ones if firmware version */
1468 /* is v.53 or later. */
1469 switch (fw_cmdio) {
1470 case FW_CMD_RA_REFRESH_N:
1471 fw_cmdio = FW_CMD_RA_REFRESH_N_COMB;
1472 break;
1473 case FW_CMD_RA_REFRESH_BG:
1474 fw_cmdio = FW_CMD_RA_REFRESH_BG_COMB;
1475 break;
1476 default:
1477 break;
1478 }
1479
1480 /* If firmware version is v.62 or later,
1481 * use FW_CMD_IO_SET for FW_CMD_CTRL_DM_BY_DRIVER */
1482 if (hal_get_firmwareversion(rtlpriv) >= 0x3E) {
1483 if (fw_cmdio == FW_CMD_CTRL_DM_BY_DRIVER)
1484 fw_cmdio = FW_CMD_CTRL_DM_BY_DRIVER_NEW;
1485 }
1486
1487
1488 /* We shall revise all FW Cmd IO into Reg0x364
1489 * DM map table in the future. */
1490 switch (fw_cmdio) {
1491 case FW_CMD_RA_INIT:
f30d7507 1492 RT_TRACE(rtlpriv, COMP_CMD, DBG_LOUD, "RA init!!\n");
d1585316
CL		 1493 fw_cmdmap |= FW_RA_INIT_CTL;
1494 FW_CMD_IO_SET(rtlpriv, fw_cmdmap);
1495 /* Clear control flag to sync with FW. */
1496 FW_CMD_IO_CLR(rtlpriv, FW_RA_INIT_CTL);
1497 break;
1498 case FW_CMD_DIG_DISABLE:
1499 RT_TRACE(rtlpriv, COMP_CMD, DBG_LOUD,
f30d7507 1500 "Set DIG disable!!\n");
d1585316
CL		 1501 fw_cmdmap &= ~FW_DIG_ENABLE_CTL;
1502 FW_CMD_IO_SET(rtlpriv, fw_cmdmap);
1503 break;
1504 case FW_CMD_DIG_ENABLE:
1505 case FW_CMD_DIG_RESUME:
1506 if (!(rtlpriv->dm.dm_flag & HAL_DM_DIG_DISABLE)) {
1507 RT_TRACE(rtlpriv, COMP_CMD, DBG_LOUD,
f30d7507 1508 "Set DIG enable or resume!!\n");
d1585316
CL		 1509 fw_cmdmap |= (FW_DIG_ENABLE_CTL | FW_SS_CTL);
1510 FW_CMD_IO_SET(rtlpriv, fw_cmdmap);
1511 }
1512 break;
1513 case FW_CMD_DIG_HALT:
1514 RT_TRACE(rtlpriv, COMP_CMD, DBG_LOUD,
f30d7507 1515 "Set DIG halt!!\n");
d1585316
CL		 1516 fw_cmdmap &= ~(FW_DIG_ENABLE_CTL | FW_SS_CTL);
1517 FW_CMD_IO_SET(rtlpriv, fw_cmdmap);
1518 break;
1519 case FW_CMD_TXPWR_TRACK_THERMAL: {
1520 u8 thermalval = 0;
1521 fw_cmdmap |= FW_PWR_TRK_CTL;
1522
1523 /* Clear FW parameter in terms of thermal parts. */
1524 fw_param &= FW_PWR_TRK_PARAM_CLR;
1525
1526 thermalval = rtlpriv->dm.thermalvalue;
1527 fw_param |= ((thermalval << 24) |
1528 (rtlefuse->thermalmeter[0] << 16));
1529
1530 RT_TRACE(rtlpriv, COMP_CMD, DBG_LOUD,
f30d7507
JP		 1531 "Set TxPwr tracking!! FwCmdMap(%#x), FwParam(%#x)\n",
1532 fw_cmdmap, fw_param);
d1585316
CL		 1533
1534 FW_CMD_PARA_SET(rtlpriv, fw_param);
1535 FW_CMD_IO_SET(rtlpriv, fw_cmdmap);
1536
1537 /* Clear control flag to sync with FW. */
1538 FW_CMD_IO_CLR(rtlpriv, FW_PWR_TRK_CTL);
1539 }
1540 break;
1541 /* The following FW CMDs are only compatible to
1542 * v.53 or later. */
1543 case FW_CMD_RA_REFRESH_N_COMB:
1544 fw_cmdmap |= FW_RA_N_CTL;
1545
1546 /* Clear RA BG mode control. */
1547 fw_cmdmap &= ~(FW_RA_BG_CTL | FW_RA_INIT_CTL);
1548
1549 /* Clear FW parameter in terms of RA parts. */
1550 fw_param &= FW_RA_PARAM_CLR;
1551
1552 RT_TRACE(rtlpriv, COMP_CMD, DBG_LOUD,
f30d7507
JP		 1553 "[FW CMD] [New Version] Set RA/IOT Comb in n mode!! FwCmdMap(%#x), FwParam(%#x)\n",
1554 fw_cmdmap, fw_param);
d1585316
CL		 1555
1556 FW_CMD_PARA_SET(rtlpriv, fw_param);
1557 FW_CMD_IO_SET(rtlpriv, fw_cmdmap);
1558
1559 /* Clear control flag to sync with FW. */
1560 FW_CMD_IO_CLR(rtlpriv, FW_RA_N_CTL);
1561 break;
1562 case FW_CMD_RA_REFRESH_BG_COMB:
1563 fw_cmdmap |= FW_RA_BG_CTL;
1564
1565 /* Clear RA n-mode control. */
1566 fw_cmdmap &= ~(FW_RA_N_CTL | FW_RA_INIT_CTL);
1567 /* Clear FW parameter in terms of RA parts. */
1568 fw_param &= FW_RA_PARAM_CLR;
1569
1570 FW_CMD_PARA_SET(rtlpriv, fw_param);
1571 FW_CMD_IO_SET(rtlpriv, fw_cmdmap);
1572
1573 /* Clear control flag to sync with FW. */
1574 FW_CMD_IO_CLR(rtlpriv, FW_RA_BG_CTL);
1575 break;
1576 case FW_CMD_IQK_ENABLE:
1577 fw_cmdmap |= FW_IQK_CTL;
1578 FW_CMD_IO_SET(rtlpriv, fw_cmdmap);
1579 /* Clear control flag to sync with FW. */
1580 FW_CMD_IO_CLR(rtlpriv, FW_IQK_CTL);
1581 break;
1582 /* The following FW CMD is compatible to v.62 or later. */
1583 case FW_CMD_CTRL_DM_BY_DRIVER_NEW:
1584 fw_cmdmap |= FW_DRIVER_CTRL_DM_CTL;
1585 FW_CMD_IO_SET(rtlpriv, fw_cmdmap);
1586 break;
1587 /* The followed FW Cmds needs post-processing later. */
1588 case FW_CMD_RESUME_DM_BY_SCAN:
1589 fw_cmdmap |= (FW_DIG_ENABLE_CTL |
1590 FW_HIGH_PWR_ENABLE_CTL |
1591 FW_SS_CTL);
1592
1593 if (rtlpriv->dm.dm_flag & HAL_DM_DIG_DISABLE ||
1594 !digtable.dig_enable_flag)
1595 fw_cmdmap &= ~FW_DIG_ENABLE_CTL;
1596
1597 if ((rtlpriv->dm.dm_flag & HAL_DM_HIPWR_DISABLE) ||
e10542c4 1598 rtlpriv->dm.dynamic_txpower_enable)
d1585316
CL		 1599 fw_cmdmap &= ~FW_HIGH_PWR_ENABLE_CTL;
1600
1601 if ((digtable.dig_ext_port_stage ==
1602 DIG_EXT_PORT_STAGE_0) ||
1603 (digtable.dig_ext_port_stage ==
1604 DIG_EXT_PORT_STAGE_1))
1605 fw_cmdmap &= ~FW_DIG_ENABLE_CTL;
1606
1607 FW_CMD_IO_SET(rtlpriv, fw_cmdmap);
1608 bPostProcessing = true;
1609 break;
1610 case FW_CMD_PAUSE_DM_BY_SCAN:
1611 fw_cmdmap &= ~(FW_DIG_ENABLE_CTL |
1612 FW_HIGH_PWR_ENABLE_CTL |
1613 FW_SS_CTL);
1614 FW_CMD_IO_SET(rtlpriv, fw_cmdmap);
1615 bPostProcessing = true;
1616 break;
1617 case FW_CMD_HIGH_PWR_DISABLE:
1618 fw_cmdmap &= ~FW_HIGH_PWR_ENABLE_CTL;
1619 FW_CMD_IO_SET(rtlpriv, fw_cmdmap);
1620 bPostProcessing = true;
1621 break;
1622 case FW_CMD_HIGH_PWR_ENABLE:
1623 if (!(rtlpriv->dm.dm_flag & HAL_DM_HIPWR_DISABLE) &&
1624 (rtlpriv->dm.dynamic_txpower_enable != true)) {
1625 fw_cmdmap |= (FW_HIGH_PWR_ENABLE_CTL |
1626 FW_SS_CTL);
1627 FW_CMD_IO_SET(rtlpriv, fw_cmdmap);
1628 bPostProcessing = true;
1629 }
1630 break;
1631 case FW_CMD_DIG_MODE_FA:
1632 fw_cmdmap |= FW_FA_CTL;
1633 FW_CMD_IO_SET(rtlpriv, fw_cmdmap);
1634 break;
1635 case FW_CMD_DIG_MODE_SS:
1636 fw_cmdmap &= ~FW_FA_CTL;
1637 FW_CMD_IO_SET(rtlpriv, fw_cmdmap);
1638 break;
1639 case FW_CMD_PAPE_CONTROL:
1640 RT_TRACE(rtlpriv, COMP_CMD, DBG_LOUD,
f30d7507 1641 "[FW CMD] Set PAPE Control\n");
d1585316
CL		 1642 fw_cmdmap &= ~FW_PAPE_CTL_BY_SW_HW;
1643
1644 FW_CMD_IO_SET(rtlpriv, fw_cmdmap);
1645 break;
1646 default:
1647 /* Pass to original FW CMD processing callback
1648 * routine. */
1649 bPostProcessing = true;
1650 break;
1651 }
1652 } while (false);
1653
1654 /* We shall post processing these FW CMD if
1655 * variable bPostProcessing is set. */
1656 if (bPostProcessing && !rtlhal->set_fwcmd_inprogress) {
1657 rtlhal->set_fwcmd_inprogress = true;
1658 /* Update current FW Cmd for callback use. */
1659 rtlhal->current_fwcmd_io = fw_cmdio;
1660 } else {
1661 return false;
1662 }
1663
1664 _rtl92s_phy_set_fwcmd_io(hw);
1665 return true;
1666}
1667
1668static void _rtl92s_phy_check_ephy_switchready(struct ieee80211_hw *hw)
1669{
1670 struct rtl_priv *rtlpriv = rtl_priv(hw);
1671 u32 delay = 100;
1672 u8 regu1;
1673
1674 regu1 = rtl_read_byte(rtlpriv, 0x554);
1675 while ((regu1 & BIT(5)) && (delay > 0)) {
1676 regu1 = rtl_read_byte(rtlpriv, 0x554);
1677 delay--;
1678 /* We delay only 50us to prevent
1679 * being scheduled out. */
1680 udelay(50);
1681 }
1682}
1683
1684void rtl92s_phy_switch_ephy_parameter(struct ieee80211_hw *hw)
1685{
1686 struct rtl_priv *rtlpriv = rtl_priv(hw);
1687 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
1688
1689 /* The way to be capable to switch clock request
1690 * when the PG setting does not support clock request.
1691 * This is the backdoor solution to switch clock
1692 * request before ASPM or D3. */
1693 rtl_write_dword(rtlpriv, 0x540, 0x73c11);
1694 rtl_write_dword(rtlpriv, 0x548, 0x2407c);
1695
1696 /* Switch EPHY parameter!!!! */
1697 rtl_write_word(rtlpriv, 0x550, 0x1000);
1698 rtl_write_byte(rtlpriv, 0x554, 0x20);
1699 _rtl92s_phy_check_ephy_switchready(hw);
1700
1701 rtl_write_word(rtlpriv, 0x550, 0xa0eb);
1702 rtl_write_byte(rtlpriv, 0x554, 0x3e);
1703 _rtl92s_phy_check_ephy_switchready(hw);
1704
1705 rtl_write_word(rtlpriv, 0x550, 0xff80);
1706 rtl_write_byte(rtlpriv, 0x554, 0x39);
1707 _rtl92s_phy_check_ephy_switchready(hw);
1708
1709 /* Delay L1 enter time */
1710 if (ppsc->support_aspm && !ppsc->support_backdoor)
1711 rtl_write_byte(rtlpriv, 0x560, 0x40);
1712 else
1713 rtl_write_byte(rtlpriv, 0x560, 0x00);
1714
1715}
1716
1717void rtl92s_phy_set_beacon_hwreg(struct ieee80211_hw *hw, u16 BeaconInterval)
1718{
1719 struct rtl_priv *rtlpriv = rtl_priv(hw);
1720 rtl_write_dword(rtlpriv, WFM5, 0xF1000000 | (BeaconInterval << 8));
1721}
Linux kernel - Deliverables
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