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rtlwifi: rtl8192{c,ce,cu,se}: Remove comparisons of booleans with true
[deliverable/linux.git] / drivers / net / wireless / rtlwifi / rtl8192se / phy.c
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d1585316
CL		 1/******************************************************************************
2 *
3 * Copyright(c) 2009-2010 Realtek Corporation.
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of version 2 of the GNU General Public License as
7 * published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details.
13 *
14 * You should have received a copy of the GNU General Public License along with
15 * this program; if not, write to the Free Software Foundation, Inc.,
16 * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
17 *
18 * The full GNU General Public License is included in this distribution in the
19 * file called LICENSE.
20 *
21 * Contact Information:
22 * wlanfae <wlanfae@realtek.com>
23 * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
24 * Hsinchu 300, Taiwan.
25 *
26 * Larry Finger <Larry.Finger@lwfinger.net>
27 *
28 *****************************************************************************/
29
30#include "../wifi.h"
31#include "../pci.h"
32#include "../ps.h"
33#include "reg.h"
34#include "def.h"
35#include "phy.h"
36#include "rf.h"
37#include "dm.h"
38#include "fw.h"
39#include "hw.h"
40#include "table.h"
41
42static u32 _rtl92s_phy_calculate_bit_shift(u32 bitmask)
43{
44 u32 i;
45
46 for (i = 0; i <= 31; i++) {
47 if (((bitmask >> i) & 0x1) == 1)
48 break;
49 }
50
51 return i;
52}
53
54u32 rtl92s_phy_query_bb_reg(struct ieee80211_hw *hw, u32 regaddr, u32 bitmask)
55{
56 struct rtl_priv *rtlpriv = rtl_priv(hw);
57 u32 returnvalue = 0, originalvalue, bitshift;
58
59 RT_TRACE(rtlpriv, COMP_RF, DBG_TRACE, ("regaddr(%#x), bitmask(%#x)\n",
60 regaddr, bitmask));
61
62 originalvalue = rtl_read_dword(rtlpriv, regaddr);
63 bitshift = _rtl92s_phy_calculate_bit_shift(bitmask);
64 returnvalue = (originalvalue & bitmask) >> bitshift;
65
66 RT_TRACE(rtlpriv, COMP_RF, DBG_TRACE,
67 ("BBR MASK=0x%x Addr[0x%x]=0x%x\n",
68 bitmask, regaddr, originalvalue));
69
70 return returnvalue;
71
72}
73
74void rtl92s_phy_set_bb_reg(struct ieee80211_hw *hw, u32 regaddr, u32 bitmask,
75 u32 data)
76{
77 struct rtl_priv *rtlpriv = rtl_priv(hw);
78 u32 originalvalue, bitshift;
79
80 RT_TRACE(rtlpriv, COMP_RF, DBG_TRACE, ("regaddr(%#x), bitmask(%#x),"
81 " data(%#x)\n", regaddr, bitmask, data));
82
83 if (bitmask != MASKDWORD) {
84 originalvalue = rtl_read_dword(rtlpriv, regaddr);
85 bitshift = _rtl92s_phy_calculate_bit_shift(bitmask);
86 data = ((originalvalue & (~bitmask)) | (data << bitshift));
87 }
88
89 rtl_write_dword(rtlpriv, regaddr, data);
90
91 RT_TRACE(rtlpriv, COMP_RF, DBG_TRACE, ("regaddr(%#x), bitmask(%#x),"
92 " data(%#x)\n", regaddr, bitmask, data));
93
94}
95
96static u32 _rtl92s_phy_rf_serial_read(struct ieee80211_hw *hw,
97 enum radio_path rfpath, u32 offset)
98{
99
100 struct rtl_priv *rtlpriv = rtl_priv(hw);
101 struct rtl_phy *rtlphy = &(rtlpriv->phy);
102 struct bb_reg_def *pphyreg = &rtlphy->phyreg_def[rfpath];
103 u32 newoffset;
104 u32 tmplong, tmplong2;
105 u8 rfpi_enable = 0;
106 u32 retvalue = 0;
107
108 offset &= 0x3f;
109 newoffset = offset;
110
111 tmplong = rtl_get_bbreg(hw, RFPGA0_XA_HSSIPARAMETER2, MASKDWORD);
112
113 if (rfpath == RF90_PATH_A)
114 tmplong2 = tmplong;
115 else
116 tmplong2 = rtl_get_bbreg(hw, pphyreg->rfhssi_para2, MASKDWORD);
117
118 tmplong2 = (tmplong2 & (~BLSSI_READADDRESS)) | (newoffset << 23) |
119 BLSSI_READEDGE;
120
121 rtl_set_bbreg(hw, RFPGA0_XA_HSSIPARAMETER2, MASKDWORD,
122 tmplong & (~BLSSI_READEDGE));
123
124 mdelay(1);
125
126 rtl_set_bbreg(hw, pphyreg->rfhssi_para2, MASKDWORD, tmplong2);
127 mdelay(1);
128
129 rtl_set_bbreg(hw, RFPGA0_XA_HSSIPARAMETER2, MASKDWORD, tmplong |
130 BLSSI_READEDGE);
131 mdelay(1);
132
133 if (rfpath == RF90_PATH_A)
134 rfpi_enable = (u8)rtl_get_bbreg(hw, RFPGA0_XA_HSSIPARAMETER1,
135 BIT(8));
136 else if (rfpath == RF90_PATH_B)
137 rfpi_enable = (u8)rtl_get_bbreg(hw, RFPGA0_XB_HSSIPARAMETER1,
138 BIT(8));
139
140 if (rfpi_enable)
141 retvalue = rtl_get_bbreg(hw, pphyreg->rflssi_readbackpi,
142 BLSSI_READBACK_DATA);
143 else
144 retvalue = rtl_get_bbreg(hw, pphyreg->rflssi_readback,
145 BLSSI_READBACK_DATA);
146
147 retvalue = rtl_get_bbreg(hw, pphyreg->rflssi_readback,
148 BLSSI_READBACK_DATA);
149
150 RT_TRACE(rtlpriv, COMP_RF, DBG_TRACE, ("RFR-%d Addr[0x%x]=0x%x\n",
151 rfpath, pphyreg->rflssi_readback, retvalue));
152
153 return retvalue;
154
155}
156
157static void _rtl92s_phy_rf_serial_write(struct ieee80211_hw *hw,
158 enum radio_path rfpath, u32 offset,
159 u32 data)
160{
161 struct rtl_priv *rtlpriv = rtl_priv(hw);
162 struct rtl_phy *rtlphy = &(rtlpriv->phy);
163 struct bb_reg_def *pphyreg = &rtlphy->phyreg_def[rfpath];
164 u32 data_and_addr = 0;
165 u32 newoffset;
166
167 offset &= 0x3f;
168 newoffset = offset;
169
170 data_and_addr = ((newoffset << 20) | (data & 0x000fffff)) & 0x0fffffff;
171 rtl_set_bbreg(hw, pphyreg->rf3wire_offset, MASKDWORD, data_and_addr);
172
173 RT_TRACE(rtlpriv, COMP_RF, DBG_TRACE, ("RFW-%d Addr[0x%x]=0x%x\n",
174 rfpath, pphyreg->rf3wire_offset, data_and_addr));
175}
176
177
178u32 rtl92s_phy_query_rf_reg(struct ieee80211_hw *hw, enum radio_path rfpath,
179 u32 regaddr, u32 bitmask)
180{
181 struct rtl_priv *rtlpriv = rtl_priv(hw);
182 u32 original_value, readback_value, bitshift;
d1585316
CL		 183
184 RT_TRACE(rtlpriv, COMP_RF, DBG_TRACE, ("regaddr(%#x), rfpath(%#x), "
185 "bitmask(%#x)\n", regaddr, rfpath, bitmask));
186
312d5479 187 spin_lock(&rtlpriv->locks.rf_lock);
d1585316
CL		 188
189 original_value = _rtl92s_phy_rf_serial_read(hw, rfpath, regaddr);
190
191 bitshift = _rtl92s_phy_calculate_bit_shift(bitmask);
192 readback_value = (original_value & bitmask) >> bitshift;
193
312d5479 194 spin_unlock(&rtlpriv->locks.rf_lock);
d1585316
CL		 195
196 RT_TRACE(rtlpriv, COMP_RF, DBG_TRACE, ("regaddr(%#x), rfpath(%#x), "
197 "bitmask(%#x), original_value(%#x)\n", regaddr, rfpath,
198 bitmask, original_value));
199
200 return readback_value;
201}
202
203void rtl92s_phy_set_rf_reg(struct ieee80211_hw *hw, enum radio_path rfpath,
204 u32 regaddr, u32 bitmask, u32 data)
205{
206 struct rtl_priv *rtlpriv = rtl_priv(hw);
207 struct rtl_phy *rtlphy = &(rtlpriv->phy);
208 u32 original_value, bitshift;
d1585316
CL		 209
210 if (!((rtlphy->rf_pathmap >> rfpath) & 0x1))
211 return;
212
213 RT_TRACE(rtlpriv, COMP_RF, DBG_TRACE, ("regaddr(%#x), bitmask(%#x),"
214 " data(%#x), rfpath(%#x)\n", regaddr, bitmask, data, rfpath));
215
312d5479 216 spin_lock(&rtlpriv->locks.rf_lock);
d1585316
CL		 217
218 if (bitmask != RFREG_OFFSET_MASK) {
219 original_value = _rtl92s_phy_rf_serial_read(hw, rfpath,
220 regaddr);
221 bitshift = _rtl92s_phy_calculate_bit_shift(bitmask);
222 data = ((original_value & (~bitmask)) | (data << bitshift));
223 }
224
225 _rtl92s_phy_rf_serial_write(hw, rfpath, regaddr, data);
226
312d5479 227 spin_unlock(&rtlpriv->locks.rf_lock);
d1585316
CL		 228
229 RT_TRACE(rtlpriv, COMP_RF, DBG_TRACE, ("regaddr(%#x), bitmask(%#x), "
230 "data(%#x), rfpath(%#x)\n", regaddr, bitmask, data, rfpath));
231
232}
233
234void rtl92s_phy_scan_operation_backup(struct ieee80211_hw *hw,
235 u8 operation)
236{
237 struct rtl_priv *rtlpriv = rtl_priv(hw);
238 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
239
240 if (!is_hal_stop(rtlhal)) {
241 switch (operation) {
242 case SCAN_OPT_BACKUP:
243 rtl92s_phy_set_fw_cmd(hw, FW_CMD_PAUSE_DM_BY_SCAN);
244 break;
245 case SCAN_OPT_RESTORE:
246 rtl92s_phy_set_fw_cmd(hw, FW_CMD_RESUME_DM_BY_SCAN);
247 break;
248 default:
249 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
250 ("Unknown operation.\n"));
251 break;
252 }
253 }
254}
255
256void rtl92s_phy_set_bw_mode(struct ieee80211_hw *hw,
257 enum nl80211_channel_type ch_type)
258{
259 struct rtl_priv *rtlpriv = rtl_priv(hw);
260 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
261 struct rtl_phy *rtlphy = &(rtlpriv->phy);
262 struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
263 u8 reg_bw_opmode;
d1585316
CL		 264
265 RT_TRACE(rtlpriv, COMP_SCAN, DBG_TRACE, ("Switch to %s bandwidth\n",
266 rtlphy->current_chan_bw == HT_CHANNEL_WIDTH_20 ?
267 "20MHz" : "40MHz"));
268
269 if (rtlphy->set_bwmode_inprogress)
270 return;
271 if (is_hal_stop(rtlhal))
272 return;
273
274 rtlphy->set_bwmode_inprogress = true;
275
276 reg_bw_opmode = rtl_read_byte(rtlpriv, BW_OPMODE);
78d57372
LF		 277 /* dummy read */
278 rtl_read_byte(rtlpriv, RRSR + 2);
d1585316
CL		 279
280 switch (rtlphy->current_chan_bw) {
281 case HT_CHANNEL_WIDTH_20:
282 reg_bw_opmode |= BW_OPMODE_20MHZ;
283 rtl_write_byte(rtlpriv, BW_OPMODE, reg_bw_opmode);
284 break;
285 case HT_CHANNEL_WIDTH_20_40:
286 reg_bw_opmode &= ~BW_OPMODE_20MHZ;
287 rtl_write_byte(rtlpriv, BW_OPMODE, reg_bw_opmode);
288 break;
289 default:
290 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
291 ("unknown bandwidth: %#X\n",
292 rtlphy->current_chan_bw));
293 break;
294 }
295
296 switch (rtlphy->current_chan_bw) {
297 case HT_CHANNEL_WIDTH_20:
298 rtl_set_bbreg(hw, RFPGA0_RFMOD, BRFMOD, 0x0);
299 rtl_set_bbreg(hw, RFPGA1_RFMOD, BRFMOD, 0x0);
300
301 if (rtlhal->version >= VERSION_8192S_BCUT)
302 rtl_write_byte(rtlpriv, RFPGA0_ANALOGPARAMETER2, 0x58);
303 break;
304 case HT_CHANNEL_WIDTH_20_40:
305 rtl_set_bbreg(hw, RFPGA0_RFMOD, BRFMOD, 0x1);
306 rtl_set_bbreg(hw, RFPGA1_RFMOD, BRFMOD, 0x1);
307
308 rtl_set_bbreg(hw, RCCK0_SYSTEM, BCCK_SIDEBAND,
309 (mac->cur_40_prime_sc >> 1));
310 rtl_set_bbreg(hw, ROFDM1_LSTF, 0xC00, mac->cur_40_prime_sc);
311
312 if (rtlhal->version >= VERSION_8192S_BCUT)
313 rtl_write_byte(rtlpriv, RFPGA0_ANALOGPARAMETER2, 0x18);
314 break;
315 default:
316 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
317 ("unknown bandwidth: %#X\n", rtlphy->current_chan_bw));
318 break;
319 }
320
321 rtl92s_phy_rf6052_set_bandwidth(hw, rtlphy->current_chan_bw);
322 rtlphy->set_bwmode_inprogress = false;
323 RT_TRACE(rtlpriv, COMP_SCAN, DBG_TRACE, ("<==\n"));
324}
325
326static bool _rtl92s_phy_set_sw_chnl_cmdarray(struct swchnlcmd *cmdtable,
327 u32 cmdtableidx, u32 cmdtablesz, enum swchnlcmd_id cmdid,
328 u32 para1, u32 para2, u32 msdelay)
329{
330 struct swchnlcmd *pcmd;
331
332 if (cmdtable == NULL) {
333 RT_ASSERT(false, ("cmdtable cannot be NULL.\n"));
334 return false;
335 }
336
337 if (cmdtableidx >= cmdtablesz)
338 return false;
339
340 pcmd = cmdtable + cmdtableidx;
341 pcmd->cmdid = cmdid;
342 pcmd->para1 = para1;
343 pcmd->para2 = para2;
344 pcmd->msdelay = msdelay;
345
346 return true;
347}
348
349static bool _rtl92s_phy_sw_chnl_step_by_step(struct ieee80211_hw *hw,
350 u8 channel, u8 *stage, u8 *step, u32 *delay)
351{
352 struct rtl_priv *rtlpriv = rtl_priv(hw);
353 struct rtl_phy *rtlphy = &(rtlpriv->phy);
354 struct swchnlcmd precommoncmd[MAX_PRECMD_CNT];
355 u32 precommoncmdcnt;
356 struct swchnlcmd postcommoncmd[MAX_POSTCMD_CNT];
357 u32 postcommoncmdcnt;
358 struct swchnlcmd rfdependcmd[MAX_RFDEPENDCMD_CNT];
359 u32 rfdependcmdcnt;
360 struct swchnlcmd *currentcmd = NULL;
361 u8 rfpath;
362 u8 num_total_rfpath = rtlphy->num_total_rfpath;
363
364 precommoncmdcnt = 0;
365 _rtl92s_phy_set_sw_chnl_cmdarray(precommoncmd, precommoncmdcnt++,
366 MAX_PRECMD_CNT, CMDID_SET_TXPOWEROWER_LEVEL, 0, 0, 0);
367 _rtl92s_phy_set_sw_chnl_cmdarray(precommoncmd, precommoncmdcnt++,
368 MAX_PRECMD_CNT, CMDID_END, 0, 0, 0);
369
370 postcommoncmdcnt = 0;
371
372 _rtl92s_phy_set_sw_chnl_cmdarray(postcommoncmd, postcommoncmdcnt++,
373 MAX_POSTCMD_CNT, CMDID_END, 0, 0, 0);
374
375 rfdependcmdcnt = 0;
376
377 RT_ASSERT((channel >= 1 && channel <= 14),
378 ("illegal channel for Zebra: %d\n", channel));
379
380 _rtl92s_phy_set_sw_chnl_cmdarray(rfdependcmd, rfdependcmdcnt++,
381 MAX_RFDEPENDCMD_CNT, CMDID_RF_WRITEREG,
382 RF_CHNLBW, channel, 10);
383
384 _rtl92s_phy_set_sw_chnl_cmdarray(rfdependcmd, rfdependcmdcnt++,
385 MAX_RFDEPENDCMD_CNT, CMDID_END, 0, 0, 0);
386
387 do {
388 switch (*stage) {
389 case 0:
390 currentcmd = &precommoncmd[*step];
391 break;
392 case 1:
393 currentcmd = &rfdependcmd[*step];
394 break;
395 case 2:
396 currentcmd = &postcommoncmd[*step];
397 break;
398 }
399
400 if (currentcmd->cmdid == CMDID_END) {
401 if ((*stage) == 2) {
402 return true;
403 } else {
404 (*stage)++;
405 (*step) = 0;
406 continue;
407 }
408 }
409
410 switch (currentcmd->cmdid) {
411 case CMDID_SET_TXPOWEROWER_LEVEL:
412 rtl92s_phy_set_txpower(hw, channel);
413 break;
414 case CMDID_WRITEPORT_ULONG:
415 rtl_write_dword(rtlpriv, currentcmd->para1,
416 currentcmd->para2);
417 break;
418 case CMDID_WRITEPORT_USHORT:
419 rtl_write_word(rtlpriv, currentcmd->para1,
420 (u16)currentcmd->para2);
421 break;
422 case CMDID_WRITEPORT_UCHAR:
423 rtl_write_byte(rtlpriv, currentcmd->para1,
424 (u8)currentcmd->para2);
425 break;
426 case CMDID_RF_WRITEREG:
427 for (rfpath = 0; rfpath < num_total_rfpath; rfpath++) {
428 rtlphy->rfreg_chnlval[rfpath] =
429 ((rtlphy->rfreg_chnlval[rfpath] &
430 0xfffffc00) | currentcmd->para2);
431 rtl_set_rfreg(hw, (enum radio_path)rfpath,
432 currentcmd->para1,
433 RFREG_OFFSET_MASK,
434 rtlphy->rfreg_chnlval[rfpath]);
435 }
436 break;
437 default:
438 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
439 ("switch case not process\n"));
440 break;
441 }
442
443 break;
444 } while (true);
445
446 (*delay) = currentcmd->msdelay;
447 (*step)++;
448 return false;
449}
450
451u8 rtl92s_phy_sw_chnl(struct ieee80211_hw *hw)
452{
453 struct rtl_priv *rtlpriv = rtl_priv(hw);
454 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
455 struct rtl_phy *rtlphy = &(rtlpriv->phy);
456 u32 delay;
457 bool ret;
458
459 RT_TRACE(rtlpriv, COMP_SCAN, DBG_TRACE,
460 ("switch to channel%d\n",
461 rtlphy->current_channel));
462
463 if (rtlphy->sw_chnl_inprogress)
464 return 0;
465
466 if (rtlphy->set_bwmode_inprogress)
467 return 0;
468
469 if (is_hal_stop(rtlhal))
470 return 0;
471
472 rtlphy->sw_chnl_inprogress = true;
473 rtlphy->sw_chnl_stage = 0;
474 rtlphy->sw_chnl_step = 0;
475
476 do {
477 if (!rtlphy->sw_chnl_inprogress)
478 break;
479
480 ret = _rtl92s_phy_sw_chnl_step_by_step(hw,
481 rtlphy->current_channel,
482 &rtlphy->sw_chnl_stage,
483 &rtlphy->sw_chnl_step, &delay);
484 if (!ret) {
485 if (delay > 0)
486 mdelay(delay);
487 else
488 continue;
489 } else {
490 rtlphy->sw_chnl_inprogress = false;
491 }
492 break;
493 } while (true);
494
495 rtlphy->sw_chnl_inprogress = false;
496
497 RT_TRACE(rtlpriv, COMP_SCAN, DBG_TRACE, ("<==\n"));
498
499 return 1;
500}
501
502static void _rtl92se_phy_set_rf_sleep(struct ieee80211_hw *hw)
503{
504 struct rtl_priv *rtlpriv = rtl_priv(hw);
505 u8 u1btmp;
506
507 u1btmp = rtl_read_byte(rtlpriv, LDOV12D_CTRL);
508 u1btmp |= BIT(0);
509
510 rtl_write_byte(rtlpriv, LDOV12D_CTRL, u1btmp);
511 rtl_write_byte(rtlpriv, SPS1_CTRL, 0x0);
512 rtl_write_byte(rtlpriv, TXPAUSE, 0xFF);
513 rtl_write_word(rtlpriv, CMDR, 0x57FC);
514 udelay(100);
515
516 rtl_write_word(rtlpriv, CMDR, 0x77FC);
517 rtl_write_byte(rtlpriv, PHY_CCA, 0x0);
518 udelay(10);
519
520 rtl_write_word(rtlpriv, CMDR, 0x37FC);
521 udelay(10);
522
523 rtl_write_word(rtlpriv, CMDR, 0x77FC);
524 udelay(10);
525
526 rtl_write_word(rtlpriv, CMDR, 0x57FC);
527
528 /* we should chnge GPIO to input mode
529 * this will drop away current about 25mA*/
530 rtl8192se_gpiobit3_cfg_inputmode(hw);
531}
532
533bool rtl92s_phy_set_rf_power_state(struct ieee80211_hw *hw,
534 enum rf_pwrstate rfpwr_state)
535{
536 struct rtl_priv *rtlpriv = rtl_priv(hw);
537 struct rtl_pci_priv *pcipriv = rtl_pcipriv(hw);
538 struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
539 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
540 bool bresult = true;
541 u8 i, queue_id;
542 struct rtl8192_tx_ring *ring = NULL;
543
544 if (rfpwr_state == ppsc->rfpwr_state)
545 return false;
546
d1585316
CL		 547 switch (rfpwr_state) {
548 case ERFON:{
549 if ((ppsc->rfpwr_state == ERFOFF) &&
550 RT_IN_PS_LEVEL(ppsc, RT_RF_OFF_LEVL_HALT_NIC)) {
551
552 bool rtstatus;
553 u32 InitializeCount = 0;
554 do {
555 InitializeCount++;
556 RT_TRACE(rtlpriv, COMP_RF, DBG_DMESG,
557 ("IPS Set eRf nic enable\n"));
558 rtstatus = rtl_ps_enable_nic(hw);
559 } while ((rtstatus != true) &&
560 (InitializeCount < 10));
561
562 RT_CLEAR_PS_LEVEL(ppsc,
563 RT_RF_OFF_LEVL_HALT_NIC);
564 } else {
565 RT_TRACE(rtlpriv, COMP_POWER, DBG_DMESG,
566 ("awake, sleeped:%d ms "
567 "state_inap:%x\n",
568 jiffies_to_msecs(jiffies -
569 ppsc->last_sleep_jiffies),
570 rtlpriv->psc.state_inap));
571 ppsc->last_awake_jiffies = jiffies;
572 rtl_write_word(rtlpriv, CMDR, 0x37FC);
573 rtl_write_byte(rtlpriv, TXPAUSE, 0x00);
574 rtl_write_byte(rtlpriv, PHY_CCA, 0x3);
575 }
576
577 if (mac->link_state == MAC80211_LINKED)
578 rtlpriv->cfg->ops->led_control(hw,
579 LED_CTL_LINK);
580 else
581 rtlpriv->cfg->ops->led_control(hw,
582 LED_CTL_NO_LINK);
583 break;
584 }
585 case ERFOFF:{
586 if (ppsc->reg_rfps_level & RT_RF_OFF_LEVL_HALT_NIC) {
587 RT_TRACE(rtlpriv, COMP_RF, DBG_DMESG,
588 ("IPS Set eRf nic disable\n"));
589 rtl_ps_disable_nic(hw);
590 RT_SET_PS_LEVEL(ppsc, RT_RF_OFF_LEVL_HALT_NIC);
591 } else {
592 if (ppsc->rfoff_reason == RF_CHANGE_BY_IPS)
593 rtlpriv->cfg->ops->led_control(hw,
594 LED_CTL_NO_LINK);
595 else
596 rtlpriv->cfg->ops->led_control(hw,
597 LED_CTL_POWER_OFF);
598 }
599 break;
600 }
601 case ERFSLEEP:
602 if (ppsc->rfpwr_state == ERFOFF)
603 break;
604
605 for (queue_id = 0, i = 0;
606 queue_id < RTL_PCI_MAX_TX_QUEUE_COUNT;) {
607 ring = &pcipriv->dev.tx_ring[queue_id];
608 if (skb_queue_len(&ring->queue) == 0 ||
609 queue_id == BEACON_QUEUE) {
610 queue_id++;
611 continue;
612 } else {
613 RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING,
614 ("eRf Off/Sleep: "
615 "%d times TcbBusyQueue[%d] = "
616 "%d before doze!\n",
617 (i + 1), queue_id,
618 skb_queue_len(&ring->queue)));
619
620 udelay(10);
621 i++;
622 }
623
624 if (i >= MAX_DOZE_WAITING_TIMES_9x) {
625 RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING,
626 ("\nERFOFF: %d times"
627 "TcbBusyQueue[%d] = %d !\n",
628 MAX_DOZE_WAITING_TIMES_9x,
629 queue_id,
630 skb_queue_len(&ring->queue)));
631 break;
632 }
633 }
634
635 RT_TRACE(rtlpriv, COMP_POWER, DBG_DMESG,
636 ("Set ERFSLEEP awaked:%d ms\n",
637 jiffies_to_msecs(jiffies -
638 ppsc->last_awake_jiffies)));
639
640 RT_TRACE(rtlpriv, COMP_POWER, DBG_DMESG,
641 ("sleep awaked:%d ms "
642 "state_inap:%x\n", jiffies_to_msecs(jiffies -
643 ppsc->last_awake_jiffies),
644 rtlpriv->psc.state_inap));
645 ppsc->last_sleep_jiffies = jiffies;
646 _rtl92se_phy_set_rf_sleep(hw);
647 break;
648 default:
649 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
650 ("switch case not process\n"));
651 bresult = false;
652 break;
653 }
654
655 if (bresult)
656 ppsc->rfpwr_state = rfpwr_state;
657
d1585316
CL		 658 return bresult;
659}
660
661static bool _rtl92s_phy_config_rfpa_bias_current(struct ieee80211_hw *hw,
662 enum radio_path rfpath)
663{
664 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
665 bool rtstatus = true;
666 u32 tmpval = 0;
667
668 /* If inferiority IC, we have to increase the PA bias current */
669 if (rtlhal->ic_class != IC_INFERIORITY_A) {
670 tmpval = rtl92s_phy_query_rf_reg(hw, rfpath, RF_IPA, 0xf);
671 rtl92s_phy_set_rf_reg(hw, rfpath, RF_IPA, 0xf, tmpval + 1);
672 }
673
674 return rtstatus;
675}
676
677static void _rtl92s_store_pwrindex_diffrate_offset(struct ieee80211_hw *hw,
678 u32 reg_addr, u32 bitmask, u32 data)
679{
680 struct rtl_priv *rtlpriv = rtl_priv(hw);
681 struct rtl_phy *rtlphy = &(rtlpriv->phy);
682
683 if (reg_addr == RTXAGC_RATE18_06)
684 rtlphy->mcs_txpwrlevel_origoffset[rtlphy->pwrgroup_cnt][0] =
685 data;
686 if (reg_addr == RTXAGC_RATE54_24)
687 rtlphy->mcs_txpwrlevel_origoffset[rtlphy->pwrgroup_cnt][1] =
688 data;
689 if (reg_addr == RTXAGC_CCK_MCS32)
690 rtlphy->mcs_txpwrlevel_origoffset[rtlphy->pwrgroup_cnt][6] =
691 data;
692 if (reg_addr == RTXAGC_MCS03_MCS00)
693 rtlphy->mcs_txpwrlevel_origoffset[rtlphy->pwrgroup_cnt][2] =
694 data;
695 if (reg_addr == RTXAGC_MCS07_MCS04)
696 rtlphy->mcs_txpwrlevel_origoffset[rtlphy->pwrgroup_cnt][3] =
697 data;
698 if (reg_addr == RTXAGC_MCS11_MCS08)
699 rtlphy->mcs_txpwrlevel_origoffset[rtlphy->pwrgroup_cnt][4] =
700 data;
701 if (reg_addr == RTXAGC_MCS15_MCS12) {
702 rtlphy->mcs_txpwrlevel_origoffset[rtlphy->pwrgroup_cnt][5] =
703 data;
704 rtlphy->pwrgroup_cnt++;
705 }
706}
707
708static void _rtl92s_phy_init_register_definition(struct ieee80211_hw *hw)
709{
710 struct rtl_priv *rtlpriv = rtl_priv(hw);
711 struct rtl_phy *rtlphy = &(rtlpriv->phy);
712
713 /*RF Interface Sowrtware Control */
714 rtlphy->phyreg_def[RF90_PATH_A].rfintfs = RFPGA0_XAB_RFINTERFACESW;
715 rtlphy->phyreg_def[RF90_PATH_B].rfintfs = RFPGA0_XAB_RFINTERFACESW;
716 rtlphy->phyreg_def[RF90_PATH_C].rfintfs = RFPGA0_XCD_RFINTERFACESW;
717 rtlphy->phyreg_def[RF90_PATH_D].rfintfs = RFPGA0_XCD_RFINTERFACESW;
718
719 /* RF Interface Readback Value */
720 rtlphy->phyreg_def[RF90_PATH_A].rfintfi = RFPGA0_XAB_RFINTERFACERB;
721 rtlphy->phyreg_def[RF90_PATH_B].rfintfi = RFPGA0_XAB_RFINTERFACERB;
722 rtlphy->phyreg_def[RF90_PATH_C].rfintfi = RFPGA0_XCD_RFINTERFACERB;
723 rtlphy->phyreg_def[RF90_PATH_D].rfintfi = RFPGA0_XCD_RFINTERFACERB;
724
725 /* RF Interface Output (and Enable) */
726 rtlphy->phyreg_def[RF90_PATH_A].rfintfo = RFPGA0_XA_RFINTERFACEOE;
727 rtlphy->phyreg_def[RF90_PATH_B].rfintfo = RFPGA0_XB_RFINTERFACEOE;
728 rtlphy->phyreg_def[RF90_PATH_C].rfintfo = RFPGA0_XC_RFINTERFACEOE;
729 rtlphy->phyreg_def[RF90_PATH_D].rfintfo = RFPGA0_XD_RFINTERFACEOE;
730
731 /* RF Interface (Output and) Enable */
732 rtlphy->phyreg_def[RF90_PATH_A].rfintfe = RFPGA0_XA_RFINTERFACEOE;
733 rtlphy->phyreg_def[RF90_PATH_B].rfintfe = RFPGA0_XB_RFINTERFACEOE;
734 rtlphy->phyreg_def[RF90_PATH_C].rfintfe = RFPGA0_XC_RFINTERFACEOE;
735 rtlphy->phyreg_def[RF90_PATH_D].rfintfe = RFPGA0_XD_RFINTERFACEOE;
736
737 /* Addr of LSSI. Wirte RF register by driver */
738 rtlphy->phyreg_def[RF90_PATH_A].rf3wire_offset =
739 RFPGA0_XA_LSSIPARAMETER;
740 rtlphy->phyreg_def[RF90_PATH_B].rf3wire_offset =
741 RFPGA0_XB_LSSIPARAMETER;
742 rtlphy->phyreg_def[RF90_PATH_C].rf3wire_offset =
743 RFPGA0_XC_LSSIPARAMETER;
744 rtlphy->phyreg_def[RF90_PATH_D].rf3wire_offset =
745 RFPGA0_XD_LSSIPARAMETER;
746
747 /* RF parameter */
748 rtlphy->phyreg_def[RF90_PATH_A].rflssi_select = RFPGA0_XAB_RFPARAMETER;
749 rtlphy->phyreg_def[RF90_PATH_B].rflssi_select = RFPGA0_XAB_RFPARAMETER;
750 rtlphy->phyreg_def[RF90_PATH_C].rflssi_select = RFPGA0_XCD_RFPARAMETER;
751 rtlphy->phyreg_def[RF90_PATH_D].rflssi_select = RFPGA0_XCD_RFPARAMETER;
752
753 /* Tx AGC Gain Stage (same for all path. Should we remove this?) */
754 rtlphy->phyreg_def[RF90_PATH_A].rftxgain_stage = RFPGA0_TXGAINSTAGE;
755 rtlphy->phyreg_def[RF90_PATH_B].rftxgain_stage = RFPGA0_TXGAINSTAGE;
756 rtlphy->phyreg_def[RF90_PATH_C].rftxgain_stage = RFPGA0_TXGAINSTAGE;
757 rtlphy->phyreg_def[RF90_PATH_D].rftxgain_stage = RFPGA0_TXGAINSTAGE;
758
759 /* Tranceiver A~D HSSI Parameter-1 */
760 rtlphy->phyreg_def[RF90_PATH_A].rfhssi_para1 = RFPGA0_XA_HSSIPARAMETER1;
761 rtlphy->phyreg_def[RF90_PATH_B].rfhssi_para1 = RFPGA0_XB_HSSIPARAMETER1;
762 rtlphy->phyreg_def[RF90_PATH_C].rfhssi_para1 = RFPGA0_XC_HSSIPARAMETER1;
763 rtlphy->phyreg_def[RF90_PATH_D].rfhssi_para1 = RFPGA0_XD_HSSIPARAMETER1;
764
765 /* Tranceiver A~D HSSI Parameter-2 */
766 rtlphy->phyreg_def[RF90_PATH_A].rfhssi_para2 = RFPGA0_XA_HSSIPARAMETER2;
767 rtlphy->phyreg_def[RF90_PATH_B].rfhssi_para2 = RFPGA0_XB_HSSIPARAMETER2;
768 rtlphy->phyreg_def[RF90_PATH_C].rfhssi_para2 = RFPGA0_XC_HSSIPARAMETER2;
769 rtlphy->phyreg_def[RF90_PATH_D].rfhssi_para2 = RFPGA0_XD_HSSIPARAMETER2;
770
771 /* RF switch Control */
772 rtlphy->phyreg_def[RF90_PATH_A].rfswitch_control =
773 RFPGA0_XAB_SWITCHCONTROL;
774 rtlphy->phyreg_def[RF90_PATH_B].rfswitch_control =
775 RFPGA0_XAB_SWITCHCONTROL;
776 rtlphy->phyreg_def[RF90_PATH_C].rfswitch_control =
777 RFPGA0_XCD_SWITCHCONTROL;
778 rtlphy->phyreg_def[RF90_PATH_D].rfswitch_control =
779 RFPGA0_XCD_SWITCHCONTROL;
780
781 /* AGC control 1 */
782 rtlphy->phyreg_def[RF90_PATH_A].rfagc_control1 = ROFDM0_XAAGCCORE1;
783 rtlphy->phyreg_def[RF90_PATH_B].rfagc_control1 = ROFDM0_XBAGCCORE1;
784 rtlphy->phyreg_def[RF90_PATH_C].rfagc_control1 = ROFDM0_XCAGCCORE1;
785 rtlphy->phyreg_def[RF90_PATH_D].rfagc_control1 = ROFDM0_XDAGCCORE1;
786
787 /* AGC control 2 */
788 rtlphy->phyreg_def[RF90_PATH_A].rfagc_control2 = ROFDM0_XAAGCCORE2;
789 rtlphy->phyreg_def[RF90_PATH_B].rfagc_control2 = ROFDM0_XBAGCCORE2;
790 rtlphy->phyreg_def[RF90_PATH_C].rfagc_control2 = ROFDM0_XCAGCCORE2;
791 rtlphy->phyreg_def[RF90_PATH_D].rfagc_control2 = ROFDM0_XDAGCCORE2;
792
793 /* RX AFE control 1 */
794 rtlphy->phyreg_def[RF90_PATH_A].rfrxiq_imbalance =
795 ROFDM0_XARXIQIMBALANCE;
796 rtlphy->phyreg_def[RF90_PATH_B].rfrxiq_imbalance =
797 ROFDM0_XBRXIQIMBALANCE;
798 rtlphy->phyreg_def[RF90_PATH_C].rfrxiq_imbalance =
799 ROFDM0_XCRXIQIMBALANCE;
800 rtlphy->phyreg_def[RF90_PATH_D].rfrxiq_imbalance =
801 ROFDM0_XDRXIQIMBALANCE;
802
803 /* RX AFE control 1 */
804 rtlphy->phyreg_def[RF90_PATH_A].rfrx_afe = ROFDM0_XARXAFE;
805 rtlphy->phyreg_def[RF90_PATH_B].rfrx_afe = ROFDM0_XBRXAFE;
806 rtlphy->phyreg_def[RF90_PATH_C].rfrx_afe = ROFDM0_XCRXAFE;
807 rtlphy->phyreg_def[RF90_PATH_D].rfrx_afe = ROFDM0_XDRXAFE;
808
809 /* Tx AFE control 1 */
810 rtlphy->phyreg_def[RF90_PATH_A].rftxiq_imbalance =
811 ROFDM0_XATXIQIMBALANCE;
812 rtlphy->phyreg_def[RF90_PATH_B].rftxiq_imbalance =
813 ROFDM0_XBTXIQIMBALANCE;
814 rtlphy->phyreg_def[RF90_PATH_C].rftxiq_imbalance =
815 ROFDM0_XCTXIQIMBALANCE;
816 rtlphy->phyreg_def[RF90_PATH_D].rftxiq_imbalance =
817 ROFDM0_XDTXIQIMBALANCE;
818
819 /* Tx AFE control 2 */
820 rtlphy->phyreg_def[RF90_PATH_A].rftx_afe = ROFDM0_XATXAFE;
821 rtlphy->phyreg_def[RF90_PATH_B].rftx_afe = ROFDM0_XBTXAFE;
822 rtlphy->phyreg_def[RF90_PATH_C].rftx_afe = ROFDM0_XCTXAFE;
823 rtlphy->phyreg_def[RF90_PATH_D].rftx_afe = ROFDM0_XDTXAFE;
824
825 /* Tranceiver LSSI Readback */
826 rtlphy->phyreg_def[RF90_PATH_A].rflssi_readback =
827 RFPGA0_XA_LSSIREADBACK;
828 rtlphy->phyreg_def[RF90_PATH_B].rflssi_readback =
829 RFPGA0_XB_LSSIREADBACK;
830 rtlphy->phyreg_def[RF90_PATH_C].rflssi_readback =
831 RFPGA0_XC_LSSIREADBACK;
832 rtlphy->phyreg_def[RF90_PATH_D].rflssi_readback =
833 RFPGA0_XD_LSSIREADBACK;
834
835 /* Tranceiver LSSI Readback PI mode */
836 rtlphy->phyreg_def[RF90_PATH_A].rflssi_readbackpi =
837 TRANSCEIVERA_HSPI_READBACK;
838 rtlphy->phyreg_def[RF90_PATH_B].rflssi_readbackpi =
839 TRANSCEIVERB_HSPI_READBACK;
840}
841
842
843static bool _rtl92s_phy_config_bb(struct ieee80211_hw *hw, u8 configtype)
844{
845 int i;
846 u32 *phy_reg_table;
847 u32 *agc_table;
848 u16 phy_reg_len, agc_len;
849
850 agc_len = AGCTAB_ARRAYLENGTH;
851 agc_table = rtl8192seagctab_array;
852 /* Default RF_type: 2T2R */
853 phy_reg_len = PHY_REG_2T2RARRAYLENGTH;
854 phy_reg_table = rtl8192sephy_reg_2t2rarray;
855
856 if (configtype == BASEBAND_CONFIG_PHY_REG) {
857 for (i = 0; i < phy_reg_len; i = i + 2) {
858 if (phy_reg_table[i] == 0xfe)
859 mdelay(50);
860 else if (phy_reg_table[i] == 0xfd)
861 mdelay(5);
862 else if (phy_reg_table[i] == 0xfc)
863 mdelay(1);
864 else if (phy_reg_table[i] == 0xfb)
865 udelay(50);
866 else if (phy_reg_table[i] == 0xfa)
867 udelay(5);
868 else if (phy_reg_table[i] == 0xf9)
869 udelay(1);
870
871 /* Add delay for ECS T20 & LG malow platform, */
872 udelay(1);
873
874 rtl92s_phy_set_bb_reg(hw, phy_reg_table[i], MASKDWORD,
875 phy_reg_table[i + 1]);
876 }
877 } else if (configtype == BASEBAND_CONFIG_AGC_TAB) {
878 for (i = 0; i < agc_len; i = i + 2) {
879 rtl92s_phy_set_bb_reg(hw, agc_table[i], MASKDWORD,
880 agc_table[i + 1]);
881
882 /* Add delay for ECS T20 & LG malow platform */
883 udelay(1);
884 }
885 }
886
887 return true;
888}
889
890static bool _rtl92s_phy_set_bb_to_diff_rf(struct ieee80211_hw *hw,
891 u8 configtype)
892{
893 struct rtl_priv *rtlpriv = rtl_priv(hw);
894 struct rtl_phy *rtlphy = &(rtlpriv->phy);
895 u32 *phy_regarray2xtxr_table;
896 u16 phy_regarray2xtxr_len;
897 int i;
898
899 if (rtlphy->rf_type == RF_1T1R) {
900 phy_regarray2xtxr_table = rtl8192sephy_changeto_1t1rarray;
901 phy_regarray2xtxr_len = PHY_CHANGETO_1T1RARRAYLENGTH;
902 } else if (rtlphy->rf_type == RF_1T2R) {
903 phy_regarray2xtxr_table = rtl8192sephy_changeto_1t2rarray;
904 phy_regarray2xtxr_len = PHY_CHANGETO_1T2RARRAYLENGTH;
905 } else {
906 return false;
907 }
908
909 if (configtype == BASEBAND_CONFIG_PHY_REG) {
910 for (i = 0; i < phy_regarray2xtxr_len; i = i + 3) {
911 if (phy_regarray2xtxr_table[i] == 0xfe)
912 mdelay(50);
913 else if (phy_regarray2xtxr_table[i] == 0xfd)
914 mdelay(5);
915 else if (phy_regarray2xtxr_table[i] == 0xfc)
916 mdelay(1);
917 else if (phy_regarray2xtxr_table[i] == 0xfb)
918 udelay(50);
919 else if (phy_regarray2xtxr_table[i] == 0xfa)
920 udelay(5);
921 else if (phy_regarray2xtxr_table[i] == 0xf9)
922 udelay(1);
923
924 rtl92s_phy_set_bb_reg(hw, phy_regarray2xtxr_table[i],
925 phy_regarray2xtxr_table[i + 1],
926 phy_regarray2xtxr_table[i + 2]);
927 }
928 }
929
930 return true;
931}
932
933static bool _rtl92s_phy_config_bb_with_pg(struct ieee80211_hw *hw,
934 u8 configtype)
935{
936 int i;
937 u32 *phy_table_pg;
938 u16 phy_pg_len;
939
940 phy_pg_len = PHY_REG_ARRAY_PGLENGTH;
941 phy_table_pg = rtl8192sephy_reg_array_pg;
942
943 if (configtype == BASEBAND_CONFIG_PHY_REG) {
944 for (i = 0; i < phy_pg_len; i = i + 3) {
945 if (phy_table_pg[i] == 0xfe)
946 mdelay(50);
947 else if (phy_table_pg[i] == 0xfd)
948 mdelay(5);
949 else if (phy_table_pg[i] == 0xfc)
950 mdelay(1);
951 else if (phy_table_pg[i] == 0xfb)
952 udelay(50);
953 else if (phy_table_pg[i] == 0xfa)
954 udelay(5);
955 else if (phy_table_pg[i] == 0xf9)
956 udelay(1);
957
958 _rtl92s_store_pwrindex_diffrate_offset(hw,
959 phy_table_pg[i],
960 phy_table_pg[i + 1],
961 phy_table_pg[i + 2]);
962 rtl92s_phy_set_bb_reg(hw, phy_table_pg[i],
963 phy_table_pg[i + 1],
964 phy_table_pg[i + 2]);
965 }
966 }
967
968 return true;
969}
970
971static bool _rtl92s_phy_bb_config_parafile(struct ieee80211_hw *hw)
972{
973 struct rtl_priv *rtlpriv = rtl_priv(hw);
974 struct rtl_phy *rtlphy = &(rtlpriv->phy);
975 struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
976 bool rtstatus = true;
977
978 /* 1. Read PHY_REG.TXT BB INIT!! */
979 /* We will separate as 1T1R/1T2R/1T2R_GREEN/2T2R */
980 if (rtlphy->rf_type == RF_1T2R || rtlphy->rf_type == RF_2T2R ||
981 rtlphy->rf_type == RF_1T1R || rtlphy->rf_type == RF_2T2R_GREEN) {
982 rtstatus = _rtl92s_phy_config_bb(hw, BASEBAND_CONFIG_PHY_REG);
983
984 if (rtlphy->rf_type != RF_2T2R &&
985 rtlphy->rf_type != RF_2T2R_GREEN)
986 /* so we should reconfig BB reg with the right
987 * PHY parameters. */
988 rtstatus = _rtl92s_phy_set_bb_to_diff_rf(hw,
989 BASEBAND_CONFIG_PHY_REG);
990 } else {
991 rtstatus = false;
992 }
993
994 if (rtstatus != true) {
995 RT_TRACE(rtlpriv, COMP_INIT, DBG_EMERG,
996 ("Write BB Reg Fail!!"));
997 goto phy_BB8190_Config_ParaFile_Fail;
998 }
999
1000 /* 2. If EEPROM or EFUSE autoload OK, We must config by
1001 * PHY_REG_PG.txt */
1002 if (rtlefuse->autoload_failflag == false) {
1003 rtlphy->pwrgroup_cnt = 0;
1004
1005 rtstatus = _rtl92s_phy_config_bb_with_pg(hw,
1006 BASEBAND_CONFIG_PHY_REG);
1007 }
1008 if (rtstatus != true) {
1009 RT_TRACE(rtlpriv, COMP_INIT, DBG_EMERG,
1010 ("_rtl92s_phy_bb_config_parafile(): "
1011 "BB_PG Reg Fail!!"));
1012 goto phy_BB8190_Config_ParaFile_Fail;
1013 }
1014
1015 /* 3. BB AGC table Initialization */
1016 rtstatus = _rtl92s_phy_config_bb(hw, BASEBAND_CONFIG_AGC_TAB);
1017
1018 if (rtstatus != true) {
1019 printk(KERN_ERR "_rtl92s_phy_bb_config_parafile(): "
1020 "AGC Table Fail\n");
1021 goto phy_BB8190_Config_ParaFile_Fail;
1022 }
1023
1024 /* Check if the CCK HighPower is turned ON. */
1025 /* This is used to calculate PWDB. */
1026 rtlphy->cck_high_power = (bool)(rtl92s_phy_query_bb_reg(hw,
1027 RFPGA0_XA_HSSIPARAMETER2, 0x200));
1028
1029phy_BB8190_Config_ParaFile_Fail:
1030 return rtstatus;
1031}
1032
1033u8 rtl92s_phy_config_rf(struct ieee80211_hw *hw, enum radio_path rfpath)
1034{
1035 struct rtl_priv *rtlpriv = rtl_priv(hw);
1036 struct rtl_phy *rtlphy = &(rtlpriv->phy);
1037 int i;
1038 bool rtstatus = true;
1039 u32 *radio_a_table;
1040 u32 *radio_b_table;
1041 u16 radio_a_tblen, radio_b_tblen;
1042
1043 radio_a_tblen = RADIOA_1T_ARRAYLENGTH;
1044 radio_a_table = rtl8192seradioa_1t_array;
1045
1046 /* Using Green mode array table for RF_2T2R_GREEN */
1047 if (rtlphy->rf_type == RF_2T2R_GREEN) {
1048 radio_b_table = rtl8192seradiob_gm_array;
1049 radio_b_tblen = RADIOB_GM_ARRAYLENGTH;
1050 } else {
1051 radio_b_table = rtl8192seradiob_array;
1052 radio_b_tblen = RADIOB_ARRAYLENGTH;
1053 }
1054
1055 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, ("Radio No %x\n", rfpath));
1056 rtstatus = true;
1057
1058 switch (rfpath) {
1059 case RF90_PATH_A:
1060 for (i = 0; i < radio_a_tblen; i = i + 2) {
1061 if (radio_a_table[i] == 0xfe)
1062 /* Delay specific ms. Only RF configuration
1063 * requires delay. */
1064 mdelay(50);
1065 else if (radio_a_table[i] == 0xfd)
1066 mdelay(5);
1067 else if (radio_a_table[i] == 0xfc)
1068 mdelay(1);
1069 else if (radio_a_table[i] == 0xfb)
1070 udelay(50);
1071 else if (radio_a_table[i] == 0xfa)
1072 udelay(5);
1073 else if (radio_a_table[i] == 0xf9)
1074 udelay(1);
1075 else
1076 rtl92s_phy_set_rf_reg(hw, rfpath,
1077 radio_a_table[i],
1078 MASK20BITS,
1079 radio_a_table[i + 1]);
1080
1081 /* Add delay for ECS T20 & LG malow platform */
1082 udelay(1);
1083 }
1084
1085 /* PA Bias current for inferiority IC */
1086 _rtl92s_phy_config_rfpa_bias_current(hw, rfpath);
1087 break;
1088 case RF90_PATH_B:
1089 for (i = 0; i < radio_b_tblen; i = i + 2) {
1090 if (radio_b_table[i] == 0xfe)
1091 /* Delay specific ms. Only RF configuration
1092 * requires delay.*/
1093 mdelay(50);
1094 else if (radio_b_table[i] == 0xfd)
1095 mdelay(5);
1096 else if (radio_b_table[i] == 0xfc)
1097 mdelay(1);
1098 else if (radio_b_table[i] == 0xfb)
1099 udelay(50);
1100 else if (radio_b_table[i] == 0xfa)
1101 udelay(5);
1102 else if (radio_b_table[i] == 0xf9)
1103 udelay(1);
1104 else
1105 rtl92s_phy_set_rf_reg(hw, rfpath,
1106 radio_b_table[i],
1107 MASK20BITS,
1108 radio_b_table[i + 1]);
1109
1110 /* Add delay for ECS T20 & LG malow platform */
1111 udelay(1);
1112 }
1113 break;
1114 case RF90_PATH_C:
1115 ;
1116 break;
1117 case RF90_PATH_D:
1118 ;
1119 break;
1120 default:
1121 break;
1122 }
1123
1124 return rtstatus;
1125}
1126
1127
1128bool rtl92s_phy_mac_config(struct ieee80211_hw *hw)
1129{
1130 struct rtl_priv *rtlpriv = rtl_priv(hw);
1131 u32 i;
1132 u32 arraylength;
1133 u32 *ptraArray;
1134
1135 arraylength = MAC_2T_ARRAYLENGTH;
1136 ptraArray = rtl8192semac_2t_array;
1137
1138 for (i = 0; i < arraylength; i = i + 2)
1139 rtl_write_byte(rtlpriv, ptraArray[i], (u8)ptraArray[i + 1]);
1140
1141 return true;
1142}
1143
1144
1145bool rtl92s_phy_bb_config(struct ieee80211_hw *hw)
1146{
1147 struct rtl_priv *rtlpriv = rtl_priv(hw);
1148 struct rtl_phy *rtlphy = &(rtlpriv->phy);
1149 bool rtstatus = true;
1150 u8 pathmap, index, rf_num = 0;
1151 u8 path1, path2;
1152
1153 _rtl92s_phy_init_register_definition(hw);
1154
1155 /* Config BB and AGC */
1156 rtstatus = _rtl92s_phy_bb_config_parafile(hw);
1157
1158
1159 /* Check BB/RF confiuration setting. */
1160 /* We only need to configure RF which is turned on. */
1161 path1 = (u8)(rtl92s_phy_query_bb_reg(hw, RFPGA0_TXINFO, 0xf));
1162 mdelay(10);
1163 path2 = (u8)(rtl92s_phy_query_bb_reg(hw, ROFDM0_TRXPATHENABLE, 0xf));
1164 pathmap = path1 | path2;
1165
1166 rtlphy->rf_pathmap = pathmap;
1167 for (index = 0; index < 4; index++) {
1168 if ((pathmap >> index) & 0x1)
1169 rf_num++;
1170 }
1171
1172 if ((rtlphy->rf_type == RF_1T1R && rf_num != 1) ||
1173 (rtlphy->rf_type == RF_1T2R && rf_num != 2) ||
1174 (rtlphy->rf_type == RF_2T2R && rf_num != 2) ||
1175 (rtlphy->rf_type == RF_2T2R_GREEN && rf_num != 2)) {
1176 RT_TRACE(rtlpriv, COMP_INIT, DBG_EMERG,
1177 ("RF_Type(%x) does not match "
1178 "RF_Num(%x)!!\n", rtlphy->rf_type, rf_num));
1179 RT_TRACE(rtlpriv, COMP_INIT, DBG_EMERG,
1180 ("path1 0x%x, path2 0x%x, pathmap "
1181 "0x%x\n", path1, path2, pathmap));
1182 }
1183
1184 return rtstatus;
1185}
1186
1187bool rtl92s_phy_rf_config(struct ieee80211_hw *hw)
1188{
1189 struct rtl_priv *rtlpriv = rtl_priv(hw);
1190 struct rtl_phy *rtlphy = &(rtlpriv->phy);
1191
1192 /* Initialize general global value */
1193 if (rtlphy->rf_type == RF_1T1R)
1194 rtlphy->num_total_rfpath = 1;
1195 else
1196 rtlphy->num_total_rfpath = 2;
1197
1198 /* Config BB and RF */
1199 return rtl92s_phy_rf6052_config(hw);
1200}
1201
1202void rtl92s_phy_get_hw_reg_originalvalue(struct ieee80211_hw *hw)
1203{
1204 struct rtl_priv *rtlpriv = rtl_priv(hw);
1205 struct rtl_phy *rtlphy = &(rtlpriv->phy);
1206
1207 /* read rx initial gain */
1208 rtlphy->default_initialgain[0] = rtl_get_bbreg(hw,
1209 ROFDM0_XAAGCCORE1, MASKBYTE0);
1210 rtlphy->default_initialgain[1] = rtl_get_bbreg(hw,
1211 ROFDM0_XBAGCCORE1, MASKBYTE0);
1212 rtlphy->default_initialgain[2] = rtl_get_bbreg(hw,
1213 ROFDM0_XCAGCCORE1, MASKBYTE0);
1214 rtlphy->default_initialgain[3] = rtl_get_bbreg(hw,
1215 ROFDM0_XDAGCCORE1, MASKBYTE0);
1216 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, ("Default initial gain "
1217 "(c50=0x%x, c58=0x%x, c60=0x%x, c68=0x%x)\n",
1218 rtlphy->default_initialgain[0],
1219 rtlphy->default_initialgain[1],
1220 rtlphy->default_initialgain[2],
1221 rtlphy->default_initialgain[3]));
1222
1223 /* read framesync */
1224 rtlphy->framesync = rtl_get_bbreg(hw, ROFDM0_RXDETECTOR3, MASKBYTE0);
1225 rtlphy->framesync_c34 = rtl_get_bbreg(hw, ROFDM0_RXDETECTOR2,
1226 MASKDWORD);
1227 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
1228 ("Default framesync (0x%x) = 0x%x\n",
1229 ROFDM0_RXDETECTOR3, rtlphy->framesync));
1230
1231}
1232
1233static void _rtl92s_phy_get_txpower_index(struct ieee80211_hw *hw, u8 channel,
1234 u8 *cckpowerlevel, u8 *ofdmpowerLevel)
1235{
1236 struct rtl_priv *rtlpriv = rtl_priv(hw);
1237 struct rtl_phy *rtlphy = &(rtlpriv->phy);
1238 struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
1239 u8 index = (channel - 1);
1240
1241 /* 1. CCK */
1242 /* RF-A */
1243 cckpowerlevel[0] = rtlefuse->txpwrlevel_cck[0][index];
1244 /* RF-B */
1245 cckpowerlevel[1] = rtlefuse->txpwrlevel_cck[1][index];
1246
1247 /* 2. OFDM for 1T or 2T */
1248 if (rtlphy->rf_type == RF_1T2R || rtlphy->rf_type == RF_1T1R) {
1249 /* Read HT 40 OFDM TX power */
1250 ofdmpowerLevel[0] = rtlefuse->txpwrlevel_ht40_1s[0][index];
1251 ofdmpowerLevel[1] = rtlefuse->txpwrlevel_ht40_1s[1][index];
1252 } else if (rtlphy->rf_type == RF_2T2R) {
1253 /* Read HT 40 OFDM TX power */
1254 ofdmpowerLevel[0] = rtlefuse->txpwrlevel_ht40_2s[0][index];
1255 ofdmpowerLevel[1] = rtlefuse->txpwrlevel_ht40_2s[1][index];
1256 }
1257}
1258
1259static void _rtl92s_phy_ccxpower_indexcheck(struct ieee80211_hw *hw,
1260 u8 channel, u8 *cckpowerlevel, u8 *ofdmpowerlevel)
1261{
1262 struct rtl_priv *rtlpriv = rtl_priv(hw);
1263 struct rtl_phy *rtlphy = &(rtlpriv->phy);
1264
1265 rtlphy->cur_cck_txpwridx = cckpowerlevel[0];
1266 rtlphy->cur_ofdm24g_txpwridx = ofdmpowerlevel[0];
1267}
1268
1269void rtl92s_phy_set_txpower(struct ieee80211_hw *hw, u8 channel)
1270{
1271 struct rtl_priv *rtlpriv = rtl_priv(hw);
1272 struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
1273 /* [0]:RF-A, [1]:RF-B */
1274 u8 cckpowerlevel[2], ofdmpowerLevel[2];
1275
1276 if (rtlefuse->txpwr_fromeprom == false)
1277 return;
1278
1279 /* Mainly we use RF-A Tx Power to write the Tx Power registers,
1280 * but the RF-B Tx Power must be calculated by the antenna diff.
1281 * So we have to rewrite Antenna gain offset register here.
1282 * Please refer to BB register 0x80c
1283 * 1. For CCK.
1284 * 2. For OFDM 1T or 2T */
1285 _rtl92s_phy_get_txpower_index(hw, channel, &cckpowerlevel[0],
1286 &ofdmpowerLevel[0]);
1287
1288 RT_TRACE(rtlpriv, COMP_POWER, DBG_LOUD,
1289 ("Channel-%d, cckPowerLevel (A / B) = "
1290 "0x%x / 0x%x, ofdmPowerLevel (A / B) = 0x%x / 0x%x\n",
1291 channel, cckpowerlevel[0], cckpowerlevel[1],
1292 ofdmpowerLevel[0], ofdmpowerLevel[1]));
1293
1294 _rtl92s_phy_ccxpower_indexcheck(hw, channel, &cckpowerlevel[0],
1295 &ofdmpowerLevel[0]);
1296
1297 rtl92s_phy_rf6052_set_ccktxpower(hw, cckpowerlevel[0]);
1298 rtl92s_phy_rf6052_set_ofdmtxpower(hw, &ofdmpowerLevel[0], channel);
1299
1300}
1301
1302void rtl92s_phy_chk_fwcmd_iodone(struct ieee80211_hw *hw)
1303{
1304 struct rtl_priv *rtlpriv = rtl_priv(hw);
1305 u16 pollingcnt = 10000;
1306 u32 tmpvalue;
1307
1308 /* Make sure that CMD IO has be accepted by FW. */
1309 do {
1310 udelay(10);
1311
1312 tmpvalue = rtl_read_dword(rtlpriv, WFM5);
1313 if (tmpvalue == 0)
1314 break;
1315 } while (--pollingcnt);
1316
1317 if (pollingcnt == 0)
1318 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG, ("Set FW Cmd fail!!\n"));
1319}
1320
1321
1322static void _rtl92s_phy_set_fwcmd_io(struct ieee80211_hw *hw)
1323{
1324 struct rtl_priv *rtlpriv = rtl_priv(hw);
1325 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
1326 struct rtl_phy *rtlphy = &(rtlpriv->phy);
1327 u32 input, current_aid = 0;
1328
1329 if (is_hal_stop(rtlhal))
1330 return;
1331
1332 /* We re-map RA related CMD IO to combinational ones */
1333 /* if FW version is v.52 or later. */
1334 switch (rtlhal->current_fwcmd_io) {
1335 case FW_CMD_RA_REFRESH_N:
1336 rtlhal->current_fwcmd_io = FW_CMD_RA_REFRESH_N_COMB;
1337 break;
1338 case FW_CMD_RA_REFRESH_BG:
1339 rtlhal->current_fwcmd_io = FW_CMD_RA_REFRESH_BG_COMB;
1340 break;
1341 default:
1342 break;
1343 }
1344
1345 switch (rtlhal->current_fwcmd_io) {
1346 case FW_CMD_RA_RESET:
1347 RT_TRACE(rtlpriv, COMP_CMD, DBG_DMESG,
1348 ("FW_CMD_RA_RESET\n"));
1349 rtl_write_dword(rtlpriv, WFM5, FW_RA_RESET);
1350 rtl92s_phy_chk_fwcmd_iodone(hw);
1351 break;
1352 case FW_CMD_RA_ACTIVE:
1353 RT_TRACE(rtlpriv, COMP_CMD, DBG_DMESG,
1354 ("FW_CMD_RA_ACTIVE\n"));
1355 rtl_write_dword(rtlpriv, WFM5, FW_RA_ACTIVE);
1356 rtl92s_phy_chk_fwcmd_iodone(hw);
1357 break;
1358 case FW_CMD_RA_REFRESH_N:
1359 RT_TRACE(rtlpriv, COMP_CMD, DBG_DMESG,
1360 ("FW_CMD_RA_REFRESH_N\n"));
1361 input = FW_RA_REFRESH;
1362 rtl_write_dword(rtlpriv, WFM5, input);
1363 rtl92s_phy_chk_fwcmd_iodone(hw);
1364 rtl_write_dword(rtlpriv, WFM5, FW_RA_ENABLE_RSSI_MASK);
1365 rtl92s_phy_chk_fwcmd_iodone(hw);
1366 break;
1367 case FW_CMD_RA_REFRESH_BG:
1368 RT_TRACE(rtlpriv, COMP_CMD, DBG_DMESG,
1369 ("FW_CMD_RA_REFRESH_BG\n"));
1370 rtl_write_dword(rtlpriv, WFM5, FW_RA_REFRESH);
1371 rtl92s_phy_chk_fwcmd_iodone(hw);
1372 rtl_write_dword(rtlpriv, WFM5, FW_RA_DISABLE_RSSI_MASK);
1373 rtl92s_phy_chk_fwcmd_iodone(hw);
1374 break;
1375 case FW_CMD_RA_REFRESH_N_COMB:
1376 RT_TRACE(rtlpriv, COMP_CMD, DBG_DMESG,
1377 ("FW_CMD_RA_REFRESH_N_COMB\n"));
1378 input = FW_RA_IOT_N_COMB;
1379 rtl_write_dword(rtlpriv, WFM5, input);
1380 rtl92s_phy_chk_fwcmd_iodone(hw);
1381 break;
1382 case FW_CMD_RA_REFRESH_BG_COMB:
1383 RT_TRACE(rtlpriv, COMP_CMD, DBG_DMESG,
1384 ("FW_CMD_RA_REFRESH_BG_COMB\n"));
1385 input = FW_RA_IOT_BG_COMB;
1386 rtl_write_dword(rtlpriv, WFM5, input);
1387 rtl92s_phy_chk_fwcmd_iodone(hw);
1388 break;
1389 case FW_CMD_IQK_ENABLE:
1390 RT_TRACE(rtlpriv, COMP_CMD, DBG_DMESG,
1391 ("FW_CMD_IQK_ENABLE\n"));
1392 rtl_write_dword(rtlpriv, WFM5, FW_IQK_ENABLE);
1393 rtl92s_phy_chk_fwcmd_iodone(hw);
1394 break;
1395 case FW_CMD_PAUSE_DM_BY_SCAN:
1396 /* Lower initial gain */
1397 rtl_set_bbreg(hw, ROFDM0_XAAGCCORE1, MASKBYTE0, 0x17);
1398 rtl_set_bbreg(hw, ROFDM0_XBAGCCORE1, MASKBYTE0, 0x17);
1399 /* CCA threshold */
1400 rtl_set_bbreg(hw, RCCK0_CCA, MASKBYTE2, 0x40);
1401 break;
1402 case FW_CMD_RESUME_DM_BY_SCAN:
1403 /* CCA threshold */
1404 rtl_set_bbreg(hw, RCCK0_CCA, MASKBYTE2, 0xcd);
1405 rtl92s_phy_set_txpower(hw, rtlphy->current_channel);
1406 break;
1407 case FW_CMD_HIGH_PWR_DISABLE:
1408 if (rtlpriv->dm.dm_flag & HAL_DM_HIPWR_DISABLE)
1409 break;
1410
1411 /* Lower initial gain */
1412 rtl_set_bbreg(hw, ROFDM0_XAAGCCORE1, MASKBYTE0, 0x17);
1413 rtl_set_bbreg(hw, ROFDM0_XBAGCCORE1, MASKBYTE0, 0x17);
1414 /* CCA threshold */
1415 rtl_set_bbreg(hw, RCCK0_CCA, MASKBYTE2, 0x40);
1416 break;
1417 case FW_CMD_HIGH_PWR_ENABLE:
1418 if ((rtlpriv->dm.dm_flag & HAL_DM_HIPWR_DISABLE) ||
e10542c4 1419 rtlpriv->dm.dynamic_txpower_enable)
d1585316
CL		 1420 break;
1421
1422 /* CCA threshold */
1423 rtl_set_bbreg(hw, RCCK0_CCA, MASKBYTE2, 0xcd);
1424 break;
1425 case FW_CMD_LPS_ENTER:
1426 RT_TRACE(rtlpriv, COMP_CMD, DBG_DMESG,
1427 ("FW_CMD_LPS_ENTER\n"));
1428 current_aid = rtlpriv->mac80211.assoc_id;
1429 rtl_write_dword(rtlpriv, WFM5, (FW_LPS_ENTER |
1430 ((current_aid | 0xc000) << 8)));
1431 rtl92s_phy_chk_fwcmd_iodone(hw);
1432 /* FW set TXOP disable here, so disable EDCA
1433 * turbo mode until driver leave LPS */
1434 break;
1435 case FW_CMD_LPS_LEAVE:
1436 RT_TRACE(rtlpriv, COMP_CMD, DBG_DMESG,
1437 ("FW_CMD_LPS_LEAVE\n"));
1438 rtl_write_dword(rtlpriv, WFM5, FW_LPS_LEAVE);
1439 rtl92s_phy_chk_fwcmd_iodone(hw);
1440 break;
1441 case FW_CMD_ADD_A2_ENTRY:
1442 RT_TRACE(rtlpriv, COMP_CMD, DBG_DMESG,
1443 ("FW_CMD_ADD_A2_ENTRY\n"));
1444 rtl_write_dword(rtlpriv, WFM5, FW_ADD_A2_ENTRY);
1445 rtl92s_phy_chk_fwcmd_iodone(hw);
1446 break;
1447 case FW_CMD_CTRL_DM_BY_DRIVER:
1448 RT_TRACE(rtlpriv, COMP_CMD, DBG_LOUD,
1449 ("FW_CMD_CTRL_DM_BY_DRIVER\n"));
1450 rtl_write_dword(rtlpriv, WFM5, FW_CTRL_DM_BY_DRIVER);
1451 rtl92s_phy_chk_fwcmd_iodone(hw);
1452 break;
1453
1454 default:
1455 break;
1456 }
1457
1458 rtl92s_phy_chk_fwcmd_iodone(hw);
1459
1460 /* Clear FW CMD operation flag. */
1461 rtlhal->set_fwcmd_inprogress = false;
1462}
1463
1464bool rtl92s_phy_set_fw_cmd(struct ieee80211_hw *hw, enum fwcmd_iotype fw_cmdio)
1465{
1466 struct rtl_priv *rtlpriv = rtl_priv(hw);
1467 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
1468 struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
1469 u32 fw_param = FW_CMD_IO_PARA_QUERY(rtlpriv);
1470 u16 fw_cmdmap = FW_CMD_IO_QUERY(rtlpriv);
1471 bool bPostProcessing = false;
1472
1473 RT_TRACE(rtlpriv, COMP_CMD, DBG_LOUD,
1474 ("Set FW Cmd(%#x), set_fwcmd_inprogress(%d)\n",
1475 fw_cmdio, rtlhal->set_fwcmd_inprogress));
1476
1477 do {
1478 /* We re-map to combined FW CMD ones if firmware version */
1479 /* is v.53 or later. */
1480 switch (fw_cmdio) {
1481 case FW_CMD_RA_REFRESH_N:
1482 fw_cmdio = FW_CMD_RA_REFRESH_N_COMB;
1483 break;
1484 case FW_CMD_RA_REFRESH_BG:
1485 fw_cmdio = FW_CMD_RA_REFRESH_BG_COMB;
1486 break;
1487 default:
1488 break;
1489 }
1490
1491 /* If firmware version is v.62 or later,
1492 * use FW_CMD_IO_SET for FW_CMD_CTRL_DM_BY_DRIVER */
1493 if (hal_get_firmwareversion(rtlpriv) >= 0x3E) {
1494 if (fw_cmdio == FW_CMD_CTRL_DM_BY_DRIVER)
1495 fw_cmdio = FW_CMD_CTRL_DM_BY_DRIVER_NEW;
1496 }
1497
1498
1499 /* We shall revise all FW Cmd IO into Reg0x364
1500 * DM map table in the future. */
1501 switch (fw_cmdio) {
1502 case FW_CMD_RA_INIT:
1503 RT_TRACE(rtlpriv, COMP_CMD, DBG_LOUD, ("RA init!!\n"));
1504 fw_cmdmap |= FW_RA_INIT_CTL;
1505 FW_CMD_IO_SET(rtlpriv, fw_cmdmap);
1506 /* Clear control flag to sync with FW. */
1507 FW_CMD_IO_CLR(rtlpriv, FW_RA_INIT_CTL);
1508 break;
1509 case FW_CMD_DIG_DISABLE:
1510 RT_TRACE(rtlpriv, COMP_CMD, DBG_LOUD,
1511 ("Set DIG disable!!\n"));
1512 fw_cmdmap &= ~FW_DIG_ENABLE_CTL;
1513 FW_CMD_IO_SET(rtlpriv, fw_cmdmap);
1514 break;
1515 case FW_CMD_DIG_ENABLE:
1516 case FW_CMD_DIG_RESUME:
1517 if (!(rtlpriv->dm.dm_flag & HAL_DM_DIG_DISABLE)) {
1518 RT_TRACE(rtlpriv, COMP_CMD, DBG_LOUD,
1519 ("Set DIG enable or resume!!\n"));
1520 fw_cmdmap |= (FW_DIG_ENABLE_CTL | FW_SS_CTL);
1521 FW_CMD_IO_SET(rtlpriv, fw_cmdmap);
1522 }
1523 break;
1524 case FW_CMD_DIG_HALT:
1525 RT_TRACE(rtlpriv, COMP_CMD, DBG_LOUD,
1526 ("Set DIG halt!!\n"));
1527 fw_cmdmap &= ~(FW_DIG_ENABLE_CTL | FW_SS_CTL);
1528 FW_CMD_IO_SET(rtlpriv, fw_cmdmap);
1529 break;
1530 case FW_CMD_TXPWR_TRACK_THERMAL: {
1531 u8 thermalval = 0;
1532 fw_cmdmap |= FW_PWR_TRK_CTL;
1533
1534 /* Clear FW parameter in terms of thermal parts. */
1535 fw_param &= FW_PWR_TRK_PARAM_CLR;
1536
1537 thermalval = rtlpriv->dm.thermalvalue;
1538 fw_param |= ((thermalval << 24) |
1539 (rtlefuse->thermalmeter[0] << 16));
1540
1541 RT_TRACE(rtlpriv, COMP_CMD, DBG_LOUD,
1542 ("Set TxPwr tracking!! "
1543 "FwCmdMap(%#x), FwParam(%#x)\n",
1544 fw_cmdmap, fw_param));
1545
1546 FW_CMD_PARA_SET(rtlpriv, fw_param);
1547 FW_CMD_IO_SET(rtlpriv, fw_cmdmap);
1548
1549 /* Clear control flag to sync with FW. */
1550 FW_CMD_IO_CLR(rtlpriv, FW_PWR_TRK_CTL);
1551 }
1552 break;
1553 /* The following FW CMDs are only compatible to
1554 * v.53 or later. */
1555 case FW_CMD_RA_REFRESH_N_COMB:
1556 fw_cmdmap |= FW_RA_N_CTL;
1557
1558 /* Clear RA BG mode control. */
1559 fw_cmdmap &= ~(FW_RA_BG_CTL | FW_RA_INIT_CTL);
1560
1561 /* Clear FW parameter in terms of RA parts. */
1562 fw_param &= FW_RA_PARAM_CLR;
1563
1564 RT_TRACE(rtlpriv, COMP_CMD, DBG_LOUD,
1565 ("[FW CMD] [New Version] "
1566 "Set RA/IOT Comb in n mode!! FwCmdMap(%#x), "
1567 "FwParam(%#x)\n", fw_cmdmap, fw_param));
1568
1569 FW_CMD_PARA_SET(rtlpriv, fw_param);
1570 FW_CMD_IO_SET(rtlpriv, fw_cmdmap);
1571
1572 /* Clear control flag to sync with FW. */
1573 FW_CMD_IO_CLR(rtlpriv, FW_RA_N_CTL);
1574 break;
1575 case FW_CMD_RA_REFRESH_BG_COMB:
1576 fw_cmdmap |= FW_RA_BG_CTL;
1577
1578 /* Clear RA n-mode control. */
1579 fw_cmdmap &= ~(FW_RA_N_CTL | FW_RA_INIT_CTL);
1580 /* Clear FW parameter in terms of RA parts. */
1581 fw_param &= FW_RA_PARAM_CLR;
1582
1583 FW_CMD_PARA_SET(rtlpriv, fw_param);
1584 FW_CMD_IO_SET(rtlpriv, fw_cmdmap);
1585
1586 /* Clear control flag to sync with FW. */
1587 FW_CMD_IO_CLR(rtlpriv, FW_RA_BG_CTL);
1588 break;
1589 case FW_CMD_IQK_ENABLE:
1590 fw_cmdmap |= FW_IQK_CTL;
1591 FW_CMD_IO_SET(rtlpriv, fw_cmdmap);
1592 /* Clear control flag to sync with FW. */
1593 FW_CMD_IO_CLR(rtlpriv, FW_IQK_CTL);
1594 break;
1595 /* The following FW CMD is compatible to v.62 or later. */
1596 case FW_CMD_CTRL_DM_BY_DRIVER_NEW:
1597 fw_cmdmap |= FW_DRIVER_CTRL_DM_CTL;
1598 FW_CMD_IO_SET(rtlpriv, fw_cmdmap);
1599 break;
1600 /* The followed FW Cmds needs post-processing later. */
1601 case FW_CMD_RESUME_DM_BY_SCAN:
1602 fw_cmdmap |= (FW_DIG_ENABLE_CTL |
1603 FW_HIGH_PWR_ENABLE_CTL |
1604 FW_SS_CTL);
1605
1606 if (rtlpriv->dm.dm_flag & HAL_DM_DIG_DISABLE ||
1607 !digtable.dig_enable_flag)
1608 fw_cmdmap &= ~FW_DIG_ENABLE_CTL;
1609
1610 if ((rtlpriv->dm.dm_flag & HAL_DM_HIPWR_DISABLE) ||
e10542c4 1611 rtlpriv->dm.dynamic_txpower_enable)
d1585316
CL		 1612 fw_cmdmap &= ~FW_HIGH_PWR_ENABLE_CTL;
1613
1614 if ((digtable.dig_ext_port_stage ==
1615 DIG_EXT_PORT_STAGE_0) ||
1616 (digtable.dig_ext_port_stage ==
1617 DIG_EXT_PORT_STAGE_1))
1618 fw_cmdmap &= ~FW_DIG_ENABLE_CTL;
1619
1620 FW_CMD_IO_SET(rtlpriv, fw_cmdmap);
1621 bPostProcessing = true;
1622 break;
1623 case FW_CMD_PAUSE_DM_BY_SCAN:
1624 fw_cmdmap &= ~(FW_DIG_ENABLE_CTL |
1625 FW_HIGH_PWR_ENABLE_CTL |
1626 FW_SS_CTL);
1627 FW_CMD_IO_SET(rtlpriv, fw_cmdmap);
1628 bPostProcessing = true;
1629 break;
1630 case FW_CMD_HIGH_PWR_DISABLE:
1631 fw_cmdmap &= ~FW_HIGH_PWR_ENABLE_CTL;
1632 FW_CMD_IO_SET(rtlpriv, fw_cmdmap);
1633 bPostProcessing = true;
1634 break;
1635 case FW_CMD_HIGH_PWR_ENABLE:
1636 if (!(rtlpriv->dm.dm_flag & HAL_DM_HIPWR_DISABLE) &&
1637 (rtlpriv->dm.dynamic_txpower_enable != true)) {
1638 fw_cmdmap |= (FW_HIGH_PWR_ENABLE_CTL |
1639 FW_SS_CTL);
1640 FW_CMD_IO_SET(rtlpriv, fw_cmdmap);
1641 bPostProcessing = true;
1642 }
1643 break;
1644 case FW_CMD_DIG_MODE_FA:
1645 fw_cmdmap |= FW_FA_CTL;
1646 FW_CMD_IO_SET(rtlpriv, fw_cmdmap);
1647 break;
1648 case FW_CMD_DIG_MODE_SS:
1649 fw_cmdmap &= ~FW_FA_CTL;
1650 FW_CMD_IO_SET(rtlpriv, fw_cmdmap);
1651 break;
1652 case FW_CMD_PAPE_CONTROL:
1653 RT_TRACE(rtlpriv, COMP_CMD, DBG_LOUD,
1654 ("[FW CMD] Set PAPE Control\n"));
1655 fw_cmdmap &= ~FW_PAPE_CTL_BY_SW_HW;
1656
1657 FW_CMD_IO_SET(rtlpriv, fw_cmdmap);
1658 break;
1659 default:
1660 /* Pass to original FW CMD processing callback
1661 * routine. */
1662 bPostProcessing = true;
1663 break;
1664 }
1665 } while (false);
1666
1667 /* We shall post processing these FW CMD if
1668 * variable bPostProcessing is set. */
1669 if (bPostProcessing && !rtlhal->set_fwcmd_inprogress) {
1670 rtlhal->set_fwcmd_inprogress = true;
1671 /* Update current FW Cmd for callback use. */
1672 rtlhal->current_fwcmd_io = fw_cmdio;
1673 } else {
1674 return false;
1675 }
1676
1677 _rtl92s_phy_set_fwcmd_io(hw);
1678 return true;
1679}
1680
1681static void _rtl92s_phy_check_ephy_switchready(struct ieee80211_hw *hw)
1682{
1683 struct rtl_priv *rtlpriv = rtl_priv(hw);
1684 u32 delay = 100;
1685 u8 regu1;
1686
1687 regu1 = rtl_read_byte(rtlpriv, 0x554);
1688 while ((regu1 & BIT(5)) && (delay > 0)) {
1689 regu1 = rtl_read_byte(rtlpriv, 0x554);
1690 delay--;
1691 /* We delay only 50us to prevent
1692 * being scheduled out. */
1693 udelay(50);
1694 }
1695}
1696
1697void rtl92s_phy_switch_ephy_parameter(struct ieee80211_hw *hw)
1698{
1699 struct rtl_priv *rtlpriv = rtl_priv(hw);
1700 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
1701
1702 /* The way to be capable to switch clock request
1703 * when the PG setting does not support clock request.
1704 * This is the backdoor solution to switch clock
1705 * request before ASPM or D3. */
1706 rtl_write_dword(rtlpriv, 0x540, 0x73c11);
1707 rtl_write_dword(rtlpriv, 0x548, 0x2407c);
1708
1709 /* Switch EPHY parameter!!!! */
1710 rtl_write_word(rtlpriv, 0x550, 0x1000);
1711 rtl_write_byte(rtlpriv, 0x554, 0x20);
1712 _rtl92s_phy_check_ephy_switchready(hw);
1713
1714 rtl_write_word(rtlpriv, 0x550, 0xa0eb);
1715 rtl_write_byte(rtlpriv, 0x554, 0x3e);
1716 _rtl92s_phy_check_ephy_switchready(hw);
1717
1718 rtl_write_word(rtlpriv, 0x550, 0xff80);
1719 rtl_write_byte(rtlpriv, 0x554, 0x39);
1720 _rtl92s_phy_check_ephy_switchready(hw);
1721
1722 /* Delay L1 enter time */
1723 if (ppsc->support_aspm && !ppsc->support_backdoor)
1724 rtl_write_byte(rtlpriv, 0x560, 0x40);
1725 else
1726 rtl_write_byte(rtlpriv, 0x560, 0x00);
1727
1728}
1729
1730void rtl92s_phy_set_beacon_hwreg(struct ieee80211_hw *hw, u16 BeaconInterval)
1731{
1732 struct rtl_priv *rtlpriv = rtl_priv(hw);
1733 rtl_write_dword(rtlpriv, WFM5, 0xF1000000 | (BeaconInterval << 8));
1734}
Linux kernel - Deliverables
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