[deliverable/linux.git] / drivers / net / wireless / rtlwifi / rtl8192se / sw.c

/******************************************************************************
 *
 * Copyright(c) 2009-2012  Realtek Corporation.
 *
 * This program is free software; you can redistribute it and/or modify it
 * under the terms of version 2 of the GNU General Public License as
 * published by the Free Software Foundation.
 *
 * This program is distributed in the hope that it will be useful, but WITHOUT
 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
 * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
 * more details.
 *
 * You should have received a copy of the GNU General Public License along with
 * this program; if not, write to the Free Software Foundation, Inc.,
 * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
 *
 * The full GNU General Public License is included in this distribution in the
 * file called LICENSE.
 *
 * Contact Information:
 * wlanfae <wlanfae@realtek.com>
 * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
 * Hsinchu 300, Taiwan.
 *
 * Larry Finger <Larry.Finger@lwfinger.net>
 *
 *****************************************************************************/

#include "../wifi.h"
#include "../core.h"
#include "../base.h"
#include "../pci.h"
#include "reg.h"
#include "def.h"
#include "phy.h"
#include "dm.h"
#include "fw.h"
#include "hw.h"
#include "sw.h"
#include "trx.h"
#include "led.h"

#include <linux/module.h>

static void rtl92s_init_aspm_vars(struct ieee80211_hw *hw)
{
	struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));

	/*close ASPM for AMD defaultly */
	rtlpci->const_amdpci_aspm = 0;

	/* ASPM PS mode.
	 * 0 - Disable ASPM,
	 * 1 - Enable ASPM without Clock Req,
	 * 2 - Enable ASPM with Clock Req,
	 * 3 - Alwyas Enable ASPM with Clock Req,
	 * 4 - Always Enable ASPM without Clock Req.
	 * set defult to RTL8192CE:3 RTL8192E:2
	 * */
	rtlpci->const_pci_aspm = 2;

	/*Setting for PCI-E device */
	rtlpci->const_devicepci_aspm_setting = 0x03;

	/*Setting for PCI-E bridge */
	rtlpci->const_hostpci_aspm_setting = 0x02;

	/* In Hw/Sw Radio Off situation.
	 * 0 - Default,
	 * 1 - From ASPM setting without low Mac Pwr,
	 * 2 - From ASPM setting with low Mac Pwr,
	 * 3 - Bus D3
	 * set default to RTL8192CE:0 RTL8192SE:2
	 */
	rtlpci->const_hwsw_rfoff_d3 = 2;

	/* This setting works for those device with
	 * backdoor ASPM setting such as EPHY setting.
	 * 0 - Not support ASPM,
	 * 1 - Support ASPM,
	 * 2 - According to chipset.
	 */
	rtlpci->const_support_pciaspm = 2;
}

static void rtl92se_fw_cb(const struct firmware *firmware, void *context)
{
	struct ieee80211_hw *hw = context;
	struct rtl_pci_priv *pcipriv = rtl_pcipriv(hw);
	struct rtl_priv *rtlpriv = rtl_priv(hw);
	struct rtl_pci *rtlpci = rtl_pcidev(pcipriv);
	struct rt_firmware *pfirmware = NULL;
	int err;

	RT_TRACE(rtlpriv, COMP_ERR, DBG_LOUD,
			 "Firmware callback routine entered!\n");
	complete(&rtlpriv->firmware_loading_complete);
	if (!firmware) {
		pr_err("Firmware %s not available\n", rtlpriv->cfg->fw_name);
		rtlpriv->max_fw_size = 0;
		return;
	}
	if (firmware->size > rtlpriv->max_fw_size) {
		RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
			 "Firmware is too big!\n");
		rtlpriv->max_fw_size = 0;
		release_firmware(firmware);
		return;
	}
	pfirmware = (struct rt_firmware *)rtlpriv->rtlhal.pfirmware;
	memcpy(pfirmware->sz_fw_tmpbuffer, firmware->data, firmware->size);
	pfirmware->sz_fw_tmpbufferlen = firmware->size;
	release_firmware(firmware);

	err = ieee80211_register_hw(hw);
	if (err) {
		RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
			 "Can't register mac80211 hw\n");
		return;
	} else {
		rtlpriv->mac80211.mac80211_registered = 1;
	}
	rtlpci->irq_alloc = 1;
	set_bit(RTL_STATUS_INTERFACE_START, &rtlpriv->status);

	/*init rfkill */
	rtl_init_rfkill(hw);
}

static int rtl92s_init_sw_vars(struct ieee80211_hw *hw)
{
	struct rtl_priv *rtlpriv = rtl_priv(hw);
	struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
	int err = 0;
	u16 earlyrxthreshold = 7;

	rtlpriv->dm.dm_initialgain_enable = true;
	rtlpriv->dm.dm_flag = 0;
	rtlpriv->dm.disable_framebursting = false;
	rtlpriv->dm.thermalvalue = 0;
	rtlpriv->dm.useramask = true;

	/* compatible 5G band 91se just 2.4G band & smsp */
	rtlpriv->rtlhal.current_bandtype = BAND_ON_2_4G;
	rtlpriv->rtlhal.bandset = BAND_ON_2_4G;
	rtlpriv->rtlhal.macphymode = SINGLEMAC_SINGLEPHY;

	rtlpci->transmit_config = 0;

	rtlpci->receive_config =
			RCR_APPFCS |
			RCR_APWRMGT |
			/*RCR_ADD3 |*/
			RCR_AMF	|
			RCR_ADF |
			RCR_APP_MIC |
			RCR_APP_ICV |
			RCR_AICV |
			/* Accept ICV error, CRC32 Error */
			RCR_ACRC32 |
			RCR_AB |
			/* Accept Broadcast, Multicast */
			RCR_AM	|
			/* Accept Physical match */
			RCR_APM |
			/* Accept Destination Address packets */
			/*RCR_AAP |*/
			RCR_APP_PHYST_STAFF |
			/* Accept PHY status */
			RCR_APP_PHYST_RXFF |
			(earlyrxthreshold << RCR_FIFO_OFFSET);

	rtlpci->irq_mask[0] = (u32)
			(IMR_ROK |
			IMR_VODOK |
			IMR_VIDOK |
			IMR_BEDOK |
			IMR_BKDOK |
			IMR_HCCADOK |
			IMR_MGNTDOK |
			IMR_COMDOK |
			IMR_HIGHDOK |
			IMR_BDOK |
			IMR_RXCMDOK |
			/*IMR_TIMEOUT0 |*/
			IMR_RDU |
			IMR_RXFOVW	|
			IMR_BCNINT
			/*| IMR_TXFOVW*/
			/*| IMR_TBDOK |
			IMR_TBDER*/);

	rtlpci->irq_mask[1] = (u32) 0;

	rtlpci->shortretry_limit = 0x30;
	rtlpci->longretry_limit = 0x30;

	rtlpci->first_init = true;

	/* for debug level */
	rtlpriv->dbg.global_debuglevel = rtlpriv->cfg->mod_params->debug;
	/* for LPS & IPS */
	rtlpriv->psc.inactiveps = rtlpriv->cfg->mod_params->inactiveps;
	rtlpriv->psc.swctrl_lps = rtlpriv->cfg->mod_params->swctrl_lps;
	rtlpriv->psc.fwctrl_lps = rtlpriv->cfg->mod_params->fwctrl_lps;
	if (!rtlpriv->psc.inactiveps)
		pr_info("Power Save off (module option)\n");
	if (!rtlpriv->psc.fwctrl_lps)
		pr_info("FW Power Save off (module option)\n");
	rtlpriv->psc.reg_fwctrl_lps = 3;
	rtlpriv->psc.reg_max_lps_awakeintvl = 5;
	/* for ASPM, you can close aspm through
	 * set const_support_pciaspm = 0 */
	rtl92s_init_aspm_vars(hw);

	if (rtlpriv->psc.reg_fwctrl_lps == 1)
		rtlpriv->psc.fwctrl_psmode = FW_PS_MIN_MODE;
	else if (rtlpriv->psc.reg_fwctrl_lps == 2)
		rtlpriv->psc.fwctrl_psmode = FW_PS_MAX_MODE;
	else if (rtlpriv->psc.reg_fwctrl_lps == 3)
		rtlpriv->psc.fwctrl_psmode = FW_PS_DTIM_MODE;

	/* for firmware buf */
	rtlpriv->rtlhal.pfirmware = vzalloc(sizeof(struct rt_firmware));
	if (!rtlpriv->rtlhal.pfirmware)
		return 1;

	rtlpriv->max_fw_size = RTL8190_MAX_RAW_FIRMWARE_CODE_SIZE;

	pr_info("Driver for Realtek RTL8192SE/RTL8191SE\n"
		"Loading firmware %s\n", rtlpriv->cfg->fw_name);
	/* request fw */
	err = request_firmware_nowait(THIS_MODULE, 1, rtlpriv->cfg->fw_name,
				      rtlpriv->io.dev, GFP_KERNEL, hw,
				      rtl92se_fw_cb);
	if (err) {
		RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
			 "Failed to request firmware!\n");
		return 1;
	}

	return err;
}

static void rtl92s_deinit_sw_vars(struct ieee80211_hw *hw)
{
	struct rtl_priv *rtlpriv = rtl_priv(hw);

	if (rtlpriv->rtlhal.pfirmware) {
		vfree(rtlpriv->rtlhal.pfirmware);
		rtlpriv->rtlhal.pfirmware = NULL;
	}
}

static struct rtl_hal_ops rtl8192se_hal_ops = {
	.init_sw_vars = rtl92s_init_sw_vars,
	.deinit_sw_vars = rtl92s_deinit_sw_vars,
	.read_eeprom_info = rtl92se_read_eeprom_info,
	.interrupt_recognized = rtl92se_interrupt_recognized,
	.hw_init = rtl92se_hw_init,
	.hw_disable = rtl92se_card_disable,
	.hw_suspend = rtl92se_suspend,
	.hw_resume = rtl92se_resume,
	.enable_interrupt = rtl92se_enable_interrupt,
	.disable_interrupt = rtl92se_disable_interrupt,
	.set_network_type = rtl92se_set_network_type,
	.set_chk_bssid = rtl92se_set_check_bssid,
	.set_qos = rtl92se_set_qos,
	.set_bcn_reg = rtl92se_set_beacon_related_registers,
	.set_bcn_intv = rtl92se_set_beacon_interval,
	.update_interrupt_mask = rtl92se_update_interrupt_mask,
	.get_hw_reg = rtl92se_get_hw_reg,
	.set_hw_reg = rtl92se_set_hw_reg,
	.update_rate_tbl = rtl92se_update_hal_rate_tbl,
	.fill_tx_desc = rtl92se_tx_fill_desc,
	.fill_tx_cmddesc = rtl92se_tx_fill_cmddesc,
	.query_rx_desc = rtl92se_rx_query_desc,
	.set_channel_access = rtl92se_update_channel_access_setting,
	.radio_onoff_checking = rtl92se_gpio_radio_on_off_checking,
	.set_bw_mode = rtl92s_phy_set_bw_mode,
	.switch_channel = rtl92s_phy_sw_chnl,
	.dm_watchdog = rtl92s_dm_watchdog,
	.scan_operation_backup = rtl92s_phy_scan_operation_backup,
	.set_rf_power_state = rtl92s_phy_set_rf_power_state,
	.led_control = rtl92se_led_control,
	.set_desc = rtl92se_set_desc,
	.get_desc = rtl92se_get_desc,
	.tx_polling = rtl92se_tx_polling,
	.enable_hw_sec = rtl92se_enable_hw_security_config,
	.set_key = rtl92se_set_key,
	.init_sw_leds = rtl92se_init_sw_leds,
	.allow_all_destaddr = rtl92se_allow_all_destaddr,
	.get_bbreg = rtl92s_phy_query_bb_reg,
	.set_bbreg = rtl92s_phy_set_bb_reg,
	.get_rfreg = rtl92s_phy_query_rf_reg,
	.set_rfreg = rtl92s_phy_set_rf_reg,
};

static struct rtl_mod_params rtl92se_mod_params = {
	.sw_crypto = false,
	.inactiveps = true,
	.swctrl_lps = true,
	.fwctrl_lps = false,
	.debug = DBG_EMERG,
};

/* Because memory R/W bursting will cause system hang/crash
 * for 92se, so we don't read back after every write action */
static struct rtl_hal_cfg rtl92se_hal_cfg = {
	.bar_id = 1,
	.write_readback = false,
	.name = "rtl92s_pci",
	.fw_name = "rtlwifi/rtl8192sefw.bin",
	.ops = &rtl8192se_hal_ops,
	.mod_params = &rtl92se_mod_params,

	.maps[SYS_ISO_CTRL] = REG_SYS_ISO_CTRL,
	.maps[SYS_FUNC_EN] = REG_SYS_FUNC_EN,
	.maps[SYS_CLK] = SYS_CLKR,
	.maps[MAC_RCR_AM] = RCR_AM,
	.maps[MAC_RCR_AB] = RCR_AB,
	.maps[MAC_RCR_ACRC32] = RCR_ACRC32,
	.maps[MAC_RCR_ACF] = RCR_ACF,
	.maps[MAC_RCR_AAP] = RCR_AAP,

	.maps[EFUSE_TEST] = REG_EFUSE_TEST,
	.maps[EFUSE_CTRL] = REG_EFUSE_CTRL,
	.maps[EFUSE_CLK] = REG_EFUSE_CLK,
	.maps[EFUSE_CLK_CTRL] = REG_EFUSE_CTRL,
	.maps[EFUSE_PWC_EV12V] = 0, /* nouse for 8192se */
	.maps[EFUSE_FEN_ELDR] = 0, /* nouse for 8192se */
	.maps[EFUSE_LOADER_CLK_EN] = 0,/* nouse for 8192se */
	.maps[EFUSE_ANA8M] = EFUSE_ANA8M,
	.maps[EFUSE_HWSET_MAX_SIZE] = HWSET_MAX_SIZE_92S,
	.maps[EFUSE_MAX_SECTION_MAP] = EFUSE_MAX_SECTION,
	.maps[EFUSE_REAL_CONTENT_SIZE] = EFUSE_REAL_CONTENT_LEN,
	.maps[EFUSE_OOB_PROTECT_BYTES_LEN] = EFUSE_OOB_PROTECT_BYTES,

	.maps[RWCAM] = REG_RWCAM,
	.maps[WCAMI] = REG_WCAMI,
	.maps[RCAMO] = REG_RCAMO,
	.maps[CAMDBG] = REG_CAMDBG,
	.maps[SECR] = REG_SECR,
	.maps[SEC_CAM_NONE] = CAM_NONE,
	.maps[SEC_CAM_WEP40] = CAM_WEP40,
	.maps[SEC_CAM_TKIP] = CAM_TKIP,
	.maps[SEC_CAM_AES] = CAM_AES,
	.maps[SEC_CAM_WEP104] = CAM_WEP104,

	.maps[RTL_IMR_BCNDMAINT6] = IMR_BCNDMAINT6,
	.maps[RTL_IMR_BCNDMAINT5] = IMR_BCNDMAINT5,
	.maps[RTL_IMR_BCNDMAINT4] = IMR_BCNDMAINT4,
	.maps[RTL_IMR_BCNDMAINT3] = IMR_BCNDMAINT3,
	.maps[RTL_IMR_BCNDMAINT2] = IMR_BCNDMAINT2,
	.maps[RTL_IMR_BCNDMAINT1] = IMR_BCNDMAINT1,
	.maps[RTL_IMR_BCNDOK8] = IMR_BCNDOK8,
	.maps[RTL_IMR_BCNDOK7] = IMR_BCNDOK7,
	.maps[RTL_IMR_BCNDOK6] = IMR_BCNDOK6,
	.maps[RTL_IMR_BCNDOK5] = IMR_BCNDOK5,
	.maps[RTL_IMR_BCNDOK4] = IMR_BCNDOK4,
	.maps[RTL_IMR_BCNDOK3] = IMR_BCNDOK3,
	.maps[RTL_IMR_BCNDOK2] = IMR_BCNDOK2,
	.maps[RTL_IMR_BCNDOK1] = IMR_BCNDOK1,
	.maps[RTL_IMR_TIMEOUT2] = IMR_TIMEOUT2,
	.maps[RTL_IMR_TIMEOUT1] = IMR_TIMEOUT1,

	.maps[RTL_IMR_TXFOVW] = IMR_TXFOVW,
	.maps[RTL_IMR_PSTIMEOUT] = IMR_PSTIMEOUT,
	.maps[RTL_IMR_BCNINT] = IMR_BCNINT,
	.maps[RTL_IMR_RXFOVW] = IMR_RXFOVW,
	.maps[RTL_IMR_RDU] = IMR_RDU,
	.maps[RTL_IMR_ATIMEND] = IMR_ATIMEND,
	.maps[RTL_IMR_BDOK] = IMR_BDOK,
	.maps[RTL_IMR_MGNTDOK] = IMR_MGNTDOK,
	.maps[RTL_IMR_TBDER] = IMR_TBDER,
	.maps[RTL_IMR_HIGHDOK] = IMR_HIGHDOK,
	.maps[RTL_IMR_COMDOK] = IMR_COMDOK,
	.maps[RTL_IMR_TBDOK] = IMR_TBDOK,
	.maps[RTL_IMR_BKDOK] = IMR_BKDOK,
	.maps[RTL_IMR_BEDOK] = IMR_BEDOK,
	.maps[RTL_IMR_VIDOK] = IMR_VIDOK,
	.maps[RTL_IMR_VODOK] = IMR_VODOK,
	.maps[RTL_IMR_ROK] = IMR_ROK,
	.maps[RTL_IBSS_INT_MASKS] = (IMR_BCNINT | IMR_TBDOK | IMR_TBDER),

	.maps[RTL_RC_CCK_RATE1M] = DESC92_RATE1M,
	.maps[RTL_RC_CCK_RATE2M] = DESC92_RATE2M,
	.maps[RTL_RC_CCK_RATE5_5M] = DESC92_RATE5_5M,
	.maps[RTL_RC_CCK_RATE11M] = DESC92_RATE11M,
	.maps[RTL_RC_OFDM_RATE6M] = DESC92_RATE6M,
	.maps[RTL_RC_OFDM_RATE9M] = DESC92_RATE9M,
	.maps[RTL_RC_OFDM_RATE12M] = DESC92_RATE12M,
	.maps[RTL_RC_OFDM_RATE18M] = DESC92_RATE18M,
	.maps[RTL_RC_OFDM_RATE24M] = DESC92_RATE24M,
	.maps[RTL_RC_OFDM_RATE36M] = DESC92_RATE36M,
	.maps[RTL_RC_OFDM_RATE48M] = DESC92_RATE48M,
	.maps[RTL_RC_OFDM_RATE54M] = DESC92_RATE54M,

	.maps[RTL_RC_HT_RATEMCS7] = DESC92_RATEMCS7,
	.maps[RTL_RC_HT_RATEMCS15] = DESC92_RATEMCS15,
};

static struct pci_device_id rtl92se_pci_ids[] = {
	{RTL_PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8192, rtl92se_hal_cfg)},
	{RTL_PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8171, rtl92se_hal_cfg)},
	{RTL_PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8172, rtl92se_hal_cfg)},
	{RTL_PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8173, rtl92se_hal_cfg)},
	{RTL_PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8174, rtl92se_hal_cfg)},
	{},
};

MODULE_DEVICE_TABLE(pci, rtl92se_pci_ids);

MODULE_AUTHOR("lizhaoming	<chaoming_li@realsil.com.cn>");
MODULE_AUTHOR("Realtek WlanFAE	<wlanfae@realtek.com>");
MODULE_AUTHOR("Larry Finger	<Larry.Finger@lwfinger.net>");
MODULE_LICENSE("GPL");
MODULE_DESCRIPTION("Realtek 8192S/8191S 802.11n PCI wireless");
MODULE_FIRMWARE("rtlwifi/rtl8192sefw.bin");

module_param_named(swenc, rtl92se_mod_params.sw_crypto, bool, 0444);
module_param_named(debug, rtl92se_mod_params.debug, int, 0444);
module_param_named(ips, rtl92se_mod_params.inactiveps, bool, 0444);
module_param_named(swlps, rtl92se_mod_params.swctrl_lps, bool, 0444);
module_param_named(fwlps, rtl92se_mod_params.fwctrl_lps, bool, 0444);
MODULE_PARM_DESC(swenc, "Set to 1 for software crypto (default 0)\n");
MODULE_PARM_DESC(ips, "Set to 0 to not use link power save (default 1)\n");
MODULE_PARM_DESC(swlps, "Set to 1 to use SW control power save (default 0)\n");
MODULE_PARM_DESC(fwlps, "Set to 1 to use FW control power save (default 1)\n");
MODULE_PARM_DESC(debug, "Set debug level (0-5) (default 0)");

static SIMPLE_DEV_PM_OPS(rtlwifi_pm_ops, rtl_pci_suspend, rtl_pci_resume);

static struct pci_driver rtl92se_driver = {
	.name = KBUILD_MODNAME,
	.id_table = rtl92se_pci_ids,
	.probe = rtl_pci_probe,
	.remove = rtl_pci_disconnect,
	.driver.pm = &rtlwifi_pm_ops,
};

module_pci_driver(rtl92se_driver);
Commit	Line	Data
5a183eec CL	1	/******************************************************************************
5a183eec CL	2	*
ca742cd9	3	* Copyright(c) 2009-2012 Realtek Corporation.
5a183eec CL	4	*
	5	* This program is free software; you can redistribute it and/or modify it
	6	* under the terms of version 2 of the GNU General Public License as
	7	* published by the Free Software Foundation.
	8	*
	9	* This program is distributed in the hope that it will be useful, but WITHOUT
	10	* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
	11	* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
	12	* more details.
	13	*
	14	* You should have received a copy of the GNU General Public License along with
	15	* this program; if not, write to the Free Software Foundation, Inc.,
	16	* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
	17	*
	18	* The full GNU General Public License is included in this distribution in the
	19	* file called LICENSE.
	20	*
	21	* Contact Information:
	22	* wlanfae <wlanfae@realtek.com>
	23	* Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
	24	* Hsinchu 300, Taiwan.
	25	*
	26	* Larry Finger <Larry.Finger@lwfinger.net>
	27	*
	28	*****************************************************************************/
	29
5a183eec CL	30	#include "../wifi.h"
5a183eec CL	31	#include "../core.h"
b0302aba LF	32	#include "../base.h"
b0302aba LF	33	#include "../pci.h"
5a183eec CL	34	#include "reg.h"
	35	#include "def.h"
	36	#include "phy.h"
	37	#include "dm.h"
	38	#include "fw.h"
	39	#include "hw.h"
	40	#include "sw.h"
	41	#include "trx.h"
	42	#include "led.h"
	43
d273bb20 LF	44	#include <linux/module.h>
d273bb20 LF	45
5a183eec CL	46	static void rtl92s_init_aspm_vars(struct ieee80211_hw *hw)
	47	{
	48	struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
	49
	50	/close ASPM for AMD defaultly /
	51	rtlpci->const_amdpci_aspm = 0;
	52
dac67975	53	/* ASPM PS mode.
5a183eec CL	54	* 0 - Disable ASPM,
	55	* 1 - Enable ASPM without Clock Req,
	56	* 2 - Enable ASPM with Clock Req,
	57	* 3 - Alwyas Enable ASPM with Clock Req,
	58	* 4 - Always Enable ASPM without Clock Req.
	59	* set defult to RTL8192CE:3 RTL8192E:2
	60	* */
fc7707a4	61	rtlpci->const_pci_aspm = 2;
5a183eec CL	62
	63	/Setting for PCI-E device /
	64	rtlpci->const_devicepci_aspm_setting = 0x03;
	65
	66	/Setting for PCI-E bridge /
	67	rtlpci->const_hostpci_aspm_setting = 0x02;
	68
dac67975	69	/* In Hw/Sw Radio Off situation.
5a183eec CL	70	* 0 - Default,
	71	* 1 - From ASPM setting without low Mac Pwr,
	72	* 2 - From ASPM setting with low Mac Pwr,
	73	* 3 - Bus D3
	74	* set default to RTL8192CE:0 RTL8192SE:2
	75	*/
	76	rtlpci->const_hwsw_rfoff_d3 = 2;
	77
dac67975	78	/* This setting works for those device with
5a183eec CL	79	* backdoor ASPM setting such as EPHY setting.
	80	* 0 - Not support ASPM,
	81	* 1 - Support ASPM,
	82	* 2 - According to chipset.
	83	*/
	84	rtlpci->const_support_pciaspm = 2;
	85	}
	86
b0302aba LF	87	static void rtl92se_fw_cb(const struct firmware firmware, void context)
	88	{
	89	struct ieee80211_hw *hw = context;
	90	struct rtl_pci_priv *pcipriv = rtl_pcipriv(hw);
	91	struct rtl_priv *rtlpriv = rtl_priv(hw);
	92	struct rtl_pci *rtlpci = rtl_pcidev(pcipriv);
	93	struct rt_firmware *pfirmware = NULL;
	94	int err;
	95
	96	RT_TRACE(rtlpriv, COMP_ERR, DBG_LOUD,
	97	"Firmware callback routine entered!\n");
	98	complete(&rtlpriv->firmware_loading_complete);
	99	if (!firmware) {
	100	pr_err("Firmware %s not available\n", rtlpriv->cfg->fw_name);
	101	rtlpriv->max_fw_size = 0;
	102	return;
	103	}
	104	if (firmware->size > rtlpriv->max_fw_size) {
	105	RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
	106	"Firmware is too big!\n");
3fccdcf5	107	rtlpriv->max_fw_size = 0;
b0302aba LF	108	release_firmware(firmware);
	109	return;
	110	}
	111	pfirmware = (struct rt_firmware *)rtlpriv->rtlhal.pfirmware;
	112	memcpy(pfirmware->sz_fw_tmpbuffer, firmware->data, firmware->size);
	113	pfirmware->sz_fw_tmpbufferlen = firmware->size;
	114	release_firmware(firmware);
	115
	116	err = ieee80211_register_hw(hw);
	117	if (err) {
	118	RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
	119	"Can't register mac80211 hw\n");
	120	return;
	121	} else {
	122	rtlpriv->mac80211.mac80211_registered = 1;
	123	}
	124	rtlpci->irq_alloc = 1;
	125	set_bit(RTL_STATUS_INTERFACE_START, &rtlpriv->status);
	126
	127	/init rfkill /
	128	rtl_init_rfkill(hw);
	129	}
	130
5a183eec CL	131	static int rtl92s_init_sw_vars(struct ieee80211_hw *hw)
	132	{
	133	struct rtl_priv *rtlpriv = rtl_priv(hw);
	134	struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
5a183eec CL	135	int err = 0;
	136	u16 earlyrxthreshold = 7;
	137
3db1cd5c	138	rtlpriv->dm.dm_initialgain_enable = true;
5a183eec	139	rtlpriv->dm.dm_flag = 0;
3db1cd5c	140	rtlpriv->dm.disable_framebursting = false;
5a183eec CL	141	rtlpriv->dm.thermalvalue = 0;
	142	rtlpriv->dm.useramask = true;
	143
	144	/* compatible 5G band 91se just 2.4G band & smsp */
	145	rtlpriv->rtlhal.current_bandtype = BAND_ON_2_4G;
	146	rtlpriv->rtlhal.bandset = BAND_ON_2_4G;
	147	rtlpriv->rtlhal.macphymode = SINGLEMAC_SINGLEPHY;
	148
	149	rtlpci->transmit_config = 0;
	150
	151	rtlpci->receive_config =
	152	RCR_APPFCS \|
	153	RCR_APWRMGT \|
	154	/RCR_ADD3 \|/
	155	RCR_AMF \|
	156	RCR_ADF \|
	157	RCR_APP_MIC \|
	158	RCR_APP_ICV \|
	159	RCR_AICV \|
	160	/* Accept ICV error, CRC32 Error */
	161	RCR_ACRC32 \|
	162	RCR_AB \|
	163	/* Accept Broadcast, Multicast */
	164	RCR_AM \|
	165	/* Accept Physical match */
	166	RCR_APM \|
	167	/* Accept Destination Address packets */
	168	/RCR_AAP \|/
	169	RCR_APP_PHYST_STAFF \|
	170	/* Accept PHY status */
	171	RCR_APP_PHYST_RXFF \|
	172	(earlyrxthreshold << RCR_FIFO_OFFSET);
	173
	174	rtlpci->irq_mask[0] = (u32)
	175	(IMR_ROK \|
	176	IMR_VODOK \|
	177	IMR_VIDOK \|
	178	IMR_BEDOK \|
	179	IMR_BKDOK \|
	180	IMR_HCCADOK \|
	181	IMR_MGNTDOK \|
	182	IMR_COMDOK \|
	183	IMR_HIGHDOK \|
	184	IMR_BDOK \|
	185	IMR_RXCMDOK \|
	186	/IMR_TIMEOUT0 \|/
	187	IMR_RDU \|
	188	IMR_RXFOVW \|
	189	IMR_BCNINT
	190	/\| IMR_TXFOVW/
	191	/*\| IMR_TBDOK \|
	192	IMR_TBDER*/);
	193
	194	rtlpci->irq_mask[1] = (u32) 0;
	195
	196	rtlpci->shortretry_limit = 0x30;
	197	rtlpci->longretry_limit = 0x30;
	198
	199	rtlpci->first_init = true;
	200
73a253ca LF	201	/* for debug level */
73a253ca LF	202	rtlpriv->dbg.global_debuglevel = rtlpriv->cfg->mod_params->debug;
5a183eec CL	203	/* for LPS & IPS */
	204	rtlpriv->psc.inactiveps = rtlpriv->cfg->mod_params->inactiveps;
	205	rtlpriv->psc.swctrl_lps = rtlpriv->cfg->mod_params->swctrl_lps;
	206	rtlpriv->psc.fwctrl_lps = rtlpriv->cfg->mod_params->fwctrl_lps;
7664beeb	207	if (!rtlpriv->psc.inactiveps)
d9595ce3	208	pr_info("Power Save off (module option)\n");
7664beeb	209	if (!rtlpriv->psc.fwctrl_lps)
d9595ce3	210	pr_info("FW Power Save off (module option)\n");
5a183eec CL	211	rtlpriv->psc.reg_fwctrl_lps = 3;
	212	rtlpriv->psc.reg_max_lps_awakeintvl = 5;
	213	/* for ASPM, you can close aspm through
	214	* set const_support_pciaspm = 0 */
	215	rtl92s_init_aspm_vars(hw);
	216
	217	if (rtlpriv->psc.reg_fwctrl_lps == 1)
	218	rtlpriv->psc.fwctrl_psmode = FW_PS_MIN_MODE;
	219	else if (rtlpriv->psc.reg_fwctrl_lps == 2)
	220	rtlpriv->psc.fwctrl_psmode = FW_PS_MAX_MODE;
	221	else if (rtlpriv->psc.reg_fwctrl_lps == 3)
	222	rtlpriv->psc.fwctrl_psmode = FW_PS_DTIM_MODE;
	223
	224	/* for firmware buf */
	225	rtlpriv->rtlhal.pfirmware = vzalloc(sizeof(struct rt_firmware));
e404decb	226	if (!rtlpriv->rtlhal.pfirmware)
5a183eec	227	return 1;
5a183eec	228
3fccdcf5	229	rtlpriv->max_fw_size = RTL8190_MAX_RAW_FIRMWARE_CODE_SIZE;
b0302aba	230
292b1192 JP	231	pr_info("Driver for Realtek RTL8192SE/RTL8191SE\n"
292b1192 JP	232	"Loading firmware %s\n", rtlpriv->cfg->fw_name);
5a183eec	233	/* request fw */
b0302aba LF	234	err = request_firmware_nowait(THIS_MODULE, 1, rtlpriv->cfg->fw_name,
	235	rtlpriv->io.dev, GFP_KERNEL, hw,
	236	rtl92se_fw_cb);
5a183eec CL	237	if (err) {
5a183eec CL	238	RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
f30d7507	239	"Failed to request firmware!\n");
5a183eec CL	240	return 1;
5a183eec CL	241	}
5a183eec CL	242
	243	return err;
	244	}
	245
	246	static void rtl92s_deinit_sw_vars(struct ieee80211_hw *hw)
	247	{
	248	struct rtl_priv *rtlpriv = rtl_priv(hw);
	249
	250	if (rtlpriv->rtlhal.pfirmware) {
	251	vfree(rtlpriv->rtlhal.pfirmware);
	252	rtlpriv->rtlhal.pfirmware = NULL;
	253	}
	254	}
	255
	256	static struct rtl_hal_ops rtl8192se_hal_ops = {
	257	.init_sw_vars = rtl92s_init_sw_vars,
	258	.deinit_sw_vars = rtl92s_deinit_sw_vars,
	259	.read_eeprom_info = rtl92se_read_eeprom_info,
	260	.interrupt_recognized = rtl92se_interrupt_recognized,
	261	.hw_init = rtl92se_hw_init,
	262	.hw_disable = rtl92se_card_disable,
	263	.hw_suspend = rtl92se_suspend,
	264	.hw_resume = rtl92se_resume,
	265	.enable_interrupt = rtl92se_enable_interrupt,
	266	.disable_interrupt = rtl92se_disable_interrupt,
	267	.set_network_type = rtl92se_set_network_type,
	268	.set_chk_bssid = rtl92se_set_check_bssid,
	269	.set_qos = rtl92se_set_qos,
	270	.set_bcn_reg = rtl92se_set_beacon_related_registers,
	271	.set_bcn_intv = rtl92se_set_beacon_interval,
	272	.update_interrupt_mask = rtl92se_update_interrupt_mask,
	273	.get_hw_reg = rtl92se_get_hw_reg,
	274	.set_hw_reg = rtl92se_set_hw_reg,
	275	.update_rate_tbl = rtl92se_update_hal_rate_tbl,
	276	.fill_tx_desc = rtl92se_tx_fill_desc,
	277	.fill_tx_cmddesc = rtl92se_tx_fill_cmddesc,
	278	.query_rx_desc = rtl92se_rx_query_desc,
	279	.set_channel_access = rtl92se_update_channel_access_setting,
	280	.radio_onoff_checking = rtl92se_gpio_radio_on_off_checking,
	281	.set_bw_mode = rtl92s_phy_set_bw_mode,
	282	.switch_channel = rtl92s_phy_sw_chnl,
	283	.dm_watchdog = rtl92s_dm_watchdog,
	284	.scan_operation_backup = rtl92s_phy_scan_operation_backup,
	285	.set_rf_power_state = rtl92s_phy_set_rf_power_state,
	286	.led_control = rtl92se_led_control,
	287	.set_desc = rtl92se_set_desc,
	288	.get_desc = rtl92se_get_desc,
	289	.tx_polling = rtl92se_tx_polling,
	290	.enable_hw_sec = rtl92se_enable_hw_security_config,
	291	.set_key = rtl92se_set_key,
	292	.init_sw_leds = rtl92se_init_sw_leds,
2455c92c	293	.allow_all_destaddr = rtl92se_allow_all_destaddr,
5a183eec CL	294	.get_bbreg = rtl92s_phy_query_bb_reg,
	295	.set_bbreg = rtl92s_phy_set_bb_reg,
	296	.get_rfreg = rtl92s_phy_query_rf_reg,
	297	.set_rfreg = rtl92s_phy_set_rf_reg,
	298	};
	299
	300	static struct rtl_mod_params rtl92se_mod_params = {
	301	.sw_crypto = false,
	302	.inactiveps = true,
	303	.swctrl_lps = true,
	304	.fwctrl_lps = false,
73a253ca	305	.debug = DBG_EMERG,
5a183eec CL	306	};
	307
	308	/* Because memory R/W bursting will cause system hang/crash
	309	* for 92se, so we don't read back after every write action */
	310	static struct rtl_hal_cfg rtl92se_hal_cfg = {
	311	.bar_id = 1,
	312	.write_readback = false,
	313	.name = "rtl92s_pci",
	314	.fw_name = "rtlwifi/rtl8192sefw.bin",
	315	.ops = &rtl8192se_hal_ops,
	316	.mod_params = &rtl92se_mod_params,
	317
	318	.maps[SYS_ISO_CTRL] = REG_SYS_ISO_CTRL,
	319	.maps[SYS_FUNC_EN] = REG_SYS_FUNC_EN,
	320	.maps[SYS_CLK] = SYS_CLKR,
	321	.maps[MAC_RCR_AM] = RCR_AM,
	322	.maps[MAC_RCR_AB] = RCR_AB,
	323	.maps[MAC_RCR_ACRC32] = RCR_ACRC32,
	324	.maps[MAC_RCR_ACF] = RCR_ACF,
	325	.maps[MAC_RCR_AAP] = RCR_AAP,
	326
	327	.maps[EFUSE_TEST] = REG_EFUSE_TEST,
	328	.maps[EFUSE_CTRL] = REG_EFUSE_CTRL,
	329	.maps[EFUSE_CLK] = REG_EFUSE_CLK,
	330	.maps[EFUSE_CLK_CTRL] = REG_EFUSE_CTRL,
	331	.maps[EFUSE_PWC_EV12V] = 0, /* nouse for 8192se */
	332	.maps[EFUSE_FEN_ELDR] = 0, /* nouse for 8192se */
	333	.maps[EFUSE_LOADER_CLK_EN] = 0,/* nouse for 8192se */
	334	.maps[EFUSE_ANA8M] = EFUSE_ANA8M,
	335	.maps[EFUSE_HWSET_MAX_SIZE] = HWSET_MAX_SIZE_92S,
	336	.maps[EFUSE_MAX_SECTION_MAP] = EFUSE_MAX_SECTION,
	337	.maps[EFUSE_REAL_CONTENT_SIZE] = EFUSE_REAL_CONTENT_LEN,
5c079d88	338	.maps[EFUSE_OOB_PROTECT_BYTES_LEN] = EFUSE_OOB_PROTECT_BYTES,
5a183eec CL	339
	340	.maps[RWCAM] = REG_RWCAM,
	341	.maps[WCAMI] = REG_WCAMI,
	342	.maps[RCAMO] = REG_RCAMO,
	343	.maps[CAMDBG] = REG_CAMDBG,
	344	.maps[SECR] = REG_SECR,
	345	.maps[SEC_CAM_NONE] = CAM_NONE,
	346	.maps[SEC_CAM_WEP40] = CAM_WEP40,
	347	.maps[SEC_CAM_TKIP] = CAM_TKIP,
	348	.maps[SEC_CAM_AES] = CAM_AES,
	349	.maps[SEC_CAM_WEP104] = CAM_WEP104,
	350
	351	.maps[RTL_IMR_BCNDMAINT6] = IMR_BCNDMAINT6,
	352	.maps[RTL_IMR_BCNDMAINT5] = IMR_BCNDMAINT5,
	353	.maps[RTL_IMR_BCNDMAINT4] = IMR_BCNDMAINT4,
	354	.maps[RTL_IMR_BCNDMAINT3] = IMR_BCNDMAINT3,
	355	.maps[RTL_IMR_BCNDMAINT2] = IMR_BCNDMAINT2,
	356	.maps[RTL_IMR_BCNDMAINT1] = IMR_BCNDMAINT1,
	357	.maps[RTL_IMR_BCNDOK8] = IMR_BCNDOK8,
	358	.maps[RTL_IMR_BCNDOK7] = IMR_BCNDOK7,
	359	.maps[RTL_IMR_BCNDOK6] = IMR_BCNDOK6,
	360	.maps[RTL_IMR_BCNDOK5] = IMR_BCNDOK5,
	361	.maps[RTL_IMR_BCNDOK4] = IMR_BCNDOK4,
	362	.maps[RTL_IMR_BCNDOK3] = IMR_BCNDOK3,
	363	.maps[RTL_IMR_BCNDOK2] = IMR_BCNDOK2,
	364	.maps[RTL_IMR_BCNDOK1] = IMR_BCNDOK1,
	365	.maps[RTL_IMR_TIMEOUT2] = IMR_TIMEOUT2,
	366	.maps[RTL_IMR_TIMEOUT1] = IMR_TIMEOUT1,
	367
	368	.maps[RTL_IMR_TXFOVW] = IMR_TXFOVW,
	369	.maps[RTL_IMR_PSTIMEOUT] = IMR_PSTIMEOUT,
e6deaf81	370	.maps[RTL_IMR_BCNINT] = IMR_BCNINT,
5a183eec CL	371	.maps[RTL_IMR_RXFOVW] = IMR_RXFOVW,
	372	.maps[RTL_IMR_RDU] = IMR_RDU,
	373	.maps[RTL_IMR_ATIMEND] = IMR_ATIMEND,
	374	.maps[RTL_IMR_BDOK] = IMR_BDOK,
	375	.maps[RTL_IMR_MGNTDOK] = IMR_MGNTDOK,
	376	.maps[RTL_IMR_TBDER] = IMR_TBDER,
	377	.maps[RTL_IMR_HIGHDOK] = IMR_HIGHDOK,
	378	.maps[RTL_IMR_COMDOK] = IMR_COMDOK,
	379	.maps[RTL_IMR_TBDOK] = IMR_TBDOK,
	380	.maps[RTL_IMR_BKDOK] = IMR_BKDOK,
	381	.maps[RTL_IMR_BEDOK] = IMR_BEDOK,
	382	.maps[RTL_IMR_VIDOK] = IMR_VIDOK,
	383	.maps[RTL_IMR_VODOK] = IMR_VODOK,
	384	.maps[RTL_IMR_ROK] = IMR_ROK,
	385	.maps[RTL_IBSS_INT_MASKS] = (IMR_BCNINT \| IMR_TBDOK \| IMR_TBDER),
	386
8e353377 LF	387	.maps[RTL_RC_CCK_RATE1M] = DESC92_RATE1M,
	388	.maps[RTL_RC_CCK_RATE2M] = DESC92_RATE2M,
	389	.maps[RTL_RC_CCK_RATE5_5M] = DESC92_RATE5_5M,
	390	.maps[RTL_RC_CCK_RATE11M] = DESC92_RATE11M,
	391	.maps[RTL_RC_OFDM_RATE6M] = DESC92_RATE6M,
	392	.maps[RTL_RC_OFDM_RATE9M] = DESC92_RATE9M,
	393	.maps[RTL_RC_OFDM_RATE12M] = DESC92_RATE12M,
	394	.maps[RTL_RC_OFDM_RATE18M] = DESC92_RATE18M,
	395	.maps[RTL_RC_OFDM_RATE24M] = DESC92_RATE24M,
	396	.maps[RTL_RC_OFDM_RATE36M] = DESC92_RATE36M,
	397	.maps[RTL_RC_OFDM_RATE48M] = DESC92_RATE48M,
	398	.maps[RTL_RC_OFDM_RATE54M] = DESC92_RATE54M,
	399
	400	.maps[RTL_RC_HT_RATEMCS7] = DESC92_RATEMCS7,
	401	.maps[RTL_RC_HT_RATEMCS15] = DESC92_RATEMCS15,
5a183eec CL	402	};
5a183eec CL	403
9e2ff36b	404	static struct pci_device_id rtl92se_pci_ids[] = {
5a183eec CL	405	{RTL_PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8192, rtl92se_hal_cfg)},
	406	{RTL_PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8171, rtl92se_hal_cfg)},
	407	{RTL_PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8172, rtl92se_hal_cfg)},
	408	{RTL_PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8173, rtl92se_hal_cfg)},
	409	{RTL_PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8174, rtl92se_hal_cfg)},
	410	{},
	411	};
	412
	413	MODULE_DEVICE_TABLE(pci, rtl92se_pci_ids);
	414
	415	MODULE_AUTHOR("lizhaoming <chaoming_li@realsil.com.cn>");
	416	MODULE_AUTHOR("Realtek WlanFAE <wlanfae@realtek.com>");
7664beeb	417	MODULE_AUTHOR("Larry Finger <Larry.Finger@lwfinger.net>");
5a183eec CL	418	MODULE_LICENSE("GPL");
	419	MODULE_DESCRIPTION("Realtek 8192S/8191S 802.11n PCI wireless");
	420	MODULE_FIRMWARE("rtlwifi/rtl8192sefw.bin");
	421
	422	module_param_named(swenc, rtl92se_mod_params.sw_crypto, bool, 0444);
73a253ca	423	module_param_named(debug, rtl92se_mod_params.debug, int, 0444);
5a183eec CL	424	module_param_named(ips, rtl92se_mod_params.inactiveps, bool, 0444);
	425	module_param_named(swlps, rtl92se_mod_params.swctrl_lps, bool, 0444);
	426	module_param_named(fwlps, rtl92se_mod_params.fwctrl_lps, bool, 0444);
7664beeb LF	427	MODULE_PARM_DESC(swenc, "Set to 1 for software crypto (default 0)\n");
	428	MODULE_PARM_DESC(ips, "Set to 0 to not use link power save (default 1)\n");
	429	MODULE_PARM_DESC(swlps, "Set to 1 to use SW control power save (default 0)\n");
	430	MODULE_PARM_DESC(fwlps, "Set to 1 to use FW control power save (default 1)\n");
73a253ca	431	MODULE_PARM_DESC(debug, "Set debug level (0-5) (default 0)");
5a183eec	432
244a77e9	433	static SIMPLE_DEV_PM_OPS(rtlwifi_pm_ops, rtl_pci_suspend, rtl_pci_resume);
603be388	434
5a183eec CL	435	static struct pci_driver rtl92se_driver = {
	436	.name = KBUILD_MODNAME,
	437	.id_table = rtl92se_pci_ids,
	438	.probe = rtl_pci_probe,
	439	.remove = rtl_pci_disconnect,
603be388	440	.driver.pm = &rtlwifi_pm_ops,
5a183eec CL	441	};
5a183eec CL	442
5b0a3b7e	443	module_pci_driver(rtl92se_driver);