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c592e631 LF |
1 | /****************************************************************************** |
2 | * | |
3 | * Copyright(c) 2009-2012 Realtek Corporation. | |
4 | * | |
5 | * This program is free software; you can redistribute it and/or modify it | |
6 | * under the terms of version 2 of the GNU General Public License as | |
7 | * published by the Free Software Foundation. | |
8 | * | |
9 | * This program is distributed in the hope that it will be useful, but WITHOUT | |
10 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
11 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | |
12 | * more details. | |
13 | * | |
14 | * You should have received a copy of the GNU General Public License along with | |
15 | * this program; if not, write to the Free Software Foundation, Inc., | |
16 | * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA | |
17 | * | |
18 | * The full GNU General Public License is included in this distribution in the | |
19 | * file called LICENSE. | |
20 | * | |
21 | * Contact Information: | |
22 | * wlanfae <wlanfae@realtek.com> | |
23 | * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park, | |
24 | * Hsinchu 300, Taiwan. | |
25 | * | |
26 | * Larry Finger <Larry.Finger@lwfinger.net> | |
27 | * | |
28 | *****************************************************************************/ | |
29 | ||
30 | #include "../wifi.h" | |
31 | #include "../efuse.h" | |
32 | #include "../base.h" | |
33 | #include "../regd.h" | |
34 | #include "../cam.h" | |
35 | #include "../ps.h" | |
36 | #include "../pci.h" | |
37 | #include "reg.h" | |
38 | #include "def.h" | |
39 | #include "phy.h" | |
40 | #include "dm.h" | |
41 | #include "fw.h" | |
42 | #include "led.h" | |
43 | #include "hw.h" | |
44 | #include "pwrseqcmd.h" | |
45 | #include "pwrseq.h" | |
46 | #include "btc.h" | |
47 | ||
48 | static void _rtl8723ae_set_bcn_ctrl_reg(struct ieee80211_hw *hw, | |
49 | u8 set_bits, u8 clear_bits) | |
50 | { | |
51 | struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw)); | |
52 | struct rtl_priv *rtlpriv = rtl_priv(hw); | |
53 | ||
54 | rtlpci->reg_bcn_ctrl_val |= set_bits; | |
55 | rtlpci->reg_bcn_ctrl_val &= ~clear_bits; | |
56 | ||
57 | rtl_write_byte(rtlpriv, REG_BCN_CTRL, (u8) rtlpci->reg_bcn_ctrl_val); | |
58 | } | |
59 | ||
60 | static void _rtl8723ae_stop_tx_beacon(struct ieee80211_hw *hw) | |
61 | { | |
62 | struct rtl_priv *rtlpriv = rtl_priv(hw); | |
63 | u8 tmp1byte; | |
64 | ||
65 | tmp1byte = rtl_read_byte(rtlpriv, REG_FWHW_TXQ_CTRL + 2); | |
66 | rtl_write_byte(rtlpriv, REG_FWHW_TXQ_CTRL + 2, tmp1byte & (~BIT(6))); | |
67 | rtl_write_byte(rtlpriv, REG_TBTT_PROHIBIT + 1, 0x64); | |
68 | tmp1byte = rtl_read_byte(rtlpriv, REG_TBTT_PROHIBIT + 2); | |
69 | tmp1byte &= ~(BIT(0)); | |
70 | rtl_write_byte(rtlpriv, REG_TBTT_PROHIBIT + 2, tmp1byte); | |
71 | } | |
72 | ||
73 | static void _rtl8723ae_resume_tx_beacon(struct ieee80211_hw *hw) | |
74 | { | |
75 | struct rtl_priv *rtlpriv = rtl_priv(hw); | |
76 | u8 tmp1byte; | |
77 | ||
78 | tmp1byte = rtl_read_byte(rtlpriv, REG_FWHW_TXQ_CTRL + 2); | |
79 | rtl_write_byte(rtlpriv, REG_FWHW_TXQ_CTRL + 2, tmp1byte | BIT(6)); | |
80 | rtl_write_byte(rtlpriv, REG_TBTT_PROHIBIT + 1, 0xff); | |
81 | tmp1byte = rtl_read_byte(rtlpriv, REG_TBTT_PROHIBIT + 2); | |
82 | tmp1byte |= BIT(1); | |
83 | rtl_write_byte(rtlpriv, REG_TBTT_PROHIBIT + 2, tmp1byte); | |
84 | } | |
85 | ||
86 | static void _rtl8723ae_enable_bcn_sufunc(struct ieee80211_hw *hw) | |
87 | { | |
88 | _rtl8723ae_set_bcn_ctrl_reg(hw, 0, BIT(1)); | |
89 | } | |
90 | ||
91 | static void _rtl8723ae_disable_bcn_sufunc(struct ieee80211_hw *hw) | |
92 | { | |
93 | _rtl8723ae_set_bcn_ctrl_reg(hw, BIT(1), 0); | |
94 | } | |
95 | ||
96 | void rtl8723ae_get_hw_reg(struct ieee80211_hw *hw, u8 variable, u8 *val) | |
97 | { | |
98 | struct rtl_priv *rtlpriv = rtl_priv(hw); | |
99 | struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw)); | |
100 | struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw)); | |
101 | ||
102 | switch (variable) { | |
103 | case HW_VAR_RCR: | |
104 | *((u32 *) (val)) = rtlpci->receive_config; | |
105 | break; | |
106 | case HW_VAR_RF_STATE: | |
107 | *((enum rf_pwrstate *)(val)) = ppsc->rfpwr_state; | |
108 | break; | |
109 | case HW_VAR_FWLPS_RF_ON:{ | |
110 | enum rf_pwrstate rfState; | |
111 | u32 val_rcr; | |
112 | ||
113 | rtlpriv->cfg->ops->get_hw_reg(hw, | |
114 | HW_VAR_RF_STATE, | |
115 | (u8 *) (&rfState)); | |
116 | if (rfState == ERFOFF) { | |
117 | *((bool *) (val)) = true; | |
118 | } else { | |
119 | val_rcr = rtl_read_dword(rtlpriv, REG_RCR); | |
120 | val_rcr &= 0x00070000; | |
121 | if (val_rcr) | |
122 | *((bool *) (val)) = false; | |
123 | else | |
124 | *((bool *) (val)) = true; | |
125 | } | |
126 | break; } | |
127 | case HW_VAR_FW_PSMODE_STATUS: | |
128 | *((bool *) (val)) = ppsc->fw_current_inpsmode; | |
129 | break; | |
130 | case HW_VAR_CORRECT_TSF:{ | |
131 | u64 tsf; | |
132 | u32 *ptsf_low = (u32 *)&tsf; | |
133 | u32 *ptsf_high = ((u32 *)&tsf) + 1; | |
134 | ||
135 | *ptsf_high = rtl_read_dword(rtlpriv, (REG_TSFTR + 4)); | |
136 | *ptsf_low = rtl_read_dword(rtlpriv, REG_TSFTR); | |
137 | ||
138 | *((u64 *) (val)) = tsf; | |
139 | ||
140 | break; } | |
141 | default: | |
142 | RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG, | |
143 | "switch case not process\n"); | |
144 | break; | |
145 | } | |
146 | } | |
147 | ||
148 | void rtl8723ae_set_hw_reg(struct ieee80211_hw *hw, u8 variable, u8 *val) | |
149 | { | |
150 | struct rtl_priv *rtlpriv = rtl_priv(hw); | |
151 | struct rtl_pci_priv *pcipriv = rtl_pcipriv(hw); | |
152 | struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw)); | |
153 | struct rtl_mac *mac = rtl_mac(rtl_priv(hw)); | |
154 | struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw)); | |
155 | struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw)); | |
156 | u8 idx; | |
157 | ||
158 | switch (variable) { | |
159 | case HW_VAR_ETHER_ADDR: | |
160 | for (idx = 0; idx < ETH_ALEN; idx++) { | |
161 | rtl_write_byte(rtlpriv, (REG_MACID + idx), | |
162 | val[idx]); | |
163 | } | |
164 | break; | |
165 | case HW_VAR_BASIC_RATE:{ | |
166 | u16 rate_cfg = ((u16 *) val)[0]; | |
167 | u8 rate_index = 0; | |
168 | rate_cfg = rate_cfg & 0x15f; | |
169 | rate_cfg |= 0x01; | |
170 | rtl_write_byte(rtlpriv, REG_RRSR, rate_cfg & 0xff); | |
171 | rtl_write_byte(rtlpriv, REG_RRSR + 1, | |
172 | (rate_cfg >> 8) & 0xff); | |
173 | while (rate_cfg > 0x1) { | |
174 | rate_cfg = (rate_cfg >> 1); | |
175 | rate_index++; | |
176 | } | |
177 | rtl_write_byte(rtlpriv, REG_INIRTS_RATE_SEL, | |
178 | rate_index); | |
179 | break; } | |
180 | case HW_VAR_BSSID: | |
181 | for (idx = 0; idx < ETH_ALEN; idx++) { | |
182 | rtl_write_byte(rtlpriv, (REG_BSSID + idx), | |
183 | val[idx]); | |
184 | } | |
185 | break; | |
186 | case HW_VAR_SIFS: | |
187 | rtl_write_byte(rtlpriv, REG_SIFS_CTX + 1, val[0]); | |
188 | rtl_write_byte(rtlpriv, REG_SIFS_TRX + 1, val[1]); | |
189 | ||
190 | rtl_write_byte(rtlpriv, REG_SPEC_SIFS + 1, val[0]); | |
191 | rtl_write_byte(rtlpriv, REG_MAC_SPEC_SIFS + 1, val[0]); | |
192 | ||
193 | if (!mac->ht_enable) | |
194 | rtl_write_word(rtlpriv, REG_RESP_SIFS_OFDM, | |
195 | 0x0e0e); | |
196 | else | |
197 | rtl_write_word(rtlpriv, REG_RESP_SIFS_OFDM, | |
198 | *((u16 *) val)); | |
199 | break; | |
200 | case HW_VAR_SLOT_TIME:{ | |
201 | u8 e_aci; | |
202 | ||
203 | RT_TRACE(rtlpriv, COMP_MLME, DBG_LOUD, | |
204 | "HW_VAR_SLOT_TIME %x\n", val[0]); | |
205 | ||
206 | rtl_write_byte(rtlpriv, REG_SLOT, val[0]); | |
207 | ||
208 | for (e_aci = 0; e_aci < AC_MAX; e_aci++) { | |
209 | rtlpriv->cfg->ops->set_hw_reg(hw, | |
210 | HW_VAR_AC_PARAM, | |
211 | (u8 *) (&e_aci)); | |
212 | } | |
213 | break; } | |
214 | case HW_VAR_ACK_PREAMBLE:{ | |
215 | u8 reg_tmp; | |
216 | u8 short_preamble = (bool) (*(u8 *) val); | |
217 | reg_tmp = (mac->cur_40_prime_sc) << 5; | |
218 | if (short_preamble) | |
219 | reg_tmp |= 0x80; | |
220 | ||
221 | rtl_write_byte(rtlpriv, REG_RRSR + 2, reg_tmp); | |
222 | break; } | |
223 | case HW_VAR_AMPDU_MIN_SPACE:{ | |
224 | u8 min_spacing_to_set; | |
225 | u8 sec_min_space; | |
226 | ||
227 | min_spacing_to_set = *((u8 *) val); | |
228 | if (min_spacing_to_set <= 7) { | |
229 | sec_min_space = 0; | |
230 | ||
231 | if (min_spacing_to_set < sec_min_space) | |
232 | min_spacing_to_set = sec_min_space; | |
233 | ||
234 | mac->min_space_cfg = ((mac->min_space_cfg & | |
235 | 0xf8) | | |
236 | min_spacing_to_set); | |
237 | ||
238 | *val = min_spacing_to_set; | |
239 | ||
240 | RT_TRACE(rtlpriv, COMP_MLME, DBG_LOUD, | |
241 | "Set HW_VAR_AMPDU_MIN_SPACE: %#x\n", | |
242 | mac->min_space_cfg); | |
243 | ||
244 | rtl_write_byte(rtlpriv, REG_AMPDU_MIN_SPACE, | |
245 | mac->min_space_cfg); | |
246 | } | |
247 | break; } | |
248 | case HW_VAR_SHORTGI_DENSITY:{ | |
249 | u8 density_to_set; | |
250 | ||
251 | density_to_set = *((u8 *) val); | |
252 | mac->min_space_cfg |= (density_to_set << 3); | |
253 | ||
254 | RT_TRACE(rtlpriv, COMP_MLME, DBG_LOUD, | |
255 | "Set HW_VAR_SHORTGI_DENSITY: %#x\n", | |
256 | mac->min_space_cfg); | |
257 | ||
258 | rtl_write_byte(rtlpriv, REG_AMPDU_MIN_SPACE, | |
259 | mac->min_space_cfg); | |
260 | ||
261 | break; } | |
262 | case HW_VAR_AMPDU_FACTOR:{ | |
263 | u8 regtoset_normal[4] = {0x41, 0xa8, 0x72, 0xb9}; | |
264 | u8 regtoset_bt[4] = {0x31, 0x74, 0x42, 0x97}; | |
265 | u8 factor_toset; | |
266 | u8 *p_regtoset = NULL; | |
267 | u8 index; | |
268 | ||
269 | if ((pcipriv->bt_coexist.bt_coexistence) && | |
270 | (pcipriv->bt_coexist.bt_coexist_type == BT_CSR_BC4)) | |
271 | p_regtoset = regtoset_bt; | |
272 | else | |
273 | p_regtoset = regtoset_normal; | |
274 | ||
275 | factor_toset = *((u8 *) val); | |
276 | if (factor_toset <= 3) { | |
277 | factor_toset = (1 << (factor_toset + 2)); | |
278 | if (factor_toset > 0xf) | |
279 | factor_toset = 0xf; | |
280 | ||
281 | for (index = 0; index < 4; index++) { | |
282 | if ((p_regtoset[index] & 0xf0) > | |
283 | (factor_toset << 4)) | |
284 | p_regtoset[index] = | |
285 | (p_regtoset[index] & 0x0f) | | |
286 | (factor_toset << 4); | |
287 | ||
288 | if ((p_regtoset[index] & 0x0f) > | |
289 | factor_toset) | |
290 | p_regtoset[index] = | |
291 | (p_regtoset[index] & 0xf0) | | |
292 | (factor_toset); | |
293 | ||
294 | rtl_write_byte(rtlpriv, | |
295 | (REG_AGGLEN_LMT + index), | |
296 | p_regtoset[index]); | |
297 | ||
298 | } | |
299 | ||
300 | RT_TRACE(rtlpriv, COMP_MLME, DBG_LOUD, | |
301 | "Set HW_VAR_AMPDU_FACTOR: %#x\n", | |
302 | factor_toset); | |
303 | } | |
304 | break; } | |
305 | case HW_VAR_AC_PARAM:{ | |
306 | u8 e_aci = *((u8 *) val); | |
307 | rtl8723ae_dm_init_edca_turbo(hw); | |
308 | ||
309 | if (rtlpci->acm_method != eAcmWay2_SW) | |
310 | rtlpriv->cfg->ops->set_hw_reg(hw, | |
311 | HW_VAR_ACM_CTRL, | |
312 | (u8 *) (&e_aci)); | |
313 | break; } | |
314 | case HW_VAR_ACM_CTRL:{ | |
315 | u8 e_aci = *((u8 *) val); | |
316 | union aci_aifsn *p_aci_aifsn = | |
317 | (union aci_aifsn *)(&(mac->ac[0].aifs)); | |
318 | u8 acm = p_aci_aifsn->f.acm; | |
319 | u8 acm_ctrl = rtl_read_byte(rtlpriv, REG_ACMHWCTRL); | |
320 | ||
321 | acm_ctrl |= ((rtlpci->acm_method == 2) ? 0x0 : 0x1); | |
322 | ||
323 | if (acm) { | |
324 | switch (e_aci) { | |
325 | case AC0_BE: | |
326 | acm_ctrl |= AcmHw_BeqEn; | |
327 | break; | |
328 | case AC2_VI: | |
329 | acm_ctrl |= AcmHw_ViqEn; | |
330 | break; | |
331 | case AC3_VO: | |
332 | acm_ctrl |= AcmHw_VoqEn; | |
333 | break; | |
334 | default: | |
335 | RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING, | |
336 | "HW_VAR_ACM_CTRL acm set failed: eACI is %d\n", | |
337 | acm); | |
338 | break; | |
339 | } | |
340 | } else { | |
341 | switch (e_aci) { | |
342 | case AC0_BE: | |
343 | acm_ctrl &= (~AcmHw_BeqEn); | |
344 | break; | |
345 | case AC2_VI: | |
346 | acm_ctrl &= (~AcmHw_ViqEn); | |
347 | break; | |
348 | case AC3_VO: | |
349 | acm_ctrl &= (~AcmHw_BeqEn); | |
350 | break; | |
351 | default: | |
352 | RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG, | |
353 | "switch case not processed\n"); | |
354 | break; | |
355 | } | |
356 | } | |
357 | ||
358 | RT_TRACE(rtlpriv, COMP_QOS, DBG_TRACE, | |
359 | "SetHwReg8190pci(): [HW_VAR_ACM_CTRL] Write 0x%X\n", | |
360 | acm_ctrl); | |
361 | rtl_write_byte(rtlpriv, REG_ACMHWCTRL, acm_ctrl); | |
362 | break; } | |
363 | case HW_VAR_RCR: | |
364 | rtl_write_dword(rtlpriv, REG_RCR, ((u32 *) (val))[0]); | |
365 | rtlpci->receive_config = ((u32 *) (val))[0]; | |
366 | break; | |
367 | case HW_VAR_RETRY_LIMIT:{ | |
368 | u8 retry_limit = ((u8 *) (val))[0]; | |
369 | ||
370 | rtl_write_word(rtlpriv, REG_RL, | |
371 | retry_limit << RETRY_LIMIT_SHORT_SHIFT | | |
372 | retry_limit << RETRY_LIMIT_LONG_SHIFT); | |
373 | break; } | |
374 | case HW_VAR_DUAL_TSF_RST: | |
375 | rtl_write_byte(rtlpriv, REG_DUAL_TSF_RST, (BIT(0) | BIT(1))); | |
376 | break; | |
377 | case HW_VAR_EFUSE_BYTES: | |
378 | rtlefuse->efuse_usedbytes = *((u16 *) val); | |
379 | break; | |
380 | case HW_VAR_EFUSE_USAGE: | |
381 | rtlefuse->efuse_usedpercentage = *((u8 *) val); | |
382 | break; | |
383 | case HW_VAR_IO_CMD: | |
384 | rtl8723ae_phy_set_io_cmd(hw, (*(enum io_type *)val)); | |
385 | break; | |
386 | case HW_VAR_WPA_CONFIG: | |
387 | rtl_write_byte(rtlpriv, REG_SECCFG, *((u8 *) val)); | |
388 | break; | |
389 | case HW_VAR_SET_RPWM:{ | |
390 | u8 rpwm_val; | |
391 | ||
392 | rpwm_val = rtl_read_byte(rtlpriv, REG_PCIE_HRPWM); | |
393 | udelay(1); | |
394 | ||
395 | if (rpwm_val & BIT(7)) { | |
396 | rtl_write_byte(rtlpriv, REG_PCIE_HRPWM, | |
397 | (*(u8 *) val)); | |
398 | } else { | |
399 | rtl_write_byte(rtlpriv, REG_PCIE_HRPWM, | |
400 | ((*(u8 *) val) | BIT(7))); | |
401 | } | |
402 | ||
403 | break; } | |
404 | case HW_VAR_H2C_FW_PWRMODE:{ | |
405 | u8 psmode = (*(u8 *) val); | |
406 | ||
407 | if (psmode != FW_PS_ACTIVE_MODE) | |
408 | rtl8723ae_dm_rf_saving(hw, true); | |
409 | ||
410 | rtl8723ae_set_fw_pwrmode_cmd(hw, (*(u8 *) val)); | |
411 | break; } | |
412 | case HW_VAR_FW_PSMODE_STATUS: | |
413 | ppsc->fw_current_inpsmode = *((bool *) val); | |
414 | break; | |
415 | case HW_VAR_H2C_FW_JOINBSSRPT:{ | |
416 | u8 mstatus = (*(u8 *) val); | |
417 | u8 tmp_regcr, tmp_reg422; | |
418 | bool recover = false; | |
419 | ||
420 | if (mstatus == RT_MEDIA_CONNECT) { | |
421 | rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_AID, NULL); | |
422 | ||
423 | tmp_regcr = rtl_read_byte(rtlpriv, REG_CR + 1); | |
424 | rtl_write_byte(rtlpriv, REG_CR + 1, | |
425 | (tmp_regcr | BIT(0))); | |
426 | ||
427 | _rtl8723ae_set_bcn_ctrl_reg(hw, 0, BIT(3)); | |
428 | _rtl8723ae_set_bcn_ctrl_reg(hw, BIT(4), 0); | |
429 | ||
430 | tmp_reg422 = rtl_read_byte(rtlpriv, | |
431 | REG_FWHW_TXQ_CTRL + 2); | |
432 | if (tmp_reg422 & BIT(6)) | |
433 | recover = true; | |
434 | rtl_write_byte(rtlpriv, REG_FWHW_TXQ_CTRL + 2, | |
435 | tmp_reg422 & (~BIT(6))); | |
436 | ||
437 | rtl8723ae_set_fw_rsvdpagepkt(hw, 0); | |
438 | ||
439 | _rtl8723ae_set_bcn_ctrl_reg(hw, BIT(3), 0); | |
440 | _rtl8723ae_set_bcn_ctrl_reg(hw, 0, BIT(4)); | |
441 | ||
442 | if (recover) | |
443 | rtl_write_byte(rtlpriv, REG_FWHW_TXQ_CTRL + 2, | |
444 | tmp_reg422); | |
445 | ||
446 | rtl_write_byte(rtlpriv, REG_CR + 1, | |
447 | (tmp_regcr & ~(BIT(0)))); | |
448 | } | |
449 | rtl8723ae_set_fw_joinbss_report_cmd(hw, (*(u8 *) val)); | |
450 | ||
451 | break; } | |
4b04edc1 LF |
452 | case HW_VAR_H2C_FW_P2P_PS_OFFLOAD: |
453 | rtl8723ae_set_p2p_ps_offload_cmd(hw, (*(u8 *)val)); | |
454 | break; | |
c592e631 LF |
455 | case HW_VAR_AID:{ |
456 | u16 u2btmp; | |
457 | u2btmp = rtl_read_word(rtlpriv, REG_BCN_PSR_RPT); | |
458 | u2btmp &= 0xC000; | |
459 | rtl_write_word(rtlpriv, REG_BCN_PSR_RPT, (u2btmp | | |
460 | mac->assoc_id)); | |
461 | break; } | |
462 | case HW_VAR_CORRECT_TSF:{ | |
463 | u8 btype_ibss = ((u8 *) (val))[0]; | |
464 | ||
465 | if (btype_ibss == true) | |
466 | _rtl8723ae_stop_tx_beacon(hw); | |
467 | ||
468 | _rtl8723ae_set_bcn_ctrl_reg(hw, 0, BIT(3)); | |
469 | ||
470 | rtl_write_dword(rtlpriv, REG_TSFTR, | |
471 | (u32) (mac->tsf & 0xffffffff)); | |
472 | rtl_write_dword(rtlpriv, REG_TSFTR + 4, | |
473 | (u32) ((mac->tsf >> 32) & 0xffffffff)); | |
474 | ||
475 | _rtl8723ae_set_bcn_ctrl_reg(hw, BIT(3), 0); | |
476 | ||
477 | if (btype_ibss == true) | |
478 | _rtl8723ae_resume_tx_beacon(hw); | |
479 | break; } | |
4b04edc1 LF |
480 | case HW_VAR_FW_LPS_ACTION: { |
481 | bool enter_fwlps = *((bool *)val); | |
482 | u8 rpwm_val, fw_pwrmode; | |
483 | bool fw_current_inps; | |
484 | ||
485 | if (enter_fwlps) { | |
486 | rpwm_val = 0x02; /* RF off */ | |
487 | fw_current_inps = true; | |
488 | rtlpriv->cfg->ops->set_hw_reg(hw, | |
489 | HW_VAR_FW_PSMODE_STATUS, | |
490 | (u8 *)(&fw_current_inps)); | |
491 | rtlpriv->cfg->ops->set_hw_reg(hw, | |
492 | HW_VAR_H2C_FW_PWRMODE, | |
493 | (u8 *)(&ppsc->fwctrl_psmode)); | |
494 | ||
495 | rtlpriv->cfg->ops->set_hw_reg(hw, | |
496 | HW_VAR_SET_RPWM, | |
497 | (u8 *)(&rpwm_val)); | |
498 | } else { | |
499 | rpwm_val = 0x0C; /* RF on */ | |
500 | fw_pwrmode = FW_PS_ACTIVE_MODE; | |
501 | fw_current_inps = false; | |
502 | rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_SET_RPWM, | |
503 | (u8 *)(&rpwm_val)); | |
504 | rtlpriv->cfg->ops->set_hw_reg(hw, | |
505 | HW_VAR_H2C_FW_PWRMODE, | |
506 | (u8 *)(&fw_pwrmode)); | |
507 | ||
508 | rtlpriv->cfg->ops->set_hw_reg(hw, | |
509 | HW_VAR_FW_PSMODE_STATUS, | |
510 | (u8 *)(&fw_current_inps)); | |
511 | } | |
512 | break; } | |
c592e631 LF |
513 | default: |
514 | RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG, | |
515 | "switch case not processed\n"); | |
516 | break; | |
517 | } | |
518 | } | |
519 | ||
520 | static bool _rtl8723ae_llt_write(struct ieee80211_hw *hw, u32 address, u32 data) | |
521 | { | |
522 | struct rtl_priv *rtlpriv = rtl_priv(hw); | |
523 | bool status = true; | |
524 | long count = 0; | |
525 | u32 value = _LLT_INIT_ADDR(address) | | |
526 | _LLT_INIT_DATA(data) | _LLT_OP(_LLT_WRITE_ACCESS); | |
527 | ||
528 | rtl_write_dword(rtlpriv, REG_LLT_INIT, value); | |
529 | ||
530 | do { | |
531 | value = rtl_read_dword(rtlpriv, REG_LLT_INIT); | |
532 | if (_LLT_NO_ACTIVE == _LLT_OP_VALUE(value)) | |
533 | break; | |
534 | ||
535 | if (count > POLLING_LLT_THRESHOLD) { | |
536 | RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG, | |
537 | "Failed to polling write LLT done at address %d!\n", | |
538 | address); | |
539 | status = false; | |
540 | break; | |
541 | } | |
542 | } while (++count); | |
543 | ||
544 | return status; | |
545 | } | |
546 | ||
547 | static bool _rtl8723ae_llt_table_init(struct ieee80211_hw *hw) | |
548 | { | |
549 | struct rtl_priv *rtlpriv = rtl_priv(hw); | |
550 | unsigned short i; | |
551 | u8 txpktbuf_bndy; | |
552 | u8 maxPage; | |
553 | bool status; | |
554 | u8 ubyte; | |
555 | ||
556 | maxPage = 255; | |
557 | txpktbuf_bndy = 246; | |
558 | ||
559 | rtl_write_byte(rtlpriv, REG_CR, 0x8B); | |
560 | ||
561 | rtl_write_word(rtlpriv, REG_RQPN_NPQ, 0x0000); | |
562 | ||
563 | rtl_write_dword(rtlpriv, REG_RQPN, 0x80ac1c29); | |
564 | rtl_write_byte(rtlpriv, REG_RQPN_NPQ, 0x03); | |
565 | ||
566 | rtl_write_dword(rtlpriv, REG_TRXFF_BNDY, (0x27FF0000 | txpktbuf_bndy)); | |
567 | rtl_write_byte(rtlpriv, REG_TDECTRL + 1, txpktbuf_bndy); | |
568 | ||
569 | rtl_write_byte(rtlpriv, REG_TXPKTBUF_BCNQ_BDNY, txpktbuf_bndy); | |
570 | rtl_write_byte(rtlpriv, REG_TXPKTBUF_MGQ_BDNY, txpktbuf_bndy); | |
571 | ||
572 | rtl_write_byte(rtlpriv, 0x45D, txpktbuf_bndy); | |
573 | rtl_write_byte(rtlpriv, REG_PBP, 0x11); | |
574 | rtl_write_byte(rtlpriv, REG_RX_DRVINFO_SZ, 0x4); | |
575 | ||
576 | for (i = 0; i < (txpktbuf_bndy - 1); i++) { | |
577 | status = _rtl8723ae_llt_write(hw, i, i + 1); | |
578 | if (true != status) | |
579 | return status; | |
580 | } | |
581 | ||
582 | status = _rtl8723ae_llt_write(hw, (txpktbuf_bndy - 1), 0xFF); | |
583 | if (true != status) | |
584 | return status; | |
585 | ||
586 | for (i = txpktbuf_bndy; i < maxPage; i++) { | |
587 | status = _rtl8723ae_llt_write(hw, i, (i + 1)); | |
588 | if (true != status) | |
589 | return status; | |
590 | } | |
591 | ||
592 | status = _rtl8723ae_llt_write(hw, maxPage, txpktbuf_bndy); | |
593 | if (true != status) | |
594 | return status; | |
595 | ||
596 | rtl_write_byte(rtlpriv, REG_CR, 0xff); | |
597 | ubyte = rtl_read_byte(rtlpriv, REG_RQPN + 3); | |
598 | rtl_write_byte(rtlpriv, REG_RQPN + 3, ubyte | BIT(7)); | |
599 | ||
600 | return true; | |
601 | } | |
602 | ||
603 | static void _rtl8723ae_gen_refresh_led_state(struct ieee80211_hw *hw) | |
604 | { | |
605 | struct rtl_priv *rtlpriv = rtl_priv(hw); | |
606 | struct rtl_pci_priv *pcipriv = rtl_pcipriv(hw); | |
607 | struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw)); | |
608 | struct rtl_led *pLed0 = &(pcipriv->ledctl.sw_led0); | |
609 | ||
610 | if (rtlpriv->rtlhal.up_first_time) | |
611 | return; | |
612 | ||
613 | if (ppsc->rfoff_reason == RF_CHANGE_BY_IPS) | |
614 | rtl8723ae_sw_led_on(hw, pLed0); | |
615 | else if (ppsc->rfoff_reason == RF_CHANGE_BY_INIT) | |
616 | rtl8723ae_sw_led_on(hw, pLed0); | |
617 | else | |
618 | rtl8723ae_sw_led_off(hw, pLed0); | |
619 | } | |
620 | ||
621 | static bool _rtl8712e_init_mac(struct ieee80211_hw *hw) | |
622 | { | |
623 | struct rtl_priv *rtlpriv = rtl_priv(hw); | |
624 | struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw)); | |
625 | unsigned char bytetmp; | |
626 | unsigned short wordtmp; | |
627 | u16 retry = 0; | |
628 | u16 tmpu2b; | |
629 | bool mac_func_enable; | |
630 | ||
631 | rtl_write_byte(rtlpriv, REG_RSV_CTRL, 0x00); | |
632 | bytetmp = rtl_read_byte(rtlpriv, REG_CR); | |
633 | if (bytetmp == 0xFF) | |
634 | mac_func_enable = true; | |
635 | else | |
636 | mac_func_enable = false; | |
637 | ||
638 | ||
639 | /* HW Power on sequence */ | |
640 | if (!rtl_hal_pwrseqcmdparsing(rtlpriv, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, | |
641 | PWR_INTF_PCI_MSK, Rtl8723_NIC_ENABLE_FLOW)) | |
642 | return false; | |
643 | ||
644 | bytetmp = rtl_read_byte(rtlpriv, REG_PCIE_CTRL_REG+2); | |
645 | rtl_write_byte(rtlpriv, REG_PCIE_CTRL_REG+2, bytetmp | BIT(4)); | |
646 | ||
647 | /* eMAC time out function enable, 0x369[7]=1 */ | |
648 | bytetmp = rtl_read_byte(rtlpriv, 0x369); | |
649 | rtl_write_byte(rtlpriv, 0x369, bytetmp | BIT(7)); | |
650 | ||
651 | /* ePHY reg 0x1e bit[4]=1 using MDIO interface, | |
652 | * we should do this before Enabling ASPM backdoor. | |
653 | */ | |
654 | do { | |
655 | rtl_write_word(rtlpriv, 0x358, 0x5e); | |
656 | udelay(100); | |
657 | rtl_write_word(rtlpriv, 0x356, 0xc280); | |
658 | rtl_write_word(rtlpriv, 0x354, 0xc290); | |
659 | rtl_write_word(rtlpriv, 0x358, 0x3e); | |
660 | udelay(100); | |
661 | rtl_write_word(rtlpriv, 0x358, 0x5e); | |
662 | udelay(100); | |
663 | tmpu2b = rtl_read_word(rtlpriv, 0x356); | |
664 | retry++; | |
665 | } while (tmpu2b != 0xc290 && retry < 100); | |
666 | ||
667 | if (retry >= 100) { | |
668 | RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, | |
669 | "InitMAC(): ePHY configure fail!!!\n"); | |
670 | return false; | |
671 | } | |
672 | ||
673 | rtl_write_word(rtlpriv, REG_CR, 0x2ff); | |
674 | rtl_write_word(rtlpriv, REG_CR + 1, 0x06); | |
675 | ||
676 | if (!mac_func_enable) { | |
677 | if (_rtl8723ae_llt_table_init(hw) == false) | |
678 | return false; | |
679 | } | |
680 | ||
681 | rtl_write_dword(rtlpriv, REG_HISR, 0xffffffff); | |
682 | rtl_write_byte(rtlpriv, REG_HISRE, 0xff); | |
683 | ||
684 | rtl_write_word(rtlpriv, REG_TRXFF_BNDY + 2, 0x27ff); | |
685 | ||
686 | wordtmp = rtl_read_word(rtlpriv, REG_TRXDMA_CTRL) & 0xf; | |
687 | wordtmp |= 0xF771; | |
688 | rtl_write_word(rtlpriv, REG_TRXDMA_CTRL, wordtmp); | |
689 | ||
690 | rtl_write_byte(rtlpriv, REG_FWHW_TXQ_CTRL + 1, 0x1F); | |
691 | rtl_write_dword(rtlpriv, REG_RCR, rtlpci->receive_config); | |
692 | rtl_write_word(rtlpriv, REG_RXFLTMAP2, 0xFFFF); | |
693 | rtl_write_dword(rtlpriv, REG_TCR, rtlpci->transmit_config); | |
694 | ||
695 | rtl_write_byte(rtlpriv, 0x4d0, 0x0); | |
696 | ||
697 | rtl_write_dword(rtlpriv, REG_BCNQ_DESA, | |
698 | ((u64) rtlpci->tx_ring[BEACON_QUEUE].dma) & | |
699 | DMA_BIT_MASK(32)); | |
700 | rtl_write_dword(rtlpriv, REG_MGQ_DESA, | |
701 | (u64) rtlpci->tx_ring[MGNT_QUEUE].dma & | |
702 | DMA_BIT_MASK(32)); | |
703 | rtl_write_dword(rtlpriv, REG_VOQ_DESA, | |
704 | (u64) rtlpci->tx_ring[VO_QUEUE].dma & DMA_BIT_MASK(32)); | |
705 | rtl_write_dword(rtlpriv, REG_VIQ_DESA, | |
706 | (u64) rtlpci->tx_ring[VI_QUEUE].dma & DMA_BIT_MASK(32)); | |
707 | rtl_write_dword(rtlpriv, REG_BEQ_DESA, | |
708 | (u64) rtlpci->tx_ring[BE_QUEUE].dma & DMA_BIT_MASK(32)); | |
709 | rtl_write_dword(rtlpriv, REG_BKQ_DESA, | |
710 | (u64) rtlpci->tx_ring[BK_QUEUE].dma & DMA_BIT_MASK(32)); | |
711 | rtl_write_dword(rtlpriv, REG_HQ_DESA, | |
712 | (u64) rtlpci->tx_ring[HIGH_QUEUE].dma & | |
713 | DMA_BIT_MASK(32)); | |
714 | rtl_write_dword(rtlpriv, REG_RX_DESA, | |
715 | (u64) rtlpci->rx_ring[RX_MPDU_QUEUE].dma & | |
716 | DMA_BIT_MASK(32)); | |
717 | ||
718 | rtl_write_byte(rtlpriv, REG_PCIE_CTRL_REG + 3, 0x74); | |
719 | ||
720 | rtl_write_dword(rtlpriv, REG_INT_MIG, 0); | |
721 | ||
722 | bytetmp = rtl_read_byte(rtlpriv, REG_APSD_CTRL); | |
723 | rtl_write_byte(rtlpriv, REG_APSD_CTRL, bytetmp & ~BIT(6)); | |
724 | do { | |
725 | retry++; | |
726 | bytetmp = rtl_read_byte(rtlpriv, REG_APSD_CTRL); | |
727 | } while ((retry < 200) && (bytetmp & BIT(7))); | |
728 | ||
729 | _rtl8723ae_gen_refresh_led_state(hw); | |
730 | ||
731 | rtl_write_dword(rtlpriv, REG_MCUTST_1, 0x0); | |
732 | ||
733 | return true; | |
734 | } | |
735 | ||
736 | static void _rtl8723ae_hw_configure(struct ieee80211_hw *hw) | |
737 | { | |
738 | struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw)); | |
739 | struct rtl_priv *rtlpriv = rtl_priv(hw); | |
740 | struct rtl_pci_priv *pcipriv = rtl_pcipriv(hw); | |
741 | u8 reg_bw_opmode; | |
b26f5f09 | 742 | u32 reg_prsr; |
c592e631 LF |
743 | |
744 | reg_bw_opmode = BW_OPMODE_20MHZ; | |
c592e631 LF |
745 | reg_prsr = RATE_ALL_CCK | RATE_ALL_OFDM_AG; |
746 | ||
747 | rtl_write_byte(rtlpriv, REG_INIRTS_RATE_SEL, 0x8); | |
748 | ||
749 | rtl_write_byte(rtlpriv, REG_BWOPMODE, reg_bw_opmode); | |
750 | ||
751 | rtl_write_dword(rtlpriv, REG_RRSR, reg_prsr); | |
752 | ||
753 | rtl_write_byte(rtlpriv, REG_SLOT, 0x09); | |
754 | ||
755 | rtl_write_byte(rtlpriv, REG_AMPDU_MIN_SPACE, 0x0); | |
756 | ||
757 | rtl_write_word(rtlpriv, REG_FWHW_TXQ_CTRL, 0x1F80); | |
758 | ||
759 | rtl_write_word(rtlpriv, REG_RL, 0x0707); | |
760 | ||
761 | rtl_write_dword(rtlpriv, REG_BAR_MODE_CTRL, 0x02012802); | |
762 | ||
763 | rtl_write_byte(rtlpriv, REG_HWSEQ_CTRL, 0xFF); | |
764 | ||
765 | rtl_write_dword(rtlpriv, REG_DARFRC, 0x01000000); | |
766 | rtl_write_dword(rtlpriv, REG_DARFRC + 4, 0x07060504); | |
767 | rtl_write_dword(rtlpriv, REG_RARFRC, 0x01000000); | |
768 | rtl_write_dword(rtlpriv, REG_RARFRC + 4, 0x07060504); | |
769 | ||
770 | if ((pcipriv->bt_coexist.bt_coexistence) && | |
771 | (pcipriv->bt_coexist.bt_coexist_type == BT_CSR_BC4)) | |
772 | rtl_write_dword(rtlpriv, REG_AGGLEN_LMT, 0x97427431); | |
773 | else | |
774 | rtl_write_dword(rtlpriv, REG_AGGLEN_LMT, 0xb972a841); | |
775 | ||
776 | rtl_write_byte(rtlpriv, REG_ATIMWND, 0x2); | |
777 | ||
778 | rtl_write_byte(rtlpriv, REG_BCN_MAX_ERR, 0xff); | |
779 | ||
780 | rtlpci->reg_bcn_ctrl_val = 0x1f; | |
781 | rtl_write_byte(rtlpriv, REG_BCN_CTRL, rtlpci->reg_bcn_ctrl_val); | |
782 | ||
783 | rtl_write_byte(rtlpriv, REG_TBTT_PROHIBIT + 1, 0xff); | |
784 | ||
785 | rtl_write_byte(rtlpriv, REG_TBTT_PROHIBIT + 1, 0xff); | |
786 | ||
787 | rtl_write_byte(rtlpriv, REG_PIFS, 0x1C); | |
788 | rtl_write_byte(rtlpriv, REG_AGGR_BREAK_TIME, 0x16); | |
789 | ||
790 | if ((pcipriv->bt_coexist.bt_coexistence) && | |
791 | (pcipriv->bt_coexist.bt_coexist_type == BT_CSR_BC4)) { | |
792 | rtl_write_word(rtlpriv, REG_NAV_PROT_LEN, 0x0020); | |
793 | rtl_write_word(rtlpriv, REG_PROT_MODE_CTRL, 0x0402); | |
794 | } else { | |
795 | rtl_write_word(rtlpriv, REG_NAV_PROT_LEN, 0x0020); | |
796 | rtl_write_word(rtlpriv, REG_NAV_PROT_LEN, 0x0020); | |
797 | } | |
798 | ||
799 | if ((pcipriv->bt_coexist.bt_coexistence) && | |
800 | (pcipriv->bt_coexist.bt_coexist_type == BT_CSR_BC4)) | |
801 | rtl_write_dword(rtlpriv, REG_FAST_EDCA_CTRL, 0x03086666); | |
802 | else | |
803 | rtl_write_dword(rtlpriv, REG_FAST_EDCA_CTRL, 0x086666); | |
804 | ||
805 | rtl_write_byte(rtlpriv, REG_ACKTO, 0x40); | |
806 | ||
807 | rtl_write_word(rtlpriv, REG_SPEC_SIFS, 0x1010); | |
808 | rtl_write_word(rtlpriv, REG_MAC_SPEC_SIFS, 0x1010); | |
809 | ||
810 | rtl_write_word(rtlpriv, REG_SIFS_CTX, 0x1010); | |
811 | ||
812 | rtl_write_word(rtlpriv, REG_SIFS_TRX, 0x1010); | |
813 | ||
814 | rtl_write_dword(rtlpriv, REG_MAR, 0xffffffff); | |
815 | rtl_write_dword(rtlpriv, REG_MAR + 4, 0xffffffff); | |
816 | ||
817 | rtl_write_dword(rtlpriv, 0x394, 0x1); | |
818 | } | |
819 | ||
820 | static void _rtl8723ae_enable_aspm_back_door(struct ieee80211_hw *hw) | |
821 | { | |
822 | struct rtl_priv *rtlpriv = rtl_priv(hw); | |
823 | struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw)); | |
824 | ||
825 | rtl_write_byte(rtlpriv, 0x34b, 0x93); | |
826 | rtl_write_word(rtlpriv, 0x350, 0x870c); | |
827 | rtl_write_byte(rtlpriv, 0x352, 0x1); | |
828 | ||
829 | if (ppsc->support_backdoor) | |
830 | rtl_write_byte(rtlpriv, 0x349, 0x1b); | |
831 | else | |
832 | rtl_write_byte(rtlpriv, 0x349, 0x03); | |
833 | ||
834 | rtl_write_word(rtlpriv, 0x350, 0x2718); | |
835 | rtl_write_byte(rtlpriv, 0x352, 0x1); | |
836 | } | |
837 | ||
838 | void rtl8723ae_enable_hw_security_config(struct ieee80211_hw *hw) | |
839 | { | |
840 | struct rtl_priv *rtlpriv = rtl_priv(hw); | |
841 | u8 sec_reg_value; | |
842 | ||
843 | RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG, | |
844 | "PairwiseEncAlgorithm = %d GroupEncAlgorithm = %d\n", | |
845 | rtlpriv->sec.pairwise_enc_algorithm, | |
846 | rtlpriv->sec.group_enc_algorithm); | |
847 | ||
848 | if (rtlpriv->cfg->mod_params->sw_crypto || rtlpriv->sec.use_sw_sec) { | |
849 | RT_TRACE(rtlpriv, COMP_SEC, DBG_DMESG, | |
850 | "not open hw encryption\n"); | |
851 | return; | |
852 | } | |
853 | ||
854 | sec_reg_value = SCR_TxEncEnable | SCR_RxDecEnable; | |
855 | ||
856 | if (rtlpriv->sec.use_defaultkey) { | |
857 | sec_reg_value |= SCR_TxUseDK; | |
858 | sec_reg_value |= SCR_RxUseDK; | |
859 | } | |
860 | ||
861 | sec_reg_value |= (SCR_RXBCUSEDK | SCR_TXBCUSEDK); | |
862 | ||
863 | rtl_write_byte(rtlpriv, REG_CR + 1, 0x02); | |
864 | ||
865 | RT_TRACE(rtlpriv, COMP_SEC, DBG_DMESG, | |
866 | "The SECR-value %x\n", sec_reg_value); | |
867 | ||
868 | rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_WPA_CONFIG, &sec_reg_value); | |
869 | ||
870 | } | |
871 | ||
872 | int rtl8723ae_hw_init(struct ieee80211_hw *hw) | |
873 | { | |
874 | struct rtl_priv *rtlpriv = rtl_priv(hw); | |
875 | struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw)); | |
876 | struct rtl_mac *mac = rtl_mac(rtl_priv(hw)); | |
877 | struct rtl_phy *rtlphy = &(rtlpriv->phy); | |
878 | struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw)); | |
879 | struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw)); | |
880 | bool rtstatus = true; | |
881 | int err; | |
882 | u8 tmp_u1b; | |
883 | ||
884 | rtlpriv->rtlhal.being_init_adapter = true; | |
885 | rtlpriv->intf_ops->disable_aspm(hw); | |
886 | rtstatus = _rtl8712e_init_mac(hw); | |
887 | if (rtstatus != true) { | |
888 | RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG, "Init MAC failed\n"); | |
889 | err = 1; | |
890 | return err; | |
891 | } | |
892 | ||
893 | err = rtl8723ae_download_fw(hw); | |
894 | if (err) { | |
895 | RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING, | |
896 | "Failed to download FW. Init HW without FW now..\n"); | |
897 | err = 1; | |
898 | rtlhal->fw_ready = false; | |
899 | return err; | |
900 | } else { | |
901 | rtlhal->fw_ready = true; | |
902 | } | |
903 | ||
904 | rtlhal->last_hmeboxnum = 0; | |
905 | rtl8723ae_phy_mac_config(hw); | |
906 | /* because the last function modifies RCR, we update | |
907 | * rcr var here, or TP will be unstable as ther receive_config | |
908 | * is wrong, RX RCR_ACRC32 will cause TP unstable & Rx | |
909 | * RCR_APP_ICV will cause mac80211 unassoc for cisco 1252 | |
910 | */ | |
911 | rtlpci->receive_config = rtl_read_dword(rtlpriv, REG_RCR); | |
912 | rtlpci->receive_config &= ~(RCR_ACRC32 | RCR_AICV); | |
913 | rtl_write_dword(rtlpriv, REG_RCR, rtlpci->receive_config); | |
914 | ||
915 | rtl8723ae_phy_bb_config(hw); | |
916 | rtlphy->rf_mode = RF_OP_BY_SW_3WIRE; | |
917 | rtl8723ae_phy_rf_config(hw); | |
918 | if (IS_VENDOR_UMC_A_CUT(rtlhal->version)) { | |
919 | rtl_set_rfreg(hw, RF90_PATH_A, RF_RX_G1, MASKDWORD, 0x30255); | |
920 | rtl_set_rfreg(hw, RF90_PATH_A, RF_RX_G2, MASKDWORD, 0x50a00); | |
921 | } else if (IS_81xxC_VENDOR_UMC_B_CUT(rtlhal->version)) { | |
922 | rtl_set_rfreg(hw, RF90_PATH_A, 0x0C, MASKDWORD, 0x894AE); | |
923 | rtl_set_rfreg(hw, RF90_PATH_A, 0x0A, MASKDWORD, 0x1AF31); | |
924 | rtl_set_rfreg(hw, RF90_PATH_A, RF_IPA, MASKDWORD, 0x8F425); | |
925 | rtl_set_rfreg(hw, RF90_PATH_A, RF_SYN_G2, MASKDWORD, 0x4F200); | |
926 | rtl_set_rfreg(hw, RF90_PATH_A, RF_RCK1, MASKDWORD, 0x44053); | |
927 | rtl_set_rfreg(hw, RF90_PATH_A, RF_RCK2, MASKDWORD, 0x80201); | |
928 | } | |
929 | rtlphy->rfreg_chnlval[0] = rtl_get_rfreg(hw, (enum radio_path)0, | |
930 | RF_CHNLBW, RFREG_OFFSET_MASK); | |
931 | rtlphy->rfreg_chnlval[1] = rtl_get_rfreg(hw, (enum radio_path)1, | |
932 | RF_CHNLBW, RFREG_OFFSET_MASK); | |
933 | rtl_set_bbreg(hw, RFPGA0_RFMOD, BCCKEN, 0x1); | |
934 | rtl_set_bbreg(hw, RFPGA0_RFMOD, BOFDMEN, 0x1); | |
935 | rtl_set_bbreg(hw, RFPGA0_ANALOGPARAMETER2, BIT(10), 1); | |
936 | _rtl8723ae_hw_configure(hw); | |
937 | rtl_cam_reset_all_entry(hw); | |
938 | rtl8723ae_enable_hw_security_config(hw); | |
939 | ||
940 | ppsc->rfpwr_state = ERFON; | |
941 | ||
942 | rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_ETHER_ADDR, mac->mac_addr); | |
943 | _rtl8723ae_enable_aspm_back_door(hw); | |
944 | rtlpriv->intf_ops->enable_aspm(hw); | |
945 | ||
946 | rtl8723ae_bt_hw_init(hw); | |
947 | ||
948 | if (ppsc->rfpwr_state == ERFON) { | |
949 | rtl8723ae_phy_set_rfpath_switch(hw, 1); | |
950 | if (rtlphy->iqk_initialized) { | |
951 | rtl8723ae_phy_iq_calibrate(hw, true); | |
952 | } else { | |
953 | rtl8723ae_phy_iq_calibrate(hw, false); | |
954 | rtlphy->iqk_initialized = true; | |
955 | } | |
956 | ||
957 | rtl8723ae_phy_lc_calibrate(hw); | |
958 | } | |
959 | ||
960 | tmp_u1b = efuse_read_1byte(hw, 0x1FA); | |
961 | if (!(tmp_u1b & BIT(0))) { | |
962 | rtl_set_rfreg(hw, RF90_PATH_A, 0x15, 0x0F, 0x05); | |
963 | RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE, "PA BIAS path A\n"); | |
964 | } | |
965 | ||
966 | if (!(tmp_u1b & BIT(4))) { | |
967 | tmp_u1b = rtl_read_byte(rtlpriv, 0x16) & 0x0F; | |
968 | rtl_write_byte(rtlpriv, 0x16, tmp_u1b | 0x80); | |
969 | udelay(10); | |
970 | rtl_write_byte(rtlpriv, 0x16, tmp_u1b | 0x90); | |
971 | RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE, "under 1.5V\n"); | |
972 | } | |
973 | rtl8723ae_dm_init(hw); | |
974 | rtlpriv->rtlhal.being_init_adapter = false; | |
975 | return err; | |
976 | } | |
977 | ||
978 | static enum version_8723e _rtl8723ae_read_chip_version(struct ieee80211_hw *hw) | |
979 | { | |
980 | struct rtl_priv *rtlpriv = rtl_priv(hw); | |
981 | struct rtl_phy *rtlphy = &(rtlpriv->phy); | |
982 | enum version_8723e version = 0x0000; | |
983 | u32 value32; | |
984 | ||
985 | value32 = rtl_read_dword(rtlpriv, REG_SYS_CFG); | |
986 | if (value32 & TRP_VAUX_EN) { | |
987 | version = (enum version_8723e)(version | | |
988 | ((value32 & VENDOR_ID) ? CHIP_VENDOR_UMC : 0)); | |
989 | /* RTL8723 with BT function. */ | |
990 | version = (enum version_8723e)(version | | |
991 | ((value32 & BT_FUNC) ? CHIP_8723 : 0)); | |
992 | ||
993 | } else { | |
994 | /* Normal mass production chip. */ | |
995 | version = (enum version_8723e) NORMAL_CHIP; | |
996 | version = (enum version_8723e)(version | | |
997 | ((value32 & VENDOR_ID) ? CHIP_VENDOR_UMC : 0)); | |
998 | /* RTL8723 with BT function. */ | |
999 | version = (enum version_8723e)(version | | |
1000 | ((value32 & BT_FUNC) ? CHIP_8723 : 0)); | |
1001 | if (IS_CHIP_VENDOR_UMC(version)) | |
1002 | version = (enum version_8723e)(version | | |
1003 | ((value32 & CHIP_VER_RTL_MASK)));/* IC version (CUT) */ | |
1004 | if (IS_8723_SERIES(version)) { | |
1005 | value32 = rtl_read_dword(rtlpriv, REG_GPIO_OUTSTS); | |
1006 | /* ROM code version */ | |
1007 | version = (enum version_8723e)(version | | |
1008 | ((value32 & RF_RL_ID)>>20)); | |
1009 | } | |
1010 | } | |
1011 | ||
1012 | if (IS_8723_SERIES(version)) { | |
1013 | value32 = rtl_read_dword(rtlpriv, REG_MULTI_FUNC_CTRL); | |
1014 | rtlphy->polarity_ctl = ((value32 & WL_HWPDN_SL) ? | |
1015 | RT_POLARITY_HIGH_ACT : | |
1016 | RT_POLARITY_LOW_ACT); | |
1017 | } | |
1018 | switch (version) { | |
1019 | case VERSION_TEST_UMC_CHIP_8723: | |
1020 | RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE, | |
1021 | "Chip Version ID: VERSION_TEST_UMC_CHIP_8723.\n"); | |
1022 | break; | |
1023 | case VERSION_NORMAL_UMC_CHIP_8723_1T1R_A_CUT: | |
1024 | RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE, | |
1025 | "Chip Version ID: VERSION_NORMAL_UMC_CHIP_8723_1T1R_A_CUT.\n"); | |
1026 | break; | |
1027 | case VERSION_NORMAL_UMC_CHIP_8723_1T1R_B_CUT: | |
1028 | RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE, | |
1029 | "Chip Version ID: VERSION_NORMAL_UMC_CHIP_8723_1T1R_B_CUT.\n"); | |
1030 | break; | |
1031 | default: | |
1032 | RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG, | |
1033 | "Chip Version ID: Unknown. Bug?\n"); | |
1034 | break; | |
1035 | } | |
1036 | ||
1037 | if (IS_8723_SERIES(version)) | |
1038 | rtlphy->rf_type = RF_1T1R; | |
1039 | ||
1040 | RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, "Chip RF Type: %s\n", | |
1041 | (rtlphy->rf_type == RF_2T2R) ? "RF_2T2R" : "RF_1T1R"); | |
1042 | ||
1043 | return version; | |
1044 | } | |
1045 | ||
1046 | static int _rtl8723ae_set_media_status(struct ieee80211_hw *hw, | |
1047 | enum nl80211_iftype type) | |
1048 | { | |
1049 | struct rtl_priv *rtlpriv = rtl_priv(hw); | |
1050 | u8 bt_msr = rtl_read_byte(rtlpriv, MSR) & 0xfc; | |
1051 | enum led_ctl_mode ledaction = LED_CTL_NO_LINK; | |
1052 | ||
1053 | rtl_write_dword(rtlpriv, REG_BCN_CTRL, 0); | |
1054 | RT_TRACE(rtlpriv, COMP_BEACON, DBG_LOUD, | |
1055 | "clear 0x550 when set HW_VAR_MEDIA_STATUS\n"); | |
1056 | ||
1057 | if (type == NL80211_IFTYPE_UNSPECIFIED || | |
1058 | type == NL80211_IFTYPE_STATION) { | |
1059 | _rtl8723ae_stop_tx_beacon(hw); | |
1060 | _rtl8723ae_enable_bcn_sufunc(hw); | |
1061 | } else if (type == NL80211_IFTYPE_ADHOC || | |
1062 | type == NL80211_IFTYPE_AP) { | |
1063 | _rtl8723ae_resume_tx_beacon(hw); | |
1064 | _rtl8723ae_disable_bcn_sufunc(hw); | |
1065 | } else { | |
1066 | RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING, | |
1067 | "Set HW_VAR_MEDIA_STATUS: No such media status(%x).\n", | |
1068 | type); | |
1069 | } | |
1070 | ||
1071 | switch (type) { | |
1072 | case NL80211_IFTYPE_UNSPECIFIED: | |
1073 | bt_msr |= MSR_NOLINK; | |
1074 | ledaction = LED_CTL_LINK; | |
1075 | RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE, | |
1076 | "Set Network type to NO LINK!\n"); | |
1077 | break; | |
1078 | case NL80211_IFTYPE_ADHOC: | |
1079 | bt_msr |= MSR_ADHOC; | |
1080 | RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE, | |
1081 | "Set Network type to Ad Hoc!\n"); | |
1082 | break; | |
1083 | case NL80211_IFTYPE_STATION: | |
1084 | bt_msr |= MSR_INFRA; | |
1085 | ledaction = LED_CTL_LINK; | |
1086 | RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE, | |
1087 | "Set Network type to STA!\n"); | |
1088 | break; | |
1089 | case NL80211_IFTYPE_AP: | |
1090 | bt_msr |= MSR_AP; | |
1091 | RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE, | |
1092 | "Set Network type to AP!\n"); | |
1093 | break; | |
1094 | default: | |
1095 | RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG, | |
1096 | "Network type %d not supported!\n", | |
1097 | type); | |
1098 | return 1; | |
1099 | break; | |
1100 | ||
1101 | } | |
1102 | ||
1103 | rtl_write_byte(rtlpriv, (MSR), bt_msr); | |
1104 | rtlpriv->cfg->ops->led_control(hw, ledaction); | |
1105 | if ((bt_msr & 0x03) == MSR_AP) | |
1106 | rtl_write_byte(rtlpriv, REG_BCNTCFG + 1, 0x00); | |
1107 | else | |
1108 | rtl_write_byte(rtlpriv, REG_BCNTCFG + 1, 0x66); | |
1109 | return 0; | |
1110 | } | |
1111 | ||
1112 | void rtl8723ae_set_check_bssid(struct ieee80211_hw *hw, bool check_bssid) | |
1113 | { | |
1114 | struct rtl_priv *rtlpriv = rtl_priv(hw); | |
1115 | struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw)); | |
1116 | u32 reg_rcr = rtlpci->receive_config; | |
1117 | ||
1118 | if (rtlpriv->psc.rfpwr_state != ERFON) | |
1119 | return; | |
1120 | ||
1121 | if (check_bssid == true) { | |
1122 | reg_rcr |= (RCR_CBSSID_DATA | RCR_CBSSID_BCN); | |
1123 | rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_RCR, | |
1124 | (u8 *)(®_rcr)); | |
1125 | _rtl8723ae_set_bcn_ctrl_reg(hw, 0, BIT(4)); | |
1126 | } else if (check_bssid == false) { | |
1127 | reg_rcr &= (~(RCR_CBSSID_DATA | RCR_CBSSID_BCN)); | |
1128 | _rtl8723ae_set_bcn_ctrl_reg(hw, BIT(4), 0); | |
1129 | rtlpriv->cfg->ops->set_hw_reg(hw, | |
1130 | HW_VAR_RCR, (u8 *) (®_rcr)); | |
1131 | } | |
1132 | } | |
1133 | ||
1134 | int rtl8723ae_set_network_type(struct ieee80211_hw *hw, | |
1135 | enum nl80211_iftype type) | |
1136 | { | |
1137 | struct rtl_priv *rtlpriv = rtl_priv(hw); | |
1138 | ||
1139 | if (_rtl8723ae_set_media_status(hw, type)) | |
1140 | return -EOPNOTSUPP; | |
1141 | ||
1142 | if (rtlpriv->mac80211.link_state == MAC80211_LINKED) { | |
1143 | if (type != NL80211_IFTYPE_AP) | |
1144 | rtl8723ae_set_check_bssid(hw, true); | |
1145 | } else { | |
1146 | rtl8723ae_set_check_bssid(hw, false); | |
1147 | } | |
1148 | return 0; | |
1149 | } | |
1150 | ||
1151 | /* don't set REG_EDCA_BE_PARAM here because mac80211 will send pkt when scan */ | |
1152 | void rtl8723ae_set_qos(struct ieee80211_hw *hw, int aci) | |
1153 | { | |
1154 | struct rtl_priv *rtlpriv = rtl_priv(hw); | |
1155 | ||
1156 | rtl8723ae_dm_init_edca_turbo(hw); | |
1157 | switch (aci) { | |
1158 | case AC1_BK: | |
1159 | rtl_write_dword(rtlpriv, REG_EDCA_BK_PARAM, 0xa44f); | |
1160 | break; | |
1161 | case AC0_BE: | |
1162 | /* rtl_write_dword(rtlpriv, REG_EDCA_BE_PARAM, u4ac_param); */ | |
1163 | break; | |
1164 | case AC2_VI: | |
1165 | rtl_write_dword(rtlpriv, REG_EDCA_VI_PARAM, 0x5e4322); | |
1166 | break; | |
1167 | case AC3_VO: | |
1168 | rtl_write_dword(rtlpriv, REG_EDCA_VO_PARAM, 0x2f3222); | |
1169 | break; | |
1170 | default: | |
1171 | RT_ASSERT(false, "invalid aci: %d !\n", aci); | |
1172 | break; | |
1173 | } | |
1174 | } | |
1175 | ||
1176 | void rtl8723ae_enable_interrupt(struct ieee80211_hw *hw) | |
1177 | { | |
1178 | struct rtl_priv *rtlpriv = rtl_priv(hw); | |
1179 | struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw)); | |
1180 | ||
1181 | rtl_write_dword(rtlpriv, 0x3a8, rtlpci->irq_mask[0] & 0xFFFFFFFF); | |
1182 | rtl_write_dword(rtlpriv, 0x3ac, rtlpci->irq_mask[1] & 0xFFFFFFFF); | |
1183 | rtlpci->irq_enabled = true; | |
1184 | } | |
1185 | ||
1186 | void rtl8723ae_disable_interrupt(struct ieee80211_hw *hw) | |
1187 | { | |
1188 | struct rtl_priv *rtlpriv = rtl_priv(hw); | |
1189 | struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw)); | |
1190 | ||
1191 | rtl_write_dword(rtlpriv, 0x3a8, IMR8190_DISABLED); | |
1192 | rtl_write_dword(rtlpriv, 0x3ac, IMR8190_DISABLED); | |
1193 | rtlpci->irq_enabled = false; | |
1194 | synchronize_irq(rtlpci->pdev->irq); | |
1195 | } | |
1196 | ||
1197 | static void _rtl8723ae_poweroff_adapter(struct ieee80211_hw *hw) | |
1198 | { | |
1199 | struct rtl_priv *rtlpriv = rtl_priv(hw); | |
1200 | struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw)); | |
1201 | u8 u1tmp; | |
1202 | ||
1203 | /* Combo (PCIe + USB) Card and PCIe-MF Card */ | |
1204 | /* 1. Run LPS WL RFOFF flow */ | |
1205 | rtl_hal_pwrseqcmdparsing(rtlpriv, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, | |
1206 | PWR_INTF_PCI_MSK, Rtl8723_NIC_LPS_ENTER_FLOW); | |
1207 | ||
1208 | /* 2. 0x1F[7:0] = 0 */ | |
1209 | /* turn off RF */ | |
1210 | rtl_write_byte(rtlpriv, REG_RF_CTRL, 0x00); | |
1211 | if ((rtl_read_byte(rtlpriv, REG_MCUFWDL) & BIT(7)) && rtlhal->fw_ready) | |
1212 | rtl8723ae_firmware_selfreset(hw); | |
1213 | ||
1214 | /* Reset MCU. Suggested by Filen. */ | |
1215 | u1tmp = rtl_read_byte(rtlpriv, REG_SYS_FUNC_EN+1); | |
1216 | rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN+1, (u1tmp & (~BIT(2)))); | |
1217 | ||
1218 | /* g. MCUFWDL 0x80[1:0]=0 */ | |
1219 | /* reset MCU ready status */ | |
1220 | rtl_write_byte(rtlpriv, REG_MCUFWDL, 0x00); | |
1221 | ||
1222 | /* HW card disable configuration. */ | |
1223 | rtl_hal_pwrseqcmdparsing(rtlpriv, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, | |
1224 | PWR_INTF_PCI_MSK, Rtl8723_NIC_DISABLE_FLOW); | |
1225 | ||
1226 | /* Reset MCU IO Wrapper */ | |
1227 | u1tmp = rtl_read_byte(rtlpriv, REG_RSV_CTRL + 1); | |
1228 | rtl_write_byte(rtlpriv, REG_RSV_CTRL + 1, (u1tmp & (~BIT(0)))); | |
1229 | u1tmp = rtl_read_byte(rtlpriv, REG_RSV_CTRL + 1); | |
1230 | rtl_write_byte(rtlpriv, REG_RSV_CTRL + 1, u1tmp | BIT(0)); | |
1231 | ||
1232 | /* 7. RSV_CTRL 0x1C[7:0] = 0x0E */ | |
1233 | /* lock ISO/CLK/Power control register */ | |
1234 | rtl_write_byte(rtlpriv, REG_RSV_CTRL, 0x0e); | |
1235 | } | |
1236 | ||
1237 | void rtl8723ae_card_disable(struct ieee80211_hw *hw) | |
1238 | { | |
1239 | struct rtl_priv *rtlpriv = rtl_priv(hw); | |
1240 | struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw)); | |
1241 | struct rtl_mac *mac = rtl_mac(rtl_priv(hw)); | |
1242 | struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw)); | |
1243 | enum nl80211_iftype opmode; | |
1244 | ||
1245 | mac->link_state = MAC80211_NOLINK; | |
1246 | opmode = NL80211_IFTYPE_UNSPECIFIED; | |
1247 | _rtl8723ae_set_media_status(hw, opmode); | |
1248 | if (rtlpci->driver_is_goingto_unload || | |
1249 | ppsc->rfoff_reason > RF_CHANGE_BY_PS) | |
1250 | rtlpriv->cfg->ops->led_control(hw, LED_CTL_POWER_OFF); | |
1251 | RT_SET_PS_LEVEL(ppsc, RT_RF_OFF_LEVL_HALT_NIC); | |
1252 | _rtl8723ae_poweroff_adapter(hw); | |
1253 | ||
1254 | /* after power off we should do iqk again */ | |
1255 | rtlpriv->phy.iqk_initialized = false; | |
1256 | } | |
1257 | ||
1258 | void rtl8723ae_interrupt_recognized(struct ieee80211_hw *hw, | |
1259 | u32 *p_inta, u32 *p_intb) | |
1260 | { | |
1261 | struct rtl_priv *rtlpriv = rtl_priv(hw); | |
1262 | struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw)); | |
1263 | ||
1264 | *p_inta = rtl_read_dword(rtlpriv, 0x3a0) & rtlpci->irq_mask[0]; | |
1265 | rtl_write_dword(rtlpriv, 0x3a0, *p_inta); | |
1266 | } | |
1267 | ||
1268 | void rtl8723ae_set_beacon_related_registers(struct ieee80211_hw *hw) | |
1269 | { | |
1270 | ||
1271 | struct rtl_priv *rtlpriv = rtl_priv(hw); | |
1272 | struct rtl_mac *mac = rtl_mac(rtl_priv(hw)); | |
1273 | u16 bcn_interval, atim_window; | |
1274 | ||
1275 | bcn_interval = mac->beacon_interval; | |
1276 | atim_window = 2; /*FIX MERGE */ | |
1277 | rtl8723ae_disable_interrupt(hw); | |
1278 | rtl_write_word(rtlpriv, REG_ATIMWND, atim_window); | |
1279 | rtl_write_word(rtlpriv, REG_BCN_INTERVAL, bcn_interval); | |
1280 | rtl_write_word(rtlpriv, REG_BCNTCFG, 0x660f); | |
1281 | rtl_write_byte(rtlpriv, REG_RXTSF_OFFSET_CCK, 0x18); | |
1282 | rtl_write_byte(rtlpriv, REG_RXTSF_OFFSET_OFDM, 0x18); | |
1283 | rtl_write_byte(rtlpriv, 0x606, 0x30); | |
1284 | rtl8723ae_enable_interrupt(hw); | |
1285 | } | |
1286 | ||
1287 | void rtl8723ae_set_beacon_interval(struct ieee80211_hw *hw) | |
1288 | { | |
1289 | struct rtl_priv *rtlpriv = rtl_priv(hw); | |
1290 | struct rtl_mac *mac = rtl_mac(rtl_priv(hw)); | |
1291 | u16 bcn_interval = mac->beacon_interval; | |
1292 | ||
1293 | RT_TRACE(rtlpriv, COMP_BEACON, DBG_DMESG, | |
1294 | "beacon_interval:%d\n", bcn_interval); | |
1295 | rtl8723ae_disable_interrupt(hw); | |
1296 | rtl_write_word(rtlpriv, REG_BCN_INTERVAL, bcn_interval); | |
1297 | rtl8723ae_enable_interrupt(hw); | |
1298 | } | |
1299 | ||
1300 | void rtl8723ae_update_interrupt_mask(struct ieee80211_hw *hw, | |
1301 | u32 add_msr, u32 rm_msr) | |
1302 | { | |
1303 | struct rtl_priv *rtlpriv = rtl_priv(hw); | |
1304 | struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw)); | |
1305 | ||
1306 | RT_TRACE(rtlpriv, COMP_INTR, DBG_LOUD, | |
1307 | "add_msr:%x, rm_msr:%x\n", add_msr, rm_msr); | |
1308 | ||
1309 | if (add_msr) | |
1310 | rtlpci->irq_mask[0] |= add_msr; | |
1311 | if (rm_msr) | |
1312 | rtlpci->irq_mask[0] &= (~rm_msr); | |
1313 | rtl8723ae_disable_interrupt(hw); | |
1314 | rtl8723ae_enable_interrupt(hw); | |
1315 | } | |
1316 | ||
1317 | static u8 _rtl8723ae_get_chnl_group(u8 chnl) | |
1318 | { | |
1319 | u8 group; | |
1320 | ||
1321 | if (chnl < 3) | |
1322 | group = 0; | |
1323 | else if (chnl < 9) | |
1324 | group = 1; | |
1325 | else | |
1326 | group = 2; | |
1327 | return group; | |
1328 | } | |
1329 | ||
1330 | static void _rtl8723ae_read_txpower_info_from_hwpg(struct ieee80211_hw *hw, | |
1331 | bool autoload_fail, | |
1332 | u8 *hwinfo) | |
1333 | { | |
1334 | struct rtl_priv *rtlpriv = rtl_priv(hw); | |
1335 | struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw)); | |
1336 | u8 rf_path, index, tempval; | |
1337 | u16 i; | |
1338 | ||
1339 | for (rf_path = 0; rf_path < 1; rf_path++) { | |
1340 | for (i = 0; i < 3; i++) { | |
1341 | if (!autoload_fail) { | |
1342 | rtlefuse->eeprom_chnlarea_txpwr_cck | |
1343 | [rf_path][i] = | |
1344 | hwinfo[EEPROM_TXPOWERCCK + rf_path * 3 + i]; | |
1345 | rtlefuse->eeprom_chnlarea_txpwr_ht40_1s | |
1346 | [rf_path][i] = | |
1347 | hwinfo[EEPROM_TXPOWERHT40_1S + rf_path * | |
1348 | 3 + i]; | |
1349 | } else { | |
1350 | rtlefuse->eeprom_chnlarea_txpwr_cck | |
1351 | [rf_path][i] = | |
1352 | EEPROM_DEFAULT_TXPOWERLEVEL; | |
1353 | rtlefuse->eeprom_chnlarea_txpwr_ht40_1s | |
1354 | [rf_path][i] = | |
1355 | EEPROM_DEFAULT_TXPOWERLEVEL; | |
1356 | } | |
1357 | } | |
1358 | } | |
1359 | ||
1360 | for (i = 0; i < 3; i++) { | |
1361 | if (!autoload_fail) | |
1362 | tempval = hwinfo[EEPROM_TXPOWERHT40_2SDIFF + i]; | |
1363 | else | |
1364 | tempval = EEPROM_DEFAULT_HT40_2SDIFF; | |
1365 | rtlefuse->eprom_chnl_txpwr_ht40_2sdf[RF90_PATH_A][i] = | |
1366 | (tempval & 0xf); | |
1367 | rtlefuse->eprom_chnl_txpwr_ht40_2sdf[RF90_PATH_B][i] = | |
1368 | ((tempval & 0xf0) >> 4); | |
1369 | } | |
1370 | ||
1371 | for (rf_path = 0; rf_path < 2; rf_path++) | |
1372 | for (i = 0; i < 3; i++) | |
1373 | RTPRINT(rtlpriv, FINIT, INIT_EEPROM, | |
1374 | "RF(%d) EEPROM CCK Area(%d) = 0x%x\n", rf_path, | |
1375 | i, rtlefuse->eeprom_chnlarea_txpwr_cck | |
1376 | [rf_path][i]); | |
1377 | for (rf_path = 0; rf_path < 2; rf_path++) | |
1378 | for (i = 0; i < 3; i++) | |
1379 | RTPRINT(rtlpriv, FINIT, INIT_EEPROM, | |
1380 | "RF(%d) EEPROM HT40 1S Area(%d) = 0x%x\n", | |
1381 | rf_path, i, | |
1382 | rtlefuse->eeprom_chnlarea_txpwr_ht40_1s | |
1383 | [rf_path][i]); | |
1384 | for (rf_path = 0; rf_path < 2; rf_path++) | |
1385 | for (i = 0; i < 3; i++) | |
1386 | RTPRINT(rtlpriv, FINIT, INIT_EEPROM, | |
1387 | "RF(%d) EEPROM HT40 2S Diff Area(%d) = 0x%x\n", | |
1388 | rf_path, i, | |
1389 | rtlefuse->eprom_chnl_txpwr_ht40_2sdf | |
1390 | [rf_path][i]); | |
1391 | ||
1392 | for (rf_path = 0; rf_path < 2; rf_path++) { | |
1393 | for (i = 0; i < 14; i++) { | |
1394 | index = _rtl8723ae_get_chnl_group((u8) i); | |
1395 | ||
1396 | rtlefuse->txpwrlevel_cck[rf_path][i] = | |
1397 | rtlefuse->eeprom_chnlarea_txpwr_cck | |
1398 | [rf_path][index]; | |
1399 | rtlefuse->txpwrlevel_ht40_1s[rf_path][i] = | |
1400 | rtlefuse->eeprom_chnlarea_txpwr_ht40_1s | |
1401 | [rf_path][index]; | |
1402 | ||
1403 | if ((rtlefuse->eeprom_chnlarea_txpwr_ht40_1s | |
1404 | [rf_path][index] - | |
1405 | rtlefuse->eprom_chnl_txpwr_ht40_2sdf[rf_path] | |
1406 | [index]) > 0) { | |
1407 | rtlefuse->txpwrlevel_ht40_2s[rf_path][i] = | |
1408 | rtlefuse->eeprom_chnlarea_txpwr_ht40_1s | |
1409 | [rf_path][index] - | |
1410 | rtlefuse->eprom_chnl_txpwr_ht40_2sdf | |
1411 | [rf_path][index]; | |
1412 | } else { | |
1413 | rtlefuse->txpwrlevel_ht40_2s[rf_path][i] = 0; | |
1414 | } | |
1415 | } | |
1416 | ||
1417 | for (i = 0; i < 14; i++) { | |
e6deaf81 | 1418 | RTPRINT(rtlpriv, FINIT, INIT_TXPOWER, |
c592e631 LF |
1419 | "RF(%d)-Ch(%d) [CCK / HT40_1S / HT40_2S] = " |
1420 | "[0x%x / 0x%x / 0x%x]\n", rf_path, i, | |
1421 | rtlefuse->txpwrlevel_cck[rf_path][i], | |
1422 | rtlefuse->txpwrlevel_ht40_1s[rf_path][i], | |
1423 | rtlefuse->txpwrlevel_ht40_2s[rf_path][i]); | |
1424 | } | |
1425 | } | |
1426 | ||
1427 | for (i = 0; i < 3; i++) { | |
1428 | if (!autoload_fail) { | |
1429 | rtlefuse->eeprom_pwrlimit_ht40[i] = | |
1430 | hwinfo[EEPROM_TXPWR_GROUP + i]; | |
1431 | rtlefuse->eeprom_pwrlimit_ht20[i] = | |
1432 | hwinfo[EEPROM_TXPWR_GROUP + 3 + i]; | |
1433 | } else { | |
1434 | rtlefuse->eeprom_pwrlimit_ht40[i] = 0; | |
1435 | rtlefuse->eeprom_pwrlimit_ht20[i] = 0; | |
1436 | } | |
1437 | } | |
1438 | ||
1439 | for (rf_path = 0; rf_path < 2; rf_path++) { | |
1440 | for (i = 0; i < 14; i++) { | |
1441 | index = _rtl8723ae_get_chnl_group((u8) i); | |
1442 | ||
1443 | if (rf_path == RF90_PATH_A) { | |
1444 | rtlefuse->pwrgroup_ht20[rf_path][i] = | |
1445 | (rtlefuse->eeprom_pwrlimit_ht20[index] & | |
1446 | 0xf); | |
1447 | rtlefuse->pwrgroup_ht40[rf_path][i] = | |
1448 | (rtlefuse->eeprom_pwrlimit_ht40[index] & | |
1449 | 0xf); | |
1450 | } else if (rf_path == RF90_PATH_B) { | |
1451 | rtlefuse->pwrgroup_ht20[rf_path][i] = | |
1452 | ((rtlefuse->eeprom_pwrlimit_ht20[index] & | |
1453 | 0xf0) >> 4); | |
1454 | rtlefuse->pwrgroup_ht40[rf_path][i] = | |
1455 | ((rtlefuse->eeprom_pwrlimit_ht40[index] & | |
1456 | 0xf0) >> 4); | |
1457 | } | |
1458 | ||
e6deaf81 | 1459 | RTPRINT(rtlpriv, FINIT, INIT_TXPOWER, |
c592e631 LF |
1460 | "RF-%d pwrgroup_ht20[%d] = 0x%x\n", rf_path, i, |
1461 | rtlefuse->pwrgroup_ht20[rf_path][i]); | |
e6deaf81 | 1462 | RTPRINT(rtlpriv, FINIT, INIT_TXPOWER, |
c592e631 LF |
1463 | "RF-%d pwrgroup_ht40[%d] = 0x%x\n", rf_path, i, |
1464 | rtlefuse->pwrgroup_ht40[rf_path][i]); | |
1465 | } | |
1466 | } | |
1467 | ||
1468 | for (i = 0; i < 14; i++) { | |
1469 | index = _rtl8723ae_get_chnl_group((u8) i); | |
1470 | ||
1471 | if (!autoload_fail) | |
1472 | tempval = hwinfo[EEPROM_TXPOWERHT20DIFF + index]; | |
1473 | else | |
1474 | tempval = EEPROM_DEFAULT_HT20_DIFF; | |
1475 | ||
1476 | rtlefuse->txpwr_ht20diff[RF90_PATH_A][i] = (tempval & 0xF); | |
1477 | rtlefuse->txpwr_ht20diff[RF90_PATH_B][i] = | |
1478 | ((tempval >> 4) & 0xF); | |
1479 | ||
1480 | if (rtlefuse->txpwr_ht20diff[RF90_PATH_A][i] & BIT(3)) | |
1481 | rtlefuse->txpwr_ht20diff[RF90_PATH_A][i] |= 0xF0; | |
1482 | ||
1483 | if (rtlefuse->txpwr_ht20diff[RF90_PATH_B][i] & BIT(3)) | |
1484 | rtlefuse->txpwr_ht20diff[RF90_PATH_B][i] |= 0xF0; | |
1485 | ||
1486 | index = _rtl8723ae_get_chnl_group((u8) i); | |
1487 | ||
1488 | if (!autoload_fail) | |
1489 | tempval = hwinfo[EEPROM_TXPOWER_OFDMDIFF + index]; | |
1490 | else | |
1491 | tempval = EEPROM_DEFAULT_LEGACYHTTXPOWERDIFF; | |
1492 | ||
1493 | rtlefuse->txpwr_legacyhtdiff[RF90_PATH_A][i] = (tempval & 0xF); | |
1494 | rtlefuse->txpwr_legacyhtdiff[RF90_PATH_B][i] = | |
1495 | ((tempval >> 4) & 0xF); | |
1496 | } | |
1497 | ||
1498 | rtlefuse->legacy_ht_txpowerdiff = | |
1499 | rtlefuse->txpwr_legacyhtdiff[RF90_PATH_A][7]; | |
1500 | ||
1501 | for (i = 0; i < 14; i++) | |
e6deaf81 | 1502 | RTPRINT(rtlpriv, FINIT, INIT_TXPOWER, |
c592e631 LF |
1503 | "RF-A Ht20 to HT40 Diff[%d] = 0x%x\n", i, |
1504 | rtlefuse->txpwr_ht20diff[RF90_PATH_A][i]); | |
1505 | for (i = 0; i < 14; i++) | |
e6deaf81 | 1506 | RTPRINT(rtlpriv, FINIT, INIT_TXPOWER, |
c592e631 LF |
1507 | "RF-A Legacy to Ht40 Diff[%d] = 0x%x\n", i, |
1508 | rtlefuse->txpwr_legacyhtdiff[RF90_PATH_A][i]); | |
1509 | for (i = 0; i < 14; i++) | |
e6deaf81 | 1510 | RTPRINT(rtlpriv, FINIT, INIT_TXPOWER, |
c592e631 LF |
1511 | "RF-B Ht20 to HT40 Diff[%d] = 0x%x\n", i, |
1512 | rtlefuse->txpwr_ht20diff[RF90_PATH_B][i]); | |
1513 | for (i = 0; i < 14; i++) | |
e6deaf81 | 1514 | RTPRINT(rtlpriv, FINIT, INIT_TXPOWER, |
c592e631 LF |
1515 | "RF-B Legacy to HT40 Diff[%d] = 0x%x\n", i, |
1516 | rtlefuse->txpwr_legacyhtdiff[RF90_PATH_B][i]); | |
1517 | ||
1518 | if (!autoload_fail) | |
1519 | rtlefuse->eeprom_regulatory = (hwinfo[RF_OPTION1] & 0x7); | |
1520 | else | |
1521 | rtlefuse->eeprom_regulatory = 0; | |
e6deaf81 | 1522 | RTPRINT(rtlpriv, FINIT, INIT_TXPOWER, |
c592e631 LF |
1523 | "eeprom_regulatory = 0x%x\n", rtlefuse->eeprom_regulatory); |
1524 | ||
1525 | if (!autoload_fail) | |
1526 | rtlefuse->eeprom_tssi[RF90_PATH_A] = hwinfo[EEPROM_TSSI_A]; | |
1527 | else | |
1528 | rtlefuse->eeprom_tssi[RF90_PATH_A] = EEPROM_DEFAULT_TSSI; | |
e6deaf81 | 1529 | RTPRINT(rtlpriv, FINIT, INIT_TXPOWER, |
c592e631 LF |
1530 | "TSSI_A = 0x%x, TSSI_B = 0x%x\n", |
1531 | rtlefuse->eeprom_tssi[RF90_PATH_A], | |
1532 | rtlefuse->eeprom_tssi[RF90_PATH_B]); | |
1533 | ||
1534 | if (!autoload_fail) | |
1535 | tempval = hwinfo[EEPROM_THERMAL_METER]; | |
1536 | else | |
1537 | tempval = EEPROM_DEFAULT_THERMALMETER; | |
1538 | rtlefuse->eeprom_thermalmeter = (tempval & 0x1f); | |
1539 | ||
1540 | if (rtlefuse->eeprom_thermalmeter == 0x1f || autoload_fail) | |
1541 | rtlefuse->apk_thermalmeterignore = true; | |
1542 | ||
1543 | rtlefuse->thermalmeter[0] = rtlefuse->eeprom_thermalmeter; | |
e6deaf81 | 1544 | RTPRINT(rtlpriv, FINIT, INIT_TXPOWER, |
c592e631 LF |
1545 | "thermalmeter = 0x%x\n", rtlefuse->eeprom_thermalmeter); |
1546 | } | |
1547 | ||
1548 | static void _rtl8723ae_read_adapter_info(struct ieee80211_hw *hw, | |
1549 | bool pseudo_test) | |
1550 | { | |
1551 | struct rtl_priv *rtlpriv = rtl_priv(hw); | |
1552 | struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw)); | |
1553 | struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw)); | |
1554 | u16 i, usvalue; | |
1555 | u8 hwinfo[HWSET_MAX_SIZE]; | |
1556 | u16 eeprom_id; | |
1557 | ||
1558 | if (pseudo_test) { | |
1559 | /* need add */ | |
1560 | return; | |
1561 | } | |
1562 | if (rtlefuse->epromtype == EEPROM_BOOT_EFUSE) { | |
1563 | rtl_efuse_shadow_map_update(hw); | |
1564 | ||
1565 | memcpy(hwinfo, &rtlefuse->efuse_map[EFUSE_INIT_MAP][0], | |
1566 | HWSET_MAX_SIZE); | |
1567 | } else if (rtlefuse->epromtype == EEPROM_93C46) { | |
1568 | RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG, | |
1569 | "RTL819X Not boot from eeprom, check it !!"); | |
1570 | } | |
1571 | ||
1572 | RT_PRINT_DATA(rtlpriv, COMP_INIT, DBG_DMESG, ("MAP\n"), | |
1573 | hwinfo, HWSET_MAX_SIZE); | |
1574 | ||
1575 | eeprom_id = *((u16 *)&hwinfo[0]); | |
1576 | if (eeprom_id != RTL8190_EEPROM_ID) { | |
1577 | RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING, | |
1578 | "EEPROM ID(%#x) is invalid!!\n", eeprom_id); | |
1579 | rtlefuse->autoload_failflag = true; | |
1580 | } else { | |
1581 | RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, "Autoload OK\n"); | |
1582 | rtlefuse->autoload_failflag = false; | |
1583 | } | |
1584 | ||
1585 | if (rtlefuse->autoload_failflag == true) | |
1586 | return; | |
1587 | ||
1588 | rtlefuse->eeprom_vid = *(u16 *) &hwinfo[EEPROM_VID]; | |
1589 | rtlefuse->eeprom_did = *(u16 *) &hwinfo[EEPROM_DID]; | |
1590 | rtlefuse->eeprom_svid = *(u16 *) &hwinfo[EEPROM_SVID]; | |
1591 | rtlefuse->eeprom_smid = *(u16 *) &hwinfo[EEPROM_SMID]; | |
1592 | RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, | |
1593 | "EEPROMId = 0x%4x\n", eeprom_id); | |
1594 | RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, | |
1595 | "EEPROM VID = 0x%4x\n", rtlefuse->eeprom_vid); | |
1596 | RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, | |
1597 | "EEPROM DID = 0x%4x\n", rtlefuse->eeprom_did); | |
1598 | RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, | |
1599 | "EEPROM SVID = 0x%4x\n", rtlefuse->eeprom_svid); | |
1600 | RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, | |
1601 | "EEPROM SMID = 0x%4x\n", rtlefuse->eeprom_smid); | |
1602 | ||
1603 | for (i = 0; i < 6; i += 2) { | |
1604 | usvalue = *(u16 *)&hwinfo[EEPROM_MAC_ADDR + i]; | |
1605 | *((u16 *) (&rtlefuse->dev_addr[i])) = usvalue; | |
1606 | } | |
1607 | ||
1608 | RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG, | |
1609 | "dev_addr: %pM\n", rtlefuse->dev_addr); | |
1610 | ||
1611 | _rtl8723ae_read_txpower_info_from_hwpg(hw, | |
1612 | rtlefuse->autoload_failflag, hwinfo); | |
1613 | ||
1614 | rtl8723ae_read_bt_coexist_info_from_hwpg(hw, | |
1615 | rtlefuse->autoload_failflag, hwinfo); | |
1616 | ||
1617 | rtlefuse->eeprom_channelplan = *(u8 *)&hwinfo[EEPROM_CHANNELPLAN]; | |
1618 | rtlefuse->eeprom_version = *(u16 *)&hwinfo[EEPROM_VERSION]; | |
1619 | rtlefuse->txpwr_fromeprom = true; | |
1620 | rtlefuse->eeprom_oemid = *(u8 *)&hwinfo[EEPROM_CUSTOMER_ID]; | |
1621 | ||
1622 | RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, | |
1623 | "EEPROM Customer ID: 0x%2x\n", rtlefuse->eeprom_oemid); | |
1624 | ||
1625 | /* set channel paln to world wide 13 */ | |
1626 | rtlefuse->channel_plan = COUNTRY_CODE_WORLD_WIDE_13; | |
1627 | ||
1628 | if (rtlhal->oem_id == RT_CID_DEFAULT) { | |
1629 | switch (rtlefuse->eeprom_oemid) { | |
1630 | case EEPROM_CID_DEFAULT: | |
1631 | if (rtlefuse->eeprom_did == 0x8176) { | |
1632 | if (CHK_SVID_SMID(0x10EC, 0x6151) || | |
1633 | CHK_SVID_SMID(0x10EC, 0x6152) || | |
1634 | CHK_SVID_SMID(0x10EC, 0x6154) || | |
1635 | CHK_SVID_SMID(0x10EC, 0x6155) || | |
1636 | CHK_SVID_SMID(0x10EC, 0x6177) || | |
1637 | CHK_SVID_SMID(0x10EC, 0x6178) || | |
1638 | CHK_SVID_SMID(0x10EC, 0x6179) || | |
1639 | CHK_SVID_SMID(0x10EC, 0x6180) || | |
1640 | CHK_SVID_SMID(0x10EC, 0x8151) || | |
1641 | CHK_SVID_SMID(0x10EC, 0x8152) || | |
1642 | CHK_SVID_SMID(0x10EC, 0x8154) || | |
1643 | CHK_SVID_SMID(0x10EC, 0x8155) || | |
1644 | CHK_SVID_SMID(0x10EC, 0x8181) || | |
1645 | CHK_SVID_SMID(0x10EC, 0x8182) || | |
1646 | CHK_SVID_SMID(0x10EC, 0x8184) || | |
1647 | CHK_SVID_SMID(0x10EC, 0x8185) || | |
1648 | CHK_SVID_SMID(0x10EC, 0x9151) || | |
1649 | CHK_SVID_SMID(0x10EC, 0x9152) || | |
1650 | CHK_SVID_SMID(0x10EC, 0x9154) || | |
1651 | CHK_SVID_SMID(0x10EC, 0x9155) || | |
1652 | CHK_SVID_SMID(0x10EC, 0x9181) || | |
1653 | CHK_SVID_SMID(0x10EC, 0x9182) || | |
1654 | CHK_SVID_SMID(0x10EC, 0x9184) || | |
1655 | CHK_SVID_SMID(0x10EC, 0x9185)) | |
1656 | rtlhal->oem_id = RT_CID_TOSHIBA; | |
1657 | else if (rtlefuse->eeprom_svid == 0x1025) | |
1658 | rtlhal->oem_id = RT_CID_819x_Acer; | |
1659 | else if (CHK_SVID_SMID(0x10EC, 0x6191) || | |
1660 | CHK_SVID_SMID(0x10EC, 0x6192) || | |
1661 | CHK_SVID_SMID(0x10EC, 0x6193) || | |
1662 | CHK_SVID_SMID(0x10EC, 0x7191) || | |
1663 | CHK_SVID_SMID(0x10EC, 0x7192) || | |
1664 | CHK_SVID_SMID(0x10EC, 0x7193) || | |
1665 | CHK_SVID_SMID(0x10EC, 0x8191) || | |
1666 | CHK_SVID_SMID(0x10EC, 0x8192) || | |
1667 | CHK_SVID_SMID(0x10EC, 0x8193)) | |
1668 | rtlhal->oem_id = RT_CID_819x_SAMSUNG; | |
1669 | else if (CHK_SVID_SMID(0x10EC, 0x8195) || | |
1670 | CHK_SVID_SMID(0x10EC, 0x9195) || | |
1671 | CHK_SVID_SMID(0x10EC, 0x7194) || | |
1672 | CHK_SVID_SMID(0x10EC, 0x8200) || | |
1673 | CHK_SVID_SMID(0x10EC, 0x8201) || | |
1674 | CHK_SVID_SMID(0x10EC, 0x8202) || | |
1675 | CHK_SVID_SMID(0x10EC, 0x9200)) | |
1676 | rtlhal->oem_id = RT_CID_819x_Lenovo; | |
1677 | else if (CHK_SVID_SMID(0x10EC, 0x8197) || | |
1678 | CHK_SVID_SMID(0x10EC, 0x9196)) | |
1679 | rtlhal->oem_id = RT_CID_819x_CLEVO; | |
1680 | else if (CHK_SVID_SMID(0x1028, 0x8194) || | |
1681 | CHK_SVID_SMID(0x1028, 0x8198) || | |
1682 | CHK_SVID_SMID(0x1028, 0x9197) || | |
1683 | CHK_SVID_SMID(0x1028, 0x9198)) | |
1684 | rtlhal->oem_id = RT_CID_819x_DELL; | |
1685 | else if (CHK_SVID_SMID(0x103C, 0x1629)) | |
1686 | rtlhal->oem_id = RT_CID_819x_HP; | |
1687 | else if (CHK_SVID_SMID(0x1A32, 0x2315)) | |
1688 | rtlhal->oem_id = RT_CID_819x_QMI; | |
1689 | else if (CHK_SVID_SMID(0x10EC, 0x8203)) | |
1690 | rtlhal->oem_id = RT_CID_819x_PRONETS; | |
1691 | else if (CHK_SVID_SMID(0x1043, 0x84B5)) | |
1692 | rtlhal->oem_id = | |
1693 | RT_CID_819x_Edimax_ASUS; | |
1694 | else | |
1695 | rtlhal->oem_id = RT_CID_DEFAULT; | |
1696 | } else if (rtlefuse->eeprom_did == 0x8178) { | |
1697 | if (CHK_SVID_SMID(0x10EC, 0x6181) || | |
1698 | CHK_SVID_SMID(0x10EC, 0x6182) || | |
1699 | CHK_SVID_SMID(0x10EC, 0x6184) || | |
1700 | CHK_SVID_SMID(0x10EC, 0x6185) || | |
1701 | CHK_SVID_SMID(0x10EC, 0x7181) || | |
1702 | CHK_SVID_SMID(0x10EC, 0x7182) || | |
1703 | CHK_SVID_SMID(0x10EC, 0x7184) || | |
1704 | CHK_SVID_SMID(0x10EC, 0x7185) || | |
1705 | CHK_SVID_SMID(0x10EC, 0x8181) || | |
1706 | CHK_SVID_SMID(0x10EC, 0x8182) || | |
1707 | CHK_SVID_SMID(0x10EC, 0x8184) || | |
1708 | CHK_SVID_SMID(0x10EC, 0x8185) || | |
1709 | CHK_SVID_SMID(0x10EC, 0x9181) || | |
1710 | CHK_SVID_SMID(0x10EC, 0x9182) || | |
1711 | CHK_SVID_SMID(0x10EC, 0x9184) || | |
1712 | CHK_SVID_SMID(0x10EC, 0x9185)) | |
1713 | rtlhal->oem_id = RT_CID_TOSHIBA; | |
1714 | else if (rtlefuse->eeprom_svid == 0x1025) | |
1715 | rtlhal->oem_id = RT_CID_819x_Acer; | |
1716 | else if (CHK_SVID_SMID(0x10EC, 0x8186)) | |
1717 | rtlhal->oem_id = RT_CID_819x_PRONETS; | |
1718 | else if (CHK_SVID_SMID(0x1043, 0x8486)) | |
1719 | rtlhal->oem_id = | |
1720 | RT_CID_819x_Edimax_ASUS; | |
1721 | else | |
1722 | rtlhal->oem_id = RT_CID_DEFAULT; | |
1723 | } else { | |
1724 | rtlhal->oem_id = RT_CID_DEFAULT; | |
1725 | } | |
1726 | break; | |
1727 | case EEPROM_CID_TOSHIBA: | |
1728 | rtlhal->oem_id = RT_CID_TOSHIBA; | |
1729 | break; | |
1730 | case EEPROM_CID_CCX: | |
1731 | rtlhal->oem_id = RT_CID_CCX; | |
1732 | break; | |
1733 | case EEPROM_CID_QMI: | |
1734 | rtlhal->oem_id = RT_CID_819x_QMI; | |
1735 | break; | |
1736 | case EEPROM_CID_WHQL: | |
1737 | break; | |
1738 | default: | |
1739 | rtlhal->oem_id = RT_CID_DEFAULT; | |
1740 | break; | |
1741 | ||
1742 | } | |
1743 | } | |
1744 | } | |
1745 | ||
1746 | static void _rtl8723ae_hal_customized_behavior(struct ieee80211_hw *hw) | |
1747 | { | |
1748 | struct rtl_priv *rtlpriv = rtl_priv(hw); | |
1749 | struct rtl_pci_priv *pcipriv = rtl_pcipriv(hw); | |
1750 | struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw)); | |
1751 | ||
e6deaf81 | 1752 | pcipriv->ledctl.led_opendrain = true; |
c592e631 LF |
1753 | RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG, |
1754 | "RT Customized ID: 0x%02X\n", rtlhal->oem_id); | |
1755 | } | |
1756 | ||
1757 | void rtl8723ae_read_eeprom_info(struct ieee80211_hw *hw) | |
1758 | { | |
1759 | struct rtl_priv *rtlpriv = rtl_priv(hw); | |
1760 | struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw)); | |
1761 | struct rtl_phy *rtlphy = &(rtlpriv->phy); | |
1762 | struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw)); | |
1763 | u8 tmp_u1b; | |
1764 | u32 value32; | |
1765 | ||
1766 | value32 = rtl_read_dword(rtlpriv, rtlpriv->cfg->maps[EFUSE_TEST]); | |
1767 | value32 = (value32 & ~EFUSE_SEL_MASK) | EFUSE_SEL(EFUSE_WIFI_SEL_0); | |
1768 | rtl_write_dword(rtlpriv, rtlpriv->cfg->maps[EFUSE_TEST], value32); | |
1769 | ||
1770 | rtlhal->version = _rtl8723ae_read_chip_version(hw); | |
1771 | ||
1772 | if (get_rf_type(rtlphy) == RF_1T1R) | |
1773 | rtlpriv->dm.rfpath_rxenable[0] = true; | |
1774 | else | |
1775 | rtlpriv->dm.rfpath_rxenable[0] = | |
1776 | rtlpriv->dm.rfpath_rxenable[1] = true; | |
1777 | RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, "VersionID = 0x%4x\n", | |
1778 | rtlhal->version); | |
1779 | ||
1780 | tmp_u1b = rtl_read_byte(rtlpriv, REG_9346CR); | |
1781 | if (tmp_u1b & BIT(4)) { | |
1782 | RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG, "Boot from EEPROM\n"); | |
1783 | rtlefuse->epromtype = EEPROM_93C46; | |
1784 | } else { | |
1785 | RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG, "Boot from EFUSE\n"); | |
1786 | rtlefuse->epromtype = EEPROM_BOOT_EFUSE; | |
1787 | } | |
1788 | if (tmp_u1b & BIT(5)) { | |
1789 | RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, "Autoload OK\n"); | |
1790 | rtlefuse->autoload_failflag = false; | |
1791 | _rtl8723ae_read_adapter_info(hw, false); | |
1792 | } else { | |
1793 | rtlefuse->autoload_failflag = true; | |
1794 | _rtl8723ae_read_adapter_info(hw, false); | |
1795 | RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG, "Autoload ERR!!\n"); | |
1796 | } | |
1797 | _rtl8723ae_hal_customized_behavior(hw); | |
1798 | } | |
1799 | ||
1800 | static void rtl8723ae_update_hal_rate_table(struct ieee80211_hw *hw, | |
1801 | struct ieee80211_sta *sta) | |
1802 | { | |
1803 | struct rtl_priv *rtlpriv = rtl_priv(hw); | |
1804 | struct rtl_pci_priv *pcipriv = rtl_pcipriv(hw); | |
1805 | struct rtl_phy *rtlphy = &(rtlpriv->phy); | |
1806 | struct rtl_mac *mac = rtl_mac(rtl_priv(hw)); | |
1807 | struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw)); | |
1808 | u32 ratr_value; | |
1809 | u8 ratr_index = 0; | |
1810 | u8 nmode = mac->ht_enable; | |
1811 | u8 mimo_ps = IEEE80211_SMPS_OFF; | |
1812 | u8 curtxbw_40mhz = mac->bw_40; | |
1813 | u8 curshortgi_40mhz = (sta->ht_cap.cap & IEEE80211_HT_CAP_SGI_40) ? | |
1814 | 1 : 0; | |
1815 | u8 curshortgi_20mhz = (sta->ht_cap.cap & IEEE80211_HT_CAP_SGI_20) ? | |
1816 | 1 : 0; | |
1817 | enum wireless_mode wirelessmode = mac->mode; | |
1818 | ||
1819 | if (rtlhal->current_bandtype == BAND_ON_5G) | |
1820 | ratr_value = sta->supp_rates[1] << 4; | |
1821 | else | |
1822 | ratr_value = sta->supp_rates[0]; | |
1823 | if (mac->opmode == NL80211_IFTYPE_ADHOC) | |
1824 | ratr_value = 0xfff; | |
1825 | ratr_value |= (sta->ht_cap.mcs.rx_mask[1] << 20 | | |
1826 | sta->ht_cap.mcs.rx_mask[0] << 12); | |
1827 | switch (wirelessmode) { | |
1828 | case WIRELESS_MODE_B: | |
1829 | if (ratr_value & 0x0000000c) | |
1830 | ratr_value &= 0x0000000d; | |
1831 | else | |
1832 | ratr_value &= 0x0000000f; | |
1833 | break; | |
1834 | case WIRELESS_MODE_G: | |
1835 | ratr_value &= 0x00000FF5; | |
1836 | break; | |
1837 | case WIRELESS_MODE_N_24G: | |
1838 | case WIRELESS_MODE_N_5G: | |
1839 | nmode = 1; | |
1840 | if (mimo_ps == IEEE80211_SMPS_STATIC) { | |
1841 | ratr_value &= 0x0007F005; | |
1842 | } else { | |
1843 | u32 ratr_mask; | |
1844 | ||
1845 | if (get_rf_type(rtlphy) == RF_1T2R || | |
1846 | get_rf_type(rtlphy) == RF_1T1R) | |
1847 | ratr_mask = 0x000ff005; | |
1848 | else | |
1849 | ratr_mask = 0x0f0ff005; | |
1850 | ||
1851 | ratr_value &= ratr_mask; | |
1852 | } | |
1853 | break; | |
1854 | default: | |
1855 | if (rtlphy->rf_type == RF_1T2R) | |
1856 | ratr_value &= 0x000ff0ff; | |
1857 | else | |
1858 | ratr_value &= 0x0f0ff0ff; | |
1859 | ||
1860 | break; | |
1861 | } | |
1862 | ||
1863 | if ((pcipriv->bt_coexist.bt_coexistence) && | |
1864 | (pcipriv->bt_coexist.bt_coexist_type == BT_CSR_BC4) && | |
1865 | (pcipriv->bt_coexist.bt_cur_state) && | |
1866 | (pcipriv->bt_coexist.bt_ant_isolation) && | |
1867 | ((pcipriv->bt_coexist.bt_service == BT_SCO) || | |
1868 | (pcipriv->bt_coexist.bt_service == BT_BUSY))) | |
1869 | ratr_value &= 0x0fffcfc0; | |
1870 | else | |
1871 | ratr_value &= 0x0FFFFFFF; | |
1872 | ||
1873 | if (nmode && ((curtxbw_40mhz && curshortgi_40mhz) || | |
1874 | (!curtxbw_40mhz && curshortgi_20mhz))) | |
1875 | ratr_value |= 0x10000000; | |
1876 | ||
1877 | rtl_write_dword(rtlpriv, REG_ARFR0 + ratr_index * 4, ratr_value); | |
1878 | ||
1879 | RT_TRACE(rtlpriv, COMP_RATR, DBG_DMESG, | |
1880 | "%x\n", rtl_read_dword(rtlpriv, REG_ARFR0)); | |
1881 | } | |
1882 | ||
1883 | static void rtl8723ae_update_hal_rate_mask(struct ieee80211_hw *hw, | |
1884 | struct ieee80211_sta *sta, u8 rssi_level) | |
1885 | { | |
1886 | struct rtl_priv *rtlpriv = rtl_priv(hw); | |
1887 | struct rtl_phy *rtlphy = &(rtlpriv->phy); | |
1888 | struct rtl_mac *mac = rtl_mac(rtl_priv(hw)); | |
1889 | struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw)); | |
1890 | struct rtl_sta_info *sta_entry = NULL; | |
1891 | u32 ratr_bitmap; | |
1892 | u8 ratr_index; | |
e1a0c6b3 | 1893 | u8 curtxbw_40mhz = (sta->bandwidth >= IEEE80211_STA_RX_BW_40) ? 1 : 0; |
c592e631 LF |
1894 | u8 curshortgi_40mhz = (sta->ht_cap.cap & IEEE80211_HT_CAP_SGI_40) ? |
1895 | 1 : 0; | |
1896 | u8 curshortgi_20mhz = (sta->ht_cap.cap & IEEE80211_HT_CAP_SGI_20) ? | |
1897 | 1 : 0; | |
1898 | enum wireless_mode wirelessmode = 0; | |
1899 | bool shortgi = false; | |
1900 | u8 rate_mask[5]; | |
1901 | u8 macid = 0; | |
1902 | u8 mimo_ps = IEEE80211_SMPS_OFF; | |
1903 | ||
1904 | sta_entry = (struct rtl_sta_info *) sta->drv_priv; | |
1905 | wirelessmode = sta_entry->wireless_mode; | |
1906 | if (mac->opmode == NL80211_IFTYPE_STATION) | |
1907 | curtxbw_40mhz = mac->bw_40; | |
1908 | else if (mac->opmode == NL80211_IFTYPE_AP || | |
1909 | mac->opmode == NL80211_IFTYPE_ADHOC) | |
1910 | macid = sta->aid + 1; | |
1911 | ||
1912 | if (rtlhal->current_bandtype == BAND_ON_5G) | |
1913 | ratr_bitmap = sta->supp_rates[1] << 4; | |
1914 | else | |
1915 | ratr_bitmap = sta->supp_rates[0]; | |
1916 | if (mac->opmode == NL80211_IFTYPE_ADHOC) | |
1917 | ratr_bitmap = 0xfff; | |
1918 | ratr_bitmap |= (sta->ht_cap.mcs.rx_mask[1] << 20 | | |
1919 | sta->ht_cap.mcs.rx_mask[0] << 12); | |
1920 | switch (wirelessmode) { | |
1921 | case WIRELESS_MODE_B: | |
1922 | ratr_index = RATR_INX_WIRELESS_B; | |
1923 | if (ratr_bitmap & 0x0000000c) | |
1924 | ratr_bitmap &= 0x0000000d; | |
1925 | else | |
1926 | ratr_bitmap &= 0x0000000f; | |
1927 | break; | |
1928 | case WIRELESS_MODE_G: | |
1929 | ratr_index = RATR_INX_WIRELESS_GB; | |
1930 | ||
1931 | if (rssi_level == 1) | |
1932 | ratr_bitmap &= 0x00000f00; | |
1933 | else if (rssi_level == 2) | |
1934 | ratr_bitmap &= 0x00000ff0; | |
1935 | else | |
1936 | ratr_bitmap &= 0x00000ff5; | |
1937 | break; | |
1938 | case WIRELESS_MODE_A: | |
1939 | ratr_index = RATR_INX_WIRELESS_A; | |
1940 | ratr_bitmap &= 0x00000ff0; | |
1941 | break; | |
1942 | case WIRELESS_MODE_N_24G: | |
1943 | case WIRELESS_MODE_N_5G: | |
1944 | ratr_index = RATR_INX_WIRELESS_NGB; | |
1945 | ||
1946 | if (mimo_ps == IEEE80211_SMPS_STATIC) { | |
1947 | if (rssi_level == 1) | |
1948 | ratr_bitmap &= 0x00070000; | |
1949 | else if (rssi_level == 2) | |
1950 | ratr_bitmap &= 0x0007f000; | |
1951 | else | |
1952 | ratr_bitmap &= 0x0007f005; | |
1953 | } else { | |
1954 | if (rtlphy->rf_type == RF_1T2R || | |
1955 | rtlphy->rf_type == RF_1T1R) { | |
1956 | if (curtxbw_40mhz) { | |
1957 | if (rssi_level == 1) | |
1958 | ratr_bitmap &= 0x000f0000; | |
1959 | else if (rssi_level == 2) | |
1960 | ratr_bitmap &= 0x000ff000; | |
1961 | else | |
1962 | ratr_bitmap &= 0x000ff015; | |
1963 | } else { | |
1964 | if (rssi_level == 1) | |
1965 | ratr_bitmap &= 0x000f0000; | |
1966 | else if (rssi_level == 2) | |
1967 | ratr_bitmap &= 0x000ff000; | |
1968 | else | |
1969 | ratr_bitmap &= 0x000ff005; | |
1970 | } | |
1971 | } else { | |
1972 | if (curtxbw_40mhz) { | |
1973 | if (rssi_level == 1) | |
1974 | ratr_bitmap &= 0x0f0f0000; | |
1975 | else if (rssi_level == 2) | |
1976 | ratr_bitmap &= 0x0f0ff000; | |
1977 | else | |
1978 | ratr_bitmap &= 0x0f0ff015; | |
1979 | } else { | |
1980 | if (rssi_level == 1) | |
1981 | ratr_bitmap &= 0x0f0f0000; | |
1982 | else if (rssi_level == 2) | |
1983 | ratr_bitmap &= 0x0f0ff000; | |
1984 | else | |
1985 | ratr_bitmap &= 0x0f0ff005; | |
1986 | } | |
1987 | } | |
1988 | } | |
1989 | ||
1990 | if ((curtxbw_40mhz && curshortgi_40mhz) || | |
1991 | (!curtxbw_40mhz && curshortgi_20mhz)) { | |
1992 | if (macid == 0) | |
1993 | shortgi = true; | |
1994 | else if (macid == 1) | |
1995 | shortgi = false; | |
1996 | } | |
1997 | break; | |
1998 | default: | |
1999 | ratr_index = RATR_INX_WIRELESS_NGB; | |
2000 | ||
2001 | if (rtlphy->rf_type == RF_1T2R) | |
2002 | ratr_bitmap &= 0x000ff0ff; | |
2003 | else | |
2004 | ratr_bitmap &= 0x0f0ff0ff; | |
2005 | break; | |
2006 | } | |
2007 | sta_entry->ratr_index = ratr_index; | |
2008 | ||
2009 | RT_TRACE(rtlpriv, COMP_RATR, DBG_DMESG, | |
2010 | "ratr_bitmap :%x\n", ratr_bitmap); | |
2011 | /* convert ratr_bitmap to le byte array */ | |
2012 | rate_mask[0] = ratr_bitmap; | |
2013 | rate_mask[1] = (ratr_bitmap >>= 8); | |
2014 | rate_mask[2] = (ratr_bitmap >>= 8); | |
2015 | rate_mask[3] = ((ratr_bitmap >> 8) & 0x0f) | (ratr_index << 4); | |
2016 | rate_mask[4] = macid | (shortgi ? 0x20 : 0x00) | 0x80; | |
2017 | RT_TRACE(rtlpriv, COMP_RATR, DBG_DMESG, | |
2018 | "Rate_index:%x, ratr_bitmap: %*phC\n", | |
2019 | ratr_index, 5, rate_mask); | |
2020 | rtl8723ae_fill_h2c_cmd(hw, H2C_RA_MASK, 5, rate_mask); | |
2021 | } | |
2022 | ||
2023 | void rtl8723ae_update_hal_rate_tbl(struct ieee80211_hw *hw, | |
2024 | struct ieee80211_sta *sta, u8 rssi_level) | |
2025 | { | |
2026 | struct rtl_priv *rtlpriv = rtl_priv(hw); | |
2027 | ||
2028 | if (rtlpriv->dm.useramask) | |
2029 | rtl8723ae_update_hal_rate_mask(hw, sta, rssi_level); | |
2030 | else | |
2031 | rtl8723ae_update_hal_rate_table(hw, sta); | |
2032 | } | |
2033 | ||
2034 | void rtl8723ae_update_channel_access_setting(struct ieee80211_hw *hw) | |
2035 | { | |
2036 | struct rtl_priv *rtlpriv = rtl_priv(hw); | |
2037 | struct rtl_mac *mac = rtl_mac(rtl_priv(hw)); | |
2038 | u16 sifs_timer; | |
2039 | ||
2040 | rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_SLOT_TIME, | |
2041 | (u8 *)&mac->slot_time); | |
2042 | if (!mac->ht_enable) | |
2043 | sifs_timer = 0x0a0a; | |
2044 | else | |
2045 | sifs_timer = 0x1010; | |
2046 | rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_SIFS, (u8 *)&sifs_timer); | |
2047 | } | |
2048 | ||
2049 | bool rtl8723ae_gpio_radio_on_off_checking(struct ieee80211_hw *hw, u8 *valid) | |
2050 | { | |
2051 | struct rtl_priv *rtlpriv = rtl_priv(hw); | |
2052 | struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw)); | |
2053 | struct rtl_phy *rtlphy = &(rtlpriv->phy); | |
b26f5f09 | 2054 | enum rf_pwrstate e_rfpowerstate_toset; |
c592e631 LF |
2055 | u8 u1tmp; |
2056 | bool actuallyset = false; | |
2057 | ||
2058 | if (rtlpriv->rtlhal.being_init_adapter) | |
2059 | return false; | |
2060 | ||
2061 | if (ppsc->swrf_processing) | |
2062 | return false; | |
2063 | ||
2064 | spin_lock(&rtlpriv->locks.rf_ps_lock); | |
2065 | if (ppsc->rfchange_inprogress) { | |
2066 | spin_unlock(&rtlpriv->locks.rf_ps_lock); | |
2067 | return false; | |
2068 | } else { | |
2069 | ppsc->rfchange_inprogress = true; | |
2070 | spin_unlock(&rtlpriv->locks.rf_ps_lock); | |
2071 | } | |
2072 | ||
c592e631 LF |
2073 | rtl_write_byte(rtlpriv, REG_GPIO_IO_SEL_2, |
2074 | rtl_read_byte(rtlpriv, REG_GPIO_IO_SEL_2)&~(BIT(1))); | |
2075 | ||
2076 | u1tmp = rtl_read_byte(rtlpriv, REG_GPIO_PIN_CTRL_2); | |
2077 | ||
2078 | if (rtlphy->polarity_ctl) | |
2079 | e_rfpowerstate_toset = (u1tmp & BIT(1)) ? ERFOFF : ERFON; | |
2080 | else | |
2081 | e_rfpowerstate_toset = (u1tmp & BIT(1)) ? ERFON : ERFOFF; | |
2082 | ||
2083 | if ((ppsc->hwradiooff == true) && (e_rfpowerstate_toset == ERFON)) { | |
2084 | RT_TRACE(rtlpriv, COMP_RF, DBG_DMESG, | |
2085 | "GPIOChangeRF - HW Radio ON, RF ON\n"); | |
2086 | ||
2087 | e_rfpowerstate_toset = ERFON; | |
2088 | ppsc->hwradiooff = false; | |
2089 | actuallyset = true; | |
2090 | } else if ((ppsc->hwradiooff == false) | |
2091 | && (e_rfpowerstate_toset == ERFOFF)) { | |
2092 | RT_TRACE(rtlpriv, COMP_RF, DBG_DMESG, | |
2093 | "GPIOChangeRF - HW Radio OFF, RF OFF\n"); | |
2094 | ||
2095 | e_rfpowerstate_toset = ERFOFF; | |
2096 | ppsc->hwradiooff = true; | |
2097 | actuallyset = true; | |
2098 | } | |
2099 | ||
2100 | if (actuallyset) { | |
2101 | spin_lock(&rtlpriv->locks.rf_ps_lock); | |
2102 | ppsc->rfchange_inprogress = false; | |
2103 | spin_unlock(&rtlpriv->locks.rf_ps_lock); | |
2104 | } else { | |
2105 | if (ppsc->reg_rfps_level & RT_RF_OFF_LEVL_HALT_NIC) | |
2106 | RT_SET_PS_LEVEL(ppsc, RT_RF_OFF_LEVL_HALT_NIC); | |
2107 | ||
2108 | spin_lock(&rtlpriv->locks.rf_ps_lock); | |
2109 | ppsc->rfchange_inprogress = false; | |
2110 | spin_unlock(&rtlpriv->locks.rf_ps_lock); | |
2111 | } | |
2112 | ||
2113 | *valid = 1; | |
2114 | return !ppsc->hwradiooff; | |
2115 | } | |
2116 | ||
2117 | void rtl8723ae_set_key(struct ieee80211_hw *hw, u32 key_index, | |
2118 | u8 *p_macaddr, bool is_group, u8 enc_algo, | |
2119 | bool is_wepkey, bool clear_all) | |
2120 | { | |
2121 | struct rtl_priv *rtlpriv = rtl_priv(hw); | |
2122 | struct rtl_mac *mac = rtl_mac(rtl_priv(hw)); | |
2123 | struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw)); | |
2124 | u8 *macaddr = p_macaddr; | |
2125 | u32 entry_id = 0; | |
2126 | bool is_pairwise = false; | |
2127 | static u8 cam_const_addr[4][6] = { | |
2128 | {0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, | |
2129 | {0x00, 0x00, 0x00, 0x00, 0x00, 0x01}, | |
2130 | {0x00, 0x00, 0x00, 0x00, 0x00, 0x02}, | |
2131 | {0x00, 0x00, 0x00, 0x00, 0x00, 0x03} | |
2132 | }; | |
2133 | static u8 cam_const_broad[] = { | |
2134 | 0xff, 0xff, 0xff, 0xff, 0xff, 0xff | |
2135 | }; | |
2136 | ||
2137 | if (clear_all) { | |
2138 | u8 idx = 0; | |
2139 | u8 cam_offset = 0; | |
2140 | u8 clear_number = 5; | |
2141 | ||
2142 | RT_TRACE(rtlpriv, COMP_SEC, DBG_DMESG, "clear_all\n"); | |
2143 | ||
2144 | for (idx = 0; idx < clear_number; idx++) { | |
2145 | rtl_cam_mark_invalid(hw, cam_offset + idx); | |
2146 | rtl_cam_empty_entry(hw, cam_offset + idx); | |
2147 | ||
2148 | if (idx < 5) { | |
2149 | memset(rtlpriv->sec.key_buf[idx], 0, | |
2150 | MAX_KEY_LEN); | |
2151 | rtlpriv->sec.key_len[idx] = 0; | |
2152 | } | |
2153 | } | |
2154 | } else { | |
2155 | switch (enc_algo) { | |
2156 | case WEP40_ENCRYPTION: | |
2157 | enc_algo = CAM_WEP40; | |
2158 | break; | |
2159 | case WEP104_ENCRYPTION: | |
2160 | enc_algo = CAM_WEP104; | |
2161 | break; | |
2162 | case TKIP_ENCRYPTION: | |
2163 | enc_algo = CAM_TKIP; | |
2164 | break; | |
2165 | case AESCCMP_ENCRYPTION: | |
2166 | enc_algo = CAM_AES; | |
2167 | break; | |
2168 | default: | |
2169 | RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG, | |
2170 | "switch case not processed\n"); | |
2171 | enc_algo = CAM_TKIP; | |
2172 | break; | |
2173 | } | |
2174 | ||
2175 | if (is_wepkey || rtlpriv->sec.use_defaultkey) { | |
2176 | macaddr = cam_const_addr[key_index]; | |
2177 | entry_id = key_index; | |
2178 | } else { | |
2179 | if (is_group) { | |
2180 | macaddr = cam_const_broad; | |
2181 | entry_id = key_index; | |
2182 | } else { | |
2183 | if (mac->opmode == NL80211_IFTYPE_AP) { | |
2184 | entry_id = rtl_cam_get_free_entry(hw, | |
2185 | macaddr); | |
2186 | if (entry_id >= TOTAL_CAM_ENTRY) { | |
2187 | RT_TRACE(rtlpriv, COMP_SEC, | |
2188 | DBG_EMERG, | |
2189 | "Can not find free hw security cam entry\n"); | |
2190 | return; | |
2191 | } | |
2192 | } else { | |
2193 | entry_id = CAM_PAIRWISE_KEY_POSITION; | |
2194 | } | |
2195 | ||
2196 | key_index = PAIRWISE_KEYIDX; | |
2197 | is_pairwise = true; | |
2198 | } | |
2199 | } | |
2200 | ||
2201 | if (rtlpriv->sec.key_len[key_index] == 0) { | |
2202 | RT_TRACE(rtlpriv, COMP_SEC, DBG_DMESG, | |
2203 | "delete one entry, entry_id is %d\n", | |
2204 | entry_id); | |
2205 | if (mac->opmode == NL80211_IFTYPE_AP) | |
2206 | rtl_cam_del_entry(hw, p_macaddr); | |
2207 | rtl_cam_delete_one_entry(hw, p_macaddr, entry_id); | |
2208 | } else { | |
2209 | RT_TRACE(rtlpriv, COMP_SEC, DBG_DMESG, | |
2210 | "add one entry\n"); | |
2211 | if (is_pairwise) { | |
2212 | RT_TRACE(rtlpriv, COMP_SEC, DBG_DMESG, | |
2213 | "set Pairwiase key\n"); | |
2214 | ||
2215 | rtl_cam_add_one_entry(hw, macaddr, key_index, | |
2216 | entry_id, enc_algo, | |
2217 | CAM_CONFIG_NO_USEDK, | |
2218 | rtlpriv->sec.key_buf[key_index]); | |
2219 | } else { | |
2220 | RT_TRACE(rtlpriv, COMP_SEC, DBG_DMESG, | |
2221 | "set group key\n"); | |
2222 | ||
2223 | if (mac->opmode == NL80211_IFTYPE_ADHOC) { | |
2224 | rtl_cam_add_one_entry(hw, | |
2225 | rtlefuse->dev_addr, | |
2226 | PAIRWISE_KEYIDX, | |
2227 | CAM_PAIRWISE_KEY_POSITION, | |
2228 | enc_algo, | |
2229 | CAM_CONFIG_NO_USEDK, | |
2230 | rtlpriv->sec.key_buf | |
2231 | [entry_id]); | |
2232 | } | |
2233 | ||
2234 | rtl_cam_add_one_entry(hw, macaddr, key_index, | |
2235 | entry_id, enc_algo, | |
2236 | CAM_CONFIG_NO_USEDK, | |
2237 | rtlpriv->sec.key_buf[entry_id]); | |
2238 | } | |
2239 | ||
2240 | } | |
2241 | } | |
2242 | } | |
2243 | ||
2244 | static void rtl8723ae_bt_var_init(struct ieee80211_hw *hw) | |
2245 | { | |
2246 | struct rtl_pci_priv *pcipriv = rtl_pcipriv(hw); | |
2247 | struct rtl_priv *rtlpriv = rtl_priv(hw); | |
2248 | ||
2249 | pcipriv->bt_coexist.bt_coexistence = | |
2250 | pcipriv->bt_coexist.eeprom_bt_coexist; | |
2251 | pcipriv->bt_coexist.bt_ant_num = | |
2252 | pcipriv->bt_coexist.eeprom_bt_ant_num; | |
2253 | pcipriv->bt_coexist.bt_coexist_type = | |
2254 | pcipriv->bt_coexist.eeprom_bt_type; | |
2255 | ||
2256 | pcipriv->bt_coexist.bt_ant_isolation = | |
2257 | pcipriv->bt_coexist.eeprom_bt_ant_isol; | |
2258 | ||
2259 | pcipriv->bt_coexist.bt_radio_shared_type = | |
2260 | pcipriv->bt_coexist.eeprom_bt_radio_shared; | |
2261 | ||
2262 | RT_TRACE(rtlpriv, COMP_BT_COEXIST, DBG_TRACE, | |
2263 | "BT Coexistance = 0x%x\n", | |
2264 | pcipriv->bt_coexist.bt_coexistence); | |
2265 | ||
2266 | if (pcipriv->bt_coexist.bt_coexistence) { | |
2267 | pcipriv->bt_coexist.bt_busy_traffic = false; | |
2268 | pcipriv->bt_coexist.bt_traffic_mode_set = false; | |
2269 | pcipriv->bt_coexist.bt_non_traffic_mode_set = false; | |
2270 | ||
2271 | pcipriv->bt_coexist.cstate = 0; | |
2272 | pcipriv->bt_coexist.previous_state = 0; | |
2273 | ||
2274 | if (pcipriv->bt_coexist.bt_ant_num == ANT_X2) { | |
2275 | RT_TRACE(rtlpriv, COMP_BT_COEXIST, DBG_TRACE, | |
2276 | "BlueTooth BT_Ant_Num = Antx2\n"); | |
2277 | } else if (pcipriv->bt_coexist.bt_ant_num == ANT_X1) { | |
2278 | RT_TRACE(rtlpriv, COMP_BT_COEXIST, DBG_TRACE, | |
2279 | "BlueTooth BT_Ant_Num = Antx1\n"); | |
2280 | } | |
2281 | ||
2282 | switch (pcipriv->bt_coexist.bt_coexist_type) { | |
2283 | case BT_2WIRE: | |
2284 | RT_TRACE(rtlpriv, COMP_BT_COEXIST, DBG_TRACE, | |
2285 | "BlueTooth BT_CoexistType = BT_2Wire\n"); | |
2286 | break; | |
2287 | case BT_ISSC_3WIRE: | |
2288 | RT_TRACE(rtlpriv, COMP_BT_COEXIST, DBG_TRACE, | |
2289 | "BlueTooth BT_CoexistType = BT_ISSC_3Wire\n"); | |
2290 | break; | |
2291 | case BT_ACCEL: | |
2292 | RT_TRACE(rtlpriv, COMP_BT_COEXIST, DBG_TRACE, | |
2293 | "BlueTooth BT_CoexistType = BT_ACCEL\n"); | |
2294 | break; | |
2295 | case BT_CSR_BC4: | |
2296 | RT_TRACE(rtlpriv, COMP_BT_COEXIST, DBG_TRACE, | |
2297 | "BlueTooth BT_CoexistType = BT_CSR_BC4\n"); | |
2298 | break; | |
2299 | case BT_CSR_BC8: | |
2300 | RT_TRACE(rtlpriv, COMP_BT_COEXIST, DBG_TRACE, | |
2301 | "BlueTooth BT_CoexistType = BT_CSR_BC8\n"); | |
2302 | break; | |
2303 | case BT_RTL8756: | |
2304 | RT_TRACE(rtlpriv, COMP_BT_COEXIST, DBG_TRACE, | |
2305 | "BlueTooth BT_CoexistType = BT_RTL8756\n"); | |
2306 | break; | |
2307 | default: | |
2308 | RT_TRACE(rtlpriv, COMP_BT_COEXIST, DBG_TRACE, | |
2309 | "BlueTooth BT_CoexistType = Unknown\n"); | |
2310 | break; | |
2311 | } | |
2312 | RT_TRACE(rtlpriv, COMP_BT_COEXIST, DBG_TRACE, | |
2313 | "BlueTooth BT_Ant_isolation = %d\n", | |
2314 | pcipriv->bt_coexist.bt_ant_isolation); | |
2315 | RT_TRACE(rtlpriv, COMP_BT_COEXIST, DBG_TRACE, | |
2316 | "BT_RadioSharedType = 0x%x\n", | |
2317 | pcipriv->bt_coexist.bt_radio_shared_type); | |
2318 | pcipriv->bt_coexist.bt_active_zero_cnt = 0; | |
2319 | pcipriv->bt_coexist.cur_bt_disabled = false; | |
2320 | pcipriv->bt_coexist.pre_bt_disabled = false; | |
2321 | } | |
2322 | } | |
2323 | ||
2324 | void rtl8723ae_read_bt_coexist_info_from_hwpg(struct ieee80211_hw *hw, | |
2325 | bool auto_load_fail, u8 *hwinfo) | |
2326 | { | |
2327 | struct rtl_pci_priv *pcipriv = rtl_pcipriv(hw); | |
2328 | struct rtl_priv *rtlpriv = rtl_priv(hw); | |
2329 | u8 value; | |
2330 | u32 tmpu_32; | |
2331 | ||
2332 | if (!auto_load_fail) { | |
2333 | tmpu_32 = rtl_read_dword(rtlpriv, REG_MULTI_FUNC_CTRL); | |
2334 | if (tmpu_32 & BIT(18)) | |
2335 | pcipriv->bt_coexist.eeprom_bt_coexist = 1; | |
2336 | else | |
2337 | pcipriv->bt_coexist.eeprom_bt_coexist = 0; | |
2338 | value = hwinfo[RF_OPTION4]; | |
2339 | pcipriv->bt_coexist.eeprom_bt_type = BT_RTL8723A; | |
2340 | pcipriv->bt_coexist.eeprom_bt_ant_num = (value & 0x1); | |
2341 | pcipriv->bt_coexist.eeprom_bt_ant_isol = ((value & 0x10) >> 4); | |
2342 | pcipriv->bt_coexist.eeprom_bt_radio_shared = | |
2343 | ((value & 0x20) >> 5); | |
2344 | } else { | |
2345 | pcipriv->bt_coexist.eeprom_bt_coexist = 0; | |
2346 | pcipriv->bt_coexist.eeprom_bt_type = BT_RTL8723A; | |
2347 | pcipriv->bt_coexist.eeprom_bt_ant_num = ANT_X2; | |
2348 | pcipriv->bt_coexist.eeprom_bt_ant_isol = 0; | |
2349 | pcipriv->bt_coexist.eeprom_bt_radio_shared = BT_RADIO_SHARED; | |
2350 | } | |
2351 | ||
2352 | rtl8723ae_bt_var_init(hw); | |
2353 | } | |
2354 | ||
2355 | void rtl8723ae_bt_reg_init(struct ieee80211_hw *hw) | |
2356 | { | |
2357 | struct rtl_pci_priv *pcipriv = rtl_pcipriv(hw); | |
2358 | ||
2359 | /* 0:Low, 1:High, 2:From Efuse. */ | |
2360 | pcipriv->bt_coexist.reg_bt_iso = 2; | |
2361 | /* 0:Idle, 1:None-SCO, 2:SCO, 3:From Counter. */ | |
2362 | pcipriv->bt_coexist.reg_bt_sco = 3; | |
2363 | /* 0:Disable BT control A-MPDU, 1:Enable BT control A-MPDU. */ | |
2364 | pcipriv->bt_coexist.reg_bt_sco = 0; | |
2365 | } | |
2366 | ||
2367 | ||
2368 | void rtl8723ae_bt_hw_init(struct ieee80211_hw *hw) | |
2369 | { | |
2370 | } | |
2371 | ||
2372 | void rtl8723ae_suspend(struct ieee80211_hw *hw) | |
2373 | { | |
2374 | } | |
2375 | ||
2376 | void rtl8723ae_resume(struct ieee80211_hw *hw) | |
2377 | { | |
2378 | } | |
2379 | ||
2380 | /* Turn on AAP (RCR:bit 0) for promicuous mode. */ | |
2381 | void rtl8723ae_allow_all_destaddr(struct ieee80211_hw *hw, | |
2382 | bool allow_all_da, bool write_into_reg) | |
2383 | { | |
2384 | struct rtl_priv *rtlpriv = rtl_priv(hw); | |
2385 | struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw)); | |
2386 | ||
2387 | if (allow_all_da) /* Set BIT0 */ | |
2388 | rtlpci->receive_config |= RCR_AAP; | |
2389 | else /* Clear BIT0 */ | |
2390 | rtlpci->receive_config &= ~RCR_AAP; | |
2391 | ||
2392 | if (write_into_reg) | |
2393 | rtl_write_dword(rtlpriv, REG_RCR, rtlpci->receive_config); | |
2394 | ||
2395 | ||
2396 | RT_TRACE(rtlpriv, COMP_TURBO | COMP_INIT, DBG_LOUD, | |
2397 | "receive_config=0x%08X, write_into_reg=%d\n", | |
2398 | rtlpci->receive_config, write_into_reg); | |
2399 | } |