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1 | /****************************************************************************** |
2 | * | |
3 | * Copyright(c) 2009-2014 Realtek Corporation. | |
4 | * | |
5 | * This program is free software; you can redistribute it and/or modify it | |
6 | * under the terms of version 2 of the GNU General Public License as | |
7 | * published by the Free Software Foundation. | |
8 | * | |
9 | * This program is distributed in the hope that it will be useful, but WITHOUT | |
10 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
11 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | |
12 | * more details. | |
13 | * | |
14 | * The full GNU General Public License is included in this distribution in the | |
15 | * file called LICENSE. | |
16 | * | |
17 | * Contact Information: | |
18 | * wlanfae <wlanfae@realtek.com> | |
19 | * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park, | |
20 | * Hsinchu 300, Taiwan. | |
21 | * | |
22 | * Larry Finger <Larry.Finger@lwfinger.net> | |
23 | * | |
24 | *****************************************************************************/ | |
25 | ||
26 | #include "../wifi.h" | |
27 | #include "reg.h" | |
28 | #include "def.h" | |
29 | #include "phy.h" | |
30 | #include "rf.h" | |
31 | #include "dm.h" | |
32 | ||
33 | static bool _rtl8723be_phy_rf6052_config_parafile(struct ieee80211_hw *hw); | |
34 | ||
35 | void rtl8723be_phy_rf6052_set_bandwidth(struct ieee80211_hw *hw, u8 bandwidth) | |
36 | { | |
37 | struct rtl_priv *rtlpriv = rtl_priv(hw); | |
38 | struct rtl_phy *rtlphy = &(rtlpriv->phy); | |
39 | ||
40 | switch (bandwidth) { | |
41 | case HT_CHANNEL_WIDTH_20: | |
42 | rtlphy->rfreg_chnlval[0] = ((rtlphy->rfreg_chnlval[0] & | |
43 | 0xfffff3ff) | BIT(10) | BIT(11)); | |
44 | rtl_set_rfreg(hw, RF90_PATH_A, RF_CHNLBW, RFREG_OFFSET_MASK, | |
45 | rtlphy->rfreg_chnlval[0]); | |
46 | break; | |
47 | case HT_CHANNEL_WIDTH_20_40: | |
48 | rtlphy->rfreg_chnlval[0] = ((rtlphy->rfreg_chnlval[0] & | |
49 | 0xfffff3ff) | BIT(10)); | |
50 | rtl_set_rfreg(hw, RF90_PATH_A, RF_CHNLBW, RFREG_OFFSET_MASK, | |
51 | rtlphy->rfreg_chnlval[0]); | |
52 | break; | |
53 | default: | |
54 | RT_TRACE(rtlpriv, COMP_INIT, DBG_EMERG, | |
55 | "unknown bandwidth: %#X\n", bandwidth); | |
56 | break; | |
57 | } | |
58 | } | |
59 | ||
60 | void rtl8723be_phy_rf6052_set_cck_txpower(struct ieee80211_hw *hw, | |
61 | u8 *ppowerlevel) | |
62 | { | |
63 | struct rtl_priv *rtlpriv = rtl_priv(hw); | |
64 | struct rtl_phy *rtlphy = &(rtlpriv->phy); | |
65 | struct rtl_mac *mac = rtl_mac(rtl_priv(hw)); | |
66 | struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw)); | |
67 | u32 tx_agc[2] = {0, 0}, tmpval; | |
68 | bool turbo_scanoff = false; | |
69 | u8 idx1, idx2; | |
70 | u8 *ptr; | |
71 | u8 direction; | |
72 | u32 pwrtrac_value; | |
73 | ||
74 | if (rtlefuse->eeprom_regulatory != 0) | |
75 | turbo_scanoff = true; | |
76 | ||
77 | if (mac->act_scanning) { | |
78 | tx_agc[RF90_PATH_A] = 0x3f3f3f3f; | |
79 | tx_agc[RF90_PATH_B] = 0x3f3f3f3f; | |
80 | ||
81 | if (turbo_scanoff) { | |
82 | for (idx1 = RF90_PATH_A; idx1 <= RF90_PATH_B; idx1++) { | |
83 | tx_agc[idx1] = ppowerlevel[idx1] | | |
84 | (ppowerlevel[idx1] << 8) | | |
85 | (ppowerlevel[idx1] << 16) | | |
86 | (ppowerlevel[idx1] << 24); | |
87 | } | |
88 | } | |
89 | } else { | |
90 | for (idx1 = RF90_PATH_A; idx1 <= RF90_PATH_B; idx1++) { | |
91 | tx_agc[idx1] = ppowerlevel[idx1] | | |
92 | (ppowerlevel[idx1] << 8) | | |
93 | (ppowerlevel[idx1] << 16) | | |
94 | (ppowerlevel[idx1] << 24); | |
95 | } | |
96 | if (rtlefuse->eeprom_regulatory == 0) { | |
97 | tmpval = | |
98 | (rtlphy->mcs_offset[0][6]) + | |
99 | (rtlphy->mcs_offset[0][7] << 8); | |
100 | tx_agc[RF90_PATH_A] += tmpval; | |
101 | ||
102 | tmpval = (rtlphy->mcs_offset[0][14]) + | |
103 | (rtlphy->mcs_offset[0][15] << | |
104 | 24); | |
105 | tx_agc[RF90_PATH_B] += tmpval; | |
106 | } | |
107 | } | |
108 | for (idx1 = RF90_PATH_A; idx1 <= RF90_PATH_B; idx1++) { | |
109 | ptr = (u8 *)(&(tx_agc[idx1])); | |
110 | for (idx2 = 0; idx2 < 4; idx2++) { | |
111 | if (*ptr > RF6052_MAX_TX_PWR) | |
112 | *ptr = RF6052_MAX_TX_PWR; | |
113 | ptr++; | |
114 | } | |
115 | } | |
116 | rtl8723be_dm_txpower_track_adjust(hw, 1, &direction, &pwrtrac_value); | |
117 | if (direction == 1) { | |
118 | tx_agc[0] += pwrtrac_value; | |
119 | tx_agc[1] += pwrtrac_value; | |
120 | } else if (direction == 2) { | |
121 | tx_agc[0] -= pwrtrac_value; | |
122 | tx_agc[1] -= pwrtrac_value; | |
123 | } | |
124 | tmpval = tx_agc[RF90_PATH_A] & 0xff; | |
125 | rtl_set_bbreg(hw, RTXAGC_A_CCK1_MCS32, MASKBYTE1, tmpval); | |
126 | ||
127 | RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, | |
128 | "CCK PWR 1M (rf-A) = 0x%x (reg 0x%x)\n", tmpval, | |
129 | RTXAGC_A_CCK1_MCS32); | |
130 | ||
131 | tmpval = tx_agc[RF90_PATH_A] >> 8; | |
132 | ||
133 | rtl_set_bbreg(hw, RTXAGC_B_CCK11_A_CCK2_11, 0xffffff00, tmpval); | |
134 | ||
135 | RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, | |
136 | "CCK PWR 2~11M (rf-A) = 0x%x (reg 0x%x)\n", tmpval, | |
137 | RTXAGC_B_CCK11_A_CCK2_11); | |
138 | ||
139 | tmpval = tx_agc[RF90_PATH_B] >> 24; | |
140 | rtl_set_bbreg(hw, RTXAGC_B_CCK11_A_CCK2_11, MASKBYTE0, tmpval); | |
141 | ||
142 | RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, | |
143 | "CCK PWR 11M (rf-B) = 0x%x (reg 0x%x)\n", tmpval, | |
144 | RTXAGC_B_CCK11_A_CCK2_11); | |
145 | ||
146 | tmpval = tx_agc[RF90_PATH_B] & 0x00ffffff; | |
147 | rtl_set_bbreg(hw, RTXAGC_B_CCK1_55_MCS32, 0xffffff00, tmpval); | |
148 | ||
149 | RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, | |
150 | "CCK PWR 1~5.5M (rf-B) = 0x%x (reg 0x%x)\n", tmpval, | |
151 | RTXAGC_B_CCK1_55_MCS32); | |
152 | } | |
153 | ||
154 | static void rtl8723be_phy_get_power_base(struct ieee80211_hw *hw, | |
155 | u8 *ppowerlevel_ofdm, | |
156 | u8 *ppowerlevel_bw20, | |
157 | u8 *ppowerlevel_bw40, | |
158 | u8 channel, u32 *ofdmbase, | |
159 | u32 *mcsbase) | |
160 | { | |
161 | struct rtl_priv *rtlpriv = rtl_priv(hw); | |
162 | struct rtl_phy *rtlphy = &(rtlpriv->phy); | |
163 | u32 powerbase0, powerbase1; | |
164 | u8 i, powerlevel[2]; | |
165 | ||
166 | for (i = 0; i < 2; i++) { | |
167 | powerbase0 = ppowerlevel_ofdm[i]; | |
168 | ||
169 | powerbase0 = (powerbase0 << 24) | (powerbase0 << 16) | | |
170 | (powerbase0 << 8) | powerbase0; | |
171 | *(ofdmbase + i) = powerbase0; | |
172 | RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, | |
173 | " [OFDM power base index rf(%c) = 0x%x]\n", | |
174 | ((i == 0) ? 'A' : 'B'), *(ofdmbase + i)); | |
175 | } | |
176 | ||
177 | for (i = 0; i < 2; i++) { | |
178 | if (rtlphy->current_chan_bw == HT_CHANNEL_WIDTH_20) | |
179 | powerlevel[i] = ppowerlevel_bw20[i]; | |
180 | else | |
181 | powerlevel[i] = ppowerlevel_bw40[i]; | |
182 | powerbase1 = powerlevel[i]; | |
183 | powerbase1 = (powerbase1 << 24) | (powerbase1 << 16) | | |
184 | (powerbase1 << 8) | powerbase1; | |
185 | ||
186 | *(mcsbase + i) = powerbase1; | |
187 | ||
188 | RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, | |
189 | " [MCS power base index rf(%c) = 0x%x]\n", | |
190 | ((i == 0) ? 'A' : 'B'), *(mcsbase + i)); | |
191 | } | |
192 | } | |
193 | ||
194 | static void txpwr_by_regulatory(struct ieee80211_hw *hw, u8 channel, u8 index, | |
195 | u32 *powerbase0, u32 *powerbase1, | |
196 | u32 *p_outwriteval) | |
197 | { | |
198 | struct rtl_priv *rtlpriv = rtl_priv(hw); | |
199 | struct rtl_phy *rtlphy = &(rtlpriv->phy); | |
200 | struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw)); | |
201 | u8 i, chnlgroup = 0, pwr_diff_limit[4]; | |
202 | u8 pwr_diff = 0, customer_pwr_diff; | |
203 | u32 writeval, customer_limit, rf; | |
204 | ||
205 | for (rf = 0; rf < 2; rf++) { | |
206 | switch (rtlefuse->eeprom_regulatory) { | |
207 | case 0: | |
208 | chnlgroup = 0; | |
209 | ||
210 | writeval = | |
211 | rtlphy->mcs_offset[chnlgroup][index + (rf ? 8 : 0)] | |
212 | + ((index < 2) ? powerbase0[rf] : powerbase1[rf]); | |
213 | ||
214 | RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, | |
215 | "RTK better performance, " | |
216 | "writeval(%c) = 0x%x\n", | |
217 | ((rf == 0) ? 'A' : 'B'), writeval); | |
218 | break; | |
219 | case 1: | |
220 | if (rtlphy->pwrgroup_cnt == 1) { | |
221 | chnlgroup = 0; | |
222 | } else { | |
223 | if (channel < 3) | |
224 | chnlgroup = 0; | |
225 | else if (channel < 6) | |
226 | chnlgroup = 1; | |
227 | else if (channel < 9) | |
228 | chnlgroup = 2; | |
229 | else if (channel < 12) | |
230 | chnlgroup = 3; | |
231 | else if (channel < 14) | |
232 | chnlgroup = 4; | |
233 | else if (channel == 14) | |
234 | chnlgroup = 5; | |
235 | } | |
236 | writeval = rtlphy->mcs_offset[chnlgroup] | |
237 | [index + (rf ? 8 : 0)] + ((index < 2) ? | |
238 | powerbase0[rf] : | |
239 | powerbase1[rf]); | |
240 | ||
241 | RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, | |
242 | "Realtek regulatory, 20MHz, " | |
243 | "writeval(%c) = 0x%x\n", | |
244 | ((rf == 0) ? 'A' : 'B'), writeval); | |
245 | ||
246 | break; | |
247 | case 2: | |
248 | writeval = | |
249 | ((index < 2) ? powerbase0[rf] : powerbase1[rf]); | |
250 | ||
251 | RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, | |
252 | "Better regulatory, " | |
253 | "writeval(%c) = 0x%x\n", | |
254 | ((rf == 0) ? 'A' : 'B'), writeval); | |
255 | break; | |
256 | case 3: | |
257 | chnlgroup = 0; | |
258 | ||
259 | if (rtlphy->current_chan_bw == HT_CHANNEL_WIDTH_20_40) { | |
260 | RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, | |
261 | "customer's limit, 40MHz " | |
262 | "rf(%c) = 0x%x\n", | |
263 | ((rf == 0) ? 'A' : 'B'), | |
264 | rtlefuse->pwrgroup_ht40[rf] | |
265 | [channel-1]); | |
266 | } else { | |
267 | RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, | |
268 | "customer's limit, 20MHz " | |
269 | "rf(%c) = 0x%x\n", | |
270 | ((rf == 0) ? 'A' : 'B'), | |
271 | rtlefuse->pwrgroup_ht20[rf] | |
272 | [channel-1]); | |
273 | } | |
274 | ||
275 | if (index < 2) | |
276 | pwr_diff = | |
277 | rtlefuse->txpwr_legacyhtdiff[rf][channel-1]; | |
278 | else if (rtlphy->current_chan_bw == | |
279 | HT_CHANNEL_WIDTH_20) | |
280 | pwr_diff = | |
281 | rtlefuse->txpwr_ht20diff[rf][channel-1]; | |
282 | ||
283 | if (rtlphy->current_chan_bw == HT_CHANNEL_WIDTH_20_40) | |
284 | customer_pwr_diff = | |
285 | rtlefuse->pwrgroup_ht40[rf][channel-1]; | |
286 | else | |
287 | customer_pwr_diff = | |
288 | rtlefuse->pwrgroup_ht20[rf][channel-1]; | |
289 | ||
290 | if (pwr_diff > customer_pwr_diff) | |
291 | pwr_diff = 0; | |
292 | else | |
293 | pwr_diff = customer_pwr_diff - pwr_diff; | |
294 | ||
295 | for (i = 0; i < 4; i++) { | |
296 | pwr_diff_limit[i] = | |
297 | (u8)((rtlphy->mcs_offset | |
298 | [chnlgroup][index + (rf ? 8 : 0)] & | |
299 | (0x7f << (i * 8))) >> (i * 8)); | |
300 | ||
301 | if (pwr_diff_limit[i] > pwr_diff) | |
302 | pwr_diff_limit[i] = pwr_diff; | |
303 | } | |
304 | ||
305 | customer_limit = (pwr_diff_limit[3] << 24) | | |
306 | (pwr_diff_limit[2] << 16) | | |
307 | (pwr_diff_limit[1] << 8) | | |
308 | (pwr_diff_limit[0]); | |
309 | ||
310 | RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, | |
311 | "Customer's limit rf(%c) = 0x%x\n", | |
312 | ((rf == 0) ? 'A' : 'B'), customer_limit); | |
313 | ||
314 | writeval = customer_limit + ((index < 2) ? | |
315 | powerbase0[rf] : | |
316 | powerbase1[rf]); | |
317 | ||
318 | RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, | |
319 | "Customer, writeval rf(%c)= 0x%x\n", | |
320 | ((rf == 0) ? 'A' : 'B'), writeval); | |
321 | break; | |
322 | default: | |
323 | chnlgroup = 0; | |
324 | writeval = | |
325 | rtlphy->mcs_offset[chnlgroup] | |
326 | [index + (rf ? 8 : 0)] | |
327 | + ((index < 2) ? powerbase0[rf] : powerbase1[rf]); | |
328 | ||
329 | RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, | |
330 | "RTK better performance, writeval " | |
331 | "rf(%c) = 0x%x\n", | |
332 | ((rf == 0) ? 'A' : 'B'), writeval); | |
333 | break; | |
334 | } | |
335 | ||
336 | if (rtlpriv->dm.dynamic_txhighpower_lvl == TXHIGHPWRLEVEL_BT1) | |
337 | writeval = writeval - 0x06060606; | |
338 | else if (rtlpriv->dm.dynamic_txhighpower_lvl == | |
339 | TXHIGHPWRLEVEL_BT2) | |
340 | writeval = writeval - 0x0c0c0c0c; | |
341 | *(p_outwriteval + rf) = writeval; | |
342 | } | |
343 | } | |
344 | ||
345 | static void _rtl8723be_write_ofdm_power_reg(struct ieee80211_hw *hw, | |
346 | u8 index, u32 *value) | |
347 | { | |
348 | struct rtl_priv *rtlpriv = rtl_priv(hw); | |
349 | u16 regoffset_a[6] = { | |
350 | RTXAGC_A_RATE18_06, RTXAGC_A_RATE54_24, | |
351 | RTXAGC_A_MCS03_MCS00, RTXAGC_A_MCS07_MCS04, | |
352 | RTXAGC_A_MCS11_MCS08, RTXAGC_A_MCS15_MCS12 | |
353 | }; | |
354 | u16 regoffset_b[6] = { | |
355 | RTXAGC_B_RATE18_06, RTXAGC_B_RATE54_24, | |
356 | RTXAGC_B_MCS03_MCS00, RTXAGC_B_MCS07_MCS04, | |
357 | RTXAGC_B_MCS11_MCS08, RTXAGC_B_MCS15_MCS12 | |
358 | }; | |
359 | u8 i, rf, pwr_val[4]; | |
360 | u32 writeval; | |
361 | u16 regoffset; | |
362 | ||
363 | for (rf = 0; rf < 2; rf++) { | |
364 | writeval = value[rf]; | |
365 | for (i = 0; i < 4; i++) { | |
366 | pwr_val[i] = (u8) ((writeval & (0x7f << | |
367 | (i * 8))) >> (i * 8)); | |
368 | ||
369 | if (pwr_val[i] > RF6052_MAX_TX_PWR) | |
370 | pwr_val[i] = RF6052_MAX_TX_PWR; | |
371 | } | |
372 | writeval = (pwr_val[3] << 24) | (pwr_val[2] << 16) | | |
373 | (pwr_val[1] << 8) | pwr_val[0]; | |
374 | ||
375 | if (rf == 0) | |
376 | regoffset = regoffset_a[index]; | |
377 | else | |
378 | regoffset = regoffset_b[index]; | |
379 | rtl_set_bbreg(hw, regoffset, MASKDWORD, writeval); | |
380 | ||
381 | RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, | |
382 | "Set 0x%x = %08x\n", regoffset, writeval); | |
383 | } | |
384 | } | |
385 | ||
386 | void rtl8723be_phy_rf6052_set_ofdm_txpower(struct ieee80211_hw *hw, | |
387 | u8 *ppowerlevel_ofdm, | |
388 | u8 *ppowerlevel_bw20, | |
389 | u8 *ppowerlevel_bw40, u8 channel) | |
390 | { | |
391 | u32 writeval[2], powerbase0[2], powerbase1[2]; | |
392 | u8 index; | |
393 | u8 direction; | |
394 | u32 pwrtrac_value; | |
395 | ||
396 | rtl8723be_phy_get_power_base(hw, ppowerlevel_ofdm, ppowerlevel_bw20, | |
397 | ppowerlevel_bw40, channel, | |
398 | &powerbase0[0], &powerbase1[0]); | |
399 | ||
400 | rtl8723be_dm_txpower_track_adjust(hw, 1, &direction, &pwrtrac_value); | |
401 | ||
402 | for (index = 0; index < 6; index++) { | |
403 | txpwr_by_regulatory(hw, channel, index, &powerbase0[0], | |
404 | &powerbase1[0], &writeval[0]); | |
405 | if (direction == 1) { | |
406 | writeval[0] += pwrtrac_value; | |
407 | writeval[1] += pwrtrac_value; | |
408 | } else if (direction == 2) { | |
409 | writeval[0] -= pwrtrac_value; | |
410 | writeval[1] -= pwrtrac_value; | |
411 | } | |
412 | _rtl8723be_write_ofdm_power_reg(hw, index, &writeval[0]); | |
413 | } | |
414 | } | |
415 | ||
416 | bool rtl8723be_phy_rf6052_config(struct ieee80211_hw *hw) | |
417 | { | |
418 | struct rtl_priv *rtlpriv = rtl_priv(hw); | |
419 | struct rtl_phy *rtlphy = &(rtlpriv->phy); | |
420 | ||
421 | if (rtlphy->rf_type == RF_1T1R) | |
422 | rtlphy->num_total_rfpath = 1; | |
423 | else | |
424 | rtlphy->num_total_rfpath = 2; | |
425 | ||
426 | return _rtl8723be_phy_rf6052_config_parafile(hw); | |
427 | } | |
428 | ||
429 | static bool _rtl8723be_phy_rf6052_config_parafile(struct ieee80211_hw *hw) | |
430 | { | |
431 | struct rtl_priv *rtlpriv = rtl_priv(hw); | |
432 | struct rtl_phy *rtlphy = &(rtlpriv->phy); | |
433 | struct bb_reg_def *pphyreg; | |
434 | u32 u4_regvalue = 0; | |
435 | u8 rfpath; | |
436 | bool rtstatus = true; | |
437 | ||
438 | for (rfpath = 0; rfpath < rtlphy->num_total_rfpath; rfpath++) { | |
439 | pphyreg = &rtlphy->phyreg_def[rfpath]; | |
440 | ||
441 | switch (rfpath) { | |
442 | case RF90_PATH_A: | |
443 | case RF90_PATH_C: | |
444 | u4_regvalue = rtl_get_bbreg(hw, pphyreg->rfintfs, | |
445 | BRFSI_RFENV); | |
446 | break; | |
447 | case RF90_PATH_B: | |
448 | case RF90_PATH_D: | |
449 | u4_regvalue = rtl_get_bbreg(hw, pphyreg->rfintfs, | |
450 | BRFSI_RFENV << 16); | |
451 | break; | |
452 | } | |
453 | ||
454 | rtl_set_bbreg(hw, pphyreg->rfintfe, BRFSI_RFENV << 16, 0x1); | |
455 | udelay(1); | |
456 | ||
457 | rtl_set_bbreg(hw, pphyreg->rfintfo, BRFSI_RFENV, 0x1); | |
458 | udelay(1); | |
459 | ||
460 | rtl_set_bbreg(hw, pphyreg->rfhssi_para2, | |
461 | B3WIREADDREAALENGTH, 0x0); | |
462 | udelay(1); | |
463 | ||
464 | rtl_set_bbreg(hw, pphyreg->rfhssi_para2, B3WIREDATALENGTH, 0x0); | |
465 | udelay(1); | |
466 | ||
467 | switch (rfpath) { | |
468 | case RF90_PATH_A: | |
469 | rtstatus = rtl8723be_phy_config_rf_with_headerfile(hw, | |
470 | (enum radio_path)rfpath); | |
471 | break; | |
472 | case RF90_PATH_B: | |
473 | rtstatus = rtl8723be_phy_config_rf_with_headerfile(hw, | |
474 | (enum radio_path)rfpath); | |
475 | break; | |
476 | case RF90_PATH_C: | |
477 | break; | |
478 | case RF90_PATH_D: | |
479 | break; | |
480 | } | |
481 | ||
482 | switch (rfpath) { | |
483 | case RF90_PATH_A: | |
484 | case RF90_PATH_C: | |
485 | rtl_set_bbreg(hw, pphyreg->rfintfs, | |
486 | BRFSI_RFENV, u4_regvalue); | |
487 | break; | |
488 | case RF90_PATH_B: | |
489 | case RF90_PATH_D: | |
490 | rtl_set_bbreg(hw, pphyreg->rfintfs, | |
491 | BRFSI_RFENV << 16, u4_regvalue); | |
492 | break; | |
493 | } | |
494 | ||
495 | if (!rtstatus) { | |
496 | RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE, | |
497 | "Radio[%d] Fail!!", rfpath); | |
498 | return false; | |
499 | } | |
500 | } | |
501 | ||
502 | RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE, "\n"); | |
503 | return rtstatus; | |
504 | } |