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0c817338 LF |
1 | /****************************************************************************** |
2 | * | |
a8d76066 | 3 | * Copyright(c) 2009-2012 Realtek Corporation. |
0c817338 LF |
4 | * |
5 | * This program is free software; you can redistribute it and/or modify it | |
6 | * under the terms of version 2 of the GNU General Public License as | |
7 | * published by the Free Software Foundation. | |
8 | * | |
9 | * This program is distributed in the hope that it will be useful, but WITHOUT | |
10 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
11 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | |
12 | * more details. | |
13 | * | |
14 | * You should have received a copy of the GNU General Public License along with | |
15 | * this program; if not, write to the Free Software Foundation, Inc., | |
16 | * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA | |
17 | * | |
18 | * The full GNU General Public License is included in this distribution in the | |
19 | * file called LICENSE. | |
20 | * | |
21 | * Contact Information: | |
22 | * wlanfae <wlanfae@realtek.com> | |
23 | * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park, | |
24 | * Hsinchu 300, Taiwan. | |
25 | * | |
26 | * Larry Finger <Larry.Finger@lwfinger.net> | |
27 | * | |
28 | *****************************************************************************/ | |
29 | ||
30 | #ifndef __RTL_WIFI_H__ | |
31 | #define __RTL_WIFI_H__ | |
32 | ||
d273bb20 LF |
33 | #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt |
34 | ||
0c817338 LF |
35 | #include <linux/sched.h> |
36 | #include <linux/firmware.h> | |
0c817338 | 37 | #include <linux/etherdevice.h> |
b08cd667 | 38 | #include <linux/vmalloc.h> |
62e63975 | 39 | #include <linux/usb.h> |
0c817338 | 40 | #include <net/mac80211.h> |
b0302aba | 41 | #include <linux/completion.h> |
0c817338 LF |
42 | #include "debug.h" |
43 | ||
f3355dd9 LF |
44 | #define MASKBYTE0 0xff |
45 | #define MASKBYTE1 0xff00 | |
46 | #define MASKBYTE2 0xff0000 | |
47 | #define MASKBYTE3 0xff000000 | |
48 | #define MASKHWORD 0xffff0000 | |
49 | #define MASKLWORD 0x0000ffff | |
50 | #define MASKDWORD 0xffffffff | |
51 | #define MASK12BITS 0xfff | |
52 | #define MASKH4BITS 0xf0000000 | |
53 | #define MASKOFDM_D 0xffc00000 | |
54 | #define MASKCCK 0x3f3f3f3f | |
55 | ||
56 | #define MASK4BITS 0x0f | |
57 | #define MASK20BITS 0xfffff | |
58 | #define RFREG_OFFSET_MASK 0xfffff | |
59 | ||
25b13dbc LF |
60 | #define MASKBYTE0 0xff |
61 | #define MASKBYTE1 0xff00 | |
62 | #define MASKBYTE2 0xff0000 | |
63 | #define MASKBYTE3 0xff000000 | |
64 | #define MASKHWORD 0xffff0000 | |
65 | #define MASKLWORD 0x0000ffff | |
66 | #define MASKDWORD 0xffffffff | |
67 | #define MASK12BITS 0xfff | |
68 | #define MASKH4BITS 0xf0000000 | |
69 | #define MASKOFDM_D 0xffc00000 | |
70 | #define MASKCCK 0x3f3f3f3f | |
71 | ||
72 | #define MASK4BITS 0x0f | |
73 | #define MASK20BITS 0xfffff | |
74 | #define RFREG_OFFSET_MASK 0xfffff | |
75 | ||
0c817338 LF |
76 | #define RF_CHANGE_BY_INIT 0 |
77 | #define RF_CHANGE_BY_IPS BIT(28) | |
78 | #define RF_CHANGE_BY_PS BIT(29) | |
79 | #define RF_CHANGE_BY_HW BIT(30) | |
80 | #define RF_CHANGE_BY_SW BIT(31) | |
81 | ||
82 | #define IQK_ADDA_REG_NUM 16 | |
83 | #define IQK_MAC_REG_NUM 4 | |
aa45a673 | 84 | #define IQK_THRESHOLD 8 |
0c817338 LF |
85 | |
86 | #define MAX_KEY_LEN 61 | |
87 | #define KEY_BUF_SIZE 5 | |
88 | ||
89 | /* QoS related. */ | |
90 | /*aci: 0x00 Best Effort*/ | |
91 | /*aci: 0x01 Background*/ | |
92 | /*aci: 0x10 Video*/ | |
93 | /*aci: 0x11 Voice*/ | |
94 | /*Max: define total number.*/ | |
95 | #define AC0_BE 0 | |
96 | #define AC1_BK 1 | |
97 | #define AC2_VI 2 | |
98 | #define AC3_VO 3 | |
99 | #define AC_MAX 4 | |
100 | #define QOS_QUEUE_NUM 4 | |
101 | #define RTL_MAC80211_NUM_QUEUE 5 | |
ff6ff96b | 102 | #define REALTEK_USB_VENQT_MAX_BUF_SIZE 254 |
30899cc6 | 103 | #define RTL_USB_MAX_RX_COUNT 100 |
0c817338 LF |
104 | #define QBSS_LOAD_SIZE 5 |
105 | #define MAX_WMMELE_LENGTH 64 | |
106 | ||
3dad618b C |
107 | #define TOTAL_CAM_ENTRY 32 |
108 | ||
0c817338 LF |
109 | /*slot time for 11g. */ |
110 | #define RTL_SLOT_TIME_9 9 | |
111 | #define RTL_SLOT_TIME_20 20 | |
112 | ||
0c5d63f0 | 113 | /*related to tcp/ip. */ |
0c817338 LF |
114 | #define SNAP_SIZE 6 |
115 | #define PROTOC_TYPE_SIZE 2 | |
116 | ||
117 | /*related with 802.11 frame*/ | |
118 | #define MAC80211_3ADDR_LEN 24 | |
119 | #define MAC80211_4ADDR_LEN 30 | |
120 | ||
e97b775d | 121 | #define CHANNEL_MAX_NUMBER (14 + 24 + 21) /* 14 is the max channel no */ |
f3355dd9 LF |
122 | #define CHANNEL_MAX_NUMBER_2G 14 |
123 | #define CHANNEL_MAX_NUMBER_5G 54 /* Please refer to | |
124 | *"phy_GetChnlGroup8812A" and | |
125 | * "Hal_ReadTxPowerInfo8812A" | |
126 | */ | |
127 | #define CHANNEL_MAX_NUMBER_5G_80M 7 | |
e97b775d | 128 | #define CHANNEL_GROUP_MAX (3 + 9) /* ch1~3, 4~9, 10~14 = three groups */ |
f3355dd9 LF |
129 | #define CHANNEL_MAX_NUMBER_5G 54 /* Please refer to |
130 | *"phy_GetChnlGroup8812A" and | |
131 | * "Hal_ReadTxPowerInfo8812A" | |
132 | */ | |
133 | #define CHANNEL_MAX_NUMBER_5G_80M 7 | |
e97b775d LF |
134 | #define MAX_PG_GROUP 13 |
135 | #define CHANNEL_GROUP_MAX_2G 3 | |
136 | #define CHANNEL_GROUP_IDX_5GL 3 | |
137 | #define CHANNEL_GROUP_IDX_5GM 6 | |
138 | #define CHANNEL_GROUP_IDX_5GH 9 | |
139 | #define CHANNEL_GROUP_MAX_5G 9 | |
140 | #define CHANNEL_MAX_NUMBER_2G 14 | |
141 | #define AVG_THERMAL_NUM 8 | |
e6deaf81 | 142 | #define AVG_THERMAL_NUM_88E 4 |
aa45a673 | 143 | #define AVG_THERMAL_NUM_8723BE 4 |
3dad618b | 144 | #define MAX_TID_COUNT 9 |
e97b775d LF |
145 | |
146 | /* for early mode */ | |
3dad618b | 147 | #define FCS_LEN 4 |
e97b775d | 148 | #define EM_HDR_LEN 8 |
26634c4b | 149 | |
e6deaf81 LF |
150 | #define MAX_TX_COUNT 4 |
151 | #define MAX_RF_PATH 4 | |
152 | #define MAX_CHNL_GROUP_24G 6 | |
153 | #define MAX_CHNL_GROUP_5G 14 | |
154 | ||
2cddad3c LF |
155 | #define TX_PWR_BY_RATE_NUM_BAND 2 |
156 | #define TX_PWR_BY_RATE_NUM_RF 4 | |
157 | #define TX_PWR_BY_RATE_NUM_SECTION 12 | |
158 | #define MAX_BASE_NUM_IN_PHY_REG_PG_24G 6 | |
159 | #define MAX_BASE_NUM_IN_PHY_REG_PG_5G 5 | |
160 | ||
f3355dd9 LF |
161 | #define RTL8192EE_SEG_NUM 1 /* 0:2 seg, 1: 4 seg, 2: 8 seg */ |
162 | ||
163 | #define DEL_SW_IDX_SZ 30 | |
164 | #define BAND_NUM 3 | |
165 | ||
2cddad3c LF |
166 | enum rf_tx_num { |
167 | RF_1TX = 0, | |
168 | RF_2TX, | |
169 | RF_MAX_TX_NUM, | |
170 | RF_TX_NUM_NONIMPLEMENT, | |
171 | }; | |
172 | ||
e6deaf81 LF |
173 | struct txpower_info_2g { |
174 | u8 index_cck_base[MAX_RF_PATH][MAX_CHNL_GROUP_24G]; | |
175 | u8 index_bw40_base[MAX_RF_PATH][MAX_CHNL_GROUP_24G]; | |
176 | /*If only one tx, only BW20 and OFDM are used.*/ | |
177 | u8 cck_diff[MAX_RF_PATH][MAX_TX_COUNT]; | |
178 | u8 ofdm_diff[MAX_RF_PATH][MAX_TX_COUNT]; | |
179 | u8 bw20_diff[MAX_RF_PATH][MAX_TX_COUNT]; | |
180 | u8 bw40_diff[MAX_RF_PATH][MAX_TX_COUNT]; | |
aa45a673 LF |
181 | u8 bw80_diff[MAX_RF_PATH][MAX_TX_COUNT]; |
182 | u8 bw160_diff[MAX_RF_PATH][MAX_TX_COUNT]; | |
e6deaf81 LF |
183 | }; |
184 | ||
185 | struct txpower_info_5g { | |
186 | u8 index_bw40_base[MAX_RF_PATH][MAX_CHNL_GROUP_5G]; | |
187 | /*If only one tx, only BW20, OFDM, BW80 and BW160 are used.*/ | |
188 | u8 ofdm_diff[MAX_RF_PATH][MAX_TX_COUNT]; | |
189 | u8 bw20_diff[MAX_RF_PATH][MAX_TX_COUNT]; | |
190 | u8 bw40_diff[MAX_RF_PATH][MAX_TX_COUNT]; | |
f3355dd9 LF |
191 | u8 bw80_diff[MAX_RF_PATH][MAX_TX_COUNT]; |
192 | u8 bw160_diff[MAX_RF_PATH][MAX_TX_COUNT]; | |
e6deaf81 LF |
193 | }; |
194 | ||
2cddad3c LF |
195 | enum rate_section { |
196 | CCK = 0, | |
197 | OFDM, | |
198 | HT_MCS0_MCS7, | |
199 | HT_MCS8_MCS15, | |
200 | VHT_1SSMCS0_1SSMCS9, | |
201 | VHT_2SSMCS0_2SSMCS9, | |
202 | }; | |
203 | ||
0c817338 LF |
204 | enum intf_type { |
205 | INTF_PCI = 0, | |
206 | INTF_USB = 1, | |
207 | }; | |
208 | ||
209 | enum radio_path { | |
210 | RF90_PATH_A = 0, | |
211 | RF90_PATH_B = 1, | |
212 | RF90_PATH_C = 2, | |
213 | RF90_PATH_D = 3, | |
214 | }; | |
215 | ||
216 | enum rt_eeprom_type { | |
217 | EEPROM_93C46, | |
218 | EEPROM_93C56, | |
219 | EEPROM_BOOT_EFUSE, | |
220 | }; | |
221 | ||
36323f81 | 222 | enum ttl_status { |
0c817338 LF |
223 | RTL_STATUS_INTERFACE_START = 0, |
224 | }; | |
225 | ||
226 | enum hardware_type { | |
227 | HARDWARE_TYPE_RTL8192E, | |
228 | HARDWARE_TYPE_RTL8192U, | |
229 | HARDWARE_TYPE_RTL8192SE, | |
230 | HARDWARE_TYPE_RTL8192SU, | |
231 | HARDWARE_TYPE_RTL8192CE, | |
232 | HARDWARE_TYPE_RTL8192CU, | |
233 | HARDWARE_TYPE_RTL8192DE, | |
234 | HARDWARE_TYPE_RTL8192DU, | |
2461c7d6 | 235 | HARDWARE_TYPE_RTL8723AE, |
18d30067 | 236 | HARDWARE_TYPE_RTL8723U, |
aa45a673 | 237 | HARDWARE_TYPE_RTL8723BE, |
5c69177d | 238 | HARDWARE_TYPE_RTL8188EE, |
f3355dd9 LF |
239 | HARDWARE_TYPE_RTL8821AE, |
240 | HARDWARE_TYPE_RTL8812AE, | |
0c817338 | 241 | |
e97b775d | 242 | /* keep it last */ |
0c817338 LF |
243 | HARDWARE_TYPE_NUM |
244 | }; | |
245 | ||
e97b775d LF |
246 | #define IS_HARDWARE_TYPE_8192SU(rtlhal) \ |
247 | (rtlhal->hw_type == HARDWARE_TYPE_RTL8192SU) | |
248 | #define IS_HARDWARE_TYPE_8192SE(rtlhal) \ | |
249 | (rtlhal->hw_type == HARDWARE_TYPE_RTL8192SE) | |
62e63975 LF |
250 | #define IS_HARDWARE_TYPE_8192CE(rtlhal) \ |
251 | (rtlhal->hw_type == HARDWARE_TYPE_RTL8192CE) | |
18d30067 G |
252 | #define IS_HARDWARE_TYPE_8192CU(rtlhal) \ |
253 | (rtlhal->hw_type == HARDWARE_TYPE_RTL8192CU) | |
e97b775d LF |
254 | #define IS_HARDWARE_TYPE_8192DE(rtlhal) \ |
255 | (rtlhal->hw_type == HARDWARE_TYPE_RTL8192DE) | |
256 | #define IS_HARDWARE_TYPE_8192DU(rtlhal) \ | |
257 | (rtlhal->hw_type == HARDWARE_TYPE_RTL8192DU) | |
258 | #define IS_HARDWARE_TYPE_8723E(rtlhal) \ | |
259 | (rtlhal->hw_type == HARDWARE_TYPE_RTL8723E) | |
18d30067 G |
260 | #define IS_HARDWARE_TYPE_8723U(rtlhal) \ |
261 | (rtlhal->hw_type == HARDWARE_TYPE_RTL8723U) | |
e97b775d LF |
262 | #define IS_HARDWARE_TYPE_8192S(rtlhal) \ |
263 | (IS_HARDWARE_TYPE_8192SE(rtlhal) || IS_HARDWARE_TYPE_8192SU(rtlhal)) | |
264 | #define IS_HARDWARE_TYPE_8192C(rtlhal) \ | |
265 | (IS_HARDWARE_TYPE_8192CE(rtlhal) || IS_HARDWARE_TYPE_8192CU(rtlhal)) | |
266 | #define IS_HARDWARE_TYPE_8192D(rtlhal) \ | |
267 | (IS_HARDWARE_TYPE_8192DE(rtlhal) || IS_HARDWARE_TYPE_8192DU(rtlhal)) | |
268 | #define IS_HARDWARE_TYPE_8723(rtlhal) \ | |
269 | (IS_HARDWARE_TYPE_8723E(rtlhal) || IS_HARDWARE_TYPE_8723U(rtlhal)) | |
62e63975 | 270 | |
da3ba88a LF |
271 | #define RX_HAL_IS_CCK_RATE(_pdesc)\ |
272 | (_pdesc->rxmcs == DESC92_RATE1M || \ | |
273 | _pdesc->rxmcs == DESC92_RATE2M || \ | |
274 | _pdesc->rxmcs == DESC92_RATE5_5M || \ | |
275 | _pdesc->rxmcs == DESC92_RATE11M) | |
276 | ||
2cddad3c LF |
277 | #define RTL8723E_RX_HAL_IS_CCK_RATE(rxmcs) \ |
278 | ((rxmcs) == DESC92_RATE1M || \ | |
279 | (rxmcs) == DESC92_RATE2M || \ | |
280 | (rxmcs) == DESC92_RATE5_5M || \ | |
281 | (rxmcs) == DESC92_RATE11M) | |
282 | ||
0c817338 LF |
283 | enum scan_operation_backup_opt { |
284 | SCAN_OPT_BACKUP = 0, | |
f3355dd9 LF |
285 | SCAN_OPT_BACKUP_BAND0 = 0, |
286 | SCAN_OPT_BACKUP_BAND1, | |
0c817338 LF |
287 | SCAN_OPT_RESTORE, |
288 | SCAN_OPT_MAX | |
289 | }; | |
290 | ||
291 | /*RF state.*/ | |
292 | enum rf_pwrstate { | |
293 | ERFON, | |
294 | ERFSLEEP, | |
295 | ERFOFF | |
296 | }; | |
297 | ||
298 | struct bb_reg_def { | |
299 | u32 rfintfs; | |
300 | u32 rfintfi; | |
301 | u32 rfintfo; | |
302 | u32 rfintfe; | |
303 | u32 rf3wire_offset; | |
304 | u32 rflssi_select; | |
305 | u32 rftxgain_stage; | |
306 | u32 rfhssi_para1; | |
307 | u32 rfhssi_para2; | |
da17fcff | 308 | u32 rfsw_ctrl; |
0c817338 LF |
309 | u32 rfagc_control1; |
310 | u32 rfagc_control2; | |
da17fcff | 311 | u32 rfrxiq_imbal; |
0c817338 | 312 | u32 rfrx_afe; |
da17fcff | 313 | u32 rftxiq_imbal; |
0c817338 | 314 | u32 rftx_afe; |
da17fcff LF |
315 | u32 rf_rb; /* rflssi_readback */ |
316 | u32 rf_rbpi; /* rflssi_readbackpi */ | |
0c817338 LF |
317 | }; |
318 | ||
319 | enum io_type { | |
320 | IO_CMD_PAUSE_DM_BY_SCAN = 0, | |
f3355dd9 LF |
321 | IO_CMD_PAUSE_BAND0_DM_BY_SCAN = 0, |
322 | IO_CMD_PAUSE_BAND1_DM_BY_SCAN = 1, | |
323 | IO_CMD_RESUME_DM_BY_SCAN = 2, | |
0c817338 LF |
324 | }; |
325 | ||
326 | enum hw_variables { | |
327 | HW_VAR_ETHER_ADDR, | |
328 | HW_VAR_MULTICAST_REG, | |
329 | HW_VAR_BASIC_RATE, | |
330 | HW_VAR_BSSID, | |
331 | HW_VAR_MEDIA_STATUS, | |
332 | HW_VAR_SECURITY_CONF, | |
333 | HW_VAR_BEACON_INTERVAL, | |
334 | HW_VAR_ATIM_WINDOW, | |
335 | HW_VAR_LISTEN_INTERVAL, | |
336 | HW_VAR_CS_COUNTER, | |
337 | HW_VAR_DEFAULTKEY0, | |
338 | HW_VAR_DEFAULTKEY1, | |
339 | HW_VAR_DEFAULTKEY2, | |
340 | HW_VAR_DEFAULTKEY3, | |
341 | HW_VAR_SIFS, | |
342 | HW_VAR_DIFS, | |
343 | HW_VAR_EIFS, | |
344 | HW_VAR_SLOT_TIME, | |
345 | HW_VAR_ACK_PREAMBLE, | |
346 | HW_VAR_CW_CONFIG, | |
347 | HW_VAR_CW_VALUES, | |
348 | HW_VAR_RATE_FALLBACK_CONTROL, | |
349 | HW_VAR_CONTENTION_WINDOW, | |
350 | HW_VAR_RETRY_COUNT, | |
351 | HW_VAR_TR_SWITCH, | |
352 | HW_VAR_COMMAND, | |
353 | HW_VAR_WPA_CONFIG, | |
354 | HW_VAR_AMPDU_MIN_SPACE, | |
355 | HW_VAR_SHORTGI_DENSITY, | |
356 | HW_VAR_AMPDU_FACTOR, | |
357 | HW_VAR_MCS_RATE_AVAILABLE, | |
358 | HW_VAR_AC_PARAM, | |
359 | HW_VAR_ACM_CTRL, | |
360 | HW_VAR_DIS_Req_Qsize, | |
361 | HW_VAR_CCX_CHNL_LOAD, | |
362 | HW_VAR_CCX_NOISE_HISTOGRAM, | |
363 | HW_VAR_CCX_CLM_NHM, | |
364 | HW_VAR_TxOPLimit, | |
365 | HW_VAR_TURBO_MODE, | |
366 | HW_VAR_RF_STATE, | |
367 | HW_VAR_RF_OFF_BY_HW, | |
368 | HW_VAR_BUS_SPEED, | |
369 | HW_VAR_SET_DEV_POWER, | |
370 | ||
371 | HW_VAR_RCR, | |
372 | HW_VAR_RATR_0, | |
373 | HW_VAR_RRSR, | |
374 | HW_VAR_CPU_RST, | |
26634c4b | 375 | HW_VAR_CHECK_BSSID, |
0c817338 LF |
376 | HW_VAR_LBK_MODE, |
377 | HW_VAR_AES_11N_FIX, | |
378 | HW_VAR_USB_RX_AGGR, | |
379 | HW_VAR_USER_CONTROL_TURBO_MODE, | |
380 | HW_VAR_RETRY_LIMIT, | |
381 | HW_VAR_INIT_TX_RATE, | |
382 | HW_VAR_TX_RATE_REG, | |
383 | HW_VAR_EFUSE_USAGE, | |
384 | HW_VAR_EFUSE_BYTES, | |
385 | HW_VAR_AUTOLOAD_STATUS, | |
386 | HW_VAR_RF_2R_DISABLE, | |
387 | HW_VAR_SET_RPWM, | |
388 | HW_VAR_H2C_FW_PWRMODE, | |
389 | HW_VAR_H2C_FW_JOINBSSRPT, | |
f3355dd9 | 390 | HW_VAR_H2C_FW_MEDIASTATUSRPT, |
26634c4b | 391 | HW_VAR_H2C_FW_P2P_PS_OFFLOAD, |
0c817338 | 392 | HW_VAR_FW_PSMODE_STATUS, |
26634c4b LF |
393 | HW_VAR_RESUME_CLK_ON, |
394 | HW_VAR_FW_LPS_ACTION, | |
0c817338 LF |
395 | HW_VAR_1X1_RECV_COMBINE, |
396 | HW_VAR_STOP_SEND_BEACON, | |
397 | HW_VAR_TSF_TIMER, | |
398 | HW_VAR_IO_CMD, | |
399 | ||
400 | HW_VAR_RF_RECOVERY, | |
401 | HW_VAR_H2C_FW_UPDATE_GTK, | |
402 | HW_VAR_WF_MASK, | |
403 | HW_VAR_WF_CRC, | |
404 | HW_VAR_WF_IS_MAC_ADDR, | |
405 | HW_VAR_H2C_FW_OFFLOAD, | |
406 | HW_VAR_RESET_WFCRC, | |
407 | ||
408 | HW_VAR_HANDLE_FW_C2H, | |
409 | HW_VAR_DL_FW_RSVD_PAGE, | |
410 | HW_VAR_AID, | |
411 | HW_VAR_HW_SEQ_ENABLE, | |
412 | HW_VAR_CORRECT_TSF, | |
413 | HW_VAR_BCN_VALID, | |
414 | HW_VAR_FWLPS_RF_ON, | |
415 | HW_VAR_DUAL_TSF_RST, | |
416 | HW_VAR_SWITCH_EPHY_WoWLAN, | |
417 | HW_VAR_INT_MIGRATION, | |
418 | HW_VAR_INT_AC, | |
419 | HW_VAR_RF_TIMING, | |
420 | ||
26634c4b | 421 | HAL_DEF_WOWLAN, |
0c817338 | 422 | HW_VAR_MRC, |
2cddad3c | 423 | HW_VAR_KEEP_ALIVE, |
f3355dd9 | 424 | HW_VAR_NAV_UPPER, |
0c817338 LF |
425 | |
426 | HW_VAR_MGT_FILTER, | |
427 | HW_VAR_CTRL_FILTER, | |
428 | HW_VAR_DATA_FILTER, | |
429 | }; | |
430 | ||
431 | enum _RT_MEDIA_STATUS { | |
432 | RT_MEDIA_DISCONNECT = 0, | |
433 | RT_MEDIA_CONNECT = 1 | |
434 | }; | |
435 | ||
436 | enum rt_oem_id { | |
437 | RT_CID_DEFAULT = 0, | |
438 | RT_CID_8187_ALPHA0 = 1, | |
439 | RT_CID_8187_SERCOMM_PS = 2, | |
440 | RT_CID_8187_HW_LED = 3, | |
441 | RT_CID_8187_NETGEAR = 4, | |
442 | RT_CID_WHQL = 5, | |
2cddad3c LF |
443 | RT_CID_819X_CAMEO = 6, |
444 | RT_CID_819X_RUNTOP = 7, | |
445 | RT_CID_819X_SENAO = 8, | |
0c817338 | 446 | RT_CID_TOSHIBA = 9, |
2cddad3c LF |
447 | RT_CID_819X_NETCORE = 10, |
448 | RT_CID_NETTRONIX = 11, | |
0c817338 LF |
449 | RT_CID_DLINK = 12, |
450 | RT_CID_PRONET = 13, | |
451 | RT_CID_COREGA = 14, | |
2cddad3c LF |
452 | RT_CID_819X_ALPHA = 15, |
453 | RT_CID_819X_SITECOM = 16, | |
0c817338 | 454 | RT_CID_CCX = 17, |
2cddad3c LF |
455 | RT_CID_819X_LENOVO = 18, |
456 | RT_CID_819X_QMI = 19, | |
457 | RT_CID_819X_EDIMAX_BELKIN = 20, | |
458 | RT_CID_819X_SERCOMM_BELKIN = 21, | |
459 | RT_CID_819X_CAMEO1 = 22, | |
460 | RT_CID_819X_MSI = 23, | |
461 | RT_CID_819X_ACER = 24, | |
462 | RT_CID_819X_HP = 27, | |
463 | RT_CID_819X_CLEVO = 28, | |
464 | RT_CID_819X_ARCADYAN_BELKIN = 29, | |
465 | RT_CID_819X_SAMSUNG = 30, | |
466 | RT_CID_819X_WNC_COREGA = 31, | |
467 | RT_CID_819X_FOXCOON = 32, | |
468 | RT_CID_819X_DELL = 33, | |
469 | RT_CID_819X_PRONETS = 34, | |
470 | RT_CID_819X_EDIMAX_ASUS = 35, | |
0f015453 LF |
471 | RT_CID_NETGEAR = 36, |
472 | RT_CID_PLANEX = 37, | |
473 | RT_CID_CC_C = 38, | |
0c817338 LF |
474 | }; |
475 | ||
476 | enum hw_descs { | |
477 | HW_DESC_OWN, | |
478 | HW_DESC_RXOWN, | |
479 | HW_DESC_TX_NEXTDESC_ADDR, | |
480 | HW_DESC_TXBUFF_ADDR, | |
481 | HW_DESC_RXBUFF_ADDR, | |
482 | HW_DESC_RXPKT_LEN, | |
483 | HW_DESC_RXERO, | |
f3355dd9 | 484 | HW_DESC_RX_PREPARE, |
0c817338 LF |
485 | }; |
486 | ||
487 | enum prime_sc { | |
488 | PRIME_CHNL_OFFSET_DONT_CARE = 0, | |
489 | PRIME_CHNL_OFFSET_LOWER = 1, | |
490 | PRIME_CHNL_OFFSET_UPPER = 2, | |
491 | }; | |
492 | ||
493 | enum rf_type { | |
494 | RF_1T1R = 0, | |
495 | RF_1T2R = 1, | |
496 | RF_2T2R = 2, | |
e97b775d | 497 | RF_2T2R_GREEN = 3, |
0c817338 LF |
498 | }; |
499 | ||
500 | enum ht_channel_width { | |
501 | HT_CHANNEL_WIDTH_20 = 0, | |
502 | HT_CHANNEL_WIDTH_20_40 = 1, | |
f3355dd9 | 503 | HT_CHANNEL_WIDTH_80 = 2, |
0c817338 LF |
504 | }; |
505 | ||
506 | /* Ref: 802.11i sepc D10.0 7.3.2.25.1 | |
507 | Cipher Suites Encryption Algorithms */ | |
508 | enum rt_enc_alg { | |
509 | NO_ENCRYPTION = 0, | |
510 | WEP40_ENCRYPTION = 1, | |
511 | TKIP_ENCRYPTION = 2, | |
512 | RSERVED_ENCRYPTION = 3, | |
513 | AESCCMP_ENCRYPTION = 4, | |
514 | WEP104_ENCRYPTION = 5, | |
2461c7d6 | 515 | AESCMAC_ENCRYPTION = 6, /*IEEE802.11w */ |
0c817338 LF |
516 | }; |
517 | ||
518 | enum rtl_hal_state { | |
519 | _HAL_STATE_STOP = 0, | |
520 | _HAL_STATE_START = 1, | |
521 | }; | |
522 | ||
7ad0ce35 LF |
523 | enum rtl_desc92_rate { |
524 | DESC92_RATE1M = 0x00, | |
525 | DESC92_RATE2M = 0x01, | |
526 | DESC92_RATE5_5M = 0x02, | |
527 | DESC92_RATE11M = 0x03, | |
528 | ||
529 | DESC92_RATE6M = 0x04, | |
530 | DESC92_RATE9M = 0x05, | |
531 | DESC92_RATE12M = 0x06, | |
532 | DESC92_RATE18M = 0x07, | |
533 | DESC92_RATE24M = 0x08, | |
534 | DESC92_RATE36M = 0x09, | |
535 | DESC92_RATE48M = 0x0a, | |
536 | DESC92_RATE54M = 0x0b, | |
537 | ||
538 | DESC92_RATEMCS0 = 0x0c, | |
539 | DESC92_RATEMCS1 = 0x0d, | |
540 | DESC92_RATEMCS2 = 0x0e, | |
541 | DESC92_RATEMCS3 = 0x0f, | |
542 | DESC92_RATEMCS4 = 0x10, | |
543 | DESC92_RATEMCS5 = 0x11, | |
544 | DESC92_RATEMCS6 = 0x12, | |
545 | DESC92_RATEMCS7 = 0x13, | |
546 | DESC92_RATEMCS8 = 0x14, | |
547 | DESC92_RATEMCS9 = 0x15, | |
548 | DESC92_RATEMCS10 = 0x16, | |
549 | DESC92_RATEMCS11 = 0x17, | |
550 | DESC92_RATEMCS12 = 0x18, | |
551 | DESC92_RATEMCS13 = 0x19, | |
552 | DESC92_RATEMCS14 = 0x1a, | |
553 | DESC92_RATEMCS15 = 0x1b, | |
554 | DESC92_RATEMCS15_SG = 0x1c, | |
555 | DESC92_RATEMCS32 = 0x20, | |
556 | }; | |
557 | ||
0c817338 LF |
558 | enum rtl_var_map { |
559 | /*reg map */ | |
560 | SYS_ISO_CTRL = 0, | |
561 | SYS_FUNC_EN, | |
562 | SYS_CLK, | |
563 | MAC_RCR_AM, | |
564 | MAC_RCR_AB, | |
565 | MAC_RCR_ACRC32, | |
566 | MAC_RCR_ACF, | |
567 | MAC_RCR_AAP, | |
f3355dd9 LF |
568 | MAC_HIMR, |
569 | MAC_HIMRE, | |
570 | MAC_HSISR, | |
0c817338 LF |
571 | |
572 | /*efuse map */ | |
573 | EFUSE_TEST, | |
574 | EFUSE_CTRL, | |
575 | EFUSE_CLK, | |
576 | EFUSE_CLK_CTRL, | |
577 | EFUSE_PWC_EV12V, | |
578 | EFUSE_FEN_ELDR, | |
579 | EFUSE_LOADER_CLK_EN, | |
580 | EFUSE_ANA8M, | |
581 | EFUSE_HWSET_MAX_SIZE, | |
18d30067 G |
582 | EFUSE_MAX_SECTION_MAP, |
583 | EFUSE_REAL_CONTENT_SIZE, | |
5c079d88 | 584 | EFUSE_OOB_PROTECT_BYTES_LEN, |
26634c4b | 585 | EFUSE_ACCESS, |
0c817338 LF |
586 | |
587 | /*CAM map */ | |
588 | RWCAM, | |
589 | WCAMI, | |
590 | RCAMO, | |
591 | CAMDBG, | |
592 | SECR, | |
593 | SEC_CAM_NONE, | |
594 | SEC_CAM_WEP40, | |
595 | SEC_CAM_TKIP, | |
596 | SEC_CAM_AES, | |
597 | SEC_CAM_WEP104, | |
598 | ||
599 | /*IMR map */ | |
600 | RTL_IMR_BCNDMAINT6, /*Beacon DMA Interrupt 6 */ | |
601 | RTL_IMR_BCNDMAINT5, /*Beacon DMA Interrupt 5 */ | |
602 | RTL_IMR_BCNDMAINT4, /*Beacon DMA Interrupt 4 */ | |
603 | RTL_IMR_BCNDMAINT3, /*Beacon DMA Interrupt 3 */ | |
604 | RTL_IMR_BCNDMAINT2, /*Beacon DMA Interrupt 2 */ | |
605 | RTL_IMR_BCNDMAINT1, /*Beacon DMA Interrupt 1 */ | |
606 | RTL_IMR_BCNDOK8, /*Beacon Queue DMA OK Interrup 8 */ | |
607 | RTL_IMR_BCNDOK7, /*Beacon Queue DMA OK Interrup 7 */ | |
608 | RTL_IMR_BCNDOK6, /*Beacon Queue DMA OK Interrup 6 */ | |
609 | RTL_IMR_BCNDOK5, /*Beacon Queue DMA OK Interrup 5 */ | |
610 | RTL_IMR_BCNDOK4, /*Beacon Queue DMA OK Interrup 4 */ | |
611 | RTL_IMR_BCNDOK3, /*Beacon Queue DMA OK Interrup 3 */ | |
612 | RTL_IMR_BCNDOK2, /*Beacon Queue DMA OK Interrup 2 */ | |
613 | RTL_IMR_BCNDOK1, /*Beacon Queue DMA OK Interrup 1 */ | |
614 | RTL_IMR_TIMEOUT2, /*Timeout interrupt 2 */ | |
615 | RTL_IMR_TIMEOUT1, /*Timeout interrupt 1 */ | |
616 | RTL_IMR_TXFOVW, /*Transmit FIFO Overflow */ | |
617 | RTL_IMR_PSTIMEOUT, /*Power save time out interrupt */ | |
e6deaf81 | 618 | RTL_IMR_BCNINT, /*Beacon DMA Interrupt 0 */ |
0c817338 LF |
619 | RTL_IMR_RXFOVW, /*Receive FIFO Overflow */ |
620 | RTL_IMR_RDU, /*Receive Descriptor Unavailable */ | |
621 | RTL_IMR_ATIMEND, /*For 92C,ATIM Window End Interrupt */ | |
622 | RTL_IMR_BDOK, /*Beacon Queue DMA OK Interrup */ | |
623 | RTL_IMR_HIGHDOK, /*High Queue DMA OK Interrupt */ | |
e97b775d | 624 | RTL_IMR_COMDOK, /*Command Queue DMA OK Interrupt*/ |
0c817338 LF |
625 | RTL_IMR_TBDOK, /*Transmit Beacon OK interrup */ |
626 | RTL_IMR_MGNTDOK, /*Management Queue DMA OK Interrupt */ | |
627 | RTL_IMR_TBDER, /*For 92C,Transmit Beacon Error Interrupt */ | |
628 | RTL_IMR_BKDOK, /*AC_BK DMA OK Interrupt */ | |
629 | RTL_IMR_BEDOK, /*AC_BE DMA OK Interrupt */ | |
630 | RTL_IMR_VIDOK, /*AC_VI DMA OK Interrupt */ | |
631 | RTL_IMR_VODOK, /*AC_VO DMA Interrupt */ | |
632 | RTL_IMR_ROK, /*Receive DMA OK Interrupt */ | |
e6deaf81 | 633 | RTL_IBSS_INT_MASKS, /*(RTL_IMR_BCNINT | RTL_IMR_TBDOK | |
e97b775d | 634 | * RTL_IMR_TBDER) */ |
0f015453 | 635 | RTL_IMR_C2HCMD, /*fw interrupt*/ |
0c817338 LF |
636 | |
637 | /*CCK Rates, TxHT = 0 */ | |
638 | RTL_RC_CCK_RATE1M, | |
639 | RTL_RC_CCK_RATE2M, | |
640 | RTL_RC_CCK_RATE5_5M, | |
641 | RTL_RC_CCK_RATE11M, | |
642 | ||
643 | /*OFDM Rates, TxHT = 0 */ | |
644 | RTL_RC_OFDM_RATE6M, | |
645 | RTL_RC_OFDM_RATE9M, | |
646 | RTL_RC_OFDM_RATE12M, | |
647 | RTL_RC_OFDM_RATE18M, | |
648 | RTL_RC_OFDM_RATE24M, | |
649 | RTL_RC_OFDM_RATE36M, | |
650 | RTL_RC_OFDM_RATE48M, | |
651 | RTL_RC_OFDM_RATE54M, | |
652 | ||
653 | RTL_RC_HT_RATEMCS7, | |
654 | RTL_RC_HT_RATEMCS15, | |
655 | ||
656 | /*keep it last */ | |
657 | RTL_VAR_MAP_MAX, | |
658 | }; | |
659 | ||
660 | /*Firmware PS mode for control LPS.*/ | |
661 | enum _fw_ps_mode { | |
662 | FW_PS_ACTIVE_MODE = 0, | |
663 | FW_PS_MIN_MODE = 1, | |
664 | FW_PS_MAX_MODE = 2, | |
665 | FW_PS_DTIM_MODE = 3, | |
666 | FW_PS_VOIP_MODE = 4, | |
667 | FW_PS_UAPSD_WMM_MODE = 5, | |
668 | FW_PS_UAPSD_MODE = 6, | |
669 | FW_PS_IBSS_MODE = 7, | |
670 | FW_PS_WWLAN_MODE = 8, | |
671 | FW_PS_PM_Radio_Off = 9, | |
672 | FW_PS_PM_Card_Disable = 10, | |
673 | }; | |
674 | ||
675 | enum rt_psmode { | |
676 | EACTIVE, /*Active/Continuous access. */ | |
677 | EMAXPS, /*Max power save mode. */ | |
678 | EFASTPS, /*Fast power save mode. */ | |
679 | EAUTOPS, /*Auto power save mode. */ | |
680 | }; | |
681 | ||
682 | /*LED related.*/ | |
683 | enum led_ctl_mode { | |
684 | LED_CTL_POWER_ON = 1, | |
685 | LED_CTL_LINK = 2, | |
686 | LED_CTL_NO_LINK = 3, | |
687 | LED_CTL_TX = 4, | |
688 | LED_CTL_RX = 5, | |
689 | LED_CTL_SITE_SURVEY = 6, | |
690 | LED_CTL_POWER_OFF = 7, | |
691 | LED_CTL_START_TO_LINK = 8, | |
692 | LED_CTL_START_WPS = 9, | |
693 | LED_CTL_STOP_WPS = 10, | |
694 | }; | |
695 | ||
696 | enum rtl_led_pin { | |
697 | LED_PIN_GPIO0, | |
698 | LED_PIN_LED0, | |
699 | LED_PIN_LED1, | |
700 | LED_PIN_LED2 | |
701 | }; | |
702 | ||
703 | /*QoS related.*/ | |
704 | /*acm implementation method.*/ | |
705 | enum acm_method { | |
706 | eAcmWay0_SwAndHw = 0, | |
707 | eAcmWay1_HW = 1, | |
2cddad3c | 708 | EACMWAY2_SW = 2, |
0c817338 LF |
709 | }; |
710 | ||
e97b775d LF |
711 | enum macphy_mode { |
712 | SINGLEMAC_SINGLEPHY = 0, | |
713 | DUALMAC_DUALPHY, | |
714 | DUALMAC_SINGLEPHY, | |
715 | }; | |
716 | ||
717 | enum band_type { | |
718 | BAND_ON_2_4G = 0, | |
719 | BAND_ON_5G, | |
720 | BAND_ON_BOTH, | |
721 | BANDMAX | |
722 | }; | |
723 | ||
0c817338 LF |
724 | /*aci/aifsn Field. |
725 | Ref: WMM spec 2.2.2: WME Parameter Element, p.12.*/ | |
726 | union aci_aifsn { | |
727 | u8 char_data; | |
728 | ||
729 | struct { | |
730 | u8 aifsn:4; | |
731 | u8 acm:1; | |
732 | u8 aci:2; | |
733 | u8 reserved:1; | |
734 | } f; /* Field */ | |
735 | }; | |
736 | ||
737 | /*mlme related.*/ | |
738 | enum wireless_mode { | |
739 | WIRELESS_MODE_UNKNOWN = 0x00, | |
740 | WIRELESS_MODE_A = 0x01, | |
741 | WIRELESS_MODE_B = 0x02, | |
742 | WIRELESS_MODE_G = 0x04, | |
743 | WIRELESS_MODE_AUTO = 0x08, | |
744 | WIRELESS_MODE_N_24G = 0x10, | |
f3355dd9 LF |
745 | WIRELESS_MODE_N_5G = 0x20, |
746 | WIRELESS_MODE_AC_5G = 0x40, | |
747 | WIRELESS_MODE_AC_24G = 0x80 | |
0c817338 LF |
748 | }; |
749 | ||
18d30067 G |
750 | #define IS_WIRELESS_MODE_A(wirelessmode) \ |
751 | (wirelessmode == WIRELESS_MODE_A) | |
752 | #define IS_WIRELESS_MODE_B(wirelessmode) \ | |
753 | (wirelessmode == WIRELESS_MODE_B) | |
754 | #define IS_WIRELESS_MODE_G(wirelessmode) \ | |
755 | (wirelessmode == WIRELESS_MODE_G) | |
756 | #define IS_WIRELESS_MODE_N_24G(wirelessmode) \ | |
757 | (wirelessmode == WIRELESS_MODE_N_24G) | |
758 | #define IS_WIRELESS_MODE_N_5G(wirelessmode) \ | |
759 | (wirelessmode == WIRELESS_MODE_N_5G) | |
760 | ||
0c817338 LF |
761 | enum ratr_table_mode { |
762 | RATR_INX_WIRELESS_NGB = 0, | |
763 | RATR_INX_WIRELESS_NG = 1, | |
764 | RATR_INX_WIRELESS_NB = 2, | |
765 | RATR_INX_WIRELESS_N = 3, | |
766 | RATR_INX_WIRELESS_GB = 4, | |
767 | RATR_INX_WIRELESS_G = 5, | |
768 | RATR_INX_WIRELESS_B = 6, | |
769 | RATR_INX_WIRELESS_MC = 7, | |
770 | RATR_INX_WIRELESS_A = 8, | |
f3355dd9 LF |
771 | RATR_INX_WIRELESS_AC_5N = 8, |
772 | RATR_INX_WIRELESS_AC_24N = 9, | |
0c817338 LF |
773 | }; |
774 | ||
775 | enum rtl_link_state { | |
776 | MAC80211_NOLINK = 0, | |
777 | MAC80211_LINKING = 1, | |
778 | MAC80211_LINKED = 2, | |
779 | MAC80211_LINKED_SCANNING = 3, | |
780 | }; | |
781 | ||
782 | enum act_category { | |
783 | ACT_CAT_QOS = 1, | |
784 | ACT_CAT_DLS = 2, | |
785 | ACT_CAT_BA = 3, | |
786 | ACT_CAT_HT = 7, | |
787 | ACT_CAT_WMM = 17, | |
788 | }; | |
789 | ||
790 | enum ba_action { | |
791 | ACT_ADDBAREQ = 0, | |
792 | ACT_ADDBARSP = 1, | |
793 | ACT_DELBA = 2, | |
794 | }; | |
795 | ||
0f015453 LF |
796 | enum rt_polarity_ctl { |
797 | RT_POLARITY_LOW_ACT = 0, | |
798 | RT_POLARITY_HIGH_ACT = 1, | |
799 | }; | |
800 | ||
0c817338 LF |
801 | struct octet_string { |
802 | u8 *octet; | |
803 | u16 length; | |
804 | }; | |
805 | ||
806 | struct rtl_hdr_3addr { | |
807 | __le16 frame_ctl; | |
808 | __le16 duration_id; | |
809 | u8 addr1[ETH_ALEN]; | |
810 | u8 addr2[ETH_ALEN]; | |
811 | u8 addr3[ETH_ALEN]; | |
812 | __le16 seq_ctl; | |
813 | u8 payload[0]; | |
e137478b | 814 | } __packed; |
0c817338 LF |
815 | |
816 | struct rtl_info_element { | |
817 | u8 id; | |
818 | u8 len; | |
819 | u8 data[0]; | |
e137478b | 820 | } __packed; |
0c817338 LF |
821 | |
822 | struct rtl_probe_rsp { | |
823 | struct rtl_hdr_3addr header; | |
824 | u32 time_stamp[2]; | |
825 | __le16 beacon_interval; | |
826 | __le16 capability; | |
827 | /*SSID, supported rates, FH params, DS params, | |
828 | CF params, IBSS params, TIM (if beacon), RSN */ | |
829 | struct rtl_info_element info_element[0]; | |
e137478b | 830 | } __packed; |
0c817338 LF |
831 | |
832 | /*LED related.*/ | |
833 | /*ledpin Identify how to implement this SW led.*/ | |
834 | struct rtl_led { | |
835 | void *hw; | |
836 | enum rtl_led_pin ledpin; | |
7ea47240 | 837 | bool ledon; |
0c817338 LF |
838 | }; |
839 | ||
840 | struct rtl_led_ctl { | |
7ea47240 | 841 | bool led_opendrain; |
0c817338 LF |
842 | struct rtl_led sw_led0; |
843 | struct rtl_led sw_led1; | |
844 | }; | |
845 | ||
846 | struct rtl_qos_parameters { | |
847 | __le16 cw_min; | |
848 | __le16 cw_max; | |
849 | u8 aifs; | |
850 | u8 flag; | |
851 | __le16 tx_op; | |
e137478b | 852 | } __packed; |
0c817338 LF |
853 | |
854 | struct rt_smooth_data { | |
855 | u32 elements[100]; /*array to store values */ | |
856 | u32 index; /*index to current array to store */ | |
857 | u32 total_num; /*num of valid elements */ | |
858 | u32 total_val; /*sum of valid elements */ | |
859 | }; | |
860 | ||
861 | struct false_alarm_statistics { | |
862 | u32 cnt_parity_fail; | |
863 | u32 cnt_rate_illegal; | |
864 | u32 cnt_crc8_fail; | |
865 | u32 cnt_mcs_fail; | |
e97b775d LF |
866 | u32 cnt_fast_fsync_fail; |
867 | u32 cnt_sb_search_fail; | |
0c817338 LF |
868 | u32 cnt_ofdm_fail; |
869 | u32 cnt_cck_fail; | |
870 | u32 cnt_all; | |
26634c4b LF |
871 | u32 cnt_ofdm_cca; |
872 | u32 cnt_cck_cca; | |
873 | u32 cnt_cca_all; | |
874 | u32 cnt_bw_usc; | |
875 | u32 cnt_bw_lsc; | |
0c817338 LF |
876 | }; |
877 | ||
878 | struct init_gain { | |
879 | u8 xaagccore1; | |
880 | u8 xbagccore1; | |
881 | u8 xcagccore1; | |
882 | u8 xdagccore1; | |
883 | u8 cca; | |
884 | ||
885 | }; | |
886 | ||
887 | struct wireless_stats { | |
888 | unsigned long txbytesunicast; | |
889 | unsigned long txbytesmulticast; | |
890 | unsigned long txbytesbroadcast; | |
891 | unsigned long rxbytesunicast; | |
892 | ||
893 | long rx_snr_db[4]; | |
894 | /*Correct smoothed ss in Dbm, only used | |
895 | in driver to report real power now. */ | |
896 | long recv_signal_power; | |
897 | long signal_quality; | |
898 | long last_sigstrength_inpercent; | |
899 | ||
900 | u32 rssi_calculate_cnt; | |
901 | ||
902 | /*Transformed, in dbm. Beautified signal | |
903 | strength for UI, not correct. */ | |
904 | long signal_strength; | |
905 | ||
906 | u8 rx_rssi_percentage[4]; | |
f3355dd9 | 907 | u8 rx_evm_dbm[4]; |
0c817338 LF |
908 | u8 rx_evm_percentage[2]; |
909 | ||
f3355dd9 LF |
910 | u16 rx_cfo_short[4]; |
911 | u16 rx_cfo_tail[4]; | |
912 | ||
0c817338 LF |
913 | struct rt_smooth_data ui_rssi; |
914 | struct rt_smooth_data ui_link_quality; | |
915 | }; | |
916 | ||
917 | struct rate_adaptive { | |
918 | u8 rate_adaptive_disabled; | |
919 | u8 ratr_state; | |
920 | u16 reserve; | |
921 | ||
922 | u32 high_rssi_thresh_for_ra; | |
923 | u32 high2low_rssi_thresh_for_ra; | |
924 | u8 low2high_rssi_thresh_for_ra40m; | |
2cddad3c | 925 | u32 low_rssi_thresh_for_ra40m; |
0c817338 | 926 | u8 low2high_rssi_thresh_for_ra20m; |
2cddad3c | 927 | u32 low_rssi_thresh_for_ra20m; |
0c817338 LF |
928 | u32 upper_rssi_threshold_ratr; |
929 | u32 middleupper_rssi_threshold_ratr; | |
930 | u32 middle_rssi_threshold_ratr; | |
931 | u32 middlelow_rssi_threshold_ratr; | |
932 | u32 low_rssi_threshold_ratr; | |
933 | u32 ultralow_rssi_threshold_ratr; | |
934 | u32 low_rssi_threshold_ratr_40m; | |
935 | u32 low_rssi_threshold_ratr_20m; | |
936 | u8 ping_rssi_enable; | |
937 | u32 ping_rssi_ratr; | |
938 | u32 ping_rssi_thresh_for_ra; | |
939 | u32 last_ratr; | |
940 | u8 pre_ratr_state; | |
f3355dd9 LF |
941 | u8 ldpc_thres; |
942 | bool use_ldpc; | |
943 | bool lower_rts_rate; | |
944 | bool is_special_data; | |
0c817338 LF |
945 | }; |
946 | ||
947 | struct regd_pair_mapping { | |
948 | u16 reg_dmnenum; | |
949 | u16 reg_5ghz_ctl; | |
950 | u16 reg_2ghz_ctl; | |
951 | }; | |
952 | ||
f3355dd9 LF |
953 | struct dynamic_primary_cca { |
954 | u8 pricca_flag; | |
955 | u8 intf_flag; | |
956 | u8 intf_type; | |
957 | u8 dup_rts_flag; | |
958 | u8 monitor_flag; | |
959 | u8 ch_offset; | |
960 | u8 mf_state; | |
961 | }; | |
962 | ||
0c817338 LF |
963 | struct rtl_regulatory { |
964 | char alpha2[2]; | |
965 | u16 country_code; | |
966 | u16 max_power_level; | |
967 | u32 tp_scale; | |
968 | u16 current_rd; | |
969 | u16 current_rd_ext; | |
970 | int16_t power_limit; | |
971 | struct regd_pair_mapping *regpair; | |
972 | }; | |
973 | ||
974 | struct rtl_rfkill { | |
975 | bool rfkill_state; /*0 is off, 1 is on */ | |
976 | }; | |
977 | ||
26634c4b LF |
978 | /*for P2P PS**/ |
979 | #define P2P_MAX_NOA_NUM 2 | |
980 | ||
981 | enum p2p_role { | |
982 | P2P_ROLE_DISABLE = 0, | |
983 | P2P_ROLE_DEVICE = 1, | |
984 | P2P_ROLE_CLIENT = 2, | |
985 | P2P_ROLE_GO = 3 | |
986 | }; | |
987 | ||
988 | enum p2p_ps_state { | |
989 | P2P_PS_DISABLE = 0, | |
990 | P2P_PS_ENABLE = 1, | |
991 | P2P_PS_SCAN = 2, | |
992 | P2P_PS_SCAN_DONE = 3, | |
993 | P2P_PS_ALLSTASLEEP = 4, /* for P2P GO */ | |
994 | }; | |
995 | ||
996 | enum p2p_ps_mode { | |
997 | P2P_PS_NONE = 0, | |
998 | P2P_PS_CTWINDOW = 1, | |
999 | P2P_PS_NOA = 2, | |
1000 | P2P_PS_MIX = 3, /* CTWindow and NoA */ | |
1001 | }; | |
1002 | ||
1003 | struct rtl_p2p_ps_info { | |
1004 | enum p2p_ps_mode p2p_ps_mode; /* indicate p2p ps mode */ | |
1005 | enum p2p_ps_state p2p_ps_state; /* indicate p2p ps state */ | |
1006 | u8 noa_index; /* Identifies instance of Notice of Absence timing. */ | |
1007 | /* Client traffic window. A period of time in TU after TBTT. */ | |
1008 | u8 ctwindow; | |
1009 | u8 opp_ps; /* opportunistic power save. */ | |
1010 | u8 noa_num; /* number of NoA descriptor in P2P IE. */ | |
1011 | /* Count for owner, Type of client. */ | |
1012 | u8 noa_count_type[P2P_MAX_NOA_NUM]; | |
1013 | /* Max duration for owner, preferred or min acceptable duration | |
1014 | * for client. | |
1015 | */ | |
1016 | u32 noa_duration[P2P_MAX_NOA_NUM]; | |
1017 | /* Length of interval for owner, preferred or max acceptable intervali | |
1018 | * of client. | |
1019 | */ | |
1020 | u32 noa_interval[P2P_MAX_NOA_NUM]; | |
1021 | /* schedule in terms of the lower 4 bytes of the TSF timer. */ | |
1022 | u32 noa_start_time[P2P_MAX_NOA_NUM]; | |
1023 | }; | |
1024 | ||
1025 | struct p2p_ps_offload_t { | |
1026 | u8 offload_en:1; | |
1027 | u8 role:1; /* 1: Owner, 0: Client */ | |
1028 | u8 ctwindow_en:1; | |
1029 | u8 noa0_en:1; | |
1030 | u8 noa1_en:1; | |
1031 | u8 allstasleep:1; | |
1032 | u8 discovery:1; | |
1033 | u8 reserved:1; | |
1034 | }; | |
1035 | ||
e97b775d LF |
1036 | #define IQK_MATRIX_REG_NUM 8 |
1037 | #define IQK_MATRIX_SETTINGS_NUM (1 + 24 + 21) | |
26634c4b | 1038 | |
e97b775d | 1039 | struct iqk_matrix_regs { |
32473284 | 1040 | bool iqk_done; |
e97b775d LF |
1041 | long value[1][IQK_MATRIX_REG_NUM]; |
1042 | }; | |
1043 | ||
18d30067 G |
1044 | struct phy_parameters { |
1045 | u16 length; | |
1046 | u32 *pdata; | |
1047 | }; | |
1048 | ||
1049 | enum hw_param_tab_index { | |
1050 | PHY_REG_2T, | |
1051 | PHY_REG_1T, | |
1052 | PHY_REG_PG, | |
1053 | RADIOA_2T, | |
1054 | RADIOB_2T, | |
1055 | RADIOA_1T, | |
1056 | RADIOB_1T, | |
1057 | MAC_REG, | |
1058 | AGCTAB_2T, | |
1059 | AGCTAB_1T, | |
1060 | MAX_TAB | |
1061 | }; | |
1062 | ||
0c817338 LF |
1063 | struct rtl_phy { |
1064 | struct bb_reg_def phyreg_def[4]; /*Radio A/B/C/D */ | |
1065 | struct init_gain initgain_backup; | |
1066 | enum io_type current_io_type; | |
1067 | ||
1068 | u8 rf_mode; | |
1069 | u8 rf_type; | |
1070 | u8 current_chan_bw; | |
1071 | u8 set_bwmode_inprogress; | |
1072 | u8 sw_chnl_inprogress; | |
1073 | u8 sw_chnl_stage; | |
1074 | u8 sw_chnl_step; | |
1075 | u8 current_channel; | |
1076 | u8 h2c_box_num; | |
1077 | u8 set_io_inprogress; | |
e97b775d | 1078 | u8 lck_inprogress; |
0c817338 | 1079 | |
e97b775d | 1080 | /* record for power tracking */ |
0c817338 LF |
1081 | s32 reg_e94; |
1082 | s32 reg_e9c; | |
1083 | s32 reg_ea4; | |
1084 | s32 reg_eac; | |
1085 | s32 reg_eb4; | |
1086 | s32 reg_ebc; | |
1087 | s32 reg_ec4; | |
1088 | s32 reg_ecc; | |
1089 | u8 rfpienable; | |
1090 | u8 reserve_0; | |
1091 | u16 reserve_1; | |
1092 | u32 reg_c04, reg_c08, reg_874; | |
1093 | u32 adda_backup[16]; | |
1094 | u32 iqk_mac_backup[IQK_MAC_REG_NUM]; | |
1095 | u32 iqk_bb_backup[10]; | |
2461c7d6 | 1096 | bool iqk_initialized; |
0c817338 | 1097 | |
f3355dd9 LF |
1098 | bool rfpath_rx_enable[MAX_RF_PATH]; |
1099 | u8 reg_837; | |
e97b775d LF |
1100 | /* Dual mac */ |
1101 | bool need_iqk; | |
e6deaf81 | 1102 | struct iqk_matrix_regs iqk_matrix[IQK_MATRIX_SETTINGS_NUM]; |
e97b775d | 1103 | |
7ea47240 | 1104 | bool rfpi_enable; |
f3355dd9 | 1105 | bool iqk_in_progress; |
0c817338 LF |
1106 | |
1107 | u8 pwrgroup_cnt; | |
7ea47240 | 1108 | u8 cck_high_power; |
e97b775d | 1109 | /* MAX_PG_GROUP groups of pwr diff by rates */ |
da17fcff | 1110 | u32 mcs_offset[MAX_PG_GROUP][16]; |
2cddad3c LF |
1111 | u32 tx_power_by_rate_offset[TX_PWR_BY_RATE_NUM_BAND] |
1112 | [TX_PWR_BY_RATE_NUM_RF] | |
1113 | [TX_PWR_BY_RATE_NUM_RF] | |
1114 | [TX_PWR_BY_RATE_NUM_SECTION]; | |
1115 | u8 txpwr_by_rate_base_24g[TX_PWR_BY_RATE_NUM_RF] | |
1116 | [TX_PWR_BY_RATE_NUM_RF] | |
1117 | [MAX_BASE_NUM_IN_PHY_REG_PG_24G]; | |
f3355dd9 LF |
1118 | u8 txpwr_by_rate_base_5g[TX_PWR_BY_RATE_NUM_RF] |
1119 | [TX_PWR_BY_RATE_NUM_RF] | |
1120 | [MAX_BASE_NUM_IN_PHY_REG_PG_5G]; | |
0c817338 LF |
1121 | u8 default_initialgain[4]; |
1122 | ||
e97b775d | 1123 | /* the current Tx power level */ |
0c817338 LF |
1124 | u8 cur_cck_txpwridx; |
1125 | u8 cur_ofdm24g_txpwridx; | |
26634c4b LF |
1126 | u8 cur_bw20_txpwridx; |
1127 | u8 cur_bw40_txpwridx; | |
0c817338 LF |
1128 | |
1129 | u32 rfreg_chnlval[2]; | |
7ea47240 | 1130 | bool apk_done; |
e97b775d | 1131 | u32 reg_rf3c[2]; /* pathA / pathB */ |
0c817338 | 1132 | |
f3355dd9 | 1133 | u32 backup_rf_0x1a;/*92ee*/ |
3dad618b | 1134 | /* bfsync */ |
0c817338 LF |
1135 | u8 framesync; |
1136 | u32 framesync_c34; | |
1137 | ||
1138 | u8 num_total_rfpath; | |
18d30067 | 1139 | struct phy_parameters hwparam_tables[MAX_TAB]; |
e97b775d | 1140 | u16 rf_pathmap; |
0f015453 | 1141 | |
f3355dd9 | 1142 | u8 hw_rof_enable; /*Enable GPIO[9] as WL RF HW PDn source*/ |
0f015453 | 1143 | enum rt_polarity_ctl polarity_ctl; |
0c817338 LF |
1144 | }; |
1145 | ||
1146 | #define MAX_TID_COUNT 9 | |
3dad618b C |
1147 | #define RTL_AGG_STOP 0 |
1148 | #define RTL_AGG_PROGRESS 1 | |
1149 | #define RTL_AGG_START 2 | |
1150 | #define RTL_AGG_OPERATIONAL 3 | |
0c817338 LF |
1151 | #define RTL_AGG_OFF 0 |
1152 | #define RTL_AGG_ON 1 | |
2461c7d6 LF |
1153 | #define RTL_RX_AGG_START 1 |
1154 | #define RTL_RX_AGG_STOP 0 | |
0c817338 LF |
1155 | #define RTL_AGG_EMPTYING_HW_QUEUE_ADDBA 2 |
1156 | #define RTL_AGG_EMPTYING_HW_QUEUE_DELBA 3 | |
1157 | ||
1158 | struct rtl_ht_agg { | |
1159 | u16 txq_id; | |
1160 | u16 wait_for_ba; | |
1161 | u16 start_idx; | |
1162 | u64 bitmap; | |
1163 | u32 rate_n_flags; | |
1164 | u8 agg_state; | |
2461c7d6 | 1165 | u8 rx_agg_state; |
0c817338 LF |
1166 | }; |
1167 | ||
26634c4b LF |
1168 | struct rssi_sta { |
1169 | long undec_sm_pwdb; | |
b9a758a8 | 1170 | long undec_sm_cck; |
26634c4b LF |
1171 | }; |
1172 | ||
0c817338 LF |
1173 | struct rtl_tid_data { |
1174 | u16 seq_number; | |
1175 | struct rtl_ht_agg agg; | |
1176 | }; | |
1177 | ||
3dad618b | 1178 | struct rtl_sta_info { |
2461c7d6 | 1179 | struct list_head list; |
3dad618b C |
1180 | u8 ratr_index; |
1181 | u8 wireless_mode; | |
1182 | u8 mimo_ps; | |
26634c4b | 1183 | u8 mac_addr[ETH_ALEN]; |
3dad618b | 1184 | struct rtl_tid_data tids[MAX_TID_COUNT]; |
2461c7d6 LF |
1185 | |
1186 | /* just used for ap adhoc or mesh*/ | |
1187 | struct rssi_sta rssi_stat; | |
3dad618b C |
1188 | } __packed; |
1189 | ||
0c817338 LF |
1190 | struct rtl_priv; |
1191 | struct rtl_io { | |
1192 | struct device *dev; | |
62e63975 | 1193 | struct mutex bb_mutex; |
0c817338 LF |
1194 | |
1195 | /*PCI MEM map */ | |
1196 | unsigned long pci_mem_end; /*shared mem end */ | |
1197 | unsigned long pci_mem_start; /*shared mem start */ | |
1198 | ||
1199 | /*PCI IO map */ | |
1200 | unsigned long pci_base_addr; /*device I/O address */ | |
1201 | ||
1202 | void (*write8_async) (struct rtl_priv *rtlpriv, u32 addr, u8 val); | |
ff6ff96b LF |
1203 | void (*write16_async) (struct rtl_priv *rtlpriv, u32 addr, u16 val); |
1204 | void (*write32_async) (struct rtl_priv *rtlpriv, u32 addr, u32 val); | |
1205 | void (*writeN_sync) (struct rtl_priv *rtlpriv, u32 addr, void *buf, | |
1206 | u16 len); | |
0c817338 | 1207 | |
e97b775d LF |
1208 | u8(*read8_sync) (struct rtl_priv *rtlpriv, u32 addr); |
1209 | u16(*read16_sync) (struct rtl_priv *rtlpriv, u32 addr); | |
1210 | u32(*read32_sync) (struct rtl_priv *rtlpriv, u32 addr); | |
3dad618b | 1211 | |
0c817338 LF |
1212 | }; |
1213 | ||
1214 | struct rtl_mac { | |
1215 | u8 mac_addr[ETH_ALEN]; | |
1216 | u8 mac80211_registered; | |
1217 | u8 beacon_enabled; | |
1218 | ||
1219 | u32 tx_ss_num; | |
1220 | u32 rx_ss_num; | |
1221 | ||
1222 | struct ieee80211_supported_band bands[IEEE80211_NUM_BANDS]; | |
1223 | struct ieee80211_hw *hw; | |
1224 | struct ieee80211_vif *vif; | |
1225 | enum nl80211_iftype opmode; | |
1226 | ||
1227 | /*Probe Beacon management */ | |
1228 | struct rtl_tid_data tids[MAX_TID_COUNT]; | |
1229 | enum rtl_link_state link_state; | |
1230 | ||
1231 | int n_channels; | |
1232 | int n_bitrates; | |
1233 | ||
9c050440 | 1234 | bool offchan_delay; |
26634c4b LF |
1235 | u8 p2p; /*using p2p role*/ |
1236 | bool p2p_in_use; | |
3dad618b | 1237 | |
0c817338 LF |
1238 | /*filters */ |
1239 | u32 rx_conf; | |
1240 | u16 rx_mgt_filter; | |
1241 | u16 rx_ctrl_filter; | |
1242 | u16 rx_data_filter; | |
1243 | ||
1244 | bool act_scanning; | |
1245 | u8 cnt_after_linked; | |
26634c4b | 1246 | bool skip_scan; |
0c817338 | 1247 | |
e97b775d LF |
1248 | /* early mode */ |
1249 | /* skb wait queue */ | |
1250 | struct sk_buff_head skb_waitq[MAX_TID_COUNT]; | |
e97b775d LF |
1251 | |
1252 | /*RDG*/ | |
1253 | bool rdg_en; | |
0c817338 | 1254 | |
e97b775d LF |
1255 | /*AP*/ |
1256 | u8 bssid[6]; | |
1257 | u32 vendor; | |
1258 | u8 mcs[16]; /* 16 bytes mcs for HT rates. */ | |
1259 | u32 basic_rates; /* b/g rates */ | |
0c817338 LF |
1260 | u8 ht_enable; |
1261 | u8 sgi_40; | |
1262 | u8 sgi_20; | |
1263 | u8 bw_40; | |
e97b775d | 1264 | u8 mode; /* wireless mode */ |
0c817338 LF |
1265 | u8 slot_time; |
1266 | u8 short_preamble; | |
1267 | u8 use_cts_protect; | |
1268 | u8 cur_40_prime_sc; | |
1269 | u8 cur_40_prime_sc_bk; | |
f3355dd9 | 1270 | u8 cur_80_prime_sc; |
0c817338 LF |
1271 | u64 tsf; |
1272 | u8 retry_short; | |
1273 | u8 retry_long; | |
1274 | u16 assoc_id; | |
26634c4b | 1275 | bool hiddenssid; |
0c817338 | 1276 | |
e97b775d LF |
1277 | /*IBSS*/ |
1278 | int beacon_interval; | |
0c817338 | 1279 | |
e97b775d LF |
1280 | /*AMPDU*/ |
1281 | u8 min_space_cfg; /*For Min spacing configurations */ | |
0c817338 LF |
1282 | u8 max_mss_density; |
1283 | u8 current_ampdu_factor; | |
1284 | u8 current_ampdu_density; | |
1285 | ||
1286 | /*QOS & EDCA */ | |
1287 | struct ieee80211_tx_queue_params edca_param[RTL_MAC80211_NUM_QUEUE]; | |
1288 | struct rtl_qos_parameters ac[AC_MAX]; | |
0f015453 LF |
1289 | |
1290 | /* counters */ | |
1291 | u64 last_txok_cnt; | |
1292 | u64 last_rxok_cnt; | |
1293 | u32 last_bt_edca_ul; | |
1294 | u32 last_bt_edca_dl; | |
1295 | }; | |
1296 | ||
1297 | struct btdm_8723 { | |
1298 | bool all_off; | |
1299 | bool agc_table_en; | |
1300 | bool adc_back_off_on; | |
1301 | bool b2_ant_hid_en; | |
1302 | bool low_penalty_rate_adaptive; | |
1303 | bool rf_rx_lpf_shrink; | |
1304 | bool reject_aggre_pkt; | |
1305 | bool tra_tdma_on; | |
1306 | u8 tra_tdma_nav; | |
1307 | u8 tra_tdma_ant; | |
1308 | bool tdma_on; | |
1309 | u8 tdma_ant; | |
1310 | u8 tdma_nav; | |
1311 | u8 tdma_dac_swing; | |
1312 | u8 fw_dac_swing_lvl; | |
1313 | bool ps_tdma_on; | |
1314 | u8 ps_tdma_byte[5]; | |
1315 | bool pta_on; | |
1316 | u32 val_0x6c0; | |
1317 | u32 val_0x6c8; | |
1318 | u32 val_0x6cc; | |
1319 | bool sw_dac_swing_on; | |
1320 | u32 sw_dac_swing_lvl; | |
1321 | u32 wlan_act_hi; | |
1322 | u32 wlan_act_lo; | |
1323 | u32 bt_retry_index; | |
1324 | bool dec_bt_pwr; | |
1325 | bool ignore_wlan_act; | |
1326 | }; | |
1327 | ||
1328 | struct bt_coexist_8723 { | |
1329 | u32 high_priority_tx; | |
1330 | u32 high_priority_rx; | |
1331 | u32 low_priority_tx; | |
1332 | u32 low_priority_rx; | |
1333 | u8 c2h_bt_info; | |
1334 | bool c2h_bt_info_req_sent; | |
1335 | bool c2h_bt_inquiry_page; | |
1336 | u32 bt_inq_page_start_time; | |
1337 | u8 bt_retry_cnt; | |
1338 | u8 c2h_bt_info_original; | |
1339 | u8 bt_inquiry_page_cnt; | |
1340 | struct btdm_8723 btdm; | |
0c817338 LF |
1341 | }; |
1342 | ||
1343 | struct rtl_hal { | |
1344 | struct ieee80211_hw *hw; | |
26634c4b | 1345 | bool driver_is_goingto_unload; |
2461c7d6 | 1346 | bool up_first_time; |
26634c4b | 1347 | bool first_init; |
2461c7d6 LF |
1348 | bool being_init_adapter; |
1349 | bool bbrf_ready; | |
26634c4b | 1350 | bool mac_func_enable; |
2cddad3c | 1351 | bool pre_edcca_enable; |
26634c4b | 1352 | struct bt_coexist_8723 hal_coex_8723; |
2461c7d6 | 1353 | |
0c817338 LF |
1354 | enum intf_type interface; |
1355 | u16 hw_type; /*92c or 92d or 92s and so on */ | |
e97b775d | 1356 | u8 ic_class; |
0c817338 | 1357 | u8 oem_id; |
18d30067 | 1358 | u32 version; /*version of chip */ |
0c817338 | 1359 | u8 state; /*stop 0, start 1 */ |
26634c4b | 1360 | u8 board_type; |
0c817338 LF |
1361 | |
1362 | /*firmware */ | |
e97b775d | 1363 | u32 fwsize; |
0c817338 | 1364 | u8 *pfirmware; |
18d30067 G |
1365 | u16 fw_version; |
1366 | u16 fw_subversion; | |
7ea47240 | 1367 | bool h2c_setinprogress; |
0c817338 | 1368 | u8 last_hmeboxnum; |
2461c7d6 | 1369 | bool fw_ready; |
0c817338 LF |
1370 | /*Reserve page start offset except beacon in TxQ. */ |
1371 | u8 fw_rsvdpage_startoffset; | |
e97b775d | 1372 | u8 h2c_txcmd_seq; |
f3355dd9 | 1373 | u8 current_ra_rate; |
e97b775d LF |
1374 | |
1375 | /* FW Cmd IO related */ | |
1376 | u16 fwcmd_iomap; | |
1377 | u32 fwcmd_ioparam; | |
1378 | bool set_fwcmd_inprogress; | |
1379 | u8 current_fwcmd_io; | |
1380 | ||
4b04edc1 | 1381 | struct p2p_ps_offload_t p2p_ps_offload; |
26634c4b LF |
1382 | bool fw_clk_change_in_progress; |
1383 | bool allow_sw_to_change_hwclc; | |
1384 | u8 fw_ps_state; | |
e97b775d LF |
1385 | /**/ |
1386 | bool driver_going2unload; | |
1387 | ||
1388 | /*AMPDU init min space*/ | |
1389 | u8 minspace_cfg; /*For Min spacing configurations */ | |
1390 | ||
1391 | /* Dual mac */ | |
1392 | enum macphy_mode macphymode; | |
1393 | enum band_type current_bandtype; /* 0:2.4G, 1:5G */ | |
1394 | enum band_type current_bandtypebackup; | |
1395 | enum band_type bandset; | |
1396 | /* dual MAC 0--Mac0 1--Mac1 */ | |
1397 | u32 interfaceindex; | |
1398 | /* just for DualMac S3S4 */ | |
1399 | u8 macphyctl_reg; | |
1400 | bool earlymode_enable; | |
26634c4b | 1401 | u8 max_earlymode_num; |
e97b775d LF |
1402 | /* Dual mac*/ |
1403 | bool during_mac0init_radiob; | |
1404 | bool during_mac1init_radioa; | |
1405 | bool reloadtxpowerindex; | |
1406 | /* True if IMR or IQK have done | |
1407 | for 2.4G in scan progress */ | |
1408 | bool load_imrandiqk_setting_for2g; | |
1409 | ||
1410 | bool disable_amsdu_8k; | |
2461c7d6 LF |
1411 | bool master_of_dmsp; |
1412 | bool slave_of_dmsp; | |
f3355dd9 LF |
1413 | |
1414 | u16 rx_tag;/*for 92ee*/ | |
1415 | u8 rts_en; | |
0c817338 LF |
1416 | }; |
1417 | ||
1418 | struct rtl_security { | |
1419 | /*default 0 */ | |
1420 | bool use_sw_sec; | |
1421 | ||
1422 | bool being_setkey; | |
1423 | bool use_defaultkey; | |
1424 | /*Encryption Algorithm for Unicast Packet */ | |
1425 | enum rt_enc_alg pairwise_enc_algorithm; | |
1426 | /*Encryption Algorithm for Brocast/Multicast */ | |
1427 | enum rt_enc_alg group_enc_algorithm; | |
3dad618b C |
1428 | /*Cam Entry Bitmap */ |
1429 | u32 hwsec_cam_bitmap; | |
1430 | u8 hwsec_cam_sta_addr[TOTAL_CAM_ENTRY][ETH_ALEN]; | |
0c817338 LF |
1431 | /*local Key buffer, indx 0 is for |
1432 | pairwise key 1-4 is for agoup key. */ | |
1433 | u8 key_buf[KEY_BUF_SIZE][MAX_KEY_LEN]; | |
1434 | u8 key_len[KEY_BUF_SIZE]; | |
1435 | ||
1436 | /*The pointer of Pairwise Key, | |
1437 | it always points to KeyBuf[4] */ | |
1438 | u8 *pairwise_key; | |
1439 | }; | |
1440 | ||
e6deaf81 LF |
1441 | #define ASSOCIATE_ENTRY_NUM 33 |
1442 | ||
1443 | struct fast_ant_training { | |
1444 | u8 bssid[6]; | |
1445 | u8 antsel_rx_keep_0; | |
1446 | u8 antsel_rx_keep_1; | |
1447 | u8 antsel_rx_keep_2; | |
1448 | u32 ant_sum[7]; | |
1449 | u32 ant_cnt[7]; | |
1450 | u32 ant_ave[7]; | |
1451 | u8 fat_state; | |
1452 | u32 train_idx; | |
1453 | u8 antsel_a[ASSOCIATE_ENTRY_NUM]; | |
1454 | u8 antsel_b[ASSOCIATE_ENTRY_NUM]; | |
1455 | u8 antsel_c[ASSOCIATE_ENTRY_NUM]; | |
1456 | u32 main_ant_sum[ASSOCIATE_ENTRY_NUM]; | |
1457 | u32 aux_ant_sum[ASSOCIATE_ENTRY_NUM]; | |
1458 | u32 main_ant_cnt[ASSOCIATE_ENTRY_NUM]; | |
1459 | u32 aux_ant_cnt[ASSOCIATE_ENTRY_NUM]; | |
1460 | u8 rx_idle_ant; | |
1461 | bool becomelinked; | |
1462 | }; | |
1463 | ||
2cddad3c LF |
1464 | struct dm_phy_dbg_info { |
1465 | char rx_snrdb[4]; | |
1466 | u64 num_qry_phy_status; | |
1467 | u64 num_qry_phy_status_cck; | |
1468 | u64 num_qry_phy_status_ofdm; | |
1469 | u16 num_qry_beacon_pkt; | |
1470 | u16 num_non_be_pkt; | |
1471 | s32 rx_evm[4]; | |
1472 | }; | |
1473 | ||
0c817338 | 1474 | struct rtl_dm { |
e97b775d | 1475 | /*PHY status for Dynamic Management */ |
da17fcff | 1476 | long entry_min_undec_sm_pwdb; |
b9a758a8 | 1477 | long undec_sm_cck; |
da17fcff LF |
1478 | long undec_sm_pwdb; /*out dm */ |
1479 | long entry_max_undec_sm_pwdb; | |
b9a758a8 | 1480 | s32 ofdm_pkt_cnt; |
7ea47240 LF |
1481 | bool dm_initialgain_enable; |
1482 | bool dynamic_txpower_enable; | |
1483 | bool current_turbo_edca; | |
1484 | bool is_any_nonbepkts; /*out dm */ | |
1485 | bool is_cur_rdlstate; | |
3dad618b | 1486 | bool txpower_trackinginit; |
7ea47240 LF |
1487 | bool disable_framebursting; |
1488 | bool cck_inch14; | |
1489 | bool txpower_tracking; | |
1490 | bool useramask; | |
1491 | bool rfpath_rxenable[4]; | |
e97b775d LF |
1492 | bool inform_fw_driverctrldm; |
1493 | bool current_mrc_switch; | |
1494 | u8 txpowercount; | |
b9a758a8 | 1495 | u8 powerindex_backup[6]; |
0c817338 | 1496 | |
e97b775d | 1497 | u8 thermalvalue_rxgain; |
0c817338 LF |
1498 | u8 thermalvalue_iqk; |
1499 | u8 thermalvalue_lck; | |
1500 | u8 thermalvalue; | |
1501 | u8 last_dtp_lvl; | |
e97b775d LF |
1502 | u8 thermalvalue_avg[AVG_THERMAL_NUM]; |
1503 | u8 thermalvalue_avg_index; | |
1504 | bool done_txpower; | |
0c817338 | 1505 | u8 dynamic_txhighpower_lvl; /*Tx high power level */ |
e97b775d | 1506 | u8 dm_flag; /*Indicate each dynamic mechanism's status. */ |
b9a758a8 | 1507 | u8 dm_flag_tmp; |
0c817338 | 1508 | u8 dm_type; |
b9a758a8 | 1509 | u8 dm_rssi_sel; |
0c817338 | 1510 | u8 txpower_track_control; |
e97b775d LF |
1511 | bool interrupt_migration; |
1512 | bool disable_tx_int; | |
f3355dd9 LF |
1513 | char ofdm_index[MAX_RF_PATH]; |
1514 | u8 default_ofdm_index; | |
1515 | u8 default_cck_index; | |
0c817338 | 1516 | char cck_index; |
2cddad3c LF |
1517 | char delta_power_index[MAX_RF_PATH]; |
1518 | char delta_power_index_last[MAX_RF_PATH]; | |
1519 | char power_index_offset[MAX_RF_PATH]; | |
f3355dd9 LF |
1520 | char absolute_ofdm_swing_idx[MAX_RF_PATH]; |
1521 | char remnant_ofdm_swing_idx[MAX_RF_PATH]; | |
1522 | char remnant_cck_idx; | |
1523 | bool modify_txagc_flag_path_a; | |
1524 | bool modify_txagc_flag_path_b; | |
2cddad3c LF |
1525 | |
1526 | bool one_entry_only; | |
1527 | struct dm_phy_dbg_info dbginfo; | |
1528 | ||
1529 | /* Dynamic ATC switch */ | |
1530 | bool atc_status; | |
1531 | bool large_cfo_hit; | |
1532 | bool is_freeze; | |
1533 | int cfo_tail[2]; | |
1534 | int cfo_ave_pre; | |
1535 | int crystal_cap; | |
1536 | u8 cfo_threshold; | |
1537 | u32 packet_count; | |
1538 | u32 packet_count_pre; | |
f3355dd9 | 1539 | u8 tx_rate; |
e6deaf81 LF |
1540 | |
1541 | /*88e tx power tracking*/ | |
f3355dd9 | 1542 | u8 swing_idx_ofdm[MAX_RF_PATH]; |
e6deaf81 | 1543 | u8 swing_idx_ofdm_cur; |
2cddad3c | 1544 | u8 swing_idx_ofdm_base[MAX_RF_PATH]; |
e6deaf81 LF |
1545 | bool swing_flag_ofdm; |
1546 | u8 swing_idx_cck; | |
1547 | u8 swing_idx_cck_cur; | |
1548 | u8 swing_idx_cck_base; | |
1549 | bool swing_flag_cck; | |
2461c7d6 | 1550 | |
f3355dd9 LF |
1551 | char swing_diff_2g; |
1552 | char swing_diff_5g; | |
1553 | ||
1554 | u8 delta_swing_table_idx_24gccka_p[DEL_SW_IDX_SZ]; | |
1555 | u8 delta_swing_table_idx_24gccka_n[DEL_SW_IDX_SZ]; | |
1556 | u8 delta_swing_table_idx_24gcckb_p[DEL_SW_IDX_SZ]; | |
1557 | u8 delta_swing_table_idx_24gcckb_n[DEL_SW_IDX_SZ]; | |
1558 | u8 delta_swing_table_idx_24ga_p[DEL_SW_IDX_SZ]; | |
1559 | u8 delta_swing_table_idx_24ga_n[DEL_SW_IDX_SZ]; | |
1560 | u8 delta_swing_table_idx_24gb_p[DEL_SW_IDX_SZ]; | |
1561 | u8 delta_swing_table_idx_24gb_n[DEL_SW_IDX_SZ]; | |
1562 | u8 delta_swing_table_idx_5ga_p[BAND_NUM][DEL_SW_IDX_SZ]; | |
1563 | u8 delta_swing_table_idx_5ga_n[BAND_NUM][DEL_SW_IDX_SZ]; | |
1564 | u8 delta_swing_table_idx_5gb_p[BAND_NUM][DEL_SW_IDX_SZ]; | |
1565 | u8 delta_swing_table_idx_5gb_n[BAND_NUM][DEL_SW_IDX_SZ]; | |
1566 | u8 delta_swing_table_idx_24ga_p_8188e[DEL_SW_IDX_SZ]; | |
1567 | u8 delta_swing_table_idx_24ga_n_8188e[DEL_SW_IDX_SZ]; | |
1568 | ||
2461c7d6 LF |
1569 | /* DMSP */ |
1570 | bool supp_phymode_switch; | |
e6deaf81 | 1571 | |
f3355dd9 | 1572 | /* DulMac */ |
e6deaf81 | 1573 | struct fast_ant_training fat_table; |
f3355dd9 LF |
1574 | |
1575 | u8 resp_tx_path; | |
1576 | u8 path_sel; | |
1577 | u32 patha_sum; | |
1578 | u32 pathb_sum; | |
1579 | u32 patha_cnt; | |
1580 | u32 pathb_cnt; | |
1581 | ||
1582 | u8 pre_channel; | |
1583 | u8 *p_channel; | |
1584 | u8 linked_interval; | |
1585 | ||
1586 | u64 last_tx_ok_cnt; | |
1587 | u64 last_rx_ok_cnt; | |
0c817338 LF |
1588 | }; |
1589 | ||
7ce24ab7 | 1590 | #define EFUSE_MAX_LOGICAL_SIZE 512 |
0c817338 LF |
1591 | |
1592 | struct rtl_efuse { | |
e97b775d | 1593 | bool autoLoad_ok; |
0c817338 LF |
1594 | bool bootfromefuse; |
1595 | u16 max_physical_size; | |
0c817338 LF |
1596 | |
1597 | u8 efuse_map[2][EFUSE_MAX_LOGICAL_SIZE]; | |
1598 | u16 efuse_usedbytes; | |
1599 | u8 efuse_usedpercentage; | |
e97b775d LF |
1600 | #ifdef EFUSE_REPG_WORKAROUND |
1601 | bool efuse_re_pg_sec1flag; | |
1602 | u8 efuse_re_pg_data[8]; | |
1603 | #endif | |
0c817338 LF |
1604 | |
1605 | u8 autoload_failflag; | |
e97b775d | 1606 | u8 autoload_status; |
0c817338 LF |
1607 | |
1608 | short epromtype; | |
1609 | u16 eeprom_vid; | |
1610 | u16 eeprom_did; | |
1611 | u16 eeprom_svid; | |
1612 | u16 eeprom_smid; | |
1613 | u8 eeprom_oemid; | |
1614 | u16 eeprom_channelplan; | |
1615 | u8 eeprom_version; | |
18d30067 G |
1616 | u8 board_type; |
1617 | u8 external_pa; | |
0c817338 LF |
1618 | |
1619 | u8 dev_addr[6]; | |
e6deaf81 LF |
1620 | u8 wowlan_enable; |
1621 | u8 antenna_div_cfg; | |
1622 | u8 antenna_div_type; | |
0c817338 | 1623 | |
7ea47240 | 1624 | bool txpwr_fromeprom; |
e97b775d | 1625 | u8 eeprom_crystalcap; |
0c817338 | 1626 | u8 eeprom_tssi[2]; |
e97b775d LF |
1627 | u8 eeprom_tssi_5g[3][2]; /* for 5GL/5GM/5GH band. */ |
1628 | u8 eeprom_pwrlimit_ht20[CHANNEL_GROUP_MAX]; | |
1629 | u8 eeprom_pwrlimit_ht40[CHANNEL_GROUP_MAX]; | |
2cddad3c LF |
1630 | u8 eeprom_chnlarea_txpwr_cck[MAX_RF_PATH][CHANNEL_GROUP_MAX_2G]; |
1631 | u8 eeprom_chnlarea_txpwr_ht40_1s[MAX_RF_PATH][CHANNEL_GROUP_MAX]; | |
1632 | u8 eprom_chnl_txpwr_ht40_2sdf[MAX_RF_PATH][CHANNEL_GROUP_MAX]; | |
e97b775d LF |
1633 | |
1634 | u8 internal_pa_5g[2]; /* pathA / pathB */ | |
1635 | u8 eeprom_c9; | |
1636 | u8 eeprom_cc; | |
0c817338 LF |
1637 | |
1638 | /*For power group */ | |
e97b775d LF |
1639 | u8 eeprom_pwrgroup[2][3]; |
1640 | u8 pwrgroup_ht20[2][CHANNEL_MAX_NUMBER]; | |
1641 | u8 pwrgroup_ht40[2][CHANNEL_MAX_NUMBER]; | |
1642 | ||
f3355dd9 LF |
1643 | u8 txpwrlevel_cck[MAX_RF_PATH][CHANNEL_MAX_NUMBER_2G]; |
1644 | /*For HT 40MHZ pwr */ | |
1645 | u8 txpwrlevel_ht40_1s[MAX_RF_PATH][CHANNEL_MAX_NUMBER]; | |
1646 | /*For HT 40MHZ pwr */ | |
1647 | u8 txpwrlevel_ht40_2s[MAX_RF_PATH][CHANNEL_MAX_NUMBER]; | |
1648 | ||
1649 | /*--------------------------------------------------------* | |
1650 | * 8192CE\8192SE\8192DE\8723AE use the following 4 arrays, | |
1651 | * other ICs (8188EE\8723BE\8192EE\8812AE...) | |
1652 | * define new arrays in Windows code. | |
1653 | * BUT, in linux code, we use the same array for all ICs. | |
1654 | * | |
1655 | * The Correspondance relation between two arrays is: | |
1656 | * txpwr_cckdiff[][] == CCK_24G_Diff[][] | |
1657 | * txpwr_ht20diff[][] == BW20_24G_Diff[][] | |
1658 | * txpwr_ht40diff[][] == BW40_24G_Diff[][] | |
1659 | * txpwr_legacyhtdiff[][] == OFDM_24G_Diff[][] | |
1660 | * | |
1661 | * Sizes of these arrays are decided by the larger ones. | |
1662 | */ | |
1663 | char txpwr_cckdiff[MAX_RF_PATH][CHANNEL_MAX_NUMBER]; | |
1664 | char txpwr_ht20diff[MAX_RF_PATH][CHANNEL_MAX_NUMBER]; | |
1665 | char txpwr_ht40diff[MAX_RF_PATH][CHANNEL_MAX_NUMBER]; | |
1666 | char txpwr_legacyhtdiff[MAX_RF_PATH][CHANNEL_MAX_NUMBER]; | |
1667 | ||
1668 | u8 txpwr_5g_bw40base[MAX_RF_PATH][CHANNEL_MAX_NUMBER]; | |
1669 | u8 txpwr_5g_bw80base[MAX_RF_PATH][CHANNEL_MAX_NUMBER_5G_80M]; | |
1670 | char txpwr_5g_ofdmdiff[MAX_RF_PATH][MAX_TX_COUNT]; | |
1671 | char txpwr_5g_bw20diff[MAX_RF_PATH][MAX_TX_COUNT]; | |
1672 | char txpwr_5g_bw40diff[MAX_RF_PATH][MAX_TX_COUNT]; | |
1673 | char txpwr_5g_bw80diff[MAX_RF_PATH][MAX_TX_COUNT]; | |
1674 | ||
e97b775d LF |
1675 | u8 txpwr_safetyflag; /* Band edge enable flag */ |
1676 | u16 eeprom_txpowerdiff; | |
1677 | u8 legacy_httxpowerdiff; /* Legacy to HT rate power diff */ | |
1678 | u8 antenna_txpwdiff[3]; | |
0c817338 LF |
1679 | |
1680 | u8 eeprom_regulatory; | |
1681 | u8 eeprom_thermalmeter; | |
e97b775d LF |
1682 | u8 thermalmeter[2]; /*ThermalMeter, index 0 for RFIC0, 1 for RFIC1 */ |
1683 | u16 tssi_13dbm; | |
1684 | u8 crystalcap; /* CrystalCap. */ | |
1685 | u8 delta_iqk; | |
1686 | u8 delta_lck; | |
0c817338 LF |
1687 | |
1688 | u8 legacy_ht_txpowerdiff; /*Legacy to HT rate power diff */ | |
7ea47240 | 1689 | bool apk_thermalmeterignore; |
e97b775d LF |
1690 | |
1691 | bool b1x1_recvcombine; | |
1692 | bool b1ss_support; | |
1693 | ||
1694 | /*channel plan */ | |
1695 | u8 channel_plan; | |
0c817338 LF |
1696 | }; |
1697 | ||
1698 | struct rtl_ps_ctl { | |
e97b775d | 1699 | bool pwrdomain_protect; |
7ea47240 | 1700 | bool in_powersavemode; |
0c817338 | 1701 | bool rfchange_inprogress; |
7ea47240 LF |
1702 | bool swrf_processing; |
1703 | bool hwradiooff; | |
0c817338 LF |
1704 | /* |
1705 | * just for PCIE ASPM | |
1706 | * If it supports ASPM, Offset[560h] = 0x40, | |
1707 | * otherwise Offset[560h] = 0x00. | |
1708 | * */ | |
7ea47240 LF |
1709 | bool support_aspm; |
1710 | bool support_backdoor; | |
0c817338 LF |
1711 | |
1712 | /*for LPS */ | |
1713 | enum rt_psmode dot11_psmode; /*Power save mode configured. */ | |
e97b775d | 1714 | bool swctrl_lps; |
7ea47240 LF |
1715 | bool leisure_ps; |
1716 | bool fwctrl_lps; | |
0c817338 LF |
1717 | u8 fwctrl_psmode; |
1718 | /*For Fw control LPS mode */ | |
7ea47240 | 1719 | u8 reg_fwctrl_lps; |
0c817338 | 1720 | /*Record Fw PS mode status. */ |
7ea47240 | 1721 | bool fw_current_inpsmode; |
0c817338 LF |
1722 | u8 reg_max_lps_awakeintvl; |
1723 | bool report_linked; | |
26634c4b | 1724 | bool low_power_enable;/*for 32k*/ |
0c817338 LF |
1725 | |
1726 | /*for IPS */ | |
7ea47240 | 1727 | bool inactiveps; |
0c817338 LF |
1728 | |
1729 | u32 rfoff_reason; | |
1730 | ||
1731 | /*RF OFF Level */ | |
1732 | u32 cur_ps_level; | |
1733 | u32 reg_rfps_level; | |
1734 | ||
1735 | /*just for PCIE ASPM */ | |
1736 | u8 const_amdpci_aspm; | |
18d30067 | 1737 | bool pwrdown_mode; |
e97b775d | 1738 | |
0c817338 LF |
1739 | enum rf_pwrstate inactive_pwrstate; |
1740 | enum rf_pwrstate rfpwr_state; /*cur power state */ | |
e97b775d LF |
1741 | |
1742 | /* for SW LPS*/ | |
1743 | bool sw_ps_enabled; | |
1744 | bool state; | |
1745 | bool state_inap; | |
1746 | bool multi_buffered; | |
1747 | u16 nullfunc_seq; | |
1748 | unsigned int dtim_counter; | |
1749 | unsigned int sleep_ms; | |
1750 | unsigned long last_sleep_jiffies; | |
1751 | unsigned long last_awake_jiffies; | |
1752 | unsigned long last_delaylps_stamp_jiffies; | |
1753 | unsigned long last_dtim; | |
1754 | unsigned long last_beacon; | |
1755 | unsigned long last_action; | |
1756 | unsigned long last_slept; | |
26634c4b LF |
1757 | |
1758 | /*For P2P PS */ | |
1759 | struct rtl_p2p_ps_info p2p_ps_info; | |
1760 | u8 pwr_mode; | |
1761 | u8 smart_ps; | |
0c817338 LF |
1762 | }; |
1763 | ||
1764 | struct rtl_stats { | |
0f015453 | 1765 | u8 psaddr[ETH_ALEN]; |
0c817338 LF |
1766 | u32 mac_time[2]; |
1767 | s8 rssi; | |
1768 | u8 signal; | |
1769 | u8 noise; | |
e6deaf81 | 1770 | u8 rate; /* hw desc rate */ |
0c817338 LF |
1771 | u8 received_channel; |
1772 | u8 control; | |
1773 | u8 mask; | |
1774 | u8 freq; | |
1775 | u16 len; | |
1776 | u64 tsf; | |
1777 | u32 beacon_time; | |
1778 | u8 nic_type; | |
1779 | u16 length; | |
1780 | u8 signalquality; /*in 0-100 index. */ | |
1781 | /* | |
1782 | * Real power in dBm for this packet, | |
1783 | * no beautification and aggregation. | |
1784 | * */ | |
1785 | s32 recvsignalpower; | |
1786 | s8 rxpower; /*in dBm Translate from PWdB */ | |
1787 | u8 signalstrength; /*in 0-100 index. */ | |
7ea47240 LF |
1788 | u16 hwerror:1; |
1789 | u16 crc:1; | |
1790 | u16 icv:1; | |
1791 | u16 shortpreamble:1; | |
0c817338 LF |
1792 | u16 antenna:1; |
1793 | u16 decrypted:1; | |
1794 | u16 wakeup:1; | |
1795 | u32 timestamp_low; | |
1796 | u32 timestamp_high; | |
1797 | ||
1798 | u8 rx_drvinfo_size; | |
1799 | u8 rx_bufshift; | |
7ea47240 | 1800 | bool isampdu; |
e97b775d | 1801 | bool isfirst_ampdu; |
0c817338 LF |
1802 | bool rx_is40Mhzpacket; |
1803 | u32 rx_pwdb_all; | |
1804 | u8 rx_mimo_signalstrength[4]; /*in 0~100 index */ | |
f3355dd9 LF |
1805 | s8 rx_mimo_sig_qual[4]; |
1806 | u8 rx_pwr[4]; /* per-path's pwdb */ | |
1807 | u8 rx_snr[4]; /* per-path's SNR */ | |
7ea47240 LF |
1808 | bool packet_matchbssid; |
1809 | bool is_cck; | |
5c079d88 | 1810 | bool is_ht; |
7ea47240 LF |
1811 | bool packet_toself; |
1812 | bool packet_beacon; /*for rssi */ | |
0c817338 | 1813 | char cck_adc_pwdb[4]; /*for rx path selection */ |
e6deaf81 LF |
1814 | |
1815 | u8 packet_report_type; | |
1816 | ||
1817 | u32 macid; | |
1818 | u8 wake_match; | |
1819 | u32 bt_rx_rssi_percentage; | |
1820 | u32 macid_valid_entry[2]; | |
0c817338 LF |
1821 | }; |
1822 | ||
e6deaf81 | 1823 | |
0c817338 | 1824 | struct rt_link_detect { |
2461c7d6 LF |
1825 | /* count for roaming */ |
1826 | u32 bcn_rx_inperiod; | |
1827 | u32 roam_times; | |
1828 | ||
0c817338 LF |
1829 | u32 num_tx_in4period[4]; |
1830 | u32 num_rx_in4period[4]; | |
1831 | ||
1832 | u32 num_tx_inperiod; | |
1833 | u32 num_rx_inperiod; | |
1834 | ||
7ea47240 | 1835 | bool busytraffic; |
2461c7d6 LF |
1836 | bool tx_busy_traffic; |
1837 | bool rx_busy_traffic; | |
7ea47240 LF |
1838 | bool higher_busytraffic; |
1839 | bool higher_busyrxtraffic; | |
3dad618b C |
1840 | |
1841 | u32 tidtx_in4period[MAX_TID_COUNT][4]; | |
1842 | u32 tidtx_inperiod[MAX_TID_COUNT]; | |
1843 | bool higher_busytxtraffic[MAX_TID_COUNT]; | |
0c817338 LF |
1844 | }; |
1845 | ||
1846 | struct rtl_tcb_desc { | |
7ea47240 LF |
1847 | u8 packet_bw:1; |
1848 | u8 multicast:1; | |
1849 | u8 broadcast:1; | |
1850 | ||
1851 | u8 rts_stbc:1; | |
1852 | u8 rts_enable:1; | |
1853 | u8 cts_enable:1; | |
1854 | u8 rts_use_shortpreamble:1; | |
1855 | u8 rts_use_shortgi:1; | |
0c817338 | 1856 | u8 rts_sc:1; |
7ea47240 | 1857 | u8 rts_bw:1; |
0c817338 LF |
1858 | u8 rts_rate; |
1859 | ||
1860 | u8 use_shortgi:1; | |
1861 | u8 use_shortpreamble:1; | |
1862 | u8 use_driver_rate:1; | |
1863 | u8 disable_ratefallback:1; | |
1864 | ||
1865 | u8 ratr_index; | |
1866 | u8 mac_id; | |
1867 | u8 hw_rate; | |
e97b775d LF |
1868 | |
1869 | u8 last_inipkt:1; | |
1870 | u8 cmd_or_init:1; | |
1871 | u8 queue_index; | |
1872 | ||
1873 | /* early mode */ | |
1874 | u8 empkt_num; | |
1875 | /* The max value by HW */ | |
e6deaf81 LF |
1876 | u32 empkt_len[10]; |
1877 | bool btx_enable_sw_calc_duration; | |
0c817338 LF |
1878 | }; |
1879 | ||
cbd0c851 LF |
1880 | struct rtl92c_firmware_header; |
1881 | ||
0c817338 LF |
1882 | struct rtl_hal_ops { |
1883 | int (*init_sw_vars) (struct ieee80211_hw *hw); | |
1884 | void (*deinit_sw_vars) (struct ieee80211_hw *hw); | |
62e63975 | 1885 | void (*read_chip_version)(struct ieee80211_hw *hw); |
0c817338 LF |
1886 | void (*read_eeprom_info) (struct ieee80211_hw *hw); |
1887 | void (*interrupt_recognized) (struct ieee80211_hw *hw, | |
1888 | u32 *p_inta, u32 *p_intb); | |
1889 | int (*hw_init) (struct ieee80211_hw *hw); | |
1890 | void (*hw_disable) (struct ieee80211_hw *hw); | |
e97b775d LF |
1891 | void (*hw_suspend) (struct ieee80211_hw *hw); |
1892 | void (*hw_resume) (struct ieee80211_hw *hw); | |
0c817338 LF |
1893 | void (*enable_interrupt) (struct ieee80211_hw *hw); |
1894 | void (*disable_interrupt) (struct ieee80211_hw *hw); | |
1895 | int (*set_network_type) (struct ieee80211_hw *hw, | |
1896 | enum nl80211_iftype type); | |
18d30067 G |
1897 | void (*set_chk_bssid)(struct ieee80211_hw *hw, |
1898 | bool check_bssid); | |
0c817338 LF |
1899 | void (*set_bw_mode) (struct ieee80211_hw *hw, |
1900 | enum nl80211_channel_type ch_type); | |
e97b775d | 1901 | u8(*switch_channel) (struct ieee80211_hw *hw); |
0c817338 LF |
1902 | void (*set_qos) (struct ieee80211_hw *hw, int aci); |
1903 | void (*set_bcn_reg) (struct ieee80211_hw *hw); | |
1904 | void (*set_bcn_intv) (struct ieee80211_hw *hw); | |
1905 | void (*update_interrupt_mask) (struct ieee80211_hw *hw, | |
1906 | u32 add_msr, u32 rm_msr); | |
1907 | void (*get_hw_reg) (struct ieee80211_hw *hw, u8 variable, u8 *val); | |
1908 | void (*set_hw_reg) (struct ieee80211_hw *hw, u8 variable, u8 *val); | |
3dad618b C |
1909 | void (*update_rate_tbl) (struct ieee80211_hw *hw, |
1910 | struct ieee80211_sta *sta, u8 rssi_level); | |
f3355dd9 LF |
1911 | void (*pre_fill_tx_bd_desc)(struct ieee80211_hw *hw, u8 *tx_bd_desc, |
1912 | u8 *desc, u8 queue_index, | |
1913 | struct sk_buff *skb, dma_addr_t addr); | |
0c817338 | 1914 | void (*update_rate_mask) (struct ieee80211_hw *hw, u8 rssi_level); |
f3355dd9 LF |
1915 | u16 (*rx_desc_buff_remained_cnt)(struct ieee80211_hw *hw, |
1916 | u8 queue_index); | |
1917 | void (*rx_check_dma_ok)(struct ieee80211_hw *hw, u8 *header_desc, | |
1918 | u8 queue_index); | |
0c817338 LF |
1919 | void (*fill_tx_desc) (struct ieee80211_hw *hw, |
1920 | struct ieee80211_hdr *hdr, u8 *pdesc_tx, | |
f3355dd9 | 1921 | u8 *pbd_desc_tx, |
0c817338 | 1922 | struct ieee80211_tx_info *info, |
36323f81 | 1923 | struct ieee80211_sta *sta, |
3dad618b C |
1924 | struct sk_buff *skb, u8 hw_queue, |
1925 | struct rtl_tcb_desc *ptcb_desc); | |
3dad618b | 1926 | void (*fill_fake_txdesc) (struct ieee80211_hw *hw, u8 *pDesc, |
18d30067 | 1927 | u32 buffer_len, bool bIsPsPoll); |
0c817338 | 1928 | void (*fill_tx_cmddesc) (struct ieee80211_hw *hw, u8 *pdesc, |
7ea47240 | 1929 | bool firstseg, bool lastseg, |
0c817338 | 1930 | struct sk_buff *skb); |
62e63975 | 1931 | bool (*cmd_send_packet)(struct ieee80211_hw *hw, struct sk_buff *skb); |
7ea47240 | 1932 | bool (*query_rx_desc) (struct ieee80211_hw *hw, |
0c817338 LF |
1933 | struct rtl_stats *stats, |
1934 | struct ieee80211_rx_status *rx_status, | |
1935 | u8 *pdesc, struct sk_buff *skb); | |
1936 | void (*set_channel_access) (struct ieee80211_hw *hw); | |
7ea47240 | 1937 | bool (*radio_onoff_checking) (struct ieee80211_hw *hw, u8 *valid); |
0c817338 LF |
1938 | void (*dm_watchdog) (struct ieee80211_hw *hw); |
1939 | void (*scan_operation_backup) (struct ieee80211_hw *hw, u8 operation); | |
7ea47240 | 1940 | bool (*set_rf_power_state) (struct ieee80211_hw *hw, |
0c817338 LF |
1941 | enum rf_pwrstate rfpwr_state); |
1942 | void (*led_control) (struct ieee80211_hw *hw, | |
1943 | enum led_ctl_mode ledaction); | |
f3355dd9 LF |
1944 | void (*set_desc)(struct ieee80211_hw *hw, u8 *pdesc, bool istx, |
1945 | u8 desc_name, u8 *val); | |
7ea47240 | 1946 | u32 (*get_desc) (u8 *pdesc, bool istx, u8 desc_name); |
2cddad3c LF |
1947 | bool (*is_tx_desc_closed) (struct ieee80211_hw *hw, |
1948 | u8 hw_queue, u16 index); | |
3dad618b | 1949 | void (*tx_polling) (struct ieee80211_hw *hw, u8 hw_queue); |
0c817338 LF |
1950 | void (*enable_hw_sec) (struct ieee80211_hw *hw); |
1951 | void (*set_key) (struct ieee80211_hw *hw, u32 key_index, | |
3dad618b | 1952 | u8 *macaddr, bool is_group, u8 enc_algo, |
0c817338 LF |
1953 | bool is_wepkey, bool clear_all); |
1954 | void (*init_sw_leds) (struct ieee80211_hw *hw); | |
1955 | void (*deinit_sw_leds) (struct ieee80211_hw *hw); | |
7ea47240 | 1956 | u32 (*get_bbreg) (struct ieee80211_hw *hw, u32 regaddr, u32 bitmask); |
0c817338 LF |
1957 | void (*set_bbreg) (struct ieee80211_hw *hw, u32 regaddr, u32 bitmask, |
1958 | u32 data); | |
7ea47240 | 1959 | u32 (*get_rfreg) (struct ieee80211_hw *hw, enum radio_path rfpath, |
0c817338 LF |
1960 | u32 regaddr, u32 bitmask); |
1961 | void (*set_rfreg) (struct ieee80211_hw *hw, enum radio_path rfpath, | |
1962 | u32 regaddr, u32 bitmask, u32 data); | |
3dad618b | 1963 | void (*linked_set_reg) (struct ieee80211_hw *hw); |
26634c4b | 1964 | void (*chk_switch_dmdp) (struct ieee80211_hw *hw); |
2461c7d6 LF |
1965 | void (*dualmac_easy_concurrent) (struct ieee80211_hw *hw); |
1966 | void (*dualmac_switch_to_dmdp) (struct ieee80211_hw *hw); | |
1472d3a8 LF |
1967 | bool (*phy_rf6052_config) (struct ieee80211_hw *hw); |
1968 | void (*phy_rf6052_set_cck_txpower) (struct ieee80211_hw *hw, | |
1969 | u8 *powerlevel); | |
1970 | void (*phy_rf6052_set_ofdm_txpower) (struct ieee80211_hw *hw, | |
1971 | u8 *ppowerlevel, u8 channel); | |
1972 | bool (*config_bb_with_headerfile) (struct ieee80211_hw *hw, | |
1973 | u8 configtype); | |
1974 | bool (*config_bb_with_pgheaderfile) (struct ieee80211_hw *hw, | |
1975 | u8 configtype); | |
1976 | void (*phy_lc_calibrate) (struct ieee80211_hw *hw, bool is2t); | |
1977 | void (*phy_set_bw_mode_callback) (struct ieee80211_hw *hw); | |
1978 | void (*dm_dynamic_txpower) (struct ieee80211_hw *hw); | |
0f015453 | 1979 | void (*c2h_command_handle) (struct ieee80211_hw *hw); |
da17fcff LF |
1980 | void (*bt_wifi_media_status_notify) (struct ieee80211_hw *hw, |
1981 | bool mstate); | |
1982 | void (*bt_coex_off_before_lps) (struct ieee80211_hw *hw); | |
5b8df24e LF |
1983 | void (*fill_h2c_cmd) (struct ieee80211_hw *hw, u8 element_id, |
1984 | u32 cmd_len, u8 *p_cmdbuffer); | |
2cddad3c | 1985 | bool (*get_btc_status) (void); |
cbd0c851 | 1986 | bool (*is_fw_header) (struct rtl92c_firmware_header *hdr); |
f3355dd9 LF |
1987 | u32 (*rx_command_packet)(struct ieee80211_hw *hw, |
1988 | struct rtl_stats status, struct sk_buff *skb); | |
0c817338 LF |
1989 | }; |
1990 | ||
1991 | struct rtl_intf_ops { | |
1992 | /*com */ | |
e97b775d | 1993 | void (*read_efuse_byte)(struct ieee80211_hw *hw, u16 _offset, u8 *pbuf); |
0c817338 LF |
1994 | int (*adapter_start) (struct ieee80211_hw *hw); |
1995 | void (*adapter_stop) (struct ieee80211_hw *hw); | |
2461c7d6 LF |
1996 | bool (*check_buddy_priv)(struct ieee80211_hw *hw, |
1997 | struct rtl_priv **buddy_priv); | |
0c817338 | 1998 | |
36323f81 TH |
1999 | int (*adapter_tx) (struct ieee80211_hw *hw, |
2000 | struct ieee80211_sta *sta, | |
2001 | struct sk_buff *skb, | |
2002 | struct rtl_tcb_desc *ptcb_desc); | |
3dad618b | 2003 | void (*flush)(struct ieee80211_hw *hw, bool drop); |
0c817338 | 2004 | int (*reset_trx_ring) (struct ieee80211_hw *hw); |
36323f81 TH |
2005 | bool (*waitq_insert) (struct ieee80211_hw *hw, |
2006 | struct ieee80211_sta *sta, | |
2007 | struct sk_buff *skb); | |
0c817338 LF |
2008 | |
2009 | /*pci */ | |
2010 | void (*disable_aspm) (struct ieee80211_hw *hw); | |
2011 | void (*enable_aspm) (struct ieee80211_hw *hw); | |
2012 | ||
2013 | /*usb */ | |
2014 | }; | |
2015 | ||
2016 | struct rtl_mod_params { | |
2017 | /* default: 0 = using hardware encryption */ | |
eb939922 | 2018 | bool sw_crypto; |
3dad618b | 2019 | |
73a253ca LF |
2020 | /* default: 0 = DBG_EMERG (0)*/ |
2021 | int debug; | |
2022 | ||
3dad618b C |
2023 | /* default: 1 = using no linked power save */ |
2024 | bool inactiveps; | |
2025 | ||
2026 | /* default: 1 = using linked sw power save */ | |
2027 | bool swctrl_lps; | |
2028 | ||
2029 | /* default: 1 = using linked fw power save */ | |
2030 | bool fwctrl_lps; | |
73070c45 AL |
2031 | |
2032 | /* default: 0 = not using MSI interrupts mode */ | |
2033 | /* submodules should set their own defalut value */ | |
2034 | bool msi_support; | |
0c817338 LF |
2035 | }; |
2036 | ||
62e63975 LF |
2037 | struct rtl_hal_usbint_cfg { |
2038 | /* data - rx */ | |
2039 | u32 in_ep_num; | |
2040 | u32 rx_urb_num; | |
2041 | u32 rx_max_size; | |
2042 | ||
2043 | /* op - rx */ | |
2044 | void (*usb_rx_hdl)(struct ieee80211_hw *, struct sk_buff *); | |
2045 | void (*usb_rx_segregate_hdl)(struct ieee80211_hw *, struct sk_buff *, | |
2046 | struct sk_buff_head *); | |
2047 | ||
2048 | /* tx */ | |
2049 | void (*usb_tx_cleanup)(struct ieee80211_hw *, struct sk_buff *); | |
2050 | int (*usb_tx_post_hdl)(struct ieee80211_hw *, struct urb *, | |
2051 | struct sk_buff *); | |
2052 | struct sk_buff *(*usb_tx_aggregate_hdl)(struct ieee80211_hw *, | |
2053 | struct sk_buff_head *); | |
2054 | ||
2055 | /* endpoint mapping */ | |
2056 | int (*usb_endpoint_mapping)(struct ieee80211_hw *hw); | |
17c9ac62 | 2057 | u16 (*usb_mq_to_hwq)(__le16 fc, u16 mac80211_queue_index); |
62e63975 LF |
2058 | }; |
2059 | ||
0c817338 | 2060 | struct rtl_hal_cfg { |
e97b775d | 2061 | u8 bar_id; |
3dad618b | 2062 | bool write_readback; |
0c817338 LF |
2063 | char *name; |
2064 | char *fw_name; | |
62009b7f | 2065 | char *alt_fw_name; |
0c817338 LF |
2066 | struct rtl_hal_ops *ops; |
2067 | struct rtl_mod_params *mod_params; | |
62e63975 | 2068 | struct rtl_hal_usbint_cfg *usb_interface_cfg; |
0c817338 LF |
2069 | |
2070 | /*this map used for some registers or vars | |
2071 | defined int HAL but used in MAIN */ | |
2072 | u32 maps[RTL_VAR_MAP_MAX]; | |
2073 | ||
2074 | }; | |
2075 | ||
2076 | struct rtl_locks { | |
d704300f | 2077 | /* mutex */ |
8a09d6d8 | 2078 | struct mutex conf_mutex; |
6539306b | 2079 | struct mutex ps_mutex; |
0c817338 LF |
2080 | |
2081 | /*spin lock */ | |
b9116b9a | 2082 | spinlock_t ips_lock; |
0c817338 | 2083 | spinlock_t irq_th_lock; |
26634c4b LF |
2084 | spinlock_t irq_pci_lock; |
2085 | spinlock_t tx_lock; | |
0c817338 LF |
2086 | spinlock_t h2c_lock; |
2087 | spinlock_t rf_ps_lock; | |
2088 | spinlock_t rf_lock; | |
2461c7d6 | 2089 | spinlock_t lps_lock; |
e97b775d | 2090 | spinlock_t waitq_lock; |
2461c7d6 | 2091 | spinlock_t entry_list_lock; |
3ce4d85b | 2092 | spinlock_t usb_lock; |
e97b775d | 2093 | |
26634c4b LF |
2094 | /*FW clock change */ |
2095 | spinlock_t fw_ps_lock; | |
2096 | ||
e97b775d LF |
2097 | /*Dual mac*/ |
2098 | spinlock_t cck_and_rw_pagea_lock; | |
2461c7d6 LF |
2099 | |
2100 | /*Easy concurrent*/ | |
2101 | spinlock_t check_sendpkt_lock; | |
f3355dd9 LF |
2102 | |
2103 | spinlock_t iqk_lock; | |
0c817338 LF |
2104 | }; |
2105 | ||
2106 | struct rtl_works { | |
2107 | struct ieee80211_hw *hw; | |
2108 | ||
2109 | /*timer */ | |
2110 | struct timer_list watchdog_timer; | |
2461c7d6 | 2111 | struct timer_list dualmac_easyconcurrent_retrytimer; |
26634c4b LF |
2112 | struct timer_list fw_clockoff_timer; |
2113 | struct timer_list fast_antenna_training_timer; | |
0c817338 LF |
2114 | /*task */ |
2115 | struct tasklet_struct irq_tasklet; | |
2116 | struct tasklet_struct irq_prepare_bcn_tasklet; | |
2117 | ||
2118 | /*work queue */ | |
2119 | struct workqueue_struct *rtl_wq; | |
2120 | struct delayed_work watchdog_wq; | |
2121 | struct delayed_work ips_nic_off_wq; | |
e97b775d LF |
2122 | |
2123 | /* For SW LPS */ | |
2124 | struct delayed_work ps_work; | |
2125 | struct delayed_work ps_rfon_wq; | |
26634c4b | 2126 | struct delayed_work fwevt_wq; |
41affd52 | 2127 | |
a269913c | 2128 | struct work_struct lps_change_work; |
5b8df24e | 2129 | struct work_struct fill_h2c_cmd; |
0c817338 LF |
2130 | }; |
2131 | ||
2132 | struct rtl_debug { | |
2133 | u32 dbgp_type[DBGP_TYPE_MAX]; | |
d221ad1a | 2134 | int global_debuglevel; |
0c817338 | 2135 | u64 global_debugcomponents; |
e97b775d LF |
2136 | |
2137 | /* add for proc debug */ | |
2138 | struct proc_dir_entry *proc_dir; | |
2139 | char proc_name[20]; | |
0c817338 LF |
2140 | }; |
2141 | ||
2461c7d6 LF |
2142 | #define MIMO_PS_STATIC 0 |
2143 | #define MIMO_PS_DYNAMIC 1 | |
2144 | #define MIMO_PS_NOLIMIT 3 | |
2145 | ||
2146 | struct rtl_dualmac_easy_concurrent_ctl { | |
2147 | enum band_type currentbandtype_backfordmdp; | |
2148 | bool close_bbandrf_for_dmsp; | |
2149 | bool change_to_dmdp; | |
2150 | bool change_to_dmsp; | |
2151 | bool switch_in_process; | |
2152 | }; | |
2153 | ||
2154 | struct rtl_dmsp_ctl { | |
2155 | bool activescan_for_slaveofdmsp; | |
2156 | bool scan_for_anothermac_fordmsp; | |
2157 | bool scan_for_itself_fordmsp; | |
2158 | bool writedig_for_anothermacofdmsp; | |
2159 | u32 curdigvalue_for_anothermacofdmsp; | |
2160 | bool changecckpdstate_for_anothermacofdmsp; | |
2161 | u8 curcckpdstate_for_anothermacofdmsp; | |
2162 | bool changetxhighpowerlvl_for_anothermacofdmsp; | |
2163 | u8 curtxhighlvl_for_anothermacofdmsp; | |
2164 | long rssivalmin_for_anothermacofdmsp; | |
2165 | }; | |
2166 | ||
df37a0ec LF |
2167 | struct ps_t { |
2168 | u8 pre_ccastate; | |
2169 | u8 cur_ccasate; | |
2170 | u8 pre_rfstate; | |
2171 | u8 cur_rfstate; | |
2cddad3c | 2172 | u8 initialize; |
df37a0ec LF |
2173 | long rssi_val_min; |
2174 | }; | |
2175 | ||
2176 | struct dig_t { | |
2177 | u32 rssi_lowthresh; | |
2178 | u32 rssi_highthresh; | |
2179 | u32 fa_lowthresh; | |
2180 | u32 fa_highthresh; | |
da17fcff | 2181 | long last_min_undec_pwdb_for_dm; |
df37a0ec LF |
2182 | long rssi_highpower_lowthresh; |
2183 | long rssi_highpower_highthresh; | |
2184 | u32 recover_cnt; | |
2185 | u32 pre_igvalue; | |
2186 | u32 cur_igvalue; | |
2187 | long rssi_val; | |
2188 | u8 dig_enable_flag; | |
2189 | u8 dig_ext_port_stage; | |
2190 | u8 dig_algorithm; | |
2191 | u8 dig_twoport_algorithm; | |
2192 | u8 dig_dbgmode; | |
2193 | u8 dig_slgorithm_switch; | |
da17fcff LF |
2194 | u8 cursta_cstate; |
2195 | u8 presta_cstate; | |
2196 | u8 curmultista_cstate; | |
f3355dd9 | 2197 | u8 stop_dig; |
da17fcff LF |
2198 | char back_val; |
2199 | char back_range_max; | |
2200 | char back_range_min; | |
e6deaf81 LF |
2201 | u8 rx_gain_max; |
2202 | u8 rx_gain_min; | |
da17fcff | 2203 | u8 min_undec_pwdb_for_dm; |
df37a0ec | 2204 | u8 rssi_val_min; |
e6deaf81 LF |
2205 | u8 pre_cck_cca_thres; |
2206 | u8 cur_cck_cca_thres; | |
df37a0ec LF |
2207 | u8 pre_cck_pd_state; |
2208 | u8 cur_cck_pd_state; | |
2209 | u8 pre_cck_fa_state; | |
2210 | u8 cur_cck_fa_state; | |
2211 | u8 pre_ccastate; | |
2212 | u8 cur_ccasate; | |
2213 | u8 large_fa_hit; | |
b9a758a8 | 2214 | u8 dig_dynamic_min; |
f3355dd9 | 2215 | u8 dig_dynamic_min_1; |
df37a0ec LF |
2216 | u8 forbidden_igi; |
2217 | u8 dig_state; | |
2218 | u8 dig_highpwrstate; | |
da17fcff LF |
2219 | u8 cur_sta_cstate; |
2220 | u8 pre_sta_cstate; | |
2221 | u8 cur_ap_cstate; | |
2222 | u8 pre_ap_cstate; | |
df37a0ec LF |
2223 | u8 cur_pd_thstate; |
2224 | u8 pre_pd_thstate; | |
2225 | u8 cur_cs_ratiostate; | |
2226 | u8 pre_cs_ratiostate; | |
2227 | u8 backoff_enable_flag; | |
2228 | char backoffval_range_max; | |
2229 | char backoffval_range_min; | |
e6deaf81 LF |
2230 | u8 dig_min_0; |
2231 | u8 dig_min_1; | |
2cddad3c | 2232 | u8 bt30_cur_igi; |
e6deaf81 LF |
2233 | bool media_connect_0; |
2234 | bool media_connect_1; | |
2235 | ||
2236 | u32 antdiv_rssi_max; | |
2237 | u32 rssi_max; | |
df37a0ec LF |
2238 | }; |
2239 | ||
2461c7d6 LF |
2240 | struct rtl_global_var { |
2241 | /* from this list we can get | |
2242 | * other adapter's rtl_priv */ | |
2243 | struct list_head glb_priv_list; | |
2244 | spinlock_t glb_list_lock; | |
2245 | }; | |
2246 | ||
aa45a673 LF |
2247 | struct rtl_btc_info { |
2248 | u8 bt_type; | |
2249 | u8 btcoexist; | |
2250 | u8 ant_num; | |
2251 | }; | |
2252 | ||
2cddad3c | 2253 | struct bt_coexist_info { |
aa45a673 LF |
2254 | struct rtl_btc_ops *btc_ops; |
2255 | struct rtl_btc_info btc_info; | |
2cddad3c LF |
2256 | /* EEPROM BT info. */ |
2257 | u8 eeprom_bt_coexist; | |
2258 | u8 eeprom_bt_type; | |
2259 | u8 eeprom_bt_ant_num; | |
2260 | u8 eeprom_bt_ant_isol; | |
2261 | u8 eeprom_bt_radio_shared; | |
2262 | ||
2263 | u8 bt_coexistence; | |
2264 | u8 bt_ant_num; | |
2265 | u8 bt_coexist_type; | |
2266 | u8 bt_state; | |
2267 | u8 bt_cur_state; /* 0:on, 1:off */ | |
2268 | u8 bt_ant_isolation; /* 0:good, 1:bad */ | |
2269 | u8 bt_pape_ctrl; /* 0:SW, 1:SW/HW dynamic */ | |
2270 | u8 bt_service; | |
2271 | u8 bt_radio_shared_type; | |
2272 | u8 bt_rfreg_origin_1e; | |
2273 | u8 bt_rfreg_origin_1f; | |
2274 | u8 bt_rssi_state; | |
2275 | u32 ratio_tx; | |
2276 | u32 ratio_pri; | |
2277 | u32 bt_edca_ul; | |
2278 | u32 bt_edca_dl; | |
2279 | ||
2280 | bool init_set; | |
2281 | bool bt_busy_traffic; | |
2282 | bool bt_traffic_mode_set; | |
2283 | bool bt_non_traffic_mode_set; | |
2284 | ||
2285 | bool fw_coexist_all_off; | |
2286 | bool sw_coexist_all_off; | |
2287 | bool hw_coexist_all_off; | |
2288 | u32 cstate; | |
2289 | u32 previous_state; | |
2290 | u32 cstate_h; | |
2291 | u32 previous_state_h; | |
2292 | ||
2293 | u8 bt_pre_rssi_state; | |
2294 | u8 bt_pre_rssi_state1; | |
2295 | ||
2296 | u8 reg_bt_iso; | |
2297 | u8 reg_bt_sco; | |
2298 | bool balance_on; | |
2299 | u8 bt_active_zero_cnt; | |
2300 | bool cur_bt_disabled; | |
2301 | bool pre_bt_disabled; | |
2302 | ||
2303 | u8 bt_profile_case; | |
2304 | u8 bt_profile_action; | |
2305 | bool bt_busy; | |
2306 | bool hold_for_bt_operation; | |
2307 | u8 lps_counter; | |
aa45a673 LF |
2308 | }; |
2309 | ||
2310 | struct rtl_btc_ops { | |
2311 | void (*btc_init_variables) (struct rtl_priv *rtlpriv); | |
2312 | void (*btc_init_hal_vars) (struct rtl_priv *rtlpriv); | |
2313 | void (*btc_init_hw_config) (struct rtl_priv *rtlpriv); | |
2314 | void (*btc_ips_notify) (struct rtl_priv *rtlpriv, u8 type); | |
2315 | void (*btc_scan_notify) (struct rtl_priv *rtlpriv, u8 scantype); | |
2316 | void (*btc_connect_notify) (struct rtl_priv *rtlpriv, u8 action); | |
2317 | void (*btc_mediastatus_notify) (struct rtl_priv *rtlpriv, | |
2318 | enum _RT_MEDIA_STATUS mstatus); | |
2319 | void (*btc_periodical) (struct rtl_priv *rtlpriv); | |
2320 | void (*btc_halt_notify) (void); | |
2321 | void (*btc_btinfo_notify) (struct rtl_priv *rtlpriv, | |
2322 | u8 *tmp_buf, u8 length); | |
2323 | bool (*btc_is_limited_dig) (struct rtl_priv *rtlpriv); | |
2324 | bool (*btc_is_disable_edca_turbo) (struct rtl_priv *rtlpriv); | |
2325 | bool (*btc_is_bt_disabled) (struct rtl_priv *rtlpriv); | |
2326 | }; | |
2327 | ||
2328 | struct proxim { | |
2329 | bool proxim_on; | |
2330 | ||
2331 | void *proximity_priv; | |
2332 | int (*proxim_rx)(struct ieee80211_hw *hw, struct rtl_stats *status, | |
2333 | struct sk_buff *skb); | |
2334 | u8 (*proxim_get_var)(struct ieee80211_hw *hw, u8 type); | |
2335 | }; | |
2336 | ||
0c817338 | 2337 | struct rtl_priv { |
26634c4b | 2338 | struct ieee80211_hw *hw; |
b0302aba | 2339 | struct completion firmware_loading_complete; |
2461c7d6 LF |
2340 | struct list_head list; |
2341 | struct rtl_priv *buddy_priv; | |
2342 | struct rtl_global_var *glb_var; | |
2343 | struct rtl_dualmac_easy_concurrent_ctl easy_concurrent_ctl; | |
2344 | struct rtl_dmsp_ctl dmsp_ctl; | |
0c817338 LF |
2345 | struct rtl_locks locks; |
2346 | struct rtl_works works; | |
2347 | struct rtl_mac mac80211; | |
2348 | struct rtl_hal rtlhal; | |
2349 | struct rtl_regulatory regd; | |
2350 | struct rtl_rfkill rfkill; | |
2351 | struct rtl_io io; | |
2352 | struct rtl_phy phy; | |
2353 | struct rtl_dm dm; | |
2354 | struct rtl_security sec; | |
2355 | struct rtl_efuse efuse; | |
2356 | ||
2357 | struct rtl_ps_ctl psc; | |
2358 | struct rate_adaptive ra; | |
f3355dd9 | 2359 | struct dynamic_primary_cca primarycca; |
0c817338 LF |
2360 | struct wireless_stats stats; |
2361 | struct rt_link_detect link_info; | |
2362 | struct false_alarm_statistics falsealm_cnt; | |
2363 | ||
2364 | struct rtl_rate_priv *rate_priv; | |
2365 | ||
2461c7d6 LF |
2366 | /* sta entry list for ap adhoc or mesh */ |
2367 | struct list_head entry_list; | |
2368 | ||
0c817338 | 2369 | struct rtl_debug dbg; |
b0302aba | 2370 | int max_fw_size; |
0c817338 LF |
2371 | |
2372 | /* | |
2373 | *hal_cfg : for diff cards | |
2374 | *intf_ops : for diff interrface usb/pcie | |
2375 | */ | |
2376 | struct rtl_hal_cfg *cfg; | |
2377 | struct rtl_intf_ops *intf_ops; | |
2378 | ||
2379 | /*this var will be set by set_bit, | |
2380 | and was used to indicate status of | |
2381 | interface or hardware */ | |
2382 | unsigned long status; | |
2383 | ||
0985dfbc LF |
2384 | /* tables for dm */ |
2385 | struct dig_t dm_digtable; | |
2386 | struct ps_t dm_pstable; | |
2387 | ||
b9a758a8 LF |
2388 | u32 reg_874; |
2389 | u32 reg_c70; | |
2390 | u32 reg_85c; | |
2391 | u32 reg_a74; | |
2392 | bool reg_init; /* true if regs saved */ | |
2393 | bool bt_operation_on; | |
2394 | __le32 *usb_data; | |
2395 | int usb_data_index; | |
2396 | bool initialized; | |
a269913c | 2397 | bool enter_ps; /* true when entering PS */ |
5b8df24e | 2398 | u8 rate_mask[5]; |
30899cc6 | 2399 | |
aa45a673 LF |
2400 | /* intel Proximity, should be alloc mem |
2401 | * in intel Proximity module and can only | |
2402 | * be used in intel Proximity mode | |
2403 | */ | |
2404 | struct proxim proximity; | |
2405 | ||
2406 | /*for bt coexist use*/ | |
2cddad3c | 2407 | struct bt_coexist_info btcoexist; |
aa45a673 LF |
2408 | |
2409 | /* separate 92ee from other ICs, | |
2410 | * 92ee use new trx flow. | |
2411 | */ | |
2412 | bool use_new_trx_flow; | |
2413 | ||
0c817338 LF |
2414 | /*This must be the last item so |
2415 | that it points to the data allocated | |
2416 | beyond this structure like: | |
2417 | rtl_pci_priv or rtl_usb_priv */ | |
60ce314d | 2418 | u8 priv[0] __aligned(sizeof(void *)); |
0c817338 LF |
2419 | }; |
2420 | ||
2421 | #define rtl_priv(hw) (((struct rtl_priv *)(hw)->priv)) | |
2422 | #define rtl_mac(rtlpriv) (&((rtlpriv)->mac80211)) | |
2423 | #define rtl_hal(rtlpriv) (&((rtlpriv)->rtlhal)) | |
2424 | #define rtl_efuse(rtlpriv) (&((rtlpriv)->efuse)) | |
2425 | #define rtl_psc(rtlpriv) (&((rtlpriv)->psc)) | |
2426 | ||
e97b775d | 2427 | |
18d30067 | 2428 | /*************************************** |
25985edc | 2429 | Bluetooth Co-existence Related |
18d30067 G |
2430 | ****************************************/ |
2431 | ||
2432 | enum bt_ant_num { | |
2433 | ANT_X2 = 0, | |
2434 | ANT_X1 = 1, | |
2435 | }; | |
2436 | ||
2437 | enum bt_co_type { | |
2438 | BT_2WIRE = 0, | |
2439 | BT_ISSC_3WIRE = 1, | |
2440 | BT_ACCEL = 2, | |
2441 | BT_CSR_BC4 = 3, | |
2442 | BT_CSR_BC8 = 4, | |
2443 | BT_RTL8756 = 5, | |
0f015453 | 2444 | BT_RTL8723A = 6, |
f3355dd9 | 2445 | BT_RTL8821A = 7, |
aa45a673 LF |
2446 | BT_RTL8723B = 8, |
2447 | BT_RTL8192E = 9, | |
f3355dd9 LF |
2448 | BT_RTL8812A = 11, |
2449 | }; | |
2450 | ||
2451 | enum bt_total_ant_num { | |
2452 | ANT_TOTAL_X2 = 0, | |
2453 | ANT_TOTAL_X1 = 1 | |
18d30067 G |
2454 | }; |
2455 | ||
2456 | enum bt_cur_state { | |
2457 | BT_OFF = 0, | |
2458 | BT_ON = 1, | |
2459 | }; | |
2460 | ||
2461 | enum bt_service_type { | |
2462 | BT_SCO = 0, | |
2463 | BT_A2DP = 1, | |
2464 | BT_HID = 2, | |
2465 | BT_HID_IDLE = 3, | |
2466 | BT_SCAN = 4, | |
2467 | BT_IDLE = 5, | |
2468 | BT_OTHER_ACTION = 6, | |
2469 | BT_BUSY = 7, | |
2470 | BT_OTHERBUSY = 8, | |
2471 | BT_PAN = 9, | |
2472 | }; | |
2473 | ||
2474 | enum bt_radio_shared { | |
2475 | BT_RADIO_SHARED = 0, | |
2476 | BT_RADIO_INDIVIDUAL = 1, | |
2477 | }; | |
2478 | ||
e97b775d | 2479 | |
0c817338 LF |
2480 | /**************************************** |
2481 | mem access macro define start | |
2482 | Call endian free function when | |
2483 | 1. Read/write packet content. | |
2484 | 2. Before write integer to IO. | |
2485 | 3. After read integer from IO. | |
2486 | ****************************************/ | |
9e0bc671 | 2487 | /* Convert little data endian to host ordering */ |
0c817338 LF |
2488 | #define EF1BYTE(_val) \ |
2489 | ((u8)(_val)) | |
2490 | #define EF2BYTE(_val) \ | |
2491 | (le16_to_cpu(_val)) | |
2492 | #define EF4BYTE(_val) \ | |
2493 | (le32_to_cpu(_val)) | |
2494 | ||
3dad618b C |
2495 | /* Read data from memory */ |
2496 | #define READEF1BYTE(_ptr) \ | |
2497 | EF1BYTE(*((u8 *)(_ptr))) | |
9e0bc671 | 2498 | /* Read le16 data from memory and convert to host ordering */ |
0c817338 | 2499 | #define READEF2BYTE(_ptr) \ |
8e2c406a | 2500 | EF2BYTE(*(_ptr)) |
3dad618b | 2501 | #define READEF4BYTE(_ptr) \ |
8e2c406a | 2502 | EF4BYTE(*(_ptr)) |
0c817338 | 2503 | |
3dad618b C |
2504 | /* Write data to memory */ |
2505 | #define WRITEEF1BYTE(_ptr, _val) \ | |
2506 | (*((u8 *)(_ptr))) = EF1BYTE(_val) | |
9e0bc671 | 2507 | /* Write le16 data to memory in host ordering */ |
0c817338 LF |
2508 | #define WRITEEF2BYTE(_ptr, _val) \ |
2509 | (*((u16 *)(_ptr))) = EF2BYTE(_val) | |
3dad618b | 2510 | #define WRITEEF4BYTE(_ptr, _val) \ |
8e2c406a | 2511 | (*((u32 *)(_ptr))) = EF2BYTE(_val) |
9e0bc671 LF |
2512 | |
2513 | /* Create a bit mask | |
2514 | * Examples: | |
2515 | * BIT_LEN_MASK_32(0) => 0x00000000 | |
2516 | * BIT_LEN_MASK_32(1) => 0x00000001 | |
2517 | * BIT_LEN_MASK_32(2) => 0x00000003 | |
2518 | * BIT_LEN_MASK_32(32) => 0xFFFFFFFF | |
2519 | */ | |
0c817338 LF |
2520 | #define BIT_LEN_MASK_32(__bitlen) \ |
2521 | (0xFFFFFFFF >> (32 - (__bitlen))) | |
2522 | #define BIT_LEN_MASK_16(__bitlen) \ | |
2523 | (0xFFFF >> (16 - (__bitlen))) | |
2524 | #define BIT_LEN_MASK_8(__bitlen) \ | |
2525 | (0xFF >> (8 - (__bitlen))) | |
2526 | ||
9e0bc671 LF |
2527 | /* Create an offset bit mask |
2528 | * Examples: | |
2529 | * BIT_OFFSET_LEN_MASK_32(0, 2) => 0x00000003 | |
2530 | * BIT_OFFSET_LEN_MASK_32(16, 2) => 0x00030000 | |
2531 | */ | |
0c817338 LF |
2532 | #define BIT_OFFSET_LEN_MASK_32(__bitoffset, __bitlen) \ |
2533 | (BIT_LEN_MASK_32(__bitlen) << (__bitoffset)) | |
2534 | #define BIT_OFFSET_LEN_MASK_16(__bitoffset, __bitlen) \ | |
2535 | (BIT_LEN_MASK_16(__bitlen) << (__bitoffset)) | |
2536 | #define BIT_OFFSET_LEN_MASK_8(__bitoffset, __bitlen) \ | |
2537 | (BIT_LEN_MASK_8(__bitlen) << (__bitoffset)) | |
2538 | ||
2539 | /*Description: | |
9e0bc671 LF |
2540 | * Return 4-byte value in host byte ordering from |
2541 | * 4-byte pointer in little-endian system. | |
2542 | */ | |
0c817338 | 2543 | #define LE_P4BYTE_TO_HOST_4BYTE(__pstart) \ |
8e2c406a | 2544 | (EF4BYTE(*((__le32 *)(__pstart)))) |
0c817338 | 2545 | #define LE_P2BYTE_TO_HOST_2BYTE(__pstart) \ |
8e2c406a | 2546 | (EF2BYTE(*((__le16 *)(__pstart)))) |
0c817338 LF |
2547 | #define LE_P1BYTE_TO_HOST_1BYTE(__pstart) \ |
2548 | (EF1BYTE(*((u8 *)(__pstart)))) | |
2549 | ||
3dad618b C |
2550 | /*Description: |
2551 | Translate subfield (continuous bits in little-endian) of 4-byte | |
2552 | value to host byte ordering.*/ | |
2553 | #define LE_BITS_TO_4BYTE(__pstart, __bitoffset, __bitlen) \ | |
2554 | ( \ | |
2555 | (LE_P4BYTE_TO_HOST_4BYTE(__pstart) >> (__bitoffset)) & \ | |
2556 | BIT_LEN_MASK_32(__bitlen) \ | |
2557 | ) | |
2558 | #define LE_BITS_TO_2BYTE(__pstart, __bitoffset, __bitlen) \ | |
2559 | ( \ | |
2560 | (LE_P2BYTE_TO_HOST_2BYTE(__pstart) >> (__bitoffset)) & \ | |
2561 | BIT_LEN_MASK_16(__bitlen) \ | |
2562 | ) | |
2563 | #define LE_BITS_TO_1BYTE(__pstart, __bitoffset, __bitlen) \ | |
2564 | ( \ | |
2565 | (LE_P1BYTE_TO_HOST_1BYTE(__pstart) >> (__bitoffset)) & \ | |
2566 | BIT_LEN_MASK_8(__bitlen) \ | |
2567 | ) | |
2568 | ||
9e0bc671 LF |
2569 | /* Description: |
2570 | * Mask subfield (continuous bits in little-endian) of 4-byte value | |
2571 | * and return the result in 4-byte value in host byte ordering. | |
2572 | */ | |
0c817338 LF |
2573 | #define LE_BITS_CLEARED_TO_4BYTE(__pstart, __bitoffset, __bitlen) \ |
2574 | ( \ | |
2575 | LE_P4BYTE_TO_HOST_4BYTE(__pstart) & \ | |
2576 | (~BIT_OFFSET_LEN_MASK_32(__bitoffset, __bitlen)) \ | |
2577 | ) | |
2578 | #define LE_BITS_CLEARED_TO_2BYTE(__pstart, __bitoffset, __bitlen) \ | |
2579 | ( \ | |
2580 | LE_P2BYTE_TO_HOST_2BYTE(__pstart) & \ | |
2581 | (~BIT_OFFSET_LEN_MASK_16(__bitoffset, __bitlen)) \ | |
2582 | ) | |
2583 | #define LE_BITS_CLEARED_TO_1BYTE(__pstart, __bitoffset, __bitlen) \ | |
2584 | ( \ | |
2585 | LE_P1BYTE_TO_HOST_1BYTE(__pstart) & \ | |
2586 | (~BIT_OFFSET_LEN_MASK_8(__bitoffset, __bitlen)) \ | |
2587 | ) | |
2588 | ||
9e0bc671 LF |
2589 | /* Description: |
2590 | * Set subfield of little-endian 4-byte value to specified value. | |
2591 | */ | |
3dad618b | 2592 | #define SET_BITS_TO_LE_4BYTE(__pstart, __bitoffset, __bitlen, __val) \ |
8e2c406a | 2593 | *((u32 *)(__pstart)) = \ |
3dad618b C |
2594 | ( \ |
2595 | LE_BITS_CLEARED_TO_4BYTE(__pstart, __bitoffset, __bitlen) | \ | |
2596 | ((((u32)__val) & BIT_LEN_MASK_32(__bitlen)) << (__bitoffset)) \ | |
2597 | ); | |
2598 | #define SET_BITS_TO_LE_2BYTE(__pstart, __bitoffset, __bitlen, __val) \ | |
8e2c406a | 2599 | *((u16 *)(__pstart)) = \ |
3dad618b C |
2600 | ( \ |
2601 | LE_BITS_CLEARED_TO_2BYTE(__pstart, __bitoffset, __bitlen) | \ | |
2602 | ((((u16)__val) & BIT_LEN_MASK_16(__bitlen)) << (__bitoffset)) \ | |
2603 | ); | |
0c817338 LF |
2604 | #define SET_BITS_TO_LE_1BYTE(__pstart, __bitoffset, __bitlen, __val) \ |
2605 | *((u8 *)(__pstart)) = EF1BYTE \ | |
2606 | ( \ | |
2607 | LE_BITS_CLEARED_TO_1BYTE(__pstart, __bitoffset, __bitlen) | \ | |
2608 | ((((u8)__val) & BIT_LEN_MASK_8(__bitlen)) << (__bitoffset)) \ | |
2609 | ); | |
2610 | ||
3dad618b C |
2611 | #define N_BYTE_ALIGMENT(__value, __aligment) ((__aligment == 1) ? \ |
2612 | (__value) : (((__value + __aligment - 1) / __aligment) * __aligment)) | |
2613 | ||
0c817338 LF |
2614 | /**************************************** |
2615 | mem access macro define end | |
2616 | ****************************************/ | |
2617 | ||
e97b775d LF |
2618 | #define byte(x, n) ((x >> (8 * n)) & 0xff) |
2619 | ||
3dad618b | 2620 | #define packet_get_type(_packet) (EF1BYTE((_packet).octet[0]) & 0xFC) |
0c817338 LF |
2621 | #define RTL_WATCH_DOG_TIME 2000 |
2622 | #define MSECS(t) msecs_to_jiffies(t) | |
17c9ac62 LF |
2623 | #define WLAN_FC_GET_VERS(fc) (le16_to_cpu(fc) & IEEE80211_FCTL_VERS) |
2624 | #define WLAN_FC_GET_TYPE(fc) (le16_to_cpu(fc) & IEEE80211_FCTL_FTYPE) | |
2625 | #define WLAN_FC_GET_STYPE(fc) (le16_to_cpu(fc) & IEEE80211_FCTL_STYPE) | |
2626 | #define WLAN_FC_MORE_DATA(fc) (le16_to_cpu(fc) & IEEE80211_FCTL_MOREDATA) | |
e6deaf81 | 2627 | #define rtl_dm(rtlpriv) (&((rtlpriv)->dm)) |
0c817338 LF |
2628 | |
2629 | #define RT_RF_OFF_LEVL_ASPM BIT(0) /*PCI ASPM */ | |
2630 | #define RT_RF_OFF_LEVL_CLK_REQ BIT(1) /*PCI clock request */ | |
2631 | #define RT_RF_OFF_LEVL_PCI_D3 BIT(2) /*PCI D3 mode */ | |
2632 | /*NIC halt, re-initialize hw parameters*/ | |
2633 | #define RT_RF_OFF_LEVL_HALT_NIC BIT(3) | |
2634 | #define RT_RF_OFF_LEVL_FREE_FW BIT(4) /*FW free, re-download the FW */ | |
2635 | #define RT_RF_OFF_LEVL_FW_32K BIT(5) /*FW in 32k */ | |
2636 | /*Always enable ASPM and Clock Req in initialization.*/ | |
2637 | #define RT_RF_PS_LEVEL_ALWAYS_ASPM BIT(6) | |
e97b775d LF |
2638 | /* no matter RFOFF or SLEEP we set PS_ASPM_LEVL*/ |
2639 | #define RT_PS_LEVEL_ASPM BIT(7) | |
0c817338 LF |
2640 | /*When LPS is on, disable 2R if no packet is received or transmittd.*/ |
2641 | #define RT_RF_LPS_DISALBE_2R BIT(30) | |
2642 | #define RT_RF_LPS_LEVEL_ASPM BIT(31) /*LPS with ASPM */ | |
2643 | #define RT_IN_PS_LEVEL(ppsc, _ps_flg) \ | |
2644 | ((ppsc->cur_ps_level & _ps_flg) ? true : false) | |
2645 | #define RT_CLEAR_PS_LEVEL(ppsc, _ps_flg) \ | |
2646 | (ppsc->cur_ps_level &= (~(_ps_flg))) | |
2647 | #define RT_SET_PS_LEVEL(ppsc, _ps_flg) \ | |
2648 | (ppsc->cur_ps_level |= _ps_flg) | |
2649 | ||
2650 | #define container_of_dwork_rtl(x, y, z) \ | |
2651 | container_of(container_of(x, struct delayed_work, work), y, z) | |
2652 | ||
3dad618b C |
2653 | #define FILL_OCTET_STRING(_os, _octet, _len) \ |
2654 | (_os).octet = (u8 *)(_octet); \ | |
2655 | (_os).length = (_len); | |
2656 | ||
2657 | #define CP_MACADDR(des, src) \ | |
2658 | ((des)[0] = (src)[0], (des)[1] = (src)[1],\ | |
2659 | (des)[2] = (src)[2], (des)[3] = (src)[3],\ | |
2660 | (des)[4] = (src)[4], (des)[5] = (src)[5]) | |
2661 | ||
0c817338 LF |
2662 | static inline u8 rtl_read_byte(struct rtl_priv *rtlpriv, u32 addr) |
2663 | { | |
2664 | return rtlpriv->io.read8_sync(rtlpriv, addr); | |
2665 | } | |
2666 | ||
2667 | static inline u16 rtl_read_word(struct rtl_priv *rtlpriv, u32 addr) | |
2668 | { | |
2669 | return rtlpriv->io.read16_sync(rtlpriv, addr); | |
2670 | } | |
2671 | ||
2672 | static inline u32 rtl_read_dword(struct rtl_priv *rtlpriv, u32 addr) | |
2673 | { | |
2674 | return rtlpriv->io.read32_sync(rtlpriv, addr); | |
2675 | } | |
2676 | ||
2677 | static inline void rtl_write_byte(struct rtl_priv *rtlpriv, u32 addr, u8 val8) | |
2678 | { | |
2679 | rtlpriv->io.write8_async(rtlpriv, addr, val8); | |
3dad618b C |
2680 | |
2681 | if (rtlpriv->cfg->write_readback) | |
2682 | rtlpriv->io.read8_sync(rtlpriv, addr); | |
0c817338 LF |
2683 | } |
2684 | ||
2685 | static inline void rtl_write_word(struct rtl_priv *rtlpriv, u32 addr, u16 val16) | |
2686 | { | |
2687 | rtlpriv->io.write16_async(rtlpriv, addr, val16); | |
3dad618b C |
2688 | |
2689 | if (rtlpriv->cfg->write_readback) | |
2690 | rtlpriv->io.read16_sync(rtlpriv, addr); | |
0c817338 LF |
2691 | } |
2692 | ||
2693 | static inline void rtl_write_dword(struct rtl_priv *rtlpriv, | |
2694 | u32 addr, u32 val32) | |
2695 | { | |
2696 | rtlpriv->io.write32_async(rtlpriv, addr, val32); | |
3dad618b C |
2697 | |
2698 | if (rtlpriv->cfg->write_readback) | |
2699 | rtlpriv->io.read32_sync(rtlpriv, addr); | |
0c817338 LF |
2700 | } |
2701 | ||
2702 | static inline u32 rtl_get_bbreg(struct ieee80211_hw *hw, | |
2703 | u32 regaddr, u32 bitmask) | |
2704 | { | |
d6b6fc14 JP |
2705 | struct rtl_priv *rtlpriv = hw->priv; |
2706 | ||
2707 | return rtlpriv->cfg->ops->get_bbreg(hw, regaddr, bitmask); | |
0c817338 LF |
2708 | } |
2709 | ||
2710 | static inline void rtl_set_bbreg(struct ieee80211_hw *hw, u32 regaddr, | |
2711 | u32 bitmask, u32 data) | |
2712 | { | |
d6b6fc14 | 2713 | struct rtl_priv *rtlpriv = hw->priv; |
0c817338 | 2714 | |
d6b6fc14 | 2715 | rtlpriv->cfg->ops->set_bbreg(hw, regaddr, bitmask, data); |
0c817338 LF |
2716 | } |
2717 | ||
2718 | static inline u32 rtl_get_rfreg(struct ieee80211_hw *hw, | |
2719 | enum radio_path rfpath, u32 regaddr, | |
2720 | u32 bitmask) | |
2721 | { | |
d6b6fc14 JP |
2722 | struct rtl_priv *rtlpriv = hw->priv; |
2723 | ||
2724 | return rtlpriv->cfg->ops->get_rfreg(hw, rfpath, regaddr, bitmask); | |
0c817338 LF |
2725 | } |
2726 | ||
2727 | static inline void rtl_set_rfreg(struct ieee80211_hw *hw, | |
2728 | enum radio_path rfpath, u32 regaddr, | |
2729 | u32 bitmask, u32 data) | |
2730 | { | |
d6b6fc14 JP |
2731 | struct rtl_priv *rtlpriv = hw->priv; |
2732 | ||
2733 | rtlpriv->cfg->ops->set_rfreg(hw, rfpath, regaddr, bitmask, data); | |
0c817338 LF |
2734 | } |
2735 | ||
2736 | static inline bool is_hal_stop(struct rtl_hal *rtlhal) | |
2737 | { | |
2738 | return (_HAL_STATE_STOP == rtlhal->state); | |
2739 | } | |
2740 | ||
2741 | static inline void set_hal_start(struct rtl_hal *rtlhal) | |
2742 | { | |
2743 | rtlhal->state = _HAL_STATE_START; | |
2744 | } | |
2745 | ||
2746 | static inline void set_hal_stop(struct rtl_hal *rtlhal) | |
2747 | { | |
2748 | rtlhal->state = _HAL_STATE_STOP; | |
2749 | } | |
2750 | ||
2751 | static inline u8 get_rf_type(struct rtl_phy *rtlphy) | |
2752 | { | |
2753 | return rtlphy->rf_type; | |
2754 | } | |
2755 | ||
3dad618b C |
2756 | static inline struct ieee80211_hdr *rtl_get_hdr(struct sk_buff *skb) |
2757 | { | |
2758 | return (struct ieee80211_hdr *)(skb->data); | |
2759 | } | |
2760 | ||
d3bb1429 | 2761 | static inline __le16 rtl_get_fc(struct sk_buff *skb) |
3dad618b | 2762 | { |
d3bb1429 | 2763 | return rtl_get_hdr(skb)->frame_control; |
3dad618b C |
2764 | } |
2765 | ||
2766 | static inline u16 rtl_get_tid_h(struct ieee80211_hdr *hdr) | |
2767 | { | |
2768 | return (ieee80211_get_qos_ctl(hdr))[0] & IEEE80211_QOS_CTL_TID_MASK; | |
2769 | } | |
2770 | ||
2771 | static inline u16 rtl_get_tid(struct sk_buff *skb) | |
2772 | { | |
2773 | return rtl_get_tid_h(rtl_get_hdr(skb)); | |
2774 | } | |
2775 | ||
2776 | static inline struct ieee80211_sta *get_sta(struct ieee80211_hw *hw, | |
2777 | struct ieee80211_vif *vif, | |
7101f404 | 2778 | const u8 *bssid) |
3dad618b C |
2779 | { |
2780 | return ieee80211_find_sta(vif, bssid); | |
2781 | } | |
2782 | ||
2461c7d6 LF |
2783 | static inline struct ieee80211_sta *rtl_find_sta(struct ieee80211_hw *hw, |
2784 | u8 *mac_addr) | |
2785 | { | |
2786 | struct rtl_mac *mac = rtl_mac(rtl_priv(hw)); | |
2787 | return ieee80211_find_sta(mac->vif, mac_addr); | |
2788 | } | |
2789 | ||
0c817338 | 2790 | #endif |