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wireless: rt2x00: rt2800pci add id
[deliverable/linux.git] / drivers / net / wireless / rtlwifi / wifi.h
CommitLineData
0c817338
LF		 1/******************************************************************************
2 *
a8d76066 3 * Copyright(c) 2009-2012 Realtek Corporation.
0c817338
LF		 4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of version 2 of the GNU General Public License as
7 * published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details.
13 *
14 * You should have received a copy of the GNU General Public License along with
15 * this program; if not, write to the Free Software Foundation, Inc.,
16 * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
17 *
18 * The full GNU General Public License is included in this distribution in the
19 * file called LICENSE.
20 *
21 * Contact Information:
22 * wlanfae <wlanfae@realtek.com>
23 * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
24 * Hsinchu 300, Taiwan.
25 *
26 * Larry Finger <Larry.Finger@lwfinger.net>
27 *
28 *****************************************************************************/
29
30#ifndef __RTL_WIFI_H__
31#define __RTL_WIFI_H__
32
d273bb20
LF		 33#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
34
0c817338
LF		 35#include <linux/sched.h>
36#include <linux/firmware.h>
0c817338 37#include <linux/etherdevice.h>
b08cd667 38#include <linux/vmalloc.h>
62e63975 39#include <linux/usb.h>
0c817338 40#include <net/mac80211.h>
b0302aba 41#include <linux/completion.h>
0c817338
LF		 42#include "debug.h"
43
44#define RF_CHANGE_BY_INIT 0
45#define RF_CHANGE_BY_IPS BIT(28)
46#define RF_CHANGE_BY_PS BIT(29)
47#define RF_CHANGE_BY_HW BIT(30)
48#define RF_CHANGE_BY_SW BIT(31)
49
50#define IQK_ADDA_REG_NUM 16
51#define IQK_MAC_REG_NUM 4
52
53#define MAX_KEY_LEN 61
54#define KEY_BUF_SIZE 5
55
56/* QoS related. */
57/*aci: 0x00 Best Effort*/
58/*aci: 0x01 Background*/
59/*aci: 0x10 Video*/
60/*aci: 0x11 Voice*/
61/*Max: define total number.*/
62#define AC0_BE 0
63#define AC1_BK 1
64#define AC2_VI 2
65#define AC3_VO 3
66#define AC_MAX 4
67#define QOS_QUEUE_NUM 4
68#define RTL_MAC80211_NUM_QUEUE 5
ff6ff96b 69#define REALTEK_USB_VENQT_MAX_BUF_SIZE 254
30899cc6 70#define RTL_USB_MAX_RX_COUNT 100
0c817338
LF		 71#define QBSS_LOAD_SIZE 5
72#define MAX_WMMELE_LENGTH 64
73
3dad618b
C		 74#define TOTAL_CAM_ENTRY 32
75
0c817338
LF		 76/*slot time for 11g. */
77#define RTL_SLOT_TIME_9 9
78#define RTL_SLOT_TIME_20 20
79
80/*related with tcp/ip. */
81/*if_ehther.h*/
82#define ETH_P_PAE 0x888E /*Port Access Entity (IEEE 802.1X) */
83#define ETH_P_IP 0x0800 /*Internet Protocol packet */
84#define ETH_P_ARP 0x0806 /*Address Resolution packet */
85#define SNAP_SIZE 6
86#define PROTOC_TYPE_SIZE 2
87
88/*related with 802.11 frame*/
89#define MAC80211_3ADDR_LEN 24
90#define MAC80211_4ADDR_LEN 30
91
e97b775d
LF		 92#define CHANNEL_MAX_NUMBER (14 + 24 + 21) /* 14 is the max channel no */
93#define CHANNEL_GROUP_MAX (3 + 9) /* ch1~3, 4~9, 10~14 = three groups */
94#define MAX_PG_GROUP 13
95#define CHANNEL_GROUP_MAX_2G 3
96#define CHANNEL_GROUP_IDX_5GL 3
97#define CHANNEL_GROUP_IDX_5GM 6
98#define CHANNEL_GROUP_IDX_5GH 9
99#define CHANNEL_GROUP_MAX_5G 9
100#define CHANNEL_MAX_NUMBER_2G 14
101#define AVG_THERMAL_NUM 8
3dad618b 102#define MAX_TID_COUNT 9
e97b775d
LF		 103
104/* for early mode */
3dad618b 105#define FCS_LEN 4
e97b775d 106#define EM_HDR_LEN 8
0c817338
LF		 107enum intf_type {
108 INTF_PCI = 0,
109 INTF_USB = 1,
110};
111
112enum radio_path {
113 RF90_PATH_A = 0,
114 RF90_PATH_B = 1,
115 RF90_PATH_C = 2,
116 RF90_PATH_D = 3,
117};
118
119enum rt_eeprom_type {
120 EEPROM_93C46,
121 EEPROM_93C56,
122 EEPROM_BOOT_EFUSE,
123};
124
36323f81 125enum ttl_status {
0c817338
LF		 126 RTL_STATUS_INTERFACE_START = 0,
127};
128
129enum hardware_type {
130 HARDWARE_TYPE_RTL8192E,
131 HARDWARE_TYPE_RTL8192U,
132 HARDWARE_TYPE_RTL8192SE,
133 HARDWARE_TYPE_RTL8192SU,
134 HARDWARE_TYPE_RTL8192CE,
135 HARDWARE_TYPE_RTL8192CU,
136 HARDWARE_TYPE_RTL8192DE,
137 HARDWARE_TYPE_RTL8192DU,
2461c7d6 138 HARDWARE_TYPE_RTL8723AE,
18d30067 139 HARDWARE_TYPE_RTL8723U,
0c817338 140
e97b775d 141 /* keep it last */
0c817338
LF		 142 HARDWARE_TYPE_NUM
143};
144
e97b775d
LF		 145#define IS_HARDWARE_TYPE_8192SU(rtlhal) \
146 (rtlhal->hw_type == HARDWARE_TYPE_RTL8192SU)
147#define IS_HARDWARE_TYPE_8192SE(rtlhal) \
148 (rtlhal->hw_type == HARDWARE_TYPE_RTL8192SE)
62e63975
LF		 149#define IS_HARDWARE_TYPE_8192CE(rtlhal) \
150 (rtlhal->hw_type == HARDWARE_TYPE_RTL8192CE)
18d30067
G		 151#define IS_HARDWARE_TYPE_8192CU(rtlhal) \
152 (rtlhal->hw_type == HARDWARE_TYPE_RTL8192CU)
e97b775d
LF		 153#define IS_HARDWARE_TYPE_8192DE(rtlhal) \
154 (rtlhal->hw_type == HARDWARE_TYPE_RTL8192DE)
155#define IS_HARDWARE_TYPE_8192DU(rtlhal) \
156 (rtlhal->hw_type == HARDWARE_TYPE_RTL8192DU)
157#define IS_HARDWARE_TYPE_8723E(rtlhal) \
158 (rtlhal->hw_type == HARDWARE_TYPE_RTL8723E)
18d30067
G		 159#define IS_HARDWARE_TYPE_8723U(rtlhal) \
160 (rtlhal->hw_type == HARDWARE_TYPE_RTL8723U)
e97b775d
LF		 161#define IS_HARDWARE_TYPE_8192S(rtlhal) \
162(IS_HARDWARE_TYPE_8192SE(rtlhal) || IS_HARDWARE_TYPE_8192SU(rtlhal))
163#define IS_HARDWARE_TYPE_8192C(rtlhal) \
164(IS_HARDWARE_TYPE_8192CE(rtlhal) || IS_HARDWARE_TYPE_8192CU(rtlhal))
165#define IS_HARDWARE_TYPE_8192D(rtlhal) \
166(IS_HARDWARE_TYPE_8192DE(rtlhal) || IS_HARDWARE_TYPE_8192DU(rtlhal))
167#define IS_HARDWARE_TYPE_8723(rtlhal) \
168(IS_HARDWARE_TYPE_8723E(rtlhal) || IS_HARDWARE_TYPE_8723U(rtlhal))
3dad618b
C		 169#define IS_HARDWARE_TYPE_8723U(rtlhal) \
170 (rtlhal->hw_type == HARDWARE_TYPE_RTL8723U)
62e63975 171
da3ba88a
LF		 172#define RX_HAL_IS_CCK_RATE(_pdesc)\
173 (_pdesc->rxmcs == DESC92_RATE1M || \
174 _pdesc->rxmcs == DESC92_RATE2M || \
175 _pdesc->rxmcs == DESC92_RATE5_5M || \
176 _pdesc->rxmcs == DESC92_RATE11M)
177
0c817338
LF		 178enum scan_operation_backup_opt {
179 SCAN_OPT_BACKUP = 0,
180 SCAN_OPT_RESTORE,
181 SCAN_OPT_MAX
182};
183
184/*RF state.*/
185enum rf_pwrstate {
186 ERFON,
187 ERFSLEEP,
188 ERFOFF
189};
190
191struct bb_reg_def {
192 u32 rfintfs;
193 u32 rfintfi;
194 u32 rfintfo;
195 u32 rfintfe;
196 u32 rf3wire_offset;
197 u32 rflssi_select;
198 u32 rftxgain_stage;
199 u32 rfhssi_para1;
200 u32 rfhssi_para2;
da17fcff 201 u32 rfsw_ctrl;
0c817338
LF		 202 u32 rfagc_control1;
203 u32 rfagc_control2;
da17fcff 204 u32 rfrxiq_imbal;
0c817338 205 u32 rfrx_afe;
da17fcff 206 u32 rftxiq_imbal;
0c817338 207 u32 rftx_afe;
da17fcff
LF		 208 u32 rf_rb; /* rflssi_readback */
209 u32 rf_rbpi; /* rflssi_readbackpi */
0c817338
LF		 210};
211
212enum io_type {
213 IO_CMD_PAUSE_DM_BY_SCAN = 0,
214 IO_CMD_RESUME_DM_BY_SCAN = 1,
215};
216
217enum hw_variables {
218 HW_VAR_ETHER_ADDR,
219 HW_VAR_MULTICAST_REG,
220 HW_VAR_BASIC_RATE,
221 HW_VAR_BSSID,
222 HW_VAR_MEDIA_STATUS,
223 HW_VAR_SECURITY_CONF,
224 HW_VAR_BEACON_INTERVAL,
225 HW_VAR_ATIM_WINDOW,
226 HW_VAR_LISTEN_INTERVAL,
227 HW_VAR_CS_COUNTER,
228 HW_VAR_DEFAULTKEY0,
229 HW_VAR_DEFAULTKEY1,
230 HW_VAR_DEFAULTKEY2,
231 HW_VAR_DEFAULTKEY3,
232 HW_VAR_SIFS,
233 HW_VAR_DIFS,
234 HW_VAR_EIFS,
235 HW_VAR_SLOT_TIME,
236 HW_VAR_ACK_PREAMBLE,
237 HW_VAR_CW_CONFIG,
238 HW_VAR_CW_VALUES,
239 HW_VAR_RATE_FALLBACK_CONTROL,
240 HW_VAR_CONTENTION_WINDOW,
241 HW_VAR_RETRY_COUNT,
242 HW_VAR_TR_SWITCH,
243 HW_VAR_COMMAND,
244 HW_VAR_WPA_CONFIG,
245 HW_VAR_AMPDU_MIN_SPACE,
246 HW_VAR_SHORTGI_DENSITY,
247 HW_VAR_AMPDU_FACTOR,
248 HW_VAR_MCS_RATE_AVAILABLE,
249 HW_VAR_AC_PARAM,
250 HW_VAR_ACM_CTRL,
251 HW_VAR_DIS_Req_Qsize,
252 HW_VAR_CCX_CHNL_LOAD,
253 HW_VAR_CCX_NOISE_HISTOGRAM,
254 HW_VAR_CCX_CLM_NHM,
255 HW_VAR_TxOPLimit,
256 HW_VAR_TURBO_MODE,
257 HW_VAR_RF_STATE,
258 HW_VAR_RF_OFF_BY_HW,
259 HW_VAR_BUS_SPEED,
260 HW_VAR_SET_DEV_POWER,
261
262 HW_VAR_RCR,
263 HW_VAR_RATR_0,
264 HW_VAR_RRSR,
265 HW_VAR_CPU_RST,
266 HW_VAR_CECHK_BSSID,
267 HW_VAR_LBK_MODE,
268 HW_VAR_AES_11N_FIX,
269 HW_VAR_USB_RX_AGGR,
270 HW_VAR_USER_CONTROL_TURBO_MODE,
271 HW_VAR_RETRY_LIMIT,
272 HW_VAR_INIT_TX_RATE,
273 HW_VAR_TX_RATE_REG,
274 HW_VAR_EFUSE_USAGE,
275 HW_VAR_EFUSE_BYTES,
276 HW_VAR_AUTOLOAD_STATUS,
277 HW_VAR_RF_2R_DISABLE,
278 HW_VAR_SET_RPWM,
279 HW_VAR_H2C_FW_PWRMODE,
280 HW_VAR_H2C_FW_JOINBSSRPT,
281 HW_VAR_FW_PSMODE_STATUS,
282 HW_VAR_1X1_RECV_COMBINE,
283 HW_VAR_STOP_SEND_BEACON,
284 HW_VAR_TSF_TIMER,
285 HW_VAR_IO_CMD,
286
287 HW_VAR_RF_RECOVERY,
288 HW_VAR_H2C_FW_UPDATE_GTK,
289 HW_VAR_WF_MASK,
290 HW_VAR_WF_CRC,
291 HW_VAR_WF_IS_MAC_ADDR,
292 HW_VAR_H2C_FW_OFFLOAD,
293 HW_VAR_RESET_WFCRC,
294
295 HW_VAR_HANDLE_FW_C2H,
296 HW_VAR_DL_FW_RSVD_PAGE,
297 HW_VAR_AID,
298 HW_VAR_HW_SEQ_ENABLE,
299 HW_VAR_CORRECT_TSF,
300 HW_VAR_BCN_VALID,
301 HW_VAR_FWLPS_RF_ON,
302 HW_VAR_DUAL_TSF_RST,
303 HW_VAR_SWITCH_EPHY_WoWLAN,
304 HW_VAR_INT_MIGRATION,
305 HW_VAR_INT_AC,
306 HW_VAR_RF_TIMING,
307
308 HW_VAR_MRC,
309
310 HW_VAR_MGT_FILTER,
311 HW_VAR_CTRL_FILTER,
312 HW_VAR_DATA_FILTER,
313};
314
315enum _RT_MEDIA_STATUS {
316 RT_MEDIA_DISCONNECT = 0,
317 RT_MEDIA_CONNECT = 1
318};
319
320enum rt_oem_id {
321 RT_CID_DEFAULT = 0,
322 RT_CID_8187_ALPHA0 = 1,
323 RT_CID_8187_SERCOMM_PS = 2,
324 RT_CID_8187_HW_LED = 3,
325 RT_CID_8187_NETGEAR = 4,
326 RT_CID_WHQL = 5,
327 RT_CID_819x_CAMEO = 6,
328 RT_CID_819x_RUNTOP = 7,
329 RT_CID_819x_Senao = 8,
330 RT_CID_TOSHIBA = 9,
331 RT_CID_819x_Netcore = 10,
332 RT_CID_Nettronix = 11,
333 RT_CID_DLINK = 12,
334 RT_CID_PRONET = 13,
335 RT_CID_COREGA = 14,
336 RT_CID_819x_ALPHA = 15,
337 RT_CID_819x_Sitecom = 16,
338 RT_CID_CCX = 17,
339 RT_CID_819x_Lenovo = 18,
340 RT_CID_819x_QMI = 19,
341 RT_CID_819x_Edimax_Belkin = 20,
342 RT_CID_819x_Sercomm_Belkin = 21,
343 RT_CID_819x_CAMEO1 = 22,
344 RT_CID_819x_MSI = 23,
345 RT_CID_819x_Acer = 24,
346 RT_CID_819x_HP = 27,
347 RT_CID_819x_CLEVO = 28,
348 RT_CID_819x_Arcadyan_Belkin = 29,
349 RT_CID_819x_SAMSUNG = 30,
350 RT_CID_819x_WNC_COREGA = 31,
351 RT_CID_819x_Foxcoon = 32,
352 RT_CID_819x_DELL = 33,
0f015453
LF		 353 RT_CID_819x_PRONETS = 34,
354 RT_CID_819x_Edimax_ASUS = 35,
355 RT_CID_NETGEAR = 36,
356 RT_CID_PLANEX = 37,
357 RT_CID_CC_C = 38,
0c817338
LF		 358};
359
360enum hw_descs {
361 HW_DESC_OWN,
362 HW_DESC_RXOWN,
363 HW_DESC_TX_NEXTDESC_ADDR,
364 HW_DESC_TXBUFF_ADDR,
365 HW_DESC_RXBUFF_ADDR,
366 HW_DESC_RXPKT_LEN,
367 HW_DESC_RXERO,
368};
369
370enum prime_sc {
371 PRIME_CHNL_OFFSET_DONT_CARE = 0,
372 PRIME_CHNL_OFFSET_LOWER = 1,
373 PRIME_CHNL_OFFSET_UPPER = 2,
374};
375
376enum rf_type {
377 RF_1T1R = 0,
378 RF_1T2R = 1,
379 RF_2T2R = 2,
e97b775d 380 RF_2T2R_GREEN = 3,
0c817338
LF		 381};
382
383enum ht_channel_width {
384 HT_CHANNEL_WIDTH_20 = 0,
385 HT_CHANNEL_WIDTH_20_40 = 1,
386};
387
388/* Ref: 802.11i sepc D10.0 7.3.2.25.1
389Cipher Suites Encryption Algorithms */
390enum rt_enc_alg {
391 NO_ENCRYPTION = 0,
392 WEP40_ENCRYPTION = 1,
393 TKIP_ENCRYPTION = 2,
394 RSERVED_ENCRYPTION = 3,
395 AESCCMP_ENCRYPTION = 4,
396 WEP104_ENCRYPTION = 5,
2461c7d6 397 AESCMAC_ENCRYPTION = 6, /*IEEE802.11w */
0c817338
LF		 398};
399
400enum rtl_hal_state {
401 _HAL_STATE_STOP = 0,
402 _HAL_STATE_START = 1,
403};
404
7ad0ce35
LF		 405enum rtl_desc92_rate {
406 DESC92_RATE1M = 0x00,
407 DESC92_RATE2M = 0x01,
408 DESC92_RATE5_5M = 0x02,
409 DESC92_RATE11M = 0x03,
410
411 DESC92_RATE6M = 0x04,
412 DESC92_RATE9M = 0x05,
413 DESC92_RATE12M = 0x06,
414 DESC92_RATE18M = 0x07,
415 DESC92_RATE24M = 0x08,
416 DESC92_RATE36M = 0x09,
417 DESC92_RATE48M = 0x0a,
418 DESC92_RATE54M = 0x0b,
419
420 DESC92_RATEMCS0 = 0x0c,
421 DESC92_RATEMCS1 = 0x0d,
422 DESC92_RATEMCS2 = 0x0e,
423 DESC92_RATEMCS3 = 0x0f,
424 DESC92_RATEMCS4 = 0x10,
425 DESC92_RATEMCS5 = 0x11,
426 DESC92_RATEMCS6 = 0x12,
427 DESC92_RATEMCS7 = 0x13,
428 DESC92_RATEMCS8 = 0x14,
429 DESC92_RATEMCS9 = 0x15,
430 DESC92_RATEMCS10 = 0x16,
431 DESC92_RATEMCS11 = 0x17,
432 DESC92_RATEMCS12 = 0x18,
433 DESC92_RATEMCS13 = 0x19,
434 DESC92_RATEMCS14 = 0x1a,
435 DESC92_RATEMCS15 = 0x1b,
436 DESC92_RATEMCS15_SG = 0x1c,
437 DESC92_RATEMCS32 = 0x20,
438};
439
0c817338
LF		 440enum rtl_var_map {
441 /*reg map */
442 SYS_ISO_CTRL = 0,
443 SYS_FUNC_EN,
444 SYS_CLK,
445 MAC_RCR_AM,
446 MAC_RCR_AB,
447 MAC_RCR_ACRC32,
448 MAC_RCR_ACF,
449 MAC_RCR_AAP,
450
451 /*efuse map */
452 EFUSE_TEST,
453 EFUSE_CTRL,
454 EFUSE_CLK,
455 EFUSE_CLK_CTRL,
456 EFUSE_PWC_EV12V,
457 EFUSE_FEN_ELDR,
458 EFUSE_LOADER_CLK_EN,
459 EFUSE_ANA8M,
460 EFUSE_HWSET_MAX_SIZE,
18d30067
G		 461 EFUSE_MAX_SECTION_MAP,
462 EFUSE_REAL_CONTENT_SIZE,
5c079d88 463 EFUSE_OOB_PROTECT_BYTES_LEN,
0c817338
LF		 464
465 /*CAM map */
466 RWCAM,
467 WCAMI,
468 RCAMO,
469 CAMDBG,
470 SECR,
471 SEC_CAM_NONE,
472 SEC_CAM_WEP40,
473 SEC_CAM_TKIP,
474 SEC_CAM_AES,
475 SEC_CAM_WEP104,
476
477 /*IMR map */
478 RTL_IMR_BCNDMAINT6, /*Beacon DMA Interrupt 6 */
479 RTL_IMR_BCNDMAINT5, /*Beacon DMA Interrupt 5 */
480 RTL_IMR_BCNDMAINT4, /*Beacon DMA Interrupt 4 */
481 RTL_IMR_BCNDMAINT3, /*Beacon DMA Interrupt 3 */
482 RTL_IMR_BCNDMAINT2, /*Beacon DMA Interrupt 2 */
483 RTL_IMR_BCNDMAINT1, /*Beacon DMA Interrupt 1 */
484 RTL_IMR_BCNDOK8, /*Beacon Queue DMA OK Interrup 8 */
485 RTL_IMR_BCNDOK7, /*Beacon Queue DMA OK Interrup 7 */
486 RTL_IMR_BCNDOK6, /*Beacon Queue DMA OK Interrup 6 */
487 RTL_IMR_BCNDOK5, /*Beacon Queue DMA OK Interrup 5 */
488 RTL_IMR_BCNDOK4, /*Beacon Queue DMA OK Interrup 4 */
489 RTL_IMR_BCNDOK3, /*Beacon Queue DMA OK Interrup 3 */
490 RTL_IMR_BCNDOK2, /*Beacon Queue DMA OK Interrup 2 */
491 RTL_IMR_BCNDOK1, /*Beacon Queue DMA OK Interrup 1 */
492 RTL_IMR_TIMEOUT2, /*Timeout interrupt 2 */
493 RTL_IMR_TIMEOUT1, /*Timeout interrupt 1 */
494 RTL_IMR_TXFOVW, /*Transmit FIFO Overflow */
495 RTL_IMR_PSTIMEOUT, /*Power save time out interrupt */
496 RTL_IMR_BcnInt, /*Beacon DMA Interrupt 0 */
497 RTL_IMR_RXFOVW, /*Receive FIFO Overflow */
498 RTL_IMR_RDU, /*Receive Descriptor Unavailable */
499 RTL_IMR_ATIMEND, /*For 92C,ATIM Window End Interrupt */
500 RTL_IMR_BDOK, /*Beacon Queue DMA OK Interrup */
501 RTL_IMR_HIGHDOK, /*High Queue DMA OK Interrupt */
e97b775d 502 RTL_IMR_COMDOK, /*Command Queue DMA OK Interrupt*/
0c817338
LF		 503 RTL_IMR_TBDOK, /*Transmit Beacon OK interrup */
504 RTL_IMR_MGNTDOK, /*Management Queue DMA OK Interrupt */
505 RTL_IMR_TBDER, /*For 92C,Transmit Beacon Error Interrupt */
506 RTL_IMR_BKDOK, /*AC_BK DMA OK Interrupt */
507 RTL_IMR_BEDOK, /*AC_BE DMA OK Interrupt */
508 RTL_IMR_VIDOK, /*AC_VI DMA OK Interrupt */
509 RTL_IMR_VODOK, /*AC_VO DMA Interrupt */
510 RTL_IMR_ROK, /*Receive DMA OK Interrupt */
e97b775d
LF		 511 RTL_IBSS_INT_MASKS, /*(RTL_IMR_BcnInt | RTL_IMR_TBDOK |
512 * RTL_IMR_TBDER) */
0f015453 513 RTL_IMR_C2HCMD, /*fw interrupt*/
0c817338
LF		 514
515 /*CCK Rates, TxHT = 0 */
516 RTL_RC_CCK_RATE1M,
517 RTL_RC_CCK_RATE2M,
518 RTL_RC_CCK_RATE5_5M,
519 RTL_RC_CCK_RATE11M,
520
521 /*OFDM Rates, TxHT = 0 */
522 RTL_RC_OFDM_RATE6M,
523 RTL_RC_OFDM_RATE9M,
524 RTL_RC_OFDM_RATE12M,
525 RTL_RC_OFDM_RATE18M,
526 RTL_RC_OFDM_RATE24M,
527 RTL_RC_OFDM_RATE36M,
528 RTL_RC_OFDM_RATE48M,
529 RTL_RC_OFDM_RATE54M,
530
531 RTL_RC_HT_RATEMCS7,
532 RTL_RC_HT_RATEMCS15,
533
534 /*keep it last */
535 RTL_VAR_MAP_MAX,
536};
537
538/*Firmware PS mode for control LPS.*/
539enum _fw_ps_mode {
540 FW_PS_ACTIVE_MODE = 0,
541 FW_PS_MIN_MODE = 1,
542 FW_PS_MAX_MODE = 2,
543 FW_PS_DTIM_MODE = 3,
544 FW_PS_VOIP_MODE = 4,
545 FW_PS_UAPSD_WMM_MODE = 5,
546 FW_PS_UAPSD_MODE = 6,
547 FW_PS_IBSS_MODE = 7,
548 FW_PS_WWLAN_MODE = 8,
549 FW_PS_PM_Radio_Off = 9,
550 FW_PS_PM_Card_Disable = 10,
551};
552
553enum rt_psmode {
554 EACTIVE, /*Active/Continuous access. */
555 EMAXPS, /*Max power save mode. */
556 EFASTPS, /*Fast power save mode. */
557 EAUTOPS, /*Auto power save mode. */
558};
559
560/*LED related.*/
561enum led_ctl_mode {
562 LED_CTL_POWER_ON = 1,
563 LED_CTL_LINK = 2,
564 LED_CTL_NO_LINK = 3,
565 LED_CTL_TX = 4,
566 LED_CTL_RX = 5,
567 LED_CTL_SITE_SURVEY = 6,
568 LED_CTL_POWER_OFF = 7,
569 LED_CTL_START_TO_LINK = 8,
570 LED_CTL_START_WPS = 9,
571 LED_CTL_STOP_WPS = 10,
572};
573
574enum rtl_led_pin {
575 LED_PIN_GPIO0,
576 LED_PIN_LED0,
577 LED_PIN_LED1,
578 LED_PIN_LED2
579};
580
581/*QoS related.*/
582/*acm implementation method.*/
583enum acm_method {
584 eAcmWay0_SwAndHw = 0,
585 eAcmWay1_HW = 1,
586 eAcmWay2_SW = 2,
587};
588
e97b775d
LF		 589enum macphy_mode {
590 SINGLEMAC_SINGLEPHY = 0,
591 DUALMAC_DUALPHY,
592 DUALMAC_SINGLEPHY,
593};
594
595enum band_type {
596 BAND_ON_2_4G = 0,
597 BAND_ON_5G,
598 BAND_ON_BOTH,
599 BANDMAX
600};
601
0c817338
LF		 602/*aci/aifsn Field.
603Ref: WMM spec 2.2.2: WME Parameter Element, p.12.*/
604union aci_aifsn {
605 u8 char_data;
606
607 struct {
608 u8 aifsn:4;
609 u8 acm:1;
610 u8 aci:2;
611 u8 reserved:1;
612 } f; /* Field */
613};
614
615/*mlme related.*/
616enum wireless_mode {
617 WIRELESS_MODE_UNKNOWN = 0x00,
618 WIRELESS_MODE_A = 0x01,
619 WIRELESS_MODE_B = 0x02,
620 WIRELESS_MODE_G = 0x04,
621 WIRELESS_MODE_AUTO = 0x08,
622 WIRELESS_MODE_N_24G = 0x10,
623 WIRELESS_MODE_N_5G = 0x20
624};
625
18d30067
G		 626#define IS_WIRELESS_MODE_A(wirelessmode) \
627 (wirelessmode == WIRELESS_MODE_A)
628#define IS_WIRELESS_MODE_B(wirelessmode) \
629 (wirelessmode == WIRELESS_MODE_B)
630#define IS_WIRELESS_MODE_G(wirelessmode) \
631 (wirelessmode == WIRELESS_MODE_G)
632#define IS_WIRELESS_MODE_N_24G(wirelessmode) \
633 (wirelessmode == WIRELESS_MODE_N_24G)
634#define IS_WIRELESS_MODE_N_5G(wirelessmode) \
635 (wirelessmode == WIRELESS_MODE_N_5G)
636
0c817338
LF		 637enum ratr_table_mode {
638 RATR_INX_WIRELESS_NGB = 0,
639 RATR_INX_WIRELESS_NG = 1,
640 RATR_INX_WIRELESS_NB = 2,
641 RATR_INX_WIRELESS_N = 3,
642 RATR_INX_WIRELESS_GB = 4,
643 RATR_INX_WIRELESS_G = 5,
644 RATR_INX_WIRELESS_B = 6,
645 RATR_INX_WIRELESS_MC = 7,
646 RATR_INX_WIRELESS_A = 8,
647};
648
649enum rtl_link_state {
650 MAC80211_NOLINK = 0,
651 MAC80211_LINKING = 1,
652 MAC80211_LINKED = 2,
653 MAC80211_LINKED_SCANNING = 3,
654};
655
656enum act_category {
657 ACT_CAT_QOS = 1,
658 ACT_CAT_DLS = 2,
659 ACT_CAT_BA = 3,
660 ACT_CAT_HT = 7,
661 ACT_CAT_WMM = 17,
662};
663
664enum ba_action {
665 ACT_ADDBAREQ = 0,
666 ACT_ADDBARSP = 1,
667 ACT_DELBA = 2,
668};
669
0f015453
LF		 670enum rt_polarity_ctl {
671 RT_POLARITY_LOW_ACT = 0,
672 RT_POLARITY_HIGH_ACT = 1,
673};
674
0c817338
LF		 675struct octet_string {
676 u8 *octet;
677 u16 length;
678};
679
680struct rtl_hdr_3addr {
681 __le16 frame_ctl;
682 __le16 duration_id;
683 u8 addr1[ETH_ALEN];
684 u8 addr2[ETH_ALEN];
685 u8 addr3[ETH_ALEN];
686 __le16 seq_ctl;
687 u8 payload[0];
e137478b 688} __packed;
0c817338
LF		 689
690struct rtl_info_element {
691 u8 id;
692 u8 len;
693 u8 data[0];
e137478b 694} __packed;
0c817338
LF		 695
696struct rtl_probe_rsp {
697 struct rtl_hdr_3addr header;
698 u32 time_stamp[2];
699 __le16 beacon_interval;
700 __le16 capability;
701 /*SSID, supported rates, FH params, DS params,
702 CF params, IBSS params, TIM (if beacon), RSN */
703 struct rtl_info_element info_element[0];
e137478b 704} __packed;
0c817338
LF		 705
706/*LED related.*/
707/*ledpin Identify how to implement this SW led.*/
708struct rtl_led {
709 void *hw;
710 enum rtl_led_pin ledpin;
7ea47240 711 bool ledon;
0c817338
LF		 712};
713
714struct rtl_led_ctl {
7ea47240 715 bool led_opendrain;
0c817338
LF		 716 struct rtl_led sw_led0;
717 struct rtl_led sw_led1;
718};
719
720struct rtl_qos_parameters {
721 __le16 cw_min;
722 __le16 cw_max;
723 u8 aifs;
724 u8 flag;
725 __le16 tx_op;
e137478b 726} __packed;
0c817338
LF		 727
728struct rt_smooth_data {
729 u32 elements[100]; /*array to store values */
730 u32 index; /*index to current array to store */
731 u32 total_num; /*num of valid elements */
732 u32 total_val; /*sum of valid elements */
733};
734
735struct false_alarm_statistics {
736 u32 cnt_parity_fail;
737 u32 cnt_rate_illegal;
738 u32 cnt_crc8_fail;
739 u32 cnt_mcs_fail;
e97b775d
LF		 740 u32 cnt_fast_fsync_fail;
741 u32 cnt_sb_search_fail;
0c817338
LF		 742 u32 cnt_ofdm_fail;
743 u32 cnt_cck_fail;
744 u32 cnt_all;
745};
746
747struct init_gain {
748 u8 xaagccore1;
749 u8 xbagccore1;
750 u8 xcagccore1;
751 u8 xdagccore1;
752 u8 cca;
753
754};
755
756struct wireless_stats {
757 unsigned long txbytesunicast;
758 unsigned long txbytesmulticast;
759 unsigned long txbytesbroadcast;
760 unsigned long rxbytesunicast;
761
762 long rx_snr_db[4];
763 /*Correct smoothed ss in Dbm, only used
764 in driver to report real power now. */
765 long recv_signal_power;
766 long signal_quality;
767 long last_sigstrength_inpercent;
768
769 u32 rssi_calculate_cnt;
770
771 /*Transformed, in dbm. Beautified signal
772 strength for UI, not correct. */
773 long signal_strength;
774
775 u8 rx_rssi_percentage[4];
776 u8 rx_evm_percentage[2];
777
778 struct rt_smooth_data ui_rssi;
779 struct rt_smooth_data ui_link_quality;
780};
781
782struct rate_adaptive {
783 u8 rate_adaptive_disabled;
784 u8 ratr_state;
785 u16 reserve;
786
787 u32 high_rssi_thresh_for_ra;
788 u32 high2low_rssi_thresh_for_ra;
789 u8 low2high_rssi_thresh_for_ra40m;
790 u32 low_rssi_thresh_for_ra40M;
791 u8 low2high_rssi_thresh_for_ra20m;
792 u32 low_rssi_thresh_for_ra20M;
793 u32 upper_rssi_threshold_ratr;
794 u32 middleupper_rssi_threshold_ratr;
795 u32 middle_rssi_threshold_ratr;
796 u32 middlelow_rssi_threshold_ratr;
797 u32 low_rssi_threshold_ratr;
798 u32 ultralow_rssi_threshold_ratr;
799 u32 low_rssi_threshold_ratr_40m;
800 u32 low_rssi_threshold_ratr_20m;
801 u8 ping_rssi_enable;
802 u32 ping_rssi_ratr;
803 u32 ping_rssi_thresh_for_ra;
804 u32 last_ratr;
805 u8 pre_ratr_state;
806};
807
808struct regd_pair_mapping {
809 u16 reg_dmnenum;
810 u16 reg_5ghz_ctl;
811 u16 reg_2ghz_ctl;
812};
813
814struct rtl_regulatory {
815 char alpha2[2];
816 u16 country_code;
817 u16 max_power_level;
818 u32 tp_scale;
819 u16 current_rd;
820 u16 current_rd_ext;
821 int16_t power_limit;
822 struct regd_pair_mapping *regpair;
823};
824
825struct rtl_rfkill {
826 bool rfkill_state; /*0 is off, 1 is on */
827};
828
e97b775d
LF		 829#define IQK_MATRIX_REG_NUM 8
830#define IQK_MATRIX_SETTINGS_NUM (1 + 24 + 21)
831struct iqk_matrix_regs {
32473284 832 bool iqk_done;
e97b775d
LF		 833 long value[1][IQK_MATRIX_REG_NUM];
834};
835
18d30067
G		 836struct phy_parameters {
837 u16 length;
838 u32 *pdata;
839};
840
841enum hw_param_tab_index {
842 PHY_REG_2T,
843 PHY_REG_1T,
844 PHY_REG_PG,
845 RADIOA_2T,
846 RADIOB_2T,
847 RADIOA_1T,
848 RADIOB_1T,
849 MAC_REG,
850 AGCTAB_2T,
851 AGCTAB_1T,
852 MAX_TAB
853};
854
0c817338
LF		 855struct rtl_phy {
856 struct bb_reg_def phyreg_def[4]; /*Radio A/B/C/D */
857 struct init_gain initgain_backup;
858 enum io_type current_io_type;
859
860 u8 rf_mode;
861 u8 rf_type;
862 u8 current_chan_bw;
863 u8 set_bwmode_inprogress;
864 u8 sw_chnl_inprogress;
865 u8 sw_chnl_stage;
866 u8 sw_chnl_step;
867 u8 current_channel;
868 u8 h2c_box_num;
869 u8 set_io_inprogress;
e97b775d 870 u8 lck_inprogress;
0c817338 871
e97b775d 872 /* record for power tracking */
0c817338
LF		 873 s32 reg_e94;
874 s32 reg_e9c;
875 s32 reg_ea4;
876 s32 reg_eac;
877 s32 reg_eb4;
878 s32 reg_ebc;
879 s32 reg_ec4;
880 s32 reg_ecc;
881 u8 rfpienable;
882 u8 reserve_0;
883 u16 reserve_1;
884 u32 reg_c04, reg_c08, reg_874;
885 u32 adda_backup[16];
886 u32 iqk_mac_backup[IQK_MAC_REG_NUM];
887 u32 iqk_bb_backup[10];
2461c7d6 888 bool iqk_initialized;
0c817338 889
e97b775d
LF		 890 /* Dual mac */
891 bool need_iqk;
892 struct iqk_matrix_regs iqk_matrix_regsetting[IQK_MATRIX_SETTINGS_NUM];
893
7ea47240 894 bool rfpi_enable;
0c817338
LF		 895
896 u8 pwrgroup_cnt;
7ea47240 897 u8 cck_high_power;
e97b775d 898 /* MAX_PG_GROUP groups of pwr diff by rates */
da17fcff 899 u32 mcs_offset[MAX_PG_GROUP][16];
0c817338
LF		 900 u8 default_initialgain[4];
901
e97b775d 902 /* the current Tx power level */
0c817338
LF		 903 u8 cur_cck_txpwridx;
904 u8 cur_ofdm24g_txpwridx;
905
906 u32 rfreg_chnlval[2];
7ea47240 907 bool apk_done;
e97b775d 908 u32 reg_rf3c[2]; /* pathA / pathB */
0c817338 909
3dad618b 910 /* bfsync */
0c817338
LF		 911 u8 framesync;
912 u32 framesync_c34;
913
914 u8 num_total_rfpath;
18d30067 915 struct phy_parameters hwparam_tables[MAX_TAB];
e97b775d 916 u16 rf_pathmap;
0f015453
LF		 917
918 enum rt_polarity_ctl polarity_ctl;
0c817338
LF		 919};
920
921#define MAX_TID_COUNT 9
3dad618b
C		 922#define RTL_AGG_STOP 0
923#define RTL_AGG_PROGRESS 1
924#define RTL_AGG_START 2
925#define RTL_AGG_OPERATIONAL 3
0c817338
LF		 926#define RTL_AGG_OFF 0
927#define RTL_AGG_ON 1
2461c7d6
LF		 928#define RTL_RX_AGG_START 1
929#define RTL_RX_AGG_STOP 0
0c817338
LF		 930#define RTL_AGG_EMPTYING_HW_QUEUE_ADDBA 2
931#define RTL_AGG_EMPTYING_HW_QUEUE_DELBA 3
932
933struct rtl_ht_agg {
934 u16 txq_id;
935 u16 wait_for_ba;
936 u16 start_idx;
937 u64 bitmap;
938 u32 rate_n_flags;
939 u8 agg_state;
2461c7d6 940 u8 rx_agg_state;
0c817338
LF		 941};
942
943struct rtl_tid_data {
944 u16 seq_number;
945 struct rtl_ht_agg agg;
946};
947
2461c7d6 948struct rssi_sta {
da17fcff 949 long undec_sm_pwdb;
2461c7d6
LF		 950};
951
3dad618b 952struct rtl_sta_info {
2461c7d6 953 struct list_head list;
3dad618b
C		 954 u8 ratr_index;
955 u8 wireless_mode;
956 u8 mimo_ps;
957 struct rtl_tid_data tids[MAX_TID_COUNT];
2461c7d6
LF		 958
959 /* just used for ap adhoc or mesh*/
960 struct rssi_sta rssi_stat;
3dad618b
C		 961} __packed;
962
0c817338
LF		 963struct rtl_priv;
964struct rtl_io {
965 struct device *dev;
62e63975 966 struct mutex bb_mutex;
0c817338
LF		 967
968 /*PCI MEM map */
969 unsigned long pci_mem_end; /*shared mem end */
970 unsigned long pci_mem_start; /*shared mem start */
971
972 /*PCI IO map */
973 unsigned long pci_base_addr; /*device I/O address */
974
975 void (*write8_async) (struct rtl_priv *rtlpriv, u32 addr, u8 val);
ff6ff96b
LF		 976 void (*write16_async) (struct rtl_priv *rtlpriv, u32 addr, u16 val);
977 void (*write32_async) (struct rtl_priv *rtlpriv, u32 addr, u32 val);
978 void (*writeN_sync) (struct rtl_priv *rtlpriv, u32 addr, void *buf,
979 u16 len);
0c817338 980
e97b775d
LF		 981 u8(*read8_sync) (struct rtl_priv *rtlpriv, u32 addr);
982 u16(*read16_sync) (struct rtl_priv *rtlpriv, u32 addr);
983 u32(*read32_sync) (struct rtl_priv *rtlpriv, u32 addr);
3dad618b 984
0c817338
LF		 985};
986
987struct rtl_mac {
988 u8 mac_addr[ETH_ALEN];
989 u8 mac80211_registered;
990 u8 beacon_enabled;
991
992 u32 tx_ss_num;
993 u32 rx_ss_num;
994
995 struct ieee80211_supported_band bands[IEEE80211_NUM_BANDS];
996 struct ieee80211_hw *hw;
997 struct ieee80211_vif *vif;
998 enum nl80211_iftype opmode;
999
1000 /*Probe Beacon management */
1001 struct rtl_tid_data tids[MAX_TID_COUNT];
1002 enum rtl_link_state link_state;
1003
1004 int n_channels;
1005 int n_bitrates;
1006
9c050440 1007 bool offchan_delay;
3dad618b 1008
0c817338
LF		 1009 /*filters */
1010 u32 rx_conf;
1011 u16 rx_mgt_filter;
1012 u16 rx_ctrl_filter;
1013 u16 rx_data_filter;
1014
1015 bool act_scanning;
1016 u8 cnt_after_linked;
1017
e97b775d
LF		 1018 /* early mode */
1019 /* skb wait queue */
1020 struct sk_buff_head skb_waitq[MAX_TID_COUNT];
1021 u8 earlymode_threshold;
1022
1023 /*RDG*/
1024 bool rdg_en;
0c817338 1025
e97b775d
LF		 1026 /*AP*/
1027 u8 bssid[6];
1028 u32 vendor;
1029 u8 mcs[16]; /* 16 bytes mcs for HT rates. */
1030 u32 basic_rates; /* b/g rates */
0c817338
LF		 1031 u8 ht_enable;
1032 u8 sgi_40;
1033 u8 sgi_20;
1034 u8 bw_40;
e97b775d 1035 u8 mode; /* wireless mode */
0c817338
LF		 1036 u8 slot_time;
1037 u8 short_preamble;
1038 u8 use_cts_protect;
1039 u8 cur_40_prime_sc;
1040 u8 cur_40_prime_sc_bk;
1041 u64 tsf;
1042 u8 retry_short;
1043 u8 retry_long;
1044 u16 assoc_id;
1045
e97b775d
LF		 1046 /*IBSS*/
1047 int beacon_interval;
0c817338 1048
e97b775d
LF		 1049 /*AMPDU*/
1050 u8 min_space_cfg; /*For Min spacing configurations */
0c817338
LF		 1051 u8 max_mss_density;
1052 u8 current_ampdu_factor;
1053 u8 current_ampdu_density;
1054
1055 /*QOS & EDCA */
1056 struct ieee80211_tx_queue_params edca_param[RTL_MAC80211_NUM_QUEUE];
1057 struct rtl_qos_parameters ac[AC_MAX];
0f015453
LF		 1058
1059 /* counters */
1060 u64 last_txok_cnt;
1061 u64 last_rxok_cnt;
1062 u32 last_bt_edca_ul;
1063 u32 last_bt_edca_dl;
1064};
1065
1066struct btdm_8723 {
1067 bool all_off;
1068 bool agc_table_en;
1069 bool adc_back_off_on;
1070 bool b2_ant_hid_en;
1071 bool low_penalty_rate_adaptive;
1072 bool rf_rx_lpf_shrink;
1073 bool reject_aggre_pkt;
1074 bool tra_tdma_on;
1075 u8 tra_tdma_nav;
1076 u8 tra_tdma_ant;
1077 bool tdma_on;
1078 u8 tdma_ant;
1079 u8 tdma_nav;
1080 u8 tdma_dac_swing;
1081 u8 fw_dac_swing_lvl;
1082 bool ps_tdma_on;
1083 u8 ps_tdma_byte[5];
1084 bool pta_on;
1085 u32 val_0x6c0;
1086 u32 val_0x6c8;
1087 u32 val_0x6cc;
1088 bool sw_dac_swing_on;
1089 u32 sw_dac_swing_lvl;
1090 u32 wlan_act_hi;
1091 u32 wlan_act_lo;
1092 u32 bt_retry_index;
1093 bool dec_bt_pwr;
1094 bool ignore_wlan_act;
1095};
1096
1097struct bt_coexist_8723 {
1098 u32 high_priority_tx;
1099 u32 high_priority_rx;
1100 u32 low_priority_tx;
1101 u32 low_priority_rx;
1102 u8 c2h_bt_info;
1103 bool c2h_bt_info_req_sent;
1104 bool c2h_bt_inquiry_page;
1105 u32 bt_inq_page_start_time;
1106 u8 bt_retry_cnt;
1107 u8 c2h_bt_info_original;
1108 u8 bt_inquiry_page_cnt;
1109 struct btdm_8723 btdm;
0c817338
LF		 1110};
1111
1112struct rtl_hal {
1113 struct ieee80211_hw *hw;
0f015453 1114 struct bt_coexist_8723 hal_coex_8723;
2461c7d6 1115 bool up_first_time;
2461c7d6
LF		 1116 bool being_init_adapter;
1117 bool bbrf_ready;
1118
0c817338
LF		 1119 enum intf_type interface;
1120 u16 hw_type; /*92c or 92d or 92s and so on */
e97b775d 1121 u8 ic_class;
0c817338 1122 u8 oem_id;
18d30067 1123 u32 version; /*version of chip */
0c817338
LF		 1124 u8 state; /*stop 0, start 1 */
1125
1126 /*firmware */
e97b775d 1127 u32 fwsize;
0c817338 1128 u8 *pfirmware;
18d30067
G		 1129 u16 fw_version;
1130 u16 fw_subversion;
7ea47240 1131 bool h2c_setinprogress;
0c817338 1132 u8 last_hmeboxnum;
2461c7d6 1133 bool fw_ready;
0c817338
LF		 1134 /*Reserve page start offset except beacon in TxQ. */
1135 u8 fw_rsvdpage_startoffset;
e97b775d
LF		 1136 u8 h2c_txcmd_seq;
1137
1138 /* FW Cmd IO related */
1139 u16 fwcmd_iomap;
1140 u32 fwcmd_ioparam;
1141 bool set_fwcmd_inprogress;
1142 u8 current_fwcmd_io;
1143
1144 /**/
1145 bool driver_going2unload;
1146
1147 /*AMPDU init min space*/
1148 u8 minspace_cfg; /*For Min spacing configurations */
1149
1150 /* Dual mac */
1151 enum macphy_mode macphymode;
1152 enum band_type current_bandtype; /* 0:2.4G, 1:5G */
1153 enum band_type current_bandtypebackup;
1154 enum band_type bandset;
1155 /* dual MAC 0--Mac0 1--Mac1 */
1156 u32 interfaceindex;
1157 /* just for DualMac S3S4 */
1158 u8 macphyctl_reg;
1159 bool earlymode_enable;
1160 /* Dual mac*/
1161 bool during_mac0init_radiob;
1162 bool during_mac1init_radioa;
1163 bool reloadtxpowerindex;
1164 /* True if IMR or IQK have done
1165 for 2.4G in scan progress */
1166 bool load_imrandiqk_setting_for2g;
1167
1168 bool disable_amsdu_8k;
2461c7d6
LF		 1169 bool master_of_dmsp;
1170 bool slave_of_dmsp;
0c817338
LF		 1171};
1172
1173struct rtl_security {
1174 /*default 0 */
1175 bool use_sw_sec;
1176
1177 bool being_setkey;
1178 bool use_defaultkey;
1179 /*Encryption Algorithm for Unicast Packet */
1180 enum rt_enc_alg pairwise_enc_algorithm;
1181 /*Encryption Algorithm for Brocast/Multicast */
1182 enum rt_enc_alg group_enc_algorithm;
3dad618b
C		 1183 /*Cam Entry Bitmap */
1184 u32 hwsec_cam_bitmap;
1185 u8 hwsec_cam_sta_addr[TOTAL_CAM_ENTRY][ETH_ALEN];
0c817338
LF		 1186 /*local Key buffer, indx 0 is for
1187 pairwise key 1-4 is for agoup key. */
1188 u8 key_buf[KEY_BUF_SIZE][MAX_KEY_LEN];
1189 u8 key_len[KEY_BUF_SIZE];
1190
1191 /*The pointer of Pairwise Key,
1192 it always points to KeyBuf[4] */
1193 u8 *pairwise_key;
1194};
1195
1196struct rtl_dm {
e97b775d 1197 /*PHY status for Dynamic Management */
da17fcff
LF		 1198 long entry_min_undec_sm_pwdb;
1199 long undec_sm_pwdb; /*out dm */
1200 long entry_max_undec_sm_pwdb;
7ea47240
LF		 1201 bool dm_initialgain_enable;
1202 bool dynamic_txpower_enable;
1203 bool current_turbo_edca;
1204 bool is_any_nonbepkts; /*out dm */
1205 bool is_cur_rdlstate;
3dad618b 1206 bool txpower_trackinginit;
7ea47240
LF		 1207 bool disable_framebursting;
1208 bool cck_inch14;
1209 bool txpower_tracking;
1210 bool useramask;
1211 bool rfpath_rxenable[4];
e97b775d
LF		 1212 bool inform_fw_driverctrldm;
1213 bool current_mrc_switch;
1214 u8 txpowercount;
0c817338 1215
e97b775d 1216 u8 thermalvalue_rxgain;
0c817338
LF		 1217 u8 thermalvalue_iqk;
1218 u8 thermalvalue_lck;
1219 u8 thermalvalue;
1220 u8 last_dtp_lvl;
e97b775d
LF		 1221 u8 thermalvalue_avg[AVG_THERMAL_NUM];
1222 u8 thermalvalue_avg_index;
1223 bool done_txpower;
0c817338 1224 u8 dynamic_txhighpower_lvl; /*Tx high power level */
e97b775d 1225 u8 dm_flag; /*Indicate each dynamic mechanism's status. */
0c817338
LF		 1226 u8 dm_type;
1227 u8 txpower_track_control;
e97b775d
LF		 1228 bool interrupt_migration;
1229 bool disable_tx_int;
0c817338
LF		 1230 char ofdm_index[2];
1231 char cck_index;
2461c7d6
LF		 1232
1233 /* DMSP */
1234 bool supp_phymode_switch;
0c817338
LF		 1235};
1236
e97b775d 1237#define EFUSE_MAX_LOGICAL_SIZE 256
0c817338
LF		 1238
1239struct rtl_efuse {
e97b775d 1240 bool autoLoad_ok;
0c817338
LF		 1241 bool bootfromefuse;
1242 u16 max_physical_size;
0c817338
LF		 1243
1244 u8 efuse_map[2][EFUSE_MAX_LOGICAL_SIZE];
1245 u16 efuse_usedbytes;
1246 u8 efuse_usedpercentage;
e97b775d
LF		 1247#ifdef EFUSE_REPG_WORKAROUND
1248 bool efuse_re_pg_sec1flag;
1249 u8 efuse_re_pg_data[8];
1250#endif
0c817338
LF		 1251
1252 u8 autoload_failflag;
e97b775d 1253 u8 autoload_status;
0c817338
LF		 1254
1255 short epromtype;
1256 u16 eeprom_vid;
1257 u16 eeprom_did;
1258 u16 eeprom_svid;
1259 u16 eeprom_smid;
1260 u8 eeprom_oemid;
1261 u16 eeprom_channelplan;
1262 u8 eeprom_version;
18d30067
G		 1263 u8 board_type;
1264 u8 external_pa;
0c817338
LF		 1265
1266 u8 dev_addr[6];
1267
7ea47240 1268 bool txpwr_fromeprom;
e97b775d 1269 u8 eeprom_crystalcap;
0c817338 1270 u8 eeprom_tssi[2];
e97b775d
LF		 1271 u8 eeprom_tssi_5g[3][2]; /* for 5GL/5GM/5GH band. */
1272 u8 eeprom_pwrlimit_ht20[CHANNEL_GROUP_MAX];
1273 u8 eeprom_pwrlimit_ht40[CHANNEL_GROUP_MAX];
1274 u8 eeprom_chnlarea_txpwr_cck[2][CHANNEL_GROUP_MAX_2G];
1275 u8 eeprom_chnlarea_txpwr_ht40_1s[2][CHANNEL_GROUP_MAX];
da17fcff 1276 u8 eprom_chnl_txpwr_ht40_2sdf[2][CHANNEL_GROUP_MAX];
e97b775d
LF		 1277 u8 txpwrlevel_cck[2][CHANNEL_MAX_NUMBER_2G];
1278 u8 txpwrlevel_ht40_1s[2][CHANNEL_MAX_NUMBER]; /*For HT 40MHZ pwr */
1279 u8 txpwrlevel_ht40_2s[2][CHANNEL_MAX_NUMBER]; /*For HT 40MHZ pwr */
1280
1281 u8 internal_pa_5g[2]; /* pathA / pathB */
1282 u8 eeprom_c9;
1283 u8 eeprom_cc;
0c817338
LF		 1284
1285 /*For power group */
e97b775d
LF		 1286 u8 eeprom_pwrgroup[2][3];
1287 u8 pwrgroup_ht20[2][CHANNEL_MAX_NUMBER];
1288 u8 pwrgroup_ht40[2][CHANNEL_MAX_NUMBER];
1289
1290 char txpwr_ht20diff[2][CHANNEL_MAX_NUMBER]; /*HT 20<->40 Pwr diff */
1291 /*For HT<->legacy pwr diff*/
1292 u8 txpwr_legacyhtdiff[2][CHANNEL_MAX_NUMBER];
1293 u8 txpwr_safetyflag; /* Band edge enable flag */
1294 u16 eeprom_txpowerdiff;
1295 u8 legacy_httxpowerdiff; /* Legacy to HT rate power diff */
1296 u8 antenna_txpwdiff[3];
0c817338
LF		 1297
1298 u8 eeprom_regulatory;
1299 u8 eeprom_thermalmeter;
e97b775d
LF		 1300 u8 thermalmeter[2]; /*ThermalMeter, index 0 for RFIC0, 1 for RFIC1 */
1301 u16 tssi_13dbm;
1302 u8 crystalcap; /* CrystalCap. */
1303 u8 delta_iqk;
1304 u8 delta_lck;
0c817338
LF		 1305
1306 u8 legacy_ht_txpowerdiff; /*Legacy to HT rate power diff */
7ea47240 1307 bool apk_thermalmeterignore;
e97b775d
LF		 1308
1309 bool b1x1_recvcombine;
1310 bool b1ss_support;
1311
1312 /*channel plan */
1313 u8 channel_plan;
0c817338
LF		 1314};
1315
1316struct rtl_ps_ctl {
e97b775d 1317 bool pwrdomain_protect;
7ea47240 1318 bool in_powersavemode;
0c817338 1319 bool rfchange_inprogress;
7ea47240
LF		 1320 bool swrf_processing;
1321 bool hwradiooff;
0c817338 1322
0c817338
LF		 1323 /*
1324 * just for PCIE ASPM
1325 * If it supports ASPM, Offset[560h] = 0x40,
1326 * otherwise Offset[560h] = 0x00.
1327 * */
7ea47240 1328 bool support_aspm;
3dad618b 1329
7ea47240 1330 bool support_backdoor;
0c817338
LF		 1331
1332 /*for LPS */
1333 enum rt_psmode dot11_psmode; /*Power save mode configured. */
e97b775d 1334 bool swctrl_lps;
7ea47240
LF		 1335 bool leisure_ps;
1336 bool fwctrl_lps;
0c817338
LF		 1337 u8 fwctrl_psmode;
1338 /*For Fw control LPS mode */
7ea47240 1339 u8 reg_fwctrl_lps;
0c817338 1340 /*Record Fw PS mode status. */
7ea47240 1341 bool fw_current_inpsmode;
0c817338
LF		 1342 u8 reg_max_lps_awakeintvl;
1343 bool report_linked;
1344
1345 /*for IPS */
7ea47240 1346 bool inactiveps;
0c817338
LF		 1347
1348 u32 rfoff_reason;
1349
1350 /*RF OFF Level */
1351 u32 cur_ps_level;
1352 u32 reg_rfps_level;
1353
1354 /*just for PCIE ASPM */
1355 u8 const_amdpci_aspm;
18d30067 1356 bool pwrdown_mode;
e97b775d 1357
0c817338
LF		 1358 enum rf_pwrstate inactive_pwrstate;
1359 enum rf_pwrstate rfpwr_state; /*cur power state */
e97b775d
LF		 1360
1361 /* for SW LPS*/
1362 bool sw_ps_enabled;
1363 bool state;
1364 bool state_inap;
1365 bool multi_buffered;
1366 u16 nullfunc_seq;
1367 unsigned int dtim_counter;
1368 unsigned int sleep_ms;
1369 unsigned long last_sleep_jiffies;
1370 unsigned long last_awake_jiffies;
1371 unsigned long last_delaylps_stamp_jiffies;
1372 unsigned long last_dtim;
1373 unsigned long last_beacon;
1374 unsigned long last_action;
1375 unsigned long last_slept;
0c817338
LF		 1376};
1377
1378struct rtl_stats {
0f015453 1379 u8 psaddr[ETH_ALEN];
0c817338
LF		 1380 u32 mac_time[2];
1381 s8 rssi;
1382 u8 signal;
1383 u8 noise;
1384 u16 rate; /*in 100 kbps */
1385 u8 received_channel;
1386 u8 control;
1387 u8 mask;
1388 u8 freq;
1389 u16 len;
1390 u64 tsf;
1391 u32 beacon_time;
1392 u8 nic_type;
1393 u16 length;
1394 u8 signalquality; /*in 0-100 index. */
1395 /*
1396 * Real power in dBm for this packet,
1397 * no beautification and aggregation.
1398 * */
1399 s32 recvsignalpower;
1400 s8 rxpower; /*in dBm Translate from PWdB */
1401 u8 signalstrength; /*in 0-100 index. */
7ea47240
LF		 1402 u16 hwerror:1;
1403 u16 crc:1;
1404 u16 icv:1;
1405 u16 shortpreamble:1;
0c817338
LF		 1406 u16 antenna:1;
1407 u16 decrypted:1;
1408 u16 wakeup:1;
1409 u32 timestamp_low;
1410 u32 timestamp_high;
1411
1412 u8 rx_drvinfo_size;
1413 u8 rx_bufshift;
7ea47240 1414 bool isampdu;
e97b775d 1415 bool isfirst_ampdu;
0c817338
LF		 1416 bool rx_is40Mhzpacket;
1417 u32 rx_pwdb_all;
1418 u8 rx_mimo_signalstrength[4]; /*in 0~100 index */
da17fcff 1419 s8 rx_mimo_sig_qual[2];
7ea47240
LF		 1420 bool packet_matchbssid;
1421 bool is_cck;
5c079d88 1422 bool is_ht;
7ea47240
LF		 1423 bool packet_toself;
1424 bool packet_beacon; /*for rssi */
0c817338
LF		 1425 char cck_adc_pwdb[4]; /*for rx path selection */
1426};
1427
1428struct rt_link_detect {
2461c7d6
LF		 1429 /* count for roaming */
1430 u32 bcn_rx_inperiod;
1431 u32 roam_times;
1432
0c817338
LF		 1433 u32 num_tx_in4period[4];
1434 u32 num_rx_in4period[4];
1435
1436 u32 num_tx_inperiod;
1437 u32 num_rx_inperiod;
1438
7ea47240 1439 bool busytraffic;
2461c7d6
LF		 1440 bool tx_busy_traffic;
1441 bool rx_busy_traffic;
7ea47240
LF		 1442 bool higher_busytraffic;
1443 bool higher_busyrxtraffic;
3dad618b
C		 1444
1445 u32 tidtx_in4period[MAX_TID_COUNT][4];
1446 u32 tidtx_inperiod[MAX_TID_COUNT];
1447 bool higher_busytxtraffic[MAX_TID_COUNT];
0c817338
LF		 1448};
1449
1450struct rtl_tcb_desc {
7ea47240
LF		 1451 u8 packet_bw:1;
1452 u8 multicast:1;
1453 u8 broadcast:1;
1454
1455 u8 rts_stbc:1;
1456 u8 rts_enable:1;
1457 u8 cts_enable:1;
1458 u8 rts_use_shortpreamble:1;
1459 u8 rts_use_shortgi:1;
0c817338 1460 u8 rts_sc:1;
7ea47240 1461 u8 rts_bw:1;
0c817338
LF		 1462 u8 rts_rate;
1463
1464 u8 use_shortgi:1;
1465 u8 use_shortpreamble:1;
1466 u8 use_driver_rate:1;
1467 u8 disable_ratefallback:1;
1468
1469 u8 ratr_index;
1470 u8 mac_id;
1471 u8 hw_rate;
e97b775d
LF		 1472
1473 u8 last_inipkt:1;
1474 u8 cmd_or_init:1;
1475 u8 queue_index;
1476
1477 /* early mode */
1478 u8 empkt_num;
1479 /* The max value by HW */
1480 u32 empkt_len[5];
0c817338
LF		 1481};
1482
1483struct rtl_hal_ops {
1484 int (*init_sw_vars) (struct ieee80211_hw *hw);
1485 void (*deinit_sw_vars) (struct ieee80211_hw *hw);
62e63975 1486 void (*read_chip_version)(struct ieee80211_hw *hw);
0c817338
LF		 1487 void (*read_eeprom_info) (struct ieee80211_hw *hw);
1488 void (*interrupt_recognized) (struct ieee80211_hw *hw,
1489 u32 *p_inta, u32 *p_intb);
1490 int (*hw_init) (struct ieee80211_hw *hw);
1491 void (*hw_disable) (struct ieee80211_hw *hw);
e97b775d
LF		 1492 void (*hw_suspend) (struct ieee80211_hw *hw);
1493 void (*hw_resume) (struct ieee80211_hw *hw);
0c817338
LF		 1494 void (*enable_interrupt) (struct ieee80211_hw *hw);
1495 void (*disable_interrupt) (struct ieee80211_hw *hw);
1496 int (*set_network_type) (struct ieee80211_hw *hw,
1497 enum nl80211_iftype type);
18d30067
G		 1498 void (*set_chk_bssid)(struct ieee80211_hw *hw,
1499 bool check_bssid);
0c817338
LF		 1500 void (*set_bw_mode) (struct ieee80211_hw *hw,
1501 enum nl80211_channel_type ch_type);
e97b775d 1502 u8(*switch_channel) (struct ieee80211_hw *hw);
0c817338
LF		 1503 void (*set_qos) (struct ieee80211_hw *hw, int aci);
1504 void (*set_bcn_reg) (struct ieee80211_hw *hw);
1505 void (*set_bcn_intv) (struct ieee80211_hw *hw);
1506 void (*update_interrupt_mask) (struct ieee80211_hw *hw,
1507 u32 add_msr, u32 rm_msr);
1508 void (*get_hw_reg) (struct ieee80211_hw *hw, u8 variable, u8 *val);
1509 void (*set_hw_reg) (struct ieee80211_hw *hw, u8 variable, u8 *val);
3dad618b
C		 1510 void (*update_rate_tbl) (struct ieee80211_hw *hw,
1511 struct ieee80211_sta *sta, u8 rssi_level);
0c817338
LF		 1512 void (*update_rate_mask) (struct ieee80211_hw *hw, u8 rssi_level);
1513 void (*fill_tx_desc) (struct ieee80211_hw *hw,
1514 struct ieee80211_hdr *hdr, u8 *pdesc_tx,
1515 struct ieee80211_tx_info *info,
36323f81 1516 struct ieee80211_sta *sta,
3dad618b
C		 1517 struct sk_buff *skb, u8 hw_queue,
1518 struct rtl_tcb_desc *ptcb_desc);
3dad618b 1519 void (*fill_fake_txdesc) (struct ieee80211_hw *hw, u8 *pDesc,
18d30067 1520 u32 buffer_len, bool bIsPsPoll);
0c817338 1521 void (*fill_tx_cmddesc) (struct ieee80211_hw *hw, u8 *pdesc,
7ea47240 1522 bool firstseg, bool lastseg,
0c817338 1523 struct sk_buff *skb);
62e63975 1524 bool (*cmd_send_packet)(struct ieee80211_hw *hw, struct sk_buff *skb);
7ea47240 1525 bool (*query_rx_desc) (struct ieee80211_hw *hw,
0c817338
LF		 1526 struct rtl_stats *stats,
1527 struct ieee80211_rx_status *rx_status,
1528 u8 *pdesc, struct sk_buff *skb);
1529 void (*set_channel_access) (struct ieee80211_hw *hw);
7ea47240 1530 bool (*radio_onoff_checking) (struct ieee80211_hw *hw, u8 *valid);
0c817338
LF		 1531 void (*dm_watchdog) (struct ieee80211_hw *hw);
1532 void (*scan_operation_backup) (struct ieee80211_hw *hw, u8 operation);
7ea47240 1533 bool (*set_rf_power_state) (struct ieee80211_hw *hw,
0c817338
LF		 1534 enum rf_pwrstate rfpwr_state);
1535 void (*led_control) (struct ieee80211_hw *hw,
1536 enum led_ctl_mode ledaction);
1537 void (*set_desc) (u8 *pdesc, bool istx, u8 desc_name, u8 *val);
7ea47240 1538 u32 (*get_desc) (u8 *pdesc, bool istx, u8 desc_name);
3dad618b 1539 void (*tx_polling) (struct ieee80211_hw *hw, u8 hw_queue);
0c817338
LF		 1540 void (*enable_hw_sec) (struct ieee80211_hw *hw);
1541 void (*set_key) (struct ieee80211_hw *hw, u32 key_index,
3dad618b 1542 u8 *macaddr, bool is_group, u8 enc_algo,
0c817338
LF		 1543 bool is_wepkey, bool clear_all);
1544 void (*init_sw_leds) (struct ieee80211_hw *hw);
1545 void (*deinit_sw_leds) (struct ieee80211_hw *hw);
7ea47240 1546 u32 (*get_bbreg) (struct ieee80211_hw *hw, u32 regaddr, u32 bitmask);
0c817338
LF		 1547 void (*set_bbreg) (struct ieee80211_hw *hw, u32 regaddr, u32 bitmask,
1548 u32 data);
7ea47240 1549 u32 (*get_rfreg) (struct ieee80211_hw *hw, enum radio_path rfpath,
0c817338
LF		 1550 u32 regaddr, u32 bitmask);
1551 void (*set_rfreg) (struct ieee80211_hw *hw, enum radio_path rfpath,
1552 u32 regaddr, u32 bitmask, u32 data);
2461c7d6
LF		 1553 void (*allow_all_destaddr)(struct ieee80211_hw *hw,
1554 bool allow_all_da, bool write_into_reg);
3dad618b 1555 void (*linked_set_reg) (struct ieee80211_hw *hw);
2461c7d6
LF		 1556 void (*check_switch_to_dmdp) (struct ieee80211_hw *hw);
1557 void (*dualmac_easy_concurrent) (struct ieee80211_hw *hw);
1558 void (*dualmac_switch_to_dmdp) (struct ieee80211_hw *hw);
1472d3a8
LF		 1559 bool (*phy_rf6052_config) (struct ieee80211_hw *hw);
1560 void (*phy_rf6052_set_cck_txpower) (struct ieee80211_hw *hw,
1561 u8 *powerlevel);
1562 void (*phy_rf6052_set_ofdm_txpower) (struct ieee80211_hw *hw,
1563 u8 *ppowerlevel, u8 channel);
1564 bool (*config_bb_with_headerfile) (struct ieee80211_hw *hw,
1565 u8 configtype);
1566 bool (*config_bb_with_pgheaderfile) (struct ieee80211_hw *hw,
1567 u8 configtype);
1568 void (*phy_lc_calibrate) (struct ieee80211_hw *hw, bool is2t);
1569 void (*phy_set_bw_mode_callback) (struct ieee80211_hw *hw);
1570 void (*dm_dynamic_txpower) (struct ieee80211_hw *hw);
0f015453 1571 void (*c2h_command_handle) (struct ieee80211_hw *hw);
da17fcff
LF		 1572 void (*bt_wifi_media_status_notify) (struct ieee80211_hw *hw,
1573 bool mstate);
1574 void (*bt_coex_off_before_lps) (struct ieee80211_hw *hw);
0c817338
LF		 1575};
1576
1577struct rtl_intf_ops {
1578 /*com */
e97b775d 1579 void (*read_efuse_byte)(struct ieee80211_hw *hw, u16 _offset, u8 *pbuf);
0c817338
LF		 1580 int (*adapter_start) (struct ieee80211_hw *hw);
1581 void (*adapter_stop) (struct ieee80211_hw *hw);
2461c7d6
LF		 1582 bool (*check_buddy_priv)(struct ieee80211_hw *hw,
1583 struct rtl_priv **buddy_priv);
0c817338 1584
36323f81
TH		 1585 int (*adapter_tx) (struct ieee80211_hw *hw,
1586 struct ieee80211_sta *sta,
1587 struct sk_buff *skb,
1588 struct rtl_tcb_desc *ptcb_desc);
3dad618b 1589 void (*flush)(struct ieee80211_hw *hw, bool drop);
0c817338 1590 int (*reset_trx_ring) (struct ieee80211_hw *hw);
36323f81
TH		 1591 bool (*waitq_insert) (struct ieee80211_hw *hw,
1592 struct ieee80211_sta *sta,
1593 struct sk_buff *skb);
0c817338
LF		 1594
1595 /*pci */
1596 void (*disable_aspm) (struct ieee80211_hw *hw);
1597 void (*enable_aspm) (struct ieee80211_hw *hw);
1598
1599 /*usb */
1600};
1601
1602struct rtl_mod_params {
1603 /* default: 0 = using hardware encryption */
eb939922 1604 bool sw_crypto;
3dad618b 1605
73a253ca
LF		 1606 /* default: 0 = DBG_EMERG (0)*/
1607 int debug;
1608
3dad618b
C		 1609 /* default: 1 = using no linked power save */
1610 bool inactiveps;
1611
1612 /* default: 1 = using linked sw power save */
1613 bool swctrl_lps;
1614
1615 /* default: 1 = using linked fw power save */
1616 bool fwctrl_lps;
0c817338
LF		 1617};
1618
62e63975
LF		 1619struct rtl_hal_usbint_cfg {
1620 /* data - rx */
1621 u32 in_ep_num;
1622 u32 rx_urb_num;
1623 u32 rx_max_size;
1624
1625 /* op - rx */
1626 void (*usb_rx_hdl)(struct ieee80211_hw *, struct sk_buff *);
1627 void (*usb_rx_segregate_hdl)(struct ieee80211_hw *, struct sk_buff *,
1628 struct sk_buff_head *);
1629
1630 /* tx */
1631 void (*usb_tx_cleanup)(struct ieee80211_hw *, struct sk_buff *);
1632 int (*usb_tx_post_hdl)(struct ieee80211_hw *, struct urb *,
1633 struct sk_buff *);
1634 struct sk_buff *(*usb_tx_aggregate_hdl)(struct ieee80211_hw *,
1635 struct sk_buff_head *);
1636
1637 /* endpoint mapping */
1638 int (*usb_endpoint_mapping)(struct ieee80211_hw *hw);
17c9ac62 1639 u16 (*usb_mq_to_hwq)(__le16 fc, u16 mac80211_queue_index);
62e63975
LF		 1640};
1641
0c817338 1642struct rtl_hal_cfg {
e97b775d 1643 u8 bar_id;
3dad618b 1644 bool write_readback;
0c817338
LF		 1645 char *name;
1646 char *fw_name;
1647 struct rtl_hal_ops *ops;
1648 struct rtl_mod_params *mod_params;
62e63975 1649 struct rtl_hal_usbint_cfg *usb_interface_cfg;
0c817338
LF		 1650
1651 /*this map used for some registers or vars
1652 defined int HAL but used in MAIN */
1653 u32 maps[RTL_VAR_MAP_MAX];
1654
1655};
1656
1657struct rtl_locks {
d704300f 1658 /* mutex */
8a09d6d8 1659 struct mutex conf_mutex;
6539306b 1660 struct mutex ps_mutex;
0c817338
LF		 1661
1662 /*spin lock */
b9116b9a 1663 spinlock_t ips_lock;
0c817338
LF		 1664 spinlock_t irq_th_lock;
1665 spinlock_t h2c_lock;
1666 spinlock_t rf_ps_lock;
1667 spinlock_t rf_lock;
2461c7d6 1668 spinlock_t lps_lock;
e97b775d 1669 spinlock_t waitq_lock;
2461c7d6 1670 spinlock_t entry_list_lock;
3ce4d85b 1671 spinlock_t usb_lock;
e97b775d
LF		 1672
1673 /*Dual mac*/
1674 spinlock_t cck_and_rw_pagea_lock;
2461c7d6
LF		 1675
1676 /*Easy concurrent*/
1677 spinlock_t check_sendpkt_lock;
0c817338
LF		 1678};
1679
1680struct rtl_works {
1681 struct ieee80211_hw *hw;
1682
1683 /*timer */
1684 struct timer_list watchdog_timer;
2461c7d6 1685 struct timer_list dualmac_easyconcurrent_retrytimer;
0c817338
LF		 1686
1687 /*task */
1688 struct tasklet_struct irq_tasklet;
1689 struct tasklet_struct irq_prepare_bcn_tasklet;
1690
1691 /*work queue */
1692 struct workqueue_struct *rtl_wq;
1693 struct delayed_work watchdog_wq;
1694 struct delayed_work ips_nic_off_wq;
e97b775d
LF		 1695
1696 /* For SW LPS */
1697 struct delayed_work ps_work;
1698 struct delayed_work ps_rfon_wq;
41affd52
SG		 1699
1700 struct work_struct lps_leave_work;
0c817338
LF		 1701};
1702
1703struct rtl_debug {
1704 u32 dbgp_type[DBGP_TYPE_MAX];
1705 u32 global_debuglevel;
1706 u64 global_debugcomponents;
e97b775d
LF		 1707
1708 /* add for proc debug */
1709 struct proc_dir_entry *proc_dir;
1710 char proc_name[20];
0c817338
LF		 1711};
1712
2461c7d6
LF		 1713#define MIMO_PS_STATIC 0
1714#define MIMO_PS_DYNAMIC 1
1715#define MIMO_PS_NOLIMIT 3
1716
1717struct rtl_dualmac_easy_concurrent_ctl {
1718 enum band_type currentbandtype_backfordmdp;
1719 bool close_bbandrf_for_dmsp;
1720 bool change_to_dmdp;
1721 bool change_to_dmsp;
1722 bool switch_in_process;
1723};
1724
1725struct rtl_dmsp_ctl {
1726 bool activescan_for_slaveofdmsp;
1727 bool scan_for_anothermac_fordmsp;
1728 bool scan_for_itself_fordmsp;
1729 bool writedig_for_anothermacofdmsp;
1730 u32 curdigvalue_for_anothermacofdmsp;
1731 bool changecckpdstate_for_anothermacofdmsp;
1732 u8 curcckpdstate_for_anothermacofdmsp;
1733 bool changetxhighpowerlvl_for_anothermacofdmsp;
1734 u8 curtxhighlvl_for_anothermacofdmsp;
1735 long rssivalmin_for_anothermacofdmsp;
1736};
1737
df37a0ec
LF		 1738struct ps_t {
1739 u8 pre_ccastate;
1740 u8 cur_ccasate;
1741 u8 pre_rfstate;
1742 u8 cur_rfstate;
1743 long rssi_val_min;
1744};
1745
1746struct dig_t {
1747 u32 rssi_lowthresh;
1748 u32 rssi_highthresh;
1749 u32 fa_lowthresh;
1750 u32 fa_highthresh;
da17fcff 1751 long last_min_undec_pwdb_for_dm;
df37a0ec
LF		 1752 long rssi_highpower_lowthresh;
1753 long rssi_highpower_highthresh;
1754 u32 recover_cnt;
1755 u32 pre_igvalue;
1756 u32 cur_igvalue;
1757 long rssi_val;
1758 u8 dig_enable_flag;
1759 u8 dig_ext_port_stage;
1760 u8 dig_algorithm;
1761 u8 dig_twoport_algorithm;
1762 u8 dig_dbgmode;
1763 u8 dig_slgorithm_switch;
da17fcff
LF		 1764 u8 cursta_cstate;
1765 u8 presta_cstate;
1766 u8 curmultista_cstate;
1767 char back_val;
1768 char back_range_max;
1769 char back_range_min;
df37a0ec
LF		 1770 u8 rx_gain_range_max;
1771 u8 rx_gain_range_min;
da17fcff 1772 u8 min_undec_pwdb_for_dm;
df37a0ec
LF		 1773 u8 rssi_val_min;
1774 u8 pre_cck_pd_state;
1775 u8 cur_cck_pd_state;
1776 u8 pre_cck_fa_state;
1777 u8 cur_cck_fa_state;
1778 u8 pre_ccastate;
1779 u8 cur_ccasate;
1780 u8 large_fa_hit;
1781 u8 forbidden_igi;
1782 u8 dig_state;
1783 u8 dig_highpwrstate;
da17fcff
LF		 1784 u8 cur_sta_cstate;
1785 u8 pre_sta_cstate;
1786 u8 cur_ap_cstate;
1787 u8 pre_ap_cstate;
df37a0ec
LF		 1788 u8 cur_pd_thstate;
1789 u8 pre_pd_thstate;
1790 u8 cur_cs_ratiostate;
1791 u8 pre_cs_ratiostate;
1792 u8 backoff_enable_flag;
1793 char backoffval_range_max;
1794 char backoffval_range_min;
1795};
1796
2461c7d6
LF		 1797struct rtl_global_var {
1798 /* from this list we can get
1799 * other adapter's rtl_priv */
1800 struct list_head glb_priv_list;
1801 spinlock_t glb_list_lock;
1802};
1803
0c817338 1804struct rtl_priv {
b0302aba 1805 struct completion firmware_loading_complete;
2461c7d6
LF		 1806 struct list_head list;
1807 struct rtl_priv *buddy_priv;
1808 struct rtl_global_var *glb_var;
1809 struct rtl_dualmac_easy_concurrent_ctl easy_concurrent_ctl;
1810 struct rtl_dmsp_ctl dmsp_ctl;
0c817338
LF		 1811 struct rtl_locks locks;
1812 struct rtl_works works;
1813 struct rtl_mac mac80211;
1814 struct rtl_hal rtlhal;
1815 struct rtl_regulatory regd;
1816 struct rtl_rfkill rfkill;
1817 struct rtl_io io;
1818 struct rtl_phy phy;
1819 struct rtl_dm dm;
1820 struct rtl_security sec;
1821 struct rtl_efuse efuse;
1822
1823 struct rtl_ps_ctl psc;
1824 struct rate_adaptive ra;
1825 struct wireless_stats stats;
1826 struct rt_link_detect link_info;
1827 struct false_alarm_statistics falsealm_cnt;
1828
1829 struct rtl_rate_priv *rate_priv;
1830
2461c7d6
LF		 1831 /* sta entry list for ap adhoc or mesh */
1832 struct list_head entry_list;
1833
0c817338 1834 struct rtl_debug dbg;
b0302aba 1835 int max_fw_size;
0c817338
LF		 1836
1837 /*
1838 *hal_cfg : for diff cards
1839 *intf_ops : for diff interrface usb/pcie
1840 */
1841 struct rtl_hal_cfg *cfg;
1842 struct rtl_intf_ops *intf_ops;
1843
1844 /*this var will be set by set_bit,
1845 and was used to indicate status of
1846 interface or hardware */
1847 unsigned long status;
1848
0985dfbc
LF		 1849 /* tables for dm */
1850 struct dig_t dm_digtable;
1851 struct ps_t dm_pstable;
1852
0f015453
LF		 1853 /* section shared by individual drivers */
1854 union {
1855 struct { /* data buffer pointer for USB reads */
1856 __le32 *usb_data;
1857 int usb_data_index;
1858 bool initialized;
1859 };
1860 struct { /* section for 8723ae */
1861 bool reg_init; /* true if regs saved */
1862 u32 reg_874;
1863 u32 reg_c70;
1864 u32 reg_85c;
1865 u32 reg_a74;
1866 bool bt_operation_on;
1867 };
1868 };
30899cc6 1869
0c817338
LF		 1870 /*This must be the last item so
1871 that it points to the data allocated
1872 beyond this structure like:
1873 rtl_pci_priv or rtl_usb_priv */
1874 u8 priv[0];
1875};
1876
1877#define rtl_priv(hw) (((struct rtl_priv *)(hw)->priv))
1878#define rtl_mac(rtlpriv) (&((rtlpriv)->mac80211))
1879#define rtl_hal(rtlpriv) (&((rtlpriv)->rtlhal))
1880#define rtl_efuse(rtlpriv) (&((rtlpriv)->efuse))
1881#define rtl_psc(rtlpriv) (&((rtlpriv)->psc))
1882
e97b775d 1883
18d30067 1884/***************************************
25985edc 1885 Bluetooth Co-existence Related
18d30067
G		 1886****************************************/
1887
1888enum bt_ant_num {
1889 ANT_X2 = 0,
1890 ANT_X1 = 1,
1891};
1892
1893enum bt_co_type {
1894 BT_2WIRE = 0,
1895 BT_ISSC_3WIRE = 1,
1896 BT_ACCEL = 2,
1897 BT_CSR_BC4 = 3,
1898 BT_CSR_BC8 = 4,
1899 BT_RTL8756 = 5,
0f015453 1900 BT_RTL8723A = 6,
18d30067
G		 1901};
1902
1903enum bt_cur_state {
1904 BT_OFF = 0,
1905 BT_ON = 1,
1906};
1907
1908enum bt_service_type {
1909 BT_SCO = 0,
1910 BT_A2DP = 1,
1911 BT_HID = 2,
1912 BT_HID_IDLE = 3,
1913 BT_SCAN = 4,
1914 BT_IDLE = 5,
1915 BT_OTHER_ACTION = 6,
1916 BT_BUSY = 7,
1917 BT_OTHERBUSY = 8,
1918 BT_PAN = 9,
1919};
1920
1921enum bt_radio_shared {
1922 BT_RADIO_SHARED = 0,
1923 BT_RADIO_INDIVIDUAL = 1,
1924};
1925
1926struct bt_coexist_info {
1927
1928 /* EEPROM BT info. */
1929 u8 eeprom_bt_coexist;
1930 u8 eeprom_bt_type;
1931 u8 eeprom_bt_ant_num;
da17fcff 1932 u8 eeprom_bt_ant_isol;
18d30067
G		 1933 u8 eeprom_bt_radio_shared;
1934
1935 u8 bt_coexistence;
1936 u8 bt_ant_num;
1937 u8 bt_coexist_type;
1938 u8 bt_state;
1939 u8 bt_cur_state; /* 0:on, 1:off */
1940 u8 bt_ant_isolation; /* 0:good, 1:bad */
1941 u8 bt_pape_ctrl; /* 0:SW, 1:SW/HW dynamic */
1942 u8 bt_service;
1943 u8 bt_radio_shared_type;
1944 u8 bt_rfreg_origin_1e;
1945 u8 bt_rfreg_origin_1f;
1946 u8 bt_rssi_state;
1947 u32 ratio_tx;
1948 u32 ratio_pri;
1949 u32 bt_edca_ul;
1950 u32 bt_edca_dl;
1951
32473284
LF		 1952 bool init_set;
1953 bool bt_busy_traffic;
1954 bool bt_traffic_mode_set;
1955 bool bt_non_traffic_mode_set;
18d30067 1956
32473284
LF		 1957 bool fw_coexist_all_off;
1958 bool sw_coexist_all_off;
0f015453
LF		 1959 bool hw_coexist_all_off;
1960 u32 cstate;
18d30067 1961 u32 previous_state;
0f015453
LF		 1962 u32 cstate_h;
1963 u32 previous_state_h;
1964
18d30067 1965 u8 bt_pre_rssi_state;
0f015453 1966 u8 bt_pre_rssi_state1;
18d30067 1967
32473284
LF		 1968 u8 reg_bt_iso;
1969 u8 reg_bt_sco;
0f015453
LF		 1970 bool balance_on;
1971 u8 bt_active_zero_cnt;
1972 bool cur_bt_disabled;
1973 bool pre_bt_disabled;
1974
1975 u8 bt_profile_case;
1976 u8 bt_profile_action;
1977 bool bt_busy;
1978 bool hold_for_bt_operation;
1979 u8 lps_counter;
18d30067
G		 1980};
1981
e97b775d 1982
0c817338
LF		 1983/****************************************
1984 mem access macro define start
1985 Call endian free function when
1986 1. Read/write packet content.
1987 2. Before write integer to IO.
1988 3. After read integer from IO.
1989****************************************/
9e0bc671 1990/* Convert little data endian to host ordering */
0c817338
LF		 1991#define EF1BYTE(_val) \
1992 ((u8)(_val))
1993#define EF2BYTE(_val) \
1994 (le16_to_cpu(_val))
1995#define EF4BYTE(_val) \
1996 (le32_to_cpu(_val))
1997
3dad618b
C		 1998/* Read data from memory */
1999#define READEF1BYTE(_ptr) \
2000 EF1BYTE(*((u8 *)(_ptr)))
9e0bc671 2001/* Read le16 data from memory and convert to host ordering */
0c817338 2002#define READEF2BYTE(_ptr) \
8e2c406a 2003 EF2BYTE(*(_ptr))
3dad618b 2004#define READEF4BYTE(_ptr) \
8e2c406a 2005 EF4BYTE(*(_ptr))
0c817338 2006
3dad618b
C		 2007/* Write data to memory */
2008#define WRITEEF1BYTE(_ptr, _val) \
2009 (*((u8 *)(_ptr))) = EF1BYTE(_val)
9e0bc671 2010/* Write le16 data to memory in host ordering */
0c817338
LF		 2011#define WRITEEF2BYTE(_ptr, _val) \
2012 (*((u16 *)(_ptr))) = EF2BYTE(_val)
3dad618b 2013#define WRITEEF4BYTE(_ptr, _val) \
8e2c406a 2014 (*((u32 *)(_ptr))) = EF2BYTE(_val)
9e0bc671
LF		 2015
2016/* Create a bit mask
2017 * Examples:
2018 * BIT_LEN_MASK_32(0) => 0x00000000
2019 * BIT_LEN_MASK_32(1) => 0x00000001
2020 * BIT_LEN_MASK_32(2) => 0x00000003
2021 * BIT_LEN_MASK_32(32) => 0xFFFFFFFF
2022 */
0c817338
LF		 2023#define BIT_LEN_MASK_32(__bitlen) \
2024 (0xFFFFFFFF >> (32 - (__bitlen)))
2025#define BIT_LEN_MASK_16(__bitlen) \
2026 (0xFFFF >> (16 - (__bitlen)))
2027#define BIT_LEN_MASK_8(__bitlen) \
2028 (0xFF >> (8 - (__bitlen)))
2029
9e0bc671
LF		 2030/* Create an offset bit mask
2031 * Examples:
2032 * BIT_OFFSET_LEN_MASK_32(0, 2) => 0x00000003
2033 * BIT_OFFSET_LEN_MASK_32(16, 2) => 0x00030000
2034 */
0c817338
LF		 2035#define BIT_OFFSET_LEN_MASK_32(__bitoffset, __bitlen) \
2036 (BIT_LEN_MASK_32(__bitlen) << (__bitoffset))
2037#define BIT_OFFSET_LEN_MASK_16(__bitoffset, __bitlen) \
2038 (BIT_LEN_MASK_16(__bitlen) << (__bitoffset))
2039#define BIT_OFFSET_LEN_MASK_8(__bitoffset, __bitlen) \
2040 (BIT_LEN_MASK_8(__bitlen) << (__bitoffset))
2041
2042/*Description:
9e0bc671
LF		 2043 * Return 4-byte value in host byte ordering from
2044 * 4-byte pointer in little-endian system.
2045 */
0c817338 2046#define LE_P4BYTE_TO_HOST_4BYTE(__pstart) \
8e2c406a 2047 (EF4BYTE(*((__le32 *)(__pstart))))
0c817338 2048#define LE_P2BYTE_TO_HOST_2BYTE(__pstart) \
8e2c406a 2049 (EF2BYTE(*((__le16 *)(__pstart))))
0c817338
LF		 2050#define LE_P1BYTE_TO_HOST_1BYTE(__pstart) \
2051 (EF1BYTE(*((u8 *)(__pstart))))
2052
3dad618b
C		 2053/*Description:
2054Translate subfield (continuous bits in little-endian) of 4-byte
2055value to host byte ordering.*/
2056#define LE_BITS_TO_4BYTE(__pstart, __bitoffset, __bitlen) \
2057 ( \
2058 (LE_P4BYTE_TO_HOST_4BYTE(__pstart) >> (__bitoffset)) & \
2059 BIT_LEN_MASK_32(__bitlen) \
2060 )
2061#define LE_BITS_TO_2BYTE(__pstart, __bitoffset, __bitlen) \
2062 ( \
2063 (LE_P2BYTE_TO_HOST_2BYTE(__pstart) >> (__bitoffset)) & \
2064 BIT_LEN_MASK_16(__bitlen) \
2065 )
2066#define LE_BITS_TO_1BYTE(__pstart, __bitoffset, __bitlen) \
2067 ( \
2068 (LE_P1BYTE_TO_HOST_1BYTE(__pstart) >> (__bitoffset)) & \
2069 BIT_LEN_MASK_8(__bitlen) \
2070 )
2071
9e0bc671
LF		 2072/* Description:
2073 * Mask subfield (continuous bits in little-endian) of 4-byte value
2074 * and return the result in 4-byte value in host byte ordering.
2075 */
0c817338
LF		 2076#define LE_BITS_CLEARED_TO_4BYTE(__pstart, __bitoffset, __bitlen) \
2077 ( \
2078 LE_P4BYTE_TO_HOST_4BYTE(__pstart) & \
2079 (~BIT_OFFSET_LEN_MASK_32(__bitoffset, __bitlen)) \
2080 )
2081#define LE_BITS_CLEARED_TO_2BYTE(__pstart, __bitoffset, __bitlen) \
2082 ( \
2083 LE_P2BYTE_TO_HOST_2BYTE(__pstart) & \
2084 (~BIT_OFFSET_LEN_MASK_16(__bitoffset, __bitlen)) \
2085 )
2086#define LE_BITS_CLEARED_TO_1BYTE(__pstart, __bitoffset, __bitlen) \
2087 ( \
2088 LE_P1BYTE_TO_HOST_1BYTE(__pstart) & \
2089 (~BIT_OFFSET_LEN_MASK_8(__bitoffset, __bitlen)) \
2090 )
2091
9e0bc671
LF		 2092/* Description:
2093 * Set subfield of little-endian 4-byte value to specified value.
2094 */
3dad618b 2095#define SET_BITS_TO_LE_4BYTE(__pstart, __bitoffset, __bitlen, __val) \
8e2c406a 2096 *((u32 *)(__pstart)) = \
3dad618b
C		 2097 ( \
2098 LE_BITS_CLEARED_TO_4BYTE(__pstart, __bitoffset, __bitlen) | \
2099 ((((u32)__val) & BIT_LEN_MASK_32(__bitlen)) << (__bitoffset)) \
2100 );
2101#define SET_BITS_TO_LE_2BYTE(__pstart, __bitoffset, __bitlen, __val) \
8e2c406a 2102 *((u16 *)(__pstart)) = \
3dad618b
C		 2103 ( \
2104 LE_BITS_CLEARED_TO_2BYTE(__pstart, __bitoffset, __bitlen) | \
2105 ((((u16)__val) & BIT_LEN_MASK_16(__bitlen)) << (__bitoffset)) \
2106 );
0c817338
LF		 2107#define SET_BITS_TO_LE_1BYTE(__pstart, __bitoffset, __bitlen, __val) \
2108 *((u8 *)(__pstart)) = EF1BYTE \
2109 ( \
2110 LE_BITS_CLEARED_TO_1BYTE(__pstart, __bitoffset, __bitlen) | \
2111 ((((u8)__val) & BIT_LEN_MASK_8(__bitlen)) << (__bitoffset)) \
2112 );
2113
3dad618b
C		 2114#define N_BYTE_ALIGMENT(__value, __aligment) ((__aligment == 1) ? \
2115 (__value) : (((__value + __aligment - 1) / __aligment) * __aligment))
2116
0c817338
LF		 2117/****************************************
2118 mem access macro define end
2119****************************************/
2120
e97b775d
LF		 2121#define byte(x, n) ((x >> (8 * n)) & 0xff)
2122
3dad618b 2123#define packet_get_type(_packet) (EF1BYTE((_packet).octet[0]) & 0xFC)
0c817338
LF		 2124#define RTL_WATCH_DOG_TIME 2000
2125#define MSECS(t) msecs_to_jiffies(t)
17c9ac62
LF		 2126#define WLAN_FC_GET_VERS(fc) (le16_to_cpu(fc) & IEEE80211_FCTL_VERS)
2127#define WLAN_FC_GET_TYPE(fc) (le16_to_cpu(fc) & IEEE80211_FCTL_FTYPE)
2128#define WLAN_FC_GET_STYPE(fc) (le16_to_cpu(fc) & IEEE80211_FCTL_STYPE)
2129#define WLAN_FC_MORE_DATA(fc) (le16_to_cpu(fc) & IEEE80211_FCTL_MOREDATA)
0c817338
LF		 2130#define SEQ_TO_SN(seq) (((seq) & IEEE80211_SCTL_SEQ) >> 4)
2131#define SN_TO_SEQ(ssn) (((ssn) << 4) & IEEE80211_SCTL_SEQ)
2132#define MAX_SN ((IEEE80211_SCTL_SEQ) >> 4)
2133
2134#define RT_RF_OFF_LEVL_ASPM BIT(0) /*PCI ASPM */
2135#define RT_RF_OFF_LEVL_CLK_REQ BIT(1) /*PCI clock request */
2136#define RT_RF_OFF_LEVL_PCI_D3 BIT(2) /*PCI D3 mode */
2137/*NIC halt, re-initialize hw parameters*/
2138#define RT_RF_OFF_LEVL_HALT_NIC BIT(3)
2139#define RT_RF_OFF_LEVL_FREE_FW BIT(4) /*FW free, re-download the FW */
2140#define RT_RF_OFF_LEVL_FW_32K BIT(5) /*FW in 32k */
2141/*Always enable ASPM and Clock Req in initialization.*/
2142#define RT_RF_PS_LEVEL_ALWAYS_ASPM BIT(6)
e97b775d
LF		 2143/* no matter RFOFF or SLEEP we set PS_ASPM_LEVL*/
2144#define RT_PS_LEVEL_ASPM BIT(7)
0c817338
LF		 2145/*When LPS is on, disable 2R if no packet is received or transmittd.*/
2146#define RT_RF_LPS_DISALBE_2R BIT(30)
2147#define RT_RF_LPS_LEVEL_ASPM BIT(31) /*LPS with ASPM */
2148#define RT_IN_PS_LEVEL(ppsc, _ps_flg) \
2149 ((ppsc->cur_ps_level & _ps_flg) ? true : false)
2150#define RT_CLEAR_PS_LEVEL(ppsc, _ps_flg) \
2151 (ppsc->cur_ps_level &= (~(_ps_flg)))
2152#define RT_SET_PS_LEVEL(ppsc, _ps_flg) \
2153 (ppsc->cur_ps_level |= _ps_flg)
2154
2155#define container_of_dwork_rtl(x, y, z) \
2156 container_of(container_of(x, struct delayed_work, work), y, z)
2157
3dad618b
C		 2158#define FILL_OCTET_STRING(_os, _octet, _len) \
2159 (_os).octet = (u8 *)(_octet); \
2160 (_os).length = (_len);
2161
2162#define CP_MACADDR(des, src) \
2163 ((des)[0] = (src)[0], (des)[1] = (src)[1],\
2164 (des)[2] = (src)[2], (des)[3] = (src)[3],\
2165 (des)[4] = (src)[4], (des)[5] = (src)[5])
2166
0c817338
LF		 2167static inline u8 rtl_read_byte(struct rtl_priv *rtlpriv, u32 addr)
2168{
2169 return rtlpriv->io.read8_sync(rtlpriv, addr);
2170}
2171
2172static inline u16 rtl_read_word(struct rtl_priv *rtlpriv, u32 addr)
2173{
2174 return rtlpriv->io.read16_sync(rtlpriv, addr);
2175}
2176
2177static inline u32 rtl_read_dword(struct rtl_priv *rtlpriv, u32 addr)
2178{
2179 return rtlpriv->io.read32_sync(rtlpriv, addr);
2180}
2181
2182static inline void rtl_write_byte(struct rtl_priv *rtlpriv, u32 addr, u8 val8)
2183{
2184 rtlpriv->io.write8_async(rtlpriv, addr, val8);
3dad618b
C		 2185
2186 if (rtlpriv->cfg->write_readback)
2187 rtlpriv->io.read8_sync(rtlpriv, addr);
0c817338
LF		 2188}
2189
2190static inline void rtl_write_word(struct rtl_priv *rtlpriv, u32 addr, u16 val16)
2191{
2192 rtlpriv->io.write16_async(rtlpriv, addr, val16);
3dad618b
C		 2193
2194 if (rtlpriv->cfg->write_readback)
2195 rtlpriv->io.read16_sync(rtlpriv, addr);
0c817338
LF		 2196}
2197
2198static inline void rtl_write_dword(struct rtl_priv *rtlpriv,
2199 u32 addr, u32 val32)
2200{
2201 rtlpriv->io.write32_async(rtlpriv, addr, val32);
3dad618b
C		 2202
2203 if (rtlpriv->cfg->write_readback)
2204 rtlpriv->io.read32_sync(rtlpriv, addr);
0c817338
LF		 2205}
2206
2207static inline u32 rtl_get_bbreg(struct ieee80211_hw *hw,
2208 u32 regaddr, u32 bitmask)
2209{
d6b6fc14
JP		 2210 struct rtl_priv *rtlpriv = hw->priv;
2211
2212 return rtlpriv->cfg->ops->get_bbreg(hw, regaddr, bitmask);
0c817338
LF		 2213}
2214
2215static inline void rtl_set_bbreg(struct ieee80211_hw *hw, u32 regaddr,
2216 u32 bitmask, u32 data)
2217{
d6b6fc14 2218 struct rtl_priv *rtlpriv = hw->priv;
0c817338 2219
d6b6fc14 2220 rtlpriv->cfg->ops->set_bbreg(hw, regaddr, bitmask, data);
0c817338
LF		 2221}
2222
2223static inline u32 rtl_get_rfreg(struct ieee80211_hw *hw,
2224 enum radio_path rfpath, u32 regaddr,
2225 u32 bitmask)
2226{
d6b6fc14
JP		 2227 struct rtl_priv *rtlpriv = hw->priv;
2228
2229 return rtlpriv->cfg->ops->get_rfreg(hw, rfpath, regaddr, bitmask);
0c817338
LF		 2230}
2231
2232static inline void rtl_set_rfreg(struct ieee80211_hw *hw,
2233 enum radio_path rfpath, u32 regaddr,
2234 u32 bitmask, u32 data)
2235{
d6b6fc14
JP		 2236 struct rtl_priv *rtlpriv = hw->priv;
2237
2238 rtlpriv->cfg->ops->set_rfreg(hw, rfpath, regaddr, bitmask, data);
0c817338
LF		 2239}
2240
2241static inline bool is_hal_stop(struct rtl_hal *rtlhal)
2242{
2243 return (_HAL_STATE_STOP == rtlhal->state);
2244}
2245
2246static inline void set_hal_start(struct rtl_hal *rtlhal)
2247{
2248 rtlhal->state = _HAL_STATE_START;
2249}
2250
2251static inline void set_hal_stop(struct rtl_hal *rtlhal)
2252{
2253 rtlhal->state = _HAL_STATE_STOP;
2254}
2255
2256static inline u8 get_rf_type(struct rtl_phy *rtlphy)
2257{
2258 return rtlphy->rf_type;
2259}
2260
3dad618b
C		 2261static inline struct ieee80211_hdr *rtl_get_hdr(struct sk_buff *skb)
2262{
2263 return (struct ieee80211_hdr *)(skb->data);
2264}
2265
d3bb1429 2266static inline __le16 rtl_get_fc(struct sk_buff *skb)
3dad618b 2267{
d3bb1429 2268 return rtl_get_hdr(skb)->frame_control;
3dad618b
C		 2269}
2270
2271static inline u16 rtl_get_tid_h(struct ieee80211_hdr *hdr)
2272{
2273 return (ieee80211_get_qos_ctl(hdr))[0] & IEEE80211_QOS_CTL_TID_MASK;
2274}
2275
2276static inline u16 rtl_get_tid(struct sk_buff *skb)
2277{
2278 return rtl_get_tid_h(rtl_get_hdr(skb));
2279}
2280
2281static inline struct ieee80211_sta *get_sta(struct ieee80211_hw *hw,
2282 struct ieee80211_vif *vif,
7101f404 2283 const u8 *bssid)
3dad618b
C		 2284{
2285 return ieee80211_find_sta(vif, bssid);
2286}
2287
2461c7d6
LF		 2288static inline struct ieee80211_sta *rtl_find_sta(struct ieee80211_hw *hw,
2289 u8 *mac_addr)
2290{
2291 struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
2292 return ieee80211_find_sta(mac->vif, mac_addr);
2293}
2294
0c817338 2295#endif
Linux kernel - Deliverables
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