Commit | Line | Data |
---|---|---|
2f01a1f5 | 1 | /* |
80301cdc | 2 | * This file is part of wl1251 |
2f01a1f5 KV |
3 | * |
4 | * Copyright (c) 1998-2007 Texas Instruments Incorporated | |
5 | * Copyright (C) 2008-2009 Nokia Corporation | |
6 | * | |
2f01a1f5 KV |
7 | * This program is free software; you can redistribute it and/or |
8 | * modify it under the terms of the GNU General Public License | |
9 | * version 2 as published by the Free Software Foundation. | |
10 | * | |
11 | * This program is distributed in the hope that it will be useful, but | |
12 | * WITHOUT ANY WARRANTY; without even the implied warranty of | |
13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU | |
14 | * General Public License for more details. | |
15 | * | |
16 | * You should have received a copy of the GNU General Public License | |
17 | * along with this program; if not, write to the Free Software | |
18 | * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA | |
19 | * 02110-1301 USA | |
20 | * | |
21 | */ | |
22 | ||
80301cdc KV |
23 | #ifndef __WL1251_H__ |
24 | #define __WL1251_H__ | |
2f01a1f5 KV |
25 | |
26 | #include <linux/mutex.h> | |
27 | #include <linux/list.h> | |
28 | #include <linux/bitops.h> | |
29 | #include <net/mac80211.h> | |
30 | ||
80301cdc | 31 | #define DRIVER_NAME "wl1251" |
2f01a1f5 KV |
32 | #define DRIVER_PREFIX DRIVER_NAME ": " |
33 | ||
34 | enum { | |
35 | DEBUG_NONE = 0, | |
36 | DEBUG_IRQ = BIT(0), | |
37 | DEBUG_SPI = BIT(1), | |
38 | DEBUG_BOOT = BIT(2), | |
39 | DEBUG_MAILBOX = BIT(3), | |
40 | DEBUG_NETLINK = BIT(4), | |
41 | DEBUG_EVENT = BIT(5), | |
42 | DEBUG_TX = BIT(6), | |
43 | DEBUG_RX = BIT(7), | |
44 | DEBUG_SCAN = BIT(8), | |
45 | DEBUG_CRYPT = BIT(9), | |
46 | DEBUG_PSM = BIT(10), | |
47 | DEBUG_MAC80211 = BIT(11), | |
48 | DEBUG_CMD = BIT(12), | |
49 | DEBUG_ACX = BIT(13), | |
50 | DEBUG_ALL = ~0, | |
51 | }; | |
52 | ||
53 | #define DEBUG_LEVEL (DEBUG_NONE) | |
54 | ||
55 | #define DEBUG_DUMP_LIMIT 1024 | |
56 | ||
80301cdc | 57 | #define wl1251_error(fmt, arg...) \ |
2f01a1f5 KV |
58 | printk(KERN_ERR DRIVER_PREFIX "ERROR " fmt "\n", ##arg) |
59 | ||
80301cdc | 60 | #define wl1251_warning(fmt, arg...) \ |
2f01a1f5 KV |
61 | printk(KERN_WARNING DRIVER_PREFIX "WARNING " fmt "\n", ##arg) |
62 | ||
80301cdc | 63 | #define wl1251_notice(fmt, arg...) \ |
2f01a1f5 KV |
64 | printk(KERN_INFO DRIVER_PREFIX fmt "\n", ##arg) |
65 | ||
80301cdc | 66 | #define wl1251_info(fmt, arg...) \ |
2f01a1f5 KV |
67 | printk(KERN_DEBUG DRIVER_PREFIX fmt "\n", ##arg) |
68 | ||
80301cdc | 69 | #define wl1251_debug(level, fmt, arg...) \ |
2f01a1f5 KV |
70 | do { \ |
71 | if (level & DEBUG_LEVEL) \ | |
72 | printk(KERN_DEBUG DRIVER_PREFIX fmt "\n", ##arg); \ | |
73 | } while (0) | |
74 | ||
80301cdc | 75 | #define wl1251_dump(level, prefix, buf, len) \ |
2f01a1f5 KV |
76 | do { \ |
77 | if (level & DEBUG_LEVEL) \ | |
78 | print_hex_dump(KERN_DEBUG, DRIVER_PREFIX prefix, \ | |
79 | DUMP_PREFIX_OFFSET, 16, 1, \ | |
80 | buf, \ | |
81 | min_t(size_t, len, DEBUG_DUMP_LIMIT), \ | |
82 | 0); \ | |
83 | } while (0) | |
84 | ||
80301cdc | 85 | #define wl1251_dump_ascii(level, prefix, buf, len) \ |
2f01a1f5 KV |
86 | do { \ |
87 | if (level & DEBUG_LEVEL) \ | |
88 | print_hex_dump(KERN_DEBUG, DRIVER_PREFIX prefix, \ | |
89 | DUMP_PREFIX_OFFSET, 16, 1, \ | |
90 | buf, \ | |
91 | min_t(size_t, len, DEBUG_DUMP_LIMIT), \ | |
92 | true); \ | |
93 | } while (0) | |
94 | ||
80301cdc | 95 | #define WL1251_DEFAULT_RX_CONFIG (CFG_UNI_FILTER_EN | \ |
9ed74ba0 | 96 | CFG_MC_FILTER_EN | \ |
2f01a1f5 KV |
97 | CFG_BSSID_FILTER_EN) |
98 | ||
80301cdc | 99 | #define WL1251_DEFAULT_RX_FILTER (CFG_RX_PRSP_EN | \ |
2f01a1f5 KV |
100 | CFG_RX_MGMT_EN | \ |
101 | CFG_RX_DATA_EN | \ | |
102 | CFG_RX_CTL_EN | \ | |
103 | CFG_RX_BCN_EN | \ | |
104 | CFG_RX_AUTH_EN | \ | |
105 | CFG_RX_ASSOC_EN) | |
106 | ||
80301cdc | 107 | #define WL1251_BUSY_WORD_LEN 8 |
2f01a1f5 KV |
108 | |
109 | struct boot_attr { | |
110 | u32 radio_type; | |
111 | u8 mac_clock; | |
112 | u8 arm_clock; | |
113 | int firmware_debug; | |
114 | u32 minor; | |
115 | u32 major; | |
116 | u32 bugfix; | |
117 | }; | |
118 | ||
80301cdc KV |
119 | enum wl1251_state { |
120 | WL1251_STATE_OFF, | |
121 | WL1251_STATE_ON, | |
122 | WL1251_STATE_PLT, | |
2f01a1f5 KV |
123 | }; |
124 | ||
80301cdc | 125 | enum wl1251_partition_type { |
2f01a1f5 KV |
126 | PART_DOWN, |
127 | PART_WORK, | |
128 | PART_DRPW, | |
129 | ||
130 | PART_TABLE_LEN | |
131 | }; | |
132 | ||
a0bbb58b JN |
133 | enum wl1251_station_mode { |
134 | STATION_ACTIVE_MODE, | |
135 | STATION_POWER_SAVE_MODE, | |
1e5f52de | 136 | STATION_IDLE, |
a0bbb58b JN |
137 | }; |
138 | ||
80301cdc | 139 | struct wl1251_partition { |
2f01a1f5 KV |
140 | u32 size; |
141 | u32 start; | |
142 | }; | |
143 | ||
80301cdc KV |
144 | struct wl1251_partition_set { |
145 | struct wl1251_partition mem; | |
146 | struct wl1251_partition reg; | |
2f01a1f5 KV |
147 | }; |
148 | ||
80301cdc | 149 | struct wl1251; |
2f01a1f5 | 150 | |
80301cdc | 151 | struct wl1251_stats { |
2f01a1f5 KV |
152 | struct acx_statistics *fw_stats; |
153 | unsigned long fw_stats_update; | |
154 | ||
155 | unsigned int retry_count; | |
156 | unsigned int excessive_retries; | |
157 | }; | |
158 | ||
80301cdc | 159 | struct wl1251_debugfs { |
2f01a1f5 KV |
160 | struct dentry *rootdir; |
161 | struct dentry *fw_statistics; | |
162 | ||
163 | struct dentry *tx_internal_desc_overflow; | |
164 | ||
165 | struct dentry *rx_out_of_mem; | |
166 | struct dentry *rx_hdr_overflow; | |
167 | struct dentry *rx_hw_stuck; | |
168 | struct dentry *rx_dropped; | |
169 | struct dentry *rx_fcs_err; | |
170 | struct dentry *rx_xfr_hint_trig; | |
171 | struct dentry *rx_path_reset; | |
172 | struct dentry *rx_reset_counter; | |
173 | ||
174 | struct dentry *dma_rx_requested; | |
175 | struct dentry *dma_rx_errors; | |
176 | struct dentry *dma_tx_requested; | |
177 | struct dentry *dma_tx_errors; | |
178 | ||
179 | struct dentry *isr_cmd_cmplt; | |
180 | struct dentry *isr_fiqs; | |
181 | struct dentry *isr_rx_headers; | |
182 | struct dentry *isr_rx_mem_overflow; | |
183 | struct dentry *isr_rx_rdys; | |
184 | struct dentry *isr_irqs; | |
185 | struct dentry *isr_tx_procs; | |
186 | struct dentry *isr_decrypt_done; | |
187 | struct dentry *isr_dma0_done; | |
188 | struct dentry *isr_dma1_done; | |
189 | struct dentry *isr_tx_exch_complete; | |
190 | struct dentry *isr_commands; | |
191 | struct dentry *isr_rx_procs; | |
192 | struct dentry *isr_hw_pm_mode_changes; | |
193 | struct dentry *isr_host_acknowledges; | |
194 | struct dentry *isr_pci_pm; | |
195 | struct dentry *isr_wakeups; | |
196 | struct dentry *isr_low_rssi; | |
197 | ||
198 | struct dentry *wep_addr_key_count; | |
199 | struct dentry *wep_default_key_count; | |
200 | /* skipping wep.reserved */ | |
201 | struct dentry *wep_key_not_found; | |
202 | struct dentry *wep_decrypt_fail; | |
203 | struct dentry *wep_packets; | |
204 | struct dentry *wep_interrupt; | |
205 | ||
206 | struct dentry *pwr_ps_enter; | |
207 | struct dentry *pwr_elp_enter; | |
208 | struct dentry *pwr_missing_bcns; | |
209 | struct dentry *pwr_wake_on_host; | |
210 | struct dentry *pwr_wake_on_timer_exp; | |
211 | struct dentry *pwr_tx_with_ps; | |
212 | struct dentry *pwr_tx_without_ps; | |
213 | struct dentry *pwr_rcvd_beacons; | |
214 | struct dentry *pwr_power_save_off; | |
215 | struct dentry *pwr_enable_ps; | |
216 | struct dentry *pwr_disable_ps; | |
217 | struct dentry *pwr_fix_tsf_ps; | |
218 | /* skipping cont_miss_bcns_spread for now */ | |
219 | struct dentry *pwr_rcvd_awake_beacons; | |
220 | ||
221 | struct dentry *mic_rx_pkts; | |
222 | struct dentry *mic_calc_failure; | |
223 | ||
224 | struct dentry *aes_encrypt_fail; | |
225 | struct dentry *aes_decrypt_fail; | |
226 | struct dentry *aes_encrypt_packets; | |
227 | struct dentry *aes_decrypt_packets; | |
228 | struct dentry *aes_encrypt_interrupt; | |
229 | struct dentry *aes_decrypt_interrupt; | |
230 | ||
231 | struct dentry *event_heart_beat; | |
232 | struct dentry *event_calibration; | |
233 | struct dentry *event_rx_mismatch; | |
234 | struct dentry *event_rx_mem_empty; | |
235 | struct dentry *event_rx_pool; | |
236 | struct dentry *event_oom_late; | |
237 | struct dentry *event_phy_transmit_error; | |
238 | struct dentry *event_tx_stuck; | |
239 | ||
240 | struct dentry *ps_pspoll_timeouts; | |
241 | struct dentry *ps_upsd_timeouts; | |
242 | struct dentry *ps_upsd_max_sptime; | |
243 | struct dentry *ps_upsd_max_apturn; | |
244 | struct dentry *ps_pspoll_max_apturn; | |
245 | struct dentry *ps_pspoll_utilization; | |
246 | struct dentry *ps_upsd_utilization; | |
247 | ||
248 | struct dentry *rxpipe_rx_prep_beacon_drop; | |
249 | struct dentry *rxpipe_descr_host_int_trig_rx_data; | |
250 | struct dentry *rxpipe_beacon_buffer_thres_host_int_trig_rx_data; | |
251 | struct dentry *rxpipe_missed_beacon_host_int_trig_rx_data; | |
252 | struct dentry *rxpipe_tx_xfr_host_int_trig_rx_data; | |
253 | ||
254 | struct dentry *tx_queue_len; | |
b7339b1d | 255 | struct dentry *tx_queue_status; |
2f01a1f5 KV |
256 | |
257 | struct dentry *retry_count; | |
258 | struct dentry *excessive_retries; | |
259 | }; | |
260 | ||
08d9f572 BC |
261 | struct wl1251_if_operations { |
262 | void (*read)(struct wl1251 *wl, int addr, void *buf, size_t len); | |
263 | void (*write)(struct wl1251 *wl, int addr, void *buf, size_t len); | |
3f9e750d GI |
264 | void (*read_elp)(struct wl1251 *wl, int addr, u32 *val); |
265 | void (*write_elp)(struct wl1251 *wl, int addr, u32 val); | |
cb7bbc7a | 266 | int (*power)(struct wl1251 *wl, bool enable); |
08d9f572 | 267 | void (*reset)(struct wl1251 *wl); |
b5ed9c1b BC |
268 | void (*enable_irq)(struct wl1251 *wl); |
269 | void (*disable_irq)(struct wl1251 *wl); | |
08d9f572 BC |
270 | }; |
271 | ||
80301cdc | 272 | struct wl1251 { |
2f01a1f5 KV |
273 | struct ieee80211_hw *hw; |
274 | bool mac80211_registered; | |
275 | ||
af8c78eb | 276 | void *if_priv; |
8e639c06 | 277 | const struct wl1251_if_operations *if_ops; |
2f01a1f5 | 278 | |
1d207cd3 | 279 | int power_gpio; |
2f01a1f5 | 280 | int irq; |
c95cf3d0 | 281 | bool use_eeprom; |
2f01a1f5 | 282 | |
e4c2e09e SR |
283 | struct regulator *vio; |
284 | ||
9df86e2e DGC |
285 | spinlock_t wl_lock; |
286 | ||
80301cdc | 287 | enum wl1251_state state; |
2f01a1f5 KV |
288 | struct mutex mutex; |
289 | ||
290 | int physical_mem_addr; | |
291 | int physical_reg_addr; | |
292 | int virtual_mem_addr; | |
293 | int virtual_reg_addr; | |
294 | ||
2f01a1f5 KV |
295 | int cmd_box_addr; |
296 | int event_box_addr; | |
297 | struct boot_attr boot_attr; | |
298 | ||
299 | u8 *fw; | |
300 | size_t fw_len; | |
301 | u8 *nvs; | |
302 | size_t nvs_len; | |
303 | ||
304 | u8 bssid[ETH_ALEN]; | |
305 | u8 mac_addr[ETH_ALEN]; | |
306 | u8 bss_type; | |
307 | u8 listen_int; | |
308 | int channel; | |
4d09b537 | 309 | bool monitor_present; |
c8909e5a | 310 | bool joined; |
2f01a1f5 KV |
311 | |
312 | void *target_mem_map; | |
313 | struct acx_data_path_params_resp *data_path; | |
314 | ||
315 | /* Number of TX packets transferred to the FW, modulo 16 */ | |
316 | u32 data_in_count; | |
317 | ||
318 | /* Frames scheduled for transmission, not handled yet */ | |
319 | struct sk_buff_head tx_queue; | |
320 | bool tx_queue_stopped; | |
321 | ||
322 | struct work_struct tx_work; | |
2f01a1f5 KV |
323 | |
324 | /* Pending TX frames */ | |
325 | struct sk_buff *tx_frames[16]; | |
326 | ||
327 | /* | |
328 | * Index pointing to the next TX complete entry | |
329 | * in the cyclic XT complete array we get from | |
330 | * the FW. | |
331 | */ | |
332 | u32 next_tx_complete; | |
333 | ||
334 | /* FW Rx counter */ | |
335 | u32 rx_counter; | |
336 | ||
337 | /* Rx frames handled */ | |
338 | u32 rx_handled; | |
339 | ||
340 | /* Current double buffer */ | |
341 | u32 rx_current_buffer; | |
342 | u32 rx_last_id; | |
343 | ||
344 | /* The target interrupt mask */ | |
345 | u32 intr_mask; | |
346 | struct work_struct irq_work; | |
347 | ||
348 | /* The mbox event mask */ | |
349 | u32 event_mask; | |
350 | ||
351 | /* Mailbox pointers */ | |
352 | u32 mbox_ptr[2]; | |
353 | ||
354 | /* Are we currently scanning */ | |
355 | bool scanning; | |
356 | ||
2f01a1f5 KV |
357 | /* Default key (for WEP) */ |
358 | u32 default_key; | |
359 | ||
360 | unsigned int tx_mgmt_frm_rate; | |
361 | unsigned int tx_mgmt_frm_mod; | |
362 | ||
363 | unsigned int rx_config; | |
364 | unsigned int rx_filter; | |
365 | ||
366 | /* is firmware in elp mode */ | |
367 | bool elp; | |
368 | ||
d5da79ac JO |
369 | struct delayed_work elp_work; |
370 | ||
a0bbb58b | 371 | enum wl1251_station_mode station_mode; |
2f01a1f5 KV |
372 | |
373 | /* PSM mode requested */ | |
374 | bool psm_requested; | |
375 | ||
f7ad1eed DG |
376 | /* retry counter for PSM entries */ |
377 | u8 psm_entry_retry; | |
378 | ||
e2fd4611 KV |
379 | u16 beacon_int; |
380 | u8 dtim_period; | |
381 | ||
2f01a1f5 KV |
382 | /* in dBm */ |
383 | int power_level; | |
384 | ||
8964e492 DG |
385 | int rssi_thold; |
386 | ||
80301cdc KV |
387 | struct wl1251_stats stats; |
388 | struct wl1251_debugfs debugfs; | |
1d3b8130 | 389 | |
ac9e2d9a | 390 | __le32 buffer_32; |
56343a3c | 391 | u32 buffer_cmd; |
80301cdc KV |
392 | u8 buffer_busyword[WL1251_BUSY_WORD_LEN]; |
393 | struct wl1251_rx_descriptor *rx_descriptor; | |
0e71bb08 | 394 | |
287f6f96 JO |
395 | struct ieee80211_vif *vif; |
396 | ||
0e71bb08 KV |
397 | u32 chip_id; |
398 | char fw_ver[21]; | |
19434148 JL |
399 | |
400 | /* Most recently reported noise in dBm */ | |
401 | s8 noise; | |
2f01a1f5 KV |
402 | }; |
403 | ||
80301cdc KV |
404 | int wl1251_plt_start(struct wl1251 *wl); |
405 | int wl1251_plt_stop(struct wl1251 *wl); | |
2f01a1f5 | 406 | |
8e639c06 BC |
407 | struct ieee80211_hw *wl1251_alloc_hw(void); |
408 | int wl1251_free_hw(struct wl1251 *wl); | |
409 | int wl1251_init_ieee80211(struct wl1251 *wl); | |
b5ed9c1b BC |
410 | void wl1251_enable_interrupts(struct wl1251 *wl); |
411 | void wl1251_disable_interrupts(struct wl1251 *wl); | |
8e639c06 | 412 | |
2f01a1f5 KV |
413 | #define DEFAULT_HW_GEN_MODULATION_TYPE CCK_LONG /* Long Preamble */ |
414 | #define DEFAULT_HW_GEN_TX_RATE RATE_2MBPS | |
415 | #define JOIN_TIMEOUT 5000 /* 5000 milliseconds to join */ | |
416 | ||
80301cdc | 417 | #define WL1251_DEFAULT_POWER_LEVEL 20 |
2f01a1f5 | 418 | |
9df86e2e DGC |
419 | #define WL1251_TX_QUEUE_LOW_WATERMARK 10 |
420 | #define WL1251_TX_QUEUE_HIGH_WATERMARK 25 | |
2f01a1f5 | 421 | |
e2fd4611 KV |
422 | #define WL1251_DEFAULT_BEACON_INT 100 |
423 | #define WL1251_DEFAULT_DTIM_PERIOD 1 | |
424 | ||
9780279c KV |
425 | #define WL1251_DEFAULT_CHANNEL 0 |
426 | ||
c3e334d2 DG |
427 | #define WL1251_DEFAULT_BET_CONSECUTIVE 10 |
428 | ||
2f01a1f5 KV |
429 | #define CHIP_ID_1251_PG10 (0x7010101) |
430 | #define CHIP_ID_1251_PG11 (0x7020101) | |
431 | #define CHIP_ID_1251_PG12 (0x7030101) | |
432 | #define CHIP_ID_1271_PG10 (0x4030101) | |
27797d68 | 433 | #define CHIP_ID_1271_PG20 (0x4030111) |
2f01a1f5 | 434 | |
9f55c620 FB |
435 | #define WL1251_FW_NAME "ti-connectivity/wl1251-fw.bin" |
436 | #define WL1251_NVS_NAME "ti-connectivity/wl1251-nvs.bin" | |
0e71bb08 | 437 | |
e8a8b252 | 438 | #define WL1251_POWER_ON_SLEEP 10 /* in milliseconds */ |
0e71bb08 KV |
439 | |
440 | #define WL1251_PART_DOWN_MEM_START 0x0 | |
441 | #define WL1251_PART_DOWN_MEM_SIZE 0x16800 | |
442 | #define WL1251_PART_DOWN_REG_START REGISTERS_BASE | |
443 | #define WL1251_PART_DOWN_REG_SIZE REGISTERS_DOWN_SIZE | |
444 | ||
445 | #define WL1251_PART_WORK_MEM_START 0x28000 | |
446 | #define WL1251_PART_WORK_MEM_SIZE 0x14000 | |
447 | #define WL1251_PART_WORK_REG_START REGISTERS_BASE | |
448 | #define WL1251_PART_WORK_REG_SIZE REGISTERS_WORK_SIZE | |
449 | ||
8964e492 DG |
450 | #define WL1251_DEFAULT_LOW_RSSI_WEIGHT 10 |
451 | #define WL1251_DEFAULT_LOW_RSSI_DEPTH 10 | |
452 | ||
2f01a1f5 | 453 | #endif |